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600-V MOSFETs pack fast recovery diode
Two 600-V N-channel super-junction MOSFETs from Alpha & Omega incorporate a body diode for robustness and fast reverse recovery. Based on the company’s aMOS5 technology, the AOK095A60FD (TO-247) and AOTF125A60FDL (TO-220F) provide an on-resistance of 95 mΩ and 125 mΩ, respectively.
The power MOSFETs are optimized to meet the high-efficiency needs of DC/DC converters (LLC, PSFB, TTF) and solar inverters. aMOS5 FETs are engineered with a strong intrinsic body diode to handle hard commutation scenarios. This proves useful during abnormal conditions such as short circuits or start-up transients, where the freewheeling body diode operates in reverse recovery mode.
In tests conducted by Alpha & Omega engineers, the body diodes of the AOK095A60FD and AOTF125A60FDL survived high di/dt under abnormal system conditions, even at elevated junction temperatures of up to 150°C. Tests also showed that the devices’ turn-off energy is noticeably lower than competing devices, which contributes to higher efficiency under light or mid-load conditions.
Both parts are available now in production quantities, with a lead time of 16 weeks. The AOK095A60FD and AOTF125A60FDL cost $3.75 and $3.22 each, respectively, in lots of 1000 units.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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IoT connectivity module is Matter-enabled
Simplifying device interoperability, Murata’s Type 2FR tri-radio connectivity module supports Matter over Wi-Fi, Matter over Thread, and Matter over Ethernet. The module integrates NXP Semiconductors’ RW612 wireless MCU in a 12×11-mm package that is approximately 50% smaller than a discrete implementation.
Well-suited for smart home devices and appliances, as well as industrial automation and smart city applications, the Type 2FR supports various communication protocols. These include dual-band 2.4 GHz/5 GHz Wi-Fi 6, Bluetooth Low Energy 5.3, IEEE 802.15.4 for low-rate wireless networks, and Ethernet.
Along with a 260-MHz Arm Cortex-M33 core, 1.2 MB of RAM, and 16 MB of flash memory, the module features NXP EdgeLock security technology. EdgeLock offers secure boot, debug, and firmware updates, as well as hardware cryptography. Additionally, NXP MCUXpresso software tools help speed development and reduce time-to-market.
Murata will showcase the Type 2FR tri-radio module at next week’s CES 2024 trade show. Samples will be available at the same time. A datasheet was not available at the time of this announcement.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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Neuromorphic processor pairs with Microchip MPU
BrainChip will demonstrate its Akida neuromorphic processor enabled by Microchip’s embedded 32-bit processor boards at next week’s CES 2024 trade show. The company will display the ability of Akida, running on Microchip’s SAMx71 Ultra and SAMA7G54-EK boards, to perform always-on machine learning tasks, such as keyword spotting and visual wake words.
Keyword spotting leverages neural networks to recognize keywords, like “Hey Siri.” Visual wake word detection classifies the presence of individuals in images for such applications as in-home security and smart doorbells.
“We look forward to demonstrating the potential and ease of integrating Akida for always-on machine learning applications on embedded devices at CES,” said Rob Telson, VP of Ecosystem and Partnerships at BrainChip. “By combining our innovative neuromorphic processor and models with Microchip’s high-performance MPUs and boards, you can deliver compelling solutions to the market to serve the rapidly growing demand for TinyML at the edge.”
Rod Drake, corporate VP of Microchip’s MPU32 and MCU32 business units, added, “In this collaborative showcase with BrainChip, we will illustrate how our customers can leverage the advantages of next-generation AI to enable low-power, high-performance machine learning applications on our embedded platforms.”
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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Choosing the Best Wide Bandgap Technology for Your Application
FBH appoints new scientific managing director
Gated 555 astable hits the ground running
The classic and versatile 555 finds its way into many low to moderate frequency oscillator applications. Some of these require the ability to selectively gate oscillation on and off on demand and the 555’s RESET pin can conveniently be used for this purpose as shown in Figure 1.
Figure 1 Typical gated (via RESET pin) 555 astable multivibrator.
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When asserted (logic level zero), RESET holds the output low and the frequency-setting RC in a known and accurately repeatable (discharged) state. But there’s a “gotcha” that occurs when RESET is returned to logic 1 and oscillation resumes. The problem is illustrated in Figure 2.
Figure 2 Excessively long first pulse occurs on oscillation restart due to C1 complete discharge.
The first pulse generated on restart is significantly longer than those that occur later. This is because during the oscillation-off interval, timing capacitor C1 is allowed to discharge completely to 0 V. This differs from the 1/3V+ “trigger” level that applies during steady-stage oscillation and results in a much longer ramp interval, which is problematic in some applications.
Happily, there’s a simple fix, illustrated in Figure 3.
Figure 3 Added timing capacitor C2 immediately precharges C1 to V+/3 trigger level when RESET returns high normalizing the duration of the first oscillation cycle.
The original C1 timing capacitance is divided into two series/parallel connected capacitors, so that the new C1 = 2/3 of the original, and C2 = 1/3. The new oscillation start-up sequence is shown in Figure 4, note the slew to 1/3V+ on oscillation startup.
Figure 4 C2 charge injection on oscillation startup equalizes pulse length.
For this scheme to work accurately, the source of RESET must provide a full 0 to V+ step and present a low impedance compatible with generation of the timing ramp when at V+. If such a signal source doesn’t already exist, a buffer such as illustrated in Figure 5 may be necessary. A typical buffer choice would be something comparable to a 74HC04.
Figure 5 A buffer may be necessary to provide a full voltage excursion RESET signal.
Oscillator design equations are unchanged from the usual 555 datasheet math, except that the timing capacitance used should be the sum C1 + C2.
Fosc = 1.44/((2R1 + R2)(C1 + C2))
Also necessary is that RESET be asserted and oscillation paused for a minimum of several R1(C1 + C2) time-constants (e.g., 5 or 6) between gates so that discharge of the timing capacitor will be accurately complete.
Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.
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