* Library of National Semiconductor Op Amp Models * $Revision: 1.14 $ * $Author: rperez $ * $Date: 02 Oct 1998 09:40:58 $ * ***************************************************************************** * * 18 APRIL 1996 * (c) National Semiconductor, Inc., 1994 * This diskette and all of its contents is under copyright by * National Semiconductor, Inc. * This is version 4.30 * The disk contains 152 files, including VERSION.TXT and consumes * 1,252,199 bytes. * /// End of VERSION.TXT /// * *////////////////////////////////////////////////////////////////////// * (C) National Semiconductor, Inc. * Models developed and under copyright by: * National Semiconductor, Inc. *///////////////////////////////////////////////////////////////////// * Legal Notice: This material is intended for free software support. * The file may be copied, and distributed; however, reselling the * material is illegal *//////////////////////////////////////////////////////////////////// * For ordering or technical information on these models, contact: * National Semiconductor's Customer Response Center * 7:00 A.M.--7:00 P.M. U.S. Central Time * (800) 272-9959 * For Applications support, contact the Internet address: * amps-apps@galaxy.nsc.com */////////////////////////////////////////////////////////////////// * * NATIONAL SEMICONDUCTOR CORPORATION * 2900 Semiconductor Drive * Santa Clara, California 95052 * * AMPLIFIER PRODUCTS * Applications Engineering * * SPICE OP-AMP MACROMODELS, Version 4.30 * 18 APRIL 1996 ************************************************************************ * Revision History: * 4.30 16-APR-96 D. SMITH Models added:LM6172. * Models modified for VOS limit:LMC6482A, * LMC6484A,LMC6492A,LMC6492B,LMC6494A, * LMC6494B. * Models removed:LMC6482,LMC6484,LMC6492, * LMC6494,LF400,LM607,LM627,LM637,LM6685 * 4.20 06-Nov-95 D. Smith Models added:LM6310,LM6311,LM6317 * 4.10 03-Oct-95 D. Stolitzka No models added * 4.00 18-Jul-95 D. Stolitzka LMC6762A/B, LMC6772A/B * 3.30 08-Feb-95 D. Stolitzka Models added:LM111,LMC7211A/B * 3.20 16-Sep-94 D. Stolitzka Models added:LM6685, begin history * 2.61 15-Mar-93 D. Stolitzka/HG Corrected multipole interaction * 3.00 06-Dec-93 D. Stolitzka/HG Models added:LM4250C,LMC6001/A * 2.60 4-Mar-93 D. Stolitzka/HG Models added:LF441/A, LF442/A, LF444/A, * LM13600/13700,LMC and LPC,New Header * 2.59 15-Feb-93 D. Stolitzka Corrected RIN for gm=1E12. * 2.50 06-Mar-92 D. Hindi Models added, begin history. ************************************************************************* * For further information on the models or products, contact National * Semiconductor's Customer Response Center: * 7:00 A.M.--7:00 P.M. U.S. Central Time * (800) 272-9959 * *********************************************************************** * Below is a table of the devices included in this revision: * * Sub-circuit name Filename Devices modeled * ------------------------------------------------------ * LM111/NS LM111.MOD LM111 * LM118/NS LM118.MOD LM118 * LM124/NS LM124.MOD LM124 * LF155/NS LF155.MOD LF155 * LF156/NS LF156.MOD LF156 * LF157/NS LF157.MOD LF157 * LM158/NS LM158.MOD LM158 * LM218/NS LM218.MOD LM218 * LM224/NS LM224.MOD LM224 * LF255/NS LF255.MOD LF255 * LF256/NS LF256.MOD LF256 * LF257/NS LF257.MOD LF257 * LM258/NS LM258.MOD LM258 * LM318/NS LM318.MOD LM318 * LM324/NS LM324.MOD LM324 * LF351/NS LF351.MOD LF351 * LF353/NS LF353.MOD LF353 * LF355/NS LF355.MOD LF355 * LF356/NS LF356.MOD LF356 * LF357/NS LF357.MOD LF357 * LM358/NS LM358.MOD LM358 * LM359/NS LM359.MOD LM359 * LF411/NS LF411.MOD LF411 * LF412/NS LF412.MOD LF412 * LF441B/NS LF441B.MOD LF441 * LF441A/NS LF441A.MOD LF441A * LF442B/NS LF442B.MOD LF442 * LF442A/NS LF442A.MOD LF442A * LF444B/NS LF444B.MOD LF444 * LF444A/NS LF444A.MOD LF444A * LF451/NS LF451.MOD LF451 * LF453/NS LF453.MOD LF453 * LM6132A/NS LM6132A.MOD LM6132A * LM6132B/NS LM6132B.MOD LM6132B * LM6152A/NS LM6152A.MOD LM6152A * LM6152B/NS LM6152B.MOD LM6152B * LM7171A/NS LM7171A.MOD LM7171A * LM7171B/NS LM7171B.MOD LM7171B * LM7121/NS LM7121.MOD LM7121 * LM6171A/NS LM6171A.MOD LM6171A * LM6171B/NS LM6171B.MOD LM6171B * LM6172/NS LM6172.MOD LM6172 * LM6310/NS LM6310.MOD LM6310 * LM6311/NS LM6311.MOD LM6311 * LM6317/NS LM6317.MOD LM6317 * LMC660B/NS LMC660B.MOD LMC660 * LMC660A/NS LMC660A.MOD LMC660A * LPC660B/NS LPC660B.MOD LPC660B * LPC660A/NS LPC660A.MOD LPC660A * LPC661B/NS LPC661B.MOD LPC661B * LPC661A/NS LPC661A.MOD LMC661A * LMC662B/NS LMC662B.MOD LMC662 * LMC662A/NS LMC662A.MOD LMC662A * LPC662B/NS LPC662B.MOD LPC662B * LPC662A/NS LPC662A.MOD LPC662A * LM741/NS LM741.MOD LM741 * LM2902/NS LM2902.MOD LM2902 * LM2904/NS LM2904.MOD LM2904 * LM4250/NS LM4250.MOD LM4250 * LMC6001B/NS LMC6001B.MOD LMC6001B * LMC6001A/NS LMC6001A.MOD LMC6001A * LMC6022/NS LMC6022.MOD LMC6022 * LMC6024/NS LMC6024.MOD LMC6024 * LMC6032/NS LMC6032.MOD LMC6032 * LMC6034/NS LMC6034.MOD LMC6034 * LMC6041B/NS LMC6041B.MOD LMC6041 * LMC6041A/NS LMC6041A.MOD LMC6041A * LMC6042B/NS LMC6042B.MOD LMC6042 * LMC6042A/NS LMC6042A.MOD LMC6042A * LMC6044B/NS LMC6044B.MOD LMC6044 * LMC6044A/NS LMC6044A.MOD LMC6044A * LMC6061B/NS LMC6061B.MOD LMC6061 * LMC6061A/NS LMC6061A.MOD LMC6061A * LMC6062B/NS LMC6062B.MOD LMC6062 * LMC6062A/NS LMC6062A.MOD LMC6062A * LMC6064B/NS LMC6064B.MOD LMC6064 * LMC6064A/NS LMC6064A.MOD LMC6064A * LMC6081B/NS LMC6081B.MOD LMC6081 * LMC6081A/NS LMC6081A.MOD LMC6081A * LMC6082B/NS LMC6082B.MOD LMC6082 * LMC6082A/NS LMC6082A.MOD LMC6082A * LMC6084B/NS LMC6084B.MOD LMC6084 * LMC6084A/NS LMC6084A.MOD LMC6084A * LMC6462A/NS LMC6462A.MOD LMC6462A * LMC6462B/NS LMC6462B.MOD LMC6462B * LMC6464A/NS LMC6464A.MOD LMC6464A * LMC6464B/NS LMC6464B.MOD LMC6464B * LMC6482A/NS LMC6482A.MOD LMC6482A * LMC6484A/NS LMC6484A.MOD LMC6484A * LMC6492A/NS LMC6492A.MOD LMC6492A * LMC6492B/NS LMC6492B.MOD LMC6492B * LMC6494A/NS LMC6494A.MOD LMC6494A * LMC6494B/NS LMC6494B.MOD LMC6494B * LMC6572A/NS LMC6572A.MOD LMC6572A * LMC6572B/NS LMC6572B.MOD LMC6572B * LMC6574A/NS LMC6574A.MOD LMC6574A * LMC6574B/NS LMC6574B.MOD LMC6574B * LMC6582A/NS LMC6582A.MOD LMC6582A * LMC6582B/NS LMC6582B.MOD LMC6582B * LMC6584A/NS LMC6584A.MOD LMC6584A * LMC6584B/NS LMC6584B.MOD LMC6584B * LMC6681A/NS LMC6681A.MOD LMC6681A * LMC6681B/NS LMC6681B.MOD LMC6681B * LMC6682A/NS LMC6682A.MOD LMC6682A * LMC6682B/NS LMC6682B.MOD LMC6682A * LMC6684A/NS LMC6684A.MOD LMC6684A * LMC6684B/NS LMC6684B.MOD LMC6684B * LMC6762A/NS LMC6762A.MOD LMC6762A * LMC6762B/NS LMC6762B.MOD LMC6762B * LMC6772A/NS LMC6772A.MOD LMC6772A * LMC6772B/NS LMC6772B.MOD LMC6772B * LMC7101A/NS LMC7101A.MOD LMC7101A * LMC7101B/NS LMC7101B.MOD LMC7101B * LMC7111A/NS LMC7111A.MOD LMC7111A * LMC7111B/NS LMC7111B.MOD LMC7111B * LMC7211A/NS LMC7211A.MOD LMC7211A * LMC7211B/NS LMC7211B.MOD LMC7211B * LMC7221A/NS LMC7221A.MOD LMC7221A * LMC7221B/NS LMC7221B.MOD LMC7221B * LM6118/NS LM6118.MOD LM6118 * LM6121/NS LM6121.MOD LM6121,LM6221,LM6321 * LM6142A/NS LM6142A.MOD LM6142A * LM6142B/NS LM6142B.MOD LM6142B * LM6161/NS LM6161.MOD LM6161 * LM6162/NS LM6162.MOD LM6162 * LM6164/NS LM6164.MOD LM6164 * LM6165/NS LM6165.MOD LM6165 * LM6181/NS LM6181.MOD LM6181 * LM6218/NS LM6218.MOD LM6218 * LM6261/NS LM6261.MOD LM6261 * LM6262/NS LM6262.MOD LM6262 * LM6264/NS LM6264.MOD LM6264 * LM6265/NS LM6265.MOD LM6265 * LM6361/NS LM6361.MOD LM6361 * LM6362/NS LM6362.MOD LM6362 * LM6364/NS LM6364.MOD LM6364 * LM6365/NS LM6365.MOD LM6365 * LM7131A/NS LM7131A.MOD LM7131A * LM7131B/NS LM7131B.MOD LM7131B * LM13600/NS LM13600.MOD LM13600 * LM13700/NS LM13700.MOD LM13700 * * --------------------- ADDON * LF155 * LF156 * LF157 * LF255 * LF256 * LF257 * LF351 * LF353 * LF355 * LF356 * LF357 * LF400 * LF411 * LF412 * LF451 * LF453 * LMC660 * LPC660 * LMC662 * LPC662 * LMC6041 * LM118 * LM124 * LM218 * LM224 * LM318 * LM324 * LM358 * LM607 * LM627 * LM637 * LM741 * LM2902 * LM2904 * LM6118 * LM6161 * LM6162 * LM6164 * LM6165 * LM6218 * LM6261 * LM6262 * LM6264 * LM6265 * LM6361 * LM6362 * LM6364 * LM6365 * * * * * * * * * The connections shown below apply for all macro-model subcircuits except the * LMC668X family, the LM359,LM6310,LM6311, and LM6317. The LMC668X family of * macromodels has one extra pin for the power-down option. Please refer to * the LM359 macromodel for the macromodel pinouts. * * sub-circuit command * | device name * | | non-inverting input * | | | inverting input * | | | | positive power supply * | | | | | negative power supply * | | | | | | output * | | | | | | | * | | | | | | | * .SUBCKT LXXXX/NS 1 2 99 50 28 * * The models were designed to provide a valuable tool for designers * which closely mimic the response of the real device while providing * a significant increase in simulation speed over a discrete model. * Here is a list of the parameters modeled and not modeled. * * Modeled * ----------------------------------------- * Non-linear input transfer characteristics * Input resistance * Input offset voltage * Input offset current * Input bias current * Open loop gain * Gain-Bandwidth product * Poles and zeros in the frequency response * Frequency dependent CMMR * Slew rate * Maximum output voltage swing * Output short circuit current * Output impedance * Quiescent and dynamic supply current * * Not modeled as part of this release * ------------------------------------------ * Asymmetrical slew rates * Power supply rejection ratio * Noise * Temperature effects * * /// END OF README.TXT FILE /// * * 18 APRIL 1996 * National Semiconductor Corporation * Amplifier Products SPICE Macromodels * * What's New in Version 4.30 * * Organization and Useful Information: * * Revision history appears in the readme file header. * * All models exist as seperate files with the extention .MOD and may * be downloaded seperately. Filename Example: LM6172.MOD * * IMPORTANT USER INFORMATION! Please READ the following: * * SET this option, * * GMIN=1E-16 * * when using models from the NSC CMOS amplifiers. These devices have * input bias currents that are 1000x smaller than the default node leakage * resistance (GMIN=1E-12) used in most SPICE simulators. * * * New macromodels of amplifier products: * LM6172 Dual High Speed, Low Power, Low Distortion, Voltage Feedback Amplifier * * Models modified for VOS limit: * LMC6482A,LMC6484A,LMC6492A,LMC6492B,LMC6494A,LMC6494B. * * Models removed:LMC6482,LMC6484,LMC6492,LMC6494,LF400,LM607,LM627,LM637,LM6685. * * * (*1 Represents a model contained in our last library that has new, * significant improvements.) * * // end-of-file: WHATSNEW.TXT // *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * *////////////////////////////////////////////////////////// *LF155 Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF155/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV *NOTE:Asymetrical slew rate not modeled. *Use default gm=1e12 ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 9.6796E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=23.7 HZ C3 98 11 67.154P *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 25 V5 28 25 -.1V D4 25 9 DX V4 24 28 -.1V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *$ *////////////////////////////////////////////////////////// *LF156 Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF156/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.5944E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=31.96 HZ C3 98 11 49.9798P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 20 V5 28 25 -.25 D4 25 9 DX V4 24 28 -.25 D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF157 Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF157/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 8.1291E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=224 HZ C3 98 11 7.10513P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 25 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF255 Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF255/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV *NOTE:Asymetrical slew rate not modeled. * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 9.6796E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=23.7 HZ C3 98 11 67.154P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 25 V5 28 25 -.1V D4 25 9 DX V4 24 28 -.1V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF256 Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF256/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.5944E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=31.96 HZ C3 98 11 49.9798P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 20 V5 28 25 -.25V D4 25 9 DX V4 24 28 -.25V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF257 Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF257/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 8.1291E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=224 HZ C3 98 11 7.10513P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 25 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF351 Wide Bandwidth JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF351/NS 1 2 99 50 28 * *Features: *Low supply current = 1.8mA *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.7MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 5E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF353 Wide Bandwidth Dual JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF353/NS 1 2 99 50 28 * *Features: *Low supply current = 1.8mA *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.7MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 5E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// *////////////////////////////////////////////////////////// *LF355 Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF355/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV *NOTE:Asymetrical slew rate not modeled. * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 9.6796E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=23.7 HZ C3 98 11 67.154P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 25 V5 28 25 -.1V D4 25 9 DX V4 24 28 -.1V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF356 Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF356/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.5944E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=31.96 HZ C3 98 11 49.9798P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 9 1 VA8 26 27 0 R16 27 28 20 V5 28 25 -.25V D4 25 9 DX V4 24 28 -.25V D3 9 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF357 Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF357/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 8.1291E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=224 HZ C3 98 11 7.10513P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 25 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// *////////////////////////////////////////////////////////// *LF411 LOW OFFSET, LOW DRIFT JFET INPUT OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF411/NS 1 2 99 50 28 * *Features: *Fast settling time (.01%) = 2uS *High bandwidth = 3MHz *High slew rate = 10V/uS *Low offset voltage = .5mV *Low supply current = 1.8mA * ****************INPUT STAGE************** * IOS 2 1 25.0P *^Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 1E12 R2 3 2 1E12 I1 99 4 1.0M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 650 R4 6 50 650 *Fp2=28 MHZ C4 5 6 4.372P * ***********COMMON MODE EFFECT*********** * I2 99 50 800UA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 .8E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 *Fp1=18 HZ C3 98 11 857.516P * ***************POLE STAGE*************** * *Fp=30 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 5.305E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 144.7M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 50 V5 28 25 0.646V D4 25 15 DX V4 24 28 0.646V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. *////////////////////////////////////////////////////////// *LF412 LOW OFFSET, LOW DRIFT DUAL JFET INPUT OP-AMP MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF412/NS 1 2 99 50 28 * *Features: *Fast settling time (.01%) = 2uS *High bandwidth = 3MHz *High slew rate = 10V/uS *Low offset voltage = 1mV *Low supply current = 1.8mA *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25.0P *^Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 1E12 R2 3 2 1E12 I1 99 4 1.0M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 650 R4 6 50 650 *Fp2=28 MHZ C4 5 6 4.372P * ***********COMMON MODE EFFECT*********** * I2 99 50 800UA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 1E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 *Fp1=18 HZ C3 98 11 857.516P * ***************POLE STAGE*************** * *Fp=30 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 5.305E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 144.7M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 50 V5 28 25 0.646V D4 25 15 DX V4 24 28 0.646V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// * ///////////////////////////////////////////////////////////// * LF441A Low Offset, Low Power JFET Input Operational Amplifier * ///////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LF441A/NS 1 2 99 50 28 * * Features: * Low input bias current = 10pA * High bandwidth = 1MHz * High slew rate = 1V/uS * Low offset voltage (max) = 0.5mV * Low supply current = 150uA * ****************INPUT STAGE************** * * Input offset current IOS 2 1 2.5P CI1 1 50 2.5P CI2 2 50 2.5P R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U IB1 4 7 48P IB2 4 2 48P J1 5 2 4 JX J2 6 7 4 JX R3 5 50 3.956K R4 6 50 3.956K * Fp2=5.02 MHZ C4 31 6 7P R20 31 5 1500 * Fz1=15.1 MHZ * ***********COMMON MODE EFFECT*********** * * Supply current I2 99 50 44UA * Input offset voltage| EOS 7 1 POLY(1) 16 49 5E-4 1 R8 99 49 1.25E6 R9 49 50 1.25E6 * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 D7 22 99 DX D8 50 22 DX * **************SECOND STAGE************** * * Level shifter EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 2E6 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 * Fp1=11.5 HZ C3 98 11 1385P * ***************POLE STAGE*************** * * Fp3=159 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 POLY(2) 1 49 2 49 0 0.5E-8 0.5E-8 L2 98 17 5.1 R13 17 16 1K * **************OUTPUT STAGE************** * * Supply current correction F6 50 99 POLY(1) V6 30U 1 E1 99 23 99 15 1 * Output resistance R16 24 23 675 D5 26 24 DX V6 26 22 0.63V R17 23 25 250 D6 25 27 DX V7 22 27 0.63V V5 22 30 6.35V R19 21 30 1.2E6 D4 21 15 DX V4 29 22 0.63V R18 20 29 24K D3 15 20 DX * Output inductor L3 22 28 1U * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=10E-12 N=3) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// * //////////////////////////////////////////////// * LF441B Low Power JFET Input Operational Amplifier * //////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LF441B/NS 1 2 99 50 28 * * Features: * Low input bias current = 10pA * High bandwidth = 1MHz * High slew rate = 1V/uS * Low offset voltage (max) = 5mV * Low supply current = 150uA * ****************INPUT STAGE************** * * Input offset current IOS 2 1 2.5P CI1 1 50 2.5P CI2 2 50 2.5P R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U IB1 4 7 48P IB2 4 2 48P J1 5 2 4 JX J2 6 7 4 JX R3 5 50 3.956K R4 6 50 3.956K * Fp2=5.02 MHZ C4 31 6 7P R20 31 5 1500 * Fz1=15.1 MHZ * ***********COMMON MODE EFFECT*********** * * Supply current I2 99 50 44UA * Input offset voltage| EOS 7 1 POLY(1) 16 49 5E-3 1 R8 99 49 1.25E6 R9 49 50 1.25E6 * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 D7 22 99 DX D8 50 22 DX * **************SECOND STAGE************** * * Level shifter EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 2E6 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 * Fp1=11.5 HZ C3 98 11 1385P * ***************POLE STAGE*************** * * Fp3=159 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 POLY(2) 1 49 2 49 0 0.5E-8 0.5E-8 L2 98 17 5.1 R13 17 16 1K * **************OUTPUT STAGE************** * * Supply current correction F6 50 99 POLY(1) V6 30U 1 E1 99 23 99 15 1 * Output resistance R16 24 23 675 D5 26 24 DX V6 26 22 0.63V R17 23 25 250 D6 25 27 DX V7 22 27 0.63V V5 22 30 6.35V R19 21 30 1.2E6 D4 21 15 DX V4 29 22 0.63V R18 20 29 24K D3 15 20 DX * Output inductor L3 22 28 1U * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=10E-12 N=3) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// * ////////////////////////////////////////////////////// * LF442A Dual Low Power JFET Input Operational Amplifier * ////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LF442A/NS 1 2 99 50 28 * * Features: * Low input bias current = 10pA * High bandwidth = 1MHz * High slew rate = 1V/uS * Low offset voltage (max) = 1mV * Low supply current = 150uA/Amplifier * * Note: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * * Input offset current IOS 2 1 2.5P CI1 1 50 2.5P CI2 2 50 2.5P R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U IB1 4 7 48P IB2 4 2 48P J1 5 2 4 JX J2 6 7 4 JX R3 5 50 3.956K R4 6 50 3.956K * Fp2=5.02 MHZ C4 31 6 7P R20 31 5 1500 * Fz1=15.1 MHZ * ***********COMMON MODE EFFECT*********** * * Supply current I2 99 50 44UA * Input offset voltage| EOS 7 1 POLY(1) 16 49 1E-3 1 R8 99 49 1.25E6 R9 49 50 1.25E6 * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 D7 22 99 DX D8 50 22 DX * **************SECOND STAGE************** * * Level shifter EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 2E6 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 * Fp1=11.5 HZ C3 98 11 1385P * ***************POLE STAGE*************** * * Fp3=159 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 POLY(2) 1 49 2 49 0 0.5E-8 0.5E-8 L2 98 17 5.1 R13 17 16 1K * **************OUTPUT STAGE************** * * Supply current correction F6 50 99 POLY(1) V6 30U 1 E1 99 23 99 15 1 * Output resistance R16 24 23 675 D5 26 24 DX V6 26 22 0.63V R17 23 25 250 D6 25 27 DX V7 22 27 0.63V V5 22 30 6.35V R19 21 30 1.2E6 D4 21 15 DX V4 29 22 0.63V R18 20 29 24K D3 15 20 DX * Output inductor L3 22 28 1U * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=10E-12 N=3) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// * ///////////////////////////////////////////////////// * LF442B Dual Low Power JFET Input Operational Amplifier * ///////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LF442B/NS 1 2 99 50 28 * * Features: * Low input bias current = 10pA * High bandwidth = 1MHz * High slew rate = 1V/uS * Low offset voltage (max) = 5mV * Low supply current = 200uA/Amplifier * * Note: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * * Input offset current IOS 2 1 2.5P CI1 1 50 2.5P CI2 2 50 2.5P R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U IB1 4 7 48P IB2 4 2 48P J1 5 2 4 JX J2 6 7 4 JX R3 5 50 3.956K R4 6 50 3.956K * Fp2=5.02 MHZ C4 31 6 7P R20 31 5 1500 * Fz1=15.1 MHZ * ***********COMMON MODE EFFECT*********** * * Supply current I2 99 50 94UA * Input offset voltage| EOS 7 1 POLY(1) 16 49 5E-3 1 R8 99 49 1.25E6 R9 49 50 1.25E6 * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 D7 22 99 DX D8 50 22 DX * **************SECOND STAGE************** * * Level shifter EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 2E6 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 * Fp1=11.5 HZ C3 98 11 1385P * ***************POLE STAGE*************** * * Fp3=159 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 POLY(2) 1 49 2 49 0 0.5E-8 0.5E-8 L2 98 17 5.1 R13 17 16 1K * **************OUTPUT STAGE************** * * Supply current correction F6 50 99 POLY(1) V6 30U 1 E1 99 23 99 15 1 * Output resistance R16 24 23 675 D5 26 24 DX V6 26 22 0.63V R17 23 25 250 D6 25 27 DX V7 22 27 0.63V V5 22 30 6.35V R19 21 30 1.2E6 D4 21 15 DX V4 29 22 0.63V R18 20 29 24K D3 15 20 DX * Output inductor L3 22 28 1U * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=10E-12 N=3) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// * ////////////////////////////////////////////////////// * LF444A Quad Low Power JFET Input Operational Amplifier * ////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LF444A/NS 1 2 99 50 28 * * Features: * Low input bias current = 10pA * High bandwidth = 1MHz * High slew rate = 1V/uS * Low offset voltage (max) = 5mV * Low supply current = 150uA/Amplifier * * Note: Model is for single device only and simulated * supply current is 1/4 of total device current. * ****************INPUT STAGE************** * * Input offset current IOS 2 1 2.5P CI1 1 50 2.5P CI2 2 50 2.5P R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U IB1 4 7 48P IB2 4 2 48P J1 5 2 4 JX J2 6 7 4 JX R3 5 50 3.956K R4 6 50 3.956K * Fp2=5.02 MHZ C4 31 6 7P R20 31 5 1500 * Fz1=15.1 MHZ * ***********COMMON MODE EFFECT*********** * * Supply current I2 99 50 44UA * input offset voltage| EOS 7 1 POLY(1) 16 49 5E-3 1 R8 99 49 1.25E6 R9 49 50 1.25E6 * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 D7 22 99 DX D8 50 22 DX * **************SECOND STAGE************** * * Level shifter EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 2E6 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 * Fp1=11.5 HZ C3 98 11 1385P * ***************POLE STAGE*************** * * Fp3=159 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 POLY(2) 1 49 2 49 0 0.5E-8 0.5E-8 L2 98 17 5.1 R13 17 16 1K * **************OUTPUT STAGE************** * * Supply current correction F6 50 99 POLY(1) V6 30U 1 E1 99 23 99 15 1 * Output resistance R16 24 23 675 D5 26 24 DX V6 26 22 0.63V R17 23 25 187 D6 25 27 DX V7 22 27 0.63V V5 22 30 6.35V R19 21 30 1.2E6 D4 21 15 DX V4 29 22 0.63V R18 20 29 24K D3 15 20 DX * Output inductor L3 22 28 1U * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=10E-12 N=3) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// * ///////////////////////////////////////////////////// * LF444B Quad Low Power JFET Input Operational Amplifier * ///////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LF444B/NS 1 2 99 50 28 * * Features: * Low input bias current = 10pA * High bandwidth = 1MHz * High slew rate = 1V/uS * Low offset voltage (max) = 10mV * Low supply current = 200uA/Amplifier * * Note: Model is for single device only and simulated * supply current is 1/4 of total device current. * ****************INPUT STAGE************** * * Input offset current IOS 2 1 2.5P CI1 1 50 2.5P CI2 2 50 2.5P R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U IB1 4 7 48P IB2 4 2 48P J1 5 2 4 JX J2 6 7 4 JX R3 5 50 3.956K R4 6 50 3.956K * Fp2=5.02 MHZ C4 31 6 7P R20 31 5 1500 * Fz1=15.1 MHZ * ***********COMMON MODE EFFECT*********** * * Supply current I2 99 50 94UA * input offset voltage| EOS 7 1 POLY(1) 16 49 1E-2 1 R8 99 49 1.25E6 R9 49 50 1.25E6 * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 D7 22 99 DX D8 50 22 DX * **************SECOND STAGE************** * * Level shifter EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 2E6 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 * Fp1=11.5 HZ C3 98 11 1385P * ***************POLE STAGE*************** * * Fp3=159 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 POLY(2) 1 49 2 49 0 0.5E-8 0.5E-8 L2 98 17 5.1 R13 17 16 1K * **************OUTPUT STAGE************** * * Supply current correction F6 50 99 POLY(1) V6 30U 1 E1 99 23 99 15 1 * Output resistance R16 24 23 675 D5 26 24 DX V6 26 22 0.63V R17 23 25 187 D6 25 27 DX V7 22 27 0.63V V5 22 30 6.35V R19 21 30 1.2E6 D4 21 15 DX V4 29 22 0.63V R18 20 29 24K D3 15 20 DX * Output inductor L3 22 28 1U * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=10E-12 N=3) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// *////////////////////////////////////////////////////////// *LF451 Wide-Bandwidth JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF451/NS 1 2 99 50 28 * *Features: *Low supply current = 3.4mA(max) *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 2.1MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 .3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes: * * 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is * modeled by assuming the option GMIN=1TOhm. If a different (non- * default) GMIN value is needed, users may recalculate as follows: * Rin=(R1||GMIN+R2||GMIN), where R1=R2, * to maintain a consistent Rin model. * /////////////////////////////////////////////////////////////////// *////////////////////////////////////////////////////////// *LF453 Wide-Bandwidth Dual JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF453/NS 1 2 99 50 28 * *Features: *Low supply current = 6.5mA(max) *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 5mV(max) *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25P *^Input offset current R1 1 3 1E12 R2 3 2 1E12 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 2.1MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 .3E-3 1 *Input offset voltage.^ R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 23 VA8 1 D5 21 23 DX VA7 99 21 0 D6 23 99 DX E1 99 26 99 15 1 VA8 26 27 0 R16 27 28 35 V5 28 25 0.1V D4 25 15 DX V4 24 28 0.1V D3 15 24 DX * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12) * .ENDS *$ * ///////////////////////////////////////// * LM111 Voltage Comparator * ///////////////////////////////////////// * * Connections: * Positive Input * | Negative Input * | | Output * | | | Positive power supply * | | | | Negative Power supply * | | | | | Ground or Emitter Output * | | | | | | .SUBCKT LM111/NS 3 2 1 8 4 104 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single 5V supply * Very Low Input current * Very Low Power Consumption * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * *----- input stage ----- vos 2 13 dc 0.0007 iee 8 10 dc 1e-4 rc_q1 11 4 1517.2 rc_q2 12 4 1517.2 re_q1 10 6 1000 re_q2 10 7 1000 q1 11 3 6 mq1 q2 12 13 7 mq2 *----- supply current ----- gsup 8 4 33 4 1 rsup 8 45 33333.3 dsup 45 4 mds iis 4 33 dc 0.00395 ris 33 4 1 TC=-0.00379747, -3.55271e-20 *----- delay vs. overdrive ----- g1 4 25 12 11 10 rcl 25 4 10 dcl1 25 26 md0 dcl2 27 25 md0 vcl1 26 4 dc 9.4 vcl2 4 27 dc 9.4 g2 4 16 25 4 0.01 d3 16 18 md1 d4 17 16 md1 v1 18 4 dc 0 v2 4 17 dc 0 *----- inter stage ----- gb 4 20 12 11 100 rb 20 4 10 h1 22 4 poly(1) v1 0 1089.83 -4491.35 h2 4 21 poly(1) v2 0 1089.83 -4491.35 db1 20 22 mdb1 db2 21 20 mdb1 gt 4 30 20 4 1e-5 rt 30 4 100k ct 30 4 0.8116e-12 gc 4 35 30 4 0.003448 rc 35 4 1k *----- output satge ----- go 104 40 35 4 -0.01 ro 104 40 10 eob 41 40 45 4 1 rr 1 104 1meg co 40 104 10p voe 42 104 dc -0.0477 qo 1 41 42 mqo .model mq1 pnp bf=805.452 xtb=1.1526 .model mq2 pnp bf=861.069 xtb=1.1526 .model md0 d is=1e-10 rs=0.01 .model md1 d is=1e-12 .model mdb1 d .model mds d is=1e-16 .model mqo npn bf=100 rc=13.4286 isc=1.8e-10 + br=10 nr=0.95 cjs=5p cjc=1p tf=2n .ENDS *$ *////////////////////////////////////////////////////////// *LM118 OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM118/NS 1 2 99 50 28 * *Features: *Internal frequency compensation *High bandwidth = 15MHz *Minimum slew rate = 50V/uS *Low bias current = 250nA *Wide supply range = +-5V to +-20V * ****************INPUT STAGE************** * IOS 2 1 6N *^Input offset current R1 1 3 1.5MEG R2 3 2 1.5MEG I1 4 50 100U R3 99 5 517 R4 99 6 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=25 MHz C4 5 6 6.1569P * ***********COMMON MODE EFFECT*********** * I2 99 50 4.9M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 4E-3 1 *Input offset voltage.^ R8 99 49 80.2K R9 49 50 80.2K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 3.0967E-4 0 596.674E-3 *Fp1=115 Hz R5 98 9 9.6877G C3 98 9 1.4286P * ************POLE/ZERO STAGE************* * *Fp=300 KHz, Fz=600 KHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 1MEG C6 14 13 2.6526E-13 * ***************POLE STAGE*************** * *Fp=55 MHz G3 98 15 13 49 1E-6 R12 98 15 1MEG C5 98 15 2.8937E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 1E-8 L2 98 17 53.1M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 E1 99 23 99 15 1 R16 24 23 30 D5 26 24 DX V6 26 22 .63V R17 23 25 30 D6 25 27 DX V7 22 27 .63V C9 23 22 100P V5 22 21 0.2V D4 21 15 DX V4 20 22 0.2V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=333.333) * .ENDS *$ *////////////////////////////////////////////////////////// *LM124 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM124/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 3N *^Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U *^Quiescent supply current EOS 7 1 POLY(1) 16 49 1E-3 1 *Input offset voltage.^ R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 0.635 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 E1 99 23 99 15 1 R16 24 23 17.5 D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *$ * \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ * LM13600 Dual Operational Transconductance Amplifier * \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ * * Amplifier Bias Input * | Diode Bias * | | Positive Input * | | | Negative Input * | | | | Output * | | | | | Negative power supply * | | | | | | Buffer Input * | | | | | | | Buffer Output * | | | | | | | | Positive power supply * | | | | | | | | | .SUBCKT LM13600/NS 1 2 3 4 5 6 7 8 11 * * Features: * gm adjustable over 6 decades. * Excellent gm linearity. * Linearizing diodes. * Controlled impedance buffers. * Wide supply range of +/-2V to +/-22V. * * Note: This model is single-pole in nature and over-estimates * AC bandwidth and phase margin (stability) by over 2X. * Although refinement may be possible in the future, please * use benchtesting to finalize AC circuit design. * * Note: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************************************************** * C1 6 4 4.8P C2 3 6 4.8P * Output capacitor C3 5 6 6.26P D1 2 4 DX D2 2 3 DX D3 11 21 DX D4 21 22 DX D5 1 26 DX D6 26 27 DX D7 5 29 DX D8 28 5 DX D10 31 25 DX * Clamp for -CMR D11 28 25 DX * Ios source F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9 F2 11 5 V2 1.022 F3 25 6 V3 1.0 F4 5 6 V1 1.022 F5 30 6 V3 1.0 * Output impedance F6 5 0 POLY(2) V3 V7 0 0 0 0 1 G1 0 33 5 0 .55E-3 I1 11 6 300U Q1 24 32 31 QX1 Q2 23 3 31 QX2 Q3 11 7 30 QX1 Q4 11 30 8 QY V1 22 24 0V V2 22 23 0V V3 27 6 0V V4 11 29 1.4 V5 28 6 1.2 V6 4 32 0V V7 33 0 0V .MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2) .MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2) .MODEL QY NPN (IS=6E-15 BF=140) .MODEL DX D (IS=5E-16) .ENDS *$ * \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ * LM13700 Dual Operational Transconductance Amplifier * \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ * * Amplifier Bias Input * | Diode Bias * | | Positive Input * | | | Negative Input * | | | | Output * | | | | | Negative power supply * | | | | | | Buffer Input * | | | | | | | Buffer Output * | | | | | | | | Positive power supply * | | | | | | | | | .SUBCKT LM13700/NS 1 2 3 4 5 6 7 8 11 * * Features: * gm adjustable over 6 decades. * Excellent gm linearity. * Linearizing diodes. * Wide supply range of +/-2V to +/-22V. * * Note: This model is single-pole in nature and over-estimates * AC bandwidth and phase margin (stability) by over 2X. * Although refinement may be possible in the future, please * use benchtesting to finalize AC circuit design. * * Note: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************************************************** * C1 6 4 4.8P C2 3 6 4.8P * Output capacitor C3 5 6 6.26P D1 2 4 DX D2 2 3 DX D3 11 21 DX D4 21 22 DX D5 1 26 DX D6 26 27 DX D7 5 29 DX D8 28 5 DX D10 31 25 DX * Clamp for -CMR D11 28 25 DX * Ios source F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9 F2 11 5 V2 1.022 F3 25 6 V3 1.0 F4 5 6 V1 1.022 * Output impedance F5 5 0 POLY(2) V3 V7 0 0 0 0 1 G1 0 33 5 0 .55E-3 I1 11 6 300U Q1 24 32 31 QX1 Q2 23 3 31 QX2 Q3 11 7 30 QZ Q4 11 30 8 QY V1 22 24 0V V2 22 23 0V V3 27 6 0V V4 11 29 1.4 V5 28 6 1.2 V6 4 32 0V V7 33 0 0V .MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2) .MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2) .MODEL QY NPN (IS=6E-15 BF=50) .MODEL QZ NPN (IS=5E-16 BF=266) .MODEL DX D (IS=5E-16) .ENDS *$ *////////////////////////////////////////////////////////// *LM158 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM158/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N *^Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 .635 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 E1 99 23 99 15 1 R16 24 23 17.5 D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM218 OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM218/NS 1 2 99 50 28 * *Features: *Internal frequency compensation *High bandwidth = 15MHz *Minimum slew rate = 50V/uS *Low bias current = 250nA *Wide supply range = +-5V to +-20V * ****************INPUT STAGE************** * IOS 2 1 6N *^Input offset current R1 1 3 1.5MEG R2 3 2 1.5MEG I1 4 50 100U R3 99 5 517 R4 99 6 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=25 MHz C4 5 6 6.1569P * ***********COMMON MODE EFFECT*********** * I2 99 50 4.9M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 4E-3 1 *Input offset voltage.^ R8 99 49 80.2K R9 49 50 80.2K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 3.0967E-4 0 596.674E-3 *Fp1=115 Hz R5 98 9 9.6877G C3 98 9 1.4286P * ************POLE/ZERO STAGE************* * *Fp=300 KHz, Fz=600 KHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 1MEG C6 14 13 2.6526E-13 * ***************POLE STAGE*************** * *Fp=55 MHz G3 98 15 13 49 1E-6 R12 98 15 1MEG C5 98 15 2.8937E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 1E-8 L2 98 17 53.1M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 E1 99 23 99 15 1 R16 24 23 30 D5 26 24 DX V6 26 22 .63V R17 23 25 30 D6 25 27 DX V7 22 27 .63V C9 23 22 100P V5 22 21 0.2V D4 21 15 DX V4 20 22 0.2V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=333.333) * .ENDS *$ *////////////////////////////////////////////////////////// *LM224 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM224/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 3N *^Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 .635 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 E1 99 23 99 15 1 R16 24 23 17.5 D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM258 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM258/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N *^Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 .635 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 E1 99 23 99 15 1 R16 24 23 17.5 D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM2902 QUAD OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM2902/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N *^Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 .635 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 E1 99 23 99 15 1 R16 24 23 17.5 D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM2904 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM2904/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N *^Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 .635 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 E1 99 23 99 15 1 R16 24 23 17.5 D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM318 OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM318/NS 1 2 99 50 28 * *Features: *Internal frequency compensation *High bandwidth = 15MHz *Minimum slew rate = 50V/uS *Low bias current = 250nA *Wide supply range = +-5V to +-20V * ****************INPUT STAGE************** * IOS 2 1 30N *^Input offset current R1 1 3 1.5MEG R2 3 2 1.5MEG I1 4 50 100U R3 99 5 517 R4 99 6 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=25 MHz C4 5 6 6.1569P * ***********COMMON MODE EFFECT*********** * I2 99 50 4.9M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 4E-3 1 *Input offset voltage.^ R8 99 49 80.2K R9 49 50 80.2K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 3.0967E-4 0 596.674E-3 *Fp1=115 Hz R5 98 9 9.6877G C3 98 9 1.4286P * ************POLE/ZERO STAGE************* * *Fp=300 KHz, Fz=600 KHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 1MEG C6 14 13 2.6526E-13 * ***************POLE STAGE*************** * *Fp=55 MHz G3 98 15 13 49 1E-6 R12 98 15 1MEG C5 98 15 2.8937E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 1E-8 L2 98 17 53.1M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 E1 99 23 99 15 1 R16 24 23 30 D5 26 24 DX V6 26 22 .63V R17 23 25 30 D6 25 27 DX V7 22 27 .63V C9 23 22 100P V5 22 21 0.2V D4 21 15 DX V4 20 22 0.2V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=333.333) * .ENDS *$ *////////////////////////////////////////////////////////// *LM324 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM324/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N *^Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 .635 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 E1 99 23 99 15 1 R16 24 23 17.5 D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM358 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM358/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N *^Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 .635 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 E1 99 23 99 15 1 R16 24 23 17.5 D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM359 DUAL HIGH-SPEED CURRENT MODE OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * Connections: I_IN(+) * | COMMON * | | I_IN(-) * | | | Output * | | | | VCC * | | | | | Comp. * | | | | | | ISET(out) * | | | | | | | ISET(in) * | | | | | | | | .SUBCKT LM359/NS 1 2 3 4 5 6 7 8 Q1 1 1 2 QINMOD Q2 3 1 2 QINMOD Q3 6 3 2 QINMOD Q4 6 41 5 QPMOD RL1 5 6 120K FA1 41 5 VSNS2 2e-2 CMP1 6 2 13e-12 EA1 35 39 6 2 1.0 R_XT 35 19 1e4 RSER 19 36 100 C_XT 36 2 3e-13 Q5 5 19 11 QOUT1 Q6 5 11 12 QBG 10 RSC 12 4 10 Q15 4 18 2 QBG 10 FB1 2 18 VSNS1 0.09 Q18 6 24 2 QINMOD RQ18 24 25 100 EQ18 25 2 12 4 1.7 EPSR2 39 2 47 2 1.0 EPSR1 46 2 5 2 1.0 CBG 46 47 1e-3 RBG 47 2 10K DO1 5 13 DMOD1 VSNS1 13 14 DC 0 RSET1 14 7 500 DO2 16 2 DMOD1 VSNS2 15 16 DC 0 RSET2 8 15 500 RPWR 5 2 3.3K .MODEL DMOD1 D .MODEL QPMOD PNP (BF=100) .MODEL QINMOD NPN (BF=100 RE=5 RC=100) .MODEL QOUT1 NPN (BF=100 RC=50) .MODEL QBG NPN (BF=100 RC=10) .ENDS *$ * ////////////////////////////////////////// * LM4250 Programmable Operational Amplifier * ////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | Quiescent Current Set * | | | | | | .SUBCKT LM4250/NS 3 2 6 4 7 8 * * Features: * +/-1V to +/-18V power supply operation * Input offset current (Iset=1uA) = 3nA * Low offset voltage (typ) = 2mV * Slew rate = .2V/uS * Gain-bandwidth product = 230kHz * Max supply current (Iset=10uA) = 100uA * Short circuit protected * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * * Input capacitors. CI1 3 4 2P CI2 2 4 2P * Primary pole=939.2mHz. C3 98 20 169.3N * Secondary pole=276kHz. C4 13 14 75.3P C6 4 9 3P * Third pole=795kHz. C7 98 19 200E-15 D1 10 8 DX D2 7 6 DX D3 4 7 DX D4 4 26 DX D5 26 7 DX D6 20 24 DX D7 25 20 DX D8 22 0 DX D9 0 21 DX D10 7 27 DX D11 27 6 DX * Determines dc CMRR. ECMRR 1 3 16 49 1.0 EH 97 98 6 49 1.0 EN 0 96 0 4 1.0 EP 97 0 6 0 1.0 E1 97 18 6 19 1.0 F1 6 0 VA2 1 F2 0 4 VA3 1 F3 23 0 VA1 1 F4 6 9 V1 1.0 F5 6 4 POLY(2) V1 V5 0 8.0 0 0 1 * Sets -Isc F6 4 26 POLY(1) VA1 -1E-2 -1 * Sets +Isc F7 27 6 POLY(1) VA1 -1.2E-2 1 G1 98 20 14 13 1.0 G2 98 19 20 49 1U G4 98 16 POLY(2) 3 49 2 49 0 1.581E-7 1.581E-7 G5 15 4 6 4 0.0333 * CMRR zero. L2 16 17 73.1M * IS of QX1/QX2 and R1/R2 determines Vos. Q1 13 1 11 QX1 Q2 14 2 12 QX2 R1 9 11 9.6K R2 9 12 10K R3 14 4 3.83K R4 13 4 3.83K R5 98 20 1E6 R8 6 49 1E8 R9 49 4 1E8 R12 98 19 1E6 R13 98 17 1K * Output resistance. R22 28 7 581 VA1 18 28 0V VA2 21 23 0V VA3 23 22 0V V1 6 10 0V V2 97 24 1.5V V3 25 96 1.5V V5 4 15 0V .MODEL QX1 PNP (IS=4.625E-16 BF=270 VAF=60 IKF=1E-3 NE=1.15 ISE=.63E-16) .MODEL QX2 PNP (IS=5E-16 BF=300 VAF=60 IKF=1E-3 NE=1.15 ISE=.63E-16) .MODEL DX D(IS=5E-15) .ENDS *$ *////////////////////////////////////////////////////////// *LM6118 Fast Settling Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6118/NS 1 2 99 50 28 * *Features: *Low offset voltage = .2mV *High bandwidth = 17MHz *Slew rate (Av=-1) = 140V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 20N *^Input offset current CI1 1 0 2.5P CI2 2 0 2.5P R1 1 3 3.125G R2 3 2 3.125G I1 99 4 40U R43 45 4 1.25K R44 46 4 1.25K Q1 5 2 45 QX Q2 6 7 46 QX R3 50 5 2.54K R4 50 6 2.54K *Fp2=30 MHz C4 5 6 1.0433P * ***********COMMON MODE EFFECT*********** * I2 99 50 2.71M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 .2E-3 1 *Input offset voltage.^ R8 99 49 71.4K R9 49 50 71.4K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 5E-3 0 5.056 *Fp1=38.24 Hz R5 98 9 100MEG C3 98 9 41.62P * ***************POLE STAGE*************** * *Fp=110 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.4469E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=6 KHz G4 98 16 3 49 1E-8 L2 98 17 26.526M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 E1 99 23 99 15 1 R16 24 23 10 D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 .001U V7 22 27 .63V V5 22 21 .63V D4 21 15 DX V4 20 22 .63V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25) .MODEL QX PNP(BF=100) * .ENDS *$ * ////////////////////////////////////// * LM6121/LM6221/LM6321 High Speed Buffer * ////////////////////////////////////// * * Connections: Input * | Positive power supply * | | Output * | | | Negative power supply * | | | | .SUBCKT LM6121/NS 2 6 7 8 * * Features: * +5V to +/-18V power supply operation * Input current = 1uA * Low offset voltage = 15mV * High Slew rate = 800V/uS * Wide bandwidth = 50MHz * Peak output current = 350mA * Short circuit and thermal limiting * * SPECIAL NOTE ABOUT CONVERGENCE * This circuit, although otherwise simple makes some demands upon a good * circuit simulator so that gain accuracy and AC specs are not compromised. * This model shows good convergence using PSPICE ver. 5.01 or later products. * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * - Temperature effects are not modeled. * - Add 'NOREUSE' to the .OPTIONS statement when * .STEP or .MC statements are used in the simulation. * - The effect of AC coupled loads on slew rate and bandwidth * is not modeled. Model parameters default to a 1K ohm load. * * Input capacitor. CIN 2 0 3.5P * Primary internal pole capacitor. C1 16 0 381P * Secondary internal pole capacitor. C2 24 27 1.723P C3 24 0 .5743P * Filter for load resistor sensor. C4 28 0 10P D1 16 19 DX D2 20 31 DX D3 16 20 DX D4 17 16 DX D5 18 16 DX D6 32 18 DX D7 0 33 DX D8 34 0 DX D9 8 7 DX D10 8 36 DX D11 36 7 DX D12 7 37 DX D13 37 6 DX D14 7 6 DX * E1, E2, E4 adjust gain for delta Vs. E1 25 0 POLY(1) 6 8 .9326 2.25E-3 E2 12 0 POLY(1) 6 8 3.516E-1 5.39E-2 -1.692E-3 2.065E-5 E3 21 0 POLY(1) 28 0 9.1839E-1 2.5364E-4 -2.0965E-7 5.7624E-11 E4 23 0 POLY(2) 24 0 25 0 0 0 0 0 1 E5 31 0 6 0 1.0 E6 0 32 0 8 1.0 * F1, F2 adjust slew rate for load and Vs. F1 20 31 POLY(2) VC VSR 0 1 -472M F2 32 18 POLY(2) VC VSR 0 -1 -472M F3 0 13 POLY(1) VL 1E-9 0 1 * F4 senses load current. F4 0 30 POLY(2) VS VR 0 0 0 0 1 * F5, F6, F7 simulate load current from +/-Vs. F5 6 0 VSP 1.0 F6 0 8 VSN 1.0 F7 35 0 POLY(2) VL VRI 0 1 -1 * F8, F9 determines Isc. F8 8 36 POLY(2) VL VRI -350M -1 1 F9 37 6 POLY(2) VL VRI -350M 1 -1 * G1 adjusts internal gain. G1 11 0 POLY(3) 10 24 12 0 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.1 G2 26 0 POLY(1) 28 0 6.6474E-1 1.1761E-3 -1.2316E-6 4.407E-10 G3 24 0 16 0 1M G4 13 0 POLY(1) 13 0 0 0 1 G5 15 0 POLY(2) 15 0 13 0 0 0 0 0 1 * G6 senses output voltage. G6 0 14 POLY(1) 7 0 2.5E-6 0 1 G7 14 0 POLY(1) 14 0 0 0 1 G8 15 0 14 0 -1.0 * G9 output proportional to dc load resistor (defalts to 1k with ac load). G9 28 0 15 0 -1U G10 29 0 POLY(1) 6 8 -1.4626E-1 4.2552E-2 4.0888E-5 -6.2241E-6 * Load capacitor sensor. H1 27 0 POLY(2) VL VRI 0 -15 15 * Input bias current. IB 2 8 1U * Supply current. IQ 6 8 12.65MA * Input resistance. RIN 10 0 5E6 R1 11 0 1K R2 12 0 1E6 R3 25 0 1E6 R4 13 0 1T R5 15 0 1T R6 21 0 1E6 R7 6 8 11.2K R8 24 0 1K * Output resistor. R9 23 22 4.7 R10 27 0 1E6 R11 14 0 1T R13 28 0 1E6 R14 7 38 1K VC 11 16 0V VL 22 7 0V * Input offset voltage. VOS 2 10 15M VR 0 26 0V VRI 38 0 0V VS 0 29 0V VSN 35 34 0V VSP 33 35 0V VSR 30 0 0V V1 31 19 2.135V V2 17 32 2.135V .MODEL DX D(IS=5E-14 TT=1E-10 CJO=1E-12) .ENDS *$ *////////////////////////////////////////////////////////// *LM6132A OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LM6132A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Offset voltage (max) = 6mV * Input current = 170nA * Slew rate = 27V/uS * Gain-bandwidth product = 17MHZ * Low supply current = 600uA * * NOTE: - This model is for a single device only and the simulated * supply current is for one op amp only. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * - In the next revision, the following will be modelled * - Voltage dependent (Vin or Vcc) slew rate * - Gain/phase variation vs output Z * CI1 1 50 2P CI2 2 50 2P * * 53Hz pole capacitor C3 98 9 0.15N * C4 6 5 .493P C5 98 15 2F C7 98 11 20F * DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 11 33 DX D12 34 11 DX D14 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 2M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 E2 18 7 32 99 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.5E-9 3.5E-9 I1 99 4 18U I2 99 50 319U * Load dependent pole L1 22 28 300N * * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 18 4 99 MX R3 5 50 1.20K R4 6 50 1.20K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * * -Rout R16 23 24 62 * +Rout R17 23 25 138 * * +Isc slope control R18 20 29 12K * -Isc slope control R19 21 30 12K * R21 98 15 1E6 R22 22 28 900 R23 32 97 100K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.61V V3 10 96 0.61V V4 29 22 .21V V5 22 30 .21V V6 26 22 0.61V V7 22 27 0.61V V8 31 50 4V V9 34 96 .34 V10 97 33 .34 * .MODEL DA D (IS=110E-9) .MODEL DB D (IS=113.4E-9) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-.6 KP=4.2E-4 GAMMA=1.1) .ENDS *$ *////////////////////////////////////////////////////////// *LM6132B OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LM6132B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Offset voltage (max) = 6mV * Input current = 170nA * Slew rate = 27V/uS * Gain-bandwidth product = 10MHZ * Low supply current = 360uA * * NOTE: - This model is for a single device only and the simulated * supply current is for one op amp only. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * - In the next revision, the following will be modelled * - Voltage dependent (Vin or Vcc) slew rate * - Gain/phase variation vs output Z * CI1 1 50 2P CI2 2 50 2P * * 53Hz pole capacitor C3 98 9 0.15N * C4 6 5 .493P C5 98 15 2F C7 98 11 20F * DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 11 33 DX D12 34 11 DX D14 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 6M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 E2 18 7 32 99 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.5E-9 3.5E-9 I1 99 4 18U I2 99 50 319U * Load dependent pole L1 22 28 300N * * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 18 4 99 MX R3 5 50 1.20K R4 6 50 1.20K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * * -Rout R16 23 24 62 * +Rout R17 23 25 138 * * +Isc slope control R18 20 29 12K * -Isc slope control R19 21 30 12K * R21 98 15 1E6 R22 22 28 900 R23 32 97 100K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.61V V3 10 96 0.61V V4 29 22 .21V V5 22 30 .21V V6 26 22 0.61V V7 22 27 0.61V V8 31 50 4V V9 34 96 .34 V10 97 33 .34 * .MODEL DA D (IS=110E-9) .MODEL DB D (IS=113.4E-9) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-.6 KP=4.2E-4 GAMMA=1.1) .ENDS *$ *////////////////////////////////////////////////////////// *LM6142A OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LM6142A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 1mV * Input current = 170nA * Slew rate = 27V/uS * Gain-bandwidth product = 17MHZ * Low supply current = 600uA * * NOTE: - This model is for a single device only and the simulated * supply current is for one op amp only. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * - In the next revision, the following will be modelled * - Voltage dependent (Vin or Vcc) slew rate * - Gain/phase variation vs output Z * CI1 1 50 2P CI2 2 50 2P * * 53Hz pole capacitor C3 98 9 0.30N * C4 6 5 .493P C7 98 11 3.54F * DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 11 33 DX D12 34 11 DX D14 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 1M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 E2 18 7 32 99 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 23U I2 99 50 627U * Load dependent pole L1 22 28 300N * * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 18 4 99 MX R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 10 * +Rout R17 23 25 18 * +Isc slope control R18 20 29 12K * -Isc slope control R19 21 30 12K R21 98 15 1E6 R22 22 28 900 R23 32 97 100K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.625V V3 10 96 0.625V V4 29 22 -.186V V5 22 30 -.186V V6 26 22 0.63V V7 22 27 0.63V V8 31 50 4V V9 34 96 .346 V10 97 33 .346 * .MODEL DA D (IS=170E-9) .MODEL DB D (IS=173E-9) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-.6 KP=4.2E-4 GAMMA=1.1) .ENDS *$ *////////////////////////////////////////////////////////// *LM6142B OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LM6142B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 1mV * Input current = 170nA * Slew rate = 27V/uS * Gain-bandwidth product = 17MHZ * Low supply current = 600uA * * NOTE: - This model is for a single device only and the simulated * supply current is for one op amp only. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * - In the next revision, the following will be modelled * - Voltage dependent (Vin or Vcc) slew rate * - Gain/phase variation vs output Z * CI1 1 50 2P CI2 2 50 2P * * 53Hz pole capacitor C3 98 9 0.30N * C4 6 5 .493P C7 98 11 3.54F * DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 11 33 DX D12 34 11 DX D14 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 2.5M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 E2 18 7 32 99 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 23U I2 99 50 627U * Load dependent pole L1 22 28 300N * * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 18 4 99 MX R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 10 * +Rout R17 23 25 18 * +Isc slope control R18 20 29 12K * -Isc slope control R19 21 30 12K R21 98 15 1E6 R22 22 28 900 R23 32 97 100K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.625V V3 10 96 0.625V V4 29 22 -.186V V5 22 30 -.186V V6 26 22 0.63V V7 22 27 0.63V V8 31 50 4V V9 34 96 .346 V10 97 33 .346 * .MODEL DA D (IS=170E-9) .MODEL DB D (IS=173E-9) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-.6 KP=4.2E-4 GAMMA=1.1) .ENDS *$ *///////////////////////////////////////////////// *LM6152A Operational Amplifier Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6152A/NS 3 2 4 5 6 * *Features *Rail to Rail Output Swing *Greater than Rail to Rail Input CMVR *Low Supply Current * EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.004000e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=4.66e-05) FIN1 18 5 VTEMP 0.97 FIN2 19 5 VTEMP 1.03 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 500000 RD2 19 11 500000 * Diff. Input Resistance RCM 11 10 2.75e+06 * Common Mode Input Resistance FCMR 10 57 VCMX 19.9526 * Low Freq. CMRR FPSR 10 57 VPSX 56.3677 * Low Freq. PSRR RSLOPE 4 5 100000 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.00135 * Quiescent Supply Current ETEMP 27 28 32 33 0.196331 RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.00228762) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.0015) RCM1 39 41 199.526 CCM 41 10 1.59155e-09 * CMRR vs. Freq. RPSR1 44 45 281.838 CPSR 45 10 1.59155e-09 * PSRR vs. Freq. ELIMN 10 52 26 10 99.3 RDM 57 10 1475.22 C2 57 10 8.84306e-13 ECMP 40 97 26 10 0 ECMN 95 50 26 10 0 G2 58 10 57 10 3e-05 R2 58 10 22.5954 GO2 59 10 58 10 214 * Avol and Slew-Rate Settings EPOS 40 74 26 10 0 ENEG 75 50 26 10 0.1 * Output Voltage Swing Settings GSOURCE 74 73 33 34 6.2e-05 GSINK 72 75 33 34 0.000169 * Output Current Settings ROO 81 86 2.5 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .ENDS *$ *///////////////////////////////////////////////// *LM6152B Operational Amplifier Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6152B/NS 3 2 4 5 6 * *Features *Rail to Rail Output Swing *Greater than Rail to Rail Input CMVR *Low Supply Current * EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.010000e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=4e-05) FIN1 18 5 VTEMP 0.97 FIN2 19 5 VTEMP 1.03 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 500000 RD2 19 11 500000 * Diff. Input Resistance RCM 11 10 2.75e+06 * Common Mode Input Resistance FCMR 10 57 VCMX 19.9526 * Low Freq. CMRR FPSR 10 57 VPSX 56.3677 * Low Freq. PSRR RSLOPE 4 5 100000 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.00135 * Quiescent Supply Current ETEMP 27 28 32 33 0.196331 RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.00210981) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.0015) RCM1 39 41 199.526 CCM 41 10 1.59155e-09 * CMRR vs. Freq. RPSR1 44 45 281.838 CPSR 45 10 1.59155e-09 * PSRR vs. Freq. ELIMN 10 52 26 10 99.3 RDM 57 10 1475.22 C2 57 10 8.84306e-13 ECMP 40 97 26 10 0 ECMN 95 50 26 10 0 G2 58 10 57 10 3e-05 R2 58 10 22.5954 GO2 59 10 58 10 214 * Avol and Slew-Rate Settings EPOS 40 74 26 10 0 ENEG 75 50 26 10 0.1 * Output Voltage Swing Settings GSOURCE 74 73 33 34 6.2e-05 GSINK 72 75 33 34 0.000169 * Output Current Settings ROO 81 86 2.5 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .ENDS *$ *////////////////////////////////////////////////////////// *LM6161 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6161/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 50MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 1.5P CI2 2 0 1.5P R1 1 3 162.5K R2 3 2 162.5K I1 4 50 1M R3 99 5 651.7 R4 99 6 651.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 600 R44 46 4 600 *Fp2=200 MHz C4 5 6 6.1054E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 5E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.335 D1 9 8 DX D2 10 9 DX V3 10 50 2.155 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA1 0 0 0 20 G1 98 9 POLY(1) 5 6 0 2.9E-3 0 5.062E-4 *Fp1=23.52 KHz R5 98 9 1MEG C3 98 9 6.7668P * ***************POLE STAGE*************** * *Fp=203 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.84E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=200 KHz G4 98 16 3 49 1.9952E-8 L2 98 17 795.77U R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 15 1 R16 24 23 10 D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 500P V7 22 27 .63V V5 22 21 .63V D4 21 15 DX V4 20 22 .63V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25) .MODEL QX NPN(BF=250) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6162 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6162/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 100MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 2P CI2 2 0 2P R1 1 3 90K R2 3 2 90K I1 4 50 1M R3 99 5 351.7 R4 99 6 351.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 300 R44 46 4 300 *Fp2=230 MHz C4 5 6 9.8376E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA1 0 0 0 .85 G1 98 9 POLY(1) 5 6 0 6.5E-3 0 8.646E-3 *Fp1=17.935 KHz R5 98 9 1MEG C3 98 9 8.874P * ***************POLE STAGE*************** * *Fp=230 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 6.9198E-16 * ***************POLE STAGE*************** * *Fp=250 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 6.3662E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 1E-8 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 200P V7 22 27 .63V V5 22 21 .23V D4 21 18 DX V4 20 22 .23V D3 18 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=227.3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6164 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6164/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 175MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 50K R2 3 2 50K I1 4 50 1M R3 99 5 201.7 R4 99 6 201.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 150 R44 46 4 150 *Fp2=190 MHz C4 5 6 2.0765P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA1 0 0 0 3.4 G1 98 9 POLY(1) 5 6 0 9.0E-3 0 10.6E-3 *Fp1=25.1 KHz R5 98 9 1MEG C3 98 9 6.3408P * ***************POLE STAGE*************** * *Fp=190 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-16 * ***************POLE STAGE*************** * *Fp=203 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 7.8401E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 5.6234E-9 L2 98 17 53.052E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 .23V D4 21 18 DX V4 20 22 .23V D3 18 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6165 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6165/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 725MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 6P CI2 2 0 6P R1 1 3 10K R2 3 2 10K I1 4 50 1M R3 99 5 51.7 R4 99 6 51.7 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=120 MHz C4 5 6 12.827P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 1E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(2) VA1 VA3 0 0 0 0 0 0 4.25 0 0 4.978143E5 G1 98 9 POLY(1) 5 6 0 38.0E-3 *Fp1=25.1 KHz R5 98 9 1MEG VA3 9 11 0 C3 98 11 3.897P * ***************POLE STAGE*************** * *Fp=120 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.3263E-15 * ***************POLE STAGE*************** * *Fp=124 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 1.2835E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 7.94328E-9 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 .25V D4 21 18 DX V4 20 22 .25V D3 18 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *$ *///////////////////////////////////////// *LM6171A Operational Amplifier Macro-Model *///////////////////////////////////////// * *Connections non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .SUBCKT LM6171A/NS 3 2 4 5 6 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * +/-15V Operation * Unity Gain Stable * Offset voltage (max) = 3mV * Gain-bandwidth product = 100 MHz * Supply current = 2.5mA * Slew rate = 3600V/uS * Open Loop gain = 90dB ******************************************************************** EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.006000e+03 .MODEL MRAX RES (TC1=-1.1e-05) FIN1 18 5 VTEMP 0.985 FIN2 19 5 VTEMP 1.015 CIN1 2 10 1e-12 CIN2 3 10 1e-12 RD1 18 11 2.45e+06 RD2 19 11 2.45e+06 RCM 11 10 3.8775e+07 FCMR 10 57 VCMX 3.16228 FPSR 10 57 VPSX 63.2456 RSLOPE 4 5 33333.3 GPWR 4 5 26 10 0.0016 ETEMP 27 28 32 33 0.178427 RIB 32 33 MRIB 1K .MODEL MRIB RES (TC1=0.00389579) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.002) RCM1 39 41 10 CCM 41 10 2.65258e-11 RPSR1 44 45 100 CPSR 45 10 1.59155e-10 ELIMN 10 52 26 10 91.8926 RDM 57 10 23.5073 C2 57 10 4.78743e-11 ECMP 40 97 26 10 2 ECMN 95 50 26 10 2 G2 58 10 57 10 0.00378 R2 58 10 11.254 GO2 59 10 58 10 35 EPOS 40 74 26 10 1.4 ENEG 75 50 26 10 1.5 GSOURCE 74 73 33 34 0.00135 GSINK 72 75 33 34 0.00135 ROO 81 86 13 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .ENDS *$ *///////////////////////////////////////// *LM6171B Operational Amplifier Macro-Model *///////////////////////////////////////// * *Connections non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .SUBCKT LM6171B/NS 3 2 4 5 6 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * +/-15V Operation * Unity Gain Stable * Offset voltage (max) = 6mV * Gain-bandwidth product = 100 MHz * Supply current = 2.5mA * Slew rate = 3600V/uS * Open Loop gain = 90dB ************************************************************************** EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.012000e+03 .MODEL MRAX RES (TC1=-1.1e-05) FIN1 18 5 VTEMP 0.985 FIN2 19 5 VTEMP 1.015 CIN1 2 10 1e-12 CIN2 3 10 1e-12 RD1 18 11 2.45e+06 RD2 19 11 2.45e+06 RCM 11 10 3.8775e+07 FCMR 10 57 VCMX 3.16228 FPSR 10 57 VPSX 63.2456 RSLOPE 4 5 33333.3 GPWR 4 5 26 10 0.0016 ETEMP 27 28 32 33 0.178427 RIB 32 33 MRIB 1K .MODEL MRIB RES (TC1=0.00389579) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.002) RCM1 39 41 10 CCM 41 10 2.65258e-11 RPSR1 44 45 100 CPSR 45 10 1.59155e-10 ELIMN 10 52 26 10 91.8926 RDM 57 10 23.5073 C2 57 10 4.78743e-11 ECMP 40 97 26 10 2 ECMN 95 50 26 10 2 G2 58 10 57 10 0.00378 R2 58 10 11.254 GO2 59 10 58 10 35 EPOS 40 74 26 10 1.4 ENEG 75 50 26 10 1.5 GSOURCE 74 73 33 34 0.00135 GSINK 72 75 33 34 0.00135 ROO 81 86 13 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .ENDS *$ *///////////////////////////////////////////////// *LM6172 Operational Amplifier Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6172/NS 3 2 4 5 6 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * +/-15V Operation * Unity Gain Stable * Offset voltage (max) = 3mV * Gain-bandwidth product = 100 MHz * Supply current = 2.3mA * Slew rate = 3000V/uS ******************************************************************** EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.005990e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=-1.1e-05) FIN1 18 5 VTEMP 0.991667 FIN2 19 5 VTEMP 1.00833 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 2.45e+06 RD2 19 11 2.45e+06 * Diff. Input Resistance RCM 11 10 3.8775e+07 * Common Mode Input Resistance FCMR 10 57 VCMX 3.16228 * Low Freq. CMRR FPSR 10 57 VPSX 63.2456 * Low Freq. PSRR RSLOPE 4 5 33333.3 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.0014 * Quiescent Supply Current ETEMP 27 28 32 33 0.173718 RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.00445322) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.002) RCM1 39 41 10 CCM 41 10 2.65258e-11 * CMRR vs. Freq. RPSR1 44 45 100 CPSR 45 10 1.59155e-10 * PSRR vs. Freq. ELIMN 10 52 26 10 99.3 RDM 57 10 29.6192 C2 57 10 3.79954e-11 ECMP 40 97 26 10 2 ECMN 95 50 26 10 2 G2 58 10 57 10 0.003 R2 58 10 11.254 GO2 59 10 58 10 35 * Avol and Slew-Rate Settings EPOS 40 74 26 10 1.4 ENEG 75 50 26 10 1.5 * Output Voltage Swing Settings GSOURCE 74 73 33 34 0.00107 GSINK 72 75 33 34 0.00105 * Output Current Settings ROO 81 86 13 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .ENDS *$ * /////////////////////////////////////////////////////////////////// * User Notes about what the CFA models can do: *Supply voltage dependant input offset voltage (Vos). *Temperature dependant input offset voltage (TCVos). *Supply voltage dependant input bias current (Ib+ & Ib- PSR). *Temperature dependant input bias current (TCIb+ & TCIb-). *Input voltage dependant input bias current (Ib- CMRR). *Non-inverting input resistance. *Asymmetrical output swing. *Output short circuit current (Isc). *Supply voltage dependant supply current. *Quiescent and dynamic supply current. *Input voltage dependant input slew rate. *Input voltage dependant output slew rate. *Multiple poles and zeros in open-loop transimpedance (Zt). *Supply voltage dependant input buffer impedance. *Supply voltage dependant open-loop voltage gain (Avol). *Feedback resistance dependant bandwidth. *Accurate small-signal pulse response. *Large-signal pulse response. *DC and AC common mode rejection ratio (CMRR). *DC and AC power supply rejection ratio (PSRR). *White and 1/f voltage noise (en). *White and 1/f current noise (in). *********************Modeled but not tested***************** *Asymmetrical output slew rate. *Input common mode input range. *Supply voltage dependant input slew rate. ***************************Not modeled********************** *Third-order large signal effects. *Self heating effects. *////////////////////////////////////////////////////////// *LM6181 CURRENT FEEDBACK OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6181/NS 1 2 99 50 40 * *Features: (TYP.) *High bandwidth = 100MHz *High slew rate = 2000V/uS *Current Feedback Topology *NOTE: Due to the addition of PSRR effects, model must be operated * with symetrical supply voltages. To avoid this limitation * and disable the PSRR effects, see EOS below. * ****************INPUT STAGE************** * GI1 99 5 POLY(1) 99 50 243.75U 2.708E-6 GI2 4 50 POLY(1) 99 50 243.75U 2.708E-6 FI1 99 5 VA3 100 FI2 4 50 VA4 100 Q1 50 3 5 QPN Q2 99 3 4 QNN GR1 5 6 5 6 2.38E-4 *^4.2K noiseless resistor C1 6 99 .468P GR2 4 7 4 7 2.38E-4 *^4.2K noiseless resistor C2 7 50 .468P GR3 99 8 99 8 1.58E-3 *^633ohm noiseless resistor V1 99 10 .3 RE1 10 30 130 D1 30 8 DX GR4 50 9 50 9 1.58E-3 *^633ohm noiseless resistor V2 11 50 .3 RE2 11 31 150 D2 9 31 DX Q3 8 6 2 QNI Q4 9 7 2 QPI DS1 3 12 DY VA3 12 5 0 DS2 13 3 DY VA4 4 13 0 GR6 1 99 1 99 5E-8 *^20MEG noiseless resistor GR7 1 50 1 50 5E-8 *^20MEG noiseless resistor GB1 1 99 POLY(2) 99 50 56 0 -1.2E-6 4E-8 1E-3 FN1 1 0 V18 1 GB2 99 2 POLY(3) 99 50 1 49 55 0 18.5E-6 -1.5E-7 -1E-7 -1E-6 FN2 2 0 V17 1 EOS 3 1 POLY(5) 99 50 45 0 47 0 57 0 59 61 -2.8E-3 9.3E-5 1 1 1 1 *To run on asymetrical supplies, change to 0.................^.^ CIN1 1 0 2P CIN2 2 0 3.75P * **************SECOND STAGE************** * I3 99 50 4.47M R8 99 49 7.19K R9 49 50 7.19K V3 99 16 1.7 D3 15 16 DX D4 17 15 DX V4 17 50 2.0 EH 99 98 99 49 1 G1 98 15 POLY(2) 99 8 50 9 0 1.58E-3 1.58E-3 *Fp1 = 27.96 KHz R5 98 15 2.372MEG C3 98 15 2.4P * ***************POLE STAGE*************** * *Fp=250MHz G2 98 20 15 49 1E-3 R14 98 20 1K C4 98 20 .692P * ***************POLE STAGE*************** * *Fp=250 MHz G3 98 21 20 49 1E-3 R15 98 21 1K C5 98 21 .692P * ***************POLE STAGE*************** * *Fp=275 MHz G4 98 22 21 49 1E-3 R16 98 22 1K C6 98 22 .5787P * ***************POLE STAGE*************** * *Fp=500 MHz G5 98 23 22 49 1E-3 R17 98 23 1K C7 98 23 .3183P * ***************PSRR STAGE*************** * G10 0 45 99 0 1.413E-4 L3 44 45 26.53U R25 44 0 10 G11 0 47 50 0 1.413E-4 L4 46 47 2.27364U R26 46 0 10 * ************THERMAL EFFECTS************* * I12 0 55 1 R27 0 55 10 TC=3.453E-3 7.93E-5 I13 0 56 1E-3 R28 0 56 1.5 TC=9.303E-4 8.075E-5 I14 0 57 1E-3 R29 0 57 3.34 TC=3.111E-3 * ************* NOISE SOURCES************* * V15 58 0 .1 D9 58 59 DN R30 59 0 726.4 V16 60 0 .1 D10 60 61 DN R31 61 0 726.4 V17 62 0 0 R32 62 0 73.6 V18 63 0 0 R33 63 0 1840 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 F5 99 35 VA8 1 D7 36 35 DX VA7 99 36 0 D8 35 99 DX E1 99 37 99 23 1 VA8 37 38 0 R35 38 40 50 V5 33 40 5.3V D5 23 33 DX V6 40 34 5.3V D6 34 23 DX CF1 40 2 2.1P * ***************MODELS USED************** * .MODEL QNI NPN(IS=1E-14 BF=10E4 VAF=62.9 KF=6.7E-14) .MODEL QPI PNP(IS=1E-14 BF=10E4 VAF=62.9 KF=6.7E-14) .MODEL QNN NPN(IS=1E-14 BF=10E4 VAF=62.9 KF=4.13E-13) .MODEL QPN PNP(IS=1E-14 BF=10E4 VAF=62.9 KF=4.13E-13) .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-17) .MODEL DN D(KF=1.667E-9 AF=1 XTI=0 EG=.3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6218 Fast Settling Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6218/NS 1 2 99 50 28 * *Features: *Low offset voltage = .2mV *High bandwidth = 17MHz *Slew rate (Av=-1) = 140V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 20N *^Input offset current CI1 1 0 2.5P CI2 2 0 2.5P R1 1 3 3.125G R2 3 2 3.125G I1 99 4 40U R43 45 4 1.25K R44 46 4 1.25K Q1 5 2 45 QX Q2 6 7 46 QX R3 50 5 2.54K R4 50 6 2.54K *Fp2=30 MHz C4 5 6 1.0433P * ***********COMMON MODE EFFECT*********** * I2 99 50 2.71M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 .2E-3 1 *Input offset voltage.^ R8 99 49 71.4K R9 49 50 71.4K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 POLY(1) 5 6 0 5E-3 0 5.056 *Fp1=38.24 Hz R5 98 9 100MEG C3 98 9 41.62P * ***************POLE STAGE*************** * *Fp=110 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.4469E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=6 KHz G4 98 16 3 49 1E-8 L2 98 17 26.526M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 E1 99 23 99 15 1 R16 24 23 10 D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 .001U V7 22 27 .63V V5 22 21 .63V D4 21 15 DX V4 20 22 .63V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25) .MODEL QX PNP(BF=100) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6261 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6261/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 50MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 1.5P CI2 2 0 1.5P R1 1 3 162.5K R2 3 2 162.5K I1 4 50 1M R3 99 5 651.7 R4 99 6 651.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 600 R44 46 4 600 *Fp2=200 MHz C4 5 6 6.1054E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 5E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.335 D1 9 8 DX D2 10 9 DX V3 10 50 2.155 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA1 0 0 0 20 G1 98 9 POLY(1) 5 6 0 2.9E-3 0 5.062E-4 *Fp1=23.52 KHz R5 98 9 1MEG C3 98 9 6.7668P ****************POLE STAGE*************** * *Fp=203 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.84E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=200 KHz G4 98 16 3 49 1.9952E-8 L2 98 17 795.77U R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 15 1 R16 24 23 10 D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 500P V7 22 27 .63V V5 22 21 .63V D4 21 15 DX V4 20 22 .63V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25) .MODEL QX NPN(BF=250) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6262 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6262/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 100MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 2P CI2 2 0 2P R1 1 3 90K R2 3 2 90K I1 4 50 1M R3 99 5 351.7 R4 99 6 351.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 300 R44 46 4 300 *Fp2=230 MHz C4 5 6 9.8376E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA1 0 0 0 .85 G1 98 9 POLY(1) 5 6 0 6.5E-3 0 8.646E-3 *Fp1=17.935 KHz R5 98 9 1MEG C3 98 9 8.874P * ***************POLE STAGE*************** * *Fp=230 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 6.9198E-16 * ***************POLE STAGE*************** * *Fp=250 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 6.3662E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 1E-8 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 200P V7 22 27 .63V V5 22 21 .23V D4 21 18 DX V4 20 22 .23V D3 18 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=227.3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6264 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6264/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 175MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 50K R2 3 2 50K I1 4 50 1M R3 99 5 201.7 R4 99 6 201.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 150 R44 46 4 150 *Fp2=190 MHz C4 5 6 2.0765P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA1 0 0 0 3.4 G1 98 9 POLY(1) 5 6 0 9.0E-3 0 10.6E-3 *Fp1=25.1 KHz R5 98 9 1MEG C3 98 9 6.3408P * ***************POLE STAGE*************** * *Fp=190 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-16 * ***************POLE STAGE*************** * *Fp=203 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 7.8401E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 5.6234E-9 L2 98 17 53.052E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 .23V D4 21 18 DX V4 20 22 .23V D3 18 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6265 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6265/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 725MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 6P CI2 2 0 6P R1 1 3 10K R2 3 2 10K I1 4 50 1M R3 99 5 51.7 R4 99 6 51.7 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=120 MHz C4 5 6 12.827P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 1E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(2) VA1 VA3 0 0 0 0 0 0 4.25 0 0 4.978143E5 G1 98 9 POLY(1) 5 6 0 38.0E-3 *Fp1=25.1 KHz R5 98 9 1MEG VA3 9 11 0 C3 98 11 3.897P * ***************POLE STAGE*************** * *Fp=120 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.3263E-15 * ***************POLE STAGE*************** * *Fp=124 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 1.2835E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 7.94328E-9 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 .25V D4 21 18 DX V4 20 22 .25V D3 18 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6310 CURRENT FEEDBACK OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * Connections: Non-Inverting Input * | Inverting Input * | | Output * | | | +Vcc * | | | | -Vee * | | | | | Vdis_bar * | | | | | | .SUBCKT LM6310/NS 3 2 6 7 4 8 *Features * This is a Low-Cost, Low-Power, 110MHz, Monolithic * Current Feedback Op Amp with Disable * * DISABLE/BIAS BLOCK * R1 7 8 20.0K C3 8 0 1.00P R2 8 10 5.00K Q1 7 10 15 QINN R3 7 12 100 V1 12 13 1.50 Q2 13 14 15 QINN D1 10 11 DDV D2 11 10 DDV 0.11 R4 11 14 2.00K R5 14 16 2.00K R6 7 16 20.0K R7 16 17 20.0K C4 15 0 336F I1 15 4 150U C5 17 0 101F V2 17 4 3.00 * R8 7 20 20.0K D3 20 21 DQ 1.88 G1 21 0 POLY(1) 7 12 0 10.0M D4 22 21 DQ 1.88 Q3 22 20 7 QINP 3.00 I2 22 4 176U R9 7 23 625 D5 23 22 DDV 0.28 C6 22 0 1.00P * C1 7 0 1.00P C2 4 0 1.00P G2 7 4 POLY(1) 7 23 0 4.13M G3 7 30 POLY(1) 7 23 0 1.54M C7 30 0 751F G4 34 4 POLY(1) 7 23 0 1.46M C8 34 0 751F * * INPUT STAGE * G5 3 0 POLY(3) 7 23 62 0 63 0 0 20.3U 1.00M 1.00M C9 3 0 1.00P E1 3 32 POLY(2) 60 0 61 0 -1.50M 1.00 1.00 D6 30 31 DQ 0.25 Q4 4 32 31 QINP Q5 7 32 33 QINN D7 33 34 DQ 0.25 G6 41 0 POLY(3) 7 23 64 0 65 0 0 36.4U 1.00M 1.00M Q6 41 30 42 QINN D8 42 2 DQ 0.25 C10 2 0 3.50P D9 2 43 DQ 0.25 Q7 44 34 43 QINP * * GAIN STAGE * R10 7 40 550 C11 7 40 1.80P V3 40 41 1.90 C12 41 47 580F C13 41 51 430F V4 7 46 750M D10 51 46 DOR G7 7 47 POLY(2) 7 40 7 47 0 3.83M 208N G8 7 51 POLY(1) 7 40 0 9.03M C14 51 0 950F * V5 44 45 1.90 R11 45 4 550 C15 45 4 1.80P C16 44 47 505F C17 44 50 270F D11 48 47 DOR V6 48 4 1.30 G9 47 4 POLY(2) 45 4 47 4 0 3.91M 2.14U G10 50 4 POLY(1) 45 4 0 3.18M C18 50 0 515F * * OUTPUT STAGE * C19 47 0 904F Q8 7 47 50 QOUTN1 D12 51 52 DDV 1.67 Q9 4 50 52 QOUTP1 Q10 7 51 6 QOUTN2 C20 6 0 1.00P C21 6 53 403F E2 53 0 POLY(2) 3 0 7 23 0 1.00 0 0 -9.09 Q11 4 52 6 QOUTP2 * * NOISE SOURCES * I3 61 60 DC 26.8U D13 60 0 DN1 D14 0 61 DN1 * I4 63 62 DC 56.9U D15 62 0 DN2 D16 0 63 DN2 * I5 65 64 DC 46.9U D17 64 0 DN3 D18 0 65 DN3 * * MODELS * .MODEL DDV D IS=0.287F N=2.00 RS=274M CJO=354F M=500M VJ=798M TT=30.4P .MODEL DN1 D IS=0.166F KF=4.48F AF=1.00 .MODEL DN2 D IS=0.166F KF=20.6F AF=1.00 .MODEL DN3 D IS=0.166F KF=87.6F AF=1.00 .MODEL DOR D TT=100N .MODEL DQ D IS=0.165F RS=561M CJO=159F M=495M VJ=797M TT=19.2P * .MODEL QINN NPN + IS =4.242E-17 BF =3.239E+02 NF =1.000E+00 VAF=2.115E+01 + IKF=6.322E-03 ISE=7.591E-18 NE =1.197E+00 BR =3.355E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=1.018E-02 ISC=6.091E-20 + NC =1.700E+00 RB =3.146E+02 IRB=0.000E+00 RBM=1.086E+02 + RE =2.185E+00 RC =3.022E+01 CJE=4.079E-14 VJE=7.973E-01 + MJE=4.950E-01 TF =2.078E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=1.529E-02 CJC=5.906E-14 VJC=8.046E-01 MJC=4.931E-01 + XCJC=1.04E-01 TR =1.620E-10 CJS=6.743E-13 MJS=0.000E+00 + VJS=5.723E-01 FC =9.765E-01 * .MODEL QOUTN1 NPN + IS =2.636E-16 BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01 + IKF=3.060E-02 ISE=3.674E-17 NE =1.197E+00 BR =3.868E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=4.928E-02 ISC=2.045E-19 + NC =1.700E+00 RB =5.467E+01 IRB=0.000E+00 RBM=1.212E+01 + RE =4.515E-01 RC =1.999E+01 CJE=1.974E-13 VJE=7.973E-01 + MJE=4.950E-01 TF =1.901E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=7.403E-02 CJC=1.883E-13 VJC=8.046E-01 MJC=4.931E-01 + XCJC=1.57E-01 TR =5.184E-10 CJS=3.540E-13 VJS=5.723E-01 + MJS=4.105E-01 FC =9.765E-01 * .MODEL QOUTN2 NPN + IS =9.456E-16 BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01 + IKF=1.098E-01 ISE=1.318E-16 NE =1.197E+00 BR =3.989E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=1.767E-01 ISC=6.688E-19 + NC =1.700E+00 RB =6.524E+01 IRB=0.000E+00 RBM=5.338E+01 + RE =1.013E+01 RC =4.303E+00 CJE=7.082E-13 VJE=7.973E-01 + MJE=4.950E-01 TF =1.866E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=2.655E-01 CJC=6.056E-13 VJC=8.046E-01 MJC=4.931E-01 + XCJC=1.76E-01 TR =8.748E-10 CJS=8.651E-13 VJS=5.723E-01 + MJS=4.105E-01 FC =9.765E-01 * .MODEL QINP PNP + IS =4.242E-17 BF =7.165E+01 NF =1.000E+00 VAF=1.720E+01 + IKF=4.832E-03 ISE=1.639E-16 NE =1.366E+00 BR =1.658E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=3.394E-02 ISC=9.789E-19 + NC =1.634E+00 RB =1.620E+02 IRB=0.000E+00 RBM=7.750E+01 + RE =2.382E+00 RC =3.386E+01 CJE=4.079E-14 VJE=7.975E-01 + MJE=5.000E-01 TF =3.263E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=1.306E-02 CJC=9.356E-14 VJC=7.130E-01 MJC=4.200E-01 + XCJC=1.04E-01 TR =6.577E-10 CJS=6.743E-13 VJS=6.691E-01 + MJS=0.000E+00 FC =8.803E-01 * .MODEL QOUTP1 PNP + IS =2.399E-16 BF =7.165E+01 NF =1.000E+00 VAF=3.439E+01 + IKF=3.509E-02 ISE=1.190E-15 NE =1.366E+00 BR =1.946E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=2.464E-01 ISC=6.685E-18 + NC =1.634E+00 RB =1.542E+01 IRB=0.000E+00 RBM=3.788E+00 + RE =3.281E-01 RC =1.420E+01 CJE=2.962E-13 VJE=7.975E-01 + MJE=5.000E-01 TF =3.051E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=9.481E-02 CJC=4.131E-13 VJC=7.130E-01 MJC=4.200E-01 + XCJC=1.70E-01 TR =1.388E-09 CJS=9.092E-13 VJS=6.691E-01 + MJS=3.950E-01 FC =8.803E-01 * .MODEL QOUTP2 PNP + IS =1.147E-15 BF =7.165E+01 NF =1.000E+00 VAF=3.439E+01 + IKF=1.678E-01 ISE=5.690E-15 NE =1.366E+00 BR =1.961E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=1.178E+00 ISC=3.188E-17 + NC =1.634E+00 RB =5.323E+01 IRB=0.000E+00 RBM=5.079E+01 + RE =1.069E+01 RC =3.177E+00 CJE=1.416E-12 VJE=7.975E-01 + MJE=5.000E-01 TF =3.042E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=4.534E-01 CJC=1.918E-12 VJC=7.130E-01 MJC=4.200E-01 + XCJC=1.76E-01 TR =1.973E-09 CJS=3.054E-12 VJS=6.691E-01 + MJS=3.950E-01 FC =8.803E-01 * .ENDS *$ *///////////////////////////////////////////////// *LM6311 Operational Amplifier Macro-Model *///////////////////////////////////////////////// * * Connections: Non-Inverting Input * | Inverting * | | Output * | | | +Vcc * | | | | -Vee * | | | | | External Compensation * | | | | | | * | | | | | | .SUBCKT LM6311/NS 3 2 6 7 4 5 *Features * This is an Ultra Low Noise, Wideband Monolithic Voltage * Feedback Op Amp with Current Supply Adjust and External * Compensation. * * * BIAS CIRCUITRY * R1 7 10 100 Q1 10 12 11 QINN1 D1 11 12 DZ R2 11 8 1.00K C1 8 0 1.00P R3 8 4 1.00G R4 7 12 100K D2 12 13 DZ D3 13 4 DZ * G1 0 14 POLY(3) 12 4 7 10 0 14 -226M 294M -10.0 1.00M D4 0 14 DY * G2 7 20 POLY(2) 14 0 7 20 -442N 2.56U 1.39U C2 20 0 800F G7 7 34 POLY(2) 14 0 7 34 -442N 2.56U 1.39U C5 34 0 800F * G4 21 4 POLY(2) 14 0 21 4 9.27U 5.43U 400N C4 21 0 400F G9 36 4 POLY(2) 14 0 36 4 9.27U 5.43U 400N C7 36 0 400F * * INPUT STAGE * C3 2 0 1.00P G3 2 0 POLY(2) 50 0 51 0 0 100U 100U Q2 4 2 20 QINP2 Q3 7 2 21 QINN1 V1 7 22 DC 1.00 Q4 22 20 23 QINN1 Q5 24 21 23 QINP2 V2 24 4 DC 1.00 * Q6 31 34 23 QINN2 Q7 32 36 23 QINP1 Q8 7 35 36 QINN2 Q9 4 35 34 QINP1 G8 35 0 POLY(2) 52 0 53 0 0 100U 100U E1 3 35 POLY(2) 54 0 55 0 1.55M 1.00 1.00 C6 3 0 1.00P * * GAIN STAGE * D5 7 30 DY G5 30 31 POLY(1) 30 31 0 1.00 R5 7 31 450 V3 7 40 DC 1.75 D7 41 40 DX C8 7 41 7.00P G10 7 41 POLY(3) 7 41 7 31 30 31 0 574N 2.22M 250M 0 4.78U 538U C11 31 43 400F G12 7 43 POLY(1) 7 31 0 2.22M C12 43 0 800F * G6 32 33 POLY(1) 32 33 0 1.00 D6 33 4 DY R6 32 4 450 D8 42 41 DX V4 42 4 DC 1.75 C10 41 4 7.00P G11 41 4 POLY(3) 41 4 32 4 32 33 0 1.33U 2.22M 250M 0 11.1U 1.25M C13 32 44 800F G13 44 4 POLY(1) 32 4 0 8.00M C14 44 0 400F * C9 5 0 1.00P R7 5 41 25.0 * * OUTPUT STAGE * Q10 4 41 43 QOUTP1 2.00 Q11 7 41 44 QOUTN1 2.00 Q12 7 43 6 QOUTN2 C15 6 0 1.00P Q13 4 44 6 QOUTP2 D9 41 6 DY D10 6 41 DY * * NOISE BLOCKS * G14 51 50 POLY(1) 14 0 8.09U 4.05U D11 50 0 DN1 D12 0 51 DN1 * G15 53 52 POLY(1) 14 0 8.09U 4.05U D13 52 0 DN2 D14 0 53 DN2 * G16 55 54 POLY(1) 14 0 2.71U 1.35U D15 54 0 DN3 D16 0 55 DN3 * * MODELS * .MODEL DN1 D IS=0.166F KF=19.6U AF=3.00 .MODEL DN2 D IS=0.166F KF=18.2U AF=3.00 .MODEL DN3 D IS=0.166F KF=1.07F AF=1.00 .MODEL DX D TT=100N .MODEL DY D IS=4.11E-16 RS=1.00 .MODEL DZ D IS=3.07E-17 RS=1.00 * .MODEL QINN1 NPN + IS =5.800E-16 BF =3.239E+02 NF =1.000E+00 VAF=4.229E+01 + IKF=6.700E-02 ISE=8.000E-17 NE =1.197E+00 BR =4.003E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=1.000E-01 ISC=4.000E-19 + NC =1.700E+00 RB =1.843E+01 IRB=0.000E+00 RBM=4.083E+00 + RE =2.100E-01 RC =1.000E+01 CJE=4.300E-13 VJE=7.973E-01 + MJE=4.950E-01 TF =1.862E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=1.651E-01 PTF=0.000E+00 CJC=3.500E-13 VJC=8.046E-01 + MJC=4.931E-01 XCJC=1.778E-01 TR =7.000E-10 CJS=1.600E-12 + VJS=5.723E-01 MJS=0.000E+00 FC =9.765E-01 * .MODEL QINN2 NPN + IS =5.800E-16 BF =2.939E+02 NF =1.000E+00 VAF=3.279E+01 + IKF=6.700E-02 ISE=8.000E-17 NE =1.197E+00 BR =4.003E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=1.000E-01 ISC=4.000E-19 + NC =1.700E+00 RB =1.843E+01 IRB=0.000E+00 RBM=4.083E+00 + RE =2.100E-01 RC =1.000E+01 CJE=4.300E-13 VJE=7.973E-01 + MJE=4.950E-01 TF =1.862E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=1.651E-01 PTF=0.000E+00 CJC=3.500E-13 VJC=8.046E-01 + MJC=4.931E-01 XCJC=1.778E-01 TR =7.000E-10 CJS=1.600E-12 + VJS=5.723E-01 MJS=0.000E+00 FC =9.765E-01 * .MODEL QOUTN1 NPN + IS =3.954E-16 BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01 + IKF=4.590E-02 ISE=5.512E-17 NE =1.197E+00 BR =3.957E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=7.392E-02 ISC=2.867E-19 + NC =1.700E+00 RB =3.645E+01 IRB=0.000E+00 RBM=8.077E+00 + RE =3.010E-01 RC =2.438E+01 CJE=2.962E-13 VJE=7.973E-01 + MJE=4.950E-01 TF =1.875E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=1.110E-01 PTF=0.000E+00 CJC=2.608E-13 VJC=8.046E-01 + MJC=4.931E-01 XCJC=1.704E-01 TR =5.832E-10 CJS=4.115E-13 + VJS=5.723E-01 MJS=4.105E-01 FC =9.765E-01 * .MODEL QOUTN2 NPN + IS =1.880E-15 BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01 + IKF=2.182E-01 ISE=2.620E-16 NE =1.197E+00 BR =4.090E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=3.513E-01 ISC=1.229E-18 + NC =1.700E+00 RB =7.668E+00 IRB=0.000E+00 RBM=1.699E+00 + RE =5.063E+00 RC =3.371E+00 CJE=1.408E-12 VJE=7.973E-01 + MJE=4.950E-01 TF =1.838E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=5.278E-01 PTF=0.000E+00 CJC=1.095E-12 VJC=8.046E-01 + MJC=4.931E-01 XCJC=1.930E-01 TR =1.296E-09 CJS=1.217E-12 + VJS=5.723E-01 MJS=4.105E-01 FC =9.765E-01 * .MODEL QINP1 PNP + IS =3.500E-16 BF =7.165E+01 NF =1.000E+00 VAF=1.720E+01 + IKF=4.120E-02 ISE=1.750E-15 NE =1.366E+00 BR =1.970E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=3.600E-01 ISC=9.877E-18 + NC =1.634E+00 RB =7.797E+00 IRB=0.000E+00 RBM=1.915E+00 + RE =2.260E-01 RC =1.500E+01 CJE=4.300E-13 VJE=7.975E-01 + MJE=5.000E-01 TF =3.032E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=1.374E-01 PTF=0.000E+00 CJC=5.600E-13 VJC=7.130E-01 + MJC=4.200E-01 XCJC=1.778E-01 TR =1.605E-09 CJS=1.600E-12 + VJS=6.691E-01 MJS=0.000E+00 FC =8.803E-01 * .MODEL QINP2 PNP + IS =3.500E-16 BF =6.565E+01 NF =1.000E+00 VAF=1.370E+01 + IKF=4.120E-02 ISE=1.750E-15 NE =1.366E+00 BR =1.970E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=3.600E-01 ISC=9.877E-18 + NC =1.634E+00 RB =7.797E+00 IRB=0.000E+00 RBM=1.915E+00 + RE =2.260E-01 RC =1.500E+01 CJE=4.300E-13 VJE=7.975E-01 + MJE=5.000E-01 TF =3.032E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=1.374E-01 PTF=0.000E+00 CJC=5.600E-13 VJC=7.130E-01 + MJC=4.200E-01 XCJC=1.778E-01 TR =1.605E-09 CJS=1.600E-12 + VJS=6.691E-01 MJS=0.000E+00 FC =8.803E-01 * .MODEL QOUTP1 PNP + IS =2.399E-16 BF =7.165E+01 NF =1.000E+00 VAF=3.439E+01 + IKF=3.509E-02 ISE=1.190E-15 NE =1.366E+00 BR =1.946E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=2.464E-01 ISC=6.685E-18 + NC =1.634E+00 RB =1.542E+01 IRB=0.000E+00 RBM=3.788E+00 + RE =3.281E-01 RC =1.420E+01 CJE=2.962E-13 VJE=7.975E-01 + MJE=5.000E-01 TF =3.051E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=9.481E-02 PTF=0.000E+00 CJC=4.131E-13 VJC=7.130E-01 + MJC=4.200E-01 XCJC=1.704E-01 TR =1.388E-09 CJS=9.092E-13 + VJS=6.691E-01 MJS=3.950E-01 FC =8.803E-01 * .MODEL QOUTP2 PNP + IS =1.140E-15 BF =1.401E+02 NF =1.000E+00 VAF=3.439E+01 + IKF=1.668E-01 ISE=5.655E-15 NE =1.366E+00 BR =2.009E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=1.171E+00 ISC=3.141E-17 + NC =1.634E+00 RB =3.245E+00 IRB=0.000E+00 RBM=7.970E-01 + RE =5.069E+00 RC =5.381E+00 CJE=1.408E-12 VJE=7.975E-01 + MJE=5.000E-01 TF =3.013E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=4.506E-01 PTF=0.000E+00 CJC=1.734E-12 VJC=7.130E-01 + MJC=4.200E-01 XCJC=1.929E-01 TR =2.704E-09 CJS=2.020E-12 + VJS=6.691E-01 MJS=3.950E-01 FC =8.803E-01 * .ENDS *$ *///////////////////////////////////////////////// *LM6317 Operational Amplifier Macro-Model *///////////////////////////////////////////////// * Connections: Non-Inverting * | Inverting * | | Output * | | | +Vcc * | | | | -Vcc * | | | | | .SUBCKT LM6317/NS 3 2 6 7 4 *Features * This is a High Speed, Unity Gain Stable Monolithic Voltage * Feedback Op Amp. * * INVERTING BUFFER * R1 7 10 318 R2 11 4 214 G1 7 12 POLY(2) 7 4 7 10 -58.71U 19.57U 3.145M C1 12 0 481F Q1 11 2 12 QINP C3 2 0 500F Q2 10 2 13 QINN C2 13 0 247F G2 13 4 POLY(2) 7 4 11 4 -16.66U 5.554U 2.921M * R3 7 14 433 V1 14 15 1.62 Q3 15 12 16 QINN R5 16 21 150 Q4 17 13 16 QINP V2 17 18 1.57 R4 18 4 433 * * NON-INVERTING BUFFER * R6 7 19 437 V3 19 20 1.64 Q5 20 24 21 QINN Q6 22 26 21 QINP V4 22 23 1.62 R7 23 4 437 G3 7 24 POLY(2) 7 4 7 27 -59.29U 19.43U 3.145M C5 24 0 481F Q7 28 25 24 QINP C4 25 0 500F Q8 27 25 26 QINN C6 26 0 247F G4 26 4 POLY(2) 7 4 28 4 -17.09U 5.697U 2.912M R8 7 27 318 E1 3 25 POLY(1) 40 0 500U 2.49 G5 3 0 POLY(1) 41 0 180N 262U R9 28 4 214 * * CURRENT MIRROR GAIN BLOCKS * V5 7 29 2.10 D1 31 29 DX C7 20 31 431F C8 20 6 1.80P C9 22 6 1.80P C10 22 31 476F D2 30 31 DX V6 30 4 2.10 G6 7 31 POLY(1) 7 19 0 6.865M R10 31 0 167K C11 31 0 475F G7 31 4 POLY(1) 23 4 0 6.865M G8 7 32 POLY(1) 7 19 0 2.288M C12 32 0 1.5P G9 35 4 POLY(1) 23 4 0 2.288M C13 35 0 1.5P * * OUTPUT STAGE * D3 32 33 DY Q9 4 31 33 QOUTP1 Q10 7 31 34 QOUTN1 D4 34 35 DY Q11 7 32 36 QOUTN1 Q12 4 31 36 QOUTP1 Q13 7 31 37 QOUTN1 Q14 4 35 37 QOUTP1 Q15 7 36 38 QOUTN2 R11 38 6 10.0 C14 6 0 3.20P R12 6 39 10.0 Q16 4 37 39 QOUTP2 * * NOISE BLOCKS * R13 40 0 122 R14 40 0 122 R15 41 0 122 R16 41 0 122 * * MODELS * .Model DX D TT=200N .Model DY D IS=0.395F .Model DZ D IS=0.240F * .MODEL QINN NPN + IS =0.166F BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01 + IKF=2.462E-02 ISE=2.956E-17 NE =1.197E+00 BR =3.719E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=3.964E-02 ISC=1.835E-19 + NC =1.700E+00 RB =118 IRB=0.000E+00 RBM=65.1 + RC =2.645E+01 CJE=1.632E-13 VJE=7.973E-01 + MJE=4.950E-01 TF =1.948E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=5.955E-02 PTF=0.000E+00 CJC=1.720E-13 VJC=8.046E-01 + MJC=4.931E-01 XCJC=589M TR =4.212E-10 CJS=629F + MJS=0 KF =1.00P AF =1.000E+00 + FC =9.765E-01 * .MODEL QOUTN1 NPN + IS =3.954E-16 BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01 + IKF=4.590E-02 ISE=5.512E-17 NE =1.197E+00 BR =3.719E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=7.392E-02 ISC=3.087E-19 + NC =1.700E+00 RB =3.645E+01 IRB=0.000E+00 RBM=8.077E+00 + RC =2.702E+01 CJE=2.962E-13 VJE=7.973E-01 + MJE=4.950E-01 TF =1.904E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=1.110E-01 PTF=0.000E+00 CJC=2.846E-13 VJC=8.046E-01 + MJC=4.931E-01 XCJC=1.562E-01 TR =5.832E-10 CJS=5.015E-13 + VJS=5.723E-01 MJS=4.105E-01 KF =1.00P AF =1.000E+00 + FC =9.765E-01 * .MODEL QOUTN2 NPN + IS =9.386E-16 BF =3.239E+02 NF =1.000E+00 VAF=8.457E+01 + IKF=1.089E-01 ISE=1.308E-16 NE =1.197E+00 BR =3.960E+01 + NR =1.000E+00 VAR=1.696E+00 IKR=1.754E-01 ISC=6.787E-19 + NC =1.700E+00 RB =15.4 IRB=0.000E+00 RBM=3.4 + RC =1.857E+01 CJE=7.030E-13 VJE=7.973E-01 + MJE=4.950E-01 TF =1.874E-11 XTF=1.873E+01 VTF=2.825E+00 + ITF=2.635E-01 PTF=0.000E+00 CJC=6.172E-13 VJC=8.046E-01 + MJC=4.931E-01 XCJC=171M TR =1.069E-09 CJS=1.028E-12 + VJS=5.723E-01 MJS=4.105E-01 KF =1.00P AF =1.000E+00 + FC =9.765E-01 * .MODEL QINP PNP + IS =0.166F BF =7.165E+01 NF =1.000E+00 VAF=20.0 + IKF=1.882E-02 ISE=6.380E-16 NE =1.366E+00 BR =1.833E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=1.321E-01 ISC=3.666E-18 + NC =1.634E+00 RB =78.8 IRB=0.000E+00 RBM=57.6 + RC =3.739E+01 CJE=1.588E-13 VJE=7.975E-01 + MJE=5.000E-01 TF =3.156E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=5.084E-02 PTF=0.000E+00 CJC=2.725E-13 VJC=7.130E-01 + MJC=4.200E-01 XCJC=741M TR =7.500E-11 CJS=515F + MJS=0 KF =1.00P AF =1.000E+00 + FC =8.803E-01 * .MODEL QOUTP1 PNP + IS =2.399E-16 BF =7.165E+01 NF =1.000E+00 VAF=3.439E+01 + IKF=3.509E-02 ISE=1.190E-15 NE =1.366E+00 BR =1.900E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=2.464E-01 ISC=6.745E-18 + NC =1.634E+00 RB =1.542E+01 IRB=0.000E+00 RBM=4.059E+00 + RC =4.174E+01 CJE=2.962E-13 VJE=7.975E-01 + MJE=5.000E-01 TF =3.107E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=9.481E-02 PTF=0.000E+00 CJC=4.508E-13 VJC=7.130E-01 + MJC=4.200E-01 XCJC=1.562E-01 TR =9.500E-11 CJS=1.045E-12 + VJS=6.691E-01 MJS=3.950E-01 KF =1.00P AF =1.000E+00 + FC =8.803E-01 * .MODEL QOUTP2 PNP + IS =5.693E-16 BF =7.165E+01 NF =1.000E+00 VAF=3.439E+01 + IKF=8.328E-02 ISE=2.824E-15 NE =1.366E+00 BR =1.948E+01 + NR =1.000E+00 VAR=1.805E+00 IKR=5.848E-01 ISC=1.586E-17 + NC =1.634E+00 RB =6.5 IRB=0.000E+00 RBM=1.7 + RC =1.767E+01 CJE=7.030E-13 VJE=7.975E-01 + MJE=5.000E-01 TF =3.073E-11 XTF=5.386E+00 VTF=2.713E+00 + ITF=2.250E-01 PTF=0.000E+00 CJC=9.776E-13 VJC=7.130E-01 + MJC=4.200E-01 XCJC=171M TR =1.450E-10 CJS=1.637E-12 + VJS=6.691E-01 MJS=3.950E-01 KF =1.00P AF =1.000E+00 + FC =8.803E-01 * .ENDS *$ *////////////////////////////////////////////////////////// *LM6361 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6361/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 50MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 1.5P CI2 2 0 1.5P R1 1 3 162.5K R2 3 2 162.5K I1 4 50 1M R3 99 5 651.7 R4 99 6 651.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 600 R44 46 4 600 *Fp2=200 MHz C4 5 6 6.1054E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 5E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.335 D1 9 8 DX D2 10 9 DX V3 10 50 2.155 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA1 0 0 0 20 G1 98 9 POLY(1) 5 6 0 2.9E-3 0 5.062E-4 *Fp1=23.52 KHz R5 98 9 1MEG C3 98 9 6.7668P * ***************POLE STAGE*************** * *Fp=203 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.84E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=200 KHz G4 98 16 3 49 1.9952E-8 L2 98 17 795.77U R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 15 1 R16 24 23 10 D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 500P V7 22 27 .63V V5 22 21 .63V D4 21 15 DX V4 20 22 .63V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25) .MODEL QX NPN(BF=250) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6362 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6362/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 100MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 2P CI2 2 0 2P R1 1 3 90K R2 3 2 90K I1 4 50 1M R3 99 5 351.7 R4 99 6 351.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 300 R44 46 4 300 *Fp2=230 MHz C4 5 6 9.8376E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 3E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA1 0 0 0 .85 G1 98 9 POLY(1) 5 6 0 6.5E-3 0 8.646E-3 *Fp1=17.935 KHz R5 98 9 1MEG C3 98 9 8.874P * ***************POLE STAGE*************** * *Fp=230 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 6.9198E-16 * ***************POLE STAGE*************** * *Fp=250 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 6.3662E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 1E-8 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 200P V7 22 27 .63V V5 22 21 .23V D4 21 18 DX V4 20 22 .23V D3 18 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=227.3) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6364 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6364/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 175MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 50K R2 3 2 50K I1 4 50 1M R3 99 5 201.7 R4 99 6 201.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 150 R44 46 4 150 *Fp2=190 MHz C4 5 6 2.0765P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 2E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(1) VA1 0 0 0 3.4 G1 98 9 POLY(1) 5 6 0 9.0E-3 0 10.6E-3 *Fp1=25.1 KHz R5 98 9 1MEG C3 98 9 6.3408P * ***************POLE STAGE*************** * *Fp=190 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-16 * ***************POLE STAGE*************** * *Fp=203 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 7.8401E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 5.6234E-9 L2 98 17 53.052E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 .23V D4 21 18 DX V4 20 22 .23V D3 18 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *$ *////////////////////////////////////////////////////////// *LM6365 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6365/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 725MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N *^Input offset current CI1 1 0 6P CI2 2 0 6P R1 1 3 10K R2 3 2 10K I1 4 50 1M R3 99 5 51.7 R4 99 6 51.7 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=120 MHz C4 5 6 12.827P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M *^Quiescent supply current EOS 7 1 POLY(1) 16 49 1E-3 1 *Input offset voltage.^ R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 F1 9 98 POLY(2) VA1 VA3 0 0 0 0 0 0 4.25 0 0 4.978143E5 G1 98 9 POLY(1) 5 6 0 38.0E-3 *Fp1=25.1 KHz R5 98 9 1MEG VA3 9 11 0 C3 98 11 3.897P * ***************POLE STAGE*************** * *Fp=120 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.3263E-15 * ***************POLE STAGE*************** * *Fp=124 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 1.2835E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 7.94328E-9 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 .25V D4 21 18 DX V4 20 22 .25V D3 18 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *$ *///////////////////////////////////////////////// *LM7121 Operational Amplifier Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM7121/NS 3 2 4 5 6 * *Features *Stable with unlimited capacitive loads *Bandwidth 235MHz *Slew Rate 1280V/usec * EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 * ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.016000e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=0.00012) FIN1 18 5 VTEMP 0.996154 FIN2 19 5 VTEMP 1.00385 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 1e+06 RD2 19 11 1e+06 * Diff. Input Resistance RCM 11 10 9.5e+06 * Common Mode Input Resistance FCMR 10 57 VCMX 12.5893 * Low Freq. CMRR FPSR 10 57 VPSX 100.237 * Low Freq. PSRR RSLOPE 4 5 100000 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.005 * Quiescent Supply Current ETEMP 27 28 32 33 0.135842 RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.00222401) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.0015) RCM1 39 41 125.893 CCM 41 10 5.30516e-11 * CMRR vs. Freq. RPSR1 44 45 501.187 CPSR 45 10 5.30516e-11 * PSRR vs. Freq. * ELIMN 10 52 26 10 99.3 RDM 57 10 96.4111 C2 57 10 4.28254e-12 ECMP 40 97 26 10 1.5 ECMN 95 50 26 10 1.5 G2 58 10 57 10 0.00128 R2 58 10 8.10332 GO2 59 10 58 10 4 * Avol and Slew-Rate Settings EPOS 40 74 26 10 1 ENEG 75 50 26 10 1.1 * Output Voltage Swing Settings GSOURCE 74 73 33 34 0.0007 GSINK 72 75 33 34 0.00055 * Output Current Settings *ROO 81 86 25.5 ROO 81 86 10 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 *Variable Slew Rate vs. Differential Input EDAA1 750 10 3 2 1.0 RADD1 750 760 1K VADD1 760 10 DC 0 FADD1 10 751 VADD1 1.0 DADD1 752 751 DMOD1 RADD2 752 10 1K DADD2 751 753 DMOD1 RADD3 753 10 1K ELIMN 712 52 26 10 15.3 EXLIMN 10 712 10 752 18.0 ELIMP 51 711 26 10 15.3 EXLIMP 711 10 753 10 18.0 .ENDS *$ *//////////////////////////////////////// *LM7131A Operational Amplifier Macro-Model *//////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM7131A/NS 3 2 4 5 6 * *Features *Internal Frequency Compensation *High Gain Bandwidth 70MHz *Single Supply Operation *******INPUT STAGE********* RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD1 DIN2 18 4 DMOD1 DIN3 5 19 DMOD1 DIN4 19 4 DMOD1 *******INTERNAL BIAS SECTIONS********* EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *******TEMP. DRIFT EFFECTS ********* FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD1 DTB 28 29 DMOD1 VTEMP 29 10 DC 0 *******CMRR and PSRR SECTIONS********* ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG *******INTERNAL GAIN STAGE********* FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 98 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 *******OUTPUT STAGE********* DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG *******CURRENT BALANCE SECTION********* FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *******VARIABLE SECTION********* FIN1 18 5 VTEMP 0.999975 FIN2 19 5 VTEMP 1.00002 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * C-M Input Capacitance RD1 18 11 5e+06 RD2 19 11 5e+06 * Diff. Input Resistance RCM 11 10 7.5e+06 * C-M. Input Resistance GOS 10 57 31 32 0.002 * Input Offset Voltage FCMR 10 57 VCMX 10 *Low Freq. CMRR FPSR 10 57 VPSX 632.456 *Low Freq. PSRR RSLOPE 4 5 7194.24 *Slope of Supply Current vs. Supp. Voltage GPWR 4 5 26 10 0.006383 *Quiescent Power Diss. ETEMP 27 28 32 33 0.101048 RVOS 31 32 MRVOS 1K .MODEL MRVOS RES (TC1=0.02) *Temp. Co. of Offset Voltage RIB 32 33 MRIB 1K .MODEL MRIB RES (TC1=0.000704658) *Temp. Co. of Input Bias Current RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) RCM1 39 41 316.228 CCM 41 10 1.59155e-11 * CMRR vs. Freq. RPSR1 44 45 316.228 CPSR 45 10 7.95775e-11 * PSRR vs. Freq. ELIMN 10 52 26 10 99.3 RDM 57 10 531.565 C2 57 557 6.30418e-12 RZERO 557 10 500 ECMP 40 97 26 10 1.5 ECMN 95 50 26 10 0.5 G2 58 10 57 10 0.00012 R2 58 10 15.677 GO2 59 10 58 10 1 *Slew-Rate and AC Resp. Settings EPOS 40 74 26 10 0.2 ENEG 75 50 26 10 0.15 *Output Voltage Swing Settings GSOURCE 74 73 33 34 0.00065 GSINK 72 75 33 34 0.0004 *Output Current Sink/Source Settings ROO 81 86 7.5 *Output Resistance Setting .MODEL DMOD1 D .MODEL NPN1 NPN (BF=100 IS=1e-15) .MODEL PNP1 PNP (BF=100 IS=1e-15) .ENDS * *$ *//////////////////////////////////////// *LM7131B Operational Amplifier Macro-Model *//////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM7131B/NS 3 2 4 5 6 * *Features *Internal Frequency Compensation *High Gain Bandwidth 70MHz *Single Supply Operation *******INPUT STAGE********* RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD1 DIN2 18 4 DMOD1 DIN3 5 19 DMOD1 DIN4 19 4 DMOD1 *******INTERNAL BIAS SECTIONS********* EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *******TEMP. DRIFT EFFECTS ********* FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD1 DTB 28 29 DMOD1 VTEMP 29 10 DC 0 ********CMRR and PSRR SECTIONS********* ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG *******INTERNAL GAIN STAGE********* FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 98 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 *******OUTPUT STAGE********* DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG *******CURRENT BALANCE SECTION********* FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *******VARIABLE SECTION********* FIN1 18 5 VTEMP 0.999975 FIN2 19 5 VTEMP 1.00002 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * C-M Input Capacitance RD1 18 11 5e+06 RD2 19 11 5e+06 * Diff. Input Resistance RCM 11 10 7.5e+06 * C-M. Input Resistance GOS 10 57 31 32 0.007 * Input Offset Voltage FCMR 10 57 VCMX 10 *Low Freq. CMRR FPSR 10 57 VPSX 632.456 *Low Freq. PSRR RSLOPE 4 5 7194.24 *Slope of Supply Current vs. Supp. Voltage GPWR 4 5 26 10 0.006383 *Quiescent Power Diss. ETEMP 27 28 32 33 0.101048 RVOS 31 32 MRVOS 1K .MODEL MRVOS RES (TC1=0.02) *Temp. Co. of Offset Voltage RIB 32 33 MRIB 1K .MODEL MRIB RES (TC1=0.000704658) *Temp. Co. of Input Bias Current RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) RCM1 39 41 316.228 CCM 41 10 1.59155e-11 * CMRR vs. Freq. RPSR1 44 45 316.228 CPSR 45 10 7.95775e-11 * PSRR vs. Freq. ELIMN 10 52 26 10 99.3 RDM 57 10 531.565 C2 57 557 6.30418e-12 RZERO 557 10 500 ECMP 40 97 26 10 1.5 ECMN 95 50 26 10 0.5 G2 58 10 57 10 0.00012 R2 58 10 15.677 GO2 59 10 58 10 1 *Slew-Rate and AC Resp. Settings EPOS 40 74 26 10 0.2 ENEG 75 50 26 10 0.15 *Output Voltage Swing Settings GSOURCE 74 73 33 34 0.00065 GSINK 72 75 33 34 0.0004 *Output Current Sink/Source Settings ROO 81 86 7.5 *Output Resistance Setting .MODEL DMOD1 D .MODEL NPN1 NPN (BF=100 IS=1e-15) .MODEL PNP1 PNP (BF=100 IS=1e-15) .ENDS * *$ *///////////////////////////////////////////////// *LM7171A Operational Amplifier Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM7171A/NS 3 2 4 5 6 * *Features *Very High Slew Rate *Wide Unity-Gain-Bandwidth Product *High CMRR ************************************** EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.001880e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=-7e-05) FIN1 18 5 VTEMP 0.983333 FIN2 19 5 VTEMP 1.01667 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 2.5e+06 RD2 19 11 2.5e+06 * Diff. Input Resistance RCM 11 10 4.375e+07 * Common Mode Input Resistance FCMR 10 57 VCMX 5.62341 * Low Freq. CMRR FPSR 10 57 VPSX 63.2456 * Low Freq. PSRR RSLOPE 4 5 25000 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.0053 * Quiescent Supply Current ETEMP 27 28 32 33 0.15005 RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.00452056) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.0015) RCM1 39 41 17.7828 CCM 41 10 1.59155e-12 * CMRR vs. Freq. RPSR1 44 45 100 CPSR 45 10 5.30516e-12 * PSRR vs. Freq. ELIMN 10 52 26 10 95.8517 RDM 57 10 37.3815 C2 57 10 1.64512e-11 ECMP 40 97 26 10 1.7 ECMN 95 50 26 10 1.7 G2 58 10 57 10 0.00435 R2 58 10 6.1497 GO2 59 10 58 10 10 * Avol and Slew-Rate Settings EPOS 40 74 26 10 1.4 ENEG 75 50 26 10 1.6 * Output Voltage Swing Settings GSOURCE 74 73 33 34 0.0014 GSINK 72 75 33 34 0.00133 * Output Current Settings ROO 81 86 12.5 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .ENDS *$ *///////////////////////////////////////////////// *LM7171B Operational Amplifier Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM7171B/NS 3 2 4 5 6 * *Features *Very High Slew Rate *Wide Unity-Gain-Bandwidth Product *High CMRR ************************************** EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.005860e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=-7e-05) FIN1 18 5 VTEMP 0.983333 FIN2 19 5 VTEMP 1.01667 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 2.5e+06 RD2 19 11 2.5e+06 * Diff. Input Resistance RCM 11 10 4.375e+07 * Common Mode Input Resistance FCMR 10 57 VCMX 5.62341 * Low Freq. CMRR FPSR 10 57 VPSX 63.2456 * Low Freq. PSRR RSLOPE 4 5 25000 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.0053 * Quiescent Supply Current ETEMP 27 28 32 33 0.15005 RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.00452056) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.0015) RCM1 39 41 17.7828 CCM 41 10 1.59155e-12 * CMRR vs. Freq. RPSR1 44 45 100 CPSR 45 10 5.30516e-12 * PSRR vs. Freq. ELIMN 10 52 26 10 95.8517 RDM 57 10 37.3815 C2 57 10 1.64512e-11 ECMP 40 97 26 10 1.7 ECMN 95 50 26 10 1.7 G2 58 10 57 10 0.00435 R2 58 10 6.1497 GO2 59 10 58 10 10 * Avol and Slew-Rate Settings EPOS 40 74 26 10 1.4 ENEG 75 50 26 10 1.6 * Output Voltage Swing Settings GSOURCE 74 73 33 34 0.0014 GSINK 72 75 33 34 0.00133 * Output Current Settings ROO 81 86 12.5 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .ENDS *$ *////////////////////////////////////////////////////////// *LM741 OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM741/NS 1 2 99 50 28 * *Features: *Improved performance over industry standards *Plug-in replacement for LM709,LM201,MC1439,748 *Input and output overload protection * ****************INPUT STAGE************** * IOS 2 1 20N *^Input offset current R1 1 3 250K R2 3 2 250K I1 4 50 100U R3 5 99 517 R4 6 99 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=2.55 MHz C4 5 6 60.3614P * ***********COMMON MODE EFFECT*********** * I2 99 50 1.6MA *^Quiescent supply current EOS 7 1 POLY(1) 16 49 1E-3 1 *Input offset voltage.^ R8 99 49 40K R9 49 50 40K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 1.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 9 5 6 2.1E-3 *Fp1=5 Hz R5 98 9 95.493MEG C3 98 9 333.33P * ***************POLE STAGE*************** * *Fp=30 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 5.3052E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=300 Hz G4 98 16 3 49 3.1623E-8 L2 98 17 530.5M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 450U 1 E1 99 23 99 15 1 R16 24 23 25 D5 26 24 DX V6 26 22 0.65V R17 23 25 25 D6 25 27 DX V7 22 27 0.65V V5 22 21 0.18V D4 21 15 DX V4 20 22 0.18V D3 15 20 DX L3 22 28 100P RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=625) * .ENDS *$ * //////////////////////////////////////////////////////// * LMC6001A Precision CMOS Single Operational Amplifier * //////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6001A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 350uV * Ultra low input current = 25fA * Slew rate = 1.5V/uS * Gain-bandwidth product = 1.3MHz * Supply current = 450uA * * NOTE: This CMOS electrometer simulates guaranteed (100% tested) * input offset voltage (VOS) & input bias current (IB) * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.634 Hz pole capacitor C3 98 9 9.715N * 1.1 MHz pole capacitor C4 6 5 13.95P * 4.98 MHz pole capacitor C5 98 15 31.9F * Drain-substrate capacitor C6 50 4 3P * 28.6 MHz pole capacitor C7 98 11 5.62F DP1 1 99 DA DP2 50 1 DD DP3 2 99 DB DP4 50 2 DC D1 9 8 DX D2 10 9 DX D3 18 20 DX D4 21 18 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 350U 1 EP 97 0 99 0 1.0 E1 97 19 99 18 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 G5 98 18 15 49 1U I1 99 4 33.46U I2 99 50 366.5U * Load dependent pole L1 22 28 80.4U * CMR lead inductor L2 16 17 73.1M * 3.30 MHz lead inductor L3 98 3 48.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.18K R4 6 50 5.18K R5 98 9 1E7 R8 99 49 50K R9 49 50 50K R10 18 3 1E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 70.7 * +Rout R17 23 25 80.3 * +Isc slope control R18 20 29 64K * -Isc slope control R19 21 30 130K R21 98 15 1E6 R22 22 28 636 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.713V V3 10 96 0.710V V4 29 22 1.170V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V * Input bias and offset current differences .MODEL DA D (IS=425FA) .MODEL DB D (IS=425FA) .MODEL DC D (IS=405FA) .MODEL DD D (IS=400FA) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.456 KP=7.0547E-4) .ENDS *$ * //////////////////////////////////////////////////// * LMC6001B Precision CMOS Single Operational Amplifier * //////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6001B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 800uV * Ultra low input current (max) = 100fA * Slew rate = 1.5V/uS * Gain-bandwidth product = 1.3MHz * Supply current = 450uA * * NOTE: This CMOS electrometer simulates guaranteed (100% tested) * input offset voltage (VOS) & input bias current (IB) * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.634 Hz pole capacitor C3 98 9 9.715N * 1.1 MHz pole capacitor C4 6 5 13.95P * 4.98 MHz pole capacitor C5 98 15 31.9F * Drain-substrate capacitor C6 50 4 3P * 28.6 MHz pole capacitor C7 98 11 5.62F DP1 1 99 DA DP2 50 1 DD DP3 2 99 DB DP4 50 2 DC D1 9 8 DX D2 10 9 DX D3 18 20 DX D4 21 18 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 800U 1 EP 97 0 99 0 1.0 E1 97 19 99 18 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 G5 98 18 15 49 1U I1 99 4 33.46U I2 99 50 366.5U * Load dependent pole L1 22 28 80.4U * CMR lead inductor L2 16 17 73.1M * 3.30 MHz lead inductor L3 98 3 48.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.18K R4 6 50 5.18K R5 98 9 1E7 R8 99 49 50K R9 49 50 50K R10 18 3 1E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 70.7 * +Rout R17 23 25 80.3 * +Isc slope control R18 20 29 64K * -Isc slope control R19 21 30 130K R21 98 15 1E6 R22 22 28 636 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.713V V3 10 96 0.710V V4 29 22 1.170V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V * Input bias and offset current differences .MODEL DA D (IS=500FA) .MODEL DB D (IS=500FA) .MODEL DC D (IS=405FA) .MODEL DD D (IS=400FA) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.456 KP=7.0547E-4) .ENDS *$ * ////////////////////////////////////////////////// * LMC6022 Low Power CMOS Dual Operational Amplifier * ////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6022/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 9mV * Ultra low input current = 40fA * Slew rate = .11V/uS * Gain-bandwidth product = 350kHz * Low supply current = 43uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 89.2E-3 Hz pole capacitor C3 98 9 178.2N * 604.1 kHz pole capacitor C4 6 5 1.68P * 1.98 MHz pole capacitor C5 98 15 80F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 15.8F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 9M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 37.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.750V V3 10 96 0.742V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * ////////////////////////////////////////////////// * LMC6024 Low Power CMOS Quad Operational Amplifier * ////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6024/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 9mV * Ultra low input current = 40fA * Slew rate = .11V/uS * Gain-bandwidth product = 350kHz * Low supply current = 40uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 89.2E-3 Hz pole capacitor C3 98 9 178.2N * 604.1 kHz pole capacitor C4 6 5 1.68P * 1.98 MHz pole capacitor C5 98 15 80F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 15.8F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 9M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 34.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.750V V3 10 96 0.742V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * //////////////////////////////////////// * LMC6032 CMOS Dual Operational Amplifier * //////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6032/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 9mV * Ultra low input current = 2fA * Slew rate = 1.1V/uS * Gain-bandwidth product = 1.4 MHz * Low supply current = 375uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 11.35N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 9M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 48.19U I2 99 50 308.1U * Load dependent pole L1 22 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.47K R4 6 50 5.47K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 900 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.721V V3 10 96 0.721V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.45 KP=7.0547E-4) .ENDS *$ * //////////////////////////////////////// * LMC6034 CMOS Quad Operational Amplifier * //////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6034/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 9mV * Ultra low input current = 2fA * Slew rate = 1.1V/uS * Gain-bandwidth product = 1.4 MHz * Low supply current = 375uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 11.35N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 9M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 48.19U I2 99 50 308.1U * Load dependent pole L1 22 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.47K R4 6 50 5.47K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 900 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.721V V3 10 96 0.721V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.45 KP=7.0547E-4) .ENDS *$ * ////////////////////////////////////////////////////// * LMC6041A CMOS Single Micropower Operational Amplifier * ////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6041A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 2fA * Slew rate = .02V/uS * Gain-bandwidth product = 75kHz * Low supply current = 14uA * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 75E-3 Hz pole capacitor C3 98 9 212N * 170.3 kHz pole capacitor C4 6 5 17.2P * 1.0 MHz pole capacitor C5 98 15 228.5F * Drain-substrate capacitor C6 50 4 10P * 1.0 MHz pole capacitor C7 98 11 110.7F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 8.89E-8 8.89E-8 I1 99 4 2.054U I2 99 50 11.9U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 148M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 26.3K R4 6 50 26.3K R5 98 9 1E7 R8 99 49 1.5E6 R9 49 50 1.5E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.707V V3 10 96 0.696V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////////////////// * LMC6041B CMOS Single Micropower Operational Amplifier * ///////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6041B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 6mV * Ultra low input current = 2fA * Slew rate = .02V/uS * Gain-bandwidth product = 75kHz * Low supply current = 14uA * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 75E-3 Hz pole capacitor C3 98 9 212N * 170.3 kHz pole capacitor C4 6 5 17.2P * 1.0 MHz pole capacitor C5 98 15 228.5F * Drain-substrate capacitor C6 50 4 10P * 1.0 MHz pole capacitor C7 98 11 110.7F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 6M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 8.89E-8 8.89E-8 I1 99 4 2.054U I2 99 50 11.9U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 148M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 26.3K R4 6 50 26.3K R5 98 9 1E7 R8 99 49 1.5E6 R9 49 50 1.5E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.707V V3 10 96 0.696V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * //////////////////////////////////////////////////// * LMC6042A CMOS Dual Micropower Operational Amplifier * //////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6042A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 2fA * Slew rate = .02V/uS * Gain-bandwidth product = 75kHz * Low supply current = 10uA * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 75E-3 Hz pole capacitor C3 98 9 212N * 170.3 kHz pole capacitor C4 6 5 17.2P * 1.0 MHz pole capacitor C5 98 15 228.5F * Drain-substrate capacitor C6 50 4 10P * 1.0 MHz pole capacitor C7 98 11 110.7F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 8.89E-8 8.89E-8 I1 99 4 2.054U I2 99 50 6.9U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 148M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 26.3K R4 6 50 26.3K R5 98 9 1E7 R8 99 49 1.5E6 R9 49 50 1.5E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.707V V3 10 96 0.696V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * /////////////////////////////////////////////////// * LMC6042B CMOS Dual Micropower Operational Amplifier * /////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6042B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 6mV * Ultra low input current = 2fA * Slew rate = .02V/uS * Gain-bandwidth product = 75kHz * Low supply current = 10uA * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 75E-3 Hz pole capacitor C3 98 9 212N * 170.3 kHz pole capacitor C4 6 5 17.2P * 1.0 MHz pole capacitor C5 98 15 228.5F * Drain-substrate capacitor C6 50 4 10P * 1.0 MHz pole capacitor C7 98 11 110.7F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 6M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 8.89E-8 8.89E-8 I1 99 4 2.054U I2 99 50 6.9U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 148M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 26.3K R4 6 50 26.3K R5 98 9 1E7 R8 99 49 1.5E6 R9 49 50 1.5E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.707V V3 10 96 0.696V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * //////////////////////////////////////////////////// * LMC6044A CMOS Quad Micropower Operational Amplifier * //////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6044A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 2fA * Slew rate = .02V/uS * Gain-bandwidth product = 75kHz * Low supply current = 10uA * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 75E-3 Hz pole capacitor C3 98 9 212N * 170.3 kHz pole capacitor C4 6 5 17.2P * 1.0 MHz pole capacitor C5 98 15 228.5F * Drain-substrate capacitor C6 50 4 10P * 1.0 MHz pole capacitor C7 98 11 110.7F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 8.89E-8 8.89E-8 I1 99 4 2.054U I2 99 50 6.9U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 148M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 26.3K R4 6 50 26.3K R5 98 9 1E7 R8 99 49 1.5E6 R9 49 50 1.5E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.707V V3 10 96 0.696V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * /////////////////////////////////////////////////// * LMC6044B CMOS Quad Micropower Operational Amplifier * /////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6044B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 6mV * Ultra low input current = 2fA * Slew rate = .02V/uS * Gain-bandwidth product = 75kHz * Low supply current = 10uA * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 75E-3 Hz pole capacitor C3 98 9 212N * 170.3 kHz pole capacitor C4 6 5 17.2P * 1.0 MHz pole capacitor C5 98 15 228.5F * Drain-substrate capacitor C6 50 4 10P * 1.0 MHz pole capacitor C7 98 11 110.7F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 6M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 8.89E-8 8.89E-8 I1 99 4 2.054U I2 99 50 6.9U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 148M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 26.3K R4 6 50 26.3K R5 98 9 1E7 R8 99 49 1.5E6 R9 49 50 1.5E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.707V V3 10 96 0.696V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * /////////////////////////////////////////////////////////////////// * LMC6061A Precision CMOS Single Micropower Operational Amplifier * /////////////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6061A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 350uV * Ultra low input current = 10fA * Slew rate = .035V/uS * Gain-bandwidth product = 100kHz * Low supply current = 20uA * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 25.5E-3 kHz pole capacitor C3 98 9 623.7N * 522 kHz pole capacitor C4 6 5 1.95P * 522 kHz pole capacitor C5 98 15 304.6F * Drain-substrate capacitor C6 50 4 23P * 522 kHz pole capacitor C7 98 11 303.8F C8 22 28 39.7P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 EOS 7 1 POLY(1) 16 49 350U 1 * Input offset voltage -| EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 I1 99 4 3.678U I2 99 50 14.4U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 485M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.25E6 R9 49 50 1.25E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 67.4 * +Rout R17 23 25 97.4 * +Isc slope control R18 20 29 24K * -Isc slope control R19 21 30 125K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.738V V3 10 96 0.742V V4 29 22 1.678V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.39 KP=7.0547E-4) .ENDS *$ * /////////////////////////////////////////////////////////////// * LMC6061B Precision CMOS Single Micropower Operational Amplifier * /////////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6061B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 800uV * Ultra low input current = 10fA * Slew rate = .035V/uS * Gain-bandwidth product = 100kHz * Low supply current = 20uA * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 25.5E-3 kHz pole capacitor C3 98 9 623.7N * 522 kHz pole capacitor C4 6 5 1.95P * 522 kHz pole capacitor C5 98 15 304.6F * Drain-substrate capacitor C6 50 4 23P * 522 kHz pole capacitor C7 98 11 303.8F C8 22 28 39.7P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 EOS 7 1 POLY(1) 16 49 800U 1 * Input offset voltage -| EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 I1 99 4 3.678U I2 99 50 14.4U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 485M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.25E6 R9 49 50 1.25E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 67.4 * +Rout R17 23 25 97.4 * +Isc slope control R18 20 29 24K * -Isc slope control R19 21 30 125K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.738V V3 10 96 0.742V V4 29 22 1.678V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.39 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////////////////////////////// * LMC6062A Precision CMOS Dual Micropower Operational Amplifier * ///////////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6062A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 350uV * Ultra low input current = 10fA * Slew rate = .035V/uS * Gain-bandwidth product = 100kHz * Low supply current = 16uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 25.5E-3 kHz pole capacitor C3 98 9 623.7N * 522 kHz pole capacitor C4 6 5 1.95P * 522 kHz pole capacitor C5 98 15 304.6F * Drain-substrate capacitor C6 50 4 23P * 522 kHz pole capacitor C7 98 11 303.8F C8 22 28 39.7P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 EOS 7 1 POLY(1) 16 49 350U 1 * Input offset voltage -| EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 I1 99 4 3.678U I2 99 50 10.4U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 485M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.25E6 R9 49 50 1.25E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 67.4 * +Rout R17 23 25 97.4 * +Isc slope control R18 20 29 24K * -Isc slope control R19 21 30 125K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.738V V3 10 96 0.742V V4 29 22 1.678V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.39 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////////////////////////// * LMC6062B Precision CMOS Dual Micropower Operational Amplifier * ///////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6062B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 800uV * Ultra low input current = 10fA * Slew rate = .035V/uS * Gain-bandwidth product = 100kHz * Low supply current = 16uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 25.5E-3 kHz pole capacitor C3 98 9 623.7N * 522 kHz pole capacitor C4 6 5 1.95P * 522 kHz pole capacitor C5 98 15 304.6F * Drain-substrate capacitor C6 50 4 23P * 522 kHz pole capacitor C7 98 11 303.8F C8 22 28 39.7P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 EOS 7 1 POLY(1) 16 49 800U 1 * Input offset voltage -| EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 I1 99 4 3.678U I2 99 50 10.4U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 485M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.25E6 R9 49 50 1.25E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 67.4 * +Rout R17 23 25 97.4 * +Isc slope control R18 20 29 24K * -Isc slope control R19 21 30 125K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.738V V3 10 96 0.742V V4 29 22 1.678V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.39 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////////////////////////////// * LMC6064A Precision CMOS Quad Micropower Operational Amplifier * ///////////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6064A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 350uV * Ultra low input current = 10fA * Slew rate = .035V/uS * Gain-bandwidth product = 100kHz * Low supply current = 16uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 25.5E-3 kHz pole capacitor C3 98 9 623.7N * 522 kHz pole capacitor C4 6 5 1.95P * 522 kHz pole capacitor C5 98 15 304.6F * Drain-substrate capacitor C6 50 4 23P * 522 kHz pole capacitor C7 98 11 303.8F C8 22 28 39.7P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 EOS 7 1 POLY(1) 16 49 350U 1 * Input offset voltage -| EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 I1 99 4 3.678U I2 99 50 10.4U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 485M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.25E6 R9 49 50 1.25E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 67.4 * +Rout R17 23 25 97.4 * +Isc slope control R18 20 29 24K * -Isc slope control R19 21 30 125K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.738V V3 10 96 0.742V V4 29 22 1.678V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.39 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////////////////////////// * LMC6064B Precision CMOS Quad Micropower Operational Amplifier * ///////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6064B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 800uV * Ultra low input current = 10fA * Slew rate = .035V/uS * Gain-bandwidth product = 100kHz * Low supply current = 16uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 25.5E-3 kHz pole capacitor C3 98 9 623.7N * 522 kHz pole capacitor C4 6 5 1.95P * 522 kHz pole capacitor C5 98 15 304.6F * Drain-substrate capacitor C6 50 4 23P * 522 kHz pole capacitor C7 98 11 303.8F C8 22 28 39.7P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 EOS 7 1 POLY(1) 16 49 800U 1 * Input offset voltage -| EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 I1 99 4 3.678U I2 99 50 10.4U * Load dependent pole L1 22 28 15.6M * CMRR zero L2 16 17 485M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.25E6 R9 49 50 1.25E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 67.4 * +Rout R17 23 25 97.4 * +Isc slope control R18 20 29 24K * -Isc slope control R19 21 30 125K R21 98 15 1E6 R22 22 28 7K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.738V V3 10 96 0.742V V4 29 22 1.678V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.39 KP=7.0547E-4) .ENDS *$ * //////////////////////////////////////////////////////// * LMC6081A Precision CMOS Single Operational Amplifier * //////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6081A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 350uV * Ultra low input current = 10fA * Slew rate = 1.5V/uS * Gain-bandwidth product = 1.3MHz * Supply current = 450uA * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.634 Hz pole capacitor C3 98 9 9.715N * 1.1 MHz pole capacitor C4 6 5 13.95P * 4.98 MHz pole capacitor C5 98 15 31.9F * Drain-substrate capacitor C6 50 4 3P * 28.6 MHz pole capacitor C7 98 11 5.62F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 18 20 DX D4 21 18 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 350U 1 EP 97 0 99 0 1.0 E1 97 19 99 18 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 G5 98 18 15 49 1U I1 99 4 33.46U I2 99 50 366.5U * Load dependent pole L1 22 28 80.4U * CMR lead inductor L2 16 17 73.1M * 3.30 MHz lead inductor L3 98 3 48.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.18K R4 6 50 5.18K R5 98 9 1E7 R8 99 49 50K R9 49 50 50K R10 18 3 1E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 70.7 * +Rout R17 23 25 80.3 * +Isc slope control R18 20 29 64K * -Isc slope control R19 21 30 130K R21 98 15 1E6 R22 22 28 636 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.713V V3 10 96 0.710V V4 29 22 1.170V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.456 KP=7.0547E-4) .ENDS *$ * //////////////////////////////////////////////////// * LMC6081B Precision CMOS Single Operational Amplifier * //////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6081B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 800uV * Ultra low input current = 10fA * Slew rate = 1.5V/uS * Gain-bandwidth product = 1.3MHz * Supply current = 450uA * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.634 Hz pole capacitor C3 98 9 9.715N * 1.1 MHz pole capacitor C4 6 5 13.95P * 4.98 MHz pole capacitor C5 98 15 31.9F * Drain-substrate capacitor C6 50 4 3P * 28.6 MHz pole capacitor C7 98 11 5.62F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 18 20 DX D4 21 18 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 800U 1 EP 97 0 99 0 1.0 E1 97 19 99 18 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 G5 98 18 15 49 1U I1 99 4 33.46U I2 99 50 366.5U * Load dependent pole L1 22 28 80.4U * CMR lead inductor L2 16 17 73.1M * 3.30 MHz lead inductor L3 98 3 48.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.18K R4 6 50 5.18K R5 98 9 1E7 R8 99 49 50K R9 49 50 50K R10 18 3 1E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 70.7 * +Rout R17 23 25 80.3 * +Isc slope control R18 20 29 64K * -Isc slope control R19 21 30 130K R21 98 15 1E6 R22 22 28 636 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.713V V3 10 96 0.710V V4 29 22 1.170V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.456 KP=7.0547E-4) .ENDS *$ * ////////////////////////////////////////////////////// * LMC6082A Precision CMOS Dual Operational Amplifier * ////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6082A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 350uV * Ultra low input current = 10fA * Slew rate = 1.5V/uS * Gain-bandwidth product = 1.3MHz * Supply current = 450uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.634 Hz pole capacitor C3 98 9 9.715N * 1.1 MHz pole capacitor C4 6 5 13.95P * 4.98 MHz pole capacitor C5 98 15 31.9F * Drain-substrate capacitor C6 50 4 3P * 28.6 MHz pole capacitor C7 98 11 5.62F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 18 20 DX D4 21 18 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 350U 1 EP 97 0 99 0 1.0 E1 97 19 99 18 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 G5 98 18 15 49 1U I1 99 4 33.46U I2 99 50 366.5U * Load dependent pole L1 22 28 80.4U * CMR lead inductor L2 16 17 73.1M * 3.30 MHz lead inductor L3 98 3 48.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.18K R4 6 50 5.18K R5 98 9 1E7 R8 99 49 50K R9 49 50 50K R10 18 3 1E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 70.7 * +Rout R17 23 25 80.3 * +Isc slope control R18 20 29 64K * -Isc slope control R19 21 30 130K R21 98 15 1E6 R22 22 28 636 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.713V V3 10 96 0.710V V4 29 22 1.170V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.456 KP=7.0547E-4) .ENDS *$ * ////////////////////////////////////////////////// * LMC6082B Precision CMOS Dual Operational Amplifier * ////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6082B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 800uV * Ultra low input current = 10fA * Slew rate = 1.5V/uS * Gain-bandwidth product = 1.3MHz * Supply current = 450uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.634 Hz pole capacitor C3 98 9 9.715N * 1.1 MHz pole capacitor C4 6 5 13.95P * 4.98 MHz pole capacitor C5 98 15 31.9F * Drain-substrate capacitor C6 50 4 3P * 28.6 MHz pole capacitor C7 98 11 5.62F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 18 20 DX D4 21 18 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 800U 1 EP 97 0 99 0 1.0 E1 97 19 99 18 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 G5 98 18 15 49 1U I1 99 4 33.46U I2 99 50 366.5U * Load dependent pole L1 22 28 80.4U * CMR lead inductor L2 16 17 73.1M * 3.30 MHz lead inductor L3 98 3 48.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.18K R4 6 50 5.18K R5 98 9 1E7 R8 99 49 50K R9 49 50 50K R10 18 3 1E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 70.7 * +Rout R17 23 25 80.3 * +Isc slope control R18 20 29 64K * -Isc slope control R19 21 30 130K R21 98 15 1E6 R22 22 28 636 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.713V V3 10 96 0.710V V4 29 22 1.170V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.456 KP=7.0547E-4) .ENDS *$ * ////////////////////////////////////////////////////// * LMC6084A Precision CMOS Quad Operational Amplifier * ////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6084A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 350uV * Ultra low input current = 10fA * Slew rate = 1.5V/uS * Gain-bandwidth product = 1.3MHz * Supply current = 450uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.634 Hz pole capacitor C3 98 9 9.715N * 1.1 MHz pole capacitor C4 6 5 13.95P * 4.98 MHz pole capacitor C5 98 15 31.9F * Drain-substrate capacitor C6 50 4 3P * 28.6 MHz pole capacitor C7 98 11 5.62F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 18 20 DX D4 21 18 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 350U 1 EP 97 0 99 0 1.0 E1 97 19 99 18 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 G5 98 18 15 49 1U I1 99 4 33.46U I2 99 50 366.5U * Load dependent pole L1 22 28 80.4U * CMR lead inductor L2 16 17 73.1M * 3.30 MHz lead inductor L3 98 3 48.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.18K R4 6 50 5.18K R5 98 9 1E7 R8 99 49 50K R9 49 50 50K R10 18 3 1E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 70.7 * +Rout R17 23 25 80.3 * +Isc slope control R18 20 29 64K * -Isc slope control R19 21 30 130K R21 98 15 1E6 R22 22 28 636 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.713V V3 10 96 0.710V V4 29 22 1.170V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.456 KP=7.0547E-4) .ENDS *$ * ////////////////////////////////////////////////// * LMC6084B Precision CMOS Quad Operational Amplifier * ////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6084B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 800uV * Ultra low input current = 10fA * Slew rate = 1.5V/uS * Gain-bandwidth product = 1.3MHz * Supply current = 450uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.634 Hz pole capacitor C3 98 9 9.715N * 1.1 MHz pole capacitor C4 6 5 13.95P * 4.98 MHz pole capacitor C5 98 15 31.9F * Drain-substrate capacitor C6 50 4 3P * 28.6 MHz pole capacitor C7 98 11 5.62F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 18 20 DX D4 21 18 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 800U 1 EP 97 0 99 0 1.0 E1 97 19 99 18 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 1.26E-8 1.26E-8 G5 98 18 15 49 1U I1 99 4 33.46U I2 99 50 366.5U * Load dependent pole L1 22 28 80.4U * CMR lead inductor L2 16 17 73.1M * 3.30 MHz lead inductor L3 98 3 48.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.18K R4 6 50 5.18K R5 98 9 1E7 R8 99 49 50K R9 49 50 50K R10 18 3 1E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 70.7 * +Rout R17 23 25 80.3 * +Isc slope control R18 20 29 64K * -Isc slope control R19 21 30 130K R21 98 15 1E6 R22 22 28 636 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.713V V3 10 96 0.710V V4 29 22 1.170V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=2.5E-14) .MODEL DB D (IS=2.0E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.456 KP=7.0547E-4) .ENDS *$ *////////////////////////////////////////////////////////// *LMC6462A CMOS Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6462A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 150fA *Slew rate = 0.02V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 6.9U M1 5 2 4 99 MOSFET R3 5 50 3.79K M2 6 7 4 99 MOSFET R4 6 50 3.79K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DC DP3 2 99 DB DP4 50 2 DC *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 50 99 6.8U *^Quiescent current EOS 7 1 POLY(1) 16 49 0.5E-3 1 *Offset voltage.......... R8 99 49 250K R9 49 50 250K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P **********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 97 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 180 RN16 123 124 130 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 350K VN4 129 28 .27 DN4 121 115 DX RN19 130 121 350K VN5 28 130 .27 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 280P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.075E-12) .MODEL DB D(IS=1.15E-12) .MODEL DC D(IS=1E-12) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS *$ *////////////////////////////////////////////////////////// *LMC6462B CMOS Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6462B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 150fA *Slew rate = 0.02V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 6.9U M1 5 2 4 99 MOSFET R3 5 50 3.79K M2 6 7 4 99 MOSFET R4 6 50 3.79K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DC DP3 2 99 DB DP4 50 2 DC *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 50 99 6.8U *^Quiescent current EOS 7 1 POLY(1) 16 49 3.0E-3 1 *Offset voltage.......... R8 99 49 250K R9 49 50 250K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P **********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 97 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 180 RN16 123 124 130 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 350K VN4 129 28 .27 DN4 121 115 DX RN19 130 121 350K VN5 28 130 .27 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 280P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.075E-12) .MODEL DB D(IS=1.15E-12) .MODEL DC D(IS=1E-12) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6464A CMOS Quad OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6464A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 150fA *Slew rate = 0.02V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 6.9U M1 5 2 4 99 MOSFET R3 5 50 3.79K M2 6 7 4 99 MOSFET R4 6 50 3.79K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DC DP3 2 99 DB DP4 50 2 DC *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 50 99 6.8U *^Quiescent current EOS 7 1 POLY(1) 16 49 0.5E-3 1 *Offset voltage.......... R8 99 49 250K R9 49 50 250K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P **********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 97 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 180 RN16 123 124 130 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 350K VN4 129 28 .27 DN4 121 115 DX RN19 130 121 350K VN5 28 130 .27 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 280P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.075E-12) .MODEL DB D(IS=1.15E-12) .MODEL DC D(IS=1E-12) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS *$ *////////////////////////////////////////////////////////// *LMC6464B CMOS Quad OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6464B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 150fA *Slew rate = 0.02V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 6.9U M1 5 2 4 99 MOSFET R3 5 50 3.79K M2 6 7 4 99 MOSFET R4 6 50 3.79K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DC DP3 2 99 DB DP4 50 2 DC *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 50 99 6.8U *^Quiescent current EOS 7 1 POLY(1) 16 49 3.0E-3 1 *Offset voltage.......... R8 99 49 250K R9 49 50 250K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P **********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 97 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 180 RN16 123 124 130 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 350K VN4 129 28 .27 DN4 121 115 DX RN19 130 121 350K VN5 28 130 .27 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 280P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.075E-12) .MODEL DB D(IS=1.15E-12) .MODEL DC D(IS=1E-12) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6482A CMOS Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6482A/NS 1 2 99 50 40 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 10fA *Slew rate = 1.2V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 17U M1 5 2 4 99 MOSFET R3 5 50 5.651K M2 6 7 4 99 MOSFET R4 6 50 5.651K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DB DP3 2 99 DB DP4 50 2 DA *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 99 50 420.5U *^Quiescent current EOS 7 1 POLY(1) 16 49 .75E-3 1 *Offset voltage..........^ R8 99 49 40K R9 49 50 40K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 99 DX V5 40 31 .77 D6 50 31 DX *Fp1=2.343 Hz C3 29 39 17P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=2E-14) .MODEL DB D(IS=1E-14) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS *$ *////////////////////////////////////////////////////////// *LMC6484A CMOS Quad OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6484A/NS 1 2 99 50 40 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 10fA *Slew rate = 1.2V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 17U M1 5 2 4 99 MOSFET R3 5 50 5.651K M2 6 7 4 99 MOSFET R4 6 50 5.651K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DB DP3 2 99 DB DP4 50 2 DA *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 99 50 420.5U *^Quiescent current EOS 7 1 POLY(1) 16 49 .75E-3 1 *Offset voltage..........^ R8 99 49 40K R9 49 50 40K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 99 DX V5 40 31 .77 D6 50 31 DX *Fp1=2.343 Hz C3 29 39 17P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=2E-14) .MODEL DB D(IS=1E-14) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS *$ *////////////////////////////////////////////////////////// *LMC6492A CMOS Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6492A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 10fA *Slew rate = 1.2V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 17U M1 5 2 4 99 MOSFET R3 5 50 5.651K M2 6 7 4 99 MOSFET R4 6 50 5.651K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 99 50 420.5U *^Quiescent current EOS 7 1 POLY(1) 16 49 3.0E-3 1 *Offset voltage.......... R8 99 49 40K R9 49 50 40K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 180 RN16 123 124 130 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 350K VN4 129 28 .27 DN4 121 115 DX RN19 130 121 350K VN5 28 130 .27 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 280P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.1E-13) .MODEL DB D(IS=1.15E-13) .MODEL DC D(IS=1E-13) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6492B CMOS Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6492B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 10fA *Slew rate = 1.2V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 17U M1 5 2 4 99 MOSFET R3 5 50 5.651K M2 6 7 4 99 MOSFET R4 6 50 5.651K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 99 50 420.5U *^Quiescent current EOS 7 1 POLY(1) 16 49 6.0E-3 1 *Offset voltage.......... R8 99 49 40K R9 49 50 40K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 180 RN16 123 124 130 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 350K VN4 129 28 .27 DN4 121 115 DX RN19 130 121 350K VN5 28 130 .27 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 280P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.1E-13) .MODEL DB D(IS=1.15E-13) .MODEL DC D(IS=1E-13) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6494A CMOS Quad OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6494A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 10fA *Slew rate = 1.2V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 17U M1 5 2 4 99 MOSFET R3 5 50 5.651K M2 6 7 4 99 MOSFET R4 6 50 5.651K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 99 50 420.5U *^Quiescent current EOS 7 1 POLY(1) 16 49 3.0E-3 1 *Offset voltage.......... R8 99 49 40K R9 49 50 40K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 180 RN16 123 124 130 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 350K VN4 129 28 .27 DN4 121 115 DX RN19 130 121 350K VN5 28 130 .27 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 280P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.1E-13) .MODEL DB D(IS=1.15E-13) .MODEL DC D(IS=1E-13) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6494B CMOS Quad OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6494B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 10fA *Slew rate = 1.2V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 17U M1 5 2 4 99 MOSFET R3 5 50 5.651K M2 6 7 4 99 MOSFET R4 6 50 5.651K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 99 50 420.5U *^Quiescent current EOS 7 1 POLY(1) 16 49 6.0E-3 1 *Offset voltage.......... R8 99 49 40K R9 49 50 40K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 180 RN16 123 124 130 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 350K VN4 129 28 .27 DN4 121 115 DX RN19 130 121 350K VN5 28 130 .27 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 280P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.1E-13) .MODEL DB D(IS=1.15E-13) .MODEL DC D(IS=1E-13) .MODEL DX D(IS=1E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS * *$ * ////////////////////////////////////////////////// * LMC6572A Low Power CMOS Dual Operational Amplifier * ////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6572A/NS 1 2 99 50 28 * * USER WARNING: Ultra-low input bias current REQUIRES that * SPICE option GMIN=1E-16 or smaller! * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 20fA * Slew rate = .09V/uS * Gain-bandwidth product = 220kHz * Low supply current = 40uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 60E-3 Hz pole capacitor C3 98 9 247N * 400 kHz pole capacitor C4 6 5 4.75P * 1.3 MHz pole capacitor C5 98 15 120F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 7.6F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 11 8 DX D2 10 11 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 37.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 37.6K R4 6 50 37.6K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 2.081E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.790V V3 10 96 0.782V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-1.74 KP=7.0547E-4) .ENDS *$ * ////////////////////////////////////////////////// * LMC6572B Low Power CMOS Dual Operational Amplifier * ////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6572B/NS 1 2 99 50 28 * * USER WARNING: Ultra-low input bias current REQUIRES that * SPICE option GMIN=1E-16 or smaller! * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 7mV * Ultra low input current = 20fA * Slew rate = .09V/uS * Gain-bandwidth product = 220kHz * Low supply current = 40uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 60E-3 Hz pole capacitor C3 98 9 247N * 400 kHz pole capacitor C4 6 5 4.75P * 1.3 MHz pole capacitor C5 98 15 120F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 7.6F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 11 8 DX D2 10 11 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 7M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 37.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 37.6K R4 6 50 37.6K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 2.081E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.790V V3 10 96 0.782V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-1.74 KP=7.0547E-4) .ENDS *$ * ////////////////////////////////////////////////// * LMC6574A Low Power CMOS Quad Operational Amplifier * ////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6574A/NS 1 2 99 50 28 * * USER WARNING: Ultra-low input bias current REQUIRES that * SPICE option GMIN=1E-16 or smaller! * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 20fA * Slew rate = .09V/uS * Gain-bandwidth product = 220kHz * Low supply current = 40uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 60E-3 Hz pole capacitor C3 98 9 247N * 400 kHz pole capacitor C4 6 5 4.75P * 1.3 MHz pole capacitor C5 98 15 120F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 7.6F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 11 8 DX D2 10 11 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 37.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 37.6K R4 6 50 37.6K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 2.081E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.790V V3 10 96 0.782V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-1.74 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////////////// * LMC6574B Low Power CMOS Quad Operational Amplifier * ///////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6574B/NS 1 2 99 50 28 * * USER WARNING: Ultra-low input bias current REQUIRES that * SPICE option GMIN=1E-16 or smaller! * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 7mV * Ultra low input current = 20fA * Slew rate = .09V/uS * Gain-bandwidth product = 220kHz * Low supply current = 40uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 60E-3 Hz pole capacitor C3 98 9 247N * 400 kHz pole capacitor C4 6 5 4.75P * 1.3 MHz pole capacitor C5 98 15 120F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 7.6F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 11 8 DX D2 10 11 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 7M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 37.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 37.6K R4 6 50 37.6K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 2.081E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.790V V3 10 96 0.782V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-1.74 KP=7.0547E-4) .ENDS *$ *////////////////////////////////////////////////////////// *LMC6582A CMOS DUAL OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6582A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 1mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * Power is for one amplifier * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 1M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 11.5U I2 99 50 680U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 99 49 25K R9 49 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K VA1 22 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6582B CMOS DUAL OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6582B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * Power is for one amplifier * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 11.5U I2 99 50 680U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 99 49 25K R9 49 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K VA1 22 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6584A CMOS QUAD OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6584A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 1mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * Power is for one amplifier * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 1M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 11.5U I2 99 50 680U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 99 49 25K R9 49 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K VA1 22 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6584B CMOS QUAD OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC6584B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * Power is for one amplifier * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 11.5U I2 99 50 680U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 99 49 25K R9 49 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K VA1 22 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .ENDS * *$ * /////////////////////////////////////////// * LMC660 CMOS Quad Operational Amplifier * /////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC660A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 2fA * Slew rate = 1.1V/uS * Gain-bandwidth product = 1.4 MHz * Low supply current = 375uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 11.35N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 48.19U I2 99 50 308.1U * Load dependent pole L1 22 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.47K R4 6 50 5.47K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 900 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.721V V3 10 96 0.721V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.45 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////// * LMC660B CMOS Quad Operational Amplifier * ///////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC660B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 6mV * Ultra low input current = 2fA * Slew rate = 1.1V/uS * Gain-bandwidth product = 1.4 MHz * Low supply current = 375uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 11.35N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 6M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 48.19U I2 99 50 308.1U * Load dependent pole L1 22 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.47K R4 6 50 5.47K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 900 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.721V V3 10 96 0.721V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.45 KP=7.0547E-4) .ENDS *$ * /////////////////////////////////////////// * LMC662 CMOS Dual Operational Amplifier * /////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC662A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 2fA * Slew rate = 1.1V/uS * Gain-bandwidth product = 1.4 MHz * Low supply current = 375uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 11.35N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 48.19U I2 99 50 308.1U * Load dependent pole L1 22 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.47K R4 6 50 5.47K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 900 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.721V V3 10 96 0.721V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.45 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////// * LMC662 CMOS Dual Operational Amplifier * ///////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LMC662B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 6mV * Ultra low input current = 2fA * Slew rate = 1.1V/uS * Gain-bandwidth product = 1.4 MHz * Low supply current = 375uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 11.35N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 6M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 48.19U I2 99 50 308.1U * Load dependent pole L1 22 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 5.47K R4 6 50 5.47K R5 98 9 1E7 R8 99 49 133.3K R9 49 50 133.3K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 900 VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.721V V3 10 96 0.721V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=1.3E-14) .MODEL DB D (IS=1.2E-14) .MODEL DX D (IS=1.0E-14) .MODEL MX PMOS (VTO=-2.45 KP=7.0547E-4) .ENDS *$ *////////////////////////////////////////////////////////// *LMC6681A CMOS Single OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | Shutdown * | | | | | | .SUBCKT LMC6681A/NS 1 2 99 50 28 33 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 1mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P CSD1 41 40 100P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 1M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 G5 99 4 39 45 11.5U G6 99 50 39 45 340U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX M3 41 33 40 40 MN1 M4 45 41 39 39 MP2 M5 45 41 40 40 MN3 R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 42 44 25K R9 44 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K R24 99 49 10MEG R25 49 50 10MEG R26 33 50 20MEG R27 39 41 250K S1 99 42 41 49 SX S2 22 36 41 49 SX VA1 36 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V V9 39 49 1 V10 49 40 1 * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MP2 PMOS (VTO=0, KP=7.0547E-4) .MODEL MN3 NMOS (VTO=0, KP=7.0547E-4) .MODEL SX VSWITCH (RON=1, ROFF=1E+8, VON=0.01, VOFF=-0.01) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6681B CMOS Single OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | Shutdown * | | | | | | .SUBCKT LMC6681B/NS 1 2 99 50 28 33 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P CSD1 41 40 100P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 G5 99 4 39 45 11.5U G6 99 50 39 45 340U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX M3 41 33 40 40 MN1 M4 45 41 39 39 MP2 M5 45 41 40 40 MN3 R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 42 44 25K R9 44 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K R24 99 49 10MEG R25 49 50 10MEG R26 33 50 20MEG R27 39 41 250K S1 99 42 41 49 SX S2 22 36 41 49 SX VA1 36 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V V9 39 49 1 V10 49 40 1 * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MP2 PMOS (VTO=0, KP=7.0547E-4) .MODEL MN3 NMOS (VTO=0, KP=7.0547E-4) .MODEL SX VSWITCH (RON=1, ROFF=1E+8, VON=0.01, VOFF=-0.01) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6682A CMOS DUAL OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | Shutdown * | | | | | | .SUBCKT LMC6682A/NS 1 2 99 50 28 33 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 1mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * Power is for one amplifier * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P CSD1 41 40 100P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 1M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 G5 99 4 39 45 11.5U G6 99 50 39 45 340U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX M3 41 33 40 40 MN1 M4 45 41 39 39 MP2 M5 45 41 40 40 MN3 R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 42 44 25K R9 44 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K R24 99 49 10MEG R25 49 50 10MEG R26 33 50 20MEG R27 39 41 250K S1 99 42 41 49 SX S2 22 36 41 49 SX VA1 36 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V V9 39 49 1 V10 49 40 1 * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MP2 PMOS (VTO=0, KP=7.0547E-4) .MODEL MN3 NMOS (VTO=0, KP=7.0547E-4) .MODEL SX VSWITCH (RON=1, ROFF=1E+8, VON=0.01, VOFF=-0.01) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6682B CMOS DUAL OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | Shutdown * | | | | | | .SUBCKT LMC6682B/NS 1 2 99 50 28 33 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * Power is for one amplifier * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P CSD1 41 40 100P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 G5 99 4 39 45 11.5U G6 99 50 39 45 340U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX M3 41 33 40 40 MN1 M4 45 41 39 39 MP2 M5 45 41 40 40 MN3 R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 42 44 25K R9 44 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K R24 99 49 10MEG R25 49 50 10MEG R26 33 50 20MEG R27 39 41 250K S1 99 42 41 49 SX S2 22 36 41 49 SX VA1 36 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V V9 39 49 1 V10 49 40 1 * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MP2 PMOS (VTO=0, KP=7.0547E-4) .MODEL MN3 NMOS (VTO=0, KP=7.0547E-4) .MODEL SX VSWITCH (RON=1, ROFF=1E+8, VON=0.01, VOFF=-0.01) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6684A CMOS QUAD OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | Shutdown * | | | | | | .SUBCKT LMC6684A/NS 1 2 99 50 28 33 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 1mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * Power is for one amplifier * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P CSD1 41 40 100P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 1M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 G5 99 4 39 45 11.5U G6 99 50 39 45 340U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX M3 41 33 40 40 MN1 M4 45 41 39 39 MP2 M5 45 41 40 40 MN3 R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 42 44 25K R9 44 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K R24 99 49 10MEG R25 49 50 10MEG R26 33 50 20MEG R27 39 41 250K S1 99 42 41 49 SX S2 22 36 41 49 SX VA1 36 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V V9 39 49 1 V10 49 40 1 * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MP2 PMOS (VTO=0, KP=7.0547E-4) .MODEL MN3 NMOS (VTO=0, KP=7.0547E-4) .MODEL SX VSWITCH (RON=1, ROFF=1E+8, VON=0.01, VOFF=-0.01) .ENDS * *$ *////////////////////////////////////////////////////////// *LMC6684B CMOS QUAD OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | Shutdown * | | | | | | .SUBCKT LMC6684B/NS 1 2 99 50 28 33 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV@5V * Slew rate = 1.2V/uS * Gain-bandwidth product = 1.2 MHz * Amplifier shut-down * Power is for one amplifier * * NOTE: - Model is for single device only and simulated. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 1.4 Hz pole capacitor C3 98 9 5.85N * 2.95 MHz pole capacitor C4 6 5 4.93P * Drain-substrate capacitor C6 50 4 10P * 35 MHz pole capacitor C7 98 11 4.54F COUT 28 0 10P CSD1 41 40 100P DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 29 22 DX D4 22 30 DX D5 22 26 DX D6 27 22 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX D11 31 32 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage -| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 23 99 15 1.0 E2 18 7 32 97 1E-3 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 G5 99 4 39 45 11.5U G6 99 50 39 45 340U * Load dependent pole L1 19 28 40.4U * CMR lead L2 16 17 7.95M M1 5 2 4 99 MPX M2 6 18 4 99 MPX M3 41 33 40 40 MN1 M4 45 41 39 39 MP2 M5 45 41 40 40 MN3 R3 5 50 3.60K R4 6 50 3.60K R5 98 9 1E7 R8 42 44 25K R9 44 50 25K R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 55 * +Rout R17 23 25 55 * +Isc slope control R18 15 20 1MEG * -Isc slope control R19 21 15 400K R21 98 15 1E6 R22 19 28 900 R23 32 97 100K R24 99 49 10MEG R25 49 50 10MEG R26 33 50 20MEG R27 39 41 250K S1 99 42 41 49 SX S2 22 36 41 49 SX VA1 36 19 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.66V V3 10 96 0.66V V4 20 29 0.13V V5 30 21 0.13V V6 24 26 0.63V V7 27 25 0.63V V8 31 96 3.6V V9 39 49 1 V10 49 40 1 * .MODEL DA D (IS=250E-15) .MODEL DB D (IS=175E-15) .MODEL DX D (IS=100E-15) .MODEL MPX PMOS (VTO=-.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MN1 NMOS (VTO=.6 KP=7.0547E-4 GAMMA=1.1) .MODEL MP2 PMOS (VTO=0, KP=7.0547E-4) .MODEL MN3 NMOS (VTO=0, KP=7.0547E-4) .MODEL SX VSWITCH (RON=1, ROFF=1E+8, VON=0.01, VOFF=-0.01) .ENDS * *$ **///////////////////////////////////////////////// *LMC6762A CMOS Comparator Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | output * | | | positive power supply * | | | | negative power supply * | | | | | * | | | | | .SUBCKT LMC6762A/NS 3 2 6 4 5 * *Features *Low Power Consumption *Wide Range of Supply *4us Propagation delay at 100mv Overdrive * *----- input satge ----- RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 FIN1 18 5 VTEMP 0.75 FIN2 19 5 VTEMP 1.25 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 5e+10 RD2 19 11 5e+10 * Diff. Input Resistance RCM 11 10 9.975e+12 * Common Mode Input Resistance *----- supply current ------ EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG RSLOPE 4 5 1e+12 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.000006 * Quiescent Supply Current *----- VOS bridge ----- EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K RAX 122 10 MRAX 1.009000e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=0) *----- delay stage ----- RX8 40 815 10K RY8 815 50 5K RBA8 815 50 5K RBB8 815 811 1K EIN8 810 811 3 2 -1 EVOSS 814 811 122 121 1 *=== RCA8 40 812 1K RCB8 40 813 1K DDA8 812 813 DDEL1 DDB8 813 812 DDEL2 * Delay Time Settings CDB8 813 812 10P RCDB8 813 812 1MEG FSET8 809 50 VSENS1 1 CCC 809 50 5P QDN1 812 810 809 NPNX QDN2 813 814 809 NPNX .MODEL NPNX NPN (BF=100 RE=25) .MODEL DDEL1 D (IS=1e-6 TT=5.2U N=1.4 ) .MODEL DDEL2 D (IS=4e-6 TT=2.5U N=0.8 ) GDM 10 57 812 813 1 *----- start-up ----- ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *----- temp. Coef. ----- FSET 10 31 VSENS1 1.0 RVOS 31 32 1K RIB 32 33 MRIB 1K .MODEL MRIB RES (TC1=0.0036363) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) R001 34 10 1K *----- CMRR ----- ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG RCM1 39 41 1778.28 CCM 41 10 1.59155e-10 * CMRR vs. Freq. *----- PSRR ----- EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG RPSR1 44 45 1000 CPSR 45 10 1.59155e-10 * PSRR vs. Freq. *----- IB temp. ----- FTEMP 10 27 VSENS1 1.0 ETEMP 27 28 32 33 0.6184 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 *----- Out Curr. sense & set ----- FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *----- comm. input sense ----- DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 ECMP 40 97 26 10 0.2 ECMN 95 50 26 10 0.1 *----- inter-stage ----- GOS 10 57 122 121 1.0 GOSD 10 57 11 0 0.14m FCMR 10 57 VCMX 1200 * Low Freq. CMRR FPSR 10 57 VPSX 1450 * Low Freq. PSRR FCXX 57 10 VCXX 100 RDM 57 10 72552 C2 57 10 1.09683e-14 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 129.3 ELIMN 10 52 26 10 199.3 * G2 58 10 57 10 1.0e-06 R2 58 10 13.7832 GO2 59 10 58 10 18 * Avol and Slew-Rate Settings RO2 59 10 1K DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 *----- output stage ----- GO3 10 71 59 10 1 RO3 71 10 1 RDN2 710 71 100 RDP 720 72 100 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 RNO 78 81 1 RPO 79 81 1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 C1 58 59 1e-10 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG EPOS 40 74 26 10 0.05 ENEG 75 50 26 10 0.04 * Output Voltage Swing Settings GSOURCE 74 73 33 34 0.00032 GSINK 72 75 33 34 0.00045 * Output Current Settings ROO 81 86 20 .MODEL DMOD1 D .MODEL DMOD2 D (IS=1e-17) .MODEL NPN1 NPN (BF=100 IS=1e-15) .MODEL PNP1 PNP (BF=100 IS=1e-15) RA 73 40 10e6 RB 72 50 10e6 RC 72 73 10e6 RD 10 57 10e6 RE 24 10 10e6 RF 93 10 10e6 * .ENDS * *$ *///////////////////////////////////////////////// *LMC6762B CMOS Comparator Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | output * | | | positive power supply * | | | | negative power supply * | | | | | * | | | | | .SUBCKT LMC6762B/NS 3 2 6 4 5 * *Features *Low Power Consumption *Wide Range of Supply *4us Propagation delay at 100mv Overdrive * *----- input satge ----- RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 FIN1 18 5 VTEMP 0.75 FIN2 19 5 VTEMP 1.25 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 5e+10 RD2 19 11 5e+10 * Diff. Input Resistance RCM 11 10 9.975e+12 * Common Mode Input Resistance *----- supply current ------ EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG RSLOPE 4 5 1e+12 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.000006 * Quiescent Supply Current *----- VOS bridge ----- EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K RAX 122 10 MRAX 1.027e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=0) *----- delay stage ----- RX8 40 815 10K RY8 815 50 5K RBA8 815 50 5K RBB8 815 811 1K EIN8 810 811 3 2 -1 EVOSS 814 811 122 121 1 *=== RCA8 40 812 1K RCB8 40 813 1K DDA8 812 813 DDEL1 DDB8 813 812 DDEL2 * Delay Time Settings CDB8 813 812 10P RCDB8 813 812 1MEG FSET8 809 50 VSENS1 1 CCC 809 50 5P QDN1 812 810 809 NPNX QDN2 813 814 809 NPNX .MODEL NPNX NPN (BF=100 RE=25) .MODEL DDEL1 D (IS=1e-6 TT=5.2U N=1.4 ) .MODEL DDEL2 D (IS=4e-6 TT=2.5U N=0.8 ) GDM 10 57 812 813 1 *----- start-up ----- ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *----- temp. Coef. ----- FSET 10 31 VSENS1 1.0 RVOS 31 32 1K RIB 32 33 MRIB 1K .MODEL MRIB RES (TC1=0.0036363) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) R001 34 10 1K *----- CMRR ----- ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG RCM1 39 41 1778.28 CCM 41 10 1.59155e-10 * CMRR vs. Freq. *----- PSRR ----- EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG RPSR1 44 45 1000 CPSR 45 10 1.59155e-10 * PSRR vs. Freq. *----- IB temp. ----- FTEMP 10 27 VSENS1 1.0 ETEMP 27 28 32 33 0.6184 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 *----- Out Curr. sense & set ----- FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *----- comm. input sense ----- DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 ECMP 40 97 26 10 0.2 ECMN 95 50 26 10 0.1 *----- inter-stage ----- GOS 10 57 122 121 1.0 GOSD 10 57 11 0 0.14m FCMR 10 57 VCMX 1200 * Low Freq. CMRR FPSR 10 57 VPSX 1450 * Low Freq. PSRR FCXX 57 10 VCXX 100 RDM 57 10 72552 C2 57 10 1.09683e-14 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 129.3 ELIMN 10 52 26 10 199.3 * G2 58 10 57 10 1.0e-06 R2 58 10 13.7832 GO2 59 10 58 10 18 * Avol and Slew-Rate Settings RO2 59 10 1K DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 *----- output stage ----- GO3 10 71 59 10 1 RO3 71 10 1 RDN2 710 71 100 RDP 720 72 100 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 RNO 78 81 1 RPO 79 81 1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 C1 58 59 1e-10 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG EPOS 40 74 26 10 0.05 ENEG 75 50 26 10 0.04 * Output Voltage Swing Settings GSOURCE 74 73 33 34 0.00032 GSINK 72 75 33 34 0.00045 * Output Current Settings ROO 81 86 20 .MODEL DMOD1 D .MODEL DMOD2 D (IS=1e-17) .MODEL NPN1 NPN (BF=100 IS=1e-15) .MODEL PNP1 PNP (BF=100 IS=1e-15) RA 73 40 10e6 RB 72 50 10e6 RC 72 73 10e6 RD 10 57 10e6 RE 24 10 10e6 RF 93 10 10e6 * .ENDS *$ *///////////////////////////////////////////////// *LMC6772A CMOS Comparator Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | output * | | | positive power supply * | | | | negative power supply * | | | | | * | | | | | .SUBCKT LMC6772A/NS 3 2 6 4 5 * *Features *Open Drain Output *Low Power Consumption *Wide Range of Supply *5us Response Time at 5V and 100mv Overdrive * *----- input satge ----- RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 FIN1 18 5 VTEMP 0.75 FIN2 19 5 VTEMP 1.25 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 5e+10 RD2 19 11 5e+10 * Diff. Input Resistance RCM 11 10 9.975e+12 * Common Mode Input Resistance *----- supply current ------ EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG RSLOPE 4 5 1e+12 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.000006 * Quiescent Supply Current *----- VOS bridge ----- EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K RAX 122 10 MRAX 1.00930e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=0) *----- delay stage ----- RX8 40 815 10K RY8 815 50 5K RBA8 815 50 5K RBB8 815 811 1K EIN8 810 811 3 2 -1 EVOSS 814 811 122 121 1 *=== RCA8 40 812 1K RCB8 40 813 1K DDA8 812 813 DDEL1 DDB8 813 812 DDEL2 * Delay Time Settings CDB8 813 812 10P RCDB8 813 812 1MEG FSET8 809 50 VSENS1 1 CCC 809 50 5P QDN1 812 810 809 NPNX QDN2 813 814 809 NPNX .MODEL NPNX NPN (BF=100 RE=25) .MODEL DDEL2 D (IS=1e-6 TT=9.5U N=4.0) .MODEL DDEL1 D (IS=4e-6 TT=12.0U N=4.5) GDM 10 57 812 813 1 *----- start-up ----- ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *----- temp. Coef. ----- FSET 10 31 VSENS1 1.0 RVOS 31 32 1K RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.0036363) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) R001 34 10 1K *----- CMRR ----- ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG RCM1 39 41 1778.28 CCM 41 10 1.59155e-10 * CMRR vs. Freq. *----- PSRR ----- EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG RPSR1 44 45 1000 CPSR 45 10 1.59155e-10 * PSRR vs. Freq. *----- IB temp. ----- FTEMP 10 27 VSENS1 1.0 ETEMP 27 28 32 33 0.6184 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 *----- Out Curr. sense & set ----- FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *----- comm. input sense ----- DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 ECMP 40 97 26 10 0.2 ECMN 95 50 26 10 0.1 *----- inter-stage ----- GOS 10 57 122 121 1.0 GOSD 10 57 11 0 0.14m FCMR 10 57 VCMX 1000 * Low Freq. CMRR FPSR 10 57 VPSX 1600 * Low Freq. PSRR FCXX 57 10 VCXX 100 RDM 57 10 7255.2 C2 57 10 1.09683e-13 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 ELIMN 10 52 26 10 99.3 * G2 58 10 57 10 1.0e-05 R2 58 10 13.7832 GO2 59 10 58 10 10 * Avol and Slew-Rate Settings RO2 59 10 1K DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 *----- output stage ----- GO3 10 71 59 10 1 RO3 71 10 1 RDP 720 72 100 RPO 79 81 28 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 C1 58 59 1e-10 VOON 77 50 DC 0 QNP 77 72 79 PNP1 VOX 86 6 DC 0 VOOP 40 76 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG ENEG 75 50 26 10 0.04 * Output Voltage Swing Settings GSINK 72 75 33 34 0.00045 * Output Current Settings ROO 81 86 0.1 .MODEL DMOD1 D .MODEL DMOD2 D (IS=1e-17) .MODEL PNP1 PNP (BF=100 IS=1e-13) RA 73 40 10e6 RB 72 50 10e6 RC 72 73 10e6 RD 10 57 10e6 RE 24 10 10e6 RF 93 10 10e6 * .ENDS * *$ *///////////////////////////////////////////////// *LMC6772B CMOS Comparator Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | output * | | | positive power supply * | | | | negative power supply * | | | | | * | | | | | .SUBCKT LMC6772B/NS 3 2 6 4 5 * *Features *Open Drain Output *Low Power Consumption *Wide Range of Supply *5us Response Time at 5V and 100mv Overdrive * *----- input satge ----- RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 FIN1 18 5 VTEMP 0.75 FIN2 19 5 VTEMP 1.25 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 5e+10 RD2 19 11 5e+10 * Diff. Input Resistance RCM 11 10 9.975e+12 * Common Mode Input Resistance *----- supply current ------ EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG RSLOPE 4 5 1e+12 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.000006 * Quiescent Supply Current *----- VOS bridge ----- EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K RAX 122 10 MRAX 1.0280e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=0) *----- delay stage ----- RX8 40 815 10K RY8 815 50 5K RBA8 815 50 5K RBB8 815 811 1K EIN8 810 811 3 2 -1 EVOSS 814 811 122 121 1 *=== RCA8 40 812 1K RCB8 40 813 1K DDA8 812 813 DDEL1 DDB8 813 812 DDEL2 * Delay Time Settings CDB8 813 812 10P RCDB8 813 812 1MEG FSET8 809 50 VSENS1 1 CCC 809 50 5P QDN1 812 810 809 NPNX QDN2 813 814 809 NPNX .MODEL NPNX NPN (BF=100 RE=25) .MODEL DDEL2 D (IS=1e-6 TT=9.5U N=4.0) .MODEL DDEL1 D (IS=4e-6 TT=12.0U N=4.5) GDM 10 57 812 813 1 *----- start-up ----- ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *----- temp. Coef. ----- FSET 10 31 VSENS1 1.0 RVOS 31 32 1K RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.0036363) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) R001 34 10 1K *----- CMRR ----- ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG RCM1 39 41 1778.28 CCM 41 10 1.59155e-10 * CMRR vs. Freq. *----- PSRR ----- EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG RPSR1 44 45 1000 CPSR 45 10 1.59155e-10 * PSRR vs. Freq. *----- IB temp. ----- FTEMP 10 27 VSENS1 1.0 ETEMP 27 28 32 33 0.6184 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 *----- Out Curr. sense & set ----- FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *----- comm. input sense ----- DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 ECMP 40 97 26 10 0.2 ECMN 95 50 26 10 0.1 *----- inter-stage ----- GOS 10 57 122 121 1.0 GOSD 10 57 11 0 0.14m FCMR 10 57 VCMX 1000 * Low Freq. CMRR FPSR 10 57 VPSX 1600 * Low Freq. PSRR FCXX 57 10 VCXX 100 RDM 57 10 7255.2 C2 57 10 1.09683e-13 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 ELIMN 10 52 26 10 99.3 * G2 58 10 57 10 1.0e-05 R2 58 10 13.7832 GO2 59 10 58 10 10 * Avol and Slew-Rate Settings RO2 59 10 1K DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 *----- output stage ----- GO3 10 71 59 10 1 RO3 71 10 1 RDP 720 72 100 RPO 79 81 28 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 C1 58 59 1e-10 VOON 77 50 DC 0 QNP 77 72 79 PNP1 VOX 86 6 DC 0 VOOP 40 76 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG ENEG 75 50 26 10 0.04 * Output Voltage Swing Settings GSINK 72 75 33 34 0.00045 * Output Current Settings ROO 81 86 0.1 .MODEL DMOD1 D .MODEL DMOD2 D (IS=1e-17) .MODEL PNP1 PNP (BF=100 IS=1e-13) RA 73 40 10e6 RB 72 50 10e6 RC 72 73 10e6 RD 10 57 10e6 RE 24 10 10e6 RF 93 10 10e6 * .ENDS * *$ *////////////////////////////////////////////////////////// *LMC7101A CMOS OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC7101A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 2pA *Slew rate = 1.2V/uS * *NOTE: Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 17U M1 5 2 4 99 MOSFET R3 5 50 5.651K M2 6 7 4 99 MOSFET R4 6 50 5.651K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DC DP3 2 99 DB DP4 50 2 DC *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 99 50 420.5U *^Quiescent current EOS 7 1 POLY(1) 16 49 4E-3 1 *Offset voltage.......... R8 99 49 40K R9 49 50 40K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 99 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** **New output stage below *(Change EH to go to 97 too) * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 130 RN16 123 124 180 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 180K VN4 129 28 2.6 DN4 121 115 DX RN19 130 121 140K VN5 28 130 2.6 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 17P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.3E-11) .MODEL DB D(IS=1.2E-11) .MODEL DC D(IS=1.0E-11) .MODEL DX D(IS=1.0E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS *$ *////////////////////////////////////////////////////////// *LMC7101B CMOS OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC7101B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * *Features: *Operates from single or dual supplies *Rail-to-rail input and output swing *Ultra low input current = 1pA *Slew rate = 1.2V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Noise is not modeled. * Asymmetrical gain is not modeled. * *****************INPUT STAGE************** * I1 99 4 17U M1 5 2 4 99 MOSFET R3 5 50 5.651K M2 6 7 4 99 MOSFET R4 6 50 5.651K *Fp2=5.9 MHz C4 5 6 2.3868P G0 98 9 6 5 4.4165E-2 R0 98 9 1K DP1 1 99 DA DP2 50 1 DC DP3 2 99 DB DP4 50 2 DC *For accurate Ib , set GMIN<=1E-16 on .OPTIONS line. * ***********COMMON MODE EFFECT*********** * I2 99 50 420.5U *^Quiescent current EOS 7 1 POLY(1) 16 49 7E-3 1 *Offset voltage.......... R8 99 49 40K R9 49 50 40K * ***************POLE STAGE*************** * *Fp=13.3 MHz G3 98 15 9 49 1E-3 R12 98 15 1K C5 98 15 11.967P * ************POLE/ZERO STAGE************* * *Fp=600 KHz, Fz= 1.4MHz G5 98 18 15 49 1E-3 R14 98 18 1K R15 98 19 750 C6 19 18 151.58P * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 POLY(2) 1 49 2 49 0 2.812E-8 2.812E-8 L2 98 17 7.958M R13 17 16 1K * **************SECOND STAGE************** * EH 97 98 99 49 1 G1 98 29 18 49 5.6667E-6 R5 98 29 100.37MEG V2 99 8 1.56 D1 29 8 DX D2 10 29 DX V3 10 50 1.56 * **************OUTPUT STAGE************** *OLD output stage. Kept for reference only * *F6 99 50 VA7 1 *^Dynamic supply current *F5 99 35 VA8 1 *D3 36 35 DX *VA7 99 36 0 *D4 35 99 DX *E1 99 37 99 49 1 *VA8 37 38 0 *G6 38 40 49 29 16.667E-3 *R16 38 40 2.3886K *V4 30 40 .77 *D5 30 99 DX *V5 40 31 .77 *D6 50 31 DX *Fp1=2.343 Hz *C3 29 39 17P *R6 39 40 1K * *New output stage below *(Change EH to go to 97 too) *(OUTPUT NODE CHANGED TO 28) * F6 99 50 VA7 1 *^Dynamic supply current F5 99 35 VA8 1 D3 36 35 DX VA7 99 36 0 D4 35 99 DX E1 99 37 99 49 1 VA8 37 38 0 GN3 98 115 40 49 1U RN21 98 115 1MEG EN1 97 123 99 115 1 RN17 123 125 130 RN16 123 124 180 DN6 125 127 DX DN5 126 124 DX VN7 28 127 0.63 VN6 126 28 0.63 DN3 115 120 DX RN18 120 129 180K VN4 129 28 2.6 DN4 121 115 DX RN19 130 121 140K VN5 28 130 2.6 ENP 97 0 99 0 1 ENN 0 96 0 50 1 DN7 28 99 DX DN8 50 28 DX * * G6 38 40 49 29 16.667E-3 R16 38 40 2.3886K V4 30 40 .77 D5 30 97 DX V5 40 31 .77 D6 96 31 DX *Fp1=7.96 Hz C3 29 39 17P R6 39 40 1K * ***************MODELS USED************** * .MODEL DA D(IS=1.3E-11) .MODEL DB D(IS=1.2E-11) .MODEL DC D(IS=1.0E-11) .MODEL DX D(IS=1.0E-14) .MODEL MOSFET PMOS(VTO=0 KP=1.842E-3) .ENDS * *$ *///////////////////////////////////////////////// *LMC7111A Operational Amplifier Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC7111A/NS 3 2 4 5 6 * *Features *Tiny SOT23-5 Package *Wide Common Mode Input Range *50 KHz Gain-Bandwidth at 5V * EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.006000e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=4e-06) FIN1 18 5 VTEMP 0.99 FIN2 19 5 VTEMP 1.01 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 5e+11 RD2 19 11 5e+11 * Diff. Input Resistance RCM 11 10 9.75e+12 * Common Mode Input Resistance FCMR 10 57 VCMX 56.2341 * Low Freq. CMRR FPSR 10 57 VPSX 200 * Low Freq. PSRR RSLOPE 4 5 2e+06 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 1.75e-05 * Quiescent Supply Current ETEMP 27 28 32 33 0.553186 RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.000554971) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.001) RCM1 39 41 177.828 CCM 41 10 1.59155e-09 * CMRR vs. Freq. RPSR1 44 45 316.228 CPSR 45 10 1.59155e-09 * PSRR vs. Freq. ELIMN 10 52 26 10 124.3 RDM 57 10 1813.8 C2 57 10 8.77467e-10 ECMP 40 97 26 10 0.5 ECMN 95 50 26 10 0 G2 58 10 57 10 2e-08 R2 58 10 27566.4 GO2 59 10 58 10 500 * Avol and Slew-Rate Settings EPOS 40 74 26 10 0 ENEG 75 50 26 10 0.2 * Output Voltage Swing Settings GSOURCE 74 73 33 34 7e-05 GSINK 72 75 33 34 7e-05 * Output Current Settings ROO 81 86 27.5 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .ENDS * *$ *///////////////////////////////////////////////// *LMC7111B Operational Amplifier Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC7111B/NS 3 2 4 5 6 * *Features *Tiny SOT23-5 Package *Wide Common Mode Input Range *50 KHz Gain-Bandwidth at 5V * EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K GOS 10 57 122 121 1.0 RVOS 31 32 1K RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 FSET 10 31 VSENS1 1.0 R001 34 10 1K FTEMP 10 27 VSENS1 1.0 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG FCXX 57 10 VCXX 100 DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 GDM 10 57 3 2 1 C1 58 59 1e-10 DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 RO2 59 10 1K GO3 10 71 59 10 1 RO3 71 10 1 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 RDN2 710 71 100 RDP 720 72 100 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 RNO 78 81 1 RPO 79 81 1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 RAX 122 10 MRAX 1.014000e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=4e-06) FIN1 18 5 VTEMP 0.99 FIN2 19 5 VTEMP 1.01 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 5e+11 RD2 19 11 5e+11 * Diff. Input Resistance RCM 11 10 9.75e+12 * Common Mode Input Resistance FCMR 10 57 VCMX 56.2341 * Low Freq. CMRR FPSR 10 57 VPSX 200 * Low Freq. PSRR RSLOPE 4 5 2e+06 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 1.75e-05 * Quiescent Supply Current ETEMP 27 28 32 33 0.553186 RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.000554971) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=-0.001) RCM1 39 41 177.828 CCM 41 10 1.59155e-09 * CMRR vs. Freq. RPSR1 44 45 316.228 CPSR 45 10 1.59155e-09 * PSRR vs. Freq. ELIMN 10 52 26 10 124.3 RDM 57 10 1813.8 C2 57 10 8.77467e-10 ECMP 40 97 26 10 0.5 ECMN 95 50 26 10 0 G2 58 10 57 10 2e-08 R2 58 10 27566.4 GO2 59 10 58 10 500 * Avol and Slew-Rate Settings EPOS 40 74 26 10 0 ENEG 75 50 26 10 0.2 * Output Voltage Swing Settings GSOURCE 74 73 33 34 7e-05 GSINK 72 75 33 34 7e-05 * Output Current Settings ROO 81 86 27.5 .MODEL DMOD1 D *-- DMOD1 DEFAULT PARAMETERS *IS=1e-14 RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL DMOD2 D (IS=1e-17) *-- DMOD2 DEFAULT PARAMETERS *RS=0 N=1 TT=0 CJO=0 *VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5 *KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27 .MODEL NPN1 NPN (BF=100 IS=1e-15) *-- NPN1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .MODEL PNP1 PNP (BF=100 IS=1e-15) *-- PNP1 DEFAULT PARAMETERS *NF=1 VAF=inf IKF=inf ISE=0 NE=1.5 *BR=1 NR=1 VAR=inf IKR=inf ISC=0 *NC=2 RB=0 IRB=inf RBM=0 RE=0 RC=0 *CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 *VTF=inf ITF=0 PTF=0 CJC=0 VJC=0.75 *MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 *MJS=0 XTB=0 EG=1.11 XTI=3 KF=0 AF=1 *FC=0.5 TNOM=27 .ENDS *$ *///////////////////////////////////////// *LMC7211A CMOS Comparator Macro-Model *///////////////////////////////////////// * * Connections Non-nverting input * | Inverting input * | | Output * | | | Positive power supply * | | | | Negative power supply * | | | | | .SUBCKT LMC7211A/NS 3 2 6 4 5 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail input common mode voltage range * Rail-to-rail output swing * Offset voltage (max) = 5mV * Low supply current = 7uA * Ultra low input current = 20fA * Overdrive response = 4us (100mV) *----- input satge ----- RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 FIN1 18 5 VTEMP 0.75 FIN2 19 5 VTEMP 1.25 CIN1 2 10 1e-12 CIN2 3 10 1e-12 RD1 18 11 5e+10 RD2 19 11 5e+10 RCM 11 10 9.975e+12 *----- supply current ------ EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG RSLOPE 4 5 1e+12 GPWR 4 5 26 10 0.00001 *----- VOS bridge ----- EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K RAX 122 10 MRAX 1.010000e+03 .MODEL MRAX RES (TC1=0) *----- delay stage ----- RX8 40 815 10K RY8 815 50 5K RBA8 815 50 5K RBB8 815 811 1K EIN8 810 811 3 2 -1 EVOSS 814 811 122 121 1 *=== RCA8 40 812 1K RCB8 40 813 1K DDA8 812 813 DDEL1 DDB8 813 812 DDEL2 CDB8 813 812 10P RCDB8 813 812 1MEG FSET8 809 50 VSENS1 1 CCC 809 50 5P QDN1 812 810 809 NPNX QDN2 813 814 809 NPNX .MODEL NPNX NPN (BF=100 RE=25) .MODEL DDEL1 D (IS=1e-6 TT=4.1U N=0.30 ) .MODEL DDEL2 D (IS=4e-6 TT=2.7U N=0.30 ) GDM 10 57 812 813 1 *----- start-up ----- ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *----- temp. Coef. ----- FSET 10 31 VSENS1 1.0 RVOS 31 32 1K RIB 32 33 MRIB 1K .MODEL MRIB RES (TC1=0.0029713) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) R001 34 10 1K *----- CMRR ----- ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG RCM1 39 41 1e6 CCM 41 10 1.59155e-10 *----- PSRR ----- EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG RPSR1 44 45 1e6 CPSR 45 10 1.59155e-10 *----- IB temp. ----- FTEMP 10 27 VSENS1 1.0 ETEMP 27 28 32 33 0.63633 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 *----- Out Curr. sense & set ----- FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *----- comm. input sense ----- DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 ECMP 40 97 26 10 0.2 ECMN 95 50 26 10 0.1 *----- inter-stage ----- GOS 10 57 122 121 1.0 FCMR 10 57 VCMX 1000 FPSR 10 57 VPSX 1000 FCXX 57 10 VCXX 100 RDM 57 10 72552 C2 57 10 1.09683e-14 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 ELIMN 10 52 26 10 99.3 * G2 58 10 57 10 1.6e-06 R2 58 10 13.7832 GO2 59 10 58 10 22 RO2 59 10 1K DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 *----- output stage ----- GO3 10 71 59 10 1 RO3 71 10 1 RDN2 710 71 100 RDP 720 72 100 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 RNO 78 81 1 RPO 79 81 1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 C1 58 59 1e-10 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG EPOS 40 74 26 10 0.0 ENEG 75 50 26 10 0.1 GSOURCE 74 73 33 34 0.00032 GSINK 72 75 33 34 0.00045 ROO 81 86 27.5 .MODEL DMOD1 D .MODEL DMOD2 D (IS=1e-17) .MODEL NPN1 NPN (BF=100 IS=1e-15) .MODEL PNP1 PNP (BF=100 IS=1e-15) RA 73 40 10e6 RB 72 50 10e6 RC 72 73 10e6 RD 10 57 10e6 RE 24 10 10e6 RF 93 10 10e6 * .ENDS * *$ *///////////////////////////////////////// *LMC7211B CMOS Comparator Macro-Model *///////////////////////////////////////// * * Connections Non-nverting input * | Inverting input * | | Output * | | | Positive power supply * | | | | Negative power supply * | | | | | .SUBCKT LMC7211B/NS 3 2 6 4 5 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * Features: * Operates from single supply * Rail-to-rail Input Common mode Voltage Range * Rail-to-rail output swing * Low offset voltage (max) = 15mV * Ultra low input current = 20fA * Low supply current = 7uA * Overdrive response = 4us (100mV) *----- input satge ----- RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 FIN1 18 5 VTEMP 0.75 FIN2 19 5 VTEMP 1.25 CIN1 2 10 1e-12 CIN2 3 10 1e-12 RD1 18 11 5e+10 RD2 19 11 5e+10 RCM 11 10 9.975e+12 *----- supply current ------ EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG RSLOPE 4 5 1e+12 GPWR 4 5 26 10 0.00001 *----- VOS bridge ----- EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K RAX 122 10 MRAX 1.030000e+03 .MODEL MRAX RES (TC1=0) *----- delay stage ----- RX8 40 815 10K RY8 815 50 5K RBA8 815 50 5K RBB8 815 811 1K EIN8 810 811 3 2 -1 EVOSS 814 811 122 121 1 *=== RCA8 40 812 1K RCB8 40 813 1K DDA8 812 813 DDEL1 DDB8 813 812 DDEL2 CDB8 813 812 10P RCDB8 813 812 1MEG FSET8 809 50 VSENS1 1 CCC 809 50 5P QDN1 812 810 809 NPNX QDN2 813 814 809 NPNX .MODEL NPNX NPN (BF=100 RE=25) .MODEL DDEL1 D (IS=1e-6 TT=4.1U N=0.30 ) .MODEL DDEL2 D (IS=4e-6 TT=2.7U N=0.30 ) GDM 10 57 812 813 1 *----- start-up ----- ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *----- temp. Coef. ----- FSET 10 31 VSENS1 1.0 RVOS 31 32 1K RIB 32 33 MRIB 1K .MODEL MRIB RES (TC1=0.0029713) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) R001 34 10 1K *----- CMRR ----- ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG RCM1 39 41 1e6 CCM 41 10 1.59155e-10 *----- PSRR ----- EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG RPSR1 44 45 1e6 CPSR 45 10 1.59155e-10 *----- IB temp. ----- FTEMP 10 27 VSENS1 1.0 ETEMP 27 28 32 33 0.63633 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 *----- Out Curr. sense & set ----- FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *----- comm. input sense ----- DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 ECMP 40 97 26 10 0.2 ECMN 95 50 26 10 0.1 *----- inter-stage ----- GOS 10 57 122 121 1.0 FCMR 10 57 VCMX 1000 FPSR 10 57 VPSX 1000 FCXX 57 10 VCXX 100 RDM 57 10 72552 C2 57 10 1.09683e-14 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 ELIMN 10 52 26 10 99.3 * G2 58 10 57 10 1.6e-06 R2 58 10 13.7832 GO2 59 10 58 10 22 RO2 59 10 1K DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 *----- output stage ----- GO3 10 71 59 10 1 RO3 71 10 1 RDN2 710 71 100 RDP 720 72 100 DDN1 73 74 DMOD1 DDN2 73 710 DMOD1 RNO 78 81 1 RPO 79 81 1 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 C1 58 59 1e-10 VOOP 40 76 DC 0 VOON 77 50 DC 0 QNO 76 73 78 NPN1 QNP 77 72 79 PNP1 VOX 86 6 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG EPOS 40 74 26 10 0.0 ENEG 75 50 26 10 0.1 GSOURCE 74 73 33 34 0.00032 GSINK 72 75 33 34 0.00045 ROO 81 86 27.5 .MODEL DMOD1 D .MODEL DMOD2 D (IS=1e-17) .MODEL NPN1 NPN (BF=100 IS=1e-15) .MODEL PNP1 PNP (BF=100 IS=1e-15) RA 73 40 10e6 RB 72 50 10e6 RC 72 73 10e6 RD 10 57 10e6 RE 24 10 10e6 RF 93 10 10e6 * .ENDS *$ *///////////////////////////////////////////////// *LMC7221A CMOS Comparator Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | output * | | | positive power supply * | | | | negative power supply * | | | | | * | | | | | .SUBCKT LMC7221A/NS 3 2 6 4 5 * *Features *Open Drain Output *Low Power Consumption *Wide Range of Supply *7us Response Time at 5V * *----- input satge ----- RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 FIN1 18 5 VTEMP 0.75 FIN2 19 5 VTEMP 1.25 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 5e+10 RD2 19 11 5e+10 * Diff. Input Resistance RCM 11 10 9.975e+12 * Common Mode Input Resistance *----- supply current ------ EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG RSLOPE 4 5 1e+12 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.000007 * Quiescent Supply Current *----- VOS bridge ----- EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K RAX 122 10 MRAX 1.00930e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=0) *----- delay stage ----- RX8 40 815 10K RY8 815 50 5K RBA8 815 50 5K RBB8 815 811 1K EIN8 810 811 3 2 -1 EVOSS 814 811 122 121 1 *=== RCA8 40 812 1K RCB8 40 813 1K DDA8 812 813 DDEL1 DDB8 813 812 DDEL2 * Delay Time Settings CDB8 813 812 10P RCDB8 813 812 1MEG FSET8 809 50 VSENS1 1 CCC 809 50 5P QDN1 812 810 809 NPNX QDN2 813 814 809 NPNX .MODEL NPNX NPN (BF=100 RE=25) .MODEL DDEL2 D (IS=1e-6 TT=9.5U N=4.0) .MODEL DDEL1 D (IS=4e-6 TT=12.0U N=4.5) GDM 10 57 812 813 1 *----- start-up ----- ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *----- temp. Coef. ----- FSET 10 31 VSENS1 1.0 RVOS 31 32 1K RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.0036363) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) R001 34 10 1K *----- CMRR ----- ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG RCM1 39 41 1778.28 CCM 41 10 1.59155e-10 * CMRR vs. Freq. *----- PSRR ----- EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG RPSR1 44 45 1000 CPSR 45 10 1.59155e-10 * PSRR vs. Freq. *----- IB temp. ----- FTEMP 10 27 VSENS1 1.0 ETEMP 27 28 32 33 0.6184 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 *----- Out Curr. sense & set ----- FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *----- comm. input sense ----- DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 ECMP 40 97 26 10 0.2 ECMN 95 50 26 10 0.1 *----- inter-stage ----- GOS 10 57 122 121 1.0 GOSD 10 57 11 0 0.14m FCMR 10 57 VCMX 1000 * Low Freq. CMRR FPSR 10 57 VPSX 1600 * Low Freq. PSRR FCXX 57 10 VCXX 100 RDM 57 10 7255.2 C2 57 10 1.09683e-13 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 ELIMN 10 52 26 10 99.3 * G2 58 10 57 10 1.0e-05 R2 58 10 13.7832 GO2 59 10 58 10 10 * Avol and Slew-Rate Settings RO2 59 10 1K DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 *----- output stage ----- GO3 10 71 59 10 1 RO3 71 10 1 RDP 720 72 100 RPO 79 81 28 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 C1 58 59 1e-10 VOON 77 50 DC 0 QNP 77 72 79 PNP1 VOX 86 6 DC 0 VOOP 40 76 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG ENEG 75 50 26 10 0.04 * Output Voltage Swing Settings GSINK 72 75 33 34 0.00045 * Output Current Settings ROO 81 86 0.1 .MODEL DMOD1 D .MODEL DMOD2 D (IS=1e-17) .MODEL PNP1 PNP (BF=100 IS=1e-13) RA 73 40 10e6 RB 72 50 10e6 RC 72 73 10e6 RD 10 57 10e6 RE 24 10 10e6 RF 93 10 10e6 * .ENDS *$ *///////////////////////////////////////////////// *LMC7221B CMOS Comparator Macro-Model *///////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | output * | | | positive power supply * | | | | negative power supply * | | | | | * | | | | | .SUBCKT LMC7221B/NS 3 2 6 4 5 * *Features *Open Drain Output *Low Power Consumption *Wide Range of Supply *7us Response Time at 5V * *----- input satge ----- RINB 2 18 1000 RINA 3 19 1000 DIN1 5 18 DMOD2 DIN2 18 4 DMOD2 DIN3 5 19 DMOD2 DIN4 19 4 DMOD2 FIN1 18 5 VTEMP 0.75 FIN2 19 5 VTEMP 1.25 * Input Bias Currents CIN1 2 10 1e-12 CIN2 3 10 1e-12 * Common Mode Input Capacitance RD1 18 11 5e+10 RD2 19 11 5e+10 * Diff. Input Resistance RCM 11 10 9.975e+12 * Common Mode Input Resistance *----- supply current ------ EXX 10 5 17 5 1.0 EEE 10 50 17 5 1.0 ECC 40 10 4 17 1.0 RAA 4 17 100MEG RBB 17 5 100MEG RSLOPE 4 5 1e+12 * Slope of Supp. Curr. vs. Supp. Volt. GPWR 4 5 26 10 0.000007 * Quiescent Supply Current *----- VOS bridge ----- EOX 120 10 31 32 2.0 RCX 120 121 1K RDX 121 10 1K RBX 120 122 1K RAX 122 10 MRAX 1.0280e+03 * Input Offset Voltage .MODEL MRAX RES (TC1=0) *----- delay stage ----- RX8 40 815 10K RY8 815 50 5K RBA8 815 50 5K RBB8 815 811 1K EIN8 810 811 3 2 -1 EVOSS 814 811 122 121 1 *=== RCA8 40 812 1K RCB8 40 813 1K DDA8 812 813 DDEL1 DDB8 813 812 DDEL2 * Delay Time Settings CDB8 813 812 10P RCDB8 813 812 1MEG FSET8 809 50 VSENS1 1 CCC 809 50 5P QDN1 812 810 809 NPNX QDN2 813 814 809 NPNX .MODEL NPNX NPN (BF=100 RE=25) .MODEL DDEL2 D (IS=1e-6 TT=9.5U N=4.0) .MODEL DDEL1 D (IS=4e-6 TT=12.0U N=4.5) GDM 10 57 812 813 1 *----- start-up ----- ISET 10 24 1e-3 DA1 24 23 DMOD1 RBAL 23 22 1000 ESUPP 22 21 4 5 1.0 VOFF 21 10 -1.25 DA2 24 25 DMOD1 VSENS1 25 26 DC 0 RSET 26 10 1K CSET 26 10 1e-10 *----- temp. Coef. ----- FSET 10 31 VSENS1 1.0 RVOS 31 32 1K RIB 32 33 MRIB 1K * Temp. Co. of Input Currents .MODEL MRIB RES (TC1=0.0036363) RISC 33 34 MRISC 1K .MODEL MRISC RES (TC1=0) R001 34 10 1K *----- CMRR ----- ECMR 38 10 11 10 1.0 VCMX 38 39 DC 0 RCM2 41 10 1MEG RCM1 39 41 1778.28 CCM 41 10 1.59155e-10 * CMRR vs. Freq. *----- PSRR ----- EPSR 42 10 4 10 1.0 CDC1 43 42 10U VPSX 43 44 DC 0 RPSR2 45 10 1MEG RPSR1 44 45 1000 CPSR 45 10 1.59155e-10 * PSRR vs. Freq. *----- IB temp. ----- FTEMP 10 27 VSENS1 1.0 ETEMP 27 28 32 33 0.6184 DTA 27 10 DMOD2 DTB 28 29 DMOD2 VTEMP 29 10 DC 0 *----- Out Curr. sense & set ----- FX 10 93 VOX 1.0 DFX1 93 91 DMOD1 VFX1 91 10 DC 0 DFX2 92 93 DMOD1 VFX2 10 92 DC 0 FPX 4 10 VFX1 1.0 FNX 10 5 VFX2 1.0 *----- comm. input sense ----- DCX1 98 97 DMOD1 DCX2 95 94 DMOD1 RCX1 99 98 100 RCX2 94 99 100 VCXX 99 96 DC 0 ECMX 96 10 11 10 1.0 ECMP 40 97 26 10 0.2 ECMN 95 50 26 10 0.1 *----- inter-stage ----- GOS 10 57 122 121 1.0 GOSD 10 57 11 0 0.14m FCMR 10 57 VCMX 1000 * Low Freq. CMRR FPSR 10 57 VPSX 1600 * Low Freq. PSRR FCXX 57 10 VCXX 100 RDM 57 10 7255.2 C2 57 10 1.09683e-13 DLIM1 52 57 DMOD1 DLIM2 57 51 DMOD1 ELIMP 51 10 26 10 99.3 ELIMN 10 52 26 10 99.3 * G2 58 10 57 10 1.0e-05 R2 58 10 13.7832 GO2 59 10 58 10 10 * Avol and Slew-Rate Settings RO2 59 10 1K DCLMP2 59 40 DMOD1 DCLMP1 50 59 DMOD1 *----- output stage ----- GO3 10 71 59 10 1 RO3 71 10 1 RDP 720 72 100 RPO 79 81 28 DDP1 75 72 DMOD1 DDP2 71 720 DMOD1 C1 58 59 1e-10 VOON 77 50 DC 0 QNP 77 72 79 PNP1 VOX 86 6 DC 0 VOOP 40 76 DC 0 RNT 76 81 100MEG RPT 81 77 1MEG ENEG 75 50 26 10 0.04 * Output Voltage Swing Settings GSINK 72 75 33 34 0.00045 * Output Current Settings ROO 81 86 0.1 .MODEL DMOD1 D .MODEL DMOD2 D (IS=1e-17) .MODEL PNP1 PNP (BF=100 IS=1e-13) RA 73 40 10e6 RB 72 50 10e6 RC 72 73 10e6 RD 10 57 10e6 RE 24 10 10e6 RF 93 10 10e6 * .ENDS *$ * ///////////////////////////////////////////////////// * LPC660A Low Power CMOS Quad Operational Amplifier * ///////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LPC660A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 40fA * Slew rate = .11V/uS * Gain-bandwidth product = 350kHz * Low supply current = 40uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 89.2E-3 Hz pole capacitor C3 98 9 178.2N * 604.1 kHz pole capacitor C4 6 5 1.68P * 1.98 MHz pole capacitor C5 98 15 80F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 15.8F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 34.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.750V V3 10 96 0.742V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////////////// * LPC660B Low Power CMOS Quad Operational Amplifier * ///////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LPC660B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 6mV * Ultra low input current = 40fA * Slew rate = .11V/uS * Gain-bandwidth product = 350kHz * Low supply current = 40uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/4 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 89.2E-3 Hz pole capacitor C3 98 9 178.2N * 604.1 kHz pole capacitor C4 6 5 1.68P * 1.98 MHz pole capacitor C5 98 15 80F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 15.8F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 6M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 34.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.750V V3 10 96 0.742V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * /////////////////////////////////////////////////////// * LPC661A Low Power CMOS Single Operational Amplifier * /////////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LPC661A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 40fA * Slew rate = .11V/uS * Gain-bandwidth product = 350kHz * Low supply current = 58uA * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 89.2E-3 Hz pole capacitor C3 98 9 178.2N * 604.1 kHz pole capacitor C4 6 5 1.68P * 1.98 MHz pole capacitor C5 98 15 80F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 15.8F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 49.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.750V V3 10 96 0.742V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * /////////////////////////////////////////////////// * LPC661B Low Power CMOS Single Operational Amplifier * /////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LPC661B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 6mV * Ultra low input current = 40fA * Slew rate = .11V/uS * Gain-bandwidth product = 350kHz * Low supply current = 58uA * * NOTE: - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 89.2E-3 Hz pole capacitor C3 98 9 178.2N * 604.1 kHz pole capacitor C4 6 5 1.68P * 1.98 MHz pole capacitor C5 98 15 80F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 15.8F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 6M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 49.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.750V V3 10 96 0.742V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////////////////// * LPC662A Low Power CMOS Dual Operational Amplifier * ///////////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LPC662A/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 3mV * Ultra low input current = 40fA * Slew rate = .11V/uS * Gain-bandwidth product = 350kHz * Low supply current = 43uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 89.2E-3 Hz pole capacitor C3 98 9 178.2N * 604.1 kHz pole capacitor C4 6 5 1.68P * 1.98 MHz pole capacitor C5 98 15 80F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 15.8F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 3M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 37.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.750V V3 10 96 0.742V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ * ///////////////////////////////////////////////// * LPC662B Low Power CMOS Dual Operational Amplifier * ///////////////////////////////////////////////// * * Connections: Non-inverting input * | Inverting input * | | Positive power supply * | | | Negative power supply * | | | | Output * | | | | | * | | | | | .SUBCKT LPC662B/NS 1 2 99 50 28 * CAUTION: SET .OPTIONS GMIN=1E-16 TO CORRECTLY MODEL INPUT BIAS CURRENT. * * Features: * Operates from single supply * Rail-to-rail output swing * Low offset voltage (max) = 6mV * Ultra low input current = 40fA * Slew rate = .11V/uS * Gain-bandwidth product = 350kHz * Low supply current = 43uA/Amplifier * * NOTE: - Model is for single device only and simulated * supply current is 1/2 of total device current. * - Noise is not modeled. * - Asymmetrical gain is not modeled. * CI1 1 50 2P CI2 2 50 2P * 89.2E-3 Hz pole capacitor C3 98 9 178.2N * 604.1 kHz pole capacitor C4 6 5 1.68P * 1.98 MHz pole capacitor C5 98 15 80F * Drain-substrate capacitance C6 50 4 5P * 10 MHz pole capacitor C7 98 11 15.8F DP1 1 99 DA DP2 50 1 DX DP3 2 99 DB DP4 50 2 DX D1 9 8 DX D2 10 9 DX D3 15 20 DX D4 21 15 DX D5 26 24 DX D6 25 27 DX D7 22 99 DX D8 50 22 DX D9 0 14 DX D10 12 0 DX EH 97 98 99 49 1.0 EN 0 96 0 50 1.0 * Input offset voltage--| EOS 7 1 POLY(1) 16 49 6M 1 EP 97 0 99 0 1.0 E1 97 19 99 15 1.0 * Sourcing load +Vs current F1 99 0 VA2 1 * Sinking load -Vs current F2 0 50 VA3 1 F3 13 0 VA1 1 G1 98 9 5 6 0.1 G2 98 11 9 49 1U G3 98 15 11 49 1U * DC CMRR G4 98 16 POLY(2) 1 49 2 49 0 3.54E-8 3.54E-8 I1 99 4 3.678U I2 99 50 37.8U * Load dependent pole L1 22 28 2.06M * CMRR lead L2 16 17 79.2M M1 5 2 4 99 MX M2 6 7 4 99 MX R3 5 50 78.2K R4 6 50 78.2K R5 98 9 1E7 R8 99 49 1.66E6 R9 49 50 1.66E6 R12 98 11 1E6 R13 98 17 1K * -Rout R16 23 24 75 * +Rout R17 23 25 70 * +Isc slope control R18 20 29 144.6K * -Isc slope control R19 21 30 185K R21 98 15 1E6 R22 22 28 4.54K VA1 19 23 0V VA2 14 13 0V VA3 13 12 0V V2 97 8 0.750V V3 10 96 0.742V V4 29 22 0.63V V5 22 30 0.63V V6 26 22 0.63V V7 22 27 0.63V .MODEL DA D (IS=5E-14) .MODEL DB D (IS=4E-14) .MODEL DX D (IS=1E-14) .MODEL MX PMOS (VTO=-2.19 KP=7.0547E-4) .ENDS *$ *////////////////////////////////////////////////////////// *LF155/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF155/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV *NOTE:Asymetrical slew rate not modeled. * ****************INPUT STAGE************** * IOS 2 1 3P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.65MA ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 9.6796E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=23.7 HZ C3 98 11 67.154P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 150U 1 ;Supply current correction E1 99 23 99 9 1 R16 24 23 25 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 25 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 9 DX V4 20 22 0.63V D3 9 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF156/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF156/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.5944E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=31.96 HZ C3 98 11 49.9798P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 150U 1 ;Supply current correction E1 99 23 99 9 1 R16 24 23 25 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 25 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 9 DX V4 20 22 0.63V D3 9 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF157/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF157/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 8.1291E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=224 HZ C3 98 11 7.10513P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 150U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 25 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 25 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF255/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF255/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV *NOTE:Asymetrical slew rate not modeled. * ****************INPUT STAGE************** * IOS 2 1 3P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.65MA ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 9.6796E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=23.7 HZ C3 98 11 67.154P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 150U 1 ;Supply current correction E1 99 23 99 9 1 R16 24 23 25 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 25 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 9 DX V4 20 22 0.63V D3 9 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF256/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF256/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.5944E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=31.96 HZ C3 98 11 49.9798P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 150U 1 ;Supply current correction E1 99 23 99 9 1 R16 24 23 25 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 25 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 9 DX V4 20 22 0.63V D3 9 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF257/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF257/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 8.1291E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=224 HZ C3 98 11 7.10513P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 150U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 25 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 25 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF351 Wide Bandwidth JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF351/NS 1 2 99 50 28 * *Features: *Low supply current = 1.8mA *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * ****************INPUT STAGE************** * IOS 2 1 25P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.7MA ;Supply current EOS 7 1 POLY(1) 16 49 5E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 400U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 35 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 35 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12 N=3) * .ENDS * *////////////////////////////////////////////////////////// *LF353 Wide Bandwidth Dual JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF353/NS 1 2 99 50 28 * *Features: *Low supply current = 1.8mA *Wide bandwidth = 4MHz *High slew rate = 13V/uS *Low offset voltage = 10mV * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.7MA ;Supply current EOS 7 1 POLY(1) 16 49 5E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.0985E7 G1 98 9 5 6 1E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=40.3 HZ C3 98 11 39.493P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.7894E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 31.831M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 400U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 35 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 35 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=50E-12 N=3) * .ENDS * *////////////////////////////////////////////////////////// *LF355/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF355/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV *NOTE:Asymetrical slew rate not modeled. * ****************INPUT STAGE************** * IOS 2 1 3P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 1.65MA ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 9.6796E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=23.7 HZ C3 98 11 67.154P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 150U 1 ;Supply current correction E1 99 23 99 9 1 R16 24 23 25 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 25 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 9 DX V4 20 22 0.63V D3 9 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF356/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF356/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=20 MHz C4 5 6 1.9894E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.5944E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=31.96 HZ C3 98 11 49.9798P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 150U 1 ;Supply current correction E1 99 23 99 9 1 R16 24 23 25 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 25 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 9 DX V4 20 22 0.63V D3 9 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF357/A/B Monolithic JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF357/NS 1 2 99 50 28 * *Features: *Low input bias current = 30pA *Low input offset current = 3pA *High input impedance = 1Tohm *Low input offset voltage = 1mV * ****************INPUT STAGE************** * IOS 2 1 3P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 100U J1 5 2 4 JX J2 6 7 4 JX R3 5 50 20K R4 6 50 20K *Fp2=12 MHz C4 5 6 3.31573E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4.65MA ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 50K R9 49 50 50K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 8.1291E7 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=224 HZ C3 98 11 7.10513P * ***************POLE STAGE*************** * *Fp3=42 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 530.52M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 150U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 25 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 25 D6 25 27 DY V7 22 27 0.63V C9 23 22 500P V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF400/A Fast-Settling JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF400/NS 1 2 99 50 28 * *Features: *Fast settling time (.01%) = 400nS *High bandwidth = 16MHz *High slew rate = 60V/uS *Low offset voltage = .5mV *NOTE: High current output not modeled. * ****************INPUT STAGE************** * IOS 2 1 50P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 1.0M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 2K R4 6 50 2K *Fp2=100MHz C4 5 6 3.9789E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 10MA ;Supply current EOS 7 1 POLY(1) 16 49 .5E-3 1 ;Input offset voltage R8 99 49 40K R9 49 50 40K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 3.13 D1 9 8 DX D2 10 9 DX V3 10 50 3.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 6.887E6 G1 98 9 5 6 2.74E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=54.6 HZ C3 98 11 29.149P * ***************POLE STAGE*************** * *Fp3=100 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.5915E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1.0E-8 L2 98 17 144.7M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 220U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 75 ;Output resistance D5 26 24 DX V6 26 22 0.63V R17 23 25 75 D6 25 27 DX V7 22 27 0.63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=1.25E-4 VTO=-2.00 IS=100E-12 N=3) * .ENDS * *////////////////////////////////////////////////////////// *LF411/A LOW OFFSET, LOW DRIFT JFET INPUT OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF411/NS 1 2 99 50 28 * *Features: *Fast settling time (.01%) = 2uS *High bandwidth = 3MHz *High slew rate = 10V/uS *Low offset voltage = .5mV *Low supply current = 1.8mA * ****************INPUT STAGE************** * IOS 2 1 25.0P ;Input offset current CI1 1 0 2.5P CI2 2 0 2.5P R1 1 3 5E11 R2 3 2 5E11 I1 99 4 1.0M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 2.33K R4 6 50 2.33K *Fp2=23 MHZ C4 5 6 1.485P * ***********COMMON MODE EFFECT*********** * I2 99 50 800UA ;Supply current EOS 7 1 POLY(1) 16 49 .8E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.429E4 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 *Fp1=18 HZ C3 98 11 884.194P * ***************POLE STAGE*************** * *Fp3=43.3 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.6756E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 144.7M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 30 ;Output resistance D5 26 24 DX V6 26 22 0.63V R17 23 25 30 D6 25 27 DX V7 22 27 0.63V V5 22 21 0.63 D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 1U ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=50E-12 N=3) * .ENDS * *////////////////////////////////////////////////////////// *LF412/A LOW OFFSET, LOW DRIFT DUAL JFET INPUT OP-AMP MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF412/NS 1 2 99 50 28 * *Features: *Fast settling time (.01%) = 2uS *High bandwidth = 3MHz *High slew rate = 10V/uS *Low offset voltage = 1mV *Low supply current = 1.8mA *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 25.0P ;Input offset current CI1 1 0 2.5P CI2 2 0 2.5P R1 1 3 5E11 R2 3 2 5E11 I1 99 4 1.0M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 2.33K R4 6 50 2.33K *Fp2=23 MHZ C4 5 6 1.485P * ***********COMMON MODE EFFECT*********** * I2 99 50 800UA ;Supply current EOS 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.429E4 G1 98 9 5 6 20E-3 R5 98 9 10MEG VA3 9 11 0 *Fp1=18 HZ C3 98 11 884.194P * ***************POLE STAGE*************** * *Fp3=43.3 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 3.6756E-15 * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 144.7M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 30 ;Output resistance D5 26 24 DX V6 26 22 0.63V R17 23 25 30 D6 25 27 DX V7 22 27 0.63V V5 22 21 0.63 D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 1U ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=50E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF451 Wide-Bandwidth JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF451/NS 1 2 99 50 28 * *Features: *Low input bias current = 50pA *High slew rate = 13V/uS *High input impedance = 1Tohm *Low input offset voltage = 5mV * ****************INPUT STAGE************** * IOS 2 1 25P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 1M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 2.33K R4 6 50 2.33K *Fp2=13.3 MHz C4 5 6 2.5679P * ***********COMMON MODE EFFECT*********** * I2 99 50 2.4MA ;Supply current EOS 7 1 POLY(1) 16 49 .3E-3 1 ;Input offset voltage R8 99 49 69.4K R9 49 50 69.4K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 2.765449E6 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=19 HZ C3 98 11 83.766P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 15.915M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 ;Supply current correction E1 99 23 99 9 1 R16 24 23 35 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 35 D6 25 27 DY V7 22 27 0.63V C9 23 22 .004U V5 22 21 0.63V D4 21 9 DX V4 20 22 0.63V D3 9 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=50E-12 N=3) * .ENDS *////////////////////////////////////////////////////////// *LF453 Wide-Bandwidth Dual JFET-Input OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LF453/NS 1 2 99 50 28 * *Features: *Low input bias current = 50pA *High slew rate = 13V/uS *High input impedance = 1Tohm *Low input offset voltage = 5mV *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************* * IOS 2 1 25P ;Input offset current R1 1 3 5E11 R2 3 2 5E11 I1 99 4 1M J1 5 2 4 JX J2 6 7 4 JX R3 5 50 2.33K R4 6 50 2.33K *Fp2=13.3 MHz C4 5 6 2.5679P * ***********COMMON MODE EFFECT*********** * I2 99 50 2.4MA ;Supply current EOS 7 1 POLY(1) 16 49 .3E-3 1 ;Input offset voltage R8 99 49 69.4K R9 49 50 69.4K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.13 D1 9 8 DX D2 10 9 DX V3 10 50 2.13 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 2.765449E6 G1 98 9 5 6 2E-3 R5 98 9 100MEG VA3 9 11 0 *Fp1=19 HZ C3 98 11 83.766P * *********COMMON-MODE ZERO STAGE********* * G4 98 16 3 49 1E-8 L2 98 17 15.915M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 ;Supply current correction E1 99 23 99 9 1 R16 24 23 35 ;Output resistance D5 26 24 DY V6 26 22 0.63V R17 23 25 35 D6 25 27 DY V7 22 27 0.63V C9 23 22 .004U V5 22 21 0.63V D4 21 9 DX V4 20 22 0.63V D3 9 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL JX PJF(BETA=9.201E-5 VTO=-2.33 IS=50E-12 N=3) * .ENDS * CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS * --------------------------------------------------------- *////////////////////////////////////////////////////////// *LMC660AM/AI/C CMOS Quad OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC660/NS 1 2 99 50 28 * *Features: *Operates from single supply *Rail-to-rail output swing *Ultra low input current = 40fA *Slew rate = 1.1V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * *****************INPUT STAGE************** * IOS 2 1 10F ;Input offset current CI1 1 0 2.5P CI2 2 0 2.5P I1 99 4 10U R1 1 3 500G R2 2 3 500G M1 4 2 5 99 MOSFET R3 5 50 141.42Kohm M2 4 7 6 99 MOSFET R4 6 50 141.42Kohm *Fp2=5 MHz C4 5 6 1.1254E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 360U ;Supply current EOS 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 350K R9 49 50 350K * *********GATE DRIVE LIMITING******** V2 8 98 5.37 D1 9 8 DX D2 10 9 DX V3 98 10 5.37 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.221879E11 G1 98 9 5 6 9.347095E-5 R5 98 9 21.39702G *Fp1=.8182 Hz C3 98 11 9.09091P VA3 9 11 0 * ************POLE/ZERO STAGE************* * *Fp=1 MHz, Fz=2.3 MHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 769.231K C5 14 13 8.9957E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 3 49 7.079458E-8 L2 98 17 7.958M R13 17 16 1K * **************OUTPUT STAGE************** * G0 98 29 13 49 1E-7 R0 98 29 1MEG F6 50 99 POLY(1) V7 37.9U 1 E1 99 23 99 49 1 D5 23 24 DX V6 26 24 .63 D6 25 23 DX V7 25 26 .63 G6 26 22 29 49 6.66667E-3 R16 26 22 1500 V8 30 22 1 D7 30 99 DX V9 22 31 .89 D8 50 31 DX VL3 22 28 .01U ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL MOSFET PMOS(LEVEL=2 KP=5E-6 VTO=-1.0) .ENDS *////////////////////////////////////////////////////////// *LPC660AM/AI/I CMOS Quad OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LPC660/NS 1 2 99 50 28 * *Features: *Operates from single supply *Rail-to-rail output swing *Ultra low input current = 40fA *Slew rate = 1.1V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * *****************INPUT STAGE************** * IOS 2 1 10F ;Input offset current CI1 1 0 2.5P CI2 2 0 2.5P I1 99 4 10U R1 1 3 500G R2 2 3 500G M1 4 2 5 99 MOSFET R3 5 50 141.42Kohm M2 4 7 6 99 MOSFET R4 6 50 141.42Kohm *Fp2=345 KHz C4 5 6 1.631P * ***********COMMON MODE EFFECT*********** * I2 99 50 25U ;Supply current EOS 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 640K R9 49 50 640K * *********GATE DRIVE LIMITING******** V2 8 98 5.37 D1 9 8 DX D2 10 9 DX V3 98 10 5.37 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 3.656256E11 G1 98 9 5 6 2.656074E-4 R5 98 9 3.765G *Fp1=.465 Hz C3 98 11 90.9091P VA3 9 11 0 * ************ZERO/POLE STAGE************* * *Fz=2.5 MHz, Fp=5.6 MHz G2 98 13 9 49 1E-6 R10 98 14 1.24MEG R11 14 13 1MEG L1 98 14 35.24M * *********COMMON-MODE ZERO STAGE********* * *Fpcm=600 Hz G4 98 16 3 49 7.079458E-8 L2 98 17 265.258M R13 17 16 1K * **************OUTPUT STAGE************** * G0 98 29 13 49 3E-8 R0 98 29 1MEG F6 50 99 POLY(1) V7 37.9U 1 E1 99 23 99 49 1 D5 23 24 DX V6 26 24 .63 D6 25 23 DX V7 25 26 .63 G6 26 22 29 49 6.66667E-3 R16 26 22 5000 V8 30 22 .66 D7 30 99 DX V9 22 31 .637 D8 50 31 DX VL3 22 28 .01U ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL MOSFET PMOS(LEVEL=2 KP=5E-6 VTO=-1.0) .ENDS *////////////////////////////////////////////////////////// *LMC662AM/AI/C CMOS Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC662/NS 1 2 99 50 28 * *Features: *Operates from single supply *Rail-to-rail output swing *Ultra low input current = 40fA *Slew rate = 1.1V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * *****************INPUT STAGE************** * IOS 2 1 10F ;Input offset current CI1 1 0 2.5P CI2 2 0 2.5P I1 99 4 10U R1 1 3 500G R2 2 3 500G M1 4 2 5 99 MOSFET R3 5 50 141.42Kohm M2 4 7 6 99 MOSFET R4 6 50 141.42Kohm *Fp2=5 MHz C4 5 6 1.1254E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 360U ;Supply current EOS 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 350K R9 49 50 350K * *********GATE DRIVE LIMITING******** V2 8 98 5.37 D1 9 8 DX D2 10 9 DX V3 98 10 5.37 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.221879E11 G1 98 9 5 6 9.347095E-5 R5 98 9 21.39702G *Fp1=.8182 Hz C3 98 11 9.09091P VA3 9 11 0 * ************POLE/ZERO STAGE************* * *Fp=1 MHz, Fz=2.3 MHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 769.231K C5 14 13 8.9957E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=20 KHz G4 98 16 3 49 7.079458E-8 L2 98 17 7.958M R13 17 16 1K * **************OUTPUT STAGE************** * G0 98 29 13 49 1E-7 R0 98 29 1MEG F6 50 99 POLY(1) V7 37.9U 1 E1 99 23 99 49 1 D5 23 24 DX V6 26 24 .63 D6 25 23 DX V7 25 26 .63 G6 26 22 29 49 6.66667E-3 R16 26 22 1500 V8 30 22 1 D7 30 99 DX V9 22 31 .89 D8 50 31 DX VL3 22 28 .01U ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL MOSFET PMOS(LEVEL=2 KP=5E-6 VTO=-1.0) .ENDS *////////////////////////////////////////////////////////// *LPC662AM/AI/I CMOS Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LPC662/NS 1 2 99 50 28 * *Features: *Operates from single supply *Rail-to-rail output swing *Ultra low input current = 40fA *Slew rate = 1.1V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * *****************INPUT STAGE************** * IOS 2 1 10F ;Input offset current CI1 1 0 2.5P CI2 2 0 2.5P I1 99 4 10U R1 1 3 500G R2 2 3 500G M1 4 2 5 99 MOSFET R3 5 50 141.42Kohm M2 4 7 6 99 MOSFET R4 6 50 141.42Kohm *Fp2=345 KHz C4 5 6 1.631P * ***********COMMON MODE EFFECT*********** * I2 99 50 25U ;Supply current EOS 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 640K R9 49 50 640K * *********GATE DRIVE LIMITING******** V2 8 98 5.37 D1 9 8 DX D2 10 9 DX V3 98 10 5.37 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 3.656256E11 G1 98 9 5 6 2.656074E-4 R5 98 9 3.765G *Fp1=.465 Hz C3 98 11 90.9091P VA3 9 11 0 * ************ZERO/POLE STAGE************* * *Fz=2.5 MHz, Fp=5.6 MHz G2 98 13 9 49 1E-6 R10 98 14 1.24MEG R11 14 13 1MEG L1 98 14 35.24M * *********COMMON-MODE ZERO STAGE********* * *Fpcm=600 Hz G4 98 16 3 49 7.079458E-8 L2 98 17 265.258M R13 17 16 1K * **************OUTPUT STAGE************** * G0 98 29 13 49 3E-8 R0 98 29 1MEG F6 50 99 POLY(1) V7 37.9U 1 E1 99 23 99 49 1 D5 23 24 DX V6 26 24 .63 D6 25 23 DX V7 25 26 .63 G6 26 22 29 49 6.66667E-3 R16 26 22 5000 V8 30 22 .66 D7 30 99 DX V9 22 31 .637 D8 50 31 DX VL3 22 28 .01U ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL MOSFET PMOS(LEVEL=2 KP=5E-6 VTO=-1.0) .ENDS *////////////////////////////////////////////////////////// *LMC6041 CMOS Single Micropower OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LMC6041/NS 1 2 99 50 28 * *Features: *Operates from single supply *Rail-to-rail output swing *Low supply current = 14uA *Ultra low input current = 2fA * ****************INPUT STAGE************** * IOS 2 1 1F ;Input offset current CI1 2 0 3P CI2 7 0 3P I1 99 4 10U R1 1 3 5000G R2 2 3 5000G M1 4 2 5 99 MOSFET R3 5 50 141.42Kohm M2 4 7 6 99 MOSFET R4 6 50 141.42Kohm *Fp2=100 KHz C4 5 6 5.627P * ***********COMMON MODE EFFECT*********** * I2 99 50 4U ;Supply current EOS 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 6.4MEG R9 49 50 6.4MEG * *********GATE DRIVE LIMITING******** V2 8 98 5.37 D1 9 8 DX D2 10 9 DX V3 98 10 5.37 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA3 0 0 0 1.943726E11 G1 98 9 5 6 1.445133E-4 R5 98 9 6.9198G *Fp1=.046 Hz C3 98 11 500P VA3 9 11 0 * ***************POLE STAGE*************** * *Fp=2.7 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 5.88463E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=800Hz G4 98 16 3 49 177.8E-9 L2 98 17 198.9M R13 17 16 1K * **************OUTPUT STAGE************** * G0 98 29 15 49 3.75E-8 R0 98 29 1MEG F6 50 99 POLY(1) V7 37.9U 1 E1 99 23 99 49 1 D5 23 24 DX V6 26 24 .63 D6 25 23 DX V7 25 26 .63 G6 26 22 29 49 2.666666E-3 R16 26 22 10K V8 30 22 .63 D7 30 99 DX V9 22 31 .63 D8 50 31 DX L3 22 28 500P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL MOSFET PMOS(LEVEL=2 KP=5E-6 VTO=-1.0) .ENDS * BIPOLAR BIPOLAR BIPOLAR BIPOLAR BIPOLAR BIPOLAR BIPOLAR BIPOLAR *////////////////////////////////////////////////////////// *LM118 OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM118/NS 1 2 99 50 28 * *Features: *Internal frequency compensation *High bandwidth = 15MHz *Minimum slew rate = 50V/uS *Low bias current = 250nA *Wide supply range = +-5V to +-20V * ****************INPUT STAGE************** * IOS 2 1 6N ;Input offset current R1 1 3 1.5MEG R2 3 2 1.5MEG I1 4 50 100U R3 99 5 517 R4 99 6 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=25 MHz C4 5 6 6.1569P * ***********COMMON MODE EFFECT*********** * I2 99 50 4.9M ;Supply current EOS 7 1 POLY(1) 16 49 4E-3 1 ;Input offset voltage R8 99 49 80.2K R9 49 50 80.2K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 3.0967E-4 0 596.674E-3 *Fp1=115 Hz R5 98 9 9.6877G C3 98 9 1.4286P * ************POLE/ZERO STAGE************* * *Fp=300 KHz, Fz=600 KHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 1MEG C6 14 13 2.6526E-13 * ***************POLE STAGE*************** * *Fp=55 MHz G3 98 15 13 49 1E-6 R12 98 15 1MEG C5 98 15 2.8937E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 1E-8 L2 98 17 53.1M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 30 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 30 D6 25 27 DX V7 22 27 .63V C9 23 22 100P V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=333.333) * .ENDS *////////////////////////////////////////////////////////// *LM124 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM124/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 3N ;Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U ;Supply current E0S 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 0.635 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 17.5 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P ;Output inductor RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *////////////////////////////////////////////////////////// *LM218 OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM218/NS 1 2 99 50 28 * *Features: *Internal frequency compensation *High bandwidth = 15MHz *Minimum slew rate = 50V/uS *Low bias current = 250nA *Wide supply range = +-5V to +-20V * ****************INPUT STAGE************** * IOS 2 1 6N ;Input offset current R1 1 3 1.5MEG R2 3 2 1.5MEG I1 4 50 100U R3 99 5 517 R4 99 6 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=25 MHz C4 5 6 6.1569P * ***********COMMON MODE EFFECT*********** * I2 99 50 4.9M ;Supply current EOS 7 1 POLY(1) 16 49 4E-3 1 ;Input offset voltage R8 99 49 80.2K R9 49 50 80.2K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 3.0967E-4 0 596.674E-3 *Fp1=115 Hz R5 98 9 9.6877G C3 98 9 1.4286P * ************POLE/ZERO STAGE************* * *Fp=300 KHz, Fz=600 KHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 1MEG C6 14 13 2.6526E-13 * ***************POLE STAGE*************** * *Fp=55 MHz G3 98 15 13 49 1E-6 R12 98 15 1MEG C5 98 15 2.8937E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 1E-8 L2 98 17 53.1M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 30 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 30 D6 25 27 DX V7 22 27 .63V C9 23 22 100P V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=333.333) * .ENDS *////////////////////////////////////////////////////////// *LM224 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM224/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 3N ;Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U ;Supply current E0S 7 1 POLY(1) 16 49 2E-3 1 ;Input offset voltage R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 .635 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 17.5 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P ;Output inductor RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *////////////////////////////////////////////////////////// *LM318 OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM318/NS 1 2 99 50 28 * *Features: *Internal frequency compensation *High bandwidth = 15MHz *Minimum slew rate = 50V/uS *Low bias current = 250nA *Wide supply range = +-5V to +-20V * ****************INPUT STAGE************** * IOS 2 1 30N ;Input offset current R1 1 3 1.5MEG R2 3 2 1.5MEG I1 4 50 100U R3 99 5 517 R4 99 6 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=25 MHz C4 5 6 6.1569P * ***********COMMON MODE EFFECT*********** * I2 99 50 4.9M ;Supply current EOS 7 1 POLY(1) 16 49 4E-3 1 ;Input offset voltage R8 99 49 80.2K R9 49 50 80.2K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 3.0967E-4 0 596.674E-3 *Fp1=115 Hz R5 98 9 9.6877G C3 98 9 1.4286P * ************POLE/ZERO STAGE************* * *Fp=300 KHz, Fz=600 KHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 1MEG C6 14 13 2.6526E-13 * ***************POLE STAGE*************** * *Fp=55 MHz G3 98 15 13 49 1E-6 R12 98 15 1MEG C5 98 15 2.8937E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 1E-8 L2 98 17 53.1M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 30 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 30 D6 25 27 DX V7 22 27 .63V C9 23 22 100P V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=333.333) * .ENDS * *////////////////////////////////////////////////////////// *LM324 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM324/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N ;Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U ;Supply current E0S 7 1 POLY(1) 16 49 2E-3 1 ;Input offset voltage R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 .635 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 17.5 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.27V D4 21 15 DX V4 20 22 0.27V D3 15 20 DX L3 22 28 500P ;Output inductor RL3 22 28 100K * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *////////////////////////////////////////////////////////// *LM358 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM358/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N ;Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U ;Supply current E0S 7 1 POLY(1) 16 49 2E-3 1 ;Input offset voltage R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 17.5 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 500P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS * *////////////////////////////////////////////////////////// *LM607/LM607A/LM607B OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM607/NS 1 2 99 50 28 * *Features: *Low Vos = 25 uV *High gain = 134 dB *High unity gain freq. = 1.8MHz *High slew rate = .7V/uS *Wide supply range = +-3V to +-18V * ****************INPUT STAGE************** * IOS 2 1 500P ;Input offset current R1 1 3 1MEG R2 3 2 1MEG I1 4 50 100U R3 5 99 517 R4 6 99 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=14 MHz C4 5 6 10.994P * ***********COMMON MODE EFFECT*********** * I2 99 50 900UA ;Supply current E0S 7 1 POLY(1) 16 49 15E-6 1 ;Input offset voltage R8 99 49 2MEG R9 49 50 2MEG * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.83 D1 9 8 DX D2 10 9 DX V3 10 50 1.83 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;VCVS @ Unity gain G1 98 9 5 6 2E-3 *Fp1=.14 Hz R5 98 9 5.116G C3 98 9 222.222P * ************POLE/ZERO STAGE************* * *Fp=500 KHz, Fz=800 KHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 1.666MEG C5 14 13 1.194E-13 * ***************POLE STAGE*************** * *Fp=14 MHz G3 98 15 13 49 1E-6 R12 98 15 1MEG C6 98 15 1.1368E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=200 Hz G4 98 16 3 49 1E-10 L2 98 17 795.8M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 80U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 50 ;Output resistance D5 26 24 DX V6 26 22 0.65V R17 23 25 50 D6 25 27 DX V7 22 27 0.65V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 500P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=5.0E4) * .ENDS * *////////////////////////////////////////////////////////// *LM627 PRECISION OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM627/NS 1 2 99 50 28 * *Features: *Low Vos = 25 uV *High gain = 134 dB *High unity gain freq. = 14 MHz *High slew rate = 4.5V/uS *Wide supply range = +-3.5V to +-18V * ****************INPUT STAGE************** * IOS 2 1 2N ;Input offset current R1 1 3 10G R2 3 2 10G I1 4 50 100U R3 5 99 517 R4 6 99 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=25.3 MHz C4 5 6 6.084P * ***********COMMON MODE EFFECT*********** * I2 99 50 2.9MA ;Supply current E0S 7 1 POLY(1) 16 49 15E-6 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.83 D1 9 8 DX D2 10 9 DX V3 10 50 1.83 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 5 6 2.1E-3 *Fp1=1.49 Hz R5 98 9 4.807G C3 98 9 22.2222P * ************POLE/ZERO STAGE************* * *Fp=300 KHz, Fz=1 MHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 428.571K C5 14 13 3.7136E-13 * ***************POLE STAGE*************** * *Fp=30 MHz G3 98 15 13 49 1E-6 R12 98 15 1MEG C6 98 15 5.305E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=300 Hz G4 98 16 3 49 1E-10 L2 98 17 530.5M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 220U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 50 ;Output resistance D5 26 24 DX V6 26 22 0.63V R17 23 25 50 D6 25 27 DX V7 22 27 0.63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 500P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=1.6667E4) * .ENDS * *////////////////////////////////////////////////////////// *LM637 PRECISION OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM637/NS 1 2 99 50 28 * *Features: *Low Vos = 25 uV *High gain = 134 dB *High unity gain freq. = 65 MHz *High slew rate = 14V/uS *Wide supply range = +-3.5V to +-18V * ****************INPUT STAGE************** * IOS 2 1 2N ;Input offset current R1 1 3 10G R2 3 2 10G I1 4 50 100U R3 5 99 517 R4 6 99 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=50 MHz C4 5 6 3.0784P * ***********COMMON MODE EFFECT*********** * I2 99 50 2.9MA ;Supply current E0S 7 1 POLY(1) 16 49 15E-6 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.83 D1 9 8 DX D2 10 9 DX V3 10 50 1.83 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 5 6 3.7E-3 F1 9 98 POLY(1) VA3 0 0 0 9.24E7 ;Slew compensation *Fp1=10 Hz R5 98 9 2.7056G C3 98 11 5.8824P VA3 9 11 0 * ************POLE/ZERO STAGE************* * *Fp=300 KHz, Fz=450 KHz G2 98 13 9 49 1E-6 R10 98 13 1MEG R11 98 14 2MEG C6 14 13 1.768E-13 * ***************POLE STAGE**************** * *Fp=50 MHz G3 98 15 13 49 1E-6 R12 98 15 1MEG C5 98 15 3.1831E-15 * ***************POLE STAGE**************** * *Fp=80 MHz G5 98 18 15 49 1E-6 R14 98 18 1MEG C7 98 18 1.9894E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=2 KHz G4 98 16 3 49 1E-10 L2 98 17 79.6M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction E1 99 23 99 18 1 R16 24 23 50 ;Output resistance D5 26 24 DX V6 26 22 0.61V R17 23 25 50 D6 25 27 DX V7 22 27 0.61V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 .02U ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=1.67E4) * .ENDS * *////////////////////////////////////////////////////////// *LM741/A/C/E OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM741/NS 1 2 99 50 28 * *Features: *Improved performance over industry standards *Plug-in replacement for LM709,LM201,MC1439,748 *Input and output overload protection * ****************INPUT STAGE************** * IOS 2 1 20N ;Input offset current R1 1 3 250K R2 3 2 250K I1 4 50 100U R3 5 99 517 R4 6 99 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=2.55 MHz C4 5 6 60.3614P * ***********COMMON MODE EFFECT*********** * I2 99 50 1.6MA ;Supply current E0S 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 40K R9 49 50 40K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.63 D1 9 8 DX D2 10 9 DX V3 10 50 1.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 5 6 2.1E-3 *Fp1=5 Hz R5 98 9 95.493MEG C3 98 9 333.33P * ***************POLE STAGE*************** * *Fp=30 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 5.3052E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=300 Hz G4 98 16 3 49 3.1623E-8 L2 98 17 530.5M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 450U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 25 ;Output resistance D5 26 24 DX V6 26 22 0.65V R17 23 25 25 D6 25 27 DX V7 22 27 0.65V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=625) * .ENDS *////////////////////////////////////////////////////////// *LM2902 QUAD OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM2902/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/4 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N ;Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U ;Supply current E0S 7 1 POLY(1) 16 49 2E-3 1 ;Input offset voltage R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 17.5 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 500P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *////////////////////////////////////////////////////////// *LM2904 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM2904/NS 1 2 99 50 28 * *Features: *Eliminates need for dual supplies *Large DC voltage gain = 100dB *High bandwidth = 1MHz *Low input offset voltage = 2mV *Wide supply range = +-1.5V to +-16V * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * Output crossover distortion with dual supplies * is not modeled. * ****************INPUT STAGE************** * IOS 2 1 5N ;Input offset current R1 1 3 500K R2 3 2 500K I1 99 4 100U R3 5 50 517 R4 6 50 517 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=1.2 MHz C4 5 6 128.27P * ***********COMMON MODE EFFECT*********** * I2 99 50 75U ;Supply current E0S 7 1 POLY(1) 16 49 2E-3 1 ;Input offset voltage R8 99 49 60K R9 49 50 60K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459 *Fp1=7.86 Hz R5 98 9 101.2433MEG C3 98 9 200P * ***************POLE STAGE*************** * *Fp=2 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.9577E-14 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 5.6234E-8 L2 98 17 15.9M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 300U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 17.5 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 17.5 D6 25 27 DX V7 22 27 .63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 500P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX PNP(BF=1.111E3) * .ENDS *////////////////////////////////////////////////////////// *LM6118/A Fast Settling Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6118/NS 1 2 99 50 28 * *Features: *Low offset voltage = .2mV *High bandwidth = 17MHz *Slew rate (Av=-1) = 140V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 20N ;Input offset current CI1 1 0 2.5P CI2 2 0 2.5P R1 1 3 3.125G R2 3 2 3.125G I1 4 50 40U R3 99 5 2.54K R4 99 6 2.54K Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 1.25K R44 46 4 1.25K *Fp2=30 MHz C4 5 6 1.0433P * ***********COMMON MODE EFFECT*********** * I2 99 50 2.71M ;Supply current EOS 7 1 POLY(1) 16 49 .2E-3 1 ;Input offset voltage R8 99 49 71.4K R9 49 50 71.4K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 5E-3 0 5.056 *Fp1=38.24 Hz R5 98 9 100MEG C3 98 9 41.62P * ***************POLE STAGE*************** * *Fp=110 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.4469E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=6 KHz G4 98 16 3 49 1E-8 L2 98 17 26.526M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 10 ;Output resistance D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 .001U V7 22 27 .63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL QX NPN(BF=100) * .ENDS *////////////////////////////////////////////////////////// *LM6161 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6161/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 50MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 1.5P CI2 2 0 1.5P R1 1 3 162.5K R2 3 2 162.5K I1 4 50 1M R3 99 5 651.7 R4 99 6 651.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 600 R44 46 4 600 *Fp2=200 MHz C4 5 6 6.1054E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 5E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.335 D1 9 8 DX D2 10 9 DX V3 10 50 2.155 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA1 0 0 0 20 G1 98 9 POLY(1) 5 6 0 2.9E-3 0 5.062E-4 *Fp1=23.52 KHz R5 98 9 1MEG C3 98 9 6.7668P * ***************POLE STAGE*************** * *Fp=203 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.84E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=200 KHz G4 98 16 3 49 1.9952E-8 L2 98 17 795.77U R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 15 1 R16 24 23 10 ;Output resistance D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 500P V7 22 27 .63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL QX NPN(BF=250) * .ENDS *////////////////////////////////////////////////////////// *LM6162 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6162/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 100MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 2P CI2 2 0 2P R1 1 3 90K R2 3 2 90K I1 4 50 1M R3 99 5 351.7 R4 99 6 351.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 300 R44 46 4 300 *Fp2=230 MHz C4 5 6 9.8376E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA1 0 0 0 .85 G1 98 9 POLY(1) 5 6 0 6.5E-3 0 8.646E-3 *Fp1=17.935 KHz R5 98 9 1MEG C3 98 9 8.874P * ***************POLE STAGE*************** * *Fp=230 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 6.9198E-16 * ***************POLE STAGE*************** * *Fp=250 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 6.3662E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 1E-8 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 200P V7 22 27 .63V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=227.3) * .ENDS *////////////////////////////////////////////////////////// *LM6164 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6164/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 175MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 50K R2 3 2 50K I1 4 50 1M R3 99 5 201.7 R4 99 6 201.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 150 R44 46 4 150 *Fp2=190 MHz C4 5 6 2.0765P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 2E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA1 0 0 0 3.4 G1 98 9 POLY(1) 5 6 0 9.0E-3 0 10.6E-3 *Fp1=25.1 KHz R5 98 9 1MEG C3 98 9 6.3408P * ***************POLE STAGE*************** * *Fp=190 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-16 * ***************POLE STAGE*************** * *Fp=203 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 7.8401E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 5.6234E-9 L2 98 17 53.052E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *////////////////////////////////////////////////////////// *LM6165 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6165/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 725MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 6P CI2 2 0 6P R1 1 3 10K R2 3 2 10K I1 4 50 1M R3 99 5 51.7 R4 99 6 51.7 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=120 MHz C4 5 6 12.827P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(2) VA1 VA3 0 0 0 0 0 0 4.25 0 0 4.978143E5 G1 98 9 POLY(1) 5 6 0 38.0E-3 *Fp1=25.1 KHz R5 98 9 1MEG VA3 9 11 0 C3 98 11 3.897P * ***************POLE STAGE*************** * *Fp=120 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.3263E-15 * ***************POLE STAGE*************** * *Fp=124 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 1.2835E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 7.94328E-9 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *////////////////////////////////////////////////////////// *LM6218/A Fast Settling Dual OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6218/NS 1 2 99 50 28 * *Features: *Low offset voltage = .2mV *High bandwidth = 17MHz *Slew rate (Av=-1) = 140V/uS * *NOTE: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************INPUT STAGE************** * IOS 2 1 20N ;Input offset current CI1 1 0 2.5P CI2 2 0 2.5P R1 1 3 3.125G R2 3 2 3.125G I1 4 50 40U R3 99 5 2.54K R4 99 6 2.54K Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 1.25K R44 46 4 1.25K *Fp2=30 MHz C4 5 6 1.0433P * ***********COMMON MODE EFFECT*********** * I2 99 50 2.71M ;Supply current EOS 7 1 POLY(1) 16 49 .2E-3 1 ;Input offset voltage R8 99 49 71.4K R9 49 50 71.4K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 2.63 D1 9 8 DX D2 10 9 DX V3 10 50 2.63 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter G1 98 9 POLY(1) 5 6 0 5E-3 0 5.056 *Fp1=38.24 Hz R5 98 9 100MEG C3 98 9 41.62P * ***************POLE STAGE*************** * *Fp=110 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.4469E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=6 KHz G4 98 16 3 49 1E-8 L2 98 17 26.526M R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction E1 99 23 99 15 1 R16 24 23 10 ;Output resistance D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 .001U V7 22 27 .63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL QX NPN(BF=100) * .ENDS *////////////////////////////////////////////////////////// *LM6261 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6261/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 50MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 1.5P CI2 2 0 1.5P R1 1 3 162.5K R2 3 2 162.5K I1 4 50 1M R3 99 5 651.7 R4 99 6 651.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 600 R44 46 4 600 *Fp2=200 MHz C4 5 6 6.1054E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 5E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.335 D1 9 8 DX D2 10 9 DX V3 10 50 2.155 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA1 0 0 0 20 G1 98 9 POLY(1) 5 6 0 2.9E-3 0 5.062E-4 *Fp1=23.52 KHz R5 98 9 1MEG C3 98 9 6.7668P * ***************POLE STAGE*************** * *Fp=203 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.84E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=200 KHz G4 98 16 3 49 1.9952E-8 L2 98 17 795.77U R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 15 1 R16 24 23 10 ;Output resistance D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 500P V7 22 27 .63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL QX NPN(BF=250) * .ENDS *////////////////////////////////////////////////////////// *LM6262 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6262/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 100MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 2P CI2 2 0 2P R1 1 3 90K R2 3 2 90K I1 4 50 1M R3 99 5 351.7 R4 99 6 351.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 300 R44 46 4 300 *Fp2=230 MHz C4 5 6 9.8376E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA1 0 0 0 .85 G1 98 9 POLY(1) 5 6 0 6.5E-3 0 8.646E-3 *Fp1=17.935 KHz R5 98 9 1MEG C3 98 9 8.874P * ***************POLE STAGE*************** * *Fp=230 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 6.9198E-16 * ***************POLE STAGE*************** * *Fp=250 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 6.3662E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 1E-8 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 200P V7 22 27 .63V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=227.3) * .ENDS *////////////////////////////////////////////////////////// *LM6264 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6264/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 175MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 50K R2 3 2 50K I1 4 50 1M R3 99 5 201.7 R4 99 6 201.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 150 R44 46 4 150 *Fp2=190 MHz C4 5 6 2.0765P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 2E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA1 0 0 0 3.4 G1 98 9 POLY(1) 5 6 0 9.0E-3 0 10.6E-3 *Fp1=25.1 KHz R5 98 9 1MEG C3 98 9 6.3408P * ***************POLE STAGE*************** * *Fp=190 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-16 * ***************POLE STAGE*************** * *Fp=203 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 7.8401E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 5.6234E-9 L2 98 17 53.052E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *////////////////////////////////////////////////////////// *LM6265 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6265/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 725MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 6P CI2 2 0 6P R1 1 3 10K R2 3 2 10K I1 4 50 1M R3 99 5 51.7 R4 99 6 51.7 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=120 MHz C4 5 6 12.827P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(2) VA1 VA3 0 0 0 0 0 0 4.25 0 0 4.978143E5 G1 98 9 POLY(1) 5 6 0 38.0E-3 *Fp1=25.1 KHz R5 98 9 1MEG VA3 9 11 0 C3 98 11 3.897P * ***************POLE STAGE*************** * *Fp=120 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.3263E-15 * ***************POLE STAGE*************** * *Fp=124 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 1.2835E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 7.94328E-9 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *////////////////////////////////////////////////////////// *LM6361 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6361/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 50MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 1.5P CI2 2 0 1.5P R1 1 3 162.5K R2 3 2 162.5K I1 4 50 1M R3 99 5 651.7 R4 99 6 651.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 600 R44 46 4 600 *Fp2=200 MHz C4 5 6 6.1054E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 5E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.335 D1 9 8 DX D2 10 9 DX V3 10 50 2.155 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA1 0 0 0 20 G1 98 9 POLY(1) 5 6 0 2.9E-3 0 5.062E-4 *Fp1=23.52 KHz R5 98 9 1MEG C3 98 9 6.7668P * ***************POLE STAGE*************** * *Fp=203 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 7.84E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=200 KHz G4 98 16 3 49 1.9952E-8 L2 98 17 795.77U R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 15 1 R16 24 23 10 ;Output resistance D5 26 24 DY V6 26 22 .63V R17 23 25 10 D6 25 27 DY C9 23 22 500P V7 22 27 .63V V5 22 21 0.63V D4 21 15 DX V4 20 22 0.63V D3 15 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL DY D(IS=1E-25 N=.5) .MODEL QX NPN(BF=250) * .ENDS *////////////////////////////////////////////////////////// *LM6362 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6362/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 100MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 2P CI2 2 0 2P R1 1 3 90K R2 3 2 90K I1 4 50 1M R3 99 5 351.7 R4 99 6 351.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 300 R44 46 4 300 *Fp2=230 MHz C4 5 6 9.8376E-13 * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 3E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA1 0 0 0 .85 G1 98 9 POLY(1) 5 6 0 6.5E-3 0 8.646E-3 *Fp1=17.935 KHz R5 98 9 1MEG C3 98 9 8.874P * ***************POLE STAGE*************** * *Fp=230 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 6.9198E-16 * ***************POLE STAGE*************** * *Fp=250 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 6.3662E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 1E-8 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 200P V7 22 27 .63V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=227.3) * .ENDS *////////////////////////////////////////////////////////// *LM6364 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6364/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 175MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 3P CI2 2 0 3P R1 1 3 50K R2 3 2 50K I1 4 50 1M R3 99 5 201.7 R4 99 6 201.7 Q1 5 2 45 QX Q2 6 7 46 QX R43 45 4 150 R44 46 4 150 *Fp2=190 MHz C4 5 6 2.0765P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 2E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(1) VA1 0 0 0 3.4 G1 98 9 POLY(1) 5 6 0 9.0E-3 0 10.6E-3 *Fp1=25.1 KHz R5 98 9 1MEG C3 98 9 6.3408P * ***************POLE STAGE*************** * *Fp=190 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 8.3766E-16 * ***************POLE STAGE*************** * *Fp=203 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 7.8401E-16 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=3 KHz G4 98 16 3 49 5.6234E-9 L2 98 17 53.052E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS *////////////////////////////////////////////////////////// *LM6365 High Speed OP-AMP MACRO-MODEL *////////////////////////////////////////////////////////// * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | * | | | | | .SUBCKT LM6365/NS 1 2 99 50 28 * *Features: *Low supply current = 5mA *High bandwidth = 725MHz *High slew rate = 300V/uS * ****************INPUT STAGE************** * IOS 2 1 150N ;Input offset current CI1 1 0 6P CI2 2 0 6P R1 1 3 10K R2 3 2 10K I1 4 50 1M R3 99 5 51.7 R4 99 6 51.7 Q1 5 2 4 QX Q2 6 7 4 QX *Fp2=120 MHz C4 5 6 12.827P * ***********COMMON MODE EFFECT*********** * I2 99 50 4M ;Supply current EOS 7 1 POLY(1) 16 49 1E-3 1 ;Input offset voltage R8 99 49 80K R9 49 50 80K * *********OUTPUT VOLTAGE LIMITING******** V2 99 8 1.43 D1 9 8 DX D2 10 9 DX V3 10 50 2.23 * **************SECOND STAGE************** * EH 99 98 99 49 1 ;Level shifter F1 9 98 POLY(2) VA1 VA3 0 0 0 0 0 0 4.25 0 0 4.978143E5 G1 98 9 POLY(1) 5 6 0 38.0E-3 *Fp1=25.1 KHz R5 98 9 1MEG VA3 9 11 0 C3 98 11 3.897P * ***************POLE STAGE*************** * *Fp=120 MHz G3 98 15 9 49 1E-6 R12 98 15 1MEG C5 98 15 1.3263E-15 * ***************POLE STAGE*************** * *Fp=124 MHz G5 98 18 15 49 1E-6 R15 98 18 1MEG C6 98 18 1.2835E-15 * *********COMMON-MODE ZERO STAGE********* * *Fpcm=10 KHz G4 98 16 3 49 7.94328E-9 L2 98 17 15.915E-3 R13 17 16 1K * **************OUTPUT STAGE************** * F6 50 99 POLY(1) V6 200U 1 ;Supply current correction VA1 99 93 0 E1 93 23 99 18 1 R16 24 23 10 ;Output resistance D5 26 24 DX V6 26 22 .63V R17 23 25 10 D6 25 27 DX C9 23 22 500P V7 22 27 .63V V5 22 21 0.63V D4 21 18 DX V4 20 22 0.63V D3 18 20 DX L3 22 28 100P ;Output inductor * ***************MODELS USED************** * .MODEL DX D(IS=1E-15) .MODEL QX NPN(BF=200) * .ENDS