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Моделюють ризики, вивчають наслідки, прогнозують майбутнє Інформація КП чт, 12/05/2024 - 13:11

Junction field-effect transistors (JFETs) usually require some reverse bias voltage to be applied to a gate terminal.

In HF and UHF applications, this bias is often provided using the voltage across the source resistor Rs (Figure 1).

Figure 1: JFETs typically require some reverse bias across the gate terminal and in HF/UHF applications, this is often provided using the voltage across resistor Rs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Barring the evident lack of efficiency, such approach has other shortcomings as well:

• The drain current has statistical dispersion, so to get a target value of the current some circuit adjustment is required.
• The drain current may depend on temperature or power fluctuations.
• To achieve an acceptable low source impedance, several capacitors Cs have to be used.
• To maintain the same headroom a higher power voltage is required.
• The lack of direct contact with the ground plane means worse cooling of the transistor, which is crucial for power applications.

The circuit in Figure 2 is free of all these. It consists of a control loop which produces control voltage of negative polarity for n-channel JFET amplifier.

Figure 2: A control loop that produces control voltage of negative polarity for n-channel JFET amplifier in HF and UHF applications.

The circuit uses two infrared LEDs IR333C (diameter = 5 mm) in a self-made photocoupler. Two such LEDs placed face-to-face in an appropriate PVC tube about 12 mm long, that’s all. One such device produces 0.81 V @ Iled < 4 mA, which is quite sufficient for the HEMT FHX35LG, for example.

Of course, if you need higher voltage, several such devices can be simply cascaded.

The main amplification in the loop is performed by the JFET itself. Its value is about gm * R1, where gm is a transconductance of Q1.

The transistor pair Q2 and Q3 compares the voltage drops on the resistors R1 and R2 making them equal. Hence, by changing the ratio R2:R3 you can set the working point you need:

Id = Vdd * R2 / ((R2 + R3) * R1)

As we can see, the drain current (Id) still depends on power voltage (Vdd). To avoid this dependence, we can replace resistor R2 with a Zener diode, then:

Id = Vz / R1

 —Peter Demchenko studied math at the University of Vilnius and has worked in software development.

 Related Content

• JFET-based dc/dc converter operates from 300-mV supply
• Input bias current of CMOS and JFET amplifiers
• Your friend, the JFET
• Discrete audio amplifier basics – Part 2: JFETs, MOSFETs and other circuit configurations
• Adaptable pullup

The post Bias for HF JFET appeared first on EDN.

During electrical design process, certain design choices need to be made. One example is USB C type connector-based design with a straddle-mount connector. In such scenario, the overall PCB thickness is constrained while using a straddle-mount connector whose thickness governs the overall thickness. For historical reasons, the standard PCB thickness is 0.063” (1.57 mm).

Before the advent of PCBs, transistor-based electronics were often assembled using a method called breadboarding, which involved using wood as a substrate. However, wood was fragile, leading to delicate assemblies. To address this, bakelite sheets, commonly used on workbench surfaces, became the standard substrate for electronic assemblies, with a thickness of 1/16 inch, marking the beginning of PCBs at this thickness.

Figure 1 A PCB cross section is shown with a straddle-mount type connector. Source: Wurth Elektronik

Take the example of Wurth Elektronik’s USB 3.1 plug, a straddle-mount connector with part number 632712000011. The part datasheet recommends a PCB thickness of 0.8 mm/0.031” for an optimal use. This board thickness is common among various board fabrication houses. The 0.031” board is relatively easy to fabricate as many fab houses do a 6-layer PCB with 1 Oz copper on each layer.

However, designing and working with thin PCBs presents several challenges. One of the primary concerns is their mechanical fragility. Thin PCBs are more flexible and prone to bending or warping, making them difficult to handle during assembly and more susceptible to damage during handling. The handling includes pick and place assembly process, holes drilling, in-circuit testing (ICT) as well as functional probes during the functional testing.

The second level of handling is by the end user, for example dropping the device containing the PCB assembly (PCBA). Additionally, thin PCBs often requires specialized manufacturing processes and materials, leading to increased production costs. Component placement becomes more critical as well, as traces may need to be positioned closer together, increasing the risk of short circuits and signal interference.

Furthermore, thin PCBs face challenges in heat dissipation due to their reduced thermal mass. Addressing these challenges demands careful consideration during the design, manufacturing, and assembly stages to ensure the reliability and performance of the final product.

These issues are especially critical when a designer mounts a ball grid array (BGA) component on a 0.031” thickness board. Most of major fabrication houses recommend a minimum thickness of 0.062” when BGAs are mounted on the board.

How to test durability

The mechanical durability of PCB assemblies is generally assessed using a drop test. Drop test requirements for a PCBA typically include specifying the drop height, drop surface, number of drops, orientation during the drop, acceptance criteria, and testing standards. The drop height is the distance from which the PCBA will be dropped, typically ranging from 30 to 48 inches, depending on the application and industry standards.

The drop surface, such as concrete or wood, is also defined. Manufacturers determine the number of drops the PCBA must withstand, usually between 3 to 6 drops. The orientation of the PCBA during the drop, whether face down, face up, or on an edge or corner, is also specified. Acceptance criteria, such as functionality after the drop and any visible damage, are clearly defined.

Testing standards like IPC-TM-650 or specific customer requirements guide the testing process. For a medical device, the drop test requirements are governed by section 15.3.4.1 of IEC 60601-1 Third Edition 2005-12. By establishing these requirements, manufacturers ensure that their PCBAs and products are robust enough to withstand real-world use and maintain functionality even after being subjected to drops and impacts.

The soldering joint might not be captured during a drop test until a functional failure is observed. The BGA can fail due to poor assembly-related issues like the thermal stresses during soldering or poor soldering joint quality. A thin board weakens due to excessive mechanical shock and vibration assembly.

These defects can be captured during a drop test as the BGA part may not withstand the stresses encountered during a drop test, as shown in the figures below. The BGA failures can be inspected using X-ray, optical inspection, or electrical testing. A detailed analysis may be performed using cross section analysis using scanning electron microscopy (SEM).

Figure 2 The BGA solder joint shows a line crack. Source: Keyence

Figure 3 The above image displays a cross section of a healthy BGA. Source: Keyence

Figure 4 Here is a view of some of the BGA failure modes. Source: Semlabs

How to fix BGA failure on thin PCBs

Pad cratering is the fracturing of laminate under Cu pads of surface mount components, which often occurs during mechanical events. The initial crack can propagate, causing electrically open circuits by affecting adjacent Cu conducting lines. It’s more common in lead-free assemblies due to different laminate materials. Mitigation involves reducing stress on the laminate or using stronger, more pad cratering-resistant materials.

The issue can be fixed by mechanically stretching the PCB or changing the laminate material. It can be done with any of the following steps.

• Thinner boards are more prone to warping and may require additional fixturing (stiffeners or work board holders) to process on the manufacturing line if the requirements below are not met. A PCB stiffener is not an integral part of the circuit board; rather, it’s an external structure that offers mechanical support to the board.

Figure 5 An aluminum bar is shown as a mechanical PCB stiffener. Source: Compufab

• Corner adhesive/epoxy on the BGA corners or use BGA underfill. For example, an adhesive that can be used for this purpose is Zymet UA-3307-B Edgebond, Korapox 558 or Eccobond 286. The epoxy along the BGA corners or as an underfill strengthens the PCB, thereby preventing PCB flexion and hence the failure.
• Strict limitations on board flexure during circuit board assembly operations. For instance, supporting the PCB during handling operation like via hole drilling, pick and place, ICT, or functional testing with flying probes.
• Matching the recommended soldering profile of the BGA. The issue can be made worse if the BGA manufacture’s recommended soldering profile is not followed, resulting in cold solder joints. There should be enough thermocouples on the PCB panel to monitor the PCB temperature.
• Ensure that the BGA pad size is as per manufactures recommendation.

Managing thin PCB challenges

A thin PCB (0.031”) can weaken the PCB assembly, thereby making it susceptible to mechanical and thermal forces. And the challenges are unique when mounting a BGA to the thin PCB.

However, the design challenges and risks can be managed by carefully controlling the PCB handling processes and then strengthening the thin PCB with design solutions discussed in this article.

Editor’s Note: The views expressed in the article are author’s personal opinion.

Jagbir Singh is a staff electrical engineer for robotics at Smith & Nephew.

Related Content

• PCB design basics
• Trends and Challenges in PCB Manufacturing
• Selecting PCB materials for high-frequency applications
• Making efficient use of BGA signal routing in PCB designs
• BGA partitioning, PCB layout are crucial to video system design

The post Thin PCBs: Challenges with BGA packages appeared first on EDN.

Starting last year, as I mentioned at writeup publication time, EDN asked me to do yearly coverage of Google’s (or is that Alphabet’s? whatevah) I/O developer conference, as I’d already long been doing for Apple’s WWDC developer-tailored equivalent event, and on top of my ongoing throughout-the-year coverage of notable Google product announcements:

• Smartphones and smartwatches and their Android O/S foundations
• Various form factor computing platforms and their Chrome OS origins
• New and evolved processor architectures for all of these plus “cloud” servers
• etc…

And, as I also covered extensively a year ago, AI ended up being the predominant focus of Google I/O’s 2023 edition. Here’s part of the upfront summary of last year’s premier event coverage (which in part explains the rationalization for the yearly coverage going forward):

Deep learning and other AI operations…unsurprisingly were a regularly repeated topic at Wednesday morning’s keynote and, more generally, throughout the multi-day event. Google has long internally developed various AI technologies and products based on them—the company invented the transformer (the “T” in “GPT”) deep learning model technique now commonly used in natural language processing, for example—but productizing those research projects gained further “code red” urgency when Microsoft, in investment partnership with OpenAI, added AI-based enhancements to its Bing search service, which competes with Google’s core business. AI promises, as I’ve written before, to revolutionize how applications and the functions they’re based on are developed, implemented and updated. So, Google’s ongoing work in this area should be of interest even if your company isn’t one of Google’s partners or customers.

And unsurprisingly, given Google’s oft-stated, at the time, substantial and longstanding planned investment in various AI technologies and products and services based on them, AI was again the predominant focus at this year’s event, which took place earlier today as I write these words, on Tuesday, May 14:

But I’m getting ahead of myself…

The Pixel 8a

Look back at Google’s Pixel smartphone family history and you’ll see a fairly consistent cadence:

• One or several new premium model(s) launched in the fall of a given year, followed by (beginning with the Pixel 3 generation, to be precise)
• one (or, with the Pixel 4, two) mainstream “a” variant(s) a few calendar quarters later

The “a” variants are generally quite similar to their high-end precursors, albeit with feature set subtractions and other tweaks reflective of their lower price points (along with Google’s ongoing desire to still turn a profit, therefore the lower associated bill of materials costs). And for the last several years, they’ve been unveiled at Google I/O, beginning with the Pixel 6a, the mainstream variant of the initial Pixel 6 generation based on Google-developed SoCs, which launched at the 2022 event edition. The company had canceled Google I/O in 2020 due to the looming pandemic, and 2021 was 100% virtual and was also (bad-pun-intended) plagued by ongoing supply chain issues, so mebbe they’d originally planned this cadence earlier? Dunno.

The new Pixel 8a continues this trend, at least from feature set foundation and optimization standpoints (thicker display bezels, less fancy-pants rear camera subsystem, etc.). And by the way, please put in proper perspective reviewers who say things like “why would I buy a Pixel 8a when I can get a Pixel 8 for around the same price?” They’re not only comparing apples to oranges; they’re also comparing old versus new fruit (this is not an allusion to Apple; that’s in the next paragraph). The Pixel 8 and 8 Pro launched seven months ago, and details on the Pixel 9 family successors are already beginning to leak. What you’re seeing are retailers promo-pricing Pixel 8s to clear out inventory, making room for Pixel 9 successors to come soon. And what these reviewers are doing is comparing them against brand-new list-price Pixel 8as. In a few months, order will once again be restored to the universe. That all said, to be clear, if you need a new phone now, the Pixel 8 is a compelling option.

But here’s the thing…this year, the Pixel 8a was unveiled a week prior to Google I/O, and even more notably, right on top of Apple’s most recent “Let Loose” product launch party. Why? I haven’t yet seen a straight answer from Google, so here are some guesses:

• It was an in-general attempt by Google to draw attention away from (or at least mute the enthusiasm for) Apple and its comparatively expensive (albeit non-phone) widgets
• Specifically, someone at Google had gotten a (mistaken) tip that Apple might roll out one (or a few) iPhone(s) at the event and decided to proactively queue up a counterpunch
• Google had so much else to announce at I/O this year that they, not wanting the Pixel 8a to get lost in all the noise, decided to unveil it ahead of time instead.
• They saw all the Pixel 8a leaks and figured “oh, what the heck, let’s just let ‘er rip”.

The Pixel Tablet (redux)

But that wasn’t the only thing that Google announced last week, on top of Apple’s news. And in this particular case the operative term is relaunched, and the presumed reasoning is, if anything, even more baffling. Go back to my year-back coverage, and you’ll see that Google launched the Tensor G2-based Pixel Tablet at $499 (128GB, 255GB for $100 more), complete with a stand that transforms it into an Amazon Echo Show-competing (and Nest Hub-succeeding) smart display:

Well, here’s the thing…Google relaunched the very same thing last week, at a lower price point ($399), but absent the stand in this particular variant instance (the stand-inclusive product option is still available at $499). It also doesn’t seem that you can subsequently buy the stand, more accurately described as a dock (since it also acts as a charger and embeds speakers that reportedly notably boost sound quality), separately. That all, said, the stand-inclusive Pixel Tablet is coincidentally (or not) on sale at Woot! for $379.99 as I type these words, so…

And what explains this relaunch? Well:

• Apple also unveiled tablets that same day last week, at much higher prices, so there’s the (more direct in this case, versus the Pixel 8a) competitive one-upmanship angle, and
• Maybe Google hopes there’s sustainable veracity to the reports that Android tablet shipments (goosed by lucrative trade-in discounts) are increasing at iPads’ detriment?

Please share your thoughts on Google’s last-week pre- and re-announcements in the comments.

OpenAI

Turnabout is fair play, it seems. Last Friday, rumors began circulating that OpenAI, the developer of the best-known GPT (generative pre-trained transformer) LLM (large language model), among others, was going to announce something on Monday, one day ahead of Google I/O. And given the supposed announcement’s chronological proximity to Google I/O, those rumors further hypothesized that perhaps OpenAI was specifically going to announce its own GPT-powered search engine as an alternative to Google’s famous (and lucrative) offering. OpenAI ended up in-advance denying the latter rumor twist, at least for the moment, but what did get announced was still (proactively, it turned out) Google-competitive, and with an interesting twist of its own.

To explain, I’ll reiterate another excerpt from my year-ago Google I/O 2023 coverage:

The way I look at AI is by splitting up the entire process into four main steps:

1. Input
2. Analysis and identification
3. Appropriate-response discernment, and
4. Output

Now a quote from the LLM-focused section of my 2023 year-end retrospective writeup:

LLMS’ speedy widespread acceptance, both as a generative AI input (and sometimes also output) mechanism and more generally as an AI-and-other interface scheme, isn’t a surprise…their popularity was a matter of when, not if. Natural language interaction is at the longstanding core of how we communicate with each other after all, and would therefore inherently be a preferable way to interact with computers and other systems (which Star Trek futuristically showcased more than a half-century ago). To wit, nearly a decade ago I was already pointing out that I was finding myself increasingly (and predominantly, in fact) talking to computers, phones, tablets, watches and other “smart” widgets in lieu of traditional tapping on screens and keyboards, and the like. That the intelligence that interprets and responds to my verbally uttered questions and comments is now deep learning trained and subsequent inferred versus traditionally algorithmic in nature is, simplistically speaking, just an (extremely effective in its end result, mind you) implementation nuance.

Here’s the thing: OpenAI’s GPT is inherently a text-trained therefore text-inferring deep learning model (steps 2 and 3 in my earlier quote), reflected in the name of the “ChatGPT” AI agent service based on it (later OpenAI GPT versions also support still image data). To speak to an LLM (step 1) as I described in the previous paragraph, for example, you need to front-end leverage another OpenAI model and associated service called Whisper. And for generative AI-based video from text (step 4) there’s another OpenAI model and service, back-end this time, called Sora.

Now for that “interesting twist” from OpenAI that I mentioned at the beginning of this section. In late April, a mysterious and powerful chatbot named “gpt2-chatbot” appeared on a LLM comparative evaluation forum, only to disappear shortly thereafter…and reappear again a week after that. Its name led some to deduce that it was a research project from OpenAI (further fueled by a cryptic social media post from CEO Sam Altman) —perhaps a potential successor to latest-generation GPT-4 Turbo—which had intentionally-or-not leaked into the public domain.

Turns out, we learned on Monday, it was a test-drive preview of now-public GPT-4o (“o” for “omni”), And not only does GPT-4o outperform OpenAI precursors as well as competitors, based on Chatbot Arena leaderboard results, it’s also increasingly multimodal, meaning that it’s been trained on and therefore comprehends additional input (as well as generating additional output) data types. In this case, it encompasses not only text and still images but also audio and vision (specifically, video). The results are very intriguing. For completeness, I should note that OpenAI also announced chatbot agent application variants for both MacOS and Windows on Monday, following up on the already-available Android and iOS/iPadOS versions.

Google Gemini

All of which leads us (finally) to today’s news, complete with the aforementioned 121 claimed utterances of “AI” (no, I don’t know how many times they said “Gemini”):

@verge Pretty sure Google is focusing on AI at this year’s I/O. #google #googleio #ai #tech #technews #techtok ♬ original sound – The Verge

Gemini is Google’s latest LLM, previewed a year ago, formally unveiled in late 2023 and notably enhanced this time around. Like OpenAI with GPT, Google’s deep learning efforts started out text-only with models such as LaMDA and PaLM; more recent Gemini has conversely been multimodal from the get-go. And pretty much everything Google talked about during today’s keynote (and will cover more comprehensively all week) is Gemini in origin, whether as-is or:

• Memory footprint and computational “muscle” fine-tuned for resource-constrained embedded systems, smartphones and such (Gemini Nano, for example), and/or
• Training dataset-tailored for application-specific use cases

including the Gemma open model variants.

In the interest of wordcount (pushing 2,000 as I type this), I’m not going to go through each of the Gemini-based services and other technologies and products announced today (and teased ahead of time, in Project Astro’s case) in detail; those sufficiently motivated can watch the earlier-embedded video (upfront warning: 2 hours), archived liveblogs and/or summaries (linked to more detailed pieces) for all the details. As usual, the demos were compelling, although it wasn’t entirely clear in some cases whether they were live or (as Google caught grief for a few months ago) prerecorded and edited. More generally, the degree of success in translating scripted and otherwise controlled-environment demo results into real-life robustness (absent hallucinations, please) is yet to be determined. Here are a few other tech tidbits:

• Google predictably (they do this every year) unveiled its sixth-generation TPU (Tensor Processing Unit) architecture, code-named Trillium, with a claimed 4.7x performance boost in compute performance per chip versus today’s 5th-generation precursor. Design enhancements to achieve this result include expanded (count? function? both? not clear) matrix multiply units, faster clock speeds, doubled memory bandwidth and the third-generation SparseCore, a “specialized accelerator for processing ultra-large embeddings common in advanced ranking and recommendation workloads,” with claimed benefits both in training throughput and subsequent inference latency.
• The company snuck a glimpse of some AR glasses (lab experiment? future-product prototype? not clear) into a demo. Google Glass 2, Revenge of the Glassholes, anyone?
• And I couldn’t help but notice that the company ran two full-page (and identical-content, to boot) ads for YouTube in today’s Wall Street Journal even though the service was barely mentioned in the keynote itself. Printing error? Google I/O-unrelated v-TikTok competitive advertising? Again, not clear.

And with that, my Google I/O coverage is finit for another year. Over to all of you for your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

 Related Content

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• Fall tech events twain: Apple’s (potential) loss is Amazon and Google’s gain
• Google Pixelbook: Reviewing the Android-on-Chrome OS experience
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The post The 2024 Google I/O: It’s (pretty much) all about AI progress, if you didn’t already guess appeared first on EDN.

Two researchers at Northern Ontario School of Medicine (NOSM) University and Laurentian University have been awarded funding from grants administered through the Natural Sciences and Engineering Research Council of Canada (NSERC) Alliance Missions program. One project studies how gallium can be mined more efficiently while the second project focuses on the extraction of critical minerals from tailings ponds...

Luminus Devices Inc of Sunnyvale, CA, USA – which designs and makes LEDs and solid-state technology (SST) light sources for illumination markets – has launched a series of 4-in-1 RGBL (red-green-blue-lime) LEDs designed for stage and architectural lighting systems that require high-output color mixing with high color-rendering index (CRI)...

Rohde & Schwarz extends its portfolio with a 2U high oscilloscope/digitizer tailored for rack mount and other applications where a low-profile form factor is critical. The new MXO 5C series is the company’s first oscilloscope without an integrated display. It delivers the same peformance as the previously introduced MXO 5 series, but with a fourth of the vertical height.

Rohde & Schwarz introduces the new MXO 5C oscilloscope with four or eight channels. The new series is based on the next-generation MXO 5 oscilloscope and specifically addresses rack mount and automated test system applications where users are often confronted with space limitations. The instrument’s 2U vertical height – just 3.5” or 8.9 cm – allows engineers to deploy it in test systems where a traditional oscilloscope with a large display would not fit. The compact form factor is also of value in applications with high channel density where users need a large number of channels in a small volume. Users operate the instrument via the integrated web interface, or they interact with it exclusively programmatically and use the instrument as a high-speed digitizer.

Like other MXO oscilloscopes, the new MXO 5C series builds on next-generation MXO-EP processing ASIC technology developed by Rohde & Schwarz. It offers the fastest acquisition capture rate in the world of up to

4.5 million acquisitions per second. This makes it the world’s first compact oscilloscope that allows engineers to capture up to 99% real-time signal activity enabling them to see more signal details and infrequent events better than with any other oscilloscope.

Philip Diegmann, Vice President Oscilloscopes at Rohde & Schwarz, said: “While oscilloscopes with large displays work well for bench usage, we’ve had a number of customers ask for a version that is tailored for rack mount applications. At the same time, we have customers who need a large channel count, for example in physics. With the MXO 5C we created a unique instrument that offers the best possible performance for both scenarios.” The new form factor allows to place many channels in close proximity. The eight-channel model of the MXO 5C provides a channel density of 1500 cm3 per channel and consumes just 23 watts per channel.

While primarily designed for rack mount usage, the instrument doubles as a stand-alone bench oscilloscope. Users can simply attach an external display via the built-in DisplayPort and HDMI connectors, or they can

access the instrument’s GUI via a web interface by typing in the oscilloscope’s IP address into their browser. As the first oscilloscope to offer E-ink display technology, the MXO 5C shows the IP address and other critical information on a small non-volatile display on the front of instrument, which stays visible even when power is switched off.

Like the MXO 5, the MXO 5C series comes in both four and eight channel models, in bandwidth ranges with100 MHz, 200 MHz, 350 MHz, 500 MHz, 1 GHz, and 2 GHz models. The starting price of EUR 18 000 for the eight-channel models sets a new industry standard. Various upgrade options are available to users with demanding application needs, such as 16 digital channels with a mixed-signal oscilloscope (MSO) option, an integrated dual-channel 100 MHz arbitrary generator, protocol decode and triggering options for industry-standard buses and a frequency response analyzer to enhance the capabilities of the instrument.

The new MXO 5C series oscilloscopes are now available from Rohde & Schwarz and selected distribution channel partners. For more information on the instrument, visit :

https://www.rohde-schwarz.com/product/MXO5C

The post Rohde & Schwarz introduces the MXO 5C series, the world’s most compact oscilloscope with up to 2 GHz bandwidth appeared first on ELE Times.

Infineon Technologies AG introduces the new XENSIV TLE49SR angle sensor family, which combines excellent stray field immunity with high accuracy. The sensors are ideal for applications of safety-critical automotive chassis systems such as electric power steering and vehicle height leveling.

All products in the XENSIV TLE49SR family withstand stray magnetic fields of up to 8 mT. The sensors exceed the requirements of ISO11452-8 level IV for car hybridization and electrification with 4000 A/m (equal to 5 mT) for inhomogeneous stray field and eliminate the need for external shielding.

The intrinsic accuracy of the sensors defines an angle error with less than 1°. By using a look-up table, the angle error can be reduced even further: Multi point calibration (16 variable and 32 equidistant) results in an angle error below 0.5°. This feature helps to compensate angle deviations resulting e.g. from mechanical misalignments of the manufacturing process.

The angle sensors were developed according to ISO 26262 as a “safety element out of context”. The ASIL C metric on component level enables system designs up to functional safety level ASIL D.

Availability

The first products of the new XENSIV TLE49SR angle sensor family are available now with either PWM, SENT or SPC interface. For surface mounting, they are supplied in a TDSO-8 package. Further information is available at www.infineon.com/angle-sensors/tle49srx8/.

The post Infineon presents XENSIV TLE49SR angle sensor family with outstanding stray field robustness appeared first on ELE Times.

At SID Display Week 2024 in San Jose (14–16 May), Mojo Vision Inc of Saratoga, CA, USA — which is developing and commercializing micro-LED display technology for consumer, enterprise and government applications — is announcing advances in display technology, including demonstrating a monolithic red, green and blue (RGB) panel with 4µm pixel pitch, representing a density of 6350 pixels per inch (ppi)...

Over the last decades, Mean Well has become one of the most recognisable global providers of power supply modules and converters. However, its product range also includes a broad selection of other solutions, such as KNX equipment for building automation systems.

The assortment described below includes modules compatible with the KNX system, i.e. a standard applied in home and industrial automation systems. They are used to control diverse consumers, for example actuators, motors or components with DALI interfaces for typical illumination systems. Mean Well offers numerous universal solutions for control, but also for the designing and scaling of KNX systems.

KNX AUTOMATION SYSTEMS

KNX is an open source, international standard for building automation systems that facilitates the control of illumination systems, actuators (gates, shutters, electromagnetic locks), ventilation/air conditioning systems (HVAC in its broadest sense), as well as monitoring or alarm systems (including anti-intrusion systems). A range of KNX-compatible consumer electronics products and white goods are now available. As a result, various complex systems can be created, managed, documented and diagnosed using dedicated software.

KNX power supply modules LCM series power supply modules PWM series power supply modules Power supply for the KNX components

The first group of KNX-compatible products offered by Mean Well includes two series of power supply modules, namely KNX-20e and KNX-40e, both designed to supply diverse consumers, mostly drivers connected to the KNX networks (30 V DC output and power up to 38.4 W). They operate at standard mains voltage (180–264V AC) or direct current sources (e.g. 254–370 V DC).

The LCM and PWM series encompasses products for LED illumination systems. These are panel-mounted, constant-current (LCM, 350–1050 mA or 500–1400 mA) or constant-voltage products (PWM, 12–48 V DC). They simplify system design by eliminating the need to install additional gates for controllers, as the units can directly activate and control consumers such as LED strips, lamps or lanterns (within the basic range). The converter power rating is up to 200 W (selected models).

Note also that, in addition to their basic functionality, all these KNX-compatible converters ensure mutual synchronisation of operation and remote monitoring of power supply parameters (voltage, current, energy consumption).

KNX drivers and other equipment from the KAA series

Apart from power supply modules, Mean Well provides a range of drivers, interfaces and other auxiliary devices used to design KNX systems. They are suitable for DIN rail mounting (35 mm), which further expands their range of application, even when it comes to retrofitting work on existing systems.

KAA universal drivers KAA LED drivers

The first product group includes basic drivers, i.e. relay drivers used to actuate motors, actuators, heaters, solenoid valves, etc. They feature eight channels and contacts with current-carrying capacity of 10 A or 16 A. They provide the simplest solution for remote control of consumers. As far as devices designed for LED illumination are concerned, they can additionally be used to dim the lights, for example to control their intensity and activate them with a gradual brightness enhancement effect (linear or logarithmic mode). This functionality is fully integrated with the driver circuit to use the same power source, which greatly simplifies installation/wiring.

KNX-USB interface KNX switch/repeater Ethernet-KNX router KNX system design and scaling

In the table above, you can see elements used to design and scale KNX networks. As the name suggests, a KNX-USB interface provides network access via any desktop computer/laptop equipped with a USB module. Such connections may be required for programming or diagnostic purposes, e.g. to adjust single controller settings. A universal serial interface can also be used to integrate a less typical device with a KNX system, e.g. a single-board computer to be configured as a remote access/control gateway. The switch/repeater comes with two RJ-45 sockets to facilitate connecting or extending network “branches” in a manner eliminating conflicts and interferences thanks to galvanic port insulation and to filtering telegrams (packages) in line with a specific hierarchy which the user can define.

An Ethernet-KNX router makes it possible to use a LAN infrastructure (and also, indirectly, the wireless WLAN infrastructure) to support a KNX system. Such a solution comes particularly handy in areas where routing new cable runs would require refurbishment work, as well as in system modernisation, servicing and scaling. The router is configured via an interface that is accessible from a web browser.

KNX-DALI converter KNX-DALI gate Operation with DALI interface

KNX is a powerful, but still generic standard for control/automation system communication and organisation. Therefore, in various set-ups, it may be necessary to integrate it with much more specialised solutions, such as the DALI interface(Digital Addressable Lighting Interface) used in the field of illumination system design. For example, DLC-02-KN is a gate with an output to two DALI-2 buses to operate a total of 128 control devices (ECG, Electronic Control Gear). Therefore, even very complex illumination systems (residential interiors, offices, and façade/architectural illumination systems) can be integrated with a broader-purpose building automation system. DALI gates ensure access to the diverse capabilities offered by this interface (e.g. RGBW LED strip colour and intensity adjustment, dimming/brightening rate setting, etc.), while also simplifying the presetting of individual functions and entire arrangement programmes which a user can activate via any available interface (smartphone app, wall switch, automatic/timer triggering).

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The Defense Advanced Research Projects Agency (DARPA) has awarded BAE Systems’ FAST Labs R&D organization in Merrimack, NH, USA a $12m contract for the program THREADS (Technologies for Heat Removal in Electronics at the Device Scale)...

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications is among the early changemakers in the ongoing sustainability issue. The company has been consciously adopting environment-friendly norms and practices and has also charted out its plan for achieving carbon neutrality by 2027. ST has been forward-looking in establishing an ecosystem where business and technology stay relevant and focused on sustainability even under lingering geopolitical and economic disturbances. They are building sophisticated and cutting-edge systems and inculcating best practices within the organization with the utmost understanding of the fact that environmental awareness is its own reward in the semiconductor industry.

Group Vice President, Corporate Sustainability at STMicroelectronics

ST published its annual Sustainability Report 2024 that delves into insights into its 2023 performance on the ESG markers.

Rashi Bajpai, Sub-Editor at ELE Times spoke with Mr Jean-Louis Champseix, Group Vice President, Corporate Sustainability at STMicroelectronics, on the subject of carbon neutrality and the many aspects of sustainability that ST works upon actively.

 

 

 

ELE Times: Give insights into your vision and sustainability goals at a time when talks on climate change and the environment have taken centre stage on a global platform.

Jean-Louis Champseix: Sustainability is not just a corporate responsibility, but a core component of our value proposition delivering benefits to our company, our customers, and to society.

We believe that technology has a critical role to play in addressing the environmental, social, and economic challenges facing our world today. We are committed to developing innovative technologies and products that enable the transformation of our economies and societies through digitalization, smarter mobility, and decarbonization.

The company’s approach to sustainability is designed to mitigate risks, capitalize on opportunities presented by the global shift towards a more sustainable economy, and build a resilient business that can thrive in an ever-changing world.

And while climate change and environmental topics at large are at the heart of many sustainability-related discussions, sustainability encompasses not only environmental conservation efforts but also addresses social issues.

This is why ST is dedicated to upholding the highest standards of labor practices, ensuring the health and safety of its employees, and engaging in community development.

ELE Times: How does a giant like ST bring out positive results in tackling sustainability and climate goals? What steps has ST taken to ensure the organization remains driven towards attaining sustainability in all areas?

Jean-Louis Champseix: Our sustainability journey started 30 years ago. Since our first environmental policy back in 1993, we have built, step by step, a robust sustainability strategy endorsed by our top management and supported by ambitious goals and a culture of continuous improvement.

There are at least two success factors.

• First, we embed more and more sustainability into our operations at all levels. The corporate environmental team is responsible for developing programs and procedures that enable us to work towards our environmental objectives. These are implemented by local sustainability committees, each of which develops a roadmap according to the needs of their respective sites. Our manufacturing sites each have an Environment, Health and Safety (EHS) steering committee responsible for implementing the environmental policy. We also launched a program to embed sustainability in each step of business strategy, planning, and decision-making. This is supported by accelerator workstreams to facilitate cross-organization collaboration in priority areas.
• Secondly, we consider transparency a must. This is why we have been publicly reporting our target as well as our performance for 27 years. Additionally, socially Responsible Investment (SRI) rating agencies, analysts and investors regularly request detailed feedback on a wide range of Environmental, Social and Governance (ESG) topics to evaluate our corporate behavior and performance. Participating in these evaluations gives us an opportunity to assess our performance within a wider context, benchmark ST against our peers and identify areas for further improvement. It also enables us to monitor investment trends and identify new risks and opportunities. These evaluations have resulted in ST’s inclusion in leading sustainability indices and rankings.

ELE Times: What have been the major challenges that ST had to overcome in the last decade to achieve a significant result in 2023? Also, highlight the top achievements in your journey towards building a more sustainable future for ST globally.

Jean-Louis Champseix: Over the last 28 years, from 1994 to 2023, we have succeeded in drastically mitigating our environmental impact per unit of production. Here are some key figures:

• -84% of perfluorinated compounds (PFC) emissions
• -76% of water consumption
• -56% of electricity consumption
• +336% of waste recycled.

As for the last decade, we have made remarkable progress in many areas, from climate action to safety.  Let’s look at responsible mineral sourcing. Responsible sourcing means companies can identify the origin of the metals contained in electronic components and ensure their extraction, transport, or trade are not associated with serious abuses related to people, working conditions, or the environment, or with bribery and money laundering. We went from 18.5% of ST products free from conflict minerals in 2012 to 100% over the last few years.

We are also proud of being among the best in class when it comes to ensuring a safe working environment to our employees. Through the collective efforts of our sites, we maintained strong safety performance results in 2023: our employee recordable injury case rate was 0.10, better than our target of 0.13.

Our journey is far from over: we intend to continually improve our performance in all areas of Sustainability.

ELE Times: Help us understand the sustainability strategy and business model that ST has adopted.

Jean-Louis Champseix: Throughout our value chain, we have integrated sustainability into our business model. We have implemented numerous programs to effectively manage our impacts, opportunities, and risks, ensuring that sustainability remains at the forefront of our operations and activities.

Our guiding principles and 24 sustainability goals are detailed in our sustainability charter. This is endorsed by Jean-Marc Chery, our President and CEO. Our progress towards these annual, 2025 and 2027 goals are described in our latest Sustainability report, with a focus on transparency.

In our business model, we leverage our expertise in the semiconductor industry to serve sectors that are pivotal for a sustainable future, such as renewable energy, electric vehicles, and smart grid technologies. The company also maintains a strong commitment to ethical business practices, transparency, and corporate social responsibility. By integrating these principles into its core operations, ST aims to not only achieve financial success but also to foster positive environmental and social outcomes, aligning with the broader goals of sustainable development.

ELE Times: ST has committed to achieving carbon neutrality by 2027. Please elaborate on the Plan of Action.

Jean-Louis Champseix: In 2020, we announced our commitment to becoming carbon neutral by 2027 on scope 1 and 2, and partially scope 3. Our carbon neutrality program comprises five main workstreams:

• reducing as much as technically possible our direct emissions, that represented more than 50% of our total emissions, through perfluorinated compounds (PFC) abatement systems
• investing in energy savings, in particular in our manufacturing sites where many energy-saving initiatives are implemented,
• using renewable energies to reach 100% of electricity coming from renewable sources in 2027,
• minimizing all our indirect emissions by optimizing product transportation, business travels and employee commuting,
• sustainable sequestration of what cannot be avoided at the end of our roadmap through credible offsetting programs.

The programs in place at all our manufacturing sites address our direct and indirect emissions in accordance with scopes 1, 2, and partially 3 of the GHG Protocol. In 2023, we continued our progress towards carbon neutrality, with –45% of scopes 1 & 2 (versus 2018) and reaching 71% of renewable electricity sourcing.

More information on ST’s sustainability efforts can be found at https://www.st.com/content/st_com/en/about/sustainability.html

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X-Silicon aims to address the current limitations of edge computing with its new low-power “C-GPU” architecture.

My wife groomed her and I thought of you guys and gals. submitted by /u/SirGreybush [link] [comments]

In an early look at on-chip power, researchers have demonstrated that thin-film micro-capacitors can be fabricated on semiconductor chips.

submitted by /u/1Davide [link] [comments]

A little more than a year after he took the reins of Intel’s ambitious bid for semiconductor contract manufacturing, Stuart Pann is retiring while handing over the charge to Kevin O’Buckley. The transition took place on Monday, 13 May, and it once more raised questions about the future viability of Intel’s third-party foundry business.

Pann, a 35-year company veteran, joined Intel during the heydays of the PC revolution in 1981. He returned to the Santa-Clara, California-based semiconductor firm in 2021 to lead the chip manufacturing division, Intel Foundry Services (IFS). He replaced Intel Foundry’s first chief, Randhir Thakur, who later became CEO and managing director of Tata Electronics, the electronics manufacturing arm of Indian conglomerate Tata Group.

Figure 1 Pann, currently in a support role for a smooth transition, will retire at the end of this month. Source: Intel

Now O’Buckley replaces Pann, and it’s a déjà vu of Thakur-to-Pann handover a year ago. For instance, during the first quarter of 2024, Intel Foundry reported revenue of $4.4 billion, which was down by $462 million compared to the first quarter of 2023. That’s mainly attributed to lower revenues from back-end services and product samples.

Pann—who left the company only a few months after Intel Foundry marked the official launch of the manufacturing business as an independent entity to compete with the likes of TSMC and Samsung—set up Intel’s IDM 2.0 Acceleration Office (IAO) to guide the implementation of an internal foundry model. IAO closely works with Intel’s business units to support the company’s internal foundry model.

Intel Foundry, which aims to move beyond traditional foundry offerings and establish itself as the world’s first open-system foundry, faces huge technical and commercial challenges. That includes combining wafer fabrication, advanced process and packaging technology, chiplet standards, software, and assembly and test capabilities in a unified semiconductor ecosystem.

O’Buckley inherits these challenges. He comes from Marvell, where he led the company’s custom chips business as senior VP for the Custom, Compute and Storage Group. O’Buckley came to Marvell in 2019 via its acquisition of Avera Semiconductor, a 1,000-person chip design company that traces its roots to IBM, which offloaded it to GlobalFoundries before it was sold to Marvell. O’Buckley led Avera’s divestiture from GlobalFoundries.

Figure 2 Like his predecessor, O’Buckley will report directly to CEO Pat Gelsinger. Source: Intel

Intel CEO Pat Gelsinger, who has bet Intel’s revival bid on setting up an independent fab business, acknowledges that Intel Foundry is still some distance away from profitability due to the large up-front investment needed to ramp it up. However, time isn’t on Gelsinger’s side, meaning a swift turnaround plan is in order for O’Buckley.

O’Buckley is an outsider, a plus at Intel, where employees are known to have stayed long years; his expertise in the custom chips business will also be an asset at Intel Foundry. Next, during his stint at IBM, he spearheaded the company’s development of 22- and 14-nm FinFET technologies. As Gelsinger puts it, he has a unique blend of expertise in both foundry and fabless companies.

Now comes the tough part, execution.

Related Content

• Change of guards at Intel Foundry Services (IFS)
• Intel Signs MediaTek as Third Major Foundry Customer
• Intel Foundry’s ‘No. 1’ Customer—U.S. DoD—Targets GAA
• Intel Foundry Services roadmap unveiled one deal at a time
• Intel’s foundry foray and its influence on the EDA, IP industries

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If we want to take samples of some analog waveform, as in doing analog to digital conversions at some particular conversion rate, there is an absolute lower limit to the rate of doing conversions versus the highest frequency component of the analog signal. That limit must not be violated if the sampling process is to yield valid results. We do not want to encounter the phenomenon called “aliasing”.

The term “aliasing” as we use it here has nothing to do with spy thrillers or crime novels. Aliasing is an unwanted effect that can arise when some analog waveform is being sampled for its instantaneous values at regular time intervals that are longer than half the reciprocal of a sampling frequency. If we were to sample some waveform once every microsecond, the sampling interval is half of that one microsecond for which we would have a sampling frequency limit of 2 MHz or faster.

Aliasing will occur if the sampled waveform has frequency component(s) that are greater in frequency than 50% of the sampling frequency. To turn that statement around, aliasing will occur if the sampling frequency is too low. Aliasing will occur at any sampling rate that is lower than twice the highest frequency component of the waveform being sampled.

The next question is: Why?

The late comedian Professor Irwin Corey once posed a similar question: “Why is the sky blue?” His answer was something like “This is a question which must be taken in two parts. The first part is ‘Why?’ ‘Why’ is a question Man has asked since the beginning of time. Why? I don’t know. The second part is ‘Is the sky blue?’ The answer is ‘Yes!'”

Fortunately, we can do a little better than that as follows.

The sampling process can be thought of as multiplying the waveform being sampled by a very narrow duty cycle pulse waveform of zero value for most of the time and of unity value for the very narrow sampling time interval. That sampling waveform will be rich in harmonics. There will be a spectral line at the sampling frequency itself plus spectral lines at each of the sampling frequency’s harmonics as well. Each spectral line will have sidebands as shown in Figure 1 which will extend from those sampling frequency spectral lines up and down the frequency spectrum in keeping with the sampled waveform’s bandwidth.

Figure 1 Sampling versus aliasing where spectral line will have sidebands that will extend from those sampling frequency spectral lines up and down the frequency spectrum in keeping with the sampled waveform’s bandwidth.

The sampling waveform is amplitude modulated by the sampled waveform and so I’ve chosen to call that sampled waveform’s highest frequency component, Fmod. Each bandwidth is 2 * Fmod.

If the sampling frequency is high enough as with Fs1, the illustrated sidebands do not overlap. There is a respectable guard band between them, and no aliasing occurs.

If the sampling frequency starts getting lower as with Fs2, the sidebands start getting closer together and there is a less comfortable, if I may use that word, guard band.

If the sampling frequency gets too low as with Fs3 which is less than twice Fmod, the sidebands overlap, and we have aliasing. Sampling integrity is lost. The sampled waveform cannot be reconstructed from the undersampled output of this now unsatisfactory system.

Consider this an homage to Claude Shannon (April 30, 1916 – February 24, 2001) and his sampling theory.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Digital oscilloscopes: When things go wrong
• The alias theorems: practical undersampling for expert engineers
• Control the sample rate of digitized signals
• Basics of ADCs and DACs, part 1
• Claude Shannon, ‘father of information theory,’ is born, April 30, 1916

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Opportunities for UK companies across the semiconductor industry in Taiwan are revealed in a new report by international business development consultancy Intralink, which delivers the UK–APAC Tech Growth Programme on behalf of the UK Government...