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Qualcomm acquired Arduino. This is a result of that acquisition. That was quick! Link to official page - Qualcomm QRB2210 (- 0.4mm pitch BGA package) - STMicroelectronics STM32U585 - 8 layer board submitted by /u/SkunkaMunka [link] [comments]

Born from a minimalist design brief in 1971, the NE555 delivered edge-triggered timing, pulse generation, and oscillation in one compact package, earning a place in everything from washing machines to rocket launchers.

Intel Corp. unveils new details about its next-generation client processor for AI PCs, the Core Ultra series 3, code-named Panther Lake, which is expected to begin shipping later this year. The company also gave a peek into its Xeon6+ server processor, code-named Clearwater Forest, expected to launch in the first half of 2026.

Core Ultra series 3 client processor (Source: Intel Corp.)

Panther Lake is the company’s first product built on the advanced Intel 18A semiconductor process, the first 2-nanometer class node manufactured in the United States. It delivers up to 15% better performance per watt and 30% improved chip density compared to Intel 35 thanks to two key advances—RibbonFET and PowerVia.

The RibbonFET transistor architecture, Intel’s first in over a decade, delivers greater scaling and more efficient switching for better performance and energy efficiency. The PowerVia backside power delivery system improves power flow and signal delivery.

Also contributing to its greater flexibility and scalability is Foveros, Intel’s advanced packaging and 3D chip stacking technology for integrating multiple chiplets into advanced SoCs.

Panther Lake

The Core Ultra series 3 processors offer scalable AI PC performance, targeting a range of consumer and commercial AI PCs, gaming devices, and edge solutions. Intel said the multi-chiplet architecture offers flexibility across form factors, segments, and price points.

The Panther lake processors offer Lunar Lake-level power efficiency and Arrow Lake-class performance, according to Intel. They offer up to 16 CPU cores, up to 96-GB LPDDR5, and up to 180 TOPS across the platform. They also feature new P- and E-cores, along with a new GPU and next-generation IPU 7.5 and NPU 5, delivering higher-performance and greater efficiency over previous generations.

Key features include up to 16 new performance-cores (P-cores) and efficient-cores (E-cores) delivering more than 50% faster CPU performance versus the previous generation; 30% lower power consumption versus Lunar Lake; and a new Intel Xe3 Arc GPU with up to 12 Xe cores delivering more than 50% faster graphics performance versus the previous generation, along with up to 12 ray tracking units and up to 16-MB L2 cache.

Panther Lake also features the next-gen NPU 5 with up to 50 trillion of operations per second (TOPS), offering >40% TOPS/area versus Lunar Lake and 3.8× TOPS versus Arrow Lake-H.

The IPU 7.5 offers AI-based noise reduction and local tone mapping. It delivers 16-MP stills and 120 frames per second slow motion and supports up to three concurrent cameras. It also offers a 1.5-W reduction in power with hardware staggered HDR compared to Lunar Lake.

Other features include enhanced power management, up to 12 lanes PCIe 5, integrated Thunderbolt 4, integrated Intel Wi-Fi 7 (R2) and dual Intel Bluetooth Core 6, and LPCAMM support.

Panther Lake will also extend to edge applications including robotics, Intel said. A new Intel Robotics AI software suite and reference board is available with AI capabilities to develop robots using Panther Lake for both controls and AI/perception. The suite includes vision libraries, real-time control frameworks, AI inference engines, orchestration-ready modules, and hardware-aware tuning

Panther Lake will begin ramping high-volume production this year, with the first SKU scheduled to ship before the end of the year. General market availability will start in January 2026.

Recommended Intel’s confidence shows as it readies new processors on 18A

Clearwater Forest

Intel also provided a sneak peek into the Xeon 6+, its first 18A-based server processor. It is also touted as the company’s most efficient server processor. Both Panther Lake and Clearwater Forest, built on Intel 18A, are being manufactured at Intel’s new Fab 52, which is Intel’s fifth high-volume fab at its Ocotillo campus in Chandler, Arizona.

Xeon 6+ server processor (Source: Intel Corp.)

Clearwater Forest is Intel’s next-generation E-core processor, featuring up to 288 E-cores, and a 17% increase in instructions per cycle (IPC) over the previous generation. Expected to offer significant improvements in density, throughput, and power efficiency, Intel plans to launch Xeon 6+ in the first half of 2026. This server processor series targets hyperscale data centers, cloud providers, and telcos.

The post Intel releases more details about Panther Lake AI processor appeared first on EDN.

Broadcom Inc. launches the Tomahawk 6 – Davisson (TH6-Davisson), the company’s third-generation co-packaged optics (CPO) Ethernet switch, delivering the bandwidth, efficiency, and reliability for next-generation AI networks. The TH6-Davisson provides advances in power efficiency and traffic stability for higher optical interconnect performance required to scale-up and scale-out AI clusters.          

The trend toward CPOs in data centers is to increase bandwidth and lower energy consumption. With the TH6-Davisson, Broadcom claims the industry’s first 102.4 Tbits/s of optically enabled switching capacity, doubling the bandwidth of any CPO switch available today. This sets a new benchmark for data-center performance, Broadcom said.

(Source: Broadcom)

Designed for power efficiency, the TH6-Davisson heterogeneously integrates TSMC Compact Universal Photonic Engine (TSMC COUPE) technology-based optical engines with advanced substrate-level multi-chip packaging. This is reported to dramatically reduce the need for signal conditioning and minimize trace loss and reflections, resulting in a 70% reduction in optical interconnect power consumption. This is more than 3.5× lower than traditional pluggable optics, delivering a significant improvement in energy efficiency for hyperscale and AI data centers, Broadcom said.

In addition to power efficiency, the TH6-Davisson Ethernet switch addresses link stability, which has become a critical bottleneck as AI training jobs scale, the company added, with even minor interruptions causing losses in XPU and GPU utilization.

The TH6-Davisson solves this challenge by directly integrating optical engines onto a common package with the Ethernet switch. The integration eliminates many of the sources of manufacturing and test variability inherent in pluggable transceivers, resulting in significantly improved link flap performance and higher cluster reliability, according to Broadcom.

In addition, operating at 200 Gbits/s per channel, TH6-Davisson doubles the line rate and overall bandwidth of Broadcom’s second-generation TH5-Bailly CPO solution. It seamlessly interconnects with DR-based transceivers as well as NPO and CPO optical interconnects running at 200 Gbits/s per channel, enabling connectivity with advanced NICs, XPUs, and fabric switches.

The TH6-Davisson BCM78919 supports a scale-up cluster size of 512 XPUs and up to 100,000+ XPUs in two-tier networks at 200 Gbits/s per link. Other features include 16 × 6.4 Tbits/s Davisson DR optical engines and field-replaceable ELSFP laser modules.

Broadcom is now developing its fourth-generation CPO solution. The new platform will double per-channel bandwidth to 400 Gbits/s and deliver higher levels of energy efficiency.

The TH6-Davisson BCM78919 is IEEE 802.3 compliant and interoperable with existing 400G and 800G standards. Broadcom is currently sampling the Ethernet switch to its early access customers and partners.

The post Broadcom debuts 102.4-Tbits/s CPO Ethernet switch appeared first on EDN.

Omnivision says its new image sensor captures sharp HDR video in any light, combining speed, clarity, and efficiency for premium phones and action cameras.

POET Technologies Inc of Toronto, Ontario, Canada — designer and developer of the POET Optical Interposer, photonic integrated circuits (PICs) and light sources for the hyperscale data-center, telecom and artificial intelligence (AI) markets — has closed a non-brokered financing with a single institutional investor. In a private placement, the firm issued and sold 13,636,364 common shares and one common share purchase warrant (at a combined price of US$5.50 each) for gross proceeds of US$75m, before deducting related expenses...

Черговий етап у розвитку. Центру декарбонізації енергетики – Енерго-Інноваційного Хабу КПІ Інформація КП пт, 10/10/2025 - 16:32

High school trigonometry combined with four-quadrant multipliers can be exploited to yield sinusoidal frequency doublers. Nothing non-linear is involved, which means no possibly strident filtering requirements.  

Starting with some sinusoidal signal and needing to derive new sinusoidal signals at multiples of the original sinusoidal frequency, a little trigonometry and four-quadrant multipliers can be useful. Consider the following SPICE simulation in Figure 1.

Figure 1 Two analog frequency doublers, A1 + U1 and A2 + U2, in cascade to form a frequency quadruple.

The above sketch shows the pair A1 and U1 configured as a frequency doubler from V1 to V2, and the pair A2 and U2 configured as another frequency doubler from V2 to V3. Together, the two of them form a frequency quadrupler from V1 to V3. With more circuits, you can make an octupler and so on within the bandwidth limits of the active semiconductors, of course.

Frequency doubler operation is based on these trigonometric identities:

sin² (x) = 0.5 * ( 1 – cos (2x) )  and  cos² (x) = 0.5 * ( 1 + cos (2x) )

sin² (x) = 0.5 – 0.5 * cos (2x)   and  cos² (x) = 0.5 + 0.5* cos (2x)

Take your pick, both equations yield a DC offset plus a sinusoid at twice the frequency you started with. Do a DC block as with C1 and R1 above, and you are left with a doubled-frequency sinusoid at half the original amplitude. Follow that up with a times two gain stage, and you have made a sinusoid at twice the original frequency and at the same amplitude with which you started.

This way of doing things takes less stuff than having to do some non-linear process on the input sinusoid to generate a harmonic comb and then having to filter out everything except the one frequency you want.

Although there might actually be some other harmonics at each op-amp output, depending on how non-ideal the multiplier and op-amp might be, this process does not nominally generate other unwanted harmonics. Such harmonics as might incidentally arise won’t require a high-performance filter for their removal.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Analog frequency doublers  appeared first on EDN.

New Simulation & Optimization Platform Enables Custom Coil Designs for Industrial, Robotics and Medical Systems

Renesas Electronics Corporation introduced a new family of magnet-free inductive position sensor (IPS) ICs that can be fully customized for various coil designs compatible with a wide range of industrial applications such as robotics, medical and healthcare, smart buildings, home appliances and motor commutation. Built for high resolution, precision, and robust performance, the new RAA2P3226, RAA2P3200, and RAA2P4200 sensor ICs offer a cost-effective alternative to traditional magnetic and optical encoders, which can be bulky, expensive, and require frequent maintenance. Renesas also launched a web-based design tool that allows customers to easily create custom sensing elements to meet their specific system needs.

Operating on non-contact coil sensor technology, Renesas IPS products use a simple metallic target and dual-coil or single-coil configurations to detect absolute rotary, linear, or arc positions. These sensor ICs are designed to maintain stable operation even in environments with elevated temperatures (-40 to 125°C), particulate matter, moisture, mechanical vibration and electromagnetic interference. Moreover, they are immune to stray magnetic fields and require no maintenance, unlike magnetic- or optical encoder-based sensors. Their durability and low upkeep make them a reliable and cost-effective sensing solution for motor drives, actuators, valves, service robots and infrastructure applications, where reliability and long-term performance are critical.

All three products offer high precision in detecting target positions, with accuracy better than 0.1 percent of the full-scale electrical range. Two of the products, the RAA2P3226 and RAA2P3200 operate at 600K RPM (electrical) with propagation delays under 100ns, which is imperative in high-speed motor applications. The advanced RAA2P3226 supports dual-coil sensing with up to 19-bit resolution and 0.01° absolute accuracy, providing the high-precision performance required for robotic applications. The RAA2P4200 targets low-speed applications such as medical devices and power tools and the RAA2P3200 is optimized for high-speed motor commutation. All three products include automatic calibration and linearization to simplify integration and improve system-level performance.

In addition to these three products, Renesas will also introduce automotive-grade IPS, RAA2P452x and RAA2P4500. The dual-channel RAA2P452x allows customers to achieve ASIL D safety compliance when paired with Renesas MCUs. This automotive-grade solution offers a cost-effective option for low-speed body control and chassis systems without compromising quality.

Designing with inductive position sensors typically involves integrating a PCB, an IC with passive components, and a metal target mounted to the moving part. The most complex part is the external sensing element, such as the transmitter and receiver coils, which must be precisely configured to realize accuracy and customized to the system’s mechanical and environmental requirements. Renesas’ web-based Inductive Position Sensor Coil Optimizer tool tackles this challenge by automating coil layout, simulation, and tuning, significantly reducing the learning curve for developers. With this tool, engineers can also obtain accurate performance estimates and overcome manufacturing constraints by optimizing the coil layout.

“Our new web-based coil design tool is a game changer for inductive position sensing,” said Leopold Beer, Vice President of the Sensors Division at Renesas. “In the past, developers had to rely on chip suppliers for technical expertise when working with inductive position sensors. We completely removed this hurdle. This intuitive tool lets developers fully customize the sensing element and automatically fine-tunes it to achieve maximum accuracy and robustness at the system level. This dramatically lowers the barrier of entry and enables more customers, regardless of their expertise level, to confidently integrate inductive position sensing into their designs.”

The post Renesas Expands Sensing Portfolio with 3 Magnet-Free IPS ICs & Web-Based Design Tool appeared first on ELE Times.

Лекція Надзвичайного і Повноважного Посла Азербайджанської Республіки в Україні пана Сеймура Гурбан оглу Мардалієва kpi пт, 10/10/2025 - 06:01

📰 Газета "Київський політехнік" № 35-36 за 2025 (.pdf) Інформація КП пт, 10/10/2025 - 06:00

КПІ ім. Ігоря Сікорського у Times Higher Education World University Rankings 2026 KPI4U-2 пт, 10/10/2025 - 06:00

Learn how Narrowband (NB)-IoT offers power-efficient, scalable connectivity for IoT and smart cities. It addresses challenges of power, coverage, and cost for massive device deployments.

Melexis introduces the MLX90514, a dual-input inductive sensor IC that simultaneously processes signals from two sets of coils to compute differential or vernier angles on-chip. The inductive sensor targets automotive applications, such as steering torque feedback, steering angle sensing, and steering rack motor control.

(Source: Melexis)

Traditionally, designers have combined two single-channel ICs or used magnetic sensors for many applications, Melexis said. However, with the move to electrification, autonomy, and advanced driver-assistance systems (ADAS), vehicle control systems have become more complex particularly in systems such as steering torque feedback, steering rack motor control, including steer-by-wire implementations, which need dual-channel position sensing to deliver accurate torque and angle measurements.

By integrating differential and vernier angle calculations on-chip, the MLX90514 reduces processing demands on the host system, enabling smaller and more streamlined sensor designs. By computing complex position information (such as differential or vernier angles) directly at the sensor it eliminates the need for multiple ICs, which reduces design complexity and component count.

The MLX90514 is Melexis’ first dual inductive application-specific standard product (ASSP). It offers several interface options—including SENT, SPC, and PWM for a standalone module, and SPI for embedded modules—with integrated on-chip processing. The SENT/SPC output accommodates up to a 24-bit payload, enabling high-fidelity transmission of two synchronized 12-bit channels, which is required for high-accuracy torque and angle sensing.

Key features include zero-latency synchronized dual-channel operation, external pulse-width-modulation (PWM) signal integration that allows reading PWM signals from external sources, and the capability to handle small inductive signals, which supports compact coil designs and tighter printed-circuit-board layouts for smaller sensing modules.

The MLX90514 enables ASIL-D-compliant sensing systems, as a Safety Element out of Context (SEooC), for automotive steering torque and angle applications. The inductive interface sensor is available now.

The post Dual-input inductive sensor simplifies design appeared first on EDN.

As you can see it's a green little toroid with a "secondary" made using green metal wire used for flowers etc 3 windings. Gave the coil some 19MHz 24VPP Sinus wich gave me a result of 5.89VPP 19MHz on osciloscope but with multimeter i got 149.9V in both AC and DC. submitted by /u/Whyjustwhydothat [link] [comments]

A team of researchers has created a sealed, durable, and rapid tactile interface for on-screen Braille, offering a new approach to tactile accessibility.

Schneider Electric offers two reference designs co-engineered with NVIDIA to accelerate deployment of AI-ready infrastructure for AI factories. The controls reference design uses a plug-and-play MQTT architecture to bridge OT and IT systems, enabling operators to access and act on data from every layer.

The first reference design integrates power management and liquid cooling controls with NVIDIA Mission Control software, enabling smooth orchestration of AI clusters. It also supports Schneider’s data-center reference designs for NVIDIA Grace Blackwell systems, giving operators precise control over power and cooling to meet the demands of accelerated AI workloads.

The second reference design supports AI factories running NVIDIA GB300 NVL72 systems at up to 142 kW per rack. It delivers a complete blueprint for facility power, cooling, IT space, and lifecycle software, compatible with both ANSI and IEC standards. Using Schneider’s validated models and digital twins, operators can plan high-density AI data halls, optimize designs, and ensure efficiency, reliability, and scalability for NVIDIA Blackwell Ultra systems.

For more information about these new reference designs, as well as other data-center reference designs developed with NVIDIA, click here.

Schneider Electric 

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ST’s L98GD8 multichannel gate driver offers flexible output configurations in 48-V automotive power systems. Its eight independent, configurable outputs can drive MOSFETs as individual power switches or as high- and low-side pairs in up to two H-bridges for DC motor control. The device also supports peak-and-hold operation for electrically actuated valves.

Programmable gate current helps minimize MOSFET switching noise to meet EMC requirements. The driver operates from a 3.8-V to 58-V battery supply and a 4.5-V to 5.5-V VDD supply. Its I/O is compatible with both 3.3-V and 5-V logic levels.

To ensure safety and reliability, each output provides comprehensive diagnostics, including short-to-battery, short-to-ground, and open-load conditions. Output status is continuously monitored through dedicated SPI registers. The L98GD8 features fast overcurrent shutdown with dual-redundant failsafe pins, battery undervoltage detection, and an ADC for monitoring battery voltage and die temperature. Additional safety functions include Built-In Self-Test (BIST), Hardware Self-Check (HWSC), and a Communication Check (CC) watchdog timer.

The L98GD8 driver is available now, with prices starting at $3.94 each in lots of 1000 units.

L98GD8 product page 

STMicroelectronics

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According to Thales, its MultiApp 5.2 Premium PQC is Europe’s first quantum-resistant smartcard to receive high-level security certification from ANSSI (the French National Cybersecurity Agency). Certified to the EAL6+ level under the Common Criteria framework, the smartcard also uses digital signature algorithms standardized by NIST in the U.S.

The MultiApp 5.2 Premium PQC leverages post-quantum cryptography to protect digital identity data in ID cards, health cards, and driving licenses. This new generation of cryptographic signatures is designed to withstand the vast computational power of quantum computers, both today and in the future.

“This first certification for a solution incorporating post-quantum cryptography reflects ANSSI’s commitment to supporting innovation, while upholding the highest cybersecurity standards,” said Franck Sadmi, Head of National Certification Center, French Cybersecurity Agency (ANSSI). “The joint work of Thales, CEA-Leti IT Security Evaluation Facility, and ANSSI is a strong signal that Europe is ready to lead the way in post-quantum security, enabling organizations and governments to deploy solutions that anticipate future risks, rather than waiting for quantum computers to become mainstream.”

Thales

The post Thales introduces quantum-safe smartcard appeared first on EDN.