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The digital control pins of Nexperia’s NMUX130x series of 1.5-V to 5.5-V analog switches are compatible with 1.8-V logic thresholds across the entire supply range. Since the control pins operate independently of the VCC range, no additional components are required for voltage translation. The series includes AEC-Q100 qualified variants for automotive use, as well as general-purpose versions to address consumer and industrial applications.

The NMUX1308 is an 8-channel multiplexer/demultiplexer, whereas the NMUX1309 offers a dual 4-channel multiplexer/demultiplexer. All analog signal pins are bidirectional. Integrated injection-current control limits output voltage shifts on the active channel to under 5 mV when an overvoltage event happens on disabled signal channels.

IOFF protection circuitry on digital control pins and analog switch pins enhances overall system safety. Standard devices operate over a temperature range of -40°C to +85°C. Automotive qualified parts operate over a temperature range of -40°C to +125°C. Packaging options for the switches include both leaded and leadless options.

NMUX1308 product page

NMUX1309 product page  

Nexperia

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Keysight’s AI Data Center Test Platform aims to fast-track the design and deployment of artificial intelligence network infrastructure. According to the company, the system speeds validation and optimization of AI network fabric and improves benchmarking of new AI infrastructures with unprecedented scale and efficiency.

The AI test platform is an 800/400GE solution with lossless fabric validation. Keysight claims it is faster to deploy and offers deeper insights than GPU-based systems, emulating high-scale AI workloads with measurable fidelity.

To simplify benchmarking and validation, the platform uses prepackaged methodologies delivered as applications. These applications have been built through partnerships with key AI operators and AI infrastructure vendors.

The platform also offers a choice of test engines. Users can choose between AI workload emulation on Keysight hardware load appliances and software engines or real AI accelerators to compare benchmarking results.

For more information about the AI Data Center Test Platform, obtain a quote, or request a demo, click here.

Keysight Technologies 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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At the end of the DI for a Simple log-scale audio meter, I promised to show how to upgrade it to work better. With these fixes, it now has near-digital performance, with faster response and smoother operation. Even this supersized version comes in two flavours, one comparatively simple, the other, maxed out. It can now out-perform the standard peak program meter (PPM) specs (for which this a good reference), and has a span of over 60 dB with easy setting of the desired minimum and maximum levels.

Wow the engineering world with your unique design: Design Ideas Submission Guide

While the goal for the original version was to produce something simple and functional, the aim of this DI is to see how closely we can match the performance of a few lines of DSP code, no matter how much hardware it may take. The original used just one dual op-amp; this approach inflates that to two quad packs. Over the top: of course. Instructive fun: definitely, at least for us analogeeks.

The underlying principle is the same as before—force current through a diode, measure the resulting voltage, which is proportional to the logarithm of the input, and capture the peak value—but the implementation is different. Figure 1 shows the basic circuit.

Figure 1 We take the log of the input signal; its peak level is captured on C2, which is discharged slowly and linearly; and temperature- and level-corrections are applied in the current source which drives the meter.

The audio input to be measured is now applied through R1, a 10k fixed resistor rather than a thermistor. The thermistor gave compensation for the diodes’ tempco by scaling the (linear) input; with the fixed resistor, we’ll apply an offset to the (logged) signal later in the circuit to achieve the same result. A1’s output is a logarithmically-squashed version of the input. For now, we only need its positive peaks.

A2 and Q1 form a simple peak detector. Whenever A1.OUT is greater than the voltage on C2, A2/Q1 dumps current into C2 until the voltages match. Using a transistor rather than a diode greatly improves the speed; as drawn, with R2 = 22R, it will capture a single half-cycle at 20 kHz, as shown in Figure 2 which is way faster than the PPM spec calls for. (For a slower, more realistic response, increase R2. 1k5 gives a ~5 ms response time to within 1 dB of the final reading.) This may seem to be several op-amps short of a “proper” peak detector, but it does the job in hand: it’s been Muntzed. (Muntz? Who he? This will explain.) Taking A2.IN- directly from C2, which might seem more usual, leads to overshoot or slows the response, depending on the value of the series resistor.

Figure 2 The attack or integration time is very fast; the decay or return time, much slower, and linear.

Now that we have charged C2 fast, we need to discharge it slowly. A3 buffers its voltage, with D3/R4 bootstrapping R3 to give a linear fall in voltage equivalent to 20 dB in 1.7 s, which, more by happy accident than by design, is exactly what we want.

Now we pass the signal through D4, whose tempco of about -2 mV/°C compensates for that of D1/2. It also drops the level by its VF of about 600 mV, which needs restoring. D5 is shown as a generic 1.25 V shunt stabiliser, and its exact type or value is not critical. (I used an LM385 which was to hand; with a clean, stable negative supply rail, it can be designed out.) It provides an accurate source for offsetting not only D4’s VF, but also the signal as a whole, to set the meter needle’s zero point. R8 allows adjustment of this from about -62 dBu (R8 = 10k) to +1 dBu (R8 = zero).

A4 drives the meter movement, buffering the voltage from D4, the offset-voltage compensation being applied through R9. A4 drives current through the meter into R11, the resulting voltage across that being fed back through R10 to close the feedback loop. The meter has D6 in series with it to prevent underswings, and D5 catches negative swings on A4. (Shame we can’t do the same for A2.)

Calibration is simple. Apply the minimum input level at the input, or apply a DC voltage corresponding to the minimum negative peak value to the signal end of R1, and adjust R8 for zero indication on the meter. Now apply the maximum level—I chose +10 dBu—and set R11 for full-scale deflection. R8 must be set first, then R11.

Temperature stability is good. According to LTspice, the tempco is zero at around +1 dBu input and reasonable at other levels, giving a reading correct within 1 dB down at -50 dB or so for 15 to 35°C. Frustratingly, I could only get better compensation by adding extra resistors and a thermistor in a network around R10, the values differing according to the desired span: too many interactions. An extra stage could have fixed this, but . . . Figure 3 shows the response of the meter, both simulated and live.

Figure 3 Simulated and measured responses when set up for a 50 dB span with a +10 dBu maximum reading, showing the effects of temperature and op-amp offset.

We now have a high-performance meter, with near-digital accuracy and even precision. But it’s still only half-wave sensing, and has a couple of residual bugs. For full-wave operation, we can add inverter A5, etc., to the output of A1, along with a second peak-detection stage, A6 and Q2, effectively paralleled with A2 and Q1, to add in the contribution from positive-going inputs: see Figure 4. If A1 and A5 have zero offset voltage or if a few trimmer-derived millivolts are applied to A2.IN+ and A5.IN+, C3 can be omitted. The input offsets inherent in real-world (and cheap) op-amps limit the span, as they lead to inaccuracies at low levels, where the signal to be measured is comparable with them.

Another way of adding bipolar detection would have been to use a full-wave rectifier at the input, but the extra op-amp offsets made this approach too inaccurate without messy trimming.

Figure 4 Extra components can be added for full-wave detection.

This circuit responds faster than a meter movement can follow. C2 may be charged almost instantaneously by a transient, but its voltage will decay by an indicated 11.8 dB/second (or 20 dB in 1.7 s). Thus, if the meter takes 85 ms to respond, it will under-read that transient by 1 dB. Figure 5 shows how to cure this.

Figure 5 Final additions: a “power-on reset”, and a monostable to give ~100 ms hold time after a peak to allow the meter movement to catch up.

A7 and A8 form a monostable, which is triggered by a sharp increase in C2’s voltage and generates a positive pulse at A7.OUT. Connecting this to R4, which no longer goes to Vs-, via a diode cures the problem: while A7.OUT is low, C2 will discharge in the normal way, but while it is high, C2’s discharge path is effectively open-circuited. As shown, and with +/-6 V rails, this hold time is ~100 ms. Adjust C5 or R16 to vary this. The result can be seen in Figure 2.

A final touch is a power-on reset, also shown in Figure 5. (Digital circuits usually have them, so why should we be left out?) A sharp rise of the positive rail turns on Q3—which may be almost any n-MOSFET—for a few hundred milliseconds, clamping C2 to ground while the circuitry stabilises. Without this, C2 may charge to a high level at power-on, taking many seconds to recover.

Although a 100 µA meter movement is shown, A4 will comfortably drive several milliamps. Select or adjust R11 to suit.

While you may not want to build a complete meter like this, the techniques and ideas used here may well come in handy for other projects. But if you do, be sure to use an ebonite-cased movement, complete with polished brass inlays, and with a pointer based on a Victorian town-hall clock’s minute hand. Electro-punk lives!

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

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Upfront in late November 2023’s most recent edition of the “Holiday Shopping Guide for Engineers” series was my recommendation to pick up a recently-introduced Raspberry Pi 5. But here we are, two months later as I write these words, and the Raspberry Pi 5 is still essentially sold out (echoing, ironically, my commentary introducing that shopping guide section, wherein I documented the longstanding supply constraints of its Raspberry Pi 4 precursor). I know. In my defense, however weak, I’ll note that I did write those words 1.5 months earlier, in mid-October (that excuse didn’t work, did it?). That said, the Raspberry Pi Foundation swears that production will ramp dramatically very soon, with supply improving shortly thereafter. Will it? I don’t know.

I bet at least some of you think that I get “special treatment” with the tech companies in constrained-supply situations like these, don’t you? Ha! Just two weeks ago, I finally gave up waiting on retailer supply and purchased a brand-new 8 GB Raspberry Pi 5 board plus an official case from a guy on eBay. He said he’d accidentally bought two of each and didn’t need the spare combo. Whatever. I didn’t get reseller-marked-up too badly, compared to most of the ridiculous pricing I’m seeing on eBay and elsewhere right now. The 8 GB board MSRP is $80, while that of the case is $10. I paid $123.39 plus tax for the combo, which probably left him with a little (but only a little) profit after covering his hardware costs plus the tax and shipping (or gas) he paid.

Don’t get me started on the Active Cooler shown in the first photo, which, if I wasn’t such a trusting fellow, I might think it doesn’t actually exist. Regardless, I still needed a power supply. A 5 V/3 A supply with a USB-C output such as the Raspberry Pi 15W USB-C Power Supply (standard “kit” for the Raspberry Pi 4, for example) might also work for the Raspberry Pi 5, especially if you only boot off a SD card and don’t have a lot of hooked-up, power-sucking peripherals:

That said, the Raspberry Pi 5’s bootup code will still grumble at you via displayed messages indicating that “current draw to peripherals will be restricted to 600mA.” And if you want to boot off a USB flash stick instead, you’ll need to tweak the config.txt prose first. Don’t even think about trying to boot off the m.2 NVMe SSD HAT (speaking of suspect vaporware) with only a 15 W PSU. And in general, you and I both know that the very first things I’ll likely do when I fire up my board are to run lengthy benchmarks on it, constrain its ventilation flow and see when clock throttling kicks in, try overclocking it, and otherwise abuse it. So yeah…27 W (or more).

The Raspberry Pi 27 W USB-C Power Supply shown above, in its white color option (black is also available) and UK plug option (among several others also available), in all cases matching the variants available with its 15 W sibling, was one obvious candidate. But…I know this is going to surprise you…it’s also near-impossible to track down right now. No problem, I thought. I have a bunch of 30 W USB-C wall warts lying around; I’ll just use one of them. Which, more than 500 words in, is where today’s story really begins.

Problem #1 centers on the term “wall wart”. More accurately, as the Wirecutter points out, I should probably be calling them “chargers” because fundamentally that’s all they are: power sources for recharging the batteries integrated within various otherwise-untethered devices (laptops, smartphones, tablets, smartwatches, etc.). Can you not only recharge a widget’s integrated battery but also simultaneously power that widget from the same charger? Sure, if the output power is high enough to handle this simultaneous-energy multitasking.

But trying to run a non-battery-powered device from a charger can be a recipe for disaster, specifically when that charger’s output power is close to what the device demands (such as my suggested 30 W charger for a Raspberry Pi 5 that wants to suck 27 W). Why? Chargers aren’t exactly known for being predictable in output as the power demands of whatever’s on the other end of the USB-C (which I’m using as an example here, although the concept’s equally relevant to USB-A and other standards) cable increase. As you near supposed “30 W”, for example, the output voltage might sag or, at minimum, exhibit notable ripple. The output current might also droop. Not a huge deal if all you’re doing is recharging a battery; it’ll just take a little longer than it might otherwise. But try to directly power a Raspberry Pi 5 with one? Iceberg dead ahead!

About that “30 W” (Problem #2)…if the wall wart has only one output, you can safely surmise that you’ll get a reasonable facsimile of that power metric out of it. But what if there are two outputs? Or more? And what if you only tap into one of the outputs? Will you get the full spec’d power, or not? The answer is “it depends”, and unfortunately the vendors don’t make it easy to get more precise than that. Here’s an example: remember the 30 W single-port USB-C GaN charger that I dissected around a year ago? Well, VOLTME also makes a two-output 35 W model:

Kudos to the company, as this graphic shows:

When either output is used standalone, it delivers the full 35 W. Use both outputs at the same time, on the other hand, and each is capable of 18 W max. Intuitive, yes? Unfortunately, as far as I can tell, VOLTME’s the exception here, not the norm. Take, for example, the two-output 70 W Spigen GaN charger that I take with me on trips:

It’s smaller and lighter than the single-output conventional-circuitry charger that came with my MacBook Pro. It’s also got enough “umph” (and outputs) to juice up both my laptop and my iPad Pro. Plus, its AC prongs are collapsable; love ‘em when jamming the adapter in my bag. All good so far. But one of the outputs is only 60 W max when used standalone and only 50 W max when used in tandem with the other (20 W max). The more powerful output is the bottom of the two in the above photo. And it’s not marked as such on the front panel for differentiation purposes. Inevitably, in the absence of visual cues to the contrary, I end up plugging my laptop into the upper, weaker output port instead.

Problem #3, particularly for 5 V devices on the other end of the cable, involves inconsistent output power at various output voltages. Let’s look back at that 30 W VOLTME teardown again:

I’ve written (more accurately, I suppose, ranted) before about USB-PD (Power Delivery), which supports upfront negotiation between the “source” and “sink” on their respective voltage and current capabilities-and-requirements, leading to the potential for higher output power. Programmable power supply (PPS), an enhancement to USB PD 3.0, supports periodic renegotiation as, for example, a battery nears full charge. Quoting from a Belkin white paper on the topic:

Programmable Power Supply (PPS) is a standard that refers to the advanced charging technology for USB-C devices. It can modify in real time the voltage and current by feeding maximum power based on a device’s charging status. The USB Implementers Forum (USB-IF), a nonprofit group that supports the marketing and promotion of the Universal Serial Bus (USB), added PPS Fast Charging to the USB PD 3.0 standard in 2017. This allows data to be exchanged every 10 seconds, making a dynamic adjustment to the output voltage and current based on the condition of the receiving device’s specifications. PPS’ main advantage over other standards is its capability to lower conversion loss during charging. This means that less heat is generated, which lengthens the device battery’s lifespan.

I mention this because the above photo indicates that this charger support PPS. But let’s backtrack and focus on its supported USB-PD options. It’s a 30 W charger, right? Well:

• 20 V x 1.5 A = 30 W
• 15 V x 2 A = 30 W
• 12 V x 2.5 A = 30 W

The next one isn’t exactly 30 W, but I’d argue that close still counts not only in horseshoes and hand grenades but also with inexpensive-but-still-impressive chargers:

• 9 V x 3 A = 27 W

But what’s the deal with that last one?

• 5 V x 3 A = 15 W

Hmmm…mebbe just a quirk of this particular charger? How about this big bad boy from Anker?

Single output. 100 W. Surely, it’ll pump out more than 3 A at 5 V, right? Nope:

• 5 V x 3 A = 15 W
• 9 V x 3 A = 27 W
• 12 V x 3 A = 36 W
• 15 V x 3 A = 45 W
• 20 V x 5 A = 100 W

And just determining this information necessitated tedious searching for a user manual online at a third-party site. I couldn’t even find mention of the product (via either its 317 product code or A2672 model number) on the manufacturer’s own website! And at this point, I’ll cut to the chase: they’re pretty much all like this.

That a charger will only output 100 W to a device that indicates it can handle 20 V is no shortage of smoke and mirrors in and of itself. But I’m actually willing to give the charger suppliers at least something of a “pass” here. Consumers value not only output power but also size, weight, and the all-important price tag, among other things. These factors likely constrain per-port (if not per-device) output current to 5 A or so. If I’m a portable computer manufacturer and I need 100vW of input power to support not only AC-connected operation but also in-parallel battery recharge at a reasonable rate, I’m going to make darn sure my device can handle a 20 V input!

But what about this seeming 3 A limitation for the 5 V output option? It’s not universal, obviously, since the Raspberry Pi 27 W USB-C power supply supports the following options:

• 1 V x 5 A = 25.5 W
• 9 V x 3 A = 27 W
• 12 V x 2.25 A = 27 W
• 15 V x 1.8 A = 27 W

In contrast, BTW, the official Raspberry Pi 15 W USB-C power supply only does this:

• 1 V x 3.0 A = 15.3 W

My guess as to the root cause of this 5 V@3 A preponderance comes from a clue in a post on the Electrical Engineering Stack Exchange site that I stumbled across while researching this writeup:

The question is about USB Type-C connectivity.

The Type-C connectivity provides two methods of determining source capability.

The primary method is the value of pull-up on HOST side on CC pins. Type-C specifications define three levels of capability: 500/900 mA (56k pull-up to 5V), 1.5 A (22k pull-up), and 3A (10k pull-up). The connecting device pulls down this with 5.1k to ground, and the resulting voltage level tells the device how much current it can take over the particular connection. When the host sees the pull-down, it will turn on “+5Vsafe” VBUS. This is per Type-C protocol.

The secondary method is provided by nearly independent Power Delivery specification. If the consumer implements PD, it still need to follow Type-C specifications for CC pull-up-down protocol, and will receive “+5Vsafe” VBUS.

Only then the consumer will send serial PD-defined messages over CC pin to discover source capabilities. If provider responds, then negotiations for power contract will proceed.

If the consumer is not PD-agnostic, no messages will be generated and no responses will be returned, and no contract will be negotiated. The link power will stay at the default “Safe+5VBUS” power schema, per DC levels on CC pins.

Here’s the irony…my Raspberry Pi 4 board that I mentioned earlier? It’s the rare, early “Model A” variant, which contained an insufficient number and types of resistors to work correctly with some USB-C cables. But that’s not what’s going on here. As the above explanation elucidates, USB-C chargers must (ideally) at minimum support 5 V@3 A for broadest device compatibility. What I’m guessing mostly happens beyond this point is that charger manufacturers focus their development attention on other voltage/current combinations enabled by the secondary compatibility negotiation, leaving the 5 V circuitry implementation well enough alone as-is.

Agree or disagree, readers? Anything more to add here? I look forward to your thoughts in the comments! Meanwhile, I have a Raspberry Pi 27 W USB-C power supply on order from an overseas supplier…and I wait…

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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Soon after Synopsys snapped up multiphysics simulation toolmaker Ansys, Cadence has responded by announcing the acquisition of engineering simulation supplier BETA CAE Systems International AG for approximately $1.24 billion. BETA CAE, which provides simulation software solutions for automotive and other industries like aerospace and industrial, is based in Lucerne, Switzerland.

BETA CAE’s solutions encompass the entire simulation and analysis flow for multiphysics system simulations, spanning mechanical/structural, computational fluid dynamics (CFD), and electromagnetics (EM). Take, for instance, ANSA, a multidisciplinary computer-aided engineering (CAE) pre-processor that facilitates functionality for full-model build-up in an integrated environment.

Cadence, which entered the multiphysics space several years ago, apparently wants to expand its multiphysics system analysis portfolio and enter structural analysis, the largest system analysis segment. The EDA firm aims to combine its computational software expertise with BETA CAE’s technology to tap into the structural analysis segment.

That’s especially critical for automotive, where the convergence of electrical and mechanical designs is further driven by an increasing shift toward electric vehicles (EVs). BETA CAE has a strong presence in the automotive and aerospace markets, and its customers include Honda Motor, General Motors, Stellantis, Renault, Volvo, and Lockheed Martin.

Multi-domain engineering simulation solutions recently came into the limelight after Cadence’s archrival Synopsys acquired Ansys. Their critical importance amid the mechanical and electrical hyperconvergence is once more affirmed by Cadence’s decision to buy BETA CAE. The acquisition, subject to regulatory approval, is expected to close in the second quarter of 2024.

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The post Cadence taps into structural analysis by acquiring BETA CAE appeared first on EDN.

The schematic below was screen-shot from a LinkedIn group. I heard alarm bells go off in my head when I saw it (Figure 1).

Figure 1 A suggested application note diagram found in a LinkedIn group with a floating node between C4 and C5 that could lead to voltage breakdown.

Capacitors C4 and C5 are placed in series with each other so that their common node has no DC path to anywhere. When I worked on some spacecraft projects, this was absolutely a forbidden thing to do because any floating node like this could drift to an indeterminately high voltage and lead to voltage breakdown.

Even in an earthly milieu, this can be a problem. Imagine something being used or merely being transported or shipped in a thunderstorm environment. Dr. Frankenstein’s lightning bolts could do some real harm.

I have no idea why in the above schematic the series pair of C4 and C5 wasn’t simply made a single 0.5 pF capacitance.

The basic badness of letting something float has been looked at before in “Design precaution: Leave nothing floating”.

It looks like someone didn’t get the message.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post No floating nodes appeared first on EDN.

For several decades, the semiconductor industry has been looking for alternative memory technologies to fill the gap between dynamic random-access memory (DRAM), the compute system’s main memory, and NAND flash—the system’s storage medium—in traditional high-performance computing system architectures.

Such an alternative memory—historically referred to as storage class memory—should outperform DRAM in terms of density and cost and, at the same time, be accessible much faster than NAND flash. The demand for these memories has recently been fueled by a surge in data-intensive applications like generative AI, requiring vast amounts of data to be accessed quickly.

The 1-PCM/1-OTS device: An intermediate solution

Around 2015, the answer came from a new type of non-volatile memory technology, called 3D XPoint, with phase-change memory (PCM) cells arranged at the ‘cross points’ of word and bit lines. PCM memory cells are made of chalcogenide ‘phase-change’ materials, such as germanium antimony telluride (GeSbTe), sandwiched between two electrodes. The material can quickly and reversibly switch between a high-conductive crystalline phase and a low-conductive amorphous phase, and this resistance contrast is used to store information.

Each PCM memory cell is put in series with a selector device, which is needed to address/select the memory cell in the array for program and read operations and to avoid interactions with adjacent cells. While previous versions of PCM used a transistor as a selector device, 3D XPoint memory makers took a different approach: they used so-called ovonic threshold switching (OTS) devices, made of the same class of material—chalcogenides—as the PCM bit cell itself.

The technology became available as a commercial product under the brand name Optane from 2017 onwards. While the first generation was introduced at the NAND side of the DRAM-NAND gap, a later generation was pushed toward the DRAM side. This move was facilitated by the simultaneous introduction of the double data rate (DDR) memory interface, providing a much-needed increase in the speed and bandwidth at which data could be transferred between the PCM memory and the memory controller.

Despite the performance improvement, the technology struggled to deliver the required speed, power, and reliability and to retain its place in the memory market. The power issue mainly arises from the high current needed to switch the PCM bit cell. But there were also constraints related to size and cost. One of the major bottlenecks came from the device architecture itself—the ‘serial’ combination of the bit cell and the OTS selector device.

On first consideration, the 1-PCM/1-OTS outperforms DRAM in terms of cost and area, fostered by the ability to stack the memory array on top of the peripheral circuit. However, these benefits would fade out when one would further increase the density by scaling the bit cell and stacking multiple cross-point layers.

The presence of the additional selector device in series with the PCM bit cell would lead to high-aspect-ratio structures and induce expensive lithography and patterning steps in each of the stacked 2D planar layers. Not to mention the increase in complexity when aiming for true 3D devices, where PCM and OTS materials are mounted on a vertical ‘wall’ by conformal deposition—in a 3D-NAND-like fashion. In 2022, the product was withdrawn from the market.

The OTS selector: its role and operation in a cross-point array

When resistive types of memories such as PCM are arranged in a cross-point array, reading, and writing of the memory cells ideally takes place only on the selected cell, leaving the rest of the cells unaffected. However, in reality, sneak currents run through the unselected cells during memory operation, degrading selectivity and leading to incorrect information retrieval.

Selector devices—usually transistors or diodes—are, therefore, connected serially with each resistive memory element. Their role is to address (or select) the memory bit cell for programming/reading and suppress unwanted sneak currents.

Figure 1 Illustration of the role of a selector device (S) in a cross-point architecture is shown along with resistive memory elements (R). On top, sneak currents run through the unselected cells without a selector, while on bottom, a selector device serially connected to a resistive memory element prevents the occurrence of unwanted sneak currents. Source: imec

Ovonic threshold switching (OTS) devices can be a good alternative to transistor-based selectors. OTS devices are named after Stanford Ovshinsky, who discovered reversible electrical switching phenomena in various amorphous chalcogenide materials in the late 1960s. About 50 years later, interest in these materials led to the development of the OTS selector, an OTS material sandwiched between two metal electrodes.

When the applied voltage exceeds a specific threshold voltage (Vth), the OTS material experiences a fast drop in resistivity, enabling a high current to flow. This current (Ion) is used to program and read the serially connected memory cell. The other devices in the array are biased in such a way that the voltage is only half of the threshold voltage. At this voltage, the (leakage) current (or Ioff) is extremely low (due to the OTS behavior), and this prevents the undesired programming of adjacent cells.

Figure 2 In a typical I-V characteristic of an OTS selector device, at half the threshold voltage, the Ioff current is sufficiently low to prevent interaction with adjacent cells. Source: imec

OTS selectors have several advantages compared to transistor-based solutions. Unlike transistors, which are three-terminal devices, OTS devices are two-terminal devices. This considerably saves area and enables higher densities. The fabrication of an OTS device is also less expensive. Moreover, OTS materials exhibit a high non-linearity—enabled by the low off current at half the threshold voltage—leading to high selectivity.

In addition, they have a large drive current (Ion), can operate at high speed, and have a sufficiently high endurance. And they enable a 3D-compatible solution by stacking 2D planar arrays or enabling true 3D solutions.

The performance and scalability of OTS selectors have improved much over the years, thanks to the past efforts to enable successive generations of the 1-PCM/1-OTS-based Optane memory. In 2015, imec began investigating and developing improved versions of the OTS selector. For example, engineering the material stack for enhanced performance and (thermal) stability, developing new process flows, exploring 3D integration routes, and examining the underlying physical mechanism.

Turning point: the observation of a memory effect in OTS devices

While trying to identify the switching mechanism in OTS selectors, researchers at imec observed an interesting phenomenon. When applying a voltage pulse of a certain polarity—so, either a positive or a negative voltage pulse—they observed that the threshold voltage of the OTS device changed noticeably if the previous pulse had the opposite polarity.

In other words, the threshold voltage seemed to ‘remember’ the polarity of the previous pulse, even after several hours. This discovery opened doors to the development of ‘OTS-only memories’ that exploit this polarity-induced shift in threshold voltage to store and read information. The beauty of the concept? This single element can act as a memory and a selector in cross-point architectures.

Figure 3 In the graph showing the polarity-induced shift in OTS devices, if the read pulse has a different polarity compared to the write pulse, a larger threshold voltage is observed compared to a write-read sequence with the same polarity. Source: imec

This new memory technology can potentially overcome some of the limitations of 1-PCM/1-OTS memories. Having only one material system for selection and memory makes these devices much easier to fabricate and integrate, benefiting cost and density, especially in 3D configurations. In addition, the current needed to write the device promises to be much lower than the current needed for switching PCM cells, resulting in a more energy-efficient memory technology.

Figure 4 The material system of the OTS-only memory (right) is much simpler than the material system needed to fabricate 1S1R cells (left). Source: imec

Imec was the first to publicly report this memory effect in SiGeAsTe-based OTS devices in 2021. After more extensive work, an alternative, Se-based material system led to a practically usable memory window of 1 V, defined by the shift in threshold voltage.

Meanwhile, other research groups have started to report a similar observation, using a variety of names to describe the memory: OTS-only memory, self-selecting memory, self-rectifying memory, or selector-less memory. This also led to an increased number of contributions at the recent 2023 IEDM conference, illustrating the growing interest of the semiconductor community in this promising OTS-only memory technology.

Making OTS-only memory technology suitable for CXL memories

A few years ago, the introduction of memory technologies toward the DRAM side of the DRAM-NAND gap was further supported by introducing the compute express link (CXL) interconnect. This open industry standard interconnect offers low-latency and high-bandwidth connections between the memory and the processor in high-performance computing applications. It also resulted in a new name for the class of memories in the DRAM-NAND gap: CXL memories.

While the OTS device had been optimized for selector applications, new requirements were imposed on the technology to be suitable as a CXL memory. The challenge is to find the most optimal tradeoff between endurance, retention, and power consumption. For CXL-type applications, power consumption (mainly determined by the current needed to switch the memory element) and endurance (targeting at least 1012 write/read cycles before failure) are the most critical parameters, while some compromise is allowed on the retention.

The retention time determines how long the memory can remain in a well-defined state without being refreshed. For CXL-type applications, a retention of a few hours or days is sufficient. This means the stored information must be refreshed periodically but less frequently than in ‘leaky’ DRAM devices.

Imec’s OTS-only memory devices are made of a SiGeAsSe OTS material system sandwiched between carbon-based bottom and top electrodes. The devices, manufactured on a 300-mm wafer, are scalable and easy to fabricate and integrate. They exhibit an endurance of >108 cycles, fast read/write operation ensuring low latency (read and write pulses are as short as 10 ns), and an ultra-low write current <15 µA (i.e., <0.6 MA/cm2).

The latter corresponds to a ~10x energy reduction compared to a typical PCM device. With a half-bias non-linearity NL1/2 ~104, good selectivity is provided, also when operated in memory mode. The polarity-induced voltage shift persists over time, allowing the achievement of a reasonable retention time (>1 month at room temperature). The memory can operate at positive and negative read polarity, showing memory windows of around 1 V and 0.5 V, respectively.

Figure 5 TEM image of the fabricated SiGeAsSe device is shown along with C-based electrodes. Source: T-ED

Figure 6 Demonstration of switching at ultra-low write current with sufficiently large memory window is shown on left and memory window for both read polarities as a function of write current on right. Source: T-ED

Material research a route to 3D integration

The above results highlight the potential of OTS-only memories for CXL applications. So, imec has identified critical directions for further research to advance the devices toward industrial uptake.

Material research is needed for several reasons. First, current OTS material systems contain elements such as As and Se that are toxic and not environmentally friendly. Finding alternative eco-friendly material systems that perform as good, or even better, than current OTS materials therefore is a priority.

Second, material and device design optimizations are needed to improve the reliability to further enhance the endurance to >1012 and lower the cell-to-cell variability. In addition, the threshold voltage is observed to drift over time, contributing to a cycle-to-cycle variability and impacting the retention time.

Reliability improvement goes hand in hand with a fundamental understanding of the physical mechanism that determines the polarity effect in OTS-only memories. So far, this mechanism is not completely clear. Learning what causes the threshold voltage shift is crucial to explain and predict the observed failures and identify the fundamental tradeoffs that limit device performance.

Figure 7 Cartoon of an OTS-only memory is shown in a true 3D architecture. Source: imec

Finally, imec is exploring routes toward true 3D integration, which will be needed to boost the density of the memory bit cells for next-gen compute system architectures.

Daniele Garbin is an R&D Engineer with research interests in OTS and various emerging memory device technologies.

Gouri Sankar Kar is VP of memory and program director of exploratory logic at imec.

Related Content

• Can the Optane Gap Be Filled?
• Emerging memories move to replace embedded NOR flash
• Processor Startup Innovates Memory Allocation Management
• Emerging Memories May Never Go Beyond Niche Applications
• How Emerging Memory Supports Next-Gen Computing in the Data Explosion Era

The post The promise of OTS-only memories for next-gen compute appeared first on EDN.

When a design needs auxiliary voltage rails and the associated current loads are modest, capacitor pump voltage multipliers are often the simplest, cheapest, and most efficient way to make them.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The simplest of these is the diode pump voltage doubler. It consists of just two diodes and two capacitors but has the inherent disadvantages of needing a separately sourced square wave for drive and of producing an output voltage that’s at least two diode drops less than twice the supply rail. Active switching (typically with CMOS FETs) is required to avoid this inefficiency and accurately double the supply.

CMOS voltage doubler chips are available off the shelf. An example is the Maxim MAX1682. It serves well in applications where the current load isn’t too heavy, but it (and similar devices) isn’t particularly cheap. The 1682 costs nearly $4 in singles, creating the temptation to see if we can do better, considering that generic CMOS switch chips (like the 74AC14) can be had in singles for 50 cents.

A plan to do so begins with Figure 1, showing a simplified sketch of a CMOS logic inverter.

Figure 1 Simplified schema of typical basic CMOS gate I/O circuitry showing clamping diodes and complementary FET switch pair.

Notice the input and output clamping diodes. These are put there by the fabricator to protect the chip from ESD damage, but a diode is a diode and can therefore perform other useful functions, too. Similarly, the P-channel FET pair was intended to connect the V+ rail to the output pin when outputting a logic ONE, and the N-channel for connection to V- to pin for a ZERO. But CMOS FETs will willingly conduct current in either direction. Thus, current running from pin to rail works equally well as from rail to pin. 

Figure 2 shows how these basic facts relate to charge pumping and voltage multiplication.

Figure 2 Simplified voltage doubler, showing driver device (U1), commutation device (U2), and coupling (Cc), pump (Cp), and filter (Cf) capacitors.

Imagine two inverters interconnected as shown in Figure 2 with a square-wave control signal coupled directly to U1’s input and through DC blocking cap Cc to U2 with U2’s input clamps providing DC restoration.

Consider the ONE half cycle of the square-wave. Both U1 and U2 N-channel FETs will turn on, connecting the U2 end of Cp to V+ and the U1 end to ground, charging Cp to V+. Note the reversed polarity of current flow from U2’s output pin due to Cp driving the pin negative.

Now consider what happens when the control signal reverses to ZERO.

The P FETs will turn ON while the N FETs turn OFF. This forces the charge previously accepted by Cc to be dumped to Cf through U2’s output and V+ pin, thus completing a charge-pumping cycle that delivers a quantum of positive charge to be deposited on Cf. Note reversed current flow through U2 occurs again. The cycle repeats with the next alternation of the control signal, and so on, etc., etc.

During startup, until sufficient voltage accumulates on Cf for normal operation of U2’s internal circuitry and FET gate drive, U2 clamp diodes serve to rectify the Cp drive signal and begin the charging of Cf until the FETs can take over.

So much for theory. Translation of Figure 2 into a complete voltage doubler is shown in Figure 3.

Figure 3 Complete voltage doubler: 100 kHz pump clock set by R1C1, Schmidt trigger , driver (U1), and commutator (U2)

A 100 kHz pump clock is output on pin 2 of 74AC14 Schmidt trigger U1. This signal is routed to the five remaining gates of U1 and (via coupling cap C2) the six gates of U2. Positive charge transfer occurs through C3 into U2 and from there accumulates on filter cap C5.

Even though Schmidt hysteresis isn’t really needed for U2, another AC14 was chosen for it in pursuit of matched switching delay times, thus improving efficiency-promoting synchronicity of charge transfer. Some performance spec’s (V+ = 5V) are:

• Impedance of 10 V output: 8.5 Ω
• Maximum continuous load: 50 mA
• Efficiency at 50 mA load: 92%
• Efficiency at 25 mA load: 95%
• Unloaded power consumption: 440 µW
• Startup time < 1 millisecond

So, what happens if merely doubling V+ isn’t enough? As Figure 4 illustrates, this design can be easily cascaded to make an efficient voltage tripler. Extension to even higher multiples is also possible.

Figure 4 Adding four inexpensive parts suffices to triple the supply voltage.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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• Easy four-quadrant multiplier using a quad op amp
• A simple, accurate, and efficient charge pump voltage inverter for $1 (in singles)

The post Efficient voltage doubler is made from generic CMOS inverters appeared first on EDN.

Editor’s Note: This is a four-part series of DIs proposing improvements in the performance of a “traditional” PWM—one whose output is a duty cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to produce a DAC. The first part suggests mitigations and eliminations of common PWM error types. The second discloses circuits driven from various Vsupply voltages to power rail-rail op amps and enable their output swings to include ground and Vsupply. This third part pursues the optimization of post-PWM analog filters.

 Part 1 can be found here.

 Part 2 can be found here.

Recently, there has been a spate of design ideas (DIs) published (see Related Content) which deals with microprocessor-generated pulse width modulators driving low-pass filters to produce DACs. Approaches have been introduced which address ripple attenuation, settling time minimization, limitations in accuracy, and enable outputs to reach and include ground and supply rails. This is the third in a series of DIs proposing improvements in overall PWM-based DAC performance. Each of the series’ recommendations are implementable independently of the others. This DI addresses low pass analog filters.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The PWM output

Spectrally, the PWM output consists of a desirable DC (average) portion and the remainder—undesirable AC signals. With a period of T, these signals consist of energy at frequencies n/T, where n = 1, 2, 3, etc., that is, harmonics of 1/T. If the PWM switches between 0 and 1, for every harmonic n there exists a duty cycle corresponding to a peak signal level of (2/π)/n. This shows the futility of an attenuation scheme which focuses on a notch or band reject type of filter—there will always be a significant amount of energy that is not attenuated by such. The highest amplitude harmonic is the first, n = 1. At the very least, this harmonic must be attenuated to an acceptable level, α. Any low pass filter that accomplishes this will apply even more attenuation to the remaining harmonics which are already lower in level than the first. In summary, the search for the best filter will focus on what are called all-pole low pass filters, which is another way of saying low pass filters which lack notch and band-reject features.

The skinny on low pass all-pole filters

Analog filters can be defined as a ratio of two polynomials in the complex (real plus imaginary) variable s:

Where I ≤ K. The terms zi and pi are referred to respectively as the zeroes and the poles of the filter. K is the order (first, second, etc.) of the filter as well as the number of its poles. All-pole filters of unity gain at DC can be specified simply as:

Filter types include Butterworth, Bessel, Chebyshev, and others. These make different trade-offs between the aggressiveness of attenuation with increasing stop-band frequency and the rapidity of settling in response to a time domain impulse, step, or other disturbance. Improving one of these generally denigrates the other. Tables of poles for various orders and types of these filters can be found in the reference [1]. Values given are for filters which at approximately 1 radian per second (2π Hz) exhibit 3 dB of attenuation with respect to the level at DC. This point is considered to be the transition between the low frequency pass and high frequency stop bands. Multiplying all poles by a frequency scaling factor (FSF) will cause the filter to attenuate 3 dB at 2π·FSF Hz. The frequency response of a filter can be calculated by substituting j·2π·f for s in H(s) and taking the magnitude of the sum of the real and imaginary parts. Here, j = √-1 and f is the frequency in Hz.

The time domain response of a filter to a change in PWM duty cycle reveals how quickly it will settle to the new duty cycle average. For a filter of unity gain at DC, this involves subtracting from 1 the inverse Laplace transform of H(s)/s. A discussion of Laplace transforms, their inverses, and practical uses is beyond the scope of this DI. These inverse transforms can, however, be readily determined by using a web-based tool [2].

Requirements of an optimal filter

A filter must attenuate the maximum value over all duty cycles (2/π) of the PWM first harmonic by a factor of α. A b-bit PWM has a resolution of Full-Scale·2-b. So, for the first harmonic peak to be no greater than ½ LSB, α should be set to (π/2)·2-(b+1). Asking for more attenuation would slow the filter response to a step change in duty cycle. From the time domain perspective, the time ts should be minimized for the filter to settle to +/- α · Full Scale in response to a duty cycle change from Full Scale to zero.

Towards an optimal filter

Consider a 12-bit PWM clocked from a 20 MHz source. The frequency of its first harmonic is F0 = 4883 Hz, and its α is 1.917·10-4. 3rd, 5th, and 7th order filters of types Bessel, Linear Phase .05° and .5° Equiripple error, Gaussian 6 dB and 12 dB, Butterworth, and .01 dB Chebyshev are considered. These are roughly in order of increasingly aggressive attenuation with frequency coupled with increasing settling times. Appropriate FSFs are needed to multiply the poles (listed in reference [1]) of each filter to achieve attenuation α at F0 Hz. Excel’s Solver [3] was used to find these factors. The scaled values were divided by 2π to convert them to Hertz and applied to LTspice’s [4] 2ndOrderLowpass filter objects in its Special Functions folder to assemble complete filters. The graph in Figure 1 shows the frequency responses of 24 scaled filters. These include 3rd, 5th, and 7th order versions of the filter types listed above. These filters were named after the mathematicians who developed the math describing them (I have for some reason failed to find any information about Mr. or Ms. Equiripple). Additionally, there are the same three orders of one more filter type that was developed by the author and will be described later. Although the author makes no claims of being a mathematician, for want of an alternative, these have been named Paul filters. (An appalling choice, I’m sure you’ll agree.)

Figure 1 The frequency response of 24 scaled filters including include 3rd, 5th, and 7th order versions of the 7 filter types listed above (Bessel, Linear Phase, Equiripple, Gaussian, Butterworth, Chebyshev and the Paul filter developed by the author) where the value of α is depicted by the horizontal red line.

In Figure 1, the value of α is depicted by the horizontal line. It and all the filter responses intersect at a frequency of F0 (the PWM’s first harmonic) satisfying the frequency response attenuation requirement. Figure 2 is the Bessel filter portion of the LTspice file which generates the above graph. The irregular pentagons are LTspice’s 2ndOrderLowPass objects. The resistors and capacitors implement first order sections. H = 1 is the filter’s gain at DC.

Figure 2 The Bessel filter portion of the LTspice file which generates the response in Figure 1, U1-U6 are LTspice’s 2ndOrderLowPass objects, resistors and capacitors implement first order sections, and H = 1 is the filter’s gain at DC.

By changing the “.ac dec 100 100 10000” command in the file to “.tran 0 .01 0”, replacing the “SINE (0 1) AC 1” voltage source with a pulsed source “PULSE(1 0 0 1u 1u .0099 .01)” and running the simulation, the response of these filters to a duty cycle step from 1 V to 0 V is obtained as shown in Figure 3.

Figure 3 Replacing the AC voltage source with a pulsed source to change the duty cycle step of the filter response from 1 V to 0 V.

Oh, what a lovely mess! The vertical scale is the common log of the absolute value of the response—absolute value because the response oscillates around zero, and log because of the large dynamic range between 1 and α, the latter of which is again shown as a horizontal line.

Which filter’s absolute response settles (reaches and remains less than α) in the shortest period of time? To find the answer to that question, use is made of LTspice’s “Export data as text” feature under the “File” option made available by right-clicking inside the plot. This data is then imported into Excel. Each filter’s data is parsed backwards in time starting from 10 ms. The first instants when the responses exceed α are recorded. These are the times that the filters require to settle to α. (As can be seen, there were some that require more than 10 ms to do so.) For each filter order, it was determined which type had the shortest settling time. Table 1 shows the settling times to ½ LSB for 8-bit through 16-bit PWMs of 3rd, 5th, and 7th orders of filters of various types.

Table 1 Settling times to ½ LSB for 8-bit through 16-bit PWMs of 3rd, 5th, and 7th orders for various types of filters. The fastest settling times are shown in bold red while those that failed to settle within 10 ms are grey and listed as “> 10 ms”.

The entries in each table row with the fastest settling time is shown in bold red. Those which failed to settle within 10 ms are listed as > 10 ms and are greyed-out. In general, the 7th orders settled faster than the 5th orders, which were noticeably faster than the 3rd’s. Also, those with the lower Q sections settled faster than the higher Q alternatives (again, see the tables in reference [1]). The Chebyshev filters with ripples greater than .01 dB (not depicted) for instance, had higher Q’s than all the ones listed above and had hopelessly long settling times.

As a group, the Paul filters settled the fastest, but that does not preclude the selection of another filter in an instance when it settles faster. Still, it’s worth discussing how the Pauls were developed. Starting with the 3rd, 5th, and 7th order frequency-scaled Bessel poles, the Excel Solver evaluated the inverse Laplace transforms of the filters’ functions H(s). It was instructed to vary the pole values while minimizing the maximum value of the filter response after a given time ts. This was made subject to the constraint that the amplitude response of |H(2πj·F0)| be α, where F0 = 20MHz / 212 and α = (π/2)·2-(12+1). If the maximum response exceeded α for a given ts, ts was increased. Otherwise ts was reduced. Several runs of Solver led to the final set of filter poles. It is interesting that even though the optimization was run for a 12-bit PWM only, settling times at other bit lengths between 8 and 16 is still rather good and in most cases superior to those of the other well-known filters. The Paul filter poles and Qs are listed in Table 2.

Table 2 The poles and Qs for 3rd, 5th, and 7th order Paul filter.

Table 3 includes FSFs for the poles of the well-known filters. The unscaled poles are given in the tables of reference [1]. The scaled poles are characteristic of filters which also attenuate a frequency of F0 by a factor of α.

Table 3 The FSFs for the poles of the well-known filters in the tables of reference [1] for the values of α and F0.

 Implementing a filter

A starting point for the implementation of a filter whose poles are taken from a reference table is to apply to those poles an appropriate FSF.  These factors are given for well-known filters in Table 3 for an attenuation, α, at a frequency of F0 Hz. In Table 2, the Paul filter poles have already been scaled as such. For any of these filters, to change the α from a frequency F0 to F1 Hz, the poles should be multiplied by an FSF of F1/F0.

In settling quickly to the small value of α, some of the biggest errors in filter performance are due to component tolerances. To limit these errors, resistors should be metal film, 1% at worst with 0.1% preferred.  Capacitors should be NPO or C0G for temperature and DC voltage stability, 2% at worst and 1% preferred. Smaller value resistors result in a quieter design and lead to smaller offset voltages due to op amp input bias and offset currents. However, these also require larger-valued, bigger, and more expensive capacitors. Keep these restrictions in mind when proceeding with the following steps.

For a first order section with pole ω:

1. Start by guessing values of R and C such that RC = 1/ω.
2. Choose a standard value NPO or COG capacitor close to that value of C.
3. Calculate R’ = 1/(ω·C) where C is that standard value capacitor.
4. Choose for R the next smaller standard value of R’ and make up the difference with another smaller resistor in series. Although this will not compensate for the components’ 1% and 2% tolerances, it will yield a result which is optimal on average.
5. Connect one terminal of R to the PWM output and the other to the capacitor C (ground its other side) and to the input of a unity gain op amp. If gain is required in the aggregate filter, it is this op amp which should supply it rather than one which implements a second order section; unlike second order sections, gain in this op amp has no effect on the R-C section’s AC characteristics because there is no feedback to the passive components. The output of this op amp should drive the cascade of remaining second order sections (Figure 4).

Figure 4 Recommended configuration where one terminal of R is connected to the PWM output, and the other is connected to the capacitor C (ground its other side) and to the input of a unity gain op amp.

For second order sections with pole ω and quality factor Q, error sources are again component values. Errors can be exacerbated by the choice of a filter topology. A second order Sallen Key [5] section with the least sensitivity employs an op amp configured for unity gain as shown in Figure 5.

Figure 5 A second order Sallen Key section with the least sensitivity employs an op amp configured for unity gain.

To select component values:

1. Start by choosing values of R and C such that RC = 1/ω.
2. Choose standard values of C1 and C2 similar to C such that C1 / C2 is as large as possible, but no larger than 4Q2. Creating a table of all possible capacitor ratios is helpful in selecting the optimal ratio.
3. Calculate D = (1 – 4Q2·C2/C1)0.5 and W = 2·Q·C2·ω
4. For R1a, select a standard resistor value slightly less than (1 + D)/W and add R1b in series to make up the difference.
5. For R2a, select a standard resistor value slightly less than (1 – D)/W and add R2b in series to make up the difference.
6. If there are more than one second order section, the sections should be connected in order of decreasing values of Q to minimize noise.

A PWM filter example

Consider a 5th order Paul filter with an attenuation of α at a frequency F1 = F0/2. Each of the ω values in the Paul filter table would be multiplied by an FSF of F1/F0 = ½, but the Q’s would be unchanged. The following schematic shown in Figure 6 satisfies these constraints.

Figure 6 A 5th order Paul filter scaled to operate at F0/2 Hertz.

 Designing PWM analog filters

A set of tables listing settling times to within ½ LSB of 8 through 16-bit PWMs of period 204.8 µs (1/4883 = 1/F0 Hz) has been generated for 3rd, 5th, and 7th order versions of eight different filter types. These filters attenuate the peak value of steady state PWM-induced ripple to ½ LSB. From these listings, the filter with the fastest settling time is readily selected. These filters can be adapted to a new PWM period by multiplying their poles by a scaling factor equal the ratio of the old to new periods. New settling times are obtained by dividing the ones in the tables by that same ratio.

Pole scaling factors for the operation of well-known filters at F0 are supplied in a separate table. The poles of these filters are available in reference [1] and should be multiplied by the relevant factor to accomplish this. A new “Paul” filter (already scaled for F0 operation) has been developed which in most cases has faster settling times than the well-known ones while providing the necessary PWM ripple attenuation. As with the others, it too can be scaled for operation at different frequencies.

It should be noted that component tolerances will lead to filters with attenuations and settling times which differ somewhat from the calculations presented. Still, it makes sense to employ filters with the smallest calculated settling time values.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content

• Double up on and ease the filtering requirements for PWMs
• Optimizing a simple analog filter for any PWM
• Fast-settling synchronous-PWM-DAC filter has almost no ripple
• Cancel PWM DAC ripple and power supply noise
• Cancel PWM DAC ripple with analog subtraction
• Cancel PWM DAC ripple with analog subtraction—revisited
• Cancel PWM DAC ripple with analog subtraction but no inverter
• Fast PWM DAC has no ripple

 References

1. http://www.analog.com/media/en/training-seminars/design-handbooks/basic-linear-design/chapter8.pdf%20 (specifically Figures 8.26 through 8.36. This reference does a great job of describing the differences between the filter response types and filter realization in general.)
2. https://www.wolframalpha.com/input?i=inverse+Laplace+transform+p*b%5E2%2F%28%28s%5E2%2Bb%5E2%29*%28s%2Bp%29%29
3. https://support.microsoft.com/en-us/office/define-and-solve-a-problem-by-using-solver-5d1a388f-079d-43ac-a7eb-f63e45925040
4. https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
5. https://www.ti.com/lit/an/sloa024b/sloa024b.pdf

The post Parsing PWM (DAC) performance: Part 3—PWM Analog Filters appeared first on EDN.

Along with a dsPIC33 digital signal controller (DSC), motor drivers from Microchip pack a three-phase MOSFET gate driver and optional LIN or CAN FD transceiver. These integrated devices reduce the component count, PCB size, and complexity of embedded motor control systems in space-constrained applications.

Real-time processing is enabled by the dsPIC33 DSC, which operates between 70 MHz and 100 MHz. It provides up to 256 kbytes of ECC flash memory, 12-bit ADCs, and a 32-bit optical/incremental encoder interface. The DSC also supports field-oriented control (FOC) and other advanced motor control algorithms.

The integrated motor drivers operate from a single power supply up to 29 V with transient tolerance up to 40 V. An internal 3.3-V low-dropout voltage regulator powers the dsPIC33 DSC, eliminating the need for an external LDO. Qualified to AEC-Q100 Grade 0 requirements, the devices operate from -40°C to +150°C.

The dsPIC33-based motor drivers are supported by an ecosystem of software and hardware development tools. These include the dsPIC33CK motor control starter kit and MCLV-48V-300W development board. The motorBench development suite is a free GUI-based tool for FOC. Also available are various reference designs, including an automotive cooling fan and drone propeller controller.

dsPIC33 driver product page

Microchip Technology 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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InnoMux-2 is a family of GaN-based flyback switcher ICs from Power Integrations that offers multiple independently regulated outputs. The switchers consolidate AC/DC and downstream DC/DC conversion stages into a single chip, providing up to three independently regulated outputs or two voltage outputs and a constant current output.

The elimination of separate DC/DC stages not only reduces component count and PCB footprint, but also increases efficiency by as much as 10% compared to conventional two-stage architectures. Efficiency is aided by integrated 750-V GaN transistors, zero-voltage switching, and synchronous rectification.

InnoMux-2 ICs deliver up to 90 W of output power with regulation of better than ±3% across input line, load, and temperature. Total power system efficiency (AC to regulated low-voltage DC) is above 90%. The InnoMux-2 controller also manages light-load power delivery, eliminating the need for preload resistors and reducing no-load consumption to less than 30 mW.

Prices for the InnoMux-2 IMX2174F devices start at $1.11 each in lots of 50,000 units. The parts come in thermally efficient InSOP 24 and InSOP 28 packages.

InnoMux-2 product page

Power Integrations

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Asahi Kasei’s CZ39 series of coreless current sensors allows OEMs to design smaller and lighter onboard chargers for electric vehicles. With its fast response time, low heat generation, and noise immunity, the CZ39 enables current measurements in high-speed SiC- and GaN-based power systems.

The current sensor employs a sensitive compound Hall element that enables a response time of 100 ns, fast enough to keep up with the high switching speed of SiC and GaN devices. Its unique package maintains a primary conductor resistance of just 0.3 mΩ.

Even under continuous 40-A current flow at an ambient temperature of +125°C, heat generation is minimal. This reduces the need for bulky thermal management measures. The structure of the package provides sufficient creepage and clearance distances for use in applications above 650 V. CZ39 devices also offer enhanced noise immunity, ensuring continuous and accurate current detection in noisy automotive environments.

Asahi Kasei has begun mass production of the CZ39 series of coreless current sensors. For more information about the CZ39 series, click here.

Asahi Kasei Microdevices

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Quectel has launched four new Wi-Fi and Bluetooth modules to provide designers with a greater array of options in terms of size, cost, and power efficiency. Joining the company’s portfolio of IoT modules are the FCU741R Wi-Fi 4 module and the FCS950R Wi-Fi 5/Bluetooth 4.2 combo module. The HCM010S Bluetooth LE 5.4 module and the HCM111Z Bluetooth LE 5.3 module also extend the IoT lineup.

The FCU741R Wi-Fi 4 module for wireless LAN connections operates at 2.4-GHz and 5-GHz frequencies to deliver a maximum data rate of 150 Mbps. It offers a USB 2.0 interface and operates over a temperature range of -20°C to +70°C.

The FCS950R Wi-Fi 5 and Bluetooth 4.2 module supports IEEE 802.11a/b/g/n/ac and achieves a maximum data rate of 433.3 Mbps in 802.11ac mode. It also furnishes an SDIO 3.0 interface and is just 12.0×12.0×2.35 mm.

Outfitted with an Arm Cortex-M33 processor, the HCM010S module supports both Bluetooth LE 5.4 and Bluetooth mesh networking. Built-in memory comprises 64 kbytes of SRAM and 768 kbytes of flash. Transmit power up to +20 dBm enables a longer transmission range.

Also based on an Arm Cortex-M33 processor, the HCM111Z Bluetooth LE 5.3 module offers a maximum data rate of 2 Mbps. It includes 48 kbytes of SRAM and 512 kbytes of flash memory, as well 13 general-purpose I/Os and a built-in codec for microphone pickup and audio playback.

Quectel Wireless Solutions 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Two 60-GHz V-band transceivers, the ST60A3H0 and ST60A3H1 from ST, offer short-range cable-free connectivity at up to 480 Mbps. Operating in half-duplex mode, these compact devices enable embedded USB2 (eUSB2), I2C, SPI, UART, and GPIO RF tunneling.

The ST60A3H0 and ST60A3H1 can be used in personal electronics like digital cameras, wearables, portable hard drives, and small gaming terminals. They also afford data transfer in industrial applications, such as rotating machinery. As cost-effective cable replacements, the transceivers allow designers to create products with slim, aperture-free cases.

Self-discovery with instant mating eliminates pairing, while low power consumption preserves battery runtime. The parts consume 130 mW in eUSB Rx/Tx mode and 90 mW in UART, GPIO, and I2C modes. Shutdown mode reduces power consumption to just 23 µW.

Housed in VFBGA packages, the ST60A3H0 connects to an external antenna, while the ST60A3H1 has an integrated antenna. Samples of the transceivers are available now and cost $5. Detailed technical data, evaluation kits, and production pricing are subject to a non-disclosure agreement.

ST60A3H0 product page

ST60A3H1 product page

STMicroelectronics  

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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A couple of years ago, I described having witnessed someone undergo an epileptic seizure at the company where I was employed at the time. I tried to keep cool and collected while writing about that incident, but the truth be told, it was jarring. Please read the story here.

I was idly browsing on my “smart” phone the other day when I came across an item about a then upcoming Star Wars movie where clever computer people had recreated the character Princess Leia as she would have been portrayed by the late Carrie Fisher. I was taken aback by an admonishing note on the link, but I grasped its justification as I watched the clip itself (Figure 1).

Figure 1 Film clip of the upcoming Star Wars movie with the warning “Contains flashing images”

Before one gets to watch the clip showing off the video technology that has been brought to bear, there is a warning about “flashing images”. When the film clip runs, the rapid flash-flash-flash for which Star Wars films are noted actually had a somewhat disorienting effect on yours truly and I do NOT have any epileptic history.

The point of all this is that those of us whose work products involve display(s) of any kind need to be cognizant of the possible dangers that a flashing display might present to some users of the product(s).

Some of us will recall that this was one of the plot devices in the movie The Andromeda Strain back in 1969 in which a woman is driven by a flashing image into an epileptic attack.

From more than half a century ago right up to this very moment, this concern is for real and quite frankly, I am glad to see it having been addressed as shown in Figure 1.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Photosensitivity: Seizures from displays appeared first on EDN.

During Day 2 of APEC 2024, Power Electronics News editor-in-chief Maurizio Di Paolo Emilio and EDN editor-in-chief Majeed Ahmad underscored the significance of silicon and silicon carbide technologies alongside passive components, gallium nitride advancements, and the promising outlook of fusion energy. ADI introduced a gate driver tailored for GaN FETs, while Infineon and Qorvo exhibited diverse, SiC-based solutions. SemiQ also made substantial investments in SiC, unveiling 1,200-V MOSFETs.

The post APEC 2024, Day 2: Daily Briefing Video appeared first on EDN.

Welcome to the first day of the 2024 APEC conference, where global leaders converge to discuss pivotal topics shaping our technological landscape. Today, we delve into the field of semiconductor technology, exploring the transformative potential of wide-bandgap semiconductors and the dichotomy between wide-bandgap and not-wide-bandgap semiconductors. In this video, we analyze some points during the plenary session on Day 1.

The post APEC 2024, Day 1: Daily Briefing Video appeared first on EDN.

Two months ago, EDN published my teardown of Lenovo’s Smart Clock 2:

I’d mentioned in it that my dissection victim, acquired at steep discount from the original MSRP, included the “optional charging dock for both it, a wireless-charging (with MagSafe support, to boot) smartphone or other device, and a USB-tethered device (the USB charging port moved from the back of the speaker itself to the dock in this second-generation design)”:

An upfront correction before proceeding; I realize in retrospect upon re-read that my imprecise wording might have left you with the impression that the dock not only charged wireless- and USB-connected devices but also powered the Smart Clock 2 itself. Indeed, there’s an array of contacts on the underside of the Smart Clock 2:

which, as you’ll soon see, mate up to an array of spring-loaded pogo pins on the dock. However, as you may have already ascertained, given that that the Smart Clock 2 comes with a wall wart:

which mates with a barrel plug connector on the back of the device:

the power flow actually goes from the Smart Clock 2 to the charging dock and from there to its USB and wireless charging facilities for other devices’ use. One other note on the latter point, by the way…since the wall wart’s DC output is only 18W (12 V x 1.5 A) and since some of that power needs to be devoted to fueling the Smart Clock 2 itself along with whatever might be connected to the dock over USB, that explains (among other reasons) why Lenovo labels the wireless charging pad as “MagSafe-compatible”, not fully “Made for MagSafe”. Indeed, dive into the products’ tech spec minutia and you’ll find the following regarding the dock’s wireless charger:

• 5 W
• 7.5 W
• 10 W
• Fast-charging

Frankly, I was surprised to see that the peak wireless charging power goes that high; I’m guessing it’s only valid if the USB charging port isn’t in simultaneous use at the time.

In that earlier writeup, I also noted that “I bought mine brand new direct from Lenovo at the end of 2022 for only $29.99, complete with the docking station (which I’ll save for another teardown to come).” That time is now if you haven’t already figured it out ;-).

Our previous allusion to the charging dock, aside from the verbiage and pictures on the outside of the combined packaging:

was intentionally titillating: a brief glimpse of a white box:

underneath the more decorative box for the Smart Clock 2 itself (which was presumably intended to be optionally placed directly on retailer shelves for standalone sale):

Here’s a fuller view of the aforementioned box o’the bottom, as-usual accompanied by a United States penny (0.75 inches/19.05 mm in diameter) for size-comparison purposes:

Riveting presentation, eh? I’ll save you six closeups of various plain white box panels, instead substituting a sole closeup of the product sticker in the previous overview shot:

Yes, the label includes the FCC ID (O57SEA61UW). And yes, if you’re impatient to see what the charging dock looks like inside you could bypass my scintillating prose and jump right to the FCC’s internal photos. But where’s the fun in that? Are you trying to hurt my feelings?

Ahem. Onward:

Here’s our first glimpse of our victim; its bottom side, to be precise:

The charging dock has dimensions of 0.93″ x 8.65″ x 3.26″ (23.66 mm x 219.65 mm x 82.77 mm). I couldn’t find a weight spec anywhere and didn’t think to weigh it myself until after it was already in pieces. Underneath it is nothing but more cardboard along with a literature sliver:

Here’s the dock again, still in its protective translucent sleeve:

First glimpse of the topside:

Finally freed from its plastic captivity:

The two oval inserts fit into matching insets on the underside of the Smart Clock 2, with the one handling power transfer obvious from the aforementioned pins-to-contacts cluster:

Let’s next look around back to get a different perspective on those pins:

Along with, refocusing slightly, that USB charging port:

Finally, flipping the dock back over (the front and sides are bland unless you’re into pictures of off-white plastic):

Let’s take a closer look at those markings and the sticker alongside them:

You probably also saw the two rubberized “feet”. If you’ve perused any of my teardowns before, you know that what’s often underneath them (screw heads, etc.) are prime candidates to get inside, therefore garnering my immediate attention. Habitual behavior rears its head again:

A-ha!

Keen-eyed readers may have already noticed that both feet left plastic film behind:

which thankfully was no match for my trusty Philips screwdriver:

That said, I’m honestly not sure how much purpose the screws served, since after I sufficiently loosened them, I was left with two enclosure halves that still stubbornly clung together. Some additional attention along the sides from my spudger followed by a screwdriver (flat head this time), along with some patience, finally convinced them to separate, however:

In the process of wrestling the bottom panel away, I’d inadvertently also dislodged a previously unknown-to-me top-side insert, which I focused my attention on next:

And after removing four screws holding the metal plate in place (underneath of which, I suspect you’ve probably already guessed, is the wireless charging coil), I was able to lift it away:

See, there’s the coil (other examples of which we’ve seen before in teardowns past)!

Revealing, in the left-behind top half of the chassis, the “MagSafe-compatible” magnets:

Next step: separate the PCB from the insert. The first four screws to be removed were obvious to my eyes, but the PCB still wouldn’t budge…until I looked again more closely and saw #5 (not the first time I’ve overlooked a screw in a disassembly rush, and likely not the last, either):

Free at last!

Speaking of magnets, here’s another (bigger) one:

Revisiting my earlier Smart Clock 2 teardown, I realized I hadn’t mentioned a metal plate on the inside of its underside, focusing instead on the mini-PCB (such an electrical engineer, aren’t I?):

This magnet, perhaps obviously, proximity-clings to the plate, thereby helping keep the Smart Clock 2 connected to the dock below it.

Finally, the closeups of the “guts” that you’ve been waiting for. Note first the black-color ground strap wire connecting the metal plate to the PCB:

Flip it over and you can see the two thick wires connecting the PCB to the coil, along with two much thinner wires that run between the PCB and the temperature sensor at the coil’s center:

Now for the PCB itself. Here’s the side you’ve already seen plenty of, which points downward when the system is assembled:

Near the center, and toward the top, is a chip marked MT581 (along with a vertical line seemingly drawn by hand with a Sharpie?) from Maxic Technology, described as a “highly integrated, high-performance System on Chip (SoC) for magnetic induction based wireless power transmitter solutions”. It’s the function equivalent of various ICs from STMicroelectronics that I’ve encountered in past wireless charger teardowns. Below and to its right is the CH552T, a USB microcontroller manufactured by Nanjing Qinheng Microelectronics. Unsurprisingly, it’s nearby the dock’s USB charging port. And in the upper right quadrant, to the right of the MT581, is a cluster of four small chips with identical markings:

RU3040
PR05078

whose function eludes my Google research (ideas, readers?). Flip the PCB over:

and the dominant feature that’ll likely catch your eye is a rectangular-ish outline near the periphery comprised of 18 small white pieces of what looks like plastic. At first, I thought they might find use in attaching the PCB to the underside of the insert, but more thoughtful analysis quickly dashed that theory. Turning the PCB sideways revealed their true purpose:

They’re LEDs, implementing the charging dock’s “nightlight” function. Duh on me!

That’s all I’ve got for today, folks, although I’ll as-usual hold onto the pieces o’hardware for a while, for potential assistance in answering any questions you might have on stuff I haven’t already covered. More generally, as always sound off with your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post Lenovo’s Smart Clock 2 Charging Dock: Multiple lights and magnetic “locks” appeared first on EDN.

When analog circuits mix with digital, the former are sometimes dissatisfied with the latter’s usual single supply rail. This creates a need for additional, often negative polarity, voltage sources that are commonly provided by capacitive charge pumps.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The simplest type is the diode pump, consisting of just two diodes and two capacitors. But it has the inherent disadvantages of needing a separately sourced square wave to drive it and of producing an output voltage magnitude that’s at least two diode drops less than the supply rail. 

Active charge pump switches (typically CMOS FETs) are required to avoid that.

Many CMOS charge pump chips are available off the shelf. Examples include the multi-sourced ICL7660 and the Maxim MAX1673 pumps that serve well in applications where the current load isn’t too heavy. But they aren’t always particularly cheap (the 1673 for example is > $5 in singles) and besides, sometimes the designer just feels the call to roll their own. Illustrated here is an example of the peculiar outcomes that can happen when that temptation isn’t resisted.

The saga begins with Figure 1, showing a (vastly simplified) sketch of a CMOS logic inverter.

Figure 1 Simplified schema of typical basic CMOS gate I/O circuitry showing clamping diodes and complementary FET switch pair.

Notice first the input and output clamping diodes. These are included mainly to protect the chip from ESD damage, but a diode is a diode and can therefore perform other useful functions, too. Similarly, the P-channel FET pair was intended to connect the V+ rail to the output pin when outputting a logic ONE, and the N-channel for connection to V- to pin for a ZERO. But CMOS FETs will willingly conduct current in either direction when ON. Thus, current running from pin to rail works just as well as from rail to pin. 

Figure 2 shows how these basic CMOS facts relate to charge pumping and voltage inversion.

Figure 2 Simplified topology of logic gates comprising voltage inverter, showing driver device (U1), switch device (U2), and coupling (Cc), pump (Cp), and filter (Cf) capacitors.

 Imagine two inverters interconnected as shown in Figure 2 with a square wave control signal coupled directly to U1’s input and through DC blocking cap Cc to U2’s with U2’s input clamps providing DC restoration.

Consider the ZERO state half cycle of the square wave. Both U1 and U2 P-channel FETs will turn on, connecting the U1 end of Cp to V+ and the U2 end to ground. This will charge Cp with its U1 terminal at V+ and its U2 end at ground. Note the reversed polarity of current flow into U2’s output pin due to Cp driving the pin positive and from there to ground through U2’s P FET and positive rail pin.

Then consider what happens when the control signal reverses to the ONE state.

Now the P FETs will turn OFF while the N FETs turn ON. This forces the charge previously accepted by Cc to be dumped to ground through U1 and its complement drawn from U2’s V- pin, thus completing a charge-pumping cycle that delivers a quantum of negative charge:

Q- = -(CpV+ + Cf V–)

to be deposited on Cf. Note that reversed current flow through U2 occurs again. This cycle will repeat with the next reversal of the control signal, and so on, etc., etc.

During startup, until sufficient voltage accumulates on Cf for normal operation of internal gate circuitry and FET gate drive, U2 clamp diodes serve to rectify the Cp drive signal and charge Cf.

That’s the theory. Translation of Figure 2 into practice as a complete voltage inverter is shown in Figure 3. It’s really not as complicated as it looks.

Figure 3 Complete voltage inverter: 100 kHz pump clock (set by R1C1), Schmidt trigger and driver (U1), and commutator (U2).

 A 100 kHz pump clock is output on pin 2 of 74AC14 Schmidt trigger U1. This signal is routed to the five remaining gates of U1 and the six gates of U2 (via coupling cap C2). Negative charge transfer occurs through C3 into U2 and accumulates on filter cap C5.

Even though the Schmidt hysteresis feature isn’t really needed for U2, the same type is used for both chips to improve efficiency-promoting synchronicity of charge-pump switching.

Some performance specs (V+ = 5V):

• Impedance of V- output: 8.5 Ω
• Maximum continuous load: 50 mA
• Efficiency at 50 mA load: 92%
• Efficiency at 25 mA load: 95%
• Unloaded power consumption: 440 µW
• Startup time < 1 millisecond

But finally, is there a cost advantage to rolling your own? Well, in singles, the 1673 is $5, the 7660 about $2, but two 74AC14s can be had for only a buck. The cost of passive components is similar, but this DI circuit has more solder joints and occupies more board area. So, the bottom line…??

But at least using outputs as inputs and ground as an output was fun.

And an afterthought: For higher voltage operation, simply drop in CD4106B metal-gate chips for the 74AC14s, then with no other changes, V+ and V- can be as high as 20V.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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• The ins and outs of charge-pump-converter ICs

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