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Arm’s edge AI platform features the Cortex-A320 CPU and Ethos-U85 NPU, enabling on-device execution of models exceeding 1 billion parameters. The Armv9 platform enhances efficiency, performance, and security for IoT, while unlocking new edge AI applications through support for both large and small language models.

Built on the Armv9 architecture, the Cortex-A320 delivers 10× higher ML performance and 30% better scalar performance than its predecessor, the Cortex-A35. It also achieves an 8× ML performance gain over the Cortex-M85-based platform launched last year. Additionally, Armv9.2 offers advanced security features like pointer authentication, branch target identification, and memory tagging extension.

The Cortex-A320 pairs with the Ethos-U85 AI accelerator, which supports transformer-based models at the edge and scales from 128 to 2048 MAC units. To streamline edge AI development, Arm’s Kleidi for IoT compute libraries enhance AI an ML performance on Arm-based CPUs with seamless ML framework integration. For example, Kleidi boosts Cortex-A320 performance by up to 70% when running Microsoft’s Tiny Stories dataset on Llama.cpp.

To learn more about the Armv9 edge AI platform, click on the product page links below.

Cortex-A320 product page

Ethos-U85 product page

Kleidi product page

Arm

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Infineon’s PSOC 4 series microcontrollers now integrate capacitive, inductive, and liquid level sensing in a single device. The PSOC 4000T, powered by a 32-bit, 48-MHz Arm Cortex-M0+ processor, combines CAPSENSE capacitive sensing with Multi-Sense inductive sensing and non-invasive, non-contact liquid sensing.

Infineon says Multi-Sense inductive sensing offers greater noise immunity and durability than existing methods. Its differential, ratio-metric architecture supports new HMI and sensing applications, including touch-over-metal, force touch, and proximity sensing.

The PSOC 4000T’s liquid sensing uses an AI/ML-based algorithm that Infineon says is more cost-effective and accurate than mechanical sensors and standard capacitive solutions. It resists environmental factors like temperature and humidity and detects liquid levels with up to 10-bit resolution. It also rejects foam and residue and operates across varying air gaps between the sensor and container.

The fifth-generation CAPSENSE technology enables hover touch sensing, allowing interaction without direct button contact. Its always-on capability reduces power consumption by 10× while delivering 10× higher signal-to-noise ratio than Infineon’s previous devices.

The PSOC 4000T with CAPSENSE and Multi-Sense is available now. A second device, the PSOC 4100T Plus, offering more memory and I/Os, will gain Multi-Sense support in 2Q 2025.

PSOC 4000T product page

Infineon Technologies

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Another week, another suite of press release-only-announced products. With the exception of the yearly (and mid-year) in-person WWDC, will we ever see Apple do another live event?

I digress. Some of what Apple’s rolled out (so far…it’s only Wednesday night as I write these words) this week was accurately prognosticated at the end of my last-week coverage. Some of it was near-spot-on forecasted, albeit with an unexpected (and still baffling, a day later) twist. And two of the system unveilings were a complete surprise, at least from a timing standpoint. At all the new system’s cores were processor updates (core…processor…get it?). And speaking of which, there’s a new one of those, as well. In chronological order, starting with Tuesday’s news…

Apple had migrated the iPad Air tablet from the M1 to the M2 SoC less than a year ago, at the same time expanding the product suite to include both 11” and 13” form factors. So when Tim Cook teased that “There’s something in the Air” on Monday, M3-based iPad Airs were not what I expected. But…whatevah… By the way, careful perusers of the press release might have already noticed that all the performance-improvement claims mentioned there were versus the 2022 M1-based model, not last year’s M2. That selective emphasis wasn’t an accident, folks.

And of course, there’s a new accompanying keyboard; heaven forbid Apple forego any available opportunity for obsolescence-by-design forced updates to its devoted customer base, yes? Sigh.

This one didn’t even justify a press release of its own; instead, Apple tacked a paragraph and photo onto the end of the iPad Air announcement. Predictably, there were performance-improvement claims in that paragraph, and once again Apple jumped two product generations in making them, comparing against the September 2021 9th-generation A13 Bionic-based iPad versus the year-later (but still 2.5 years old) 10th-generation offering running the A14 Bionic SoC. And the doubled-up internal storage is nice. But here’s the surprising-to-me (and pretty much everyone else whose coverage I read) twist; the new 11th-gen iPad is based on the A16 SoC.

“What’s the big deal, Dipert?” you might understandably be asking at this point. The big deal is that the A16 is not Apple Intelligence-compatible. On the one hand, I get it; the iPad is the lowest-priced offering in Apple’s tablet portfolio, so to maintain shareholder-friendly profit margins, the bill-of-materials cost must be similarly suppressed. But given how increasingly fiscal-reliant Apple is on the services segment of its business, I’m still shocked that Apple didn’t instead put the A17 Pro, already found in the latest iPad mini, into the new iPad too, along with enough RAM to enable AI capabilities. Maybe the company just wants to upsell everyone to the iPad Air and Pro instead? If so, I’ve got an intentionally terse response: “good luck with that”.

This is what everyone thought Tim Cook was alluding to with Monday’s “There’s something in the Air” tease, in-advance suggested by dwindling inventory of existing M3-based products. And one day later than the iPad Air, they belatedly got their wish. That said, with the exception of a new sky blue scheme (No more Space Gray? You gotta be kidding me!), all the changes are on the inside. The M4 SoC (this time exclusively with a 10-core CPU, albeit in both 8-and-10-core GPU variants) is more energy-efficient than its M3 forebear; we’ve already discussed this. But Apple was even more comparison-silly this time, benchmarking against the three-generations-old (and more than four years old) M1 MacBook Air, as well as even more geriatric x86-based variants (Really, Apple? Isn’t it time to stop kicking Intel?). About the most notable thing I can say, aside from the price cut, is that akin to its M4 Mac mini sibling, the M4 MacBook Air now supports up to two external displays in addition to the integrated LCD, without any software-based (therefore CPU-burdening) DisplayLink hacks. Oh, and the front camera is improved. Yay.

Speaking of the Mac mini, let’s close by mentioning its bigger (albeit not biggest) brother, the Mac Studio. Until earlier today (again, as I write these words on Wednesday evening) the most powerful Mac Studios, introduced at the 2023 WWDC, were based on M2 SoC variants: the 12 CPU core and 30-or-38 GPU core M2 Max; and dual-die (interposer-connected) 24 CPU core and 60-or-76 GPU core M2 Ultra. They were follow-ups to 2022’s M1 Max (an example of which I own) and M1 Ultra premiere Mac Studio products. So, we were clearly (over)due for next-gen offerings. But, although the M1 versions were introduced in March, M2 successors arrived the following June. So, I’d placed my bets on the (likely June) 2025 WWDC for the next-gen launch timing.

Shows you how much (or accurately, little) I know…Apple instead decided on a 2022-era early-March re-do this time. And skipping past the M3 Max, the new “lower-end” (I chuckle to even type those words, and you’ll see why in second) version of the Mac Studio is based on the 14-or-16 CPU core, 32-or-40 GPU core, and 16 neural processing core M4 Max SoC also found in the latest high-end MacBook Pros.

But, at least for now (and maybe never?) there’s no M4 Ultra processor. Instead, Apple revisited the M3 architecture to come up with the M3 Ultra, its latest high-end SoC for the Mac Studio family. It holds 28-or-32 CPU cores, 60-or-80 GPU cores, and 32 neural processing cores, all prior-gen. I’m guessing the target market will still be satisfied with the available “muscle”, in spite of the generational back-step. And it’s more than just an interposer-connected dual-die M3 Max pairing. It also upgrades Thunderbolt capabilities to v5, previously found only on higher-end M4 SoC variants, and the max RAM to 512 GBytes (the M3 Max only supports 128 GBytes max…see what I did there?).

Maybe we’ll see a next-gen Mac Pro at WWDC, then? And maybe it (or if not, which of its other product line siblings) will be the first system implementation of the next-gen M5 SoC? Stand by. Until then, let me know your thoughts on this week’s announcements in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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• 2024: A technology forecast for the year ahead

The post Apple’s spring 2025 part II: Computers, tablets, and a new chip, too appeared first on EDN.

A new design platform streamlines electronics system development from component selection to software development by integrating hardware, software, and lifecycle data into a single digital environment. Renesas 365 is built around Altium 365, a design suite that provides seamless access to component sources and intelligence while connecting all stakeholders throughout the creation process.

Embedded system developers often struggle due to manual component searches, fragmented documentation, and siloed design teams. Renesas 365 addresses these challenges by connecting Altium’s cloud-connected system design platform with Renesas’ components for embedded compute, connectivity, analog, and power applications.

Renesas 365, built around Altium’s system design platform, streamlines development from component selection to lifecycle management. Source: Renesas

Renesas CEO Hidetoshi Shibata calls it a first-of-its-kind solution. “It’s the next step in the digital transformation of electronics, bridging the gap between silicon and system development.” Renesas has joined hands with the company it acquired last year to redefine how electronics systems are designed, developed, and sustained—from silicon selection to full system realization—in a connected world.

Here is how Renesas 365 works in five steps.

1. Silicon: Renesas 365 will ensure that every silicon component is application-ready, optimized for software-defined products, and seamlessly integrated with the broader system.
2. Discover: This part powered by Altium enables engineers to find components as well as complete solutions from Renesas’ portfolio for faster and more accurate system design.
3. Develop: Altium powers this part to provide a cloud-based development environment to ensure real-time collaboration across hardware, software, and mechanical teams.
4. Lifecycle: Also powered by Altium, this part establishes persistent digital traceability to facilitate over-the-air (OTA) updates and ensure compliance and security from concept to deployment.
5. Software: This part provides developers with artificial intelligence (AI)-ready development tools to ensure that the software is optimized for their applications.

The final part of Renesas 365 offerings demonstrates how a unified software framework covering low- to high-compute performance can help developers create software-defined systems. For instance, these development tools enable real-time, low-power AI inference at the edge. They can also track compliance and automate OTA updates to ensure secure lifecycle management.

This cloud-connected system design platform can aid developers in everything from component selection to embedded software development to OTA updates. Meanwhile, it ensures that existing workflows remain uninterrupted and supports everything from custom AI models to advanced real-time operating system (RTOS) implementations.

Renesas will demonstrate this system design platform live at embedded world 2025, which will be held from 11 to 13 March in Nuremberg, Germany. The company’s booth 5-371 will be dedicated to presentations and interactive demonstrations of the Renesas 365 solution.

Related Content

• PCB design basics
• PCB Design Considerations and Tools
• PCB Design Basics: Example design flow
• Renesas acquires Altium as part of its digitalization strategy
• What does Renesas’ acquisition of PCB toolmaker Altium mean?

The post This is how an electronic system design platform works appeared first on EDN.

It’s remarkable how many switching regulator chips use the same basic two-resistor network for output voltage programming. Figure 1 illustrates this feature in a typical (buck type) regulator. See R1 and R2 where:

Vout = Vsense(R1/R2 + 1) = 0.8v(11.5 + 1) = 10v

Figure 1 A typical regulator output programming network with a basic two-resistor network for output voltage programming.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Quantitatively, the Vsense feedback node voltage varies from type to type and recommended values for R1 can vary too, but the topology doesn’t. Most conform faithfully to Figure 1. This defacto uniformity is useful if your application needs digital control of Vout via PWM. 

Figure 2 shows the simplistic three-component solution it makes possible where:

Vout = Vsense(R1/(R2 + R3/DF) + 1) = 0.8v to 10v as DF = 0 to 1

All that’s required to add PWM control to Figure 1 is to split R2 into two equal halves, connect filter cap Cf to the middle of the pair, and add PWM switch Q1 in series with its ground end.

Figure 2 Simple circuit for regulator programming with PWM where Vout ranges from 0.8 V to 10 V as the duty factor (DF) goes from 0 to 1.

The Cf capacitance required for 1-lsb PWM ripple attenuation is 2(N-2)Tpwm/R2, where N is number of PWM bits and Tpwm is the PWM period. Since Cf will never see more than perhaps a volt, its voltage rating isn’t much of an issue.

A cool feature of this simple topology is that, unlike many other schemes for digital power supply control, only the regulator’s internal voltage reference matters to regulation accuracy. Precision is therefore independent of external voltage sources, e.g. logic rails. This is a good thing because, for example, the tempco of the TPS54332’s reference is only 15 ppm/oC.

Figure 3 graphs Vout versus the PWM DF for the Figure 2 circuit where the X-axis is DF, the Y-axis is Vout and,

Vout = Vsense(R1/(R2 + R3/DF) + 1)
Vout(min) = Vsense
Vout(max) = Vsense(R1/(R2 + R3) + 1)
R1/(R2 + R3) = Vout(max)/Vsense – 1

Figure 3 Graph showing Vout versus the Figure 2 PWM DF.

Figure 4 plots the inverse function with DF vs Vout where,

DF = R3/(R1/(Vout/Vsense – 1) – R2)

The nonlinearity of DF versus Vout does incur the cost of a bit of software complexity (two subtractions and three divisions) to do the conversion. But since it buys substantial circuitry simplification, it seems a reasonable (maybe zero) cost. Or, if the necessary memory is available, a lookup table is another (simple!) possibility.

 Figure 4 DF versus Vout; the non-linearity necessitates a bit of software complexity to perform the conversion.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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The post Three discretes suffice to interface PWM to switching regulators appeared first on EDN.

The need for intelligent interconnect solutions has become critical as the scale, complexity, and customizability of today’s systems-on-chip (SoC) continue to increase. Traditional network-on-chip (NoC) technologies have played a vital role in addressing connectivity and data movement challenges, but the growing intricacy of designs necessitates a more advanced approach. Especially, when high-end SoC designs are surpassing the human ability to create NoCs without smart assistance.

The key drivers for this demand can be summarized as follows:

• Application-specific requirements: Many industries and applications, such as automotive, Internet of Things (IoT), consumer electronics, artificial intelligence (AI), and machine learning (ML), require highly specialized hardware tailored to unique workloads, such as real-time processing, low latency, or energy efficiency. Off-the-shelf chips often fall short of providing the precise blend of performance, power, and cost-efficiency these applications need.
• Cost and performance optimization: Custom SoCs allow companies to integrate multiple functions into a single chip, reducing system complexity, power consumption, and overall costs. With advanced process nodes, custom SoCs can achieve higher levels of performance tailored to the application, offering a competitive edge.
• Miniaturization and integration: Devices in areas like wearables, medical implants, and IoT sensors demand miniaturized solutions. Custom SoCs consolidate functionality onto a single chip, reducing size and weight.
• Data-centric and AI workloads: AI and ML require processing architectures optimized for parallel computation and real-time inferencing. Custom SoCs can incorporate specialized processing units, like neural network accelerators or high-bandwidth memory interfaces, to handle these demanding tasks.

The market now demands a next-level approach, one that leverages AI and ML to optimize performance, reduce development time, and ensure efficient data movement across the entire system. Today’s high-end SoC designs are necessitating smarter, automated solutions to address evolving industry needs.

The solution is the introduction of a new type of smart NoC interconnect IP that can leverage smart heuristics using ML and AI technology to dramatically speed up the creation and increase the quality of efficient, high-performance SoC designs.

Today’s NoC technologies

Each IP in an SoC has one or more interfaces, each with its own width and frequency. A major challenge is the variety of standard interfaces and protocols, such as AXI, AHB, and APB, used across the industry. Adding to this complexity, SoCs often integrate IPs from multiple vendors, each with different interface requirements.

NoC technology helps manage this complexity by assigning a network interface unit (NIU) to each IP interface. For initiator IPs, the NIU packetizes and serializes data for the NoC. For target IPs, it de-packetizes and de-serializes incoming data.

Packets contain source and destination addresses, and NoC switches direct them to their targets. These switches have multiple ports, allowing several packets to move through the network at once. Buffers and pipeline stages further support data flow.

Without automation, designers often add extra switches, buffers, or pipeline stages as a precaution. However, too many switches waste area and power, excessive buffering increases latency and power use, and undersized buffers can cause congestion. Overusing pipeline stages also adds delay and consumes more power and silicon.

Existing NoC interconnect solutions provide tools for manual optimization, such as selecting topology and fine-tuning settings. However, they still struggle to keep pace with the growing complexity of modern SoCs.

Figure 1 SoC design complexity which has surpassed manual human capabilities, calls for smart NoC automation. Source: Arteris

Smart NoC IP

The typical number of IPs in one of today’s high-end SoCs ranges from 50 to 500+, the typical number of transistors in each of these IPs ranges from 1 million to 1+ billion, and the typical number of transistors on an SoC ranges from 1 billion to 100+ billion. Furthermore, modern SoCs may comprise between 5 to 50+ subsystems, all requiring seamless internal and subsystem-to-subsystem communication and data movement.

The result of all this is that today’s high-end SoC designs are surpassing human ability to create their NoCs without smart assistance. The solution is the introduction of a new type of advanced NoC IP, such as FlexGen smart NoC IP from Arteris. The advanced IP can leverage smart heuristics using ML technology to dramatically speed up the creation and increase the quality of efficient, high-performance SoC designs. A high-level overview of the smart NoC IP flow is illustrated in Figure 2.

Figure 2 A high-level overview of the FlexGen shows how smart NoC IP flow works. Source: Arteris

Designers start by using an intuitive interface to capture the high-level specifications for the SoC (Figure 2a). These include the socket specifications, such as the widths and frequencies of each interface. They also cover connectivity requirements, defining which initiator IPs need to communicate with which target IPs and any available floorplan information.

The designers can also specify objectives at any point in the form of traffic classes and assign performance goals like bandwidths and latencies to different data pathways (Figure 2b).

FlexGen’s ML heuristics determine optimal NoC topologies, employing different topologies for different areas of the SoC. The IP automatically generates the smart NoC architecture, including switches, buffers, and pipeline stages. The tool minimizes wire lengths and reduces latencies while adhering to user-defined constraints and performance goals (Figure 2c). Eventually, the system IP can be used to export everything for use with physical synthesis (Figure 2d).

NoC with smart assistant

The rapid increase in SoC complexity has exceeded the capabilities of traditional NoC design methodologies, making it difficult for engineers to design these networks without smart assistance. This has driven the demand for more advanced solutions.

Take the case of FlexGen, a smart NoC IP from Arteris, which addresses these challenges by leveraging intelligent ML heuristics to automate and optimize the NoC generation process. The advanced IP delivers expert-level results 10x faster than traditional NoC flows. It reduces wire lengths by up to 30%, minimizes latencies typically by 10% or more, and improves PPA metrics.

Streamlining NoC development accelerates time to market and enhances engineering productivity.

Andy Nightingale, VP of product management and marketing at Arteris, has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm.

Related Content

• SoC Interconnect: Don’t DIY!
• What is the future for Network-on-Chip?
• SoC design: When is a network-on-chip (NoC) not enough
• Network-on-chip (NoC) interconnect topologies explained
• Why verification matters in network-on-chip (NoC) design

The post How AI is changing the game for high-performance SoC designs appeared first on EDN.

Editor’s Note: This DI is a two-part series.

Part 1 shows how to make an oscillator with a pitch that is proportional to a control-voltage.

Part 2 will show how to modify the circuit for use with higher supply voltages, implement it using discrete parts, and modify it to closely approximate a sine wave.

An ongoing project (or gadget) called for a means of generating an audio output to represent a varying voltage level. Ho hum: that sounds like a voltage-controlled oscillator. But this signal was bipolar, spanning peaks ranging from -1 to +1 V. A linear-in-frequency response just sounded wrong, and anyway could never deliver the symmetrical ±1-octave output that I wanted.

Wow the engineering world with your unique design: Design Ideas Submission Guide

A typical, well-known type of oscillator—though as drawn, lacks voltage control—is shown in Figure 1. At the start of a cycle, C1 is fully charged. It then discharges through R1 until the reference voltage, shown as mid-rail, is reached, when the monostable multivibrator is triggered, delivering a pulse to turn on Q1, which shorts C1 to the positive rail, thereby starting the next cycle. The output, an exponentially-decaying sawtooth having constant amplitude, is taken from the top of C1 via a buffer (not shown). (Strictly, the op-amp should be a comparator; it’s used as one.) C1 would normally be switched for different ranges, with R1 varied for tuning.

Figure 1 A typical relaxation oscillator with an exponentially decaying sawtooth output, is the starting point for this design.

Another method of tuning this is to keep R1 and C1 constant and vary the reference voltage. The output level now varies, the tuning law being exponential. If we want pitch-linearity, maybe that would be a good starting point?

An exponential decay may not give the exact curve we need, but with a little tweaking, parts of it are close enough to be useful. Some experimenting produced the workable circuit shown in Figure 2.

Figure 2 Varying the reference voltage instead of the R-C time-constant gives a tuning law that is close enough to being linear in pitch over a couple of octaves, especially after adding R2.

Just as described above, the bipolar control voltage is compared with the falling exponential(-ish) ramp to tune the oscillator’s frequency. When they coincide, U2a, used as a multi-supply multi-voltage (MSMV), is triggered to produce a reset pulse to turn Q1 on momentarily, thus resetting C1’s voltage to its maximum value. Figure 3 shows the key waveforms.

Figure 3 Waveforms from the circuit in Figure 2, at both extremes of its two-octave span.

The single, simple, humble resistor R2 is the key to this design. By compressing and shifting the exponential decay curve, it allows a reasonably close approximation to a tuning law that is linear with pitch rather than frequency over a couple of octaves and more: an increment in the control voltage now changes the frequency by a fairly constant frequency ratio rather than a fixed amount. The match is worst at the low-frequency end, being around 5% off close to the low calibration point and way off even lower down. (A semitone is ~7%.) Using 51k for R2 gives the closest match for the bottom octave frequency itself, but 56k generally “sounds” better on average in that region.

With the values shown, the output frequency ranges from about 250 Hz to 1000 Hz for inputs from -1 to +1 V, which is close to the two octaves upwards from “C4” (middle C: ~262 Hz if we define A4 to be precisely 440 Hz) to “C6”. (The quotes are used here to distinguish pitch values from capacitors!) For different spans, just change C1 or both R1 and R2, whose ratio must be kept constant. If the control voltage falls below about -1.5 V, as determined by R1 and R2, oscillation will stop. Above +1 V, the match is still reasonable for another half octave and more.

U2b divides the oscillator’s pulse output by 2 to give a square wave, which the output network turns into a trapezoid of about 1.1 V pk-pk (~-6 dBu). While this has no pretensions to waveform purity, it does now have softer and “more analog” edges rather than sharp digital ones.

Other comments: MCP6002s are cheap and cheerful. The MCP6022 is better specified (much faster, and with <500 µV input offset) but more costly. The spare half of U1 could be used for further filtering of the output if desired. The spec for Q1 is not critical. A ZVP3306A has an RDS(ON) of up to 15 Ω, but the width of the pulse driving its gate ensures that C1 is fully charged under all conditions. The ~±1 V control range was just what I wanted, but that was a happy accident rather than being designed in.

It now does what’s needed and is ready for dropping into the project (or gadget). However, . . .

Contemplating the basic circuit threw up an interesting idea. Linear-in-frequency tuning can be done in two ways, one being to use a linear ramp and vary the control voltage much as we’re doing with the exponential one, while the other would be to replace R1 with a controllable current sink and delete R2. Use these together and the tuning law becomes “squared”, giving a power law that is inherently much closer to being linear-in-pitch. Figure 4 shows how to do that.

Figure 4 Adding a voltage-controlled current sink in place of tuning resistor R1 is the key to operation over more than 4 octaves with much better pitch accuracy.

Q2, U1b, and R1 form the current sink. Its control voltage is half of that at the input, ensuring that Q2 never saturates. C1 discharges linearly, the slope being governed by Vcon. The power rails are shown as 0 V / +5 V rather than ±2.5 V to reflect the wider tuning range, but the output frequency is still centered at around 520 Hz (close to a pitch of “C5”) with the component values shown.

The required control-voltage swing now measures ~840 mV/octave (or ~70 mV/semitone). The response is almost exactly linear-in-pitch over the middle two octaves, and still decent for the two octaves and more surrounding those. The errors are worst at the low-frequency end because the current sink is then running out of steam (or electrons). An MCP6022 is used because of its better performance but the rest of the circuit is almost unchanged.

While the range of 4-plus octaves is over the top for my target application, improved accuracy is always welcome, and this better performance opens the way to possible musical use.

In Part 2, that will be shown, but first we’ll see how to modify the circuit for use with higher supply voltages, how to implement it using only discrete parts apart from the op-amp, and how to end up with a respectable sine wave at the output.

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

Related Content

• VCO using the TL431 reference
• Ultra-low distortion oscillator, part 1: how not to do it.
• How to control your impulses—part 1
• Squashed triangles: sines, but with teeth?
• Simple 5-component oscillator works below 0.8V
• A two transistor sine wave oscillator

The post A pitch-linear VCO, part 1: Getting it going appeared first on EDN.

A new microcontroller featuring multi-sense capabilities claims to enable new human-machine interface (HMI) and sensing solutions, ranging from sleek metallic product designs with touch-on metal buttons to waterproof touch buttons. Infineon’s PSOC 4 is an Arm Cortex-M0+-based MCU that offers capacitive, inductive, and liquid sensing in a single device.

Figure 1 PSOC 4 integrates capacitive, inductive, and liquid sensing to accommodate a variety of HMI uses cases. Source: Infineon

This new MCU combines the company’s fifth-generation capacitive sensing technology, CAPSENSE, with inductive and liquid sensing to optimize performance, enable new use cases, and realize cost savings. For a start, the fifth-generation CAPSENSE featuring always-on capability enables sensing at 10x lower power consumption and offers a 10x higher signal-to-noise ratio (SNR) than previous devices.

Figure 2 Capacitive sensing (left) and inductive sensing (right) complement each other to enable new HMI and sensing use cases. Source: Infineon

Inductive sensing is based on a proprietary methodology that is less sensitive to noise; it complements capacitive sensing to enable new HMI use cases like touch-over-metal, force touch surfaces, and proximity sensing. This allows developers to create modern, metal-based and waterproof designs with sleek form factors such as metal touch buttons on refrigerators or robust HMI for underwater devices such as cameras and wearables.

Then there is non-invasive and non-contact liquid sensing, which employs an AI/ML algorithm to facilitate more cost-effective and accurate sensing than mechanical sensors and typical capacitive solutions. Liquid sensing is resistant to environmental factors like temperature and humidity and can detect liquid levels with up to 10-bit resolution in various container shapes.

As a result, it offers capabilities—such as foam and residue rejection and reliably working with varying air gaps between sensor and container—that other liquid sensors don’t support. So, liquid sensing on PSOC 4 can efficiently manage liquids in robot vacuum cleaners, washing machines, coffee machines, and humidifiers.

Figure 3 PSOC 4 multi-sense eliminates the need for a sensor in a liquid and is insensitive to process variations like gaps between sensor and container. Source: Infineon

Finally, CAPSENSE hover touch sensors enable applications that benefit CAPSENSE from having an air gap between the sensor and the touch surface. It leverages highly sensitive capacitive sensing capability to detect touch interactions from a significant distance. That eliminates the need for the gap to be bridged using a conductive material, typically a spring or conductive foam.

Figure 4 Hover touch sensing comes into play when a direct touch of a button is not required. Source: Infineon

PSOC 4000T with fifth-generation CAPSENSE and multi-sense capability is available now. Another MCU in PSOC 4 family, PSOC 4100T Plus, offering higher memory and more I/Os, will be available in the second quarter of 2025.

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The post Multi-sense MCU enables new HMI and sensing use cases appeared first on EDN.

I didn’t originally plan to begin this teardown with a language lesson, but it turned out that way. Skip ahead a couple of paragraphs if you insist on bypassing it

As regular readers may already realize, likely to their dismay, I’ve spent the bulk of my nearly-30-year to-date tech journalism career attempting, among other things, to inject rhymes into writeup titles (and content, for that matter) whenever possible and management-blessed (or at least tolerated). Occasionally, I succeeded modestly. Often, I failed miserably. The challenge was particularly acute this time. See for yourself: visit RhymeZone for a listing of how many (or more accurate, few) options exist for rhyming pairings with the word “ultra”. I could have cheated and stuck “streamer” after “ultra” to expand the rhyming options list, but where’s the fun in that?

The Chromecast Ultra streaming receiver we’ll be dissecting today is (or more accurately was) among other things the “kit” partner with Google’s Stadia controller (also on my teardown pile), the usage nexus of the company’s now-defunct online-streamed gaming service. So, what popped into my head next was the word “consort”, specifically the noun defined as (among other things) an “associate”. But I needed something ending in an “a” to even sorta-rhyme. Fortunately, at least for me (your opinions may differ, understandably) the similar-meaning “consorta” also exists, at least in the Swiss Romansh language.

Thus concludes the etymology. Thanks for indulging me (see, another rhyme)! Now for the “meat” of the writeup. As I recently mentioned in my third-generation Google Chromecast teardown, I ended up reordering the publication cadence from the originally planned chronological sequence; the 2018 Chromecast 3 came first, after the 2015 Chromecast 2, followed by today’s 2016 Chromecast Ultra. That said, the calendar-year proximity between the Chromecast 2 and Chromecast Ultra may explain why the latter retained the former’s magnet-augmented HDMI connector and metal-augmented back-of-body, dropped from the Chromecast 3 successor.

As with the Chromecast 3, I wasn’t able to find a “nonfunctional, for parts only” device to tear down; instead, I resigned myself to picking a functional (albeit well-used) alternative off eBay:

for only $19.46 ($12 plus sales tax and $6.35 for shipping), shown here as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

The backside printing is a bit less faint this time compared to that in the Chromecast 3, but it’s still dim. Here’s what it says around the circumference, if your eyes are as old and tired as mine:

Model NC2-6A5-D
FCC ID A4RNC2-6A5-D
IC 10395A-NC26A5D
CAN ICES-3 B
NMB-3 B
Made in China
HDMI
Designed by Google
1600 Amphitheater Parkway
Mountain View, CA 94043
UL US LISTED
ITE E258392
6B11CYFWMB

The earlier “magnetic” image’s hinted-at tint may have tipped you off that the HDMI connector has an atypical orange-ish color (for a possible reason I’ll explain shortly) with this device:

The power supply’s micro-USB connector’s equally uncommon color scheme is similar:

Zooming out, here’s what the latter connector is attached to:

And zooming back in:

Flip the wall wart 180° to check out its specs:

And now rotate it 90° and…wait, what’s this (it’s “only” 100 Mpbs-supportive, BTW)?

The Chromecast Ultra differs from its conventional Chromecast siblings in that it, to quote the spec sheet, “supports all resolutions up to 4K Ultra HD and high dynamic range (HDR) for superior picture quality” (at up to 60 fps, too, content source- and display support-dependent). Here’s the twist: it apparently only delivers a 4K output if the original power supply is in use (thereby explaining, I suspect, albeit in an undocumented manner as far as I can tell, the usage-reminder color match between the micro-USB input power connector and the HDMI A/V output connector). Note that the Ethernet port doesn’t actually need to be in use, as this photo I just snapped of another Chromecast Ultra I own, connected to my master guest bedroom UHD TV (whose date and time settings beg for configuration) and to my LAN over Wi-Fi, reveals:

What I’m guessing is that, in actuality, the Chromecast Ultra is looking for a USB cable that supports both power and data transfer capabilities. Would a different supplier’s PSU with a functionally compatible integrated Ethernet port (as well as an adequate USB PD output, of course), thereby also satisfying the power-plus-data cable requirements, also work? Dunno.

Onward: let’s get inside. Specifically, there’s a seam along the edge, visible in this photo of the device’s micro-USB input:

and, rotating roughly 180°, this shot of its hardware reset button and (to the left) status LED:

I decided to try popping apart the two device halves absent preparatory heat application this time, which still proved successful:

That’s some seriously dry thermal paste in-between the top-half case insides and Faraday Cage:

which may at least in part explain the Chromecast Ultra’s reported propensity for overheating (especially, I’m suggesting, as the device ages and the paste dries out). This guy’s alternative “fix” involved sticking supplemental heatsinks to the outside top case (the video is worth a viewing if only to check out the measured temperature drop post-augmentation):

Next, let’s get that Faraday Cage off:

(No) surprise: more thermal paste!

Let’s apply some isopropyl alcohol to clean off that gray goo, so we can see what’s underneath:

Hold that “what’s underneath” thought until we get the PCB out of the remaining lower-case half. Two screws removed (I’ve already confirmed there are no more at the bottom of the PCB; read my Chromecast 3 teardown for the embarrassing-to-me details of why this was necessary):

followed by the bracket that holds the HDMI connector in place:

At this point, the PCB began to elevate itself out of the remaining case half, so I redirected my attention away from the HDMI cable:

and to the first-time revealed PCB bottom half:

Look, it’s another Faraday Cage!

And here’s (in the center) the metal plate that the HDMI connector magnetically mates with when not in use, along with (at upper right) the reset switch and LED light guide assemblies:

At this point, the HDMI cable disconnected itself (gravity-encouraged) from the other (upper) side of the PCB:

Next to go, Brian-encouraged this time, was the Faraday Cage:

And after one more thermal paste wipe-off session:

let’s get to identification. At the upper-left edge are the reset switch and status LED. Along both lower edges are the PCB-embedded antennae. The large rectangular IC at the right is a Samsung K4F8E304HB-MGCH 8 Gbit LPDDR4-3200 SDRAM (there’s nothing underneath the cage frame above it, trust me; I subsequently ripped it off to check. Also, there’s nothing below the frame at bottom). And in the lower left is another, smaller rectangular IC, labeled as follows:

MARVELL
W8997-A0
637BETP

which I think is now the NXP Semiconductors 88W8997 (NXP having acquired Marvell’s Wi-Fi and Bluetooth connectivity assets in late 2019) and implements the Chromecast Ultra’s dual-band 802.11ac Wi-Fi facilities.

Back to the now-case-free PCB topside, and more Marvell-branded chips come into view:

The one in the center is a real head-scratcher, labeled as follows:

MARVEL
DE3009-A0
633ARTE TJ

Do a Google search on “Marvell DE3009” (I’m assuming “A0” refers to the design stepping version) and you’ll find, unless you’re more adept than me…nothing, save for a Google suggestion that perhaps I meant “DE3005” instead. The DE3006, specifically the 88DE3006, was used in the Chromecast 2 and (in Synaptics-renamed form) the Chromecast 3, so on a hunch I did a search on “Marvell 88DE3009” instead. This was more fruitful, but only a bit; there was a short discussion on iFixit’s website concurring with my suspicion that it was a Google-only implemented device, along with a terse mention on WikiDevi indicating that post-Synaptics’ acquisition of Marvell’s Multimedia Solutions Business in mid-2017, the 88DE3009 was renamed the Synaptics BG4CDP (not that I can find much about it, either, save that it’s supposedly dual-core and runs at 1.25 GHz). More knowledgeable reader insights are as-always welcomed!

The markings on the small IC to the left of the DE3009 and peeking out from the frame edge are too faint for me to discern, other than that the first line is again “MRVL”. Below the DE3009 is a Toshiba TC58NVG1S3HBAI6 2 Gbit NAND flash memory. In the upper right corner of the PCB, again peeking out from under the frame, is a small IC with a Marvell logo mark in the upper left corner, along with the following:

52K
00B0G
624AK

And below it is another Marvell-sourced mystery IC:

MRVL
823AA0
634GAC

As I mentioned earlier specifically regarding the DE3009, reader insights on any of the chips I’ve been unable to identify (along with those I’ve sorta-kinda-maybe ID’d), along with any other thoughts on this teardown, are appreciated in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

 Related Content

• The Google Chromecast Gen 3: Gluey and screwy
• The Google Chromecast Gen 2 (2015): A Form Factor Redesign with Beefier Wi-Fi, Too
• Google’s Chromecast with Google TV: Car accessory similarity, and a post-teardown resurrection opportunity?
• The Google Chromecast with Google TV: Realizing a resurrection opportunity
• Google’s Chromecast with Google TV: Dissecting the HD edition

The post Google’s Chromecast Ultra: More than just a Stadia Consorta appeared first on EDN.

Malaysia is serious about its bid to move up the semiconductor industry ladder by establishing an IC design presence, and Arm’s setting up a design shop there is a testament to this ambition. Malaysia’s Prime Minister Anwar Ibrahim told reporters late last week that he has been on a call with Arm CEO Rene Haas and SoftBank’s head Masayoshi Son regarding this matter.

He added that talks are in the final stage and the agreement will be finalized and signed this month. Ibrahim also said that this demonstrates confidence in Malaysia’s policies and its ambition to become a regional hub for semiconductor design and manufacturing.

Malaysia is keen to penetrate the IC design market to bolster its standing as a regional tech hub. Source: CNA

This initiative is part of Malaysia’s National Semiconductor Strategy (NSS), which calls for $110 billion of direct investment in IC design, advanced packaging, and front-end semiconductor manufacturing processes, which includes wafer fabs and manufacturing equipment.

Details on what kind of design work Arm will carry out in Malaysia are yet to emerge. Ibrahim calls it a major test for the country’s ambition to embrace IC design work. “Can we provide tens of thousands of young professionals?”

“This is a challenge for the youth,” he added. “A professional workforce is essential when we attract significant investments.” That also shows a lot of sense of excitement.

Related Content

• Fabless venture formed in Malaysia
• Has Malaysia’s ‘semiconductor moment’ finally arrived
• Malaysia’s semiconductor journey spanning half a century
• Malaysia’s fabless chip company orders design tools, workstations
• Bosch to Invest Another €400M in German, Malaysian Chip Facilities

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There’s a small AC-line device that has received a lot of favorable media coverage lately. It’s called Ting from Whisker Labs, Inc. and its purpose is to monitor the home AC line, Figure 1. It then alerts the homeowner via smartphone to surges, brownouts, and arcing (arc faults) which could lead to house fires. It’s even getting glowing click-bait testimonials such as “This Device Saved My House From an Electrical Fire. And You Might Be Able to Get It for Free.” Let’s face it, accolades don’t get much better than that.

Figure 1 The Ting voltage monitor is a small, plug-in box with no user buttons except a reset. Source: Wisker Labs

(“Arcing”—which can ignite nearby flammable substances—occurs when electrical energy jumps across a gap between conductors; it usually but not always occurs at a connector and is often accompanied by sparks, buzzing sounds, and overheating; if it’s in a wall or basement, you might not know about it.)

The $99 device plugs into any convenient outlet—more formally, a receptacle—and once set up with your smartphone, it continuously monitors the AC line for conditions which may be detrimental. It needs no additional sensors or special wiring and looks like any other plug-in device. The vendor claims over a million homes have been protected, aggregating over 980,000 “home years” of coverage and that four of five electrical fires have been prevented.

When the Ting unit identifies a problem it recognizes, the owner receives an alert through the Ting app that provides advice on what to do, Figure 2. Depending on the issue, a live member of the company’s Fire Safety Team may contact you to walk you through whatever remediation steps might be required. In addition, if Ting finds a problem, the company will coordinate service by a licensed electrician and cover costs to remedy the problem up to $1,000.

Figure 2 All interaction between the homeowner and the Ting unit for alerts and reporting is via a Wi-Fi to a smartphone. Source: Wirecutter/New York Times

It all seems so straightforward and beneficial. However, whenever you are dealing with the AC line, there’s lots of room for oversimplification, misunderstanding, and confusion. Just look at the National Electrical Code (NEC) in the US (other countries have similar codes) and you’ll see that there’s more to safety in wiring than just using the appropriate gauge wire, making solid connection, and insulating obvious points. The code is complicated and there are good reasons for its many requirements and mandates.

My first thought on seeing this was “this is a great idea.” Then my natural skepticism kicked in and I wondered: does it really do what they claim? Exactly what does it do, and is that actually meaningful? And then the extra credit question: what else does it do that might not be so good or desirable?

For example, some home-insurance companies are offering it for free, and waive the monthly fee for the first year. That’s a tradeoff users might consider, or is it a clever subscription-service hook?

There is lots of laudatory and flowery language associated with the marketing of this device, but solid technical details are scant, see “How Ting Works.” They state, “Ting pinpoints and identifies the unique signals generated by tiny electrical arcs, the precursors to imminent fire risks. These signals are incredibly small but are clearly visible thanks to Ting’s advanced detection technology.”

Other online postings say that Ting samples the at 30 megasamples/second, looking for anomalies. When it identifies a problem it recognizes, the owner receives an alert through the Ting app that provides advice on what to do.

Let’s face it: the real-world AC line looks nothing like the smoothly undulating textbook sine wave with a steady RMS value. Instead, these are some voltage level variations which the vendor says Ting captured, Figure 3.

Figure 3 The real-world AC line has voltage variation, spikes, surges, and dropouts. Source: F150 Lightning Forum

As for arcing, that’s more complicated than just a low or high-voltage assessment, as it produces RF emissions which can be captured and analyzed.

I was about to sign up to try one out myself but realized the pointlessness of that. First, a sample of one doesn’t prove much. Also, how could I “inject” known faults into the system (my house wiring) to evaluate it? That would be difficult, risky, foolish, and almost meaningless.

Instead, I looked around the web to see what others said, knowing that you can’t believe everything you read there. One electrician noted that it is only monitoring one side of the two split phases feeding the house, so there’s a significant coverage gap. Another one responded by saying that it was true, but most issues come across on the neutral wire that is shared by both phases.

Even Ting addressed this “one side” concern with a semi-technical response: “The signals that Ting is looking for can be detected throughout the home’s electrical system even though it is installed on a single 120V phase. Fundamentally, Ting is designed to detect the tiny electro-magnetic emissions associated with micro-arcing characteristics of potential electrical faults and does so at very high frequencies. At high frequencies, your home wiring acts like a communications network.”

They continued: “Since each phase shares a common neutral back at your main breaker panel, arcing signals from one phase can be detected by Ting even if it is on the opposite phase. Thus, each outlet in the home will see the signal no matter its location of origin to some degree. With its sensitive detector and powerful post-processing algorithms, Ting can separate the signal from the noise and detect if there is unusual electrical activity. So, you only need one Ting for your home.”

This response brought yet another online response: “monitoring the voltage of both sides of the split phase would be far more ideal. One of the more common types of electrical fires is a damaged or open neutral coming from the transformer. This could send one side of your split phase low and the other high frying equipment and starting fires. But if you’re only monitoring one side of the split phase, you will only see a high or low voltage and have no way of knowing if that is from a neutral issue or voltage sagging on the street.”

As for arcing, every house built since 1999 in the US has been required by code to use AFCI (arc fault circuit interrupter) outlets; those can stop an electrical fire in nearly all cases, not just report it. However, using a single Ting is less costly and presumably has some value for an older home that isn’t going to be renovated or updated to code.

Data on house fires is collected and analyzed by various organizations including the National Fire Protection Association (NFPA), individual insurance companies and industry-insurance consortiums. Are house first due to electrical faults a problem? The answer is that it depends on how you look at it.

Depending on who you ask and what you count, there are about 1.5 million fires each year—but many are outdoor barbeque or backyard wood-pile fires. The blog “Predict & Prevent: From Data to Practical Insight” from the Insurance Information Institute deals with electrical house fires and Ting in a generally favorable way (of course, you have to consider the blog’s source) with some interesting numbers: The 10 years from 2012 through 2021 saw reduced cooking, smoking, and heating fires; however, electrical fires saw an 11 percent increase over that same period, Figure 4. Fire ignitions with an undetermined cause also increased by 11 percent.  

Figure 4 The causes of house fires have changed in recent years; electrical fires have increased while others have decreased. Source: U.S. Fire Administration via the Insurance Information Institute

Specific hazards are also detailed, Figure 5:

Figure 5 For those fires whose source has been identified, connected devices and appliances are the source of about half while infrastructure wiring is at about one quarter. Source: Whisker Labs via Insurance Information Institute

The blog also points out that there are many misconceptions regarding electrical fires. It’s easy to assume that most fires are due to older home-wiring infrastructure. However, their data found that 50 percent of home electrical-fire hazards are due to failing or defective devices and appliances, with the other half attributed to home wiring and outlets.

Further, it seems obvious that older homes have higher risk. This may be true only if all other things are equal when considering the effects of age and use on existing wiring infrastructure, but they rarely are. The data shows that assumption is suspect when considering all other factors such as materials, build quality, and the standards and codes at that time.

If you get this unit through an insurance company (free or semi-free), that means there’s yet another player the story in addition to the homeowner and Whisker Labs. First, one poster claimed “Digging through the web pages I found each device sends 160 megabytes back to Ting every month…So that means you have to have a stable WiFi router to do the upload. As far as I know, the homeowner does not get a copy of the report uploaded to Ting, but the insurance company does.”

Further, there’s a clause in the agreement between the insurance company that supplied the unit and the homeowner. It says they “may also use the data for purposes of insurance underwriting, pricing, claims handling, and other insurance uses.” Will this information be used to increase your rates or worse cancel your home insurance for imperfect wiring?

It’s not easy to say that the Ting project is a good or bad idea, as that assessment depends on many technical factors and personal preferences. One thing is clear: it may be very useful for collecting and analyzing “big data” across the wiring of millions of homes, AC-line performance, and the relationships between house specifics and electrical risks (hello, AI). However, it can be very tricky when it starts looking at microdata related to a single residence, as it can tell others more about your lifestyle than you would like others to know or how affects how the insurance company rates your house.

What’s your sense of this device and its technical validity?  What about larger-scale technical data-collection value? Finally, how do you feel about personal security and privacy implications?

Bill Schweber is an EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features.

Related content

• Ground-fault interruption protection—without a ground?
• AC-DC adapters get their GaN shrink
• Cable Self-Heating: The Other Side of IR Drop
• ‘Mistakes Were Made’,” Even in a Simple 3-Wire AC Hookup

References

• The Wall Street Journal, “This (Possibly) Free Smart Device Listens to Your Home’s Wiring — and Could Prevent a Fire”
• Electrician Talk, “Ting Power Quality device”
• F150 Lightning Forum. “Ting Electrical Fire Safety Device”
• Insurance Information Institute, “Predict & Prevent: From Data to Practical Insight”
• Wirecutter, “This Device Saved My House From an Electrical Fire. And You Might Be Able to Get It for Free.”
• Reddit, “Does Ting actually work and if so, how?”
• Reddit, “Do you recommend Ting electrical monitors?”
• Wikipedia, “Arc-fault circuit interrupter”
• Rainbow Restoration Blog, “28 House Fire Statistics: How Common Are House Fires?”
• Whisker Labs, “2023 Data Analysis Update: Internet of Things (IoT) System Preventing 4 of 5 Home Electrical Fires”

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For artificial intelligence (AI) at the edge moving from basic tasks like noise reduction and anomaly detection to more sophisticated use cases such as big models and AI agents, Arm has launched a new CPU core, the Cortex A-320, as part of the Arm v9 architecture. Combined with Arm’s Ethos-U85 NPU, Cortex A-320 enables generative and agentic AI use cases in Internet of Things (IoT) devices. EE Times’ Sally Ward-Foxton provides details of this AI-centric CPU upgrade while also highlighting key features like better memory access, Kleidi AI, and software compatibility.

Read the full story at EDN’s sister publication, EE Times.

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With high measurement speed and stability, the R&S ZNB3000 vector network analyzer (VNA) supports large-scale RF component production. Its PCB-based frontend minimizes thermal drift, enabling reliable measurements for days without recalibration. The analyzer is also useful in RF labs.

The ZNB3000 is available with two or four ports and covers frequency ranges of 9 kHz to 4.5 GHz, 9 GHz, 20 GHz, and 26.5 GHz. R&S states that it offers the highest dynamic range and output power in its class, achieving up to 150 dB RMS with trace noise below 0.0015 dB RMS and providing +11 dBm output power at 26.5 GHz. Further, the VNA completes a 1-MHz to 26.5-GHz frequency sweep with 1601 points, 500-kHz IF bandwidth, and two-port error correction in 21.2 ms.

Understanding measurement uncertainty under test conditions is essential. Previously, calculating uncertainty for DUT S-parameters was only possible in a metrology lab. With the R&S ZNB3-K50(P) option, developed with METAS, the R&S ZNB3000 now calculates and displays uncertainty bands alongside measured S-parameters.

The ZNB3000 VNA is available now. To request pricing information, use the link to the product page below.

ZNB3000 product page 

Rohde & Schwarz 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Silicon Labs’ MG26 family of wireless SoCs enables mesh IoT connectivity through Matter, OpenThread, and Zigbee protocols. By supporting concurrent multiprotocol capabilities, the MG26 chips simplify the integration of smart home and building devices—such as LED lighting, switches, sensors, and locks—into both Matter and Zigbee networks simultaneously.

The MG26 SoCs offer up to 3 MB of flash and 512 KB of RAM, doubling the memory of other Silicon Labs multiprotocol devices. Powered by an Arm Cortex-M33 CPU with dedicated cores for radio and security subsystems, these devices offload tasks from the main core, optimizing performance for customer applications. Embedded AI/ML hardware acceleration enables up to 8x faster processing of machine learning algorithms, consuming just 1/6th the power compared to running them on the CPU.

Silicon Labs’ Secure Vault and Arm TrustZone meet all Matter security requirements. Secure OTA firmware updates and secure boot protect against malicious software installation and enable vulnerability patching. Through Silicon Labs’ Custom Part Manufacturing Service, MG26 devices can be programmed with customer-specific Matter device attestation certificates, security keys, and other features during fabrication.

The MG26 family of wireless SoCs is now generally available through Silicon Labs and its distribution partners.

MG26 series product page

Silicon Labs 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Microchip’s SAMA7D65 MPUs, based on an Arm Cortex-A7 core running up to 1 GHz, integrate a 2D GPU, LVDS, and MIPI DSI. These features enhance data transmission and processing for improved graphics performance, optimizing HMI applications in industrial, medical, and transportation markets.

The SAMA7D65 microprocessors feature dual Gigabit Ethernet MACs with Time Sensitive Networking (TSN) support, ensuring precise synchronization and low-latency communication for industrial and building automation HMI systems. This enables seamless data exchange and deterministic networking, essential for responsive user interfaces.

Microchip also offers a system-in-package (SiP) variant of the SAMA7D65 MPU, the SAMA7D65D2G, which integrates a 2-Gb DDR3L DRAM for high-speed synchronization. Its low-voltage design reduces power consumption and optimizes energy efficiency. SiPs streamline development by addressing high-speed memory interface challenges and simplifying memory supply, accelerating time to market. Additionally, a system-on-module (SOM) variant is available for early access.

SAMA7D65 MPUs are available now in production quantities.

SAMA7D65 product page

Microchip Technology

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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TeseoVI GNSS receivers from Microchip integrate multi-constellation and quad-band signal processing on a single die. This series of ICs and modules provides centimeter-level accuracy for high-volume automotive and industrial applications, such as ADAS, autonomous driving, asset trackers, and mobile robots for home deliveries.

Three standalone chips—the STA8600A, STA8610A, and STA9200MA—include dual independent Arm Cortex-M7 processing cores for local control of IC functions, along with ST’s phase-change memory to remove external memory needs. The STA9200MA runs dual cores in lockstep, providing hardware redundancy that meets ISO26262 ASIL-B functional safety requirements.

The TeseoVI family also includes two GNSS automotive modules, the VIC6A (16×12 mm) and ELE6A (17×22 mm), which integrate the chipset along with key external components—TCXO, RTC, SAW filter, and RF frontend—into a larger package with fewer pins and an EMI shield. These modules simplify development by eliminating the need for RF path design.

Samples of the TeseoVI GNSS receivers are available on request. Read the blogpost here.

TeseoVI product page 

STMicroelectronics

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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MaxLinear and RFHIC have collaborated on a power amp solution for high-power macro cell radio units (RUs) that lowers power consumption, weight, and volume. The setup combines RFHIC’s GaN power amplifiers with MaxLinear’s digital predistortion (DPD) technology running on the Sierra radio SoC. The companies will showcase the solution at next week’s Mobile World Congress 2025.

MaxLinear’s DPD technology (MaxLIN) and Sierra radio chip, combined with RFHIC’s ID19801D GaN power amplifier and SDM19007-30H drive amplifier, achieve 55.2% line-up power efficiency with ACLR < -61 dBc and EVM < 3% at 49.6 dBm (91 W). The setup operates in the PCS band (1930–1995 MHz) with 2×NR10MHz carriers.

The Sierra radio SoC supports all major RU applications, including conventional macro, massive MIMO, pico, and all-in-one small cells. It integrates an RF transceiver supporting up to 8 transmitters, digital frontend with MaxLIN, low-PHY baseband processor, O-RAN split 7.2x fronthaul interface, and Arm Cortex-A53 quad-core CPU subsystem.

RFHIC’s ID series GaN power transistors operate from 1.8 GHz to 4.2 GHz, delivering saturated power levels of 410 W, 460 W, 700 W, and 800 W. The SDM series two-stage GaN hybrid drive amplifiers, internally matched to 50 Ω, cover 1.8 GHz to 4.1 GHz with output power options of 40 W, 60 W, and 80 W.

MaxLinear

RFHIC

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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This design idea reprises another “1A, 20V, PWM controlled current source.” Like the earlier circuit, this design integrates an LM3x7 adjustable regulator with a PWM DAC to make a programmable 20 V, 1 A current source. It profits from the accurate internal voltage reference and overload and thermal protection features of this time proven Bob Pease masterpiece! 

However, unlike the earlier design idea that requires a floating, fixed output 24-VDC power adapter, this sequel incorporates a ground-referred boost preregulator that can run from a 5-V regulated or unregulated supply rail. The previous linear design has limited power efficiency that actually drops below single-digit percentages when driving low voltage loads. The preregulator in this version fixes that by tracking the input-output voltage differential across the LM3x7, maintaining it at a constant 3 V. This provides adequate dropout-suppressing headroom for the LM3x7 while minimizing wasted power and unnecessary heat.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Here’s how it works. LM317 fans will recognize Figure 1 as the traditional LM317 constant current source topology that maintains Iout = Vadj/Rs by forcing the ADJ pin to be 1.25 V more negative (a.k.a. less positive) than the OUT pin. It has worked great for 50 years, but of course the only way you can vary Iout is by changing R. 

Figure 1 A classic LM317 constant current source where: Iout = Vadj/R = 1.25v/Rs.

Figure 2 shows another (easier) way to make Iout programmable. The circuit enables control of ampere-scale Iout with only milliamps of Ic control current. 

Figure 2 A modification that makes the current source variable where: Iout = (Vadj – IcRc)/Rs – Ic.

Figure 3 shows this idea fleshed out and put to practical use. Note that Rs = R4 and Rc = R5.

Figure 3 U2 current source programmed by U1 PWM DAC and powered by U3 tracking preregulator.

Figure 2’s Ic control current is provided by the Q2 Q3 complementary pair. Since Q3 provides tempco compensation for Q2, it should be closely thermally coupled with its partner. Q4 does some nonlinearity compensation by providing curvature correction to Q2’s Ic control current generation. The daisy chain of three 1N4001 diodes provides bias for Q2 and Q4.

The PWM input frequency is assumed to be 10 kHz or thereabouts. Ripple filtering is the purpose of C1 and C2 and gets some help from an analog subtraction cancellation trick first described in “Cancel PWM DAC ripple with analog subtraction.”

About that tracking preregulator thing: Control of U3 to maintain the 3 V of headroom required to hold U2 safe from dropout relies on Q1 acting as a simple differential amplifier. Q1 drives U3’s Vfb voltage feedback pin to maintain Vfb = 1.245 V. Therefore (if Vbe = Q1’s base-emitter bias, typically ~0.6 V for Ie = ~500 µA)

Vfb/R7 = ((U2in – U2out) – Vbe)/R6
1.245v = (U2in – U2out – 0.6v)/(5100/2700)
U2in – U2out = 1.89 * 1.245v + 0.6v = 3v

 Note, if you want to use this circuit with a different preregulator with a different Vfb, just adjust:

R7 = R6 Vfb/2.4v

Finally, a note about overvoltage. Current sources have the potential (no pun!) for output voltage to soar to damaging levels (destructive of U3’s internal switch and downstream circuitry too) if deprived of a proper load. R11 and R12 protect against this by utilizing U3’s built in OVP feature to limit max open circuit voltage to about 30 V if the load is lost.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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The post 1 A, 20V PWM DAC current source with tracking preregulator appeared first on EDN.

Truthfully, I originally didn’t plan on covering the new iPhone 16e, Apple’s latest “entry-level” phone preceded by three generations worth of iPhone SE devices.

I knew a fourth-generation offering was coming (and sooner vs later), since European regulations had compelled Apple to phase out the SEs’ proprietary Lightning connector in favor of industry-standard USB-C. The iPhone SE 3, announced in 2022, had already been discontinued at the end of last year in Europe, in fact, along with the similarly Lightning-equipped iPhone 14, both subsequently also pulled from Apple’s product line across the rest of the world coincident with the iPhone 16e’s unveiling on February 19, 2025. Considering the heavy company-wide Apple Intelligence push, the iPhone SE 3 was also encumbered by its sub-par processor (A15 Bionic) and system memory allocation (4 GBytes), both factors suggesting the sooner-vs-later appearance of a replacement.

But how exciting could a new “entry-level” (translation: cost-optimized trailing-edge feature set) smartphone be, after all? Instead, I was planning on covering Amazon’s unveiling of its new AI-enhanced (and Anthropic-leveraging, among others) Alexa+ service, which happened earlier today as I write these words on the evening of February 26. That said, as Amazon’s launch event date drew near, I began hearing that no new hardware would be unveiled, just the upgraded service (in spite of the fact that Amazon referred to it as a “Devices & Services event”), and that what we now know of as Alexa+ would only beta-demoed, not actually released until weeks or months later. Those rumors unfortunately all panned out; initial user upgrades won’t start until sometime in March, more broadly rolling out over an unspecified-duration period of “time”.

What those in attendance in New York (no virtual livestream was offered) saw were only tightly scripted, albeit reportedly impressive (when they worked, that is, which wasn’t always the case), demos. As we engineers know well, translating from curated demos to real-world diverse usage experiences rarely goes without a hitch or few. Then there were the indications of longstanding (and ongoing) struggles with AI “hallucinations”, another big-time technology hit. Add in the fact that Alexa+ won’t run on any of the numerous, albeit all geriatric, Amazon devices in my abode, and I suspect at last for a while, I’ll be putting my coverage plans on hold.

Back to the iPhone 16e then, which I’m happy to report ended up being far more interesting than I’d anticipated, both for Apple’s entry-level and broader smartphone product line and more generally for the company’s fuller hardware portfolio. Let’s begin with the name. “SE” most typically in the industry refers to “Special Edition”, I’ve found, but Apple has generally avoided clarifying the meaning here, aside from a brief explanation that Phil Schiller, Apple’s then-head of Worldwide Product Marketing (and now Apple Fellow), gave a reporter back in 2016 at the first-generation iPhone SE unveiling.

And in contrast to the typical Special Edition reputation, which comes with an associated price tag uptick, Apple’s various iPhone SE generations were historically priced lower than the mainstream and high-end iPhone offerings that accompanied them in the product line at any point in time. To accomplish this, they were derivations of prior-generation mainstream iPhones, for which development costs had already been amortized. The iPhone SE 3, for example, was form factor-reminiscent of the 2017-era, LCD-based iPhone 8, albeit with upgraded internals akin to those in the 2021-era iPhone 13.

The iPhone 16e marks the end of the SE generational cadence, at least for now. So, what does “e” stand for? Once again, Apple isn’t saying. I’m going with “economy” for now, although reality doesn’t exactly line up with that definitional expectation. The starting price for the iPhone SE 3 at introduction was $429. In contrast, the iPhone 16e begins at $599 and goes up from there, depending on how much internal storage you need. Not only did Apple ratchet up the price tag, as it’s more broadly done in recent years, it also broke through the perception-significant $499 barrier, which frankly shocked me. In contrast, if you’ll indulge a bit of snark, I chuckled when I noticed Google’s response to Apple’s news: a Pixel 8a price cut to $399.

That said, RAM jumps from 4 GBytes on the iPhone SE 3 to (reportedly: as usual, Apple didn’t reveal the amount) 8 GBytes. The iPhone SE 3’s storage started at 64 GBytes; now it’s 128 GBytes minimum. The 4.7” diagonal LCD has been superseded by a 6.1” OLED; more generally, Apple no longer sells a single sub-6” smartphone. And the front and rear cameras are both notably resolution-upgraded from those in the iPhone SE. The front sensor array also now supports TrueDepth for (among other things) FaceID unlock, replacing the legacy Touch ID fingerprint sensor built into the no-longer-present Home button, and the rear one, although still only one, includes 2x optical zoom support.

Turning now to the internals, there are three particularly notable (IMHO) evolutions that I’ll focus on. Unsurprisingly, the application processor was upgraded for the Apple Intelligence era, from the aforementioned A15 Bionic to the A18. But this version of the newer SoC is different than that in the iPhone 16, only enabling 4 GPU cores versus 5 on the mainstream iPhone 16 (and 6 on the iPhone 16 Pro). Again, as I mentioned before, I suspect that all three A18 variants are sourced from the same sliver of silicon, with the iPhone 16e’s version detuned to maximize usable wafer yield. Similarly, there may also be clock speed variations, another spec that Apple unfortunately doesn’t make public, between the three A18 versions.

More significant to me is that this smartphone marks the initial unveil of Apple’s first internally developed LTE-plus-5G cellular subsystem. A quick history lesson; as regular readers already know, the company generally prefers to be vertically integrated versus external supplier-dependent, when doing so makes sense. One notable example was the transition from Intel x86 to Apple Silicon Arm-based computer chipsets that began in 2020. Notable exceptions (at least to date) to this rule, conversely, include volatile (DRAM) and nonvolatile (flash) memory, and image sensors. As with Intel in CPUs, Apple has long had a “complicated” (among other words) relationship with Qualcomm for cellular chipsets. Specifically, back in April 2019, the two companies agreed to drop all pending litigation between them, shortly after Qualcomm had won a patent infringement lawsuit, and which had begun two years earlier. Three months later, Apple dropped $1B to buy the bulk of Intel’s (small world, eh?) cellular modem business.

Six years later, the premier C1 cellular modem marks the fruits (Apple? Fruit? Get it?) of the company’s longstanding labors. Initial testing results on pre-release devices are encouraging from performance and network-compatibility standpoints, and Apple’s expertise in power consumption coupled with the tight coupling potential with other internally developed silicon subsystems, operating systems and applications are also promising. That said, this initial offering is absent support for ultra-high-speed—albeit range-restrictive, interference-prone and coverage-limited—mmWave, i.e., ultrawideband (UWB) 5G. For that matter, speaking of wireless technologies, there’s no short-range UWB support for AirTags and the like in the iPhone 16e, either.

Whose modem—Apple’s own, Qualcomm’s, or a combination—will the company be using in its next-generation mainstream and high-end iPhone 17 offerings due out later this year? Longer term, will Apple integrate the cellular modem—at minimum, the digital-centric portions of it—into its application processors, minimally at the common-package or perhaps even the common-die level? And what else does the company have planned for its newfound internally developed technology; cellular service-augmented laptops, perhaps? Only time will tell. Apple is rumored to also be developing its own Wi-Fi transceiver silicon, with the aspiration of supplanting today’s Broadcom-supplied devices in the future.

Speaking of wireless—and cellular modems—let’s close out with a mention of wireless charging support. The iPhone 16e still has it. But in a first since the company initially rolled out its MagSafe-branded wireless charging capabilities with the iPhone 12 series in October 2020, there are no embedded magnets this time around (or in future devices as well?).

Initial speculation suggested that perhaps they got dropped because they might functionally conflict with the C1 cellular modem, a rumor that Apple promptly squashed. My guess, instead, is that this was a straightforward bill-of-materials cost reduction move on the company’s part, perhaps coupled with aspirations toward system weight and thickness reductions, and maybe even a desire to otherwise devote the available internal cavity volume for expanded battery capacity and the like. After all, as I’ve mentioned before, anyone using a case on their phone needs to pick a magnet-inclusive case option anyway, regardless of whether magnets are already embedded in the device. That all said, I’m still struck by the atypical-for-Apple backstep the omission of magnets represents, not to mention the Android-reminiscent aspect of it.

The iPhone 16e isn’t the only announcement that Apple has made so far in 2025. Preceding it were, for example:

• Apple TV+ service support for Android (Messages next? I jest), and
• The second-generation Beats Powerbeats Pro (again, unlike Apple-branded earbuds, with Android support)

And what might be coming down the pike? Well, with today’s heavy discounts on current offerings as one possible indication of the looming next-generation queue’s contents, there’s likely to be:

• An M4 upgrade to the 13” and 15” MacBook Air, and
• An Apple Intelligence-supportive hardware update to the baseline iPad

Further down the road, I’m guessing we’ll also see:

• Next-generation AirTags
• The third generation of the AirPods Pro
• The aforementioned iPhone 17 family, reportedly including an “Air” variant, accompanied by next-generation Apple Watches
• M5 SoC-based devices (leading with the iPad Pro again, or back to the traditional computer-first cadence? The latter would be my guess), and
• Maybe even that HomePod Hub, aka HomePad we keep hearing rumors about

You’ll note that I mindfully omitted a Vision Pro upgrade from the 2025 wishlist Stay tuned for more press release-based unveilings to come later this spring, the yearly announcement-rich WWDC this summer, and the company’s traditional yearly smartphone and computer family generational-upgrade events this fall. I’ll of course cover the particularly notable stuff here in the blog. And for now, I welcome your thoughts on today’s coverage in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post The Apple iPhone 16e: No more fiscally friendly “SE” for thee (or me) appeared first on EDN.

The quantum low-density parity check (QLDPC) codes, the “holy grail” of quantum error correction research and development for 30 years, have a breakthrough, according to the Vancouver-based Photonic Inc. These codes use fewer quantum bits (qubits) than traditional surface code approaches. The company’s chief quantum officer, Stephanie Simmons, sat with EE Times to explain how this low-overhead error correction technology works to realize the promised exponential speedups in quantum computing.

Read the full story at EDN’s sister publication EE Times.

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The post The QLDPC code breakthrough in quantum error correction appeared first on EDN.