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Rheostats are simple and ubiquitous circuit elements, usually comprising a potentiometer connected as an adjustable two terminal resistor. The availability of manual pots with resistances spanning ohms to megohms makes the optimum choice of nominal resistance easy. But when an application calls for a digital potentiometer (Dpot), the problem can be challenging.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Dpots are only available in a resistance range that’s narrow compared to manual pots. They also typically suffer from problematically high wiper resistance and resistance tolerance. These limitations conspire to make Dpots a difficult medium for implementing precision rheostats. Recent EDN design idea (DI) articles have addressed these issues with a variety of strategies and topologies:

• Op-amp wipes out DPOT wiper resistance
• Synthesize precision Dpot resistances that aren’t in the catalog
• Synthesize precision bipolar Dpot rheostats
• A class of programmable rheostats

While each of these designs corrects one or more complaints on the lengthy list of digital rheostat shortcomings, none fixes them all and some introduce complications of their own. Examples include crossover distortion, unreduced sensitivity to resistance tolerances, resolution-reducing nonlinearity of the programmed resistance, and just plain old complexity.

Figure 1’s circuit isn’t a perfect solution either. But it does synthesize an accurate programmed resistance equal to reference resistor R1 linearly multiplied by U1’s Rbw/Rab digital setting (the ratio between the terminal B to wiper resistance and total element resistance).

Figure 1 A precision digital rheostat that synthesizes an accurate programmed resistance equal to reference resistor R1 linearly multiplied by U1’s Rbw/Rab.

Here’s how it works.

 R = (Va – Vb)/Ia
R = R1/(Raw/Rbw + 1) = R1 Rbw/Rab
Rab = Raw + Rbw = typically 5k to 10k

Where R is the programmed synthetic resistance, R1 is the reference resistor, Raw is the resistance between terminal A and wiper terminal, Rbw is the resistance between B and wiper terminal, and Rab is the total element resistance.

U1 works in “voltage divider” (pot) mode to set the gain of inverting amplifier A2. Pot mode makes gain insensitive to both U1’s wiper resistance (Rw) and Rab. They really don’t matter much—see Figure 4-4 in the Microchip MCP41XXX/42XXX datasheet.

Turning the crank on Figure 1’s design equation math, we get:

Ga2 = Raw/Rbw

Where Ga2 is A2’s gain. Further,

Voltage across R1 = (Va – Vb) + Ga2(Va – Vb) = (Raw/Rbw + 1)(Va – Vb) =  Rab/Rbw(Va – Vb)
Current through R1 = Ia = Rab/Rbw(Va – Vb)/R1

Then, since R = (Va – Vb)/Ia:

R = R1*Rbw/Rab

Va is lightly loaded by A1’s ~10 picoamp (pA) input bias, so R1 can range from hundreds of ohms up to multiple megohms as the application may dictate. It should be precision, certainly 1% or better; then, programming and the math above takes over.

Figure 2 plots the linear relationship between R and Rbw.

Figure 2 Linear relationship between R and Rbw showing the circuit synthesizes an accurate programmed resistance equal to reference resistor R1 linearly multiplied by U1’s Rbw/Rab.

A compensation capacitor (C1) probably isn’t necessary for the parts selection shown in Figure 1 for A2 and U1. But if a faster amplifier or a higher resistance Dpot is chosen, then 10 pF to 20 pF would probably be prudent.

Meanwhile, I think it would be fair to say this design looks competitive with its peers. But earlier I described it as imperfect. Besides being a single-terminal topology (like two others on the list), where else does it fall short of being a complete solution to the ideal digital rheostat (Digistat) problem?

Here’s where: As Figure 3 shows, when the programmed value for R goes down, A2’s gain (Ga2) must go up. Reading the graph from right to left, we see gain rising moderately as R declines by 75% from R1 to R1/4 where, Rbw/Rab = 64/256 and gain = 3, but then it takes off. This tends to exaggerate errors like input offset, finite GBW and other op-amp nonidealities while creating the possibility of early A2 saturation at relatively low signal levels.

Figure 3 Graphs for Ga2 (red) and R/R1 (black) versus Rbw/Rab on the x-axis. When the programmed value for R goes down, Ga2 must go up.

The severity of the impact of these effects on utility of the design, whether mild, serious, or fatal, will depend on how low you need go in R/R1 and other specifics of the application. So, it’s certainly not perfect, but maybe it’s still useful somewhere.

And about that single terminal problem. If you have an application that absolutely requires a two-terminal programmable resistance, you might consider Figure 4. Depending on the external circuitry, it might not oscillate.

Figure 4 Duplicate and cross-connect Figure 1’s circuitry to get a two-terminal programmable resistance.

In closing…

Thanks to frequent contributor Christopher R. Paul for his clever innovations and stimulating discussions on this topic, I would likely never have come up with this design without his help. More thanks go to editor Aalyia Shaukat for her clever creation of this DI section that makes fun teamwork like this possible in the first place. This article would definitely never have happened without her help.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Op-amp wipes out DPOT wiper resistance
• Synthesize precision Dpot resistances that aren’t in the catalog
• Synthesize precision bipolar Dpot rheostats
• A class of programmable rheostats

The post A precision digital rheostat appeared first on EDN.

A new network-on-chip (NoC) IP aims to dramatically accelerate chip development by introducing artificial intelligence (AI)-driven automation and reducing wire length to lower power use in system-on-chip (SoC) interconnect design. Arteris, which calls its newly introduced FlexGen interconnect IP a smart NoC, claims to deliver a 10x productivity boost, shortening design iterations from weeks to days.

Modern chips—connected by billions of wires—are ever-expanding with growing complexity. Modern SoCs have 5 to 20+ unique NoC instances, and each instance can require 5-10 iterations. As a result, SoC design complexity has surpassed manual human capabilities, which calls for smarter NoC automation.

“In SoC interconnect, while technology has advanced to new levels, a lot of work is still done in manual mode,” said Michal Siwinski, CMO of Arteris. FlexGen accelerates chip design by shortening and reducing iterations from weeks to days for greater efficiency.

“While FlexGen is still using the tried-and-tested NoC IP technology as basic building blocks, it automates the existing infrastructure by employing AI technology,” said Andy Nightingale, VP of product management and marketing at Arteris. “With FlexGen, we automate the NoC IP generation to reduce the manual work while opening high-quality configurations that rival or surpass the manual designs.”

Figure 1 A FlexNoC manual interconnect (above) is shown for an ADAS chip, while an automated FlexGen interconnect (blow) accelerates this chip design by up to 10x. Source: Arteris

According to Nightingale, it enhances engineering efficiency by 3x while delivering expert-quality results with optimized routing and reduced congestion. Dream Chip Technologies, a supplier of advanced driver assistance systems (ADAS) silicon solutions, acknowledges reducing design iterations from weeks to days while using FlexGen in its Zukimo 1.1 automotive ADAS chip design.

“FlexGen’s automated NoC IP generation allows us to create floorplan adaptive topologies with complex automotive traffic requirements within minutes,” said Jens Benndorf, GM at Dream Chip Technologies. “That enabled rapid experimentation to find design sweet spots and to respond quickly to floorplan changes with almost push-button timing closure.”

Shorter wire length

With AI comes a compute performance explosion, and as a result, the complexity of interconnects is going to exponential levels in SoC designs, leading to a huge explosion in the number of wires. FlexGen claims to reduce wire length by up to 30% to improve chip or chiplet power efficiency.

“We are also tackling the big problem of wire length in modern SoC designs,” said Nightingale. “As the gate count size reduces, it inevitably leads to dynamic power issues due to massive data traffic across wires.” By reducing wire length, FlexGen interconnect IP can reduce overall system power and thus help heating problems caused by the energy density of moving massive amounts of data across SoC interconnects.

Figure 2 FlexNoC manual interconnect (above) is shown with the best performance, while automated FlexGen (below) significantly reduces the interconnect wire length. Source: Arteris

Siwinski added that the number of gates doesn’t matter at smaller nodes. “Power from wire length kills you, so we reduce wire length to reduce overall power, performance, and area (PPA) in SoC designs.” That’s crucial as SoCs scale and become more powerful to meet the demands of applications like AI, autonomous driving, and cloud computing.

FlexGen is processor agnostic and supports Arm, RISC-V, and x86 processors. Moreover, its IP generation is highly repeatable to facilitate incremental design.

Related Content

• SoC Interconnect: Don’t DIY!
• What is the future for Network-on-Chip?
• Why verification matters in network-on-chip (NoC) design
• SoC design: When is a network-on-chip (NoC) not enough
• Network-on-chip (NoC) interconnect topologies explained

The post SoC interconnect automates processes, reduces wire length appeared first on EDN.

electronica China 2025 will take place from April 15 to 17, 2025 at the Shanghai New International Expo Centre (SNIEC), in halls W3-W5 and N1-N5. It is expected to attract a total of 1,700 high-quality exhibitors from Chinese and international markets covering 100,000 square meters. The visitor registration is going on heatedly, register now and check out the highlights of the important trade fair for the electronics industry in Asia!

The venue will feature sections for semiconductors, sensors, power supplies, testing and measurement, passive components, displays, connectors, switches, wiring harnesses and cables, distributors, printed circuit boards, electronic manufacturing services, semiconductor intelligent manufacturing, etc. 1,700 premium enterprises from both Chinese and international markets will join in succession, showcasing their cutting – edge scientific research achievements and industry solutions.

This year’s exhibition will continue to host multiple themed forums, focusing on popular application markets and rapidly evolving industries such as electric vehicles, automotive electronics, humanoid robot, third-generation semiconductor, embedded system, AI, IoT, energy storage, smart manufacturing, connector, motor drive. Industry leaders, technical experts, and academic researchers from the electronic sector, application domains, and research institutes will be invited to address audience queries, share case studies, and provide cutting-edge technological solutions.

Click to register now: https://ec.global-eservice.com/?lang=en&channel=ele

For more information: https://www.electronicachina.com.cn/en

The post electronica China 2025 is Coming: Embarking on a journey of in-depth exploration of the electronic industry chain! appeared first on ELE Times.

The latest radio resource management (RRM) conformance work item from the Global Certification Forum (GCF) has reached “Active” status following the approval of the Rohde & Schwarz R&S TS8980FTA-M1 5G conformance test system as the first to meet test platform approval criteria (TPAC). This includes the validation of RRM FR2 test cases in standalone mode (SA) for both one and two angles of arrival (1x AoA and 2xAoA) within 5G mmWave band combinations.

Rohde & Schwarz is the first company to obtain Global Certification Forum (GCF) test approval for validating the radio resource management (RRM) performance of advanced 5G New Radio (NR) devices. This approval specifically applies to devices operating in 5G NR standalone (SA) mode within FR2 and capable of managing multiple angles of arrival. It enables device manufacturers to certify their products for global compatibility with mobile networks that utilize mmWave frequencies and operate in 5G SA with a real 5G core network (5GC).

Verifying compliance with critical RRM test cases is increasingly important as wireless 5G routers and customer premises equipment (CPE) gain prominence for fixed wireless access (FWA) applications. These test cases are essential for ensuring a reliable end user experience, especially in challenging network conditions, such as blockages, or at the cell edge.

After the Conformance Agreement Group (CAG) #81 meeting held by GCF in Bangkok January 21 to 23, 2025, it was confirmed that Rohde & Schwarz is currently the only provider offering certification solutions that meet all mandatory test requirements for 5G FR2 RRM, while also supporting the largest number of validated test cases for both RF and RRM in this frequency range. The Rohde & Schwarz 5G mmWave test platform offers a wide range of advanced 5G FR2 non-standalone (NSA) and SA test cases. The platform is built on the CMX500 5G network emulator and includes the R&S ATS1800M anechoic chamber series as well as a powerful device under test (DUT) positioner.

Thomas Eyring, Senior Director of Device Certification at Rohde & Schwarz, commented on the milestone, saying: “We are proud to take a significant step toward enhanced conformance testing as a pioneer in mobile device testing. Our technology will help ensure the quality and reliability of 5G devices while addressing the

challenges in the FR2 frequency range. We are also working on test cases for the upcoming FR3 frequency range, which is expected to play a key role in 6G networks.”

The post Rohde & Schwarz first to achieve GCF approval for 5G FR2 RRM standalone mode conformance test cases appeared first on ELE Times.

Altium joins AWS Skills to Jobs Tech Alliance in India; Aims to Bridge Skills Gaps and Enhance Employability for Indian Students

• AWS Cloud Practitioner Essentials – Covering cloud technology basics
• AWS Technical Essentials – Introducing core cloud concepts like networking, databases, and storage
• Amazon AppStream 2.0 Primer – AWS’s application streaming solution
• IoT Fundamentals – Training in IoT and smart technology

• On Campus Applied Learning: Co-hosted events, workshops and challenges will give students hands-on experience in solving industry challenges.
• Pathways to Employment: Students who complete the joint curriculum will connect with industry partners for career opportunities.

The post Altium and AWS Collaborate to Equip India’s Next Generation of Engineers with Industry-Ready Skills in Electronics Design and Cloud Technology appeared first on ELE Times.

The global semiconductor manufacturing industry closed 2024 with strong fourth quarter results and solid year-on-year (YoY) growth across most of the key industry segments, SEMI announced today in its Q4 2024 publication of the Semiconductor Manufacturing Monitor (SMM) Report, prepared in partnership with TechInsights. The industry outlook is cautiously optimistic at the start of 2025 as seasonality and macroeconomic uncertainty may impede near-term growth despite momentum from strong investments related to AI applications.

After declining in the first half of 2024, electronics sales bounced back later in the year resulting in a 2% annual increase. Electronics sales grew 4% YoY in Q4 2024 and are expected to see a 1% YoY increase in Q1 2025 impacted by seasonality. Integrated circuit (IC) sales rose by 29% YoY in Q4 2024 and continued growth is expected in Q1 2025 with a 23% increase YoY as AI-fueled demand continues boosting shipments of high-performance computing (HPC) and datacenter memory chips.

Similar to electronics sales, semiconductor capital expenditures (CapEx) decreased in the first half of 2024 but saw a strong rebound, particularly in the fourth quarter, resulting in 3% annual growth by the end of 2024. Memory-related CapEx continued to lead the growth surging 53% quarter-on-quarter (QoQ) and 56% YoY in Q4 2024. Non-memory CapEx also edged up in Q4 2024 showing 19% QoQ and 17% YoY improvement. Total CapEx is expected to remain strong in Q1 2025, growing 16% relative to the same period of the previous year on the strength of investments to support high bandwidth memory (HBM) capacity additions for AI deployment.

The semiconductor capital equipment segment remained resilient primarily due to increased investments into expanding leading-edge logic, advanced packaging and HBM capacity. Wafer fab equipment (WFE) spending increased 14% YoY and 8% QoQ in Q4 2024. Quarterly WFE billings are expected to be around $26 billion in Q1 2025. China’s investment continues to play a significant role in the WFE market but started to subside by end of the year. Additionally, back-end equipment showed strong increases in Q4 2024 with the Test segment logging 5% QoQ growth and an impressive 55% YoY increase for the quarter, while the Assembly and Packaging segment experienced a YoY increase of 15%. Both segments are expected to show similar QoQ growth between 6-8% in Q1 2025.

In Q4 2024, installed wafer fab capacity surpassed a record 42 million wafers per quarter worldwide (in 300mm wafer equivalent), and capacity is projected to reach nearly 42.7 million in Q1 2025. Foundry and Logic-related capacity continues to show stronger increases, growing 2.3% QoQ in Q4 2024, and the segment is projected to rise 2.1% in Q1 2025 driven by capacity expansion for advanced nodes. Memory capacity increased 1.1% in Q4 2024 and is forecasted to remain at the same level in Q1 2025 driven by strong demand for HBM.

“Despite seasonality and the challenges of macroeconomic uncertainty, momentum in AI-driven investments continues to fuel expansion across key segments, including memory, capital expenditures, and wafer fab equipment,” said Clark Tseng, Senior Director of Market Intelligence at SEMI. “Looking forward for 2025, the industry remains cautiously optimistic, with robust growth prospects driven by ongoing demand for high-performance computing and data center buildout.”

“As we begin the year, our expectation is for stronger performance in the second half, with semiconductor sales anticipated to remain flat sequentially in the first half, followed by a notable double-digit increase in the latter half,” said Boris Metodiev, Director of Market Analysis at TechInsights. “Inventory challenges persist for discrete, analog, and optoelectronic manufacturers, which will need to be addressed before we can expect widespread growth to resume.”

The Semiconductor Manufacturing Monitor (SMM) report provides end-to-end data on the worldwide semiconductor manufacturing industry. The report highlights key trends based on industry indicators including capital equipment, fab capacity, and semiconductor and electronics sales, along with a capital equipment market forecast. The SMM report also contains two years of quarterly data and a one-quarter outlook for the semiconductor manufacturing supply chain including leading IDM, fabless, foundry, and OSAT companies. An SMM subscription includes quarterly reports.

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