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Forget Tesla coils and check out Marx generators

EDN Network - Fri, 09/23/2022 - 16:52

Low-voltage designs with rails in the single digits get a lot of attention these days, for reasons I don’t need to detail to this audience. Still, there are many situations where rails at hundreds of volts are needed, such as EVs. There are also many important uses for even higher-voltage systems ranging into the thousands of volts, such as physics experiments, safety tests, and even some mass-market consumer products.

I’m always fascinated by the clever ways engineers and scientists have devised to increase a supply voltage by orders of magnitude. You’re undoubtedly familiar with and may have even built a Tesla coil, used for dramatic science demonstrations as well as serious research. (There are many websites showing how to build your own—with suitable safety-related caveats, of course.) As its name implies, the core design uses step-up transformer coils. That’s simple enough in principle, but the “devil” and danger is in the details of the implementation, of course. Another high-voltage scheme is the flyback converter, widely used in CRT-based TVs until they became obsolete, but still used in other applications.

There’s yest another high-voltage topology which is much less known but often used when high-voltage pulses are needed: the Marx generator. It’s not new, as it was first described by Erwin Otto Marx in 1924. Marx generators generate a high-voltage pulse from a low-voltage DC supply, and they are used in high-energy physics experiments, as well as to simulate the effects of lightning on products such as power-line switchgear and aviation equipment.

As with the Tesla coil, the concept is simple, as is the schematic diagram, Figure 1. It operates by charging a number of capacitors in parallel, then quickly connecting them in series. Initially, the capacitors are charged in parallel to voltage VC by a DC power supply through resistors RC. The individual spark gaps are “open” as the voltage VC across them is below their breakdown voltage, thus allowing to capacitors to continue charging. The last spark gap isolates the output of the generator from the load.

Figure 1 The Marx generator schematic diagram shows its simplicity, as a cascaded series of repeated spark-gap, resistor, and capacitor stages. Source: Wikipedia

Once the charged voltage is high enough for the first spark gap to trigger (breakdown), the critical sequential action begins. The short-circuit, which now occurs across the gap, puts the first two capacitors in series, so there is a voltage of about 2VC across the second spark gap. Now the second gap breaks down and adds to the third capacitor, with a cascade of  breakdowns across all of the gaps.

To generate the final spark, the last gap connects the output of the capacitors to the load. In principle, this output voltage is the sum of the voltages across all the capacitors; in practice, it is somewhat less. One of the interesting features about this design is that the voltage across each of the charging resistors is equal to the charging voltage and not the final voltage even as the array charges up; this greatly simplifies component procurement and layout, and also reduces costs.

How much voltage can you generate with this topology? The answer is simple: as much as you want and can afford. It’s used for megavolt-level research-laboratory systems, Figure 2, but you can also generate a few thousand volts from a 1.5 V AA battery.

Figure 2 This megavolt Marx generator used for testing high-voltage power-transmission components at TU Dresden, Germany. Source: Wikiwand

Looking at the schematic diagram, bill of materials, and construction details, it seems that building a Marx generator is easier than doing the popular the Tesla coil, since it doesn’t require windings or as many high-voltage components, Figure 3. There are many web sites showing how to build your own (of course, the usual high-voltage warnings apply).

Figure 3 Compared to the Tesla coil, the Marx generator has a simpler physical construction – but there are still high and dangerous voltages, of course. Source: Electric Stuff – UK

You can also buy one in kit form (the main PC board only, or board plus all components), Figure 4, from Eastern Voltage Research. This unit produces 3 to 4 inches of output arc and 90-kV maximum theoretical output voltage depending on input voltage source, spark gap tuning, and atmospheric conditions. (Note that the company is high-voltage-device agnostic, as they also offer Tesla-coil kits.)

Figure 4 You can also buy a tabletop Marx generator as a ready-to-assemble kit, yielding an output arc up to 4 inches and voltage as high as 90 kV. Source: Eastern Voltage Research

Of course, there are other ways to boost low voltages to much-higher ones. Voltage-multiplier circuits (doublers, triplers, and cascades of these) can also reach thousands of volts. Like the Marx generator, these “multiply” the source voltage by charging capacitors in parallel and discharging them in series. One important difference is that voltage multipliers are powered with alternating current and produce a steady DC output voltage, whereas the Marx generator produces a pulse. Also, there is no open ‘”spark” with the multiplier circuit, which makes it more suitable to use in consumer or mass-market products where higher voltages are needed.

Have you ever built any of these higher-voltage projects, either for personal use or commercial production? If you came from a lower-voltage background, what were the most important lessons you learned about component selection, procurement, or use? What about physical layout? 


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Tektronix and Anritsu collaborate to build new PCIe 6.0 receiver test

EDN Network - Fri, 09/23/2022 - 16:41

Tektronix, in collaboration with Anritsu, has introduced a PCIe 6.0 receiver test solution that it says renders fast, high-quality measurements. The receiver automation software runs on the Tektronix DPO70000SX series of real-time oscilloscopes and Anritsu’s MP1900A BERT.

The software performs PCIe 6.0 stressed eye calibration at 64 GT/s (PAM4), providing confidence that designs are thoroughly tested at the required bit error rate target. Intuitive step-by-step tools provide link training routines for the MP1900A BERT to ensure the receiver is tested accurately. The PAMJET DSP tool provides critical 64-GT/s jitter and noise measurements with instrument noise compensation.

The receiver test automation software provides a single control panel to manage the Tektronix oscilloscope and Anritsu BERT during receiver calibration. An intuitive software wizard guides users through short- and long-channel calibration steps for accurate and repeatable calibration at 64 GT/s.

The Tektronix PCIe 6.0 receiver test solution is available worldwide for use with DPO70000SX real-time oscilloscopes. For more information and pricing, click here.


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Fabless startup leverages Xpeedic EM simulator

EDN Network - Fri, 09/23/2022 - 16:39

Chipletz has adopted Xpeedic’s Metis EM simulation tool for its upcoming Smart Substrate products, which will bundle multiple ICs in a single package. The fabless substrate vendor looks to bridge the gap between the slowing of Moore’s law and the rising demand for compute performance with its advanced packaging technology.

Metis is a fast EM simulation tool that integrates with both chip and package design tools to address capacity, accuracy, and throughput requirements. Its 3D EM solver covers simulation from DC to high frequencies and cross-scale simulation from nano to centimeter level.

“The Chipletz Smart Substrate products will be a welcome addition to toolkits of designers working on advanced 2.5D and 3D IC packaging,” said Feng Ling, CEO of Xpeedic. “Smart Substrate will facilitate multiple ICs from different vendors in a single package, especially important for the AI workloads, immersive consumer experiences and high-performance computing markets. We’re pleased to have a role in the delivery of this advanced packaging technology.”

“Xpeedic and its Metis EM simulation tool are helping us meet our unique signal and power integrity analysis challenges by delivering unprecedented performance advantages for runtime and memory usage” commented Bryan Black, CEO of Chipletz.

Chipletz is targeting delivery of its initial products to its customers and partners in early 2024.



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80 reference designs released for motor commutation sensors

EDN Network - Fri, 09/23/2022 - 16:38

With the Resolver 4.0 catalog from Renesas, engineers can select from 80 market-ready designs based on the company’s IPS2 motor commutation sensors. Each design for the inductive position sensors targets a unique motor shaft or pole-pair configuration and comes with complete design files, measurement reports, tools, and guidelines.

The Resolver 4.0 catalog offers turnkey solutions that can be implemented in a wide range of applications, including automotive systems, robotics, servo motors, home automation, and medical. The designs provide completed schematics, fully wired PCB designs, and Gerber files, along with software stacks, bill of materials, and more. An inductive coil optimization tool allows the design of optimized sensing elements based on experiments with air gap variations and performance simulations, including accuracy and error analysis.

According to Renesas, the IPS2550 and IPS2200 inductive position sensors weigh significantly less than conventional magnet-based sensors and deliver fast rotational speeds to support high-speed motor commutation for passenger cars and motor control for industrial equipment. They also offer stray-field immunity, are less sensitive to noise and vibration, provide better efficiency and accuracy, and are less susceptible to error than magnets.

The Resolver 4.0 catalog is free of charge and can be downloaded using the links to the product pages below. The IPS2550 (automotive) and ISP2200 (industrial) sensors are available now in full production.

IPS2550 product page

IPS2200 product page

Renesas Electronics 

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ADS improvements for DDR5 simulation

EDN Network - Fri, 09/23/2022 - 16:36

Keysight’s PathWave Advanced Design System (ADS) 2023 for high-speed digital design includes improvements for DDR5 simulation. In addition to DDR5, the new Memory Designer capabilities in PathWave enable modeling and simulation of other interface standards, such as LPDDR5/5x, GDDR6/7, and HBM3.

PathWave ADS 2023 ensures rapid simulation setup and advanced measurements, while providing designers critical insights to overcome signal integrity challenges. Its Memory Designer quickly constructs parameterized memory buses using the new pre-layout builder, allowing designers to explore system trade-offs that reduce design time and derisk product development of memory systems.

Keysight reports that PathWave ADS 2023 for high-speed digital design completes simulations up to 80% faster. It leverages cloud-based high-performance computing using parallel processing to accelerate Memory Designer and EM simulation runtime. PathWave also automates design-to-test workflows with an easy connection between simulation and measurement domains to  enable comparison of stored data against measured results from physical prototypes.

To learn more about PathWave ADS 2023 for high-speed digital design, click here.

Keysight Technologies  

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How to manage changing IP in an evolving SoC design

EDN Network - Fri, 09/23/2022 - 16:36

In a previous article, Getting started in structured assembly in complex SoC designs, an unexceptional system-on-chip (SoC) design was shown to contain hundreds of intellectual property (IP) blocks. Also, it was demonstrated how connections between these IP blocks may involve hundreds or thousands of ports with multiple tie-off options.

Some IP blocks may come from third-party suppliers, while others are developed internally. The problem is that any of these blocks may experience revision changes throughout the course of design. This is especially true of internally developed IP, which may undergo multiple revisions due to evolving specifications and requirements. Managing these changes as the design evolves can quickly become a nightmare.

Why do things change?

The ancient Greek philosopher Heraclitus of Ephesus (535-475 BC) famously noted: “The only constant in life is change.” When it comes to the IP blocks forming an SoC, the goal is to make the process of change as easy as possible (Figure 1).

Figure 1 The goal is to make change in IP blocks smooth. Source: Arteris IP

In the case of IP from third-party vendors, changes during a particular project are relatively rare. One exception is when the design team detects and reports a bug or other issue, and the vendor responds by generating a new revision of the IP to address the problem. Another scenario is when it becomes necessary to replace an IP from one vendor with an equivalent IP from another vendor, which—among other things—may necessitate changes at the interface.

By internally generating IP, change—especially in the early stages of the design—is the normal modus operandi. In many cases, an IP block starts out as a stub in the form of a black box with port definitions. As the design progresses, more and more details are added, eventually resulting in the completed IP. Even then, changes to the IP, including modifications to the interfaces, may persist long into the development process.

An SoC design is typically represented as a hierarchical netlist of blocks, with the lowest level being the IP blocks themselves. This netlist is captured in a hardware description language (HDL) such as Verilog or VHDL at the register-transfer level (RTL) of design abstraction.

Traditionally, this netlist has been created by hand using an extensible and customizable text editor like VI or GNU Emacs. Although some die-hard designers still use this approach, the fact that a single IP block instantiation may now involve a thousand connections and span hundreds of lines of code means that it’s becoming increasingly untenable.

If the netlist is hand-crafted, it can be hard enough to update a single IP instantiation. The problem is only exacerbated when multiple instantiations of the same block exist. The result is that implementing IP changes by hand is time-consuming and prone to error, increasing risk, degrading productivity, and impacting time to market (TTM).

Managing change in IP

The foundational step to managing change is for the hierarchical RTL netlist to be described in such a way as to facilitate assembly, refinement and update through abstraction and automation. This is achieved by using the IP-XACT standard, which comes in an XML-based format. IP-XACT was originally developed by The SPIRIT Consortium, which subsequently merged with Accellera, and the standard is now supported as IEEE 1685.

Several companies have developed internal, proprietary tools that employ IP-XACT. One approach for managing IP change is to use tools like Magillem IP Deployment Technology. In the case of IP blocks acquired from third-party vendors, these blocks will typically come supplied with a corresponding IP-XACT model. If not, such a model will need to be created. Similarly, in the case of internally generated IP blocks, each block will require an associated IP-XACT model. Unfortunately, the IP-XACT standard is complex and unfamiliar to many. However, the tools can be used to read an existing RTL representation of an IP block and automatically generate the corresponding IP-XACT model. As part of this, users can add control and status registers (CSRs) to legacy IPs.

If members of the design team create the top-level hierarchical netlist by hand, this can be read by Magillem, which can automatically create a hierarchical graphical representation of the design. Alternatively, if the design team starts with a clean slate, the tools can be used to display the collection of IP blocks available. The users can employ a drag-and-drop interface to capture the design hierarchy and place and connect the desired blocks. The tool can then generate a correct-by-construction RTL netlist of the design.

But this is just the start. What makes tools like this powerful is that it’s possible to create scripts associated with individual blocks of IP, hierarchical blocks, and the design as a whole. These scripts, which can be in Python, Tcl (pronounced “tickle”) or Java, may be captured using a regular text editing tool. Alternatively, clicking on a block in the graphical view of the design allows the user to create or edit a script associated with that block (Figure 2).

Figure 2 Scripts can be associated with IP blocks, hierarchical blocks, or the design as a whole. Source: Arteris IP

In conjunction with Magillem’s application programming interface (API), these scripts can be instructed to perform tasks like updating version X.X of an IP block with X.Y. Furthermore, a script can be used to update all instances of the same block. This is similar in concept to a “search and replace” function in an editor, except that the tool also performs appropriate checks, such as ensuring that the ports still match. If any problems are detected, the user is alerted and supported by tools that aid in addressing the issues. An even more powerful feature is that scripts can call other scripts as required.

Simulation and verification

The combination of Magillem’s API and scripting capabilities goes far beyond managing change. In the case of simulation, for example, it is common to have multiple representations of each IP block, from a simple stub to a full-blown implementation with the possibility of one or more limited-function implementations.

Traditionally, selecting between these various representations has been performed using “ifdef” type statements embedded in the netlist to control the compiler. Although this sounds simple, actually employing this approach to define multiple views of a complex SoC can quickly become unwieldy. The alternative is to use scripts to perform tasks like “swap out representation X with Y.”

Similarly, although the focus of this article has been on the management of design IP, these techniques can also be applied to managing associated verification IP.

Adoption of IP-XACT tools

As SoC designs have continued to evolve in size and complexity—with many devices featuring hundreds of IP blocks and tens of thousands of connections—creating and maintaining the hierarchical RTL netlist by hand is no longer tenable.

In addition to speeding the generation of the initial netlist and ensuring a correct-by-construction design, the API and scripting facilities provided by IP-XACT-based tools like Magillem facilitate managing changes to the IP throughout the development process. The aim is to speed development, increase productivity, reduce risk, and decrease time to market.

Ryan Y. Chen is field applications engineering manager at Arteris IP.

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Transimpedance amplifier enables 50-Gbps PAM4 5G deployments

EDN Network - Fri, 09/23/2022 - 16:34

Semtech announced the production of the GN1700 linear transimpedance amplifier (TIA) for emerging 50-Gbps PAM4 5G front and mid haul deployments. Intended for use with 50-Gbps SFP56 PAM4 5G wireless optical modules, the GN1700 can be paired with the company’s Tri-Edge GN2255 and GN2256 bidirectional clock data recovery (CDR) ICs with integrated drivers for optimized performance.

Semtech reports that 50-Gbps PAM4 architectures will be used to enable 5G deployments, such as 64T64R massive MIMO-based macro base stations and mmWave small base stations. IC technology that enables optical fiber communication in these deployments is a critical part of the network enabling the wired backbone of this architecture.

“With the production of our FiberEdge GN1700 and Tri-Edge 5G portfolio, including GN2255 and GN2256, our customers can now enable successful pilot qualifications for 50-Gbps PAM4 systems,” said Raza Khan, senior market manager for Semtech’s Signal Integrity Products Group. “This is a great milestone and a testament to Semtech’s on-time execution on our innovative product offerings.”

Datasheets for Semtech’s signal integrity products are available by creating an online account.

GN1700 product page


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