ELE Times

DRFM jammers rely on receiving radar signals, digitizing them and retransmitting them with controlled delay, phase and frequency. As radar systems become more agile and use increasingly complex waveforms, test systems need to measure parameters such as pulse shape, timing, modulation and repeatability, as well as analyze complete pulse trains and pulse-to pulse variations. The R&S FSWX signal and spectrum analyzer addresses these requirements with its dual-channel, phase coherent architecture. With the R&S FSWX-KM700 pulse analysis option, Rohde & Schwarz adds a software extension dedicated to pulsed-signal and DRFM analysis, enabling engineers to evaluate pulse parameters, pulse trains, modulation and the timing behavior of jammer signals.

The R&S FSWX-KM700 pulse analysis option measures key pulse parameters, including pulse width, amplitude, rise time, fall time, pulse repetition interval, duty cycle, pulse shape and overshoot. These measurements can help engineers evaluate the accuracy and consistency of reproduced radar pulses and identify variations in timing, amplitude and other pulse characteristics. Such variations can affect the fidelity of a reproduced signal, making accurate pulse analysis important when testing DRFM-based deception and jamming systems.

The analysis also covers complete pulse trains. The option extracts pulse repetition frequency spectra and pulse-to-pulse variation data, allowing engineers to verify complex pulse sequence behavior and timing patterns. R&S FSWX-KM700 supports chirped pulses, pulse width modulation, pulse position modulation and phase-modulated waveforms. Engineers can use these measurements to check whether a device handles modulation schemes used by modern radar systems, including both the pulse envelope and modulation content.

The system can trigger on amplitude, pulse width, pulse repetition interval or user-defined patterns. This helps engineers isolate selected events inside a pulse train and focus the measurement on the relevant parts of the signal. For longer measurements, R&S FSWX-KM700 aggregates results from many captured pulses. This provides information about repeatability and consistency over time and helps engineers assess whether timing or modulation errors occur only under certain conditions.

The option comes with the following displays: parameter trend for DRFM electronic attack technique analysis, capture vs. time to measure jammer response time and latency between stimulus and response, individual pulse parameter display such as pulse amplitude, frequency, and phase to make sure there are no distortions introduced by the jammer. These measurements connect pulse analysis with the behavior of the jammer under test.

With the new R&S FSWX-KM700 option, the FSWX signal and spectrum analyzer gains a more specialized role in DRFM test workflows. It combines phase coherent multi-channel analysis with pulse, pulse train, modulation and segmented capture functions in one instrument, supporting verification of signal fidelity, timing behavior and consistency in agile electronic warfare scenarios.

 

The post Rohde & Schwarz FSWX-KM700 Adds Pulse Analysis for DRFM Jammer and Radar Testing appeared first on ELE Times.

​A new analysis report presented by EY-IESA estimates that India’s semiconductor market will grow more than threefold by 2035. It states that the market will increase from nearly $64 billion in 2026 to $200 billion by 2035 covering areas such as artificial intelligence, data centres, telecommunications, electric vehicles, and advanced semiconductor manufacturing.

The findings of the report point to the increase in demand for semiconductors in India’s consumer electronics and industrial sectors. Consumer electronics is the largest demand segment accounting for a 30% market share, followed by Automotive (16%) and Industrial (15%).

Semiconductor imports by India have also increased in recent years. According to the report, semiconductor imports have increased fivefold, from $5.7 billion in FY2017 to $30.3 billion in FY2025, representing a compound annual growth rate of 23%. The report also states that increased domestic demand presents a good opportunity to expand India’s manufacturing, research and development, and supply chain capabilities for semiconductors.

Another key strength is India’s ability in chip design. The country has nearly 20% of the global chip design engineers which is a positive point for talent development and there is a huge opportunity for expand semiconductor manufacturing, chip design and commercialisation.

According to the report, key technologies in the semiconductor industry—including advanced packaging, compound semiconductors, photonics and chip-to-system integration—should be the focus for India’s potential growth. It also calls for stronger semiconductor manufacturing clusters, improved infrastructure, specialised talent and closer industry-academic collaboration.

The Indian semiconductor market, projected $200 billion by 2035, indicates the scale of the opportunity for India as it seeks to expanding its footprints across the semiconductor supply chain.

The post India’s Semiconductor Market Projected to Reach $200 Billion by 2035: EY-IESA Report appeared first on ELE Times.

​As India emerges as a global supplier in the semiconductor industry and builds capabilities in chip design and manufacturing, the country could face cybersecurity, geopolitical, and other disruption-related challenges. Union IT Minister Ashwini Vaishnaw gave this warning during a media interview in New Delhi. While speaking to the media on September 19, the minister urged Indian startup companies to be careful against potential cyberattacks, geopolitical risks and other disruptions.

Addressing the media, the minister said that India’s emergence as a country capable of designing and manufacturing chips for semiconductor devices could improve its position in the global semiconductor value chain, potentially drawing attention from established players and opponents of India’s rise. He also stated that he had discussed these concerns with the industry and urged them to prepare for potential cyberattacks, threats, and other possible disruptions.

These risks could extend beyond common business competition to include cyberattacks, physical attacks, misinformation, and other forms of disruption. The country’s push for semiconductors has also attracted increasing investment interest. Recent announcements related to this include Applied Materials, a United States manufacturing company, planning a US$5 billion investment in India through 2035, Lam Research’s proposed ₹10,000 crore investment; and Fujifilm planning to invest approximately ₹800 crore to establish a semiconductor material plant in Dholera. These developments reflect the country’s growing ambition to expand India’s semiconductor ecosystem.

The warning from Union IT Minister reflects the major concern that needs to be cater by Indian semiconductor companies to consider cybersecurity and other broader disruption risks alongside investment in manufacturing capacity, technology and talent.​

The post Vaishnaw Warns India’s Semiconductor Industry of Cyberattacks and Disruptions appeared first on ELE Times.

Vishay Intertechnology has introduced a new Automotive Grade, top-side cooling mount thick film power resistor. The Vishay Sfernice D2TO35S is designed for automotive applications, offering improved thermal performance and reduced PCB space requirements. The resistor provides high power dissipation of up to 35 W at 25°C and is housed in a surface-mount TO-263 (D²PAK) package.

As thermal constraints increasingly become the primary system design limitation, many power components are transitioning from PCB-based cooling to top-side cooled architectures. By transferring heat directly to a heatsink, the D2TO35S released today enables up to nine times greater power dissipation than standard PCB-mounted devices when paired with an appropriate heatsink. Its compact, surface-mount design allows designers to increase power dissipation within the same footprint or provide the same functionality in a smaller footprint, while lowering PCB temperatures, reducing thermal stress on neighboring components, and improving overall system reliability.

Offering a non-inductive design for improved signal integrity and power handling in fast transient conditions, the D2TO35S features a resistance range from 4.7 Ω to 550 kΩ — with tolerances down to ± 1 % — thermal resistance of 4.28 °C/W, TCR down to ± 150 ppm/°C, and a wide operating temperature range from -55 °C to +175 °C. The RoHS-compliant device is solder reflow secure at 270 °C/10 s.

The post Vishay D2TO35S: 35 W Automotive Thick Film Power Resistor with Top-Side Cooling in TO-263 Package appeared first on ELE Times.

ROHM has developed a 2nd Generation terahertz (THz) wave oscillation device using semiconductor elements known as Resonant Tunneling Diodes (RTDs). The company is making the device available via the RTD-EVK-G2 Terahertz Wave Device Evaluation Kit, which includes a sample device, cable, and evaluation board. The kit enables companies and research institutions to evaluate THz wave oscillation and detection in a compact development environment.

Occupying the frequency region between radio waves and light, terahertz waves combine the penetrating properties of radio waves with the straight-line propagation of light. Because they exhibit unique absorption characteristics for polymers, moisture, and other substances, they are expected to be used in non-destructive testing without ionizing radiation, medical and healthcare applications, and high-resolution radar sensing. However, conventional terahertz systems require large equipment and high implementation costs, making it difficult for new companies and research institutions to enter the field or pursue commercialization.

Since the late 2000s, ROHM has engaged in joint research with the Institute of Science Tokyo, Osaka University, and many other universities and research institutions to develop THz wave oscillation and detection devices using RTDs. In 2024, ROHM began offering samples of 1st Generation products, achieving substantial downsizing and cost reduction compared with conventional methods.

What’s New in the 2nd Gen Wave Oscillation Device?

To address the growing demand for improved signal quality in application development, ROHM has now developed a 2nd Generation terahertz wave oscillation device. The device maintains the same compact 0.5×0.5mm chip size as the 1st Generation product while adopting an internal structure that enables higher output power. As a result, output power has been increased to approximately 4 times that of the 1st Generation product, reaching a maximum of 40µW. The higher output power improves the detectability of THz waves after transmission through or reflection from target objects – making the device well suited for applications such as sensing and imaging that require high signal quality.

The device is mounted in the same 4.0×4.3mm PLCC package, maintaining the industry’s smallest footprint. This enables evaluation environments to be built even in space-constrained settings. In addition, compared with other THz generation methods, the RTD approach generates less heat and consumes less power. This reduces application development load at both companies and research institutions. Sales of the RTD-EVK-G2 evaluation kit, which includes samples of the 2nd Generation wave oscillation device, are scheduled to begin later this year at $3,300 per set.

By enabling evaluation at a lower cost than other methods, the kit supports the development of a wide range of applications. This includes non-destructive testing; imaging and sensing in the medical and healthcare sectors; material identification; and moisture detection. ROHM will also continue sales of 1st Generation devices for applications that prioritize low power consumption. For further information, please contact a sales representative or visit the contact page on ROHM’s website. Purchase of the evaluation kit requires signing a non-disclosure agreement (NDA) with ROHM.

Expanding THz Wave Applications

Sharing his views on the development, Professor Safumi Suzuki, Laboratory for Future Interdisciplinary Research of Science and Technology, Institute of Integrated Research, Institute of Science Tokyo, said, “Terahertz waves are expected to be applied in a wide range of fields, including non-destructive testing, imaging and sensing, and wireless communications. At the same time, commercialization continues to face major challenges, such as the need for large-scale equipment and high implementation costs.

Professor Safumi Suzuki, Institute of Integrated Research, Institute of Science Tokyo

Conventional methods for generating terahertz waves include the ‘frequency multiplication’ method. This converts the frequency of an electrical signal into an integer multiple for output. The “photomixing” method that produces terahertz waves from the difference frequency created when two laser beams of different wavelengths are mixed in a photo-mixer. Both approaches necessitate large or medium sized costly equipment to generate terahertz waves.

“The RTD terahertz wave device, developed through many years of joint research with ROHM is compact, power saving, and does not require cooling. It can also be introduced at low cost, helping companies and research institutions begin terahertz wave research. With the launch of the 2nd Generation device featuring significantly improved oscillation output, I expect development of applications requiring higher signal quality to accelerate,” added Suzuki.

“With the launch of RTD-EVK-G2, we expect to make another major step forward toward the practical implementation of terahertz technology. Feedback from users of the 1st Generation device revealed strong demand for higher-output devices. With this 2nd Generation product, we have succeeded in increasing oscillation output to approximately 4 times that of the 1st Generation device while maintaining a compact size, bringing us closer to meeting those needs. Terahertz technology is steadily progressing toward real-world implementation,” mentioned Ken Nakahara, General Manager of ROHM Research & Development Center, ROHM Co., Ltd.

The Smallest Terahertz Wave Device Now Becomes Smarter!

Innovative oscillation and detection devices have been ROHM’s forte. Readers will remember that last year, the company introduced the first generation of the industry’s smallest THz wave oscillation and detection devices utilizing RTDs. Its extremely compact size, typically less than one-thousandth that of conventional oscillators, enabled this innovation to ensure easy development of terahertz wave applications, even in space-constrained environments.

By positioning the antenna surfaces of the oscillation and detection devices facing each other 10mm apart, a dynamic range of 40dB (typ.) was easily achievable. Both oscillator and detector maintain a drive power consumption of 10mW (typ.), while their ability to oscillate and detect terahertz waves at room temperature eliminates the need for cooling equipment required with some conventional methods. These compact, power-saving devices are almost unaffected by the operating environment, enabling use in a wide range of applications.

Ken Nakahara, General Manager of ROHM Research & Development Center

Going forward, ROHM intends to continue diversifying the possibilities for THz wave application development and contribute to the early commercialisation and real-world implementation of terahertz technology. This will help accelerate its deployment across a broad range of industries. “ROHM will continue working together with customers, partners, universities, research institutions, and government agencies to support the development of terahertz wave applications and contribute to the realization of a sustainable society,” averred Nakahara.

The post ROHM’s 2nd-Gen Terahertz Wave Oscillation Device Delivers 4 Times Higher Output Power appeared first on ELE Times.

As automotive, AI/data centre, networking and industrial systems rapidly transition to 48V power architectures to improve efficiency and support higher power demands, designers require more than visibility into instantaneous voltage and current conditions. They also need systems that can track energy consumption over time and respond to changing power conditions. To address these requirements, Microchip Technology has introduced the PAC1761 and PAC1861 families of 65V energy-aware digital power monitors. The devices combine accumulated energy-measurement capabilities with 65V measurement headroom and transient spike protection to support efficient and resilient 48V power architectures.

The move to 48V power architectures requires digital power monitors to provide additional operating margin, including up to 65V measurement capability and 75V spike protection to ensure transient survivability. The PAC1761 and PAC1861 devices add intelligence to these capabilities, enabling real-time responses to energy-usage dynamics based on accumulated power measurement data.

“The industry conversation is shifting from measuring power at a single point in time to understanding and responding to energy behavior across an entire system and its lifecycle,” said Keith Pazul, vice president of Microchip’s mixed-signal linear business unit. “The PAC1761 and PAC1861 families are designed to help customers build better performing and more reliable 48V systems that can measure instantaneous conditions and understand energy consumption and availability over time. These scalable, low-power solutions reduce monitoring overhead and include pin-compatible package options that improve source flexibility while reducing design risk.”

Microchip’s digital power monitoring devices feature programmable alerts for voltage, current and power excursions, step-limit detection to identify sudden load changes, and configurable accumulated-energy thresholds that enable proactive system management based on both instantaneous and long-term power behavior.

Target applications include automotive, AI/data center, networking, industrial, server, telecom/Power over Ethernet (PoE) and 48V power distribution systems. The 12-bit PAC1761 and 16-bit PAC1861 options are available in VDFN-8 (similar to SOT23-8), VDFN-10 and MSOP-10 packages including automotive-orderable variants. Pin-compatible options can reduce redesign risk, shorten qualification cycles and give customers flexibility to move between devices as requirements, availability, cost or performance change.

Development Tools

Development support includes evaluation board EV12R33A, a Python Command Line Interface (CLI) with library, Linux driver and generic C library with multiple MCU code examples.

The post Microchip Launches 65V Digital Power Monitors for Smarter 48V Power Systems appeared first on ELE Times.

Battery-swapping technology allows electric heavy trucks to replace a drained battery placed between the frame rails with a fully charged one at a charging station in just 5 to 10 minutes. Unlike conventional plug-in EV trucks, battery-swapping vehicles are designed with modular and removable battery packs along with the mechanical, electrical and communication interfaces required for rapid battery exchange.

Automated swapping equipment can then remove the depleted pack and install a charged one. Current heavy-duty EV examples in India demonstrate the growing adoption of this approach, with some systems completing a battery swap in less than five to seven minutes.

This battery-swapping technology is gaining attention in India’s EV transportation sector as manufacturers look for a better option to reduce electric vehicle charging downtime. It also provides an advantage of lower upfront costs because the battery is owned by a battery-swapping operator, allowing the customer to pay for battery use through a subscription.

This technology is now moving beyond the deployment phase towards a wider infrastructure network. In July 2026, Energy In Motion (EIM) and Hindustan Petroleum Corporation Limited (HPCL) announced plans to develop fast-charging and battery swapping stations for heavy EV trucks at specific HPCL petrol pumps or service stations. The partnership company (EIM) will establish swap-and-charge hubs along freight corridors including Mumbai-Pune, Delhi-Jaipur and Chennai-Bengaluru over the next 18 to 24 months.

The implementation of battery-swapping at a wider scale demonstrates that India is adopting modern technologies to provide faster and efficient charging solutions to the EV industry. The adoption of this technology at a very large scale will depend on several factors such as battery standardisation, station availability, interoperability, fleet economics, and the development of reliable freight-corridor infrastructure.

The post Battery Swapping for E-Trucks Gains Momentum: India Builds Heavy-Duty EV Infrastructure appeared first on ELE Times.

​The demand for electric vehicles is continuously rising in India. Government and charging companies are making continuous efforts to make charging easy for consumers by expanding charging infrastructure and improving charging efficiency. But increasing the number of chargers alone is not sufficient to provide a reliable charging experience.

A new report from the Institute for Energy Economics and Financial Analysis (IEEFA) found that charger reliability, interoperability, charging cost, home-charging challenges and delays in grid connection are rising problems affecting EV charging in India. The report was published on September 16, 2026.

In the early stages of EV adoption, vehicle range was a major focus for manufacturers and consumers. As EV sales and charging infrastructure continue to expand, attention is increasingly turning​to the reliability and accessibility of charging infrastructure. A charging station is useful only when it is operational and available when an EV user needs it.

Network interoperability is another growing concern, as different charging networks may require separate apps, accounts or payment systems, making it less convenient for users to access and pay for charging across different locations. IEEFA has identified charger reliability and interoperability among charging networks as key factors that need to be addressed to improve India’s EV charging experience.

As India’s charging network continues to grow, the next stage of development will therefore depend not only on deploying more chargers but also on improving their reliability, interoperability, affordability and integration with the electricity grid.

The post EV Charging in India: Reliability and Interoperability Emerge as Key Challenges appeared first on ELE Times.

As manufactures and battery material companies are searching for increasing energy density and improve charging performance in electric vehicles, silicon-based anode technology that replace traditional graphite parts with silicon-based materials is gaining momentum in the electric vehicle (EV) battery industry. The advantage of adopting these technologies is that it holds significantly more lithium ions (up to 10 times more lithium per gram than standard graphite) to boost energy storage of an anode without increasing its size.

Although, this technology suffers from big challenges such as silicon undergo tremendous expansion once it absorbs lithium during charging. This expansion can destroy the anode and cause capacity loss over repeated charging cycles. Researchers have come up with the solution of using silicon-carbon composites to overcome this problem. By combining silicon with carbon based materials can accommodate the expansion to preserve the anode stability.

The technology has new completed its testing phase and is new ready to be implement toward large-scale manufacturing. Group14 Technologies, an American battery technology company, in March 2026 announced that its South Korea battery- material plant for silicon batteries has started production of its SCC55 material at the scale needed for EV batteries. The plant can produce up to 2,000 tonnes of silicon battery material per year, which should amount to about 10 GWh of energy-storage capacity annually once production reaches its planned level.

Australia is another major supporting commercialisation of this silicon-adopting material for energy storage. The Australian Renewable Energy Agency (ARENA) announced an award of $45 million to silicon battery technologies to build a commercial scale facility for advanced silicon-carbon battery material.

These developments put silicon-carbon anodes closer to commercialisation. If the manufacturers can overcome the issues of cost, cycle life, expansion and manufacturing scale, then the technology could contribute to higher battery energy density in future EV batteries, while allowing for faster charging.

The post Silicon-Carbon Anodes Move Toward EV-Scale Production for Higher Energy Density appeared first on ELE Times.

With the rise in the implementation of software technologies in Electric vehicles, the transition towards Software-Defined Vehicles (SDVs) is changing how electric vehicles are designed. Technologies in software-defined vehicles such as advanced automotive semiconductors, edge artificial intelligence (AI) and centralised computing are becoming key concepts in designing future transportation vehicles.

During electronica India 2026 held at Bangalore International Exhibition Centre (BIEC), Renesas Electronics showcased technologies related to SDVs, edge AI, EV charging and intelligent mobility. These technologies highlight the growing role of semiconductor-based computing in designing next-generation vehicles. At the event, Renesas demonstrated its newly designed 3nm multi-domain automotive SoC, the R-Car Gen 5 platform, highlighting features such as advanced driver assistance systems (ADAS), digital cockpit technologies and connected-vehicle solutions providing personalised functions and voice interfaces.

The platform combines high-performance automotive computing with AI capabilities and supports software-defined vehicle architectures. Edge Intelligence was another area of interest, where AI processing is being executed with the help of the vehicle’s sensors and systems instead of depending on cloud interface. Renesas demonstrated applications that support AI vision, autonomous and assisted driving for the driver, and embedded intelligence.

Edge AI can result in faster local responses compared to cloud connectivity and reduce the amount of sensor data that needs to be transmitted to external system. As EV architectures shift towards software-defined systems, the use of advanced automotive system-on-chip (SoC) platforms, edge AI, power semiconductors, and software platform will increasingly play an important role in vehicle computing, charging, connectivity, and smart mobility.

The post Software-Defined Vehicles and Edge AI Reshape Next-Generation EV Architecture appeared first on ELE Times.

SEMICON India 2026, the fifth edition of India’s flagship semiconductor conference, concluded on September 19 at Yashobhoomi, New Delhi, highlighting the country’s growing capabilities across the global semiconductor value chain. Held from September 17 to 19 under the theme “Silicon to Systems: Building the Ecosystem,” the three-day event brought together semiconductor companies, policymakers, investors, academia and start-ups.

The event featured more than 600 exhibitors, including around 300 international participants, with representatives from 52 countries and more than 150 speakers. Six country pavilions representing Japan, South Korea, Malaysia, the Netherlands, Singapore and Sweden, along with 12 state pavilions, showcased capabilities across different areas of the semiconductor ecosystem. The event recorded 51,656 registrations and around 40,000 cumulative footfall.

Prime Minister Narendra Modi inaugurated SEMICON India 2026 highlighting India’s progression from policy discussions and project planning to commercial semiconductor production. During the inauguration, the Prime Minister virtually inaugurated commercial production lines at CDIL Semiconductor in Mohali for discrete semiconductor devices and Suchi Semicon in Surat for semiconductor packaging. The two facilities added to India’s operational commercial semiconductor units under the Semicon 1.0 programme.

As a major outcome of SEMICON India 2026, a total of 56 MoUs, announcements and strategic initiatives were announced across areas including semiconductor design, fabrication, advanced packaging, equipment, materials, power electronics, AI, R&D, startups and talent development.

The post SEMICON India 2026 Concludes at Yashobhoomi, Showcasing India’s Growing Semiconductor Ecosystem appeared first on ELE Times.

Due to massive pool of specialised VLSI (Very Large Scale Integration) engineers, large number of Global Capability Centre (GCCs) presence and ongoing government support, India currently accounts for nearly 20% of the world’s semiconductor design workforce. This number highlights the India’s increasing role in global chip design and research. The statement of accounting 20% global workforce in semiconductor design was made by S. Krishnan, the MeitY Secretary on the side-lines of SEMICON India 2026 in New Delhi.

The government is prioritising the development of semiconductor design talent, said S. Krishnan. He said an ongoing programme is focused on training around 85,000 semiconductor design engineers, while skill-development efforts are also being expanded across the semiconductor value chain, with a strong focus on supporting semiconductor manufacturing in India.

The semiconductor design workforce will play an important in strengthening India’s position in the global semiconductor ecosystem. According to government data, India holds 7% of the world’s semiconductor-related Global Capability Centres (GCSs) along with Indian engineers continue to contributing to chip design, fabrication, verification and testing activities.

The government is taking action to move beyond design and improve semiconductor ecosystem by covering fabrication, advanced packaging, assembly and testing, semiconductor equipment and materials, research and development (R&D), and talent development. The recent organised event Semicon 2.0 has an outlay of ₹1,27,500 crore and is structured around six pillars which include design, machine, materials, advanced packaging, additional fabs, research, and talent.

There are different schemes supported by the government body encouraging semiconductor design which include Design Linked Incentive (DLI) Scheme and the Chips to Startup (C2S) Programme. The focus of these programmes is to train around 85,000 semiconductor design engineers. The initiatives are also aimed at strengthening India’s domestic chip-design capabilities and building a stronger semiconductor design ecosystem.

The post India Accounts for 20% of Global Semiconductor Design Workforce, Says MeitY appeared first on ELE Times.

India continues to focus on raising domestic value addition and further deepening domestic manufacturing in electronics industry. Moving beyond large-scale assembly towards deeper manufacturing and stronger local supply chains, S. Krishnan, the Secretary of the Ministry of Electronics and Information Technology (MeitY) made the statement that India is targeting 35-40% domestic value addition in mobile-phone manufacturing, up from the current level of about 22-23%. To achieve this number, different government schemes are giving support such as India Semiconductor Mission (ISM), mobile manufacturing, the Production Linked Incentive (PLI) for electronics hardware and the Electronics Component Manufacturing Scheme (ECMS).

The Electronics Component and Manufacturing Scheme (ECMS) is expected to play a major role by focusing on deep component-level manufacturing rather than basic assembly. Key areas include printed circuit boards, passive components, electrochemical components, subassemblies, camera module, optical transceivers, and critical equipment.

The government aims to wider the development of India’s semiconductor ecosystem by expanding capabilities across components, semiconductor manufacturing and other parts of electronics value chain. ECMS is designed to integrate Indian manufactures with global value chains and ISM supports semiconductor design, fabrication, advanced packaging, equipment and materials.

The 40% target in domestic manufacturing does not means that forty percent of the electronic devices to be made in India. It means if a device is selling in India, then its forty percent value must be manufactured within the country. This target reflect India’s deepen participation in global value chains by moving beyond final assembly, creating a deeper supplier ecosystem, reduce dependence on imported components, and moving towards complete manufacturing location. This will allow Indian factories to source more inputs locally while maintaining competitive cost, quality and scale.

The post India Targets 40% Domestic Value Addition in Electronics Manufacturing appeared first on ELE Times.

On 22 September 2026, North Korea said it had tested a new weapon system that it claimed utilised modern defence technology. State media images seem to indicate that North Korea tested an improved Hwasongpho-11Ma short-range ballistic missile capable of carrying a manoeuvrable hypersonic glide vehicle. South Korea’s military identified two missiles fired from the Wonsan area on 20 September, which it said travelled 450 kilometres and 600 kilometres before crashing into the sea.

North Korean reporting gave other performance numbers that could not be checked. A hypersonic glide vehicle is a rocket disseminated missile released from a booster that then glides course toward its target at very high speeds and altitude. Its capability to change course after launch presents a challenge to tracking and destroying it because of the ballistic predictability for defenders.

Latest test indicates progress by Pyongyang in enhancing the lethality and penetrability of its short-range missile arsenal. Such weapons, if employed, are likely meant to saturate regional missile-defence systems through rapid, highly manoeuvrable and possibly erratic flight trajectories. Still, outside analysts are sceptical of North Korea’s claims: briefly achieving hypersonic speed is one thing; sustained hypersonic manoeuvring-especially under realistic operational conditions- is another.

Additional launches will be necessary to determine the missile’s precision, guidance accuracy and ability to defeat existing missile defences. The missile test, however, inevitably heightens South Korea’s, Japan’s and the United States’ urgency to enhance regional tracking and interception capabilities.

The post North Korea Tests New Manoeuvrable Missile System appeared first on ELE Times.

Lockheed Martin won a US Army contract worth up to US$1.2 billion for production of the Increment 2 configuration of the PrSM, or Precision Strike Missile. The contract announced on 21 September 2026 supports the Army’s effort to succeed the legacy Army Tactical Missile System. PrSM is a surface-to-surface precision missile launched from the M142 High Mobility Artillery Rocket System and the tracked M270 Multiple Launch Rocket System.

Its more compact size will enable the two launch pods to carry two PrSM rounds per pod as opposed to one ATACMS missile, which could expand the number of precision weapons available to a firing battery. The missile family is being fielded in subsets (increments) to allow the Army to incrementally add improved systems without replacing the entire missile.

Increment 2 targets increasing the PrSM’s targeting ability, which is necessary to address the US military’s need to engage mobile maritime and land-based threats. This is obviously related to the countries’ operations in the Indo-Pacific, where ground forces are expected to engage enemy ships, air-defence facilities, and command and control facilities at extended distances. Some technical details remain classified.

The award further indicates that the US Army aims to move from limited early production toward establishing a larger manufacturing base. Increased production capacity has become a top priority as recent conflicts have highlighted how rapidly precision-missile stockpiles can be depleted in prolonged campaigns.

The post Lockheed Martin Wins $1.2-Billion US Army PrSM Contract appeared first on ELE Times.

Renesas Electronics Corporation on 24th September, 2026, announced the SLG46801, the industry’s smallest GreenPAK configurable mixed-signal device, available in both WLCSP and STQFN packages. The 9-ball WLCSP measures just 1.155 mm × 1.155 mm and combines an ultra-small footprint with multi-time programmability, helping designers reduce PCB space in compact products such as smart rings, smartwatches, fitness bands, VR glasses and portable electronics.

Consumers are demanding smaller, more feature-rich products, while designers need to add functionality while reducing component count, PCB area and bill-of-materials (BoM) costs. The SLG46801 addresses these requirements by combining commonly used analog, timing and logic functions in a compact, low-power device. It can complement an MCU or replace multiple discrete components, helping designers reduce board space and simplify designs.

“Designers are being asked to integrate more functionality into increasingly compact products without increasing system cost or development effort, while also reducing power consumption.” said Jason Kim, Vice President and General Manager of the Core Analog Division at Renesas. “The SLG46801 expands our GreenPAK portfolio with an ultra-compact WLCSP option and flexible in-system configurability, helping customers create smaller, more feature-rich products and implement updates even after deployment.”

The SLG46801 integrates two high-speed analog comparators, configurable lookup tables, counters and delays, 10 kHz and 25 MHz oscillators, voltage-tolerant GPIOs and an I²C-compatible serial interface. These resources support sensing, control, glue logic, timing and system housekeeping functions in applications across consumer electronics, handheld devices, smart-home systems, networking and communications, computing and storage, industrial control and IoT sensor nodes.

In addition to the 9-ball WLCSP, the SLG46801 is available in a 12-lead, 1.6 mm × 1.6 mm × 0.55 mm STQFN package. The two package options allow customers to balance minimum board area with additional GPIO availability and industrial package preferences. The device also offers one of the lowest cost per GPIO in the GreenPAK family.

Renesas is a leader in configurable mixed-signal technology, with more than four billion GreenPAK devices shipped worldwide. GreenPAK ICs enable designers to combine analog and digital system functions in small, low-power devices that can be configured using the Renesas Go Configure Software Hub. The free GUI-based development environment helps customers develop custom hardware functions without the need for additional discrete components or complex firmware development.

The SLG46801 includes multi-time programmable non-volatile memory that can be configured in system through its I²C interface. This allows customers to implement bug fixes, configuration changes and product upgrades after the device has been integrated into the end application, helping reduce redesign cycles and additional hardware revisions.

The device supports operation and programming across the full 1.71 V to 5.5 V supply range—the widest operating and configurable range among MTP GreenPAK devices. GPIO pins can also be repurposed dynamically for the I²C interface, maximizing flexibility in designs with limited pin availability. Optional CRC-8 and read-back protection support more robust and controlled configurable implementations.

The post Renesas Introduces Smallest GreenPAK Configurable Mixed-Signal IC with Multi-Time Programmability appeared first on ELE Times.

Cadence on September 24, 2026, announced a new agent for the Cadence ChipStack AI Super Agent that automates front-end digital design and verification, covering power, performance and area (PPA)-driven spec-to-RTL generation, RTL analysis and refinement through natural language prompts. Building on the industry’s first agentic workflow for front-end design and verification announced in February 2026, the RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug to high-quality RTL creation and optimization. In early evaluations, the RTL Generation Agent delivered an average 24% reduction in area and 18% reduction in power compared with pure foundation model code generation, while ensuring 100% functionally accurate RTL, according to Cadence.

Building on the industry’s first agentic workflow for front end design and verification announced in February 2026, this RTL Generation Agent extends the ChipStack AI Super Agent from autonomous verification and debug into high quality RTL creation and optimization.

“These latest agentic AI advancements take us from AI assisted tools to coordinated agentic workflows that behave more like virtual design engineers with expert-level command of the underlying technologies,” said Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “By pairing agentic automation of spec-to-RTL and RTL refinement with our proven implementation and signoff engines, we enable customers to achieve better design outcomes with higher productivity and stronger correlation across the design flow, further extending Cadence’s leadership in AI driven, end to end chip design.”

Cadence’s transformational approach to applying agentic AI to engineering design is founded on a hierarchy of solutions—super agents orchestrate task-specific agents, which in turn use trusted electronic design automation (EDA) software, optimized for agentic workflows. The new RTL Generation Agent converts high level specification into production ready RTL optimized for PPA.

Customer Validation from Honda

Early collaborations with Honda R&D demonstrate how these agentic AI capabilities translate into real world PPA and productivity gains on next generation SoCs.

Honda is evaluating the RTL Generation Agent on advanced automotive SoCs, where safety critical requirements and tight power and cost envelopes demand highly optimized RTL.

“As a key enabler of Software-Defined Vehicles (SDVs), AI technology for autonomous driving is advancing rapidly. However, the long development cycle of SoCs remains a major challenge. With the Cadence ChipStack AI Super Agent’s RTL Generation Agent and AI-powered automation, Honda R&D is working to improve productivity from specification through RTL development,” said Tomoya Nishino, chief engineer and general manager, Digital Engine Development Division, SDV R&D Center, Honda R&D Co., Ltd.

Smarter RTL Updates and Early PPA Insight

In addition to new RTL creation within the RTL Generation Agent, Cadence is introducing technology for design updates to existing RTL based on new requirements. This RTL upgrade flow brings AI automation to accelerate RTL revision, enabling customers to rapidly adapt legacy RTL to new architecture requirements, new PPA targets and new functional requirements. Engineers describe changes at a high level, and the agents carry out the updates while analyzing and verifying PPA and functionality.

Advancing Cadence’s Agentic AI Vision

These enhancements build on Cadence’s “Design for AI and AI for Design” strategy highlighted at CadenceLIVE and Computex, further extending the company’s leadership in AI driven chip design. From the initial ChipStack AI Super Agent launch through June’s announcement of the industry’s first fully autonomous virtual engineer for chip design, and now today’s RTL Generation Agent, Cadence continues to expand the scope of agentic workflows across the design stack. Together with the broader ChipStack, InnoStack and ViraStack AI Super Agent portfolio, they advance a scalable platform that applies AI across digital, analog and verification domains.

The post Cadence Expands ChipStack AI Super Agent with AI-Powered RTL Generation and PPA Optimization appeared first on ELE Times.

From discovering new component vendors and evaluating production equipment to addressing gaps in domestic manufacturing, electronica India and productronica India 2026 in Bengaluru were marked by three days of intensive commercial and technical engagement across the electronics value chain.

Both trade fair was organised by Messe Muenchen India from 16–18 September 2026 at the Bangalore International Exhibition Centre (BIEC). The co-located trade fairs welcomed 793 exhibitors and 52,411 business visitors. The exhibition occupied 60,000 square metres and featured exhibiting companies from over 30 countries. Together, visitors, exhibitors, speakers and industry delegations represented more than 50 countries.

The event covered electronic components, embedded technologies, printed circuit boards, electronic manufacturing services, production machinery, automation, testing, inspection and related manufacturing solutions. Its breadth allowed decision makers to examine several stages of electronics production within a single business platform.

The Bengaluru edition was inaugurated by Shri M. B. Patil, Hon’ble Minister for Large and Medium Industries and Infrastructure Development, Government of Karnataka, and Mr. Hiroshi Nawata, Consul-General of Japan in Bengaluru.

Industry attention shifts from capacity to capability

The conversations across the exhibition indicated a clear industry priority: increasing manufacturing capacity must now be supported by stronger capabilities in components, equipment, quality, testing, design and production processes.

Manufacturers attending the event evaluated technologies against practical requirements such as application suitability, production output, process control, inspection accuracy, automation and supplier support. Component and equipment providers, in turn, gained direct exposure to the requirements emerging from Indian electronics manufacturers.

Bhupinder Singh, President – IMEA, Messe München, and CEO, Messe Muenchen India, said, “The value of a trade fair is ultimately determined by the quality of the business conversations it enables. In Bengaluru, we saw manufacturers arriving with specific sourcing, production and technology requirements. Suppliers were able to respond with relevant capabilities and technical expertise. This level of engagement shows that India’s electronics sector is progressing from broad expansion plans towards more defined manufacturing decisions.”

The Buyer–Seller Forum supported this process through 3,225 focused B2B meetings over three days with 645 unique buyer companies and 1,682 VIP buyers. The discussions gave both sides a structured setting to examine technical requirements, supplier capabilities and potential areas of cooperation.

The exhibition floor was complemented by the Podcast Studio, Executive Club Lounge and dedicated networking areas, creating additional settings for conversations among business leaders, technology specialists and industry representatives.

International participation reflects demand for closer market engagement

Companies from Germany, China, France, Italy, the United Kingdom, Japan, Israel, the United States, Korea and other markets participated in the Bengaluru edition.

Dedicated pavilions from Germany, Japan, Taiwan and China brought together technologies and suppliers from their respective electronics industries. The Japan Pavilion was organised in partnership with the Japan External Trade Organization (JETRO), while the Taiwan Pavilion was presented with the Taiwan Electrical and Electronic Manufacturers’ Association (TEEMA).

Rather than serving only as international showcases, the pavilions enabled participating companies to hold direct discussions with Indian buyers, understand local manufacturing requirements and explore potential commercial relationships.

Dr. Reinhard Pfeiffer, CEO, Messe München GmbH, said, “Global electronics companies are increasingly in need of a closer understanding of India’s manufacturing requirements and business environment. The Bengaluru edition gave international suppliers direct access to the companies investing in production, sourcing and technology adoption. For Indian participants, it provided an efficient way to compare the capabilities of several established technology markets.”

Conference discussions examine the foundations of competitive manufacturing

The accompanying programme moved the industry conversation beyond manufacturing volume to the capabilities required for long-term competitiveness.

The India Electronics Conclave comprised 14 conferences at the BIEC Conference Centre. Across the event, approximately 150 speakers participated in 18 supporting programmes covering electronics policy, capital goods, artificial intelligence, exports, free trade agreements, printed circuit boards, flexible electronics, standards, compliance and power electronics.

The programme included the eFuture Conference with Avanteum as Knowledge Partner, CEO Forum with ELCINA, Industrial Electronics & Capital Goods Summit 2026 with ICEA, Exports and FTAs: Electronics Sector with MEDEPC, Bharat PCB Tech Conference with ELCINA, VDMA Symposium and OE-A Symposium on Flexible Electronics.

Reinforcing its role as a platform for industry dialogue and future-focused thinking, electronica India and productronica India 2026 hosted the launch of MMI and Avanteum Advisors’ e-paper, eFuture 2035: Engineering India’s Next Electronics Revolution. The report outlines the strategic shifts and opportunities that could shape India’s electronics manufacturing and its position in the global value chain over the next decade.

Technical learning was addressed through the IEEE Standards Workshop on EMI/EMC Compliance and the Power Electronics & Power Supply Design Workshop.

“India’s electronics industry is entering a phase where competitiveness will be measured by consistency, reliability, process maturity and the ability to meet global customer expectations. Forums at electronica India and productronica India 2026 helped bring sharper attention to these priorities by connecting industry leaders, technology providers and policy stakeholders around the practical capabilities required to move from capacity creation to globally competitive manufacturing,” said Rajoo Goel, Secretary General, ELCINA.

The Industrial Electronics & Capital Goods Summit 2026, organised with the India Cellular & Electronics Association, examined the role of domestically available equipment and production technologies in supporting manufacturing growth.

Shri Pankaj Mahindroo, Chairman, India Cellular & Electronics Association (ICEA), said: “As India’s electronics manufacturing ecosystem continues to expand, reliable access to advanced equipment, automation, testing and quality-control technologies will be critical to sustaining growth. The summit provided an important platform for industry and policymakers to examine these requirements from the perspective of real-world production needs and identify the areas where India’s capital-goods and technology ecosystem must continue to evolve.”

The OE-A Symposium brought international and Indian experts together to consider the commercial potential of flexible and printed electronics across mobility, healthcare, energy, consumer products and industrial applications.

Sandip Roy, General Manager, VDMA India, said, “The opportunity in flexible electronics depends on connecting research and  technology development with viable industrial applications. The symposium created a useful exchange between international specialists and Indian stakeholders exploring how these technologies can move towards adoption and commercial deployment.”

Speakers participating in the supporting programme said that the value of the discussions lay in bringing policy, manufacturing experience and technical expertise into the same forum.

“The session provided an opportunity to examine the emerging power paradigm in the context of the decisions manufacturers are making today. The discussion highlighted the immediate challenges facing the industry, while also bringing into focus the technologies and capabilities that need to be developed to meet the evolving demands of power electronics over the coming years,” said Amit Kumar, Vice President & Business Unit Head – Metering and Protection Systems, Schneider Electric India.

“India has a significant opportunity to strengthen its position in next-generation PCB design to manufacturing, but realising this potential will require closer collaboration among industry, government, academia and technology providers. The event brought these stakeholders together for a practical and meaningful exchange of perspectives on bridging the journey from design to manufacturability,” said Savita Ganjigatti, Sr. Vice President – Engineering & Operations, Sienna ECAD Technologies (An Avalon Group Company), during the session Engineering for Tomorrow: Design to Manufacturing.

Emerging engineers work on industry-defined challenges

The 2026 edition also introduced formats designed to connect emerging technical talent with practical industry problems.

Organised with HackCulture and supported by presenting partner DigiKey, the electronica India Tech Challenge featured a prize pool of ₹5 lakh. Participating teams developed responses to defined technology challenges and presented their work during the Hackathon Demo Day, where the three winning teams were recognised for the originality, technical merit and practical relevance of their solutions.

The AI Buildathon, conducted by Sarvam AI, and AI Masterclass conducted by GrowthX, explored the application of artificial intelligence to practical use cases. A Hand Soldering Skill Test brought attention to production skills at the operator level, while an industrial visit to the Central Manufacturing Technology Institute provided exposure to an established manufacturing and engineering environment.

At electronica India 2026, the Taipei Computer Association and IIIT-Bangalore signed an LoI to advance Taiwan–India collaboration across AI, electronics, smart manufacturing, smart cities and cybersecurity.

Together, these initiatives connected the event’s wider manufacturing agenda with engineering skills, applied problem-solving and future workforce requirements.

‘India’s Powerplay in Electronics’ reaches the industry nationwide

The Bengaluru edition was presented under the theme “India’s Powerplay in Electronics.” Cricket icon KL Rahul served as Brand Ambassador for the visitor campaign, which ran across outdoor, digital and print media through September 2026. At the event, the campaign shifted from a public-facing message to a physical demonstration of the breadth of companies, technologies and expertise in India’s electronics industry.

Exhibitors and buyers report focused business engagement

Exhibitors highlighted the quality of conversations with manufacturers, sourcing teams and technology decision-makers attending the Bengaluru edition.

“productronica India 2026 gave us a strong platform to showcase advanced technologies with our global partners. Unveiling Fuji’s CLT-FG for the first time outside Japan was the main highlight. The strong industry response reinforced the growing demand for advanced manufacturing solutions in India and opened new opportunities for collaboration,” said Soni Saran Singh, Founder, MD & CEO, NMTronics India Pvt. Ltd.

“India’s electronics ecosystem is evolving rapidly, with growing focus on technology adoption, local manufacturing and stronger supply chains. The exhibition enabled meaningful conversations around these priorities and how we can support customers across the electronics value chain, from design to delivery,” said Haresh Abichandani, Managing Director, Millennium Semiconductors.

“Visitors came with defined requirements and a clear understanding of the capabilities they wanted to evaluate. This allowed our discussions to move quickly from general enquiries to applications, technical specifications and potential projects,” said Nandini Balasubramanian, Director, Tescom Pvt. Ltd.

Buyers valued the opportunity to compare suppliers and technologies against specific production and sourcing requirements.

“We attended the exhibition with clearly defined requirements for passive components used in electronic control boards. The event provided an excellent opportunity to meet multiple relevant suppliers under one roof, enabling us to compare their technical capabilities, product offerings, quality standards, and application expertise. The interactions were valuable in identifying potential suppliers for further technical evaluation and future collaboration,” said Jagadeesha M H, Team Lead, R&D, Delta Electronics India Pvt Ltd.

“Our priority was to understand which technologies could support improvements in production/quality/testing/automation. The live discussions gave us information that would have taken considerably longer to gather through individual supplier meetings,” said Venkata Ravindra, Head R&D, SFO Technologies.

“The event was the seventh in a row for me. This time, I felt that the combination of Indian and international suppliers gave our team a wider view of the available options. We have shortlisted potential partners and will continue the technical and commercial discussions initiated at the event. It was well organized this time and thanks to the team for making it better every year,” said Anil Krishna K S, Associate Director – Procurement & Supply Chain, Pioneer India Electronics Pvt Ltd.

The trade fairs were supported by the Government of Karnataka, with ELCINA as Partner Association and ICEA as Industry Partner. ELCIA, CLIK, GEZIA and AIEA participated as Supporting Associations; MEDEPC and CEAMA as Strategic Partners; and  VDMA, IEEE and OE-A as Conclave Partners.

Yeemak and Delvitech were Gold Partners, while Mouser Electronics participated as Registration Partner. JETRO and TEEMA supported the Japan and Taiwan pavilions, respectively.

Expanded national format proceeds to Delhi-NCR

The conclusion of the Bengaluru edition completes the first year of the trade fairs’ expanded national model.

Previously conducted in alternate years in Noida and Bengaluru, electronica India and productronica India moved to annual editions in both markets in 2026. The change represents 50 percent growth under the new format and provides more regular access to the electronics manufacturing regions of northern and southern India.

The next edition will be held from 28–30 April 2027 in Delhi-NCR.

The programme will mark the launch of Defence Electronics NEXT, creating a dedicated platform for technologies, capabilities and partnerships supporting India’s defence electronics ecosystem. It will also maintain a strong focus on printed circuit boards through BPCA and on the semiconductor value chain through the India Semiconductor Conclave.

Supported by the Uttar Pradesh Host State Partnership, these initiatives align with the Government of Uttar Pradesh’s investment priorities in defence electronics, PCBs, semiconductors and advanced manufacturing. Together, they will connect industry, government and technology stakeholders around sectors critical to India’s electronics manufacturing ambitions.

The post Electronica India and Productronica India 2026 Conclude in Bengaluru with 793 Exhibitors and 52,411 Business Visitors appeared first on ELE Times.

​To strengthen India’s semiconductor manufacturing ecosystem across different stages of the value chain, Tata Electronics signed seven Memorandums of Understanding (MoUs) with global companies and Indian institutions during SEMICON India 2026, held in New Delhi from September 17 to 19. The collaborations cover wafer manufacturing, assembly and testing, advanced semiconductor packaging, materials, technology development, supply-chain localisation and talent development.

One of Tata Electronics’ major collaborations is with Nexperia, a Dutch semiconductor company. This partnership covers front end wafer fabrication, back-end assembly, and testing along with technology and ecosystem development. As per the partnership, Nexperia’s semiconductor products are expected to be manufactured and packaged through Tata Electronics’ facilities located in Dholera, Gujarat and Jagiroad, Assam.

Tata Electronics’ second collaboration is with Fujifilm, a Japanese multinational company, with the primary goal of developing a semiconductor materials ecosystem in the Dholera fabrication facility to enhance supply chain resilience. These materials include high-purity process chemicals and raw materials such as photoresists, CMP slurries, and thin-film solutions. Fujifilm plans to invest ₹800 crore to establish a semiconductor materials plant in Dholera to support the localisation of semiconductor materials.

Another important partnership is with Enomoto, a Japanese steel manufacturing company signed with Tata ​Electrics to strengthen its semiconductor packaging materials supply chain facility in Jagiroad, Assam. Enomoto will support Tata Electronics by providing manufacturing expertise for developing next-generation semiconductor packaging capabilities.

This collaboration of Tata Electronics with global partners reflects the effort to develop an integrated semiconductor ecosystem in India, supporting Tata Electronics’ planned fabrication facility in Dholera and semiconductor packaging facility in Assam while building domestic capabilities across the semiconductor value chain.

The post Tata Electronics Signs Seven MoUs to Strengthen India’s Semiconductor Value Chain appeared first on ELE Times.

“India presents a significant opportunity to develop globally competitive solutions that shape the future of intelligent transportation.”

The automotive industry is making a seamless transition to Software Defined Vehicle (SDV) architectures and technology providers are gearing up for exciting times ahead! In an exclusive interaction with Anwesh Koley of ELE Times, Hitesh Garg, Vice President & India Managing Director, NXP Semiconductors, shared his views on SDVs and their evolution in the automotive landscape. Excerpts from the interview:

ELE Times: With car buyers becoming more concerned with comfort, connectivity, and safety than horsepower and acceleration, how does this impact the design of technological architectures in SDVs?

Hitesh Garg: Traditional automotive engineering focused on mechanical performance, but today’s buyers increasingly evaluate vehicles based on their digital experience. About 95% of Indian consumers are willing to pay for Software-Defined Vehicle capabilities, with safety, security, and continuous vehicle-health reporting emerging as key purchase considerations.  As a result, vehicles are evolving into intelligent, software-driven platforms where features can be continuously enhanced throughout their lifecycle.

NXP is powering this transition through its portfolio of automotive processors, secure connectivity, edge AI, radar, and vehicle networking solutions that help OEMs build scalable, software-defined vehicle architectures.

ELE Times: With vehicles becoming increasingly software-defined, share your thoughts on NXP’s advancements in zonal networking solutions.

Hitesh Garg: At NXP, we view zonal networking as one of the foundational building blocks for scalable SDVs. Our S32 portfolio, including the S32G vehicle network processors and S32J family of Ethernet switches, is designed to deliver the secure, deterministic, and high-bandwidth communication required for next-generation architectures.

More recently, we introduced the SAF8444 multi-gigabit Automotive Ethernet switch, enabling higher network bandwidth and lower latency to support data-intensive applications such as advanced driver assistance systems (ADAS), autonomous driving, and immersive in-vehicle experiences. Combined with Automotive Ethernet, Time-Sensitive Networking (TSN), and intelligent gateway capabilities, these solutions enable seamless communication between sensors, actuators, and centralised compute systems.

ELE Times: India is increasingly positioning itself as a design-led electronics ecosystem. In this scenario, please elaborate on NXP’s current initiatives in the development and adoption of Software Defined Vehicles.

Hitesh Garg: India plays a critical role in NXP’s global automotive R&D ecosystem. With more than 2500 employees across our centres, the recent acquisition of Kinara further strengthens NXP’s edge AI capabilities, enabling high-performance neural processing directly within the vehicle for applications such as advanced driver assistance, driver monitoring, and intelligent in-cabin experiences.

Coupled with India’s growing semiconductor ecosystem and supportive government initiatives, we see significant opportunities to collaborate with OEMs and ecosystem partners to accelerate the development of globally competitive SDV solutions.

ELE Times: Software Defined Vehicles require a fundamentally different approach to vehicle architecture. How is the industry poised to address this challenge?

Hitesh Garg: The industry is adopting standardised software platforms, service-oriented architectures, Automotive Ethernet, zonal and centralised processing to simplify integration and improve scalability. Equally important is the growing collaboration between semiconductor companies, OEMs, Tier-1 suppliers, cloud providers, and software developers to reduce development complexity and accelerate time-to-market.

ELE Times: What’s different in the current approach to designing an SDV than 3-to-5 years ago?

Hitesh Garg: Over the last few years, the industry has moved from viewing software as an enhancement to recognising it as the primary driver of vehicle innovation. Three to five years ago, software largely supported individual vehicle functions through isolated ECUs. Today, manufacturers are designing vehicles around centralised computing platforms where software defines functionality, user experience, and feature evolution throughout the vehicle’s lifecycle.

NXP is enabling this shift with our automotive processors, radar solutions, secure connectivity technologies, and vehicle networking platforms designed to support this evolution by enabling scalable compute, real-time intelligence, and continuous software innovation while meeting the stringent safety and cybersecurity requirements of modern vehicles.

ELE Times: Software seems to be enabling more variations. Are there any engineering challenges in managing and implementing this?

Hitesh Garg: The increasing software content in vehicles brings tremendous flexibility, but it also introduces new engineering challenges around functional safety, cybersecurity, software integration, and lifecycle management. As vehicle architecture becomes more centralised and software-driven, ensuring that hardware and software operate reliably, securely, and in compliance with automotive safety standards becomes critical.

ELE Times: What can automotive engineers do to balance the need for more circuitry with the requirement to limit weight, particularly in EVs?

Hitesh Garg: One of the most effective ways to achieve this is by transitioning from distributed ECU architectures to centralised and zonal architectures. Instead of connecting every sensor and actuator through long wiring harnesses, zonal architectures group components based on their physical location within the vehicle and connect them through high-speed Automotive Ethernet. This significantly reduces cable length, lowers vehicle weight, simplifies manufacturing, and improves serviceability while supporting future software-defined capabilities.

Equally important is semiconductor integration. By consolidating multiple functions into high-performance processors and highly integrated system-on-chip (SoC) solutions, OEMs can reduce component count, optimise power consumption, and improve thermal efficiency.

ELE Times: What are the barriers to SDV adoption, and what can OEMs and technology providers do to address these concerns?

Hitesh Garg: Infrastructure is an important enabler for SDVs. The deployment of reliable infrastructure, high-speed connectivity, and intelligent transport systems will also be essential to unlock the full potential of SDVs. Addressing these challenges requires close collaboration across the automotive ecosystem. Semiconductor companies, OEMs, Tier-1 suppliers, software developers, and standards bodies must work together to build interoperable platforms based on open architectures and common software frameworks.

ELE Times: How do you perceive the future of connected car technology and what innovations can we expect in the foreseeable future?

Hitesh Garg: We at NXP are enabling this future through our broad automotive portfolio spanning secure connectivity, V2X, UWB, radar, edge AI, and high-performance automotive processing. As vehicles become more software-defined and connected, our focus remains on delivering secure, scalable technologies that enable automakers to accelerate innovation while ensuring functional safety, cybersecurity, and reliability. For India, where connected mobility is gaining momentum alongside the growth of electric and software-defined vehicles, this presents a significant opportunity to develop globally competitive solutions that shape the future of intelligent transportation.

ELE Times: What are your views on the India Semiconductor Mission 2.0?

Hitesh Garg: Government initiatives such as ‘ISM 2.0’ are a defining milestone in India’s journey toward global semiconductor leadership. By expanding support across the entire value chain from manufacturing and advanced packaging to critical materials and design, this initiative builds a foundation for long-term competitiveness.

India’s world-class engineering talent is a proven asset, and sustained R&D investments will further elevate its position in the global supply chain. At NXP, we are fully committed to this vision. We continue to advance cutting-edge R&D locally and nurture future-ready talent. We believe that collaborative ecosystem innovation is the key, and we look forward to partnering with industry, academia, and policymakers to drive India’s emergence as a global semiconductor hub.

The post Interview | Hitesh Garg, Vice President & India Managing Director, NXP Semiconductors appeared first on ELE Times.