ELE Times

Keysight Technologies (NYSE: KEYS) today announced Keysight Multiphysics, a design and verification solution that addresses the physics interactions driving failure in modern electronic designs. The structural analysis application covering drop, shock, and vibration enables engineering teams to identify and fix problems earlier, before a prototype is built.

Electronic products are growing in complexity faster than traditional engineering workflows can scale. As electrical, thermal, mechanical, and optical elements are compressed into tighter, more integrated designs, the physics interactions between them create failure risks that cannot be evaluated in isolation. Physics effects in one domain can produce unintended outcomes in another, and those interdependencies are rarely caught until the physical product is built, when the cost of redesign is highest and projects often miss deadlines and exceed budgets.

Keysight Multiphysics integrates physics simulation into the electronic engineering workflow, completing in hours a process that traditionally takes weeks. The first release addresses structural analysis and includes compliance simulation for drop, shock, and vibration. Previously, this step required building numerous physical prototypes for testing in an external lab, committing design and manufacturing tooling before identifying potential failures. Pre-built application templates embed setup expertise directly into the workflow, improving simulation fidelity.This allows teams to avoid late-stage failures without requiring a computer-aided

Key application benefits:

• Faster time to insight: Simulation-driven development helps teams reduce physical prototype iterations and identify reliability issues earlier in the design cycle.
• Lower redesign cost: Drop, shock, and vibration simulation enables engineers to locate where failures originate and make targeted corrections earlier in development.
• Increased design confidence: An application-specific database, expanded to include modern electronic materials, helps engineers model component behavior under realistic operating conditions.
• Broader access to simulation: A guided workflow interface embeds application expertise for each use case directly into the process, enabling engineers to confidently evaluate product reliability without specialist CAE skills.
• More time for engineering: Automated setup workflows eliminate manual configuration tasks traditionally required for structural simulation.
• Accelerated regulatory sign-off: Built-in compliance workflows support MIL-STD, IEC, and JEDEC standards for shock, drop, and vibration.

Niels Faché, Senior Vice President, Keysight Design Engineering Software, said: “Complexity now defines electronic design. Engineers used to treat electrical, thermal, and mechanical effects as separate problems. That approach can no longer keep pace. We built Keysight Multiphysics by working through the very problems our own engineers faced, giving teams a digital thread to detect failures earlier and more predictably.”

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In a breakthrough that will power the nation’s aspirations in aerospace propulsion, the first Indian expendable turbojet engine in the 350-kg thrust class was successfully demonstrated and marks an important step towards India’s capabilities in developing advanced propulsion technology. Developed by the Gas Turbine Research Establishment (GTRE) of the Defence Research and Development Organisation (DRDO), the engine will pave the way for increased self-reliance on high-end propulsion technology for upcoming aerial platforms and other defence applications.

Hyderabad-based Azad Engineering that was chosen by GTRE as the industry partner for its manufacturing and assembly, delivered the engine to GTRE on July 22, 2026. This also marks the coming together of the Indian defence research infrastructure and the private sector for building the aircraft. While DRDO lends its in-house design expertise and research in this field, Azad Engineering provides the cutting edge in precision manufacturing, modern engineering, and tooling facilities to make this possible.

The newly developed 350-kgf-thrust-class expendable turbojet engine is expected to power future air-breathing platforms, including selected missile systems and unmanned aerial vehicles (UAVs) that require compact, lightweight, and high-performance propulsion systems. As a turbojet is an air-breathing engine, it uses atmospheric air as part of the combustion process to generate thrust. The development represents an important advancement in India’s indigenous aerospace and propulsion capabilities, as the design and manufacture of jet engines require advanced materials, precision engineering, highly accurate manufacturing processes, and stringent quality-control measures. The technology could strengthen India’s domestic propulsion ecosystem and support the development of future high-speed aerial platforms.

The successful development highlights the growing contribution of India’s private defence industry to major propulsion programmes. Through its role in the indigenous manufacturing and assembly of the engine, Azad Engineering demonstrates how precision-engineering companies are increasingly participating in the development of complex aerospace and defence systems. The 350-kgf-thrust-class expendable turbojet engine was manufactured and assembled in India by Azad Engineering based on the design and technology developed by the Gas Turbine Research Establishment (GTRE), a laboratory of the Defence Research and Development Organisation (DRDO). This collaboration reflects the increasing role of private-sector companies in supporting India’s efforts to develop advanced indigenous propulsion technologies.

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According to STMicroelectronics, net revenues for the second quarter were $3.49 billion, up 26% on an annual basis. Gross margins reached 34.8% and for the quarter the firm saw $187 million in operating income. Net income of $222 million signifies a robust bounce back from a net loss last year.

The company said that the quarterly results were helped by solid business conditions with demand for a range of products rising in the markets such as communications equipment, computer peripheral, automotive and other semiconductor applications. In addition, STMicroelectronics revised upward its outlook for its data-centre activities due to rising demand associated with AI-related infrastructure.

For the third quarter of 2026, the company forecasts net revenues of $3.70 billion and a gross margin of 37.0%. STMicroelectronics is looking forward to robust second-half demand from AI and other end-market segments.

During the Q2 2026, STMicroelectronics (news releases) reported quarterly net revenues came above the mid-point of its business outlook driven by stronger revenue performance in its Communications Equipment, Computer Peripherals (CECP) and Automotive segments, and the company also reported gross margin in line with the mid-point of the outlook. “Q2 net revenues came above the mid-point of our business outlook range, driven by higher revenues in CECP and Automotive,” stated Jean-Marc Chery, President & CEO at STMicroelectronics. “Gross margin was in line with the mid-point of our business outlook range.”

Chery added that it will also see a rise in AI data-centre markets contribute to revenue, seeing “sustained strength in AI data-centres” means the company will now increase revenue for its data-centre market segment. This segment’s revenues “will exceed $1 billion in 2026, and, if we maintain customer engagements and market trends continue to evolve, are projected to well surpass $2 billion in 2027”, the company confirmed, signalling strength within “this burgeoning AI data-centre market space.”

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Rohde & Schwarz has introduced the new R&S MXO-K333 software option for three-phase power analysis on its MXO series oscilloscopes. The software adds in-depth measurement and analysis functions for testing and debugging three phase power systems, drives and inverters.

Available for all four and eight channel models of the MXO 3, MXO 4, MXO 5 and 5C oscilloscopes, it supports the analysis of voltage and current signals in three-phase AC systems. This innovative test solution keeps the captured waveforms visible during measurement, allowing engineers to review power values and check transient behavior in the same instrument. Other oscilloscope functions such as math, spectrum analysis, measurement tracking and zone trigger remain available for further analysis.

A guided setup wizard assigns the oscilloscope channels to the voltage and current probes used for the three-phase analysis. It verifies the wiring and supports common two-wire, three-wire and four-wire configurations (2V2A, 3V3A and 3VN3A). After setup, the software provides cycle-by-cycle calculations for RMS values, power factor, active power, reactive power and total power. By defining the input and output configuration, users can also calculate the system’s three-phase efficiency. Additional analysis views include phasor display, harmonic analysis and THD measurements in line with IEC 61000-3-2 and MIL-STD-1399.

As an oscilloscope-based solution, the R&S MXO-K333 enables engineers to correlate three-phase power results directly with the underlying voltage and current waveforms in real time. This is especially valuable during R&D and debugging, when power behavior often must be analyzed alongside switching events, transients, control signals and communication activity. Users can combine the three-phase analysis with inherent MXO capabilities such as advanced triggering, FFT, automated measurements, track functions and protocol decoding. This allows engineers to move from power measurement to root-cause investigation in a single instrument.

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Bosch is expanding its portfolio for diesel components with the new DCP 800 test bench. The abbreviation DCP stands for Diagnostic Common-Rail Pump and refers to a test bench specially developed for common-rail high-pressure pumps. The system helps workshops meet the increasing demands for efficiency, precision, and economy in diesel service.

High-performance technology for precise test results

The DCP 800 enables the testing of common-rail pumps for passenger cars, commercial vehicles, and off-road applications at pressures of up to 2,700 bar. A powerful 25-kW electric motor is directly connected to the drive mechanism and operates without intermediate systems. This drive concept supports precise and reliable testing, particularly for commercial and heavy-duty vehicle applications. Automated inlet and counter-pressure regulation, as well as electronic flow measurement, further contribute to measurement accuracy.

Efficient workflows in the workshop

A key advantage for workshops is the high efficiency of the test sequences. With test times of around 20 minutes – regardless of the application – service processes can be significantly accelerated. At the same time, a quick setup process combined with predefined, standardized test plans ensures simple and repeatable test execution. Optimized filtration, cooling, and measurement systems support automated maintenance intervals and help reduce operating costs.

The test bench covers a broad spectrum of Bosch common-rail pumps, including the CP1 to CPN6 series. Furthermore, it is compatible with existing generations of Bosch test kits such as CP1, CP3, and CBX8 from EPS 815/708 systems. This allows workshops a gradual and economical transition to the new testing technology.

Flexible integration into different workshop environments

A newly developed drive coupling system, which enables the quick mounting of different pump types, provides additional flexibility in the workshop. An adapter solution ensures that older coupling designs can continue to be used. The ergonomic machine concept with three-sided access supports comfortable and safe operation.

The operating computer with a screen for controlling and monitoring the test sequences can be positioned on either side of the test bench, depending on workshop requirements. This allows the DCP 800 to be easily adapted to different workshop specifications. Workshops benefit from optimized workflows, ergonomic operation, and seamless integration into their existing workspace.

The DCP 800 complements the existing Bosch test benches for common-rail injectors and enables workshops to perform comprehensive testing of pumps and injectors from a single source. The new test bench will make its debut at Automechanika Frankfurt from September 8 to 12, where it will be showcased live for the first time.

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Worldwide end-user spending on AI models and platforms is projected to total $64 billion in 2026, up 63.4% from $39 billion in 2025, according to Gartner, Inc., a business and technology insights company. Spending on GenAI models is forecast to grow 117%, while AI platform spending will rise 36.9% in 2026.

“Enterprise AI budgets are coming under greater scrutiny, with increased focus on usage efficiency, cost control and measurable outcomes,” said Arunasree Cheparthi, Sr Principal Research Analyst at Gartner. “Spending is shifting toward providers who can demonstrate clear value across cost, latency, performance and reliability.

“This is giving an edge to providers that embed evaluation, cost transparency and usage tracking into customer workflows, making it easier to manage and optimize AI use. However, as spending becomes more usage-driven, providers face increasing pressure to demonstrate real adoption, sustained use and durable margins.”

This dynamic is accelerating growth in domain-specific language models (DSLMs) and specialized models, which are forecast to grow 210% in 2026 (see Table 1).

Table 1: Worldwide AI Platforms and Models End-User Spending Forecast, 2025-2026, (Millions of U.S. Dollars)

			2025-2026 Growth %)
Segment	2025	2026
Foundation Generative AI Models	11,438	23,356	104.2
DSLMs and Specialized GenAI Models	1,583	4,910	210
AI Application Development Platforms	6,885	9,541	38.6
AI Platforms for Data Science and Machine Learning	19,405	26,444	36.3
Total Market	39,311	64,252	63.4

 

“Over the long-term, the biggest winners will be vendors that help enterprises manage where and how AI is used across the business,” said Cheparthi. “As more models enter the market and usage-based pricing becomes harder to predict, buyers will turn to platforms that help them choose the right tools, monitor performance, enforce policy and keep costs under control.”

 

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The second phase of the India Semiconductor Mission has received a much larger budget than the first phase, with Rs 1.27 lakh crore allocated to support different areas of semiconductor and electronics manufacturing. Similar to the first phase, it is expected that most of the budget will be allocated to the selected individual projects, either as a capital subsidy (in which case, the government might contribute less than the 50% that it agreed to in the first phase) and as manufacturing-linked incentives paid on a per-unit basis once sales are completed. An added element of Incremental incentive boosters will be made available for those manufacturing those electronic goods that make use of domestic technologies and components.

It promises to extend the government’s stated intent of making India a strategic hub for the electronics value chain and build those capabilities in-house, with both intellectual and human capital, when only a few countries globally command such capabilities across different components of the value chain.

The government had stated from the very beginning that this would be a multi- decade process and its continued patronage with a more substantive kitty of money is indeed welcome. While this might not be a high job-generating industry per se, it is their strategic, geo-political considerations to deploy public funds. Whether this was a good initial wager is still largely unclear, as many of the first round of awarded projects have still to commence commercial production.

Some technology is well beyond the reach of all economies: The complexity of the machines that print nanoscale feature images from “extreme ultraviolet,” or EUV, lithography, currently mastered only by the Netherlands with a looming challenge
from Japan, means the thought of India’s committing investment to such a technology is enticing, but unfathomable. Such strategic capabilities have hard payoffs. Such a capacity to do “hard things” will breed resistance to India rapidly developing the capability and attracting talent.

 

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Tata Electronics, a group company under the $103 billion Tata Sons conglomerate, is set to establish the country’s first commercial chip fabrication plant utilising an older technology to focus on a market segment for semiconductor designs from external customers, said an official with knowledge of the project. This would mark the first time the Indian government allocates resources to support establishing a chip making unit. The Tata Group had earlier reported the creation of India’s maiden integrated device manufacturer (IDM) in the country, a unit that designs and produces semiconductor chips in-house.

Tata Electronics Pvt. It will use technology far older than planned to produce India’s first semiconductor wafers, coming from a country with virtually no history of the sophisticated technology, highlighting how much work it will need to do to catch up. The tech unit of the sprawling Tata conglomerate will use 90-nanometer process technology for a large part of its first chip fab, which will be located in Dholera, a city in the western state of Gujarat, according to the sources.

That’s a very mature technology used in low-end industrial applications and cars – one that might even be obsolete in the coming years. It’s a more humble beginning compared with the 28nm node which Tata Sons Pvt., the group’s holding company, said would be the first step of its chipmaking innings in its annual report for the year ended March 2025.
It has been observed that Tata’s public plans could have been aspirational regarding what is realistically possible on the ground in the next couple of years. Tata’s entry into chipmaking involves a partnership with Taiwanese rival Powerchip Semiconductor Manufacturing Corp.

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The STM32U3B5/C5 are the first STM32U3 devices featuring 2 MB of flash and our new hardware signal processor (HSP). In a nutshell, the HSP is an embedded signal processor that accelerates certain computations, enabling a whole range of industrial and AI applications on our ultra-low-power microcontroller. While the new models retain the near-threshold design that allowed the STM32U3 series to boost efficiency by a factor of four, the HSP opens the way for sensing and machine learning programs that would have been too demanding before. We wrote an accompanying blog post on the new hardware signal processor to help avid readers grasp the performance gains and what it means for the STM32 community.

What’s new? The new STM32U3B5/C5

The STM32U3B5/C5 primarily stands out from the other STM32U3 devices thanks to its HSP. It’s also why it carries double the flash memory of previous models and 640 KB of RAM, as we expect developers to need a much greater capacity for larger applications and datasets. The new device also comes with one additional group of interfaces, bringing the total to four SPI and I2C, two I3C and CAN-FD, and five UARTs. There are also five more 16-bit timers, for a total of 10. The only difference between the STM32U3B5 and the STM32U3C5 is that the latter includes a cryptocore to accelerate encryption and decryption operations, as well as offer CCB (see more on that later).

What makes the STM32U3 series special? Ultra-low-power consumption and high energy efficiency

One number sums up the efficiency of the STM32U3: at 117 Coremark/mW, it breaks the 100 symbolic threshold, literally making it a new benchmark in the industry. Indeed, most of the best devices from the competition hover below 100, and the STM32U5 reached 53.9. This significant jump in energy efficiency is due to our near-threshold design. We dedicated an entire blog article to this region of CMOS transistors that many are trying to utilize, but that has remained mainly in the background until now due to its inherent challenges.

0.65 V minimum and 105ºC maximum

In a nutshell, near-threshold conduction in a CMOS transistor occurs when applying a voltage between the gate and the source near a threshold (VT). In most of the devices used in a microcontroller like the STM32U3, that threshold is 500 mV. The vast majority of near-threshold designs apply a VGS of about 700 mV or more. And since near-threshold conduction is a diffusion current as residual leakage current flows under the gate oxide, the transistor itself experiences strict limitations in its operating voltage and temperatures. Most competing devices don’t go above 85ºC, which is why we don’t usually find these devices in industrial applications.

The STM32U3 is different because, thanks to unique optimization in the lithographic processes and manufacturing, ST can apply a lower voltage of 650 mV. The most direct benefit of a VGS value that’s closer to VT is that it helps lower the VCORE further, meaning that we can reach a minimum of 0.65 V and a typical value of 0.75 V. Additionally, as we are experiencing significantly less leakage current than competing solutions, the STM32U3 supports an operating voltage of up to 3 V and a temperature of 105ºC. It can, therefore, tolerate far harsher environments. Hence, the STM32U3 is unique because it makes near-threshold designs mainstream in most industrial applications.

Adaptive Voltage Scaling

Another issue common in near-threshold designs is die variability. Because the near-threshold region is sensitive to the smallest voltage variations, it affects dies on the same wafer more significantly. That’s why tuning each die to account for changes between them can be time-consuming and costly. To solve this challenge, ST implemented a testing system at the factory level, which automates machine learning on STM32 devices. We call it Adaptive Voltage Scaling. Simply put, our machines test each die, and a machine learning algorithm automatically tweaks various aspects to ensure consistent ultra-low-power consumption.

Versatile peripheral offering without compromising cost efficiency

Another challenge of near-threshold designs is performance. Indeed, as the VCORE is low, so is the operating frequency. However, that is not the case with the STM32U3, which features a Cortex-M33 running at 96 MHz. Moreover, we ensured that despite its more cost-effective pricing, engineers would still get a lot of peripherals and timers. Indeed, the new device supports two I3C buses, CAN-FD, one octo-SPI interface, and more. It also comes with 16 timers, including two 16-bit ones for motor control applications, and a touch-sensing controller for those working on a UI.

Robust safety and security for sensitive and mission-critical applications

Besides efficiency and performance, ST also designed the STM32U3 for safety and security. Consequently, the new device offers up to 1 MB of dual bank flash, enabling firmware updates without shutting the system down, which is often a critical consideration in mission-critical applications. The STM32U3 also introduces CCB to securely transmit keys by using independent buses ([patent filed in 2023 and 2024]). And we’ve already updated STM32CubeMX, our initialization tool. After activating the random number generator, users can select “CCB” in the list of cryptographic options and start using the feature. Finally, the STM32U3 can also target PSA L3 and SESIP3 certifications.

What’s next

To ensure the STM32U3 can reach numerous industrial applications, we are offering eight packages, which is unique for a near-threshold design. We are also releasing a Nucleo board to help developers rapidly design a proof-of-concept or run their tests to witness the ultra-low-power consumption for themselves. SmaXtec, a member of the ST Partner Program specializing in bovine monitoring already shared how,

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The effective implementation of India-UK Comprehensive Economic and Trade Agreement (CETA) on July 15, 2026, highlights a significant growth for India’s automotive and electric vehicle (EV) sector. This agreement is a landmark free trade that eliminates custom duties on thousands of products, significantly boosting exports and foreign-investment by encouraging UK companies to invest in India through supply chains and manufacturing facilities. It was introduced by Indian Prime Minister Narendra Modi and UK Prime Minister Sir Keir Stamer, officially signed in July 2025 by both nations with the primary objective of expanding bilateral trade and investment.

The CETA establishes a comprehensive framework for creating new opportunities for Indian EV manufacturers, component suppliers, and battery companies by reducing traffic barriers and improving market access. Indian automakers like Tata Motors, Mahindra, and Maruti Suzuki can export up to 88,000 vehicles to the UK completely duty-free and scale their domestic manufacturing by integrating domestic MSME suppliers deeper into the UK and global EV supply chains.

The UK gains benefits by this agreement through deepened cooperation with India’s expanding clean energy and technology sector. The CETA provides UK businesses with improved access to India’s rapidly growing market and creating opportunities for greater trade and investment. This agreement improves the UK economy by granting tariff cuts on 90% of UK exports to India, lowering costs for UK consumers, and improving market access for British products.

The agreement is fully active and remain operational to its provisions on implementation. The future goal is to double bilateral trade to 100-120 billion by 2030. The current status of this agreement is that it operates alongside the Double Contribution Convention (DCC), a social security pact that saves Indian companies up to $600 million annually by exempting Indian professionals working temporarily in the UK from paying social security contributions in both countries simultaneously.

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The Indian Ballistic Missile Defence (BMD) Programme introduced by Atal Bihari Vajpayee government following the Kargil War was developed by Defence Research and Development Organization (DRDO). It is designed to destroy both high-altitude and low- altitude incoming enemy missiles by employing a two-tier, multi-layered missile defence architecture. The objective of this system is to provide more than one opportunity to destroy an incoming missile before it reaches its target using multiple layers of detection, tracking, command-and-control, and interceptor missiles (or Anti-Ballistic Missiles).

India has successfully enhanced its indigenous missile defence capabilities after DRDO successfully demonstrated a series of flight tests conducted on June 10 and 11, 2026, which reinforce the ability of Ballistic Missile Defence (BMD) system to counter evolving long- range ballistic missile threats. The test comprised three consecutive flight trials of the Phase-2 BMD system in which interceptor missiles successfully detected, tracked, and neutralized the enemy missile attack for testing purposes. The trial also included the maiden flight test of the Naval Anti-Ship Missile Medium Range (NASM-MR), showcasing DRDO’s progress in both air and maritime defence systems.

India’s indigenous BMD architecture is designed for a multi-layered interception strategy where it can destroy enemy hostile missiles by operating at two distinct interception layers — outside the earth’s atmosphere and within Earth’s atmosphere. India is updating its defence system that can handle more complex threats such as hypersonic missiles and Intercontinental Ballistic Missiles (ICBs). The BMD system uses AD-1 and AD-2 which are advanced, high-speed interceptor missiles used to destroy long range threats travelling at extremely high speed and in different weather conditions.

Through these trial tests BMS introduced new defence advance technologies such as latest interceptor designed to address complex flight trajectories, advanced tracking radars to destroy enemy missiles, capabilities of AD-1 interceptor, and improvement in target tracking. As missile technologies continue to evolve, future BMD systems are expected to incorporate artificial intelligence, machine learning, and more capable interceptor technologies.

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Marquistech has selected Rohde & Schwarz to equip its conformance and EMI/EMC test lab in Noida, India, with various systems for GCF and PTCRB certification testing. The investment includes the R&S TS8980FTA-3A RF/RRM full type approval system, the CMX500 radio communication tester for protocol conformance, the R&S TS-LBS positioning test system for location based service testing and the R&S TS9982 and R&S TS9975 EMI/EMC test systems.

With this expanded setup, Marquistech has become the first fully equipped conformance test house in India for both certification programs. The lab, strategically located in the Delhi National Capital Region, is aimed at serving companies in the mobile, IoT and wireless module markets, at a time when India is gaining importance as an export focused electronics manufacturing location.

The newly installed systems from Rohde & Schwarz support legacy 4G as well as advanced 5G features, including non terrestrial networks (NTN) and mission-critical communications (MCX), and lead in numbers of validated test cases covered. Additionally, Rohde & Schwarz has provided regulatory testing capabilities for EMC and EMI at the site to enable abroad range of services offered. This helps the test house minimize costs and reduce reliance on outsourced testing. For customers, it reduces the time to complete a certification campaign.

Marquistech has been active for some time as a GCF field testing RTO. With the expansion of their site in the Delhi National Capital Region, the company has now extended its global operations to conformance testing. This adds a broader local test offering for device makers that need certification support during development and before market entry.

Prashant Jain, VP, Marquistech, said: “Our goal is to provide a globally competitive certification hub for GCF and PTCRB testing, delivering quality, flexibility and faster time-to-market. Together with Rohde & Schwarz, we are helping strengthen the global wireless certification ecosystem.”

The local support structure provided by Rohde & Schwarz was a decisive factor for Marquistech. Rohde & Schwarz operates a major development site nearby with integrated laboratories that cover the wireless product lifecycle for conformance solutions, supported by local engineering and application teams.

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As industrial environments become more automated and connected, demand for Power over Ethernet is rising to enable industrial applications by delivering reliable power and data over a single cable, simplifying deployment and scalability. To offer an industrial-grade solution, Microchip Technology (Nasdaq: MCHP) has extended its broad range of single- and multi-port PoE solutions to include its PD-9601GCI Midspan, designed to meet the IEEE 802.3bt standard for industrial applications and their challenging environments.

“In a market where many existing networks don’t fully support PoE’s convenient single-cable deployment models, our industrial-grade PD-9601GCI midspan makes it easier for our customers to power their smart equipment in factories and industrial settings,” said Charlie Forni, corporate vice president of Microchip’s networking and connectivity business unit. “Additionally, our customers have the option to use our midspans as a private label powering option, enabling them to differentiate their products by offering a simpler integrated power solution.”

Microchip’s PD-9601GCI midspan stands out from its existing PC-9601GC single-port indoor PoE midspan because it’s industrial-grade and is designed to reduce the need for complex electrical work and additional power outlets, while delivering up to 90W of power and 10/100/1000 Mbps data rates over a single Ethernet cable.

The device offers features and capabilities that support reliable operation in remote or challenging factory and outdoor locations, minimizing downtime and support issues:

• Sealed, vibration-resistant metal enclosure that is Ingress Protection (IP)-rated: The IP rating is IP30.
• Extended operating temperature: Designed to sustain a temperature range of -40°C to 75°C.
• Extended power input options: Supports dual DC input in the range of 20V-60V.
• Enhanced industrial-grade surge protection: Helps protect against voltage spikes in industrial environments.
• Industrial mounting: Includes DIN rail, wall or panel mount options.
• Compatibility testing with industrial automation devices: Helps reduce integration and reliability issues
  for manufacturers.

Midspans are inserted after the network switch where they inject power onto an Ethernet line so it can deliver both power and data. These devices provide a convenient and cost-effective solution to deploy PoE in remote or challenging environments. Bundled with an IoT device, midspans enable manufacturers to offer a plug-and-play solution designed to support power delivery over the network.

 

 

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Texas Instruments (TI) India today announced the conclusion of its fifth
edition of the Women in Semiconductors and Hardware (WiSH) program, TI India’s flagship initiative to
inspire, mentor, and accelerate the careers of women engineering students in semiconductors, hardware,
and embedded systems. During the program, participants engage in hands-on experiments, technical
simulations, lab visits and engineering projects that expose them to real-world semiconductor applications
and product development workflows.

Since its inception five years ago, the program has empowered 685 women engineering students through
mentorship by TI engineers and facilitated more than 300 internship opportunities, helping create a
sustained pipeline of female talent into one of the world’s fastest-growing technology sectors. Building on
the momentum of previous editions, the 2026 WiSH program recorded a 33% increase in registrations,
close to 2,600 applications last year, reflecting growing aspiration among women students across India to
pursue semiconductor careers.

“At Texas Instruments, we believe early exposure to industry and mentorship can play an important role
in shaping future engineers. While women account for 43% of STEM graduates in India, one of the
highest rates globally, they continue to be underrepresented in technical roles,” said Arbab Kausar, HR
director, Texas Instruments India. “Over the past five years, the WiSH program has helped women
engineering students gain practical skills in semiconductor and hardware engineering while building their
technical capabilities. The significant increase in registrations this year is encouraging and reflects the
growing interest in semiconductor careers among female engineering students across India.”

While the program’s core architecture remains consistent, the 2026 cohort has been meaningfully
strengthened. Pre-work learning modules and streamlined sessions significantly expanded the time
participants spent on hands-on problem-solving, brainstorming, and collaborative design thinking.
Students continue to engage with TI mentors, former WiSH participants, interns, and early-career
engineers, gaining practical insights into what a career in semiconductor engineering truly looks like.

“The WiSH program gave me an opportunity to learn directly from experienced hardware engineers and
gain valuable insights into the semiconductor industry,” said Ashmita Das, who joined TI India as a
digital intern after participating in the WiSH program. “Returning to TI as a summer intern feels like a
dream come true and marks the beginning of an exciting new chapter in my journey. Deepening my
technical expertise while gaining first-hand experience of working with teams that collaborate, innovate,
and drive impactful engineering solutions has been incredibly rewarding.”

Through WiSH and its broader talent development initiatives, TI India continues to invest in
strengthening the long-term growth of India’s semiconductor ecosystem by nurturing the next generation
of women engineers.

 

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While accelerating towards manufacturing modern semiconductor technologies,
India has achieved another milestone by reducing the Basic Custom Duty (BCD) to 0%
on 85 categories of electronics components and manufacturing equipment by issuing
three official notifications through the Finance Ministry and the Central Board of
Indirect Taxes and Customs (CBIC). This policy removes the previous 5% to 7.5%
import taxes to make it cheaper to manufacture electronics inside the country. It also
simplifies supply chains by lowering landed costs, which boosts local component
sourcing and accelerates the country’s ambition of becoming a global electronics and
manufacturing hub.

The duty exemption primarily covers components, machinery, and equipment that
are not manufactured in sufficient quantities within India but are essential for the
production of smartphones, laptops, consumer electronics, telecom equipment,
industrial electronics, automotive electronics, and semiconductor-related products.
This elimination of costs on import duties in semiconductor manufacturing lowers
production costs, making electronics cheaper to build, and attracting global
investments by lowering their global supply chain expenses.

Industry experts believe that reduction in import duty will practically benefit
manufacturers by directly lowering production costs. Manufacturing electronic
products that rely on advanced electronic components, precision manufacturing
equipment, semiconductor materials, and testing systems that are currently
unavailable or produced only in limited quantities will be able to source these critical
inputs at lower costs.

Combined with ongoing investments under the India Semiconductor Mission, PLI
schemes, and expanding semiconductor manufacturing projects, the cost-cutting of
import duties is expected to strengthen India’s position as a preferred destination for
electronics production and innovation. As the semiconductor market grows, the
zero-duty policy on electronics input is expected to improve export competitiveness
and the development of a resilient semiconductor ecosystem, supporting India’s
emergence as a key player in the global semiconductor industry.

The post India Cuts Duty to 0% on 85 Electronics Categories, Leading Global Manufacturers to Invest in India appeared first on ELE Times.

The Ministry of Electronics and Information Technology (MeitY) with Drone
Federation of India, has introduced NIDAR 2.0 (2026-27) under the SwaYaan initiative to
build indigenous drones and flight controllers powered by India’s homegrown VEGA
processor. This innovation reduces reliance on foreign chips, strengthen the
domestic drone and electronics manufacturing ecosystem. This initiative aims to
accelerate the development of next-generation unmanned aerial system (UAS) by
encouraging startups, researchers, and industry to build drones using domestically
manufactured electronic components.

NIDAR 2.0 stands for National Innovation Challenge for Drone Application and
Research that aligns with government’s vision of Atmanirbhar Bharat, the India
Semiconductor Mission (ISM), and the Designed Linked Incentive (DLI) Scheme. The
goal of this hackathon is to provide a valuable opportunity for students and working
professionals to build flight controller and autopilot hardware powered by India’s
indigenous VEGA microchip.

According to MeitY release, NIDAR 2.0 offers a prize pool of more than 65 lakh that
not only promote innovation but also supports startups, nurtures young talents, and
accelerate the development of domestic drones and semiconductor technologies
through incubation, technical mentorship, and industry collaboration.

Launching the challenge, MeitY Secretary S Krishnan said, “NIDAR 2.0 takes our
students from just flying drones to building the drone’s brain. When the drone’s
brain runs on India’s own VEGA processor, we are not just training engineers. We are
laying the foundation of a self-reliant drone industry.”

The primary focus of this hackathon is to build autonomous swarm drones capable of
locating survivors and delivering medical supplies in disaster-hit areas without an
external communication network, and developing GPS-denied drones for indoor
industrial inspection. By collaborating as a coordinated fleet, swarm drones can
rapidly survey large areas, identify victims using onboard sensors and AI-based image
processing, and optimizing search-and-rescue operations without relying on constant
human intervention.

The post NIDAR 2.0: MeitY Boosts Indigenous Drone Innovation with India’s homegrown chips appeared first on ELE Times.

Cadence (Nasdaq: CDNS) today introduced the AuraStack AI Super
Agent on Cadence Allegro AI Studio, the world’s first agentic AI platform for printed circuit board
(PCB) and advanced packaging design, taking designers from system planning to final product in a
single AI-native environment. The Cadence AuraStack AI Super Agent, accelerated by NVIDIA
Blackwell and NVIDIA CUDA-X, coordinates domain-specific AI agents across planning,
implementation and tightly integrated multiphysics analysis domains to compress the system-design
cycle through manufacturing. With the AuraStack AI Super Agent, Cadence is now the only provider
with agentic AI solutions spanning the full electronic system design flow, from digital and analog
silicon design, advanced packaging, through to PCB design, building on its ChipStack, InnoStack
and ViraStack AI Super Agents.

“The next era of AI infrastructure—spanning data centers, automotive, aerospace and physical
AI—will be defined not only by silicon, but by the systems that connect, power and cool it,” said
Michael Jackson, corporate vice president of R&D for System Design and Analysis at
Cadence. “As hyperscale data centers deploy massive AI clusters and other industries advance
increasingly intelligent, high-performance systems, engineering teams face growing complexity in
PCB and advanced package design. Agentic AI orchestration, combined with trusted EDA and SDA
tools, enables customers to move from manual iteration to intelligent, automated design realization.”

Agentic AI for Packaging and PCB Design

Building on the same architecture as Cadence’s ChipStack AI Super Agent, agentic AI is combined with principled simulation and optimization tools, leveraging a mental model of the design intent, to automate and orchestrate the design exploration, realization and signoff. The AuraStack AI Super Agent brings together automation and optimization for system planning, constraints management, physical structure definition, IP creation and reuse, place and route, design for manufacturability and multiphysics analysis across Cadence’s system design and analysis portfolio. It introduces a unified, AI-driven multiphysics foundation that concurrently models and optimizes electrical, thermal and mechanical behavior—including SI/PI, thermal, mechanical stress, drop, vibration and fatigue analysis—within a closed-loop environment, enabling earlier tradeoff evaluation and product-level optimization across the entire design flow. This continuous multiphysics feedback loop enables real- time design convergence, reducing late-stage surprises and improving overall system reliability.

The AuraStack AI Super Agent’s key benefits include:

• Accelerating time to market by 2X, with 15X productivity and multiphysics-driven
  quality—automating complex tasks, expanding design exploration.
• Unifying separate engineering teams around a shared, multiphysics-aware design
  environment with a single source of truth across domains.
• Advancing early and continuous multiphysics co-optimization to reduce late-stage
  rework and costly design iterations. Unifies Cadence multiphysics signoff solutions, such as
  Celsius Thermal Solver, Clarity 3D Solver for 3D-EM, MSC Nastran and Marc Linear
  and Non-Linear Finite Element Analysis Solvers for mechanical analysis, and Sigrity X
  Platform for signal and power integrity.
• Limiting expensive respins by identifying system issues earlier in development.
• Enabling product-level optimization, including co-optimization with advanced packaging
  approaches.

Industry Leaders Advancing Agentic AI with Cadence
Cadence is collaborating with industry leaders to deploy AuraStack AI Super Agent workflows for real-
world advanced IC packaging and PCB design challenges.

NVIDIA is using Cadence to help automate and optimize increasingly complex system design
workflows for its engineering teams.

“The scale and complexity of modern AI infrastructure demands a new design approach,” said Tim
Costa, vice president and general manager of computational engineering at NVIDIA. “NVIDIA’s
collaboration with Cadence is advancing AI-powered engineering workflows that accelerate design
convergence and innovation across the industry. The Cadence AuraStack AI Super Agent and the
Millennium M2000 Supercomputer deliver up to 20X faster multiphysics performance, giving our
engineers the capability to tackle the most demanding design challenges and bring the next
generation of AI infrastructure to life.”

Cadence is partnering with TSMC to help customers accelerate advanced package implementation
through AI-driven automation, enabling timely design convergence for increasingly complex multi-die
systems.

“As advanced packaging complexity grows, customers need new levels of automation to achieve
timely design convergence,” said Aveek Sarkar, director of the Ecosystem and Alliance
Management Division at TSMC. “Our long-standing partnership with Open Innovation Platform
(OIP) ecosystem partners like Cadence to deliver advanced package design and verification solutions
for TSMC 3DFabric technologies helps customers accelerate the realization of next-generation
multi-die systems for AI and high-performance computing applications. Through our multi-year
collaboration on substrate auto routing, we are already enabling customers to boost productivity by
100X while delivering quality of results similar to manual routing.”

Socionext is leveraging Cadence to accelerate the automation and optimization of increasingly
complex semiconductor package and PCB design workflows.

“AI-driven agents are set to transform IC package and PCB design by automating SI, PI and thermal
workflows and enabling generative design,” said Iwasaki Toshifumi, lead design execution leading
unit, Global Leading Group at Socionext Inc. “This acceleration allows our engineers to focus on
higher-value work like architecture exploration, margin optimization, and multiphysics tradeoffs, while
capabilities such as automated routing and chip-package-board co-design accelerate convergence
and reduce manual effort.”

FORVIA HELLA continues to advance intelligent, sustainable mobility solutions that will define the
future of automotive technology.

“Working closely with Cadence has fundamentally changed the way FORVIA HELLA develops
advanced automotive electronics. Using AI-assisted placement technology, a task involving the
placement of 300 components that previously took up to four days can now be completed in just four
minutes,” said Sven Hoenecke, president & CEO, Electronics NSA at FORVIA HELLA. “This step
change in productivity allows our engineers to evaluate more design alternatives, optimize layouts
earlier in the development process, and accelerate the development of innovative products without
compromising quality. By automating repetitive work, our teams can focus more time on solving
complex engineering challenges and bringing new technologies to market faster.”

Schneider Electric is collaborating with Cadence to apply AI-driven design automation and
engineering expertise to accelerate electronic design workflows and scale institutional knowledge
across engineering teams.

“At Schneider Electric, we see AI as much more than a productivity tool. Our collaboration with
Cadence has demonstrated the potential of AI to accelerate design activities and improve engineer
efficiency,” said Daniel Gheno, senior vice president, Innovation and Technology EM at
Schneider Electric. “The next frontier is to combine design automation with engineering expertise,
enabling companies to capture decades of know-how and make robust design decisions available to
every engineer. We believe this is where AI can truly transform electronic design.”

The post Cadence Introduces AuraStack AI Super Agent, the World’s First Agentic AI Platform for PCB and Advanced Packaging appeared first on ELE Times.

Keysight Technologies, Inc. has been selected by the European Space Agency (ESA)
to lead a three‑year development program focused on creating secure, blockchain‑enabled
anomaly detection for 5G non‑terrestrial networks (NTN). Keysight will serve as the prime
contractor, collaborating with Sateliot to support key technical development and satellite mission
integration.

As more satellite communication constellations are deployed, space‑based networks are
becoming increasingly complex, with growing interactions between satellites, ground systems,
and terrestrial 5G infrastructure. This introduces new challenges related to quality of service,
anomaly management, operational security, and confidence in network behavior once deployed.
Looking ahead to 6G, where non-terrestrial infrastructure will play a central role, ensuring
access to trusted, verifiable data will be critical to enabling autonomous and artificial intelligence
(AI)-driven network operations.

The project, which benefits from the support of ESA’s Space for 5G/6G & Sustainable
Connectivity program line within the Agency’s Advanced Research in Telecommunications
Systems (ARTES), is designed to address these challenges by establishing a secure, verifiable
trust framework for NTN environments. Keysight will leverage its design, test, and measurement
expertise to explore how blockchain, AI, machine learning (ML), and digital calibration
certificates can be applied across the full NTN lifecycle, from satellite manufacturing and
calibration to in‑orbit operation and service delivery.

Albert Pujol, Chief Innovation Officer at Sateliot, stated: “This program represents a
definitive shift toward integrating space-based assets into a secure, unified 5G ecosystem. By
anchoring blockchain within our orbital operations, we are creating a transparent validation layer
that allows massive IoT networks to scale globally while consistently ensuring security and
performance.”

Antonio Franchi, Head of the Space for 5G/6G & Sustainable Connectivity programme at
ESA, said: “The future of Europe’s connectivity depends on networks that are not only
advanced, but trusted, resilient and secure. Supporting this project, which benefits from
Keysight’s leadership and Sateliot’s expertise, underscores ESA’s commitment to helping
pioneer the technologies required to safeguard the integration of non-terrestrial and terrestrial
networks. Together, we’re not only taking a step towards defending Europe’s communications
against spoofing and tampering, but we’re also ensuring that our Member States remain at the
forefront of secure 5G and future 6G communications.”

Eric Taylor, Vice President, Aerospace, Defense and Government Solutions at Keysight,
said: “This initiative represents a major step toward securing hybrid space–terrestrial networks
at a time when global NTN deployments are accelerating. By combining test and measurement
expertise with AI-driven assurance and blockchain technologies, this work will demonstrate how
trust can be embedded across the full NTN lifecycle – from design and validation through in-orbit
operation.”

By integrating these technologies, the program aims to enhance the integrity and reliability of
space‑based IoT, 5G, and future 6G communications, helping to protect networks from
spoofing, tampering, and other cyber threats. Over the course of the program, development will
progress from laboratory research and prototyping to a full in‑orbit demonstration, validating
how blockchain‑anchored trust, autonomous anomaly detection, and secure telemetry can be
applied in operational satellite environments.

The ESA‑funded program is expected to inform future NTN operations, strengthen Europe’s
position in secure satellite connectivity, and accelerate the adoption of trusted space‑based
5G/6G networks worldwide.

The post Keysight and Sateliot Selected by European Space Agency to Develop Blockchain‑Enabled Framework for 5G Non‑Terrestrial Networks appeared first on ELE Times.

Deploying AI inference in powerconstrained and missioncritical environments such
as aerospace and defense systems requires solutions that balance performance, efficiency, reliability and
ease of development. To better manage these challenges, Microchip Technology (Nasdaq: MCHP) has
released the VectorBlox 3.0 Accelerator Software Development Kit (SDK) to help simplify FPGAbased AI
implementation and speed timetomarket. Offered to developers free of charge, VectorBlox 3.0 SDK and
associated CoreVectorBlox IP is designed as an integrated toolchain that streamlines optimization,
compilation and deployment of convolutional neural network (CNN) models on PolarFire FPGA and SoC-
based platforms. Because the accelerator scales efficiently across model sizes and supports multiple AI
workloads on a single device, customers can consolidate various vision or sensorbased AI functions on a
single low power FPGA.

“As AI models continue to grow in complexity, compression is becoming essential for deploying intelligence
at the edge,” said Shakeel Peera, corporate vice president and GM of Microchip’s FPGA business unit.
“With VectorBlox 3.0, we’re leveraging sparsity-based model compression from our Neuronix acquisition to
reduce compute demands while preserving accuracy.”

With support for sparse neural networks, VectorBlox 3.0 helps enable efficient execution of vision-based
CNN models by skipping zerovalued operations. This capability helps developers accelerate inference
performance while reducing power consumption, an important advantage for alwayson edge AI
applications that must balance responsiveness with energy efficiency. Enabling sparsity-based model
compression is designed to reduce compute and memory demands, while preserving accuracy.

“Leveraging VectorBlox acceleration on Microchip’s PolarFire SoC enabled us to efficiently deploy advanced
onboard AI pipelines for low-latency payload operations in orbit,” said Vito Fortunato, SPACEDGE
services line manager at Planetek Italia. “The platform allowed us to validate real-time Earth Observation
processing capabilities including object detection, semantic scene analysis and edge-generated actionable
information products on top of the AI-eXpress-1 satellite, deployed in 2025, while providing the radiation
resilience and operational reliability required for continuous Low Earth Orbit operations.”

Additionally, Spacecraft Pose Network v2 (SPNv2), a neural network designed to estimate position and
orientation using vision data, enables autonomous navigation and proximity operations in space for
applications such as autonomous rendezvous and docking, space debris removal, satellite inspection and
formation flying. Built on mid-range, power-efficient, single-event-upset (SEU) immune PolarFire FPGAs and
SoCs, the solution delivers secure boot, anti-tamper protection and high reliability for harsh environments.
These features are necessary for missioncritical defense, aerospace and industrial deployments where long
operational life, data protection and system resilience are essential.

“The combination of PolarFire SoC and VectorBlox creates a powerful synergy for deploying AI-powered
autonomy solutions directly in orbit,” said Federico Fontana, Head of Hardware Engineering at AIKO. “We
validated this through the deployment of our clear_CHARLES suite, which provides onboard cloud and ship
detection for adaptive and autonomous payload operations on power-efficient platforms, making a further
step toward increasingly autonomous, responsive and software-defined space systems.”

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Indian deep-tech startup Meine Electric has developed the world’s first fast-charging iron-air battery system, marking a significant technical advancement for long-duration energy storage (LDES). The technology, which features a proprietary Fast Charge Long Discharge (FCLD) capability allowing the battery to charge in 6 hours and discharge over 18 hours, has been independently validated by Customized Energy Solutions (CES), a US-headquartered global energy services and technology company and the parent organization of the India Energy Storage Alliance (IESA).

The independent testing was conducted by the CES Battery Laboratory through a structured testing protocol designed to assess electrochemical performance, capacity retention, and operational stability. Testing two iron-air electrochemical cells, the assessment validated the system’s operational stability under an asymmetric duty cycle comprising a rapid 6 hours of charging followed by 18 hours of discharging per cycle.

Historically, iron-air battery chemistry has been limited by longer charge cycles, with existing approaches focused on multi-day storage applications. According to DataM Intelligence’s Iron Air Battery Market Size, Long-Duration Energy Storage Forecast 2035; 2026 Report, Iron-Air batteries are emerging as a promising solution for long-duration energy storage due to their ability to provide reliable and scalable storage using abundant materials such as iron. Global players, including Form Energy (US) and Ore Energy (Europe), have built Iron-Air systems focused on long-duration applications, with existing approaches demonstrating storage durations of up to 100 hours. However, these longer cycle times have restricted its suitability for daily renewable energy balancing.

Meine Electric has addressed this limitation through its proprietary Fast Charge Long Discharge (FCLD) technology, electrode development processes, and new system architecture. The technology enables a 6-hour charge and 18-hour discharge cycle, making it the world’s first fast-charging Iron-Air battery technology designed for daily-cycling renewable energy applications. The chemistry also offers fundamental advantages including inherent safety, reliance on abundant raw materials, and lower system costs compared to lithium-ion.

“Traditional iron-air systems are restricted to multi-day cycles, making them largely incompatible with the intermittent nature of renewable energy generation. Furthermore, solar-heavy grids don’t need a 100-hour battery. Unlike regions that require seasonal storage, the renewable challenge across Asia and MEA is fundamentally a daily balancing problem. By engineering our system to capture a full charge within a tight 6-to-8-hour window, we are finally turning iron-air batteries from a sluggish backup chemistry into a foundational, daily-cycling asset,” said Priyansh Mohan, Co-founder and CEO of Meine Electric.

This daily-cycling capability aligns precisely with the requirements of rapidly growing renewable energy markets like India, where the grid demands storage technologies that can consistently capture excess solar generation during the day and discharge it reliably overnight. For Meine Electric, it reinforces the company’s progress from laboratory-scale development towards real-world deployment of next-generation storage solutions.

Founded in 2023 by Priyansh Mohan and Stuti Kakkar, Meine Electric is the first company in APAC, and the third player globally, pioneering iron-air long-duration energy storage. As India races towards its 500 GW renewable energy target by 2030, Meine Electric is positioned to deliver key strategic advantages:

• Market-Leading Costs: The proprietary technology operates at a levelised cost of storage (LCOS) of less than $0.05/kWh (~₹5/kWh).
• Daily-Cycling Capability: Affordable, daily-cycling batteries that seamlessly complement lithium-ion to unlock true round-the-clock renewable power.
• Grid Infrastructure: Systems capable of functioning as foundational assets to firm renewables and flexibilize thermal assets.

“The energy industry prioritizes lower costs and higher reliability, and iron-air technology is structurally positioned to deliver on both. We are betting on iron-air as a foundational infrastructure play to support the renewable grid,” stated Stuti Kakkar, Co-founder and COO of Meine Electric.

The validation by CES adds critical third-party credibility to Meine Electric’s technology roadmap as the company moves towards larger-scale demonstrations, pilot deployments, and continues developing indigenous energy storage solutions to secure India’s transition to renewable energy.

The post Indian Deep-Tech Startup Meine Electric’s Fast-Charging Iron-Air Battery Clears Independent Validation, Paving the Way for 24/7 Renewable Energy Storage appeared first on ELE Times.