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STSPIN32G4, The 1st motor controller with an integrated MCU solves 2 major challenges
Author: STMicroelectronics
The STSPIN32G4 integrates a three-phase gate driver, an STM32G431, and a power management system under one package to solve major engineering challenges, thus enabling new applications. While ST continues to offer STSPIN motor drivers, we also realized that engineers still face several conundrums. Designers want to run more powerful applications but must also shrink their PCBs and reduce costs. Similarly, applications demand more efficiency, but improving it by a few decimal percentage points remains a struggle. ST engineers thus launched the STSPIN32G4 because no other integrated motor controller offered such a powerful mainstream MCU and such a flexible power management system.
STSPIN32G4 and the first challenge: How to make things more powerful in a smaller design? More power under one roof The STSPIN32G4Let’s take the example of an engineer working on a high-end vacuum cleaner with a high-speed motor. The MCU inside the STSPIN32G4 will stand out, in this instance, because of its computational throughput. A lower-performance CPU core means a lower conversion rate when designing a field-oriented control (FOC) sensorless application. The engineer in the vacuum cleaner example would have to use two or three shunt resistors to compensate for the MCU’s lower performance. On the other hand, the greater computational throughput means a single shunt is sufficient. As a result, using the STSPIN32G4 enables the creation of a powerful application with fewer components.
More peripherals in one deviceA team working on a collaborative robot or a guided vehicle would also appreciate the MCU in the STSPIN32G4 for reasons other than the bump in DMIPS. In this instance, engineers must drive two sets of wheels, but traditional motor controllers don’t have enough analog-to-digital converters to handle such a task. As a result, engineers end up using two motor drivers. The STSPIN32G4 is unique because it provides two sets of PWM timers and 12-bit ADCs, among other things. It, therefore, becomes possible to drive two motors with just one integrated device.
Saving 65% spaceWhile it’s impossible to enumerate all the features in the STSPIN32G4, the reality is that its integrated nature is one of the best ways to solve the space challenge. Motor control applications are increasingly smaller, whether for convenience, costs, or to stand out better. Thanks to its integrated nature, the STSPIN32G4 helps reduce the overall design size by 65% compared to discrete solutions. Practically, it allows engineers to put the control system at the back of the motor and design a much smaller e-bike, vacuum cleaner, or power tool, among other things.
STSPIN32G4 and the second challenge: how to make things more energy efficient while keeping costs down? A more efficient power managementAccording to our benchmarks, using the new device lowers the overall power consumption by 3% to 5% compared to a system that uses external components. A saving of just a single percent already has a significant impact. ST provided such power efficiency by bringing the typical standby consumption to only 15 µA thanks to a very low-quiescent regulator. Hence, we expect engineers to create significantly more compact designs without needing an external cooling system, thus lowering the BoM.
The motor controller also supports a supply voltage of up to 75 V, compared to only 48 V previously. Additionally, the STSPIN32G4 comes with an over-current protection mechanism and a drain-source voltage (VDS) monitoring system that acts as a redundancy. It monitors the external MOSFETs and turns all gate driver outputs off if it detects an over-voltage condition. As a result, we expect engineers to use the STSPIN32G4 in appliances. Indeed, a white good connected to a grid often suffers from wide voltage variations from the mains. The greater supply voltage range and protection features of the new device will better handle these abnormal conditions.
A more flexible power managementEngineers sometimes shy away from integrated solutions, fearing they may restrict their optimization capabilities. Hence, ST ensured a high level of customization. For instance, developers can program registers through an I2C interface to use the STSPIN32G4’s VCC buck converter. Moreover, we published an application note showing how to use the buck regulator in a buck-boost configuration by adding a few external components. Finally, engineers can bypass the buck and LDO regulators to rely on only an external Vcc supply.
Teams that designed a highly precise power supply to meet the stringent requirements of their application can, thus, ignore the STSPIN32G4 regulators. In contrast, others can simplify their designs by using its VCC buck converter to power a few external components, like a memory module. Similarly, developers can choose to enable or disable the standby mode. Such a feature is vital for products like power tools. When users pick a drill after months or even years, they must use it immediately. In such a case, engineers will want to completely disconnect their system from the battery to maximize its usage.
Engineers also get a lot more flexibility in how they drive a motor. They could use a 6-step driver circuit or a field-oriented control, both with or without a sensor and with one, two, or even three shunts. It gives developers the ability to control how much measurement data they gather. Consequently, it also becomes possible to qualify an STSPIN32G4 and use it in many different applications, which can help a company shorten its time to market and optimize its operations.
How to get started The EVSPIN32G4ST launched two development boards to enable teams to test and experiment with the STSPIN32G4. The EVSPIN32G4 uses STL110N10F7 power MOSFETs and a heat sink to allow an output current of up to 20 A RMS. As a result, teams can push the new devices to develop more powerful designs. However, ST is also mindful that not every designer will use the STSPIN32G4 in high-powered systems. Hence, we are also launching the EVSPIN32G4NH, a similar development board without passive cooling; NH at the end of the nomenclature stands for “no heat sink”. We also updated the X-CUBE-MCSDK to support the new boards and devices.
The EVLSPIN32G4-ACTMore recently, our teams released two reference designs. The EVLSPIN32G4-ACT drives a three-phase brushless motor supporting up to 5 ARMS and can manage a supply input of 48 V for a surprising 250 W total power in a board measuring only 62 mm x 50 mm. Additionally, it can connect to the STWIN.box (STEVAL-STWINBX1) to rapidly create a high-speed data logger. Thanks to our FP-IND-DATALOGMC software pack and Quick Start Guide, engineers have a step-by-step process to connect both boards and run applications that can gather data from the sensors on the STWIN.box and the motor itself. We even offer a GUI to help visualize the information.
The EVSPIN32G4-DUALThe other board is the EVSPIN32G4-DUAL, which combines the STSPIN32G4 and the STDRIVE101, a triple half-bridge gate driver. As a result, the board can drive two three-phase brushless motors for up to 10 ARMS output current and a supply of 74 V thanks to two power stages. Thanks to the operational amplifiers of the STSPIN32G4, it’s possible to have a sensor-less system with a single shunt current sensing or use Hall sensors and encoders with the embedded MCU. Put simply, the reference design shows how to create a powerful dual motor application in a small factor for home appliances, e-mobility, pumps, tools, and more.
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Just got this in the mail today, just in time for work bench wednesday!
submitted by /u/BlownUpCapacitor [link] [comments] |
Quintessent raises $11.5m in oversubscribed seed funding round
EU-funded photonixFAB consortium now open for first prototyping
Overloaded Infineon EconoPIM
Yet another magic smoke cloud frozen in the transparent gel. [link] [comments] |
Parsing PWM (DAC) performance: Part 4 – Groups of inhomogeneous duty cycles
Editor’s Note: This is a four-part series of DIs proposing improvements in the performance of a “traditional” PWM—one whose output is a duty cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to produce a DAC. The first part suggests mitigations and eliminations of common PWM error types. The second discloses circuits driven from various Vsupply voltages to power rail-rail op amps and enable their output swings to include ground and Vsupply. The third pursues the optimization of post-PWM analog filters. This fourth part pursues the optimization of post-PWM analog filters.
Part 1 can be found here.
Part 2 can be found here.
Part 3 can be found here.
Recently, there has been a spate of design ideas (DIs) published (see Related Content) which deals with microprocessor-generated pulse width modulators driving low-pass filters to produce DACs. Approaches have been introduced which address ripple attenuation, settling time minimization, and limitations in accuracy. This is the fourth in a series of DIs proposing improvements in overall PWM-based DAC performance. Each of the series’ recommendations is implementable independently of the others. This DI addresses PWM sequence modifications which ease low pass analog filtering requirements.
Wow the engineering world with your unique design: Design Ideas Submission Guide
The tyranny of resolution vs response time
The combination of PWM clock frequency Fclk Hz and the number of bits b of PWM resolution dictates the lowest frequency (Fclk·2-b Hz) output component of a standard PWM. Over all the possible duty cycles, this component is also the largest and therefore the most challenging for an analog filter to suppress. For a given Fclk, the more bits of resolution, the longer the settling time will be of a filter which provides adequate suppression. But there is a way around this limitation.
Suppose a standard 8-bit PWM whose output is either 0 or 1 is configured for a duty cycle of (arbitrarily) 121/256. The first 121 states in a 256-state cycle would be 1 and the remaining 135 would be 0’s. But what if the first 128 states started with 60 ones and the last 128 states started with 61 ones? Let’s call this the “split-in-two” PWM. These two sequences have been offset in amplitude slightly so that they can be clearly seen on a graph shown in Figure 1.
Figure 1 Output sequences of standard and split-in-two 8-bit PWMs with the same clock frequency, period, and duty cycle (121/256).
The blue waveform represents the standard PWM and the orange one is the split-in-two PWM. Why might the latter be advantageous? Consider the spectra of the two PWMs seen in Figure 2.
Figure 2 Frequency content of standard and split-in-two 8-bit PWMs with the same clock frequency, period, and duty cycle (121/256).
The energy in the first harmonic of the split-in-two PWM is negligible in comparison with that of the standard PWM. The necessary attenuation for the first harmonic has been significantly lessened, and that which was required is now applied to the harmonic at double the frequency. A less aggressive attenuation-with-frequency analog filter can now be employed, resulting in a shorter settling time in response to a change in duty cycle.
Another way to look at this is to double the split-in-two PWM period to 512 states to produce a 9-bit PWM. As shown in Figure 3, the spectra of the two PWMs are almost identical because the time domain waveforms are almost identical—they differ only in that every other 256-bit sequence, one additional one-state replaces a zero-state. The higher resolution 9-bit PWM produces a small amount of energy (less than 1%) at half the frequency of the 8-bit’s fundamental. Any analog low pass filter with adequate suppression of the 8-bit fundamental frequency will more than sufficiently attenuate the signal at half that frequency.
Figure 3 Frequency content of a standard 8-bit PWM of duty cycle 121/256 and a split-in-two 9-bit PWM of duty cycle (121.5/256). They share the same clock, but the split-in-two’s period is twice the standard PWM’s.
The super-cycle
We can think of the split-in-two as generating a “super-cycle” consisting of two cycles of 2b states, each having at least S one-states, with 0 ≤ S < 2b. In one cycle, one zero-state could be swapped for a one-state if the total number of ones in the super-cycle is odd. This is a (b+1)-bit PWM with a period of 2b+1 states. But there is no reason to stop at two. There can be a super-cycle of 2n cycles where n is any integer. With each cycle capable of optionally swapping one zero-state for a one-state, this leads to a PWM super-cycle with a resolution of 2b+n bits. But unlike standard, non-super-cycle PWMs whose maximum spectral energy component is at fclk/2b+n Hz, the super-cycle’s is at a much higher fclk/2b Hz. As with the specific case of the split-in-two, this eases analog filtering requirements and results in a shorter settling time.
It’s worth thinking of a super-cycle as consisting of the sum of two different sequences. One is the S-sequence in which every cycle consists of an identical sequence of S contiguous one-states. The other is the X-sequence where each cycle optionally swaps the first zero-state following the last one-state with another one-state. The X-sequence has X one-states where 0 ≤ X < 2n. The duty cycle of the super-cycle is then (2n·S + X)/2b+n.
When n = 1 for a super-cycle, there is only one cycle where an extra one-state can reside. But when n > 1, X is also greater than one and the question becomes how to distribute the X ones among the 2n cycles so as to minimize the super-cycle’s energy at low frequencies. The fine folks at Microchip who manufacture the SAM D21 microcontroller not only have figured this out for us, but they have also implemented it in hardware [1]! For this IC, it is necessary only to write the values of X and S to separate registers to implement a super-cycle PWM; the hardware does the rest unsupervised. Fortunately, it is simple for almost any microprocessor to augment a standard PWM to implement a super-cycle. For each PWM cycle, the duty cycle count must be modified so that immediately after the sequence of S ones, the first zero gets changed to a one if and only if the following C expression is true for that cycle:
MASK & (cycleNbr * X) > MASK – X
Here, MASK = 2n– 1, X is as before, and cycleNbr is the numeric position of the cycle in the super-cycle. Figure 4 is a graph of the magnitudes of the lowest 32 harmonics of an n = 4, b = 8 super-cycle PWM. The graph provides evidence of the benefit of this approach.
Figure 4 First 32 harmonics of an n=4, b=8 super-cycle PWM. Spectra are displayed for X=1 through 8. (Spectra of X=9 through 15 are the same as those shown.)
The X-sequence’s energy is relatively low, having only 0 through 2n-1 one-states, but it also presents the lowest frequency component, fclk/2n+b Hz. The S-sequence generally contains the most energy by far (except for instances of very small duty cycles), but its smallest frequency component is noticeably higher at Fclk/2b Hz. Among the X sequences, X = 1 gives the largest amplitude for its first harmonic: 2-11 at fclk/2n+b Hz. The S sequence’s spectrum starts at the X sequence’s harmonic number 24 = 16 and produces its largest amplitude of 2/π for that harmonic when S = 211. If this were a standard PWM (an n = 0 super-cycle—no super-cycle at all that is, just a normal PWM), then that amplitude of 2/π would appear at frequency which is 16 times lower. The standard PWM presents a much more severe filtering problem. Its filter would take a lot longer to settle in response to a duty cycle change because of the much larger amount of low frequency attenuation required.
Comparing the filters for (n+b)-bit standard and super-cycle PWMs
The filtered AC steady state time-domain contributions of both the standard and the super-cycle (with its X and S sequences) PWMs should be less than some fraction α of the voltage of the PWMs’ one-state. A reasonable value of α is 2-(n+b+1), ½ LSB. This translates to an attenuation factor of 1/4 at the first harmonic of the X sequence. It is fortunate that even a simple two-component R-C filter meeting this requirement will sufficiently attenuate all higher X sequence harmonics, so there are no additional constraints to meet to suppress them. The 16th X harmonic frequency is that of the first S harmonic. Its PWM energy requires an attenuation factor of (π/2)·2-(n+b+1) at a 50% duty cycle. Again, any low pass filter meeting this requirement will adequately attenuate the remaining S-sequence harmonics. For an Fclk = 20 MHz, Figure 5 and Figure 6are graphs of the frequency and time domain step responses of 3rd order filters (two op-amps, 3 resistors, and 3 capacitors) meeting these requirements for standard 12-bit and super-cycle n = 4, b = 8 (12-bit) PWMs.
Figure 5 The frequency responses of filters for standard and super-cycle n = 4 bit PWMs with 12 bits of resolution. The maxima of the peaked waveforms are the maximum responses allowed for the filters at the peaked frequencies. The filters ensure that the steady state time domain energy at their outputs is less than ½ LSB of Full Scale.
Figure 6 The log of the absolute value of time responses of filters for standard and super-cycle n = 4 bit PWMs with 12 bits of resolution. The much shorter settling time of the super-cycle PWM is clearly evident.
Easing low pass analog filter requirements
When partnered with an appropriate analog filter, an approach to PWM embodiment available in hardware in an existing microprocessor [1] offers significantly shorter settling times than does a standard PWM. This approach can be implemented with the aid of a small amount of software in almost any microcontroller.
Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.
Related Content
- Double up on and ease the filtering requirements for PWMs
- Optimizing a simple analog filter for any PWM
- Fast-settling synchronous-PWM-DAC filter has almost no ripple
- Cancel PWM DAC ripple and power supply noise
- Cancel PWM DAC ripple with analog subtraction
- Cancel PWM DAC ripple with analog subtraction—revisited
- Cancel PWM DAC ripple with analog subtraction but no inverter
- Fast PWM DAC has no ripple
References
- https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-D21DA1-Family-Data-Sheet-DS40001882G.pdf(See section 31.6.3.3.)
The post Parsing PWM (DAC) performance: Part 4 – Groups of inhomogeneous duty cycles appeared first on EDN.
BelGaN qualifies its BEL1 650V eGaN platform for volume production with orders from several lead customers
Vector Photonics and University of Glasgow collaborating to develop surface-emitting lasers
Wolfspeed tops out construction of John Palmour Manufacturing Center for Silicon Carbide
Power Integrations’ gallium nitride (GaN) story
Gallium nitride (GaN) power semiconductors continue to push the boundaries of high-voltage electronics, as evident at this year’s Applied Power Electronics Conference (APEC) in Long Beach, California. GaN devices are moving beyond fast chargers for cell phones, tablets, and game machines into the realm of automotive, renewable energy, and industrial applications.
At APEC 2024, during his plenary presentation titled “Innovating for Sustainability and Profitability,” Power Integrations CEO Balu Balakrishnan revealed that his company had been shipping GaN switches for two to three years in high volume before anybody knew it. “We never advertised our GaN technology because we saw it as a means to an end to deliver high efficiency and performance.”
Figure 1 Balakrishnan talked about his company’s GaN history and future roadmap at APEC 2024. Source: Power Integrations
That was quite a revelation because, according to Omdia, Power Integrations was the number one supplier of GaN power semiconductors in 2022, with nearly 17% market share. Moreover, in October 2023, Power Integrations unveiled a 1,250 V GaN IC; it claims power conversion efficiency as high as 93% while enabling highly compact flyback power supplies that can deliver up to 85 W without a heatsink.
Earlier, in March 2023, the Silicon Valley-based power semiconductor supplier released a 900-V GaN IC as part of its InnoSwitch3 family of flyback switcher ICs. It delivers up to 100 W with better than 93% efficiency and eliminates the need for heat sinks.
Figure 2 The 1,250-V GaN power supply IC is part of the company’s InnoSwitch flyback switcher ICs. Source: Power Integrations
Power Integrations claims to be the first to market with high-volume shipments of GaN-based power-supply ICs in 2019. A GaN switch, integrated with a controller and everything else in a single package, was first used in a notebook adapter design. “Two customers were very suspicious, saying there is no way you can have that level of efficiency with silicon,” Balakrishnan told the APEC audience. “So, we had to tell them under a non-disclosure agreement (NDA).”
“Efficiency is going to be the mantra in power electronics for a long time,” he added. Balakrishnan also said that GaN will eventually be less expensive than silicon for high-voltage switches. “There is no fundamental reason why it won’t be cost-effective in the long run.”
However, he clarified that GaN will replace silicon in certain areas. “Everybody thinks it will replace silicon, but GaN won’t replace silicon in controllers and digital circuitry,” he added. Balakrishnan and his engineers at Power Integrations also believe that GaN will get to the point where it’ll be very competitive with SiC while being less expensive to build.
As Balakrishnan noted, GaN has been talked about for a long time, but the challenge was operating reliably on high voltage. It’s ascent to voltages as high as 900 V, 1,250 V, and potentially even higher voltages shows that GaN is ready for commercial limelight.
Consequently, stakes for GaN semiconductor players, including Power Integrations, are getting higher as well.
Related Content
- SiC and GaN Drive Vehicle Electrification
- GaN prolongs short-circuit withstand time
- Gallium Nitride (GaN) technology overview
- The Next Generation of GaN for Electrification
- A brief history of gallium nitride (GaN) semiconductors
The post Power Integrations’ gallium nitride (GaN) story appeared first on EDN.
Anritsu and NTT Collaborate to Showcase End-to-End 400G Testing for IOWN Open APN at OFC2024
Anritsu Corporation, in collaboration with NTT, will participate in the “OFCnet” state-of-the-art network demonstration environment at the Optical Fiber Communication Conference and Exhibition 2024 (OFC2024) to be held in San Diego, USA, from March 26 to March 28, 2024. We will showcase 400G Testing that supports IOWN Open APN[*1].
The demand for interconnection bandwidth between data centres has greatly increased due to the rapid spread of generative AI and cloud services, as well as advances in DX (Digital Transformation). To realize a Datacenter Exchange (DCX) that connects remotely distributed data centres while featuring ultra-high capacity, ultra-low latency, and ultra-low power consumption, the IOWN Global Forum has proposed the Open All-Photonic Network (Open APN) as a new network infrastructure.
At our exhibition, the IOWN Networking Hub (Booth 912), an interconnected booth utilizing OFCnet, will showcase an example Datacenter Exchange (DCX) based on the IOWN APN in a multi-vendor configuration. 400G optical transceivers compliant with the OpenZR+[*2] MSA will be mounted on data centre switches, being interconnected through an OpenROADM network constructed in an adjacent booth, in accordance with OpenROADM MSA[*3] and OpenLab@ University of Texas at Dallas (UTD). Anritsu will provide two interconnected compact and lightweight handheld measuring instruments, MT1040A, that will simultaneously transmit and receive high-bandwidth 400-Gbps traffic, thereby demonstrating the end-to-end performance of the multi-vendor network. The MT1040A flexibly supports standard protocols such as 400G Ethernet, OpenZR+, OpenROADM, and more. It provides real-time measurements of the physical layer (Layer 1) Pre/Post FEC BER, as well as Ethernet (Layer 2) latency and throughput.
Through this collaboration, Anritsu will contribute to forums such as the IOWN Global Forum, Open ROADM, and OpenZR+, with the realization of a data center exchange (DCX) based on the IOWN Open APN architecture. In addition, we will contribute to the construction of automated systems used for orchestration that integrate higher-level network management.
Product Details MT1040A Network Master Pro / MU104014B 400G (QSFP-DD) multi-rate moduleMT1040A is a B5 size 400G handheld tester with excellent expandability and operability. It is a touch panel-operated field measurement instrument equipped with a 9-inch screen that is small enough to carry with a single hand. It supports a range of interfaces from 10M up to 400G.
MU104014B is the test module and has the following futures to test 400ZR/ZR+
- Powerful hardware for easy handling 400ZR/ZR+ transceivers
- Flexible Settings for All Network Environments
- Grid, Wavelength, Tx Power setting
- Coherent monitoring (OSNR, SOP, CD, etc.) via OIF CMIS
- Media-side FEC monitoring (PreFEC BER) via OIF CMIS
- 1x 400G, 4x 100G, 2x 100G, 1x 100G client signal
- Flexible Layer-2 to Layer-4 configuration
- History Function Monitoring Live Network
- Auto-save all of the results at a minimum of 1 second
- CSV output for detailed analysis and comparison
*1 Open APN
Abbreviation for Open All-Photonic Network – an open architecture proposed by the IOWN Global Forum (IOWN GF). It features low power consumption, high capacity, and low latency by configuring an entire section with a photonic network.
*2 OpenZR+
A transceiver interface standard is used mainly in data centre interconnect (DCI). It supports data rates of 100G, 200G, 300G, and 400G, and supports large-scale links of over 120 km with OFEC (forward error correction). Facilitates lower-cost connections between data centres than conventional wavelength division multiplexing (WDM) systems.
*3 OpenROADM MSA
Abbreviation for OpenROADM Multi-Source Agreement, the international organization established to promote OpenROADM.
OpenROADM specifies interconnection specifications for optical transmission equipment (ROADM), optical transponders, and detachable optical components, as well as YANG data model specifications, and defines interfaces for realizing interconnection and interoperability between each functional part of an optical transmission network in a multi-vendor environment.
The post Anritsu and NTT Collaborate to Showcase End-to-End 400G Testing for IOWN Open APN at OFC2024 appeared first on ELE Times.
Renesas Introduces Industry’s First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core
- CPU: RISC-V core at 48MHz, 3.27 Coremark/MHz
- Memory: 128KB code flash, 16KB SRAM (12KB and ECC SRAM 4KB) and 4KB data flash
- Power Consumption: 162µA/MHz (Active power), 0.3µA (SW Standby), 4µs (Standby wakeup)
- Serial communications interfaces: UART, SPI, I2C, SAU
- Analog peripherals: 12-bit ADC and 8-bit DAC
- Temperature range: -40°C to 125°C (Ta)
- Operating voltage range: 1.6 to 5.5V
- Packages: 16 WLCSP, 24/32/48 QFN package (QFP option)
The post Renesas Introduces Industry’s First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core appeared first on ELE Times.
IQE expands portfolio of epiwafers for high-speed optical connectivity
Accelerating the Adoption of AI Applications, Nuvoton Technology Introduces an Endpoint AI Product Platform Based on Microcontrollers and Microprocessors
Nuvoton Technology introduces an endpoint AI platform based on microcontrollers, expanding the AI ecosystem into the microcontroller domain. This solution is based on Nuvoton’s newly designed microcontrollers and microprocessors, including the NuMicro MA35D1, NuMicro M467, and the NuMicro M55M1 series equipped with Arm Ethos-U55 NPU. Nuvoton provides a complete software stack and development tools to facilitate the rapid deployment of advanced machine learning and deep learning models, leveraging advantages such as low power consumption and cost-effectiveness to accelerate the adoption of AI applications, enhancing productivity, and improving human life.
As a leading microcontroller platform provider, Nuvoton not only offers advanced hardware chips but also provides developers with complete software development tools, significantly improving development efficiency. NuEdgeWise is an easy-to-use graphical Python machine learning development tool that provides rich machine learning sample code covering processes such as data collection, labeling, model training, and validation, making the machine learning development process easier.
Nuvoton’s latest microcontroller endpoint AI platform is designed to elevate a wide array of applications, including smart home, security access control, smart city, industrial automation, smart agriculture, interactive toys, fitness equipment, and wearable devices, by infusing embedded system products with advanced AI capabilities.
Endpoint AI microcontroller with Ethos-U55 NPU: NuMicro M55M1
The new NuMicro M55M1 series microcontroller is an innovative Endpoint AI solution that integrates comprehensive microcontroller features, including control, connectivity, security, and advanced machine learning inference capabilities. The M55M1 microcontroller features a 200 MHz Arm Cortex-M55 CPU and a 200 MHz Arm Ethos-U55 NPU, providing machine learning inference capability and supporting CNN and RNN operations. It includes built-in 1.5 MB SRAM and 2 MB flash memory and can expand HYPERRAM or HYPERFLASH via the HYPERBUS interface. To enhance the overall performance of application systems, the M55M1 microcontroller incorporates three unique features to optimize system performance, security, and power consumption. Firstly, it enables continuous operation of image sensors, microphones, and various sensors in a low-power sleep mode, allowing for constant monitoring of predefined events such as personnel presence or significant sound and vibration detection. Secondly, it stores machine learning model data in an area accessible only to the NPU but not to the CPU, to prevent malicious programs from stealing model data and thus protect intellectual property. Lastly, the M55M1 also implements sine and cosine hardware circuits, which are defined within Arm’s custom instructions for easy invocation by software. These unique features of M55M1 empower developers to develop endpoint AI applications that achieve performance, power efficiency, and security.
High-performance edge industrial IoT series: NuMicro MA35D1
The NuMicro MA35D1 series heterogeneous multicore microprocessor is designed to meet the high-end industrial IoT requirements, featuring dual-core Arm Cortex-A35 64-bit processors with a maximum frequency of 800 MHz and a 180 MHz Arm Cortex-M4F core. Combined with a USB camera and CNN models, MA35D1 can perform endpoint AI tasks such as object detection.
The Ethernet/Crypto MCU with excellent security and connectivity: NuMicro M467
The M467 series features a 200 MHz Arm Cortex-M4F core with a built-in DSP instruction set and a single-precision floating-point unit (FPU). With the tinyML software technology, the M467 can perform various endpoint AI applications, such as gesture recognition, equipment anomaly detection, and keyword spotting. The M467 series microcontrollers have also participated in the MLPerf Tiny Benchmark test, demonstrating excellent inference speed across four endpoint AI tasks.
Complete machine learning development tools – Accelerating the implementation of AI applications
In addition to innovative microcontroller specifications, Nuvoton also supports a complete machine-learning software development stack for developers to develop machine-learning applications. The software stack includes NuEdgeWise Python development environment and machine learning sample code, Tensorflow machine learning model training framework, Vela neural network compiler dedicated to Ethos NPU, Tensorflow Lite for microcontroller inference framework, Arm CMSIS-NN machine learning library, and Ethos-U55 NPU driver.
Nuvoton’s endpoint AI microcontrollers enhance products across a diverse range of applications – including smart home, security access control, smart city, industrial automation, smart agriculture, interactive toys, fitness equipment, and wearable devices – by seamlessly integrating AI capabilities to deliver added value.
The post Accelerating the Adoption of AI Applications, Nuvoton Technology Introduces an Endpoint AI Product Platform Based on Microcontrollers and Microprocessors appeared first on ELE Times.
Lumentum enhances performance of 800ZR+ transceivers for broader applications
TRUMPF applies proprietary subwavelength surface-grating technology to datacom VCSELs
Microchip Technology Expands TrustFLEX Family with CEC1736 Real-time Platform Root of Trust Devices
TrustFLEX devices along with the Trust Platform Design Suite tool will simplify the enablement of the root of trust from concept to production in a wide range of applications
As technology and cybersecurity standards continue to evolve, Microchip Technology is helping make embedded security solutions more accessible with its CEC1736 TrustFLEX devices. The CEC1736 Trust Shield family is a microcontroller-based platform root of trust solution enabling cyber resiliency for data centres, telecom, networking, embedded computing and industrial applications. Now, as part of the TrustFLEX platform, the devices are partially configured and provisioned with Microchip-signed Soteria-G3 firmware to reduce the development time needed to integrate the platform root of trust. These devices also help fast-track the provisioning of required cryptographic assets and signed firmware images, simplifying the process of secure manufacturing as required by the National Institute of Standards and Technology (NIST) and Open Compute Project (OCP) standards.
Specifically designed to meet NIST 800-193 platform resiliency guidelines, as well as OCP requirements, CEC1736 TrustFLEX devices can support security features necessary to enable hardware root of trust across various markets. The Trust Platform Design Suite tool will allow customers to personalize platform-specific configuration settings, including unique credentials, to support any application, host processor or SoC that boots out of an external SPI Flash device to extend the root of trust in the system.
“Microchip has led our industry in streamlining secure provisioning from design to deployment for devices and platforms of all scales. This rich range of solutions now include OCP-compliant root of trust devices,” said Nuri Dagdeviren, corporate vice president of Microchip’s secure computing group. “With the pre-configured CEC1736 TrustFLEX family, we are helping lower the barrier of entry and making it easier for customers to implement platform root of trust and enable faster prototyping and speed to market.”
Modern firmware security features enabled on the CEC1736 TrustFLEX—like SPI bus monitoring, secure boot, component attestation and lifecycle management—can keep both the pre-boot and real-time (time of check and time of use) environments shielded from both in-person and remote threats.
The highly configurable, mixed-signal, advanced I/O CEC1736 controllers integrate a 32-bit 96 MHz Arm Cortex-M4 processor core with closely coupled memory to offer optimal code execution and data access.
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Vertiv Joins the NVIDIA Partner Network
Vertiv brings its high-density power and cooling infrastructure expertise to the NVIDIA Partner Network to better support adoption of accelerated computing and AI workloads
Vertiv, a global leader in critical infrastructure and continuity solutions, is now a Solution Advisor:Consultant partner in the NVIDIA Partner Network (NPN), providing wider access to Vertiv’s experience and a full portfolio of power and cooling solutions.
NPN is a global program for technology partners who offer solutions built on or powered by NVIDIA technologies. Among leading software vendors, cloud service providers, solution providers, and system integrators, Vertiv joins the network to offer its expertise in addressing the unique infrastructure challenges presented by accelerated computing. NPN provides access to a range of benefits, including technical support, training, and collaboration opportunities, helping partners deliver innovative solutions to their customers.
“Vertiv has collaborated with NVIDIA in research, development, and engineering for multiple years, designing innovative products and solutions that support the deployment of NVIDIA technologies globally,” said Giordano (Gio) Albertazzi, CEO at Vertiv. “We have combined our leadership in power and cooling solutions with NVIDIA’s cutting-edge platforms to help meet the demands of the most compute-intensive applications and support the deployment of AI infrastructure across the globe. Now, we are collaborating to build state-of-the-art liquid cooling solutions for next-gen NVIDIA accelerated data centers powered by GB200 NVL72 systems.”
Vertiv’s high-density power and cooling solutions are designed to support the next generation of GPUs running the most compute-intensive AI workloads safely, at optimal performance and with high availability. Vertiv’s portfolio of liquid cooling technologies, such as Vertiv Liebert XDU coolant distribution units, Vertiv Liebert XDM split indoor chillers, and Vertiv Liebert DCD rear-door heat exchangers, cover a wide range of application requirements. The Vertiv Geist rack power distribution units (PDUs) family has been extended to accommodate higher power draw within the rack, minimizing footprint while maintaining high efficiency.
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My workbench
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The ingredients for a few good hours
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