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With over 8.9 million micromirrors, TI’s DLP991UUV digital micromirror device (DMD) enables maskless digital lithography for advanced packaging. Its 4096×2176 micromirror array, 5.4-µm pitch, and 110-Gpixel/s data rate remove the need for costly mask technology while providing scalability and precision for increasingly complex designs.

The DMD is a spatial light modulator that controls the amplitude, direction, and phase of incoming light. Paired with the DLPC964 controller, the DLP991UUV DMD supports high-speed continuous data streaming for laser direct imaging. Its resolution enables large 3D-print build sizes, fine feature detail, and scanning of larger objects in 3D machine vision applications.

Offering the highest resolution and smallest mirror pitch in TI’s Digital Light Processing (DLP) portfolio, the DLP991UUV provides precise light control for industrial, medical, and consumer applications. It steers UV wavelengths from 343 nm to 410 nm and delivers up to 22.5 W/cm² at 405 nm.

Preproduction quantities of the DLP991UUV are available now on TI.com.

DLP991UUV product page 

Texas Instruments 

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AIchip Technologies and Ayar Labs unveiled a co-packaged optics (CPO) solution for multi-rack AI clusters, providing extended reach, low latency, and high radix. The joint development tackles AI infrastructure data-movement bottlenecks by replacing copper interconnects with CPO in large-scale accelerator deployments.

The offering integrates Ayar’s TeraPHY optical engines with AIchip’s advanced packaging on a common substrate, bringing optical I/O directly to the AI accelerator interface. This enables over 100 Tbps of scale-up bandwidth per accelerator and supports more than 256 optical scale-up ports per device. TeraPHY is also protocol agnostic, allowing flexible integration with customer-designed chiplets and fabrics.

The co-packaged solution scales multi-rack networks without the power and latency penalties of pluggable optics by shortening electrical traces and placing optical I/O close to the compute core. With UCIe support and flexible protocol endpoints at the package boundary, it integrates alongside compute tiles, memory, and accelerators while maintaining performance, signal integrity, and thermal requirements.

Both companies are working with select customers to integrate co-packaged optics into next-generation AI accelerators and scale-up switches. They will provide collateral, reference architectures, and build options to qualified design teams.

Ayar Labs 

The post Co-packaged optics enables AI data center scale-up appeared first on EDN.

Purpose-built for Lantronix Open-Q system-on-modules (SOMs), EdgeFabric.ai is a no-code development platform for designing and deploying edge AI applications. According to Lantronix, it helps customers move AI from prototype to production in minutes instead of months, without needing a team of AI experts.

The visual orchestration platform integrates with Open-Q hardware and leading AI model ecosystems, automatically configuring performance across Qualcomm GPUs, DSPs, and NPUs. It streamlines data pipelines with drag-and-drop workflows for AI, video, and sensors, while delivering real-time visualization. Prebuilt templates support common use cases such as surveillance, anomaly detection, and safety monitoring.

EdgeFabric.ai auto-generates production-ready code in Python and C++, making it easy to build and adjust pipelines, fine-tune parameters, and adapt workflows quickly.

Learn more about the EdgeFabric.ai platform here. For details on Open-Q SOMs, visit SOM solutions. Lantronix also offers engineering services for development support.

Lantronix

The post Platform speeds AI from prototype to production appeared first on EDN.

RA8T2 MCUs from Renesas integrate dual processors for real-time motor control in advanced factory automation and robotics. They pair a 1-GHz Arm Cortex-M85 core with an optional 250-MHz Cortex-M33 core, combining high-speed operation, large memory, timers, and analog functions on a single chip.

The Cortex-M85 with Helium technology accelerates DSP and machine-learning workloads, enabling AI functions that predict motor maintenance needs. In dual-core variants, the embedded Cortex-M33 separates real-time control from general-purpose tasks to further enhance system performance.

RA8T2 devices integrate up to 1 MB of MRAM and 2 MB of SRAM, including 256 KB of TCM for the Cortex-M85 and 128 KB of TCM for the Cortex-M33. For high-speed networking in factory automation, they offer multiple interfaces, such as two Gigabit Ethernet MACs with DMA and a two-port EtherCAT slave. A 32-bit, 14-channel timer delivers PWM functionality up to 300 MHz.

The RA8T2 series of MCUs is available now through Renesas and its distributors.

RA8T2 product page

Renesas Electronics 

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Omnivision’s OV50R40 50-Mpixel CMOS image sensor delivers single-exposure HDR up to 110 dB with second-generation TheiaCel technology. It also reduces power consumption by ~20% compared with the previous-generation OV50K40, enabling longer HDR video capture.

Aimed at high-end smartphones and action cameras, the OV50R40 achieves ultra-high dynamic range in any lighting. Built on PureCel Plus‑S stacked die technology, the color sensor supports 100% coverage quad phase detection for improved autofocus. It features an active array of 8192×6144 with 1.2‑µm pixels in a 1/1.3‑in. format and supports premium 8K video with dual analog gain (DAG) HDR and on-sensor crop zoom.

The sensor also supports 4-cell binning, producing 12.5‑Mpixel resolution at 120 fps. For 4K video at 60 fps, it provides 3-channel HDR with 4× sensitivity, ensuring enhanced low-light performance.

The OV50R40 is now sampling, with mass production planned for Q1 2026.

OV50R40 product page 

Omnivision

The post Image sensor provides ultra-high dynamic range appeared first on EDN.

Прийнято Положення про систему запобігання плагіату, фабрикації та фальсифікації kpi чт, 10/02/2025 - 21:03

💥 ІІ Міжнародна підсумкова науково-практична онлайн конференція та ІІ Міжнародний конкурс студентських наукових робіт з англійської мови “Advances in Science and Technology” kpi чт, 10/02/2025 - 20:41

TI designed the new devices to provide cost-effective, high-speed sensorless control to household and industrial systems.

The relentless pursuit of performance in sectors such as AI, cloud computing, and autonomous driving is creating a heat crisis. As the next generation of processors demand more power in smaller spaces, the switched-mode power supply (SMPS) is being pushed to its thermal limit. SMPS’s integrated circuit (IC) packages have traditionally used a large thermal pad on the bottom side of the package, known as a die attach paddle (DAP), to dissipate the majority of the heat through the printed circuit board (PCB). But as power density increases, relying on only one side of the package to dissipate heat quickly becomes a serious constraint.

A thermally enhanced package is a type of IC package designed to dissipate heat from both the top and bottom surfaces. In this article, we’ll explore the standard thermal metrics of IC packages, along with the composition, top-side cooling methods, and thermal benefits of a thermally enhanced package.

Thermal metrics of IC packages

In order to understand what a thermally-enhanced package is and why it is beneficial, it’s important to first understand the terminology for describing the thermal performance of an IC package. Three foundational metrics of thermal resistance are the junction-to-ambient thermal resistance (RθJA), the junction-to-case (top) thermal resistance (RθJC(top)), and the junction-to-board thermal resistance (RθJB).

Thermal resistance measures the opposition to the flow of heat in a medium. In IC packages, thermal resistance is usually measured in Celsius rise per watt dissipated (°C/W), or how much the temperature rises when the IC dissipates a certain amount of power.

RθJA measures the thermal resistance between the junction (J) (the silicon die itself), and the ambient air (A) around the IC. RθJC(top) measures the thermal resistance specifically between (J) and the top (t) of the case (C) or package mold. RθJB measures the thermal resistance specifically between (J) and the PCB on which the package is mounted.

RθJA significantly depends on its subcomponents—both RθJC(top) and RθJB. The lower the RθJA, the better, because it clearly indicates that there will be a lower temperature rise per unit of power dissipated. Power IC designers spend a lot of time and resources to come up with new ways to lower RθJA. A thermally enhanced package is one such way.

Thermally enhanced package composition

A thermally enhanced package is a quad flat no-lead (QFN) package that has both a bottom-side DAP and a top-side cutout of the molding to directly expose the back of the silicon die to the environment. Figure 1 shows the gray backside of the die for the Texas Instruments (TI) LM61495T-Q1 buck converter.

Figure 1 The LM61495T-Q1 buck converter in a thermally enhanced package. Source: Texas Instruments

Exposing the die on the top side of the package does two things: it lowers the RθJC(top) compared to an IC package that completely molds over the die, and enables a direct connection between the die and an external heat sink, which can significantly reduce RθJA.

RθJC(top) in a thermally enhanced package

RθJC(top) allows heat to escape more effectively from the top of the device. Typically, heat escapes through the package mold and then to the air, but in a thermally enhanced package, it escapes directly to the air. This helps reduce the device temperature and reduces the risk of thermal shutdown and long-term heat stress issues. The thermally enhanced package also has a lower RθJA, which makes it possible for a converter to handle more current and operate in hotter environments.

Figure 2 shows a series of IC junction temperature measurements taken across output current for both the LM61495T-Q1 in the thermally enhanced package and TI’s LM61495-Q1 buck converter in the standard QFN package under two common operating conditions.

VOUT = 5V

FSW = 400kHz

TA = 25°C

Figure 2 Output current vs. junction temperature for the LM61495-Q1 and LM61495T-Q1 with no heat sink. Source: Texas Instruments

Clearly, even with no heat sink attached, the thermally enhanced package runs slightly cooler, simply because more heat is dissipating out of the top of the package and into the air. The RθJA for a thermally enhanced package is slightly lower, demonstrating with certainty that, even if only marginally, this package type will provide better thermals compared to the standard QFN with top-side molding, even without any additional thermal management techniques. Table 1 lists the official thermal metrics found in both devices’ data sheets.

Part number	Package type	RθJA (evaluation module)(°C/W)	RθJC(top) (°C/W)	RθJB (°C/W)
LM61495-Q1	Standard QFN	21.6	19.2	12.2
LM61495T-Q1	Thermally enhanced package QFN	21	0.64	11.5

Table 1 Comparing data sheet-derived thermal metrics for the LM61495-Q1 and LM61495T-Q1. Source: Texas Instruments

Top-side cooling vs QFN

Combining its near-zero RθJC(Top) top side with an effective heat sink significantly reduces the RθJA of an IC in a thermally enhanced package. There are three significant improvements when compared to the same IC in a standard QFN package under otherwise similar operating conditions:

• Higher switching-frequency operation.
• Higher output-current capability.
• Operation at higher ambient temperatures.

For any SMPS under a given input voltage (VIN), output voltage (VOUT) condition and supplying a given output current, the maximum switching frequency will be thermally limited. Within every switching period, there are switching losses and conduction losses that dissipate as heat. Switching more frequently dissipates more power in the IC, leading to an increased IC junction temperature. This can be frustrating for engineers because switching at higher frequencies enables the use of a smaller buck inductor, and therefore a smaller overall solution size and lower cost.

Under the same operating conditions, using the thermally enhanced package and a heat sink, the heat dissipated in each switching period is now more easily channeled out of the IC, leading to a lower junction temperature and enabling a higher switching frequency without hitting the IC’s junction temperature limit. Just don’t exceed the maximum switching frequency recommendation of the device as outlined in the data sheet.

The benefits of using a smaller inductor are especially pronounced in higher-current multiphase designs that require an inductor for every phase. Figure 3 shows a simplified four-phase design capable of supplying 24 A at 3.3 VOUT at 2.2 MHz using the TI LM64AA2-Q1 step-down converter. If the design were to overheat and the switching frequency had to be reduced to 400 kHz, you would have to replace all four inductors with larger inductors (in terms of both inductance and size), inflating the overall solution cost and size substantially.

Figure 3 Simplified schematic of a single-output, four-phase step-down converter design using the LM644A2-Q1 step-down converter in the thermally enhanced package. Source: Texas Instruments

Conversely, for any SMPS under a given VIN, VOUT condition, and operating at a specific switching frequency, the maximum output current will be thermally limited. When discussing the current limit of an IC, it’s important to clarify that for all high-side FET integrated SMPSs, there is a data sheet-specified high-side current limit that bounds the possible output current.

Upon reaching the current-limit setpoint, the high-side FET turns off, and the IC may enter a hiccup interval to reduce the operating temperature until the overcurrent condition goes away. But even before reaching the current limit, it is very possible for an IC to overheat from a high output-current requirement. This is especially true, again, at higher frequencies. As long as you don’t exceed the high-side current limit, using an IC in the thermally enhanced package with a heat sink can extend the maximum possible output current to a level at which the standard QFN IC alone would overheat.

There is another constant to make the thermally enhanced package versus the standard QFN package comparison valid, and that is the ambient temperature (TA). TA is a significant factor when considering how much power an SMPS can deliver before it starts to overheat.

For example, a buck converter may be able to easily do a 12VIN-to-5VOUT conversion and support a continuous 6 A of current while switching at 2.2 MHz when the TA is 25°C, but not at 105°C. So, there is yet a third way to look at the benefit that a thermally enhanced package can provide. Assuming the VIN, VOUT, output current, and maximum switching frequency are constant, a thermally enhanced package used with a heat sink can enable an SMPS to operate at a meaningfully higher TA compared to a standard QFN package with no heat sink.

Figure 4 uses a current derating curve to demonstrate both the higher output current capability and operation at a higher TA. In an experiment using the LM61495-Q1 and LM61495T-Q1 buck converters, we measured the output current against the TA in a standard QFN package without a heat sink and in a thermally enhanced package QFN connected to an off-the-shelf 45 x 45 x 15 mm stand-alone fin-type heat sink. Other than the package and the heat sink, all other conditions are constant: operating conditions, PCB, and measurement instrumentation.

VIN = 12V

VOUT = 3.3V

FSW = 2.2MHz

Figure 4 Output current vs. ambient temperature of the LM61495-Q1 with no heat sink and the LM61495T-Q1 with an off-the-shelf 45 x 45 x 15 mm stand-alone fin-type heat sink. Source: Texas Instruments

When TA reaches about 83˚C, the standard QFN package hits its thermal shutdown threshold, and the output current begins to collapse. As TA increases further, the device cycles into and out of thermal shutdown, and the maximum achievable output current that the device can deliver is necessarily reduced until TA reaches a steady 125˚C. At this point, the converter may not be able to sustain even 5 A without overheating.

Compare this to the thermally enhanced package QFN connected to a heat sink. The first instance of thermal shutdown now doesn’t occur until about 117˚C. That’s an increase in TA before hitting a thermal shutdown of 34˚C, or 40%. The LM61495-Q1 is a 10-A buck converter, meaning that its recommended maximum output current is 10 A. But in this case, with a thermally enhanced package and effective heat sinking, a continuous 11 A output was clearly achievable up to 117˚C – in other words, a 10% increase in maximum continuous output current even at a high TA.

Methods of top-side cooling

Figure 5, Figure 6, and Figure 7 show some of the most common methods of top-side cooling. Stand-alone heat sinks are simple and readily available in many different forms, materials, and sizes, but are sometimes impractical in small-form-factor designs.

Figure 5 Stand-alone fin-type heat sink, these are simple and readily available but sometimes impractical in small form factor designs. Source: Texas Instruments

Cold plates are very effective in dissipating heat but are more complex and costlier to implement (Figure 6).

Figure 6 Cold plate-type heat sink, these are very effective in dissipating heat but are more complex and costlier to implement. Source: Texas Instruments

Using the metal housing containing the power supply and the surrounding electronics as a heat sink is compact, effective, and relatively inexpensive if the housing already exists. As shown in Figure 7, this is done by creating a pillar or dimple that connects the IC to the housing to enable efficient heat transfer. For power supplies powering processors, it’s likely that this method is already helping dissipate heat on the processor. Adding an additional dimple or pillar that now gives heat-sink access to the power supply is often a simple change, making it a very popular method, especially for processor power.

Figure 7 Contact-with-housing heat sink where a pillar or dimple connects the IC to the housing to enable efficient heat transfer. Source: Texas Instruments

There are many ways to implement heat sinking, but that doesn’t mean that they are all equally effective. The size, material, and form of the heat sink matter. The type and amount of thermal interface material used between the IC and the heat sink matter, as does its placement. It is important to optimize all of these factors for the design at hand.

Comparing heat sinks

Figure 8 shows another current derating curve. It compares two different types of heat sinks, each mounted on the LM61495T-Q1. For reference, the figure includes the performance of the standard QFN package with no heat sink.

VIN = 24V

VOUT = 3.3V

FSW = 2.2MHz

Figure 8 Output current versus the ambient temperature of the LM61495-Q1 with no heat sink, the LM61495T-Q1 with an off-the-shelf 45 x 45 x 15 mm stand-alone fin-type heat sink, and with an aluminum plate heat sink. Source: Texas Instruments

For a visualization of these heat sinks, see Figure 9 and Figure 10, which show a top-down view of the PCB and a clear view of how the heat sinks are mounted to the IC and PCB. The heat sink shown in Figure 9 is a commercially available, off-the-shelf product. To reiterate, it is a 45 mm by 45 mm aluminum alloy heat sink with a base that is 3mm thick and pin-type fins that extend the surface area and allow omnidirectional airflow.

Figure 9 The LM61495T-Q1 evaluation board with the off-the-shelf 45 x 45 x 15 mm stand-alone fin-type heat sink. Source: Texas Instruments

Figure 10 shows a custom heat sink that is essentially just a 50 mm by 50 mm aluminum plate with a 2 mm thickness and a small pillar that directly touches the IC. This heat sink was designed to mimic the contact-with-housing method, as it is very similar in size and material to the types of housing seen in real applications.

Figure 10 The LM61495T-Q1 evaluation board with a custom aluminum plate heat sink to mimic the contact-with-housing method. Source: Texas Instruments

Under the same conditions, the stand-alone heat sink provides a major benefit compared to the standard QFN package with no heat sink. The standard QFN package hits thermal shutdown around 67°C TA. For the stand-alone heat-sink setup, thermal shutdown isn’t triggered until the TA reaches about 111°C, which is a major improvement. However, the aluminum plate heat-sink setup doesn’t hit thermal shutdown at all. With the aluminum plate setup, the converter is still able to supply a continuous 10-A current at the highest TA tested (125˚C), demonstrating both the importance of choosing the correct heat sink for the system requirements as well as the popularity of the contact-with-housing method.

Addressing modern thermal challenges

Power supply designers increasingly deal with thermal challenges as modern applications demand more power and smaller form factors in hotter spaces. Standard QFN packaging has long relied on dissipating the majority of generated heat through the bottom side of the package to the PCB. A thermally enhanced package QFN uses both the top and bottom sides of the package to improve heat flow out of the IC, essentially paralleling the thermal impedance paths and reducing the effective thermal impedance.

Combining a thermally enhanced package with effective heat sinking results in significant thermal benefits and enables higher-power-density designs. Because these benefits are derived from reducing the effective RθJA, designers can realize just one or all of these benefits in varying degrees. Increase the maximum switching frequency and reduce solution size and cost. Enabling a higher maximum output current for higher power conversion. Enable operation at a higher TA.

Jonathan Riley is a Senior Product Marketing Engineer for Texas Instruments’ Switching Regulators organization. He holds a BS in Electrical Engineering from the University of California Santa Cruz. At TI, Jonathan works in the crossroads of marketing and engineering to ensure TI’s Switching Regulator product line continues to evolve ahead of the market and enable customers to power the technologies of tomorrow.

 Related Content

• Power Tips #101: Use a thermal camera to assess temperatures in automotive environments
• IC packages and thermal design
• Keeping space chips cool and reliable
• QFN? QFP? QFWHAT?

Additional resources

• Read the TI application note, “Semiconductor and IC Package Thermal Metrics.”
• Check out these TI application reports:
  • “AN-2020 Thermal Design by Insight, Not Hindsight.”
  • “AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages.”
• See the TI application brief, “PowerPAD Made Easy.”
• Watch the TI video resource, “Improve thermal performance using thermally enhanced packaging (TEP).”

The post Thermally enhanced packages—hot or not? appeared first on EDN.

Where do HDDs stand after the advent of SDDs? Are they a thing of the past now, or do they still have a life? While HDDs store digital data, what’s their relation to analog technology? Here is a fascinating look at HDD’s past, present, and future, accompanied by data from the industry. The author also raises a very valid point: while their trajectory is very similar to the world of semiconductors, why don’t HDDs have their own version of Moore’s Law?

Read the full article at EDN’s sister publication, Planet Analog.

Related Content

• When big data crashes against small problems
• The Hottest Data-Storage Medium Is…Magnetic Tape?
• Audio cassette tapes are coming back, this time for mass storage

The post Past, present, and future of hard disk drives (HDDs) appeared first on EDN.

Ion implantation system maker Axcelis Technologies Inc of Beverly, MA, USA and epitaxial deposition and process equipment maker Veeco Instruments Inc of Plainview, NY, USA have entered into a definitive agreement to combine in an all-stock merger, forming a a semiconductor equipment supplier worth about $4.4bn (based on Axcelis’ and Veeco’s closing share prices as of end-September, and outstanding debt as of end-June) offering an expanded product portfolio for complementary, diversified and growing end markets. On a pro-forma basis for fiscal year 2024, the combined company generated revenue of $1.7bn, non-GAAP gross margin of 44% and adjusted EBITDA of $387m (not including expected cost and revenue synergies)...

NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and developed and previously manufactured high-power industrial blue lasers — has implemented a dual-CEO structure, complementing Alessandro Zamboni’s role as executive chairman and supports the company’s ongoing transformation plan. The plan aims to achieve revenue growth starting in Q4 2025 through strategic acquisitions and international alliances, while also managing increased organizational complexity...

День захисників і захисниць України kpi чт, 10/02/2025 - 10:49

Курсанти ІСЗЗІ КПІ ім. Ігоря Сікорського пройшли стажування із кіберзахисту в Литві kpi чт, 10/02/2025 - 10:31

Manufacturing today depends on processes that balance speed, precision, and scalability. Among them, injection molding has become indispensable for industries ranging from healthcare to consumer goods. Its ability to deliver identical, high-quality parts in massive volumes makes it one of the most reliable and cost-effective production methods. But what makes this process so vital, and how exactly does it work?

Understanding Injection Molding

Fundamentally, injection molding is about thrusting molten material into a precisely crafted mold, where it solidifies and takes on its final shape. Plastics are the stalwart of the operation, but producers also apply it to metals and testing uses in new industries. The greatest strength of injection molding is consistency and efficiency once a mold has been made, it can be used to churn out hundreds of thousands of duplicate parts with little deviation.

Unlike subtractive methods such as CNC machining, injection molding is less wasteful of material and can be more flexible in terms of design, with the ability to create everything from small medical devices to large automotive panels.

Industries that Depend on Injection Molding

• Food and Beverage

From yogurt cups to condiment containers, the packaging business relies heavily on injection molding for its light, disposable products. Moving beyond packaging, researchers at one of the University are testing whether this process can be used to mass-produce plant-based meat substitutes, demonstrating how versatile the method can be. In contrast to 3D printing, injection molding offers cost savings and is able to maintain taste and texture in food applications.

• Healthcare and Medical Devices

The medical sector applies injection molding in the production of syringes, implants, and wearables. Due to the stringent regulatory conditions, manufacturers tend to include sensors within the mold to check for temperature and pressure, allowing for perfect outcomes. Robotic equipment is also utilized, which removes faulty components automatically to ensure high levels of safety in patient-care products.

• Sporting Goods and Consumer Products

Leisure goods used daily picnic tableware, coolers, and even high-precision golf clubs are produced with this process as well. Metal injection molding enables golf club manufacturers to create products that improve performance and feedback. Molding single-piece coolers thinner but stronger walls speaks to the process’s efficiency and resilience.

The Injection Molding Process

In any industry and whether small, medium, or large, the injection molding process adheres to a systematic approach:

1. Material Selection – Companies select metals or polymers according to strength, flexibility, durability, or resistance characteristics. Polypropylene is suitable for packaging food, while polycarbonate resists UV exposure for use outside.
2. Design of Mold – Designers make precise steel or aluminum molds with orientation, core, cavity, and mold base in mind. CNC machining is usually employed to cut the mold exactly.
3. Clamping – A clamping mechanism provides pressure to keep the mold halves tightly closed, preventing any leak during the process of injection.
4. Injection – Pellets are melted into molten form, blended by a reciprocating screw, and injected into the mold at regulated velocities and pressures.
5. Dwelling – Pressure is held for a temporary period to guarantee the molten material fills all the cavities of the mold.
6. Cooling – The part solidifies within the mold, a phase often constituting the bulk of cycle time.
7. Opening and Removal – After cooling, the mold is opened and ejector pins force the part out. Any remaining flash material is removed and sometimes recycled.
8. Inspection – Finished parts are visually inspected and tested to detect defects, maintaining consistent quality control.

Why Injection Molding Remains Essential

The scalability, accuracy, and versatility to perform in various industries of the process make injection molding a corner stone of contemporary manufacturing. From life-saving medical technologies to common consumer products, the process continues to transform with automation, robotics, and intelligent sensors, which guarantee ever-greater levels of quality and efficiency.

As industries seek faster, more sustainable, and more innovative ways to produce goods, injection molding remains a cornerstone technology that bridges traditional manufacturing with future possibilities.

(This article has been adapted and modified from content on Revolutionized.)

The post Injection Molding: The Backbone of Modern Mass Production appeared first on ELE Times.

Simple linear and switching voltage regulators with feedback networks of the type shown in Figure 1 are legion. Their output voltages are the reference voltage at the feedback (FB) pin multiplied by 1 + Rf / Rg. Recommended values of Cf from 100 pF to 10nF increase the amount of feedback at higher frequencies, or at least ensure it is not reduced by stray capacitances at the feedback pin.

Figure 1 The configurations of common regulators and their feedback networks. A linear regulator is shown on the left and a switcher on the right.

Modifying this structure to incorporate PWM control of the output voltage requires some thought, and both Stephen Woodward and I have presented several Design Ideas (DIs) that address this.

Wow the engineering world with your unique design: Design Ideas Submission Guide

I’ve suggested disconnecting Rg from ground and driving it from a heavily filtered (op-amp-based) PWM signal supplied by a 74xx04-type logic inverter. Although this can result in excellent ripple suppression, it has a disadvantage—the need for an inverter power supply, which does not degrade the accuracy of the regulator’s 1% or better reference voltage.

Stephen has proposed switching the disconnected Rg leg between ground and open with a MOSFET. The beauty of this is that no new reference is needed. Although the output voltage is no longer a linear function of the PWM duty cycle, a simple software-based lookup table renders this a mere inconvenience. (Yup, “we can fix it in software!”)

A general scheme to mitigate PWM controller-induced ripple should be flexible enough to accommodate different regulators, regulator reference voltages, output voltage ranges, and PWM frequencies. In selecting one, here are some possible traps to be aware of:

• Nulling by adding an out-of-phase version of the ripple signal is at the mercy of component tolerances.
• Cheap ceramics, such as the ubiquitous X7R, have DC voltage and temperature-sensitive capacitances. If used, the circuit must tolerate these undesirable traits.
• Schemes which connect capacitors between ground and the feedback pin will reduce loop feedback at higher frequencies. The result could be degradation of line and load transient responses.

Circuit

With this in mind, consider the circuit of Figure 2, capable of operation from 0.8 V to a little more than 5 V.

Figure 2 A specific instance of a PWM-controlled regulator with ripple suppression. Only a linear regulator is shown, but the adaptation for switcher operation entails only the addition of an inductor and a filter capacitor.

The low capacitance MOSFET has a maximum on-resistance of under 2 Ω at a VGS of 2.5 V or more. Cg1 and Cg2 see maximum DC voltages of 0.8 V (up to 1.25 V in some regulators). Their capacitive accuracies are not critical, and at these low voltages, they barely budge when 10-V or higher-rated X7R capacitors are employed.

Cf can see a significant DC voltage, however. Here, you might get away with an X7R, but a 10-nF (voltage-insensitive) C0G is cheap. The value of Cf was chosen to aid in ripple management. If it were not present, the ripple would be larger and proportional to the value of Rf. With a 10-nF Cf, larger values of Rf for higher output voltages would have no effect on the PWM-induced ripple; smaller ones could only reduce it. The largest peak-to-peak ripple occurs at duty cycles from 30 to 40%.

The filtering supplied by the three capacitors produces a sinusoidal ripple waveform of amplitude 5.7 µV peak-to-peak. For a 16-bit ADC with a full scale of 5 V, the peak-to-peak amplitude is less than 1 LSbit.

Flexibility

You might have a requirement for a wider or narrower range of output voltages. Feel free to modify Rf accordingly without a penalty in ripple amplitude.

Ripple amplitude will scale in proportion to the regulator’s reference voltage. The design assumes a regulator whose optimum FB-to-ground resistance is 10 kΩ. If it’s necessary to change this for the regulator of your choice, scale the three Rg resistors by the same factor Z. Because the resistors and three capacitors implement a 3rd order filter, the ripple will scale in accordance with Z-3. To keep the same ripple amplitude, scale the three capacitors by 1/Z. You might want to scale the capacitors’ values for some other reason, even if the resistors are unchanged.

Changing the PWM frequency by a factor F will change the ripple amplitude by a factor of F-3. But too high a frequency could encounter accuracy problems due to the parasitic capacitances and unequal turn-on/turn-off times of the MOSFET.

Some regulators might not tolerate a Cf of a value large enough to aid in ripple suppression. Usually, these will tolerate a resistor Rcf in series with Cf. In such cases, ripple will be increased by a factor K equal to the square root of ( 1 + Rcf · 2π · fPWM · Cf ), and the waveform might no longer be sinusoidal. But increasing Cg1 and Cg2 by the square root of K will compensate to yield approximately the same suppression as offered by the design with Rcf equal to 0. If all else fails, there is always the possibility of adding an Rg4 and a Cg3 to provide another stage of filtering.

Tying it all together

 A flexible approach has been introduced for the suppression of PWM control-induced ripple in linear and switching regulators. Simple rules have been presented for the use and modification of the Figure 2 circuit for operation over different output voltage ranges, PWM frequencies, preferred resistances between ground and the regulator’s feedback pin, and tolerances for moderately large capacitances between the FB pins and the output.

The limitations of capacitors with sensitivities to DC voltages are recognized. These components are used appropriately and judiciously. Dependency on component matching is avoided. Standard feedback network structures are maintained or, at worst, subjected to minor modifications only; specifically, feedback at higher frequencies is not reduced from that recommended by the regulator manufacturer. This maintains the specified line and load transient responses.

Addendum

Once again, the Comments section of DIs has shown its worth. And it’s Deja vu all over again; value was provided by the redoubtable Stephen Woodward. In an earlier DI, he pointed out that regulators generally do not tolerate negative voltages at their feedback pins. But if there is a capacitor Cf of more than a few hundred picofarads connected from the output to this pin, as I have recommended in this DI, and the output is shorted or rapidly discharged, this capacitor could couple a negative voltage to that pin and damage the part. To protect against this, add the components shown in the following figure.

Figure 3 Add these components to protect the FB pin from output rapid negative voltage changes.

In normal operation and during startup, the CUS10S30 Schottky diode looks like an open circuit and it, Cc, and the 1 MΩ resistor have a negligible effect on circuit operation. Cc prevents the flow of diode reverse current, which could otherwise produce output voltage errors. If Vout transitions to ground rapidly, Cc and the diode prevent any negative voltage from appearing at the junction of the capacitors. Rc provides a cheap “just in case” limit of the current into the FB pin from that voltage transient if it somehow saw a negative voltage. (Check the maximum FB pin current to ensure that no significant error-inducing voltages develop across Rc.) When the circuit has settled, the voltage across Cc is discharged, and the circuit is ready to restart normally.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

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The post Improve PWM controller-induced ripple in voltage regulators appeared first on EDN.

Всеукраїнський день бібліотек 2025 KPI4U-1 ср, 10/01/2025 - 18:08

Нове укриття у 5 корпусі КПІ ім. Ігоря Сікорського! kpi ср, 10/01/2025 - 18:02

Frequent contributor Christopher Paul recently provided us with a painstakingly conservatively error-budget-analyzed Design Idea (DI) for a state-of-the-art pursuit of a 16-bit-perfection PWM DAC.

The DI presented below, while shamelessly kibitzing on Chris’ excellent design process and product, should in no way be construed as criticism or even a suggested modification. It is neither. It’s just a voyage into the strange land of ultimate precision.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In his pursuit of perfect precision, Christopher creatively coped with the limitations of the “art.” Perhaps the most intractable of these limitations in the context of his design was the temperature coefficient of available moderately priced precision voltage references. His choice of the excellent 35xxx family of references, for example, exhibits a temperature coefficient (tempco) of 12 ppm/°C = 0.8 lsb/°C = 55 lsb over 0 to 70°C, reducing this element of conversion precision to only an effective 10.2 bits. 

Since that was more than an order of magnitude worse than other error factors (e.g., DNL, INL, ripple) in Christopher’s simple and elegant (and nice!) design, it got me musing about what possibilities might exist to mediate it. 

Let me candidly admit upfront that my musing was unconstrained by a concern for the practical damage such possibilities might imply towards the simplicity and elegance of the design. This included damage, such as doubling the parts count and vastly increasing the power consumption.

But with those caveats out of the way, here we go.

The obvious possibility that came to mind, of course, was what if we reduced the importance of thermal instability of the reference by the simple (and brute-force) tactic of putting it in a thermostat? Over the years, we’ve seen lots of DIs for using transistors as sensors and heaters (sometimes combining both functions in the same device) for controlling the temperature of single components. Figure 1 illustrates the thermo-mechanics of such a scheme for this application. 

Figure 1 Thermally coupling the transistor sensor/heater to the DAC voltage reference to stabilize its temperature.

A nylon machine screw clamps the heatsink hotspot of a TO-220-packaged transistor (TIP31G) in a cantilever fashion onto the surface of the reference. A foam O-ring provides a modicum of thermal insulation. A dab of thermal grease on the mating surfaces will improve thermal coupling.

Figure 2 shows the electronics of the thermostat. Here’s how that works.

Figure 2 Q1 is a combo heater/sensor for a ±1°C thermostat, nominal setpoint ~70°C. R3 = 37500/(Vref – 0.375).

Q1 is the core of the thermostat. Under the control of gated multivibrator U1, it alternates between a temperature measurement when U1’s “Out” pin is low, and heating when U1’s “Out” pin goes high. Setpoint corresponds to Q1 Vbe = 375 mV as generated by the voltage divider R3/R4, detected by comparator A1, and timed by U1. 

I drew Figure 1 with the R3/R4 divider connected to +5 V, but in practice, this might not be the ideal choice. The thermostat setpoint will change by ~1.6°C per 1% change in Vref, so sub-percentage-point Vref stability is crucial to achieve optimal 16-bit DAC performance. The +5-V supply rail may therefore not be stable enough, and using the thermostatted DAC reference itself would be (much) better.

Any Vref of adequate stability and at least 365 mV may be used by simply setting R3 = 37500/(Vref – 0.375). For the same reason, R3 and R4 should be 1% or better metal film types. The point isn’t setpoint accuracy, which matters little, but stability, which matters much.

Vbe > 375mV indicates Q1 junction temp < setpoint, which gates U1 on. This allows U1 “Out” to transition to +5 V. This turns on driver transistor Q3, supplying ~20 mA to the Q1, Q2 pair. Q2 functions as a basic current regulator, limiting Q1’s heating current to ~0.7 V/1.5 Ω = 470 mA and therefore heating power to 2 W

The feedback loop thus established, Q1 Vbe to A1 to U1 to Q3 to Q1, adjusts the U1 duty cycle from 0 to 95%, and thereby tweaks the heating power to maintain thermostasis. Note that I omitted pinout numbers on A1 to accommodate the possibility that it might be contained in a multifunction chip (e.g., a quad) used elsewhere in the DAC.

Q.E.D. But wait! What are C2 and R2 for? Their reason for being, in general terms, is to be found in “Fixing a fundamental flaw of self-sensing transistor thermostats.”

As “Fixing…” explains, a fundamental limitation on the accuracy of thermostats like Figure 1 is as follows. The junction temperature (Tj) that we can actually measure is only an imperfect approximation of what we’re really interested in: controlling the package temperature (Tc). Figure 3 shows why.

Figure 3 The fatal flaw of Figure 1: the junction temperature is an imperfect approximation of the package temperature.

Because of the nonzero thermal impedance (Rjc) between the transistor junction and the surface of its case, an error term is introduced that’s proportional to that impedance and the heating power:

Terr = Tj – Tc = Rjc*Pj

In the TIP31 datasheet, Rjc is specified in the “Thermal Characteristics” section as 3.125 °C/W. Therefore, as Pj goes from 0 to 2 W, Terr would go from 0 to 6.25 °C. Recalling that the REF35 has a 12 ppm/°C tempco, that would leave us with 12 x 6.25 = 75 ppm = 5 lsb DAC drift. 

That’s 11x better than the 55-lsb tempco error we started with, but it’s still quite a way from true 16-bit accuracy. Can we do even better?

Just like the R11, R12, C2 network in Figure 2 of “Fixing a fundamental flaw of self-sensing transistor thermostats” that adds a Pj proportional Terr correction to the thermostat setpoint, that’s what R2 and C2 do here in this DI. C2 accumulates a ~23 ms average of 0 to 100% heating duty cycle = 0 to 700 mV, and adds through R2 a proportional 0 to 14 mV = 0 to 6.25°C Terr correction to the setpoint for net ±1°C stable thermostasis and < 1 lsb reference instability.

Now Q.E.D!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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The post A transistor thermostat for DAC voltage references appeared first on EDN.

Molecular beam epitaxy (MBE) system maker Riber S.A. of Bezons, France has confirmed a 22% drop in revenue from €13.7m in first-half 2024 to €10.7m for first-half 2025, reflecting a delivery schedule that is concentrated into second-half 2025. The firm says that, in a complex international environment, it recorded solid commercial activity, despite particularly pronounced seasonality...