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LM317 fans will recognize Figure 1 as the traditional LM317 constant current source topology. It closely regulates Iout = Vadj/Rs by forcing the OUTPUT pin to be Vadj = 1.25 V positive relative to the ADJ pin. Thus, Iout = Vadj/Rs to a very good approximation. Master chip chef Bob Pease cooked it up to be so!

Figure 1 Classic LM317 constant current source,
Iout = Vadj/Rs + Iadj ≃ Vadj/Rs = 1.25/Rs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In usual practice, Iout >> Iadj, the latter being specified at 50 µA typical, 100 µA max. This simplifies the math by making the Iadj bias current safely ignorable without letting accuracy take a hit. It’s worked great for 50 years but it has an obvious downside. the way you program Iout is by changing Rs.

Figure 2 shows a new(er) topology with a different (more agile) method for making Iout programmable.

Figure 2 A novel LM317 topology enables control of amps of Iout with just milliamps of Ic,
Iout = (Vadj – (Ic – Iadj)Rc)/Rs – Ic + Iadj ≃ (Vadj – (Ic – Iadj)Rc)/Rs. 

Typically, Rc > 100Rs, making Figure 2 able to control up to 1.5 A of Iout with just milliamps of Ic. Of course, now it may no longer be good enough to just ignore Iadj. 

Figure 3 shows the idea fleshed out into a complete PWM controlled 15 V, 1 A, grounded-load current source that includes Iadj compensation. Here’s how it works.

Figure 3 The 1-A, 15-V, PWM-programmed grounded-load current source with a novel LM317 topology. The asterisked resistors are 1% or better and Rs = 1.25 Ω.

The 5-Vpp PWM input has a frequency (Fpwm) assumed to be 10 kHz or thereabouts. If it doesn’t, scale C1 appropriately with:

C1 = 22µF*10kHz/Fpwm

The resulting PWM switching of Q2 creates a variable resistance averaged by C1 to Rc(1 + 1/Df) where Df = the 0 to 1 PWM duty factor.  Thus a (0 to 2.5v)/2Rc = 3.11 mA Ic current = 2.5v/Rc(1 + 1/Df) flows into Z1’s summing point.

Z1 servos the V1 gate drive of Q1 to hold its source at an accurate 2.5-V reference for the PWM conversion and to level shift Ic to track U1’s ADJ pin. Also summed with Ic is Iadj bias compensation (2.5v/51k = 50µA) provided by R1.

The unsightly stack of six 1N4001’s is needed to provide bias for Q1 to work into. I freely admit that it’s not very pretty. Hopefully the novelty of Figure 2 makes up for it! 

Note that accuracy and linearity mostly depend only on the match of the Rc resistors and the precision of the Z1 and U1 internal references. It’s a happy coincidence that the 2:1 ratio of the TL431’s 2.5-V versus the LM317’s 1.25 V permits the convenient use of three identical Rc resistors.

If Rs = 1.25 Ω, then Iout(max) = 1 A and Iout versus Df is as plotted in Figure 4.

Figure 4 Iout versus Df where Df (x-axis) is the PWM duty factor and Iout (y-axis) is Vadj/1.25 = 1 A full-scale = 1 – 2/(1 + 1/Df).

 Df versus Iout is plotted in Figure 5.

Figure 5 Df versus Iout where Iout (x-axis) is 1 A full-scale and Df (y-axis) = 1/(2/(1 – Iout) – 1).

Note that U1 might be called upon to dissipate as much as:

• 20 W if Rs = 1.25 Ω and Iout(max) = 1 A
• 30 W if Rs = 0.83 Ω and Iout(max) = 1.5A

Moral of the story: don’t be skimpy on the heatsink! Also note that Rs should be rated for a wattage of at least 1.252/Rs.

Then there’s the consideration of power up/down transients. When the system is first switched on and C1 is sitting discharged, and the controller will have about 4 to 8 milliseconds to initialize the PWM logic to 1.0 before C1 can charge enough to allow U1 to come on and start sourcing current. Don’t forget this detail during software development! On power-down, Q3 kicks in when +5 V drops below ~2 V. This saturates Q1 and forces Iout to zero to protect the load as well as discharging C1 in preparation for the next power-up.

In closing, thanks go (again) to savvy reader Ashutosh for his suggestion that the Figure 2 topology might deserve a focused DI of its own, and (likewise again) to editor Aalyia for the fertile DI environment she has created that makes this kind of teamwork, well, workable!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• 1 A, 20 V PWM DAC current source with tracking preregulator
• Classic 3-leg adjustable regulators have a shunt mode? Who knew?
• LM317 smooths but doesn’t regulate
• PWM power DAC incorporates an LM317
• Power Zener using the LM317
• Use an LM317 as 0 to 3V adjustable regulator

The post PWM-programmed LM317 constant current source appeared first on EDN.

Firmware is open source though. A small (52x30) PCB to forward USB HID reports over BLE. Plus additional buttons and a rotary encoder. submitted by /u/No_Pilot_1974 [link] [comments]

submitted by /u/1Davide [link] [comments]

Analog/mixed-signal and specialty foundry X-FAB Silicon Foundries SE of Tessenderlo, Belgium, independent pure-play indium phosphide (InP) integrated photonics foundry SMART Photonics of Eindhoven, The Netherlands, and Epiphany Design of Enschede, The Netherlands (a fabless photonic design house specialized in hybrid and heterogeneous photonics) are collaborating to develop a new heterogeneous photonics integration platform that combines the strengths of InP and silicon-on-insulator (SOI) technologies, enabling multi-terabit data rates for datacom and telecom applications...

What is Gold Soldering?

Gold soldering is a sophisticated metallurgical joining technique that represents the pinnacle of precision manufacturing processes. Unlike conventional soldering methods, this specialized technique involves creating permanent, high-integrity connections between gold or gold-alloy components with exceptional precision and reliability. The process goes beyond simple mechanical joining, instead creating a deep metallurgical bond that ensures optimal electrical, thermal, and structural performance.

How Gold Soldering Works

The scientific principles underlying gold soldering are complex and multifaceted. At its core, the process involves creating an atomic-level bond between gold surfaces using a carefully selected filler material with a strategically lower melting point. The metallurgical interaction is not merely a surface-level connection but a profound interdiffusion of metal atoms that creates a seamless, integrated joint.

The fundamental mechanism begins with the careful preparation of surfaces, where even microscopic contaminants can compromise the entire soldering process. As the filler material is heated, it transitions from a solid to a liquid state, simultaneously wetting the gold surfaces and creating a capillary action that draws the molten material between the components. During this process, atomic diffusion occurs, where the atoms of the filler material intermingle with the gold surfaces, creating a bond that is often stronger and more reliable than the original base materials.

Gold Soldering Process

Surface Preparation: The Critical First Step

Surface preparation is arguably the most crucial phase of gold soldering. This stage requires meticulous attention to detail and advanced cleaning techniques. Professionals employ a combination of chemical and mechanical methods to eliminate any potential contaminants. Specialized solvents are used to remove organic residues, while precise chemical etching or plasma cleaning techniques eliminate oxide layers and microscopic impurities.

The goal is to create an absolutely pristine surface that allows for maximum metallurgical interaction. Even a thin layer of oxidation or a microscopic particle can prevent proper bonding, leading to weak joints or complete soldering failure. Advanced cleaning techniques may include ultrasonic cleaning, chemical degreasing, and high-precision surface treatments that can remove contaminants at the atomic level.

Material Selection: A Delicate Science

Selecting the appropriate materials is a complex process that requires deep understanding of metallurgical properties. The gold alloy composition must be carefully matched with an appropriate filler material that can create a reliable bond while maintaining the desired mechanical and electrical properties. Factors such as melting point, thermal expansion coefficient, and chemical compatibility are meticulously evaluated.

Different applications demand different material characteristics. For instance, electronics may require a filler material that provides optimal electrical conductivity, while medical devices might prioritize biocompatibility and corrosion resistance. This selection process often involves extensive material testing and simulation to ensure optimal performance under various operational conditions.

Uses & Applications

Electronics Industry: Pushing Technological Boundaries

In the electronics industry, gold soldering is nothing short of revolutionary. Semiconductor packaging relies on this technique to create microscopic connections that form the backbone of advanced electronic devices. Hybrid microelectronics, which combine different types of electronic components, depend entirely on the precision and reliability of gold soldering techniques.

Modern smartphones, advanced medical imaging equipment, and cutting-edge aerospace technologies all benefit from gold soldering’s ability to create miniaturized, high-performance connections. The technique allows for the integration of components at nanoscale levels, enabling technological advancements that were previously impossible.

Medical and Aerospace Applications: Reliability in Extreme Conditions

In medical and aerospace domains, gold soldering’s reliability becomes paramount. Implantable medical devices require connections that can withstand the human body’s complex chemical environment, while aerospace components must endure extreme temperature variations and intense radiation.

The ability to create stable, corrosion-resistant joints makes gold soldering indispensable in these critical fields. Precision surgical instruments, satellite communication systems, and advanced sensor technologies all rely on the unique properties that gold soldering provides.

Advantages and Challenges

Gold soldering offers remarkable advantages, including exceptional conductivity, corrosion resistance, and the ability to create extremely precise connections. However, these benefits come with significant challenges. The process is inherently expensive, requiring specialized equipment and highly trained professionals.

The narrow temperature window for optimal soldering demands extraordinary skill and precision. A deviation of mere degrees can compromise the entire soldering process, making it a technique that requires continuous training and technological investment.

Conclusion

Gold soldering represents more than just a joining technique—it is a sophisticated technology that pushes the boundaries of what is possible in manufacturing. As technological demands become increasingly complex, the importance of this precise metallurgical process will only continue to grow.

Professionals in electronics, medical technology, aerospace, and advanced manufacturing must continually invest in understanding and mastering these intricate soldering techniques to drive technological innovation forward.

 

The post Understanding Gold Soldering: Definition, Process, Working, Uses & Advantages appeared first on ELE Times.

Acacia Communications Inc of Maynard, MA, USA (now part of Cisco) — which develops and manufactures high-speed coherent optical interconnect products — has expanded its client optics components portfolio with new products that leverage its proven digital signal processing (DSP) and silicon photonics expertise in coherent optics. Specifically, the firm is introducing a 3nm Kibo 1.6T PAM4 DSP and a family of 200G-per-lane optical engine products that can deliver a solution with the power efficiency required for the most demanding AI workloads...

Deposition equipment maker Aixtron SE in Herzogenrath, near Aachen, Germany is a partner in the research project GraFunkL (Graphene as a functional layer in UVC LEDs) for the use of novel UVC LEDs, which are to be used, among other things, against multi-resistant hospital pathogens...

Photonic application-specific integrated circuit (PASIC) chip design and manufacturing company OpenLight of Santa Barbara, CA, USA (which launched as an independent company in June 2022, introducing the first open silicon photonics platform with heterogeneously integrated III-V lasers) has completed Telcordia GR-468 qualification for all active components in its photonic design kit (PDK) based on Tower Semiconductor’s PH18DA process...

submitted by /u/ryleymcc [link] [comments]

Fully TTL driven Nixie clock I have been buildng recently. It have 6x IN-14 and 2x IN-19V Nixie tubes. Clock pulse is taken from mains frequency by optocoupler and devided by 7490 cunters. It can be set for 50Hz o 60Hz. There will be an option to choose beside Mains CLK, Crystal CLK and External CLK. There is also output to drive other clocks as "slave". Later on I will add "Day of the week" display. submitted by /u/Papa_Tronik [link] [comments]

Power semiconductor product supplier Diodes Inc of Plano, TX, USA has introduced its first series of indium antimonide (InSb) Hall-element sensors for rotation speed detection and current measurement in consumer applications such as laptops, mobile phones, joysticks, and in motors found in various home appliances. In industrial applications, they are designed for use in position encoders and commutation of brushless motors and fans. The development of these devices addresses the market demand for greater availability of high-sensitivity InSb Hall sensors in industry-standard 4-pin SOT23-4 and SIP-4 packages...

In booth 6357 at the Optical Fiber Communications Conference & Exposition (OFC 2025) in San Francisco, CA, USA (1–3 April), Scintil Photonics of Grenoble, France (a fabless firm developing and commercializing silicon photonic integrated circuits with integrated lasers for AI data centers) is demonstrating LEAF Light, which is claimed to be the world’s first single-chip, multi-wavelength laser source that delivers the speed, reach, power efficiency and lower latency required for scale-up networks. Scintil’s compact dense wavelength division multiplexing (DWDM) remote light source (with what is claimed to be the world’s most precise wavelength spacing) is said to be a vital component within the emerging co-packaged DWDM architecture that addresses the challenges for scalable AI data centers...

Semiconductor compute has grown drastically over the past 18 to 24 months amid the vast artificial intelligence (AI) infrastructure buildup. Nvidia and hyperscalers have made many announcements about migrating to GPUs with 200 Gbps per lane speeds. However, with computation moving to higher data rates, optical connectivity must also migrate to higher data rates.

But here comes the rub. While the rapid growth of AI workloads drives demand for increased bandwidth and interconnect density in AI clusters, optical interconnect power is a major factor limiting cluster scalability. Broadcom claims its new Sian3 and Sian2M PHY chips supporting 200 G/lane speeds offer greater levels of power efficiency and cost optimization for next-generation AI infrastructure.

Figure 1 Sian3 and Sian2M DSP PHYs enable module developers to rapidly address the growing demand for 200G optics in AI. Source: Broadcom

Optical connections can be short-reach or long-reach because sometimes AI clusters are in two different buildings. Natarajan Ramachandran, director of product line management for Broadcom’s Physical Layer Products Division, told EDN that Sian2M and Sian3 devices address these two scenarios, respectively.

Sian2M PHY chips

Ramachandran said that for shorter distances of less than 100 m, traditional optics, commonly termed multi-mode optics (MMF), is used. Here, vertical-cavity surface-emitting laser (VCSEL) technology has scaled very well so far. “However, in transition from 800 Gbps to 1.6 Tbps, VCSELs increasingly face physics limitations, making short-link bandwidths hugely constrained.”

Sian2M provides an optimized solution for 800G and 1.6T short-reach MMF links within AI clusters. It’s the first 200 G/lane DSP with integrated VCSEL drivers that enables low-power short-reach MMF links in AI clusters. “While industry watchers mostly believed that short link optics has reached a dead end, we are extending its life by at least one more generation,” Ramachandran said.

For longer distances of 2 Km to 3 Km operating across single-mode fiber (SMF) links, problems lie in power consumption. At 800 Gbps, power consumption was 15-16 W; but when you go to 1.6 Tbps, you don’t want to double the power usage. Enter Sian3 PHY chip.

Figure 2 Sian3 and Sian2M DSPs optimize power across single-mode fiber (SMF) and short-reach multi-mode fiber (MMF) links in 800G and 1.6T optical transceiver applications. Source: Broadcom

Sian3 PHY chips

At GTC 2025, held in San Jose, California, from 17 to 21 March, Nvidia’s chief Jensen Huang stressed the need for picojoule per bit to come down. That’s where Siam3 comes in, said Ramachandran. “We achieved 28 W with Sian2 while competition is roughly at 32 W,” he added. “With Siam3, a follow-on to Siam2, the transition from 5 nm to 3nm node results in 5-W savings, bringing power consumption down to 23 W.”

“So, we are getting close to what we’ve been consuming at 800 Gbps while moving to 1.6 Tbps speeds,” Ramachandran said. “And picojoule per bit is also showing a nice downward trend.” He also stated Broadcom’s aim to lower power consumption numbers, eventually reaching less than 20 W.

But is the cost also going down? Besides picojoule per bit, what about dollar per bit? Ramachandran said that with the transition from 5-nm to 3-nm process node, the die size also shrinks a lot, which significantly impacts the cost.

Broadcom is sampling Sian3 and Sian2M chips to early access customers and partners; Sian3 production is ramping up in the third quarter of 2025. Broadcom will demonstrate Sian chips and 200G VCSEL operating inside 1.6T optical modules at OFC in San Francisco, California, to be held on 1-3 April 2025.

Related Content

• Silicon Photonics Reaches Prime Time
• Optical transceivers: SFP, QSFP or CFP?
• How to Power Your QSFP-DD Optical Transceiver
• New test requirements for 40/100 GbE transceivers
• Interfacing Fast Ethernet Transceivers with PHY ICs

The post Optical PHYs facilitate 200G/lane speeds for AI clusters appeared first on EDN.

In booth 5315 at the Optical Fiber Communications Conference & Exposition (OFC 2025) in San Francisco, CA, USA (1-3 April), POET Technologies Inc of Toronto, Ontario, Canada — designer and developer of the POET Optical Interposer, photonic integrated circuits (PICs) and light sources for the hyperscale data-center, telecom and artificial intelligence (AI) markets — is demonstrating its latest technology innovations and products, detailed as follows...

Injection locking [1] can not only improve oscillator frequency stability and phase noise, but act as a selective frequency divider as well [2][3].

You can find sample setups of a simple two-transistor LC-based Peltz oscillator acting as a selective frequency divider in “Simple 5-component oscillator works below 0.8V” and “Investigating injection locking with DSO Bode function”.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The oscillator in the setup and shown in Figure 1 is just a pair of 2N3904s, a 10 µH inductor, a 2.6 nF capacitor, and a 1K bias resistor operating from -2 V. This produces a ~1 MHz oscillator output.

Figure 1 The Peltz oscillator found in the “Simple 5-component oscillator works below 0.8V” design idea (DI) consisting of only 5 components.

Signal injection is by means of a series 10 KΩ and 0.01 µF RC connected to the common emitters of the Q1 and Q2 2N3906 transistors. The subtle non-linearities within the oscillator allow selective frequency locking and division without additional active components. Figure 2 shows examples of frequency division by 2, 3, 5, and 10 respectively without any component values or circuit changes!

Figure 2 Examples of frequency division by 2, 3, 5, and 10 without any changes to the component values or circuit, this is due to the subtle non-linearities within the oscillator that allow selective frequency locking and division.

Injection locking also improves the oscillator phase noise even when acting as a divider. Figure 3 shows some results from the free running oscillator and when acting as a frequency-selective divider.

Figure 3 Spectrum analysis of the oscillator free running and when acting as a frequency-selective divider with an injection-locked division of 3 and 10. There is a marked improvement in phase noise when acting as a frequency-selective divider.

The test setup used a general-purpose AWG (SDG2042X) as the signal source, a DSO (SDS814X HD) and spectrum analyzer (SSA3021X Plus) for the displays. Of course this technique isn’t going to replace a proper digital divider, but might find use in a pinch when one needs frequency division, or improve a simple oscillators stability and phase noise.

Michael A Wyatt is a life member with IEEE and has continued to enjoy electronics ever since his childhood. Mike has a long career spanning Honeywell, Northrop Grumman, Insyte/ITT/Ex-elis/Harris, ViaSat and retiring (semi) with Wyatt Labs. During his career he accumulated 32 US Patents and in the past published a few EDN Articles including Best Idea of the Year in 1989.

 Related Content

• Simple 5-component oscillator works below 0.8V
• Investigating injection locking with DSO Bode function
• Ultra-low distortion oscillator, part 1: how not to do it.
• Ultra-low distortion oscillator, part 2: the real deal
• The Colpitts oscillator
• A two transistor sine wave oscillator
• Clapp versus Colpitts

References

1. Razavi, B. “A study of injection pulling and locking in oscillators.” Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., pp. 305–312, https://doi.org/10.1109/cicc.2003.1249409.
2. “EEVblog Electronics Community Forum.” SMD Test Fixture for the Tektronix 576 Curve Tracer – Page 1, eevblog.com/forum/projects/smd-test-fixture-for-the-tektronix-576-curve-tracer/.
3. “EEVblog Electronics Community Forum.” Injection Locked Peltz Oscillator with Bode Analysis – Page 1, www.eevblog.com/forum/projects/injection-locked-peltz-oscillator-with-bode-analysis/. Accessed 25 Mar. 2025.

 

The post Injection locking acts as a frequency divider and improves oscillator performance appeared first on EDN.

submitted by /u/Patate-Furtif [link] [comments]

Hey! I repaired the LCD ribbon cable in a Nintendo DS Lite. I know it’s completely not worth it since a new screen is super cheap, but I wanted to practice soldering and test my skills. And it actually worked! I intentionally placed a human hair on one of the pictures—for scale. I used an ultra-thin wire from a phone speaker coil to reconnect the traces. This was more of an experiment than a necessity, but the screen works like new, so mission accomplished. The photos are a bit blurry since I took them with my phone through a microscope eyepiece—I don’t have a proper adapter. All this effort for something that costs just a few bucks—but the satisfaction is priceless! submitted by /u/misiekbba [link] [comments]

To enhance production of its proprietary high-power distributed feedback (DFB) laser and laser array technology, Sivers Semiconductors AB of Kista, Sweden is partnering with WIN Semiconductors Corp of Taoyuan City, Taiwan — which provides pure-play gallium arsenide (GaAs) and gallium nitride (GaN) wafer foundry services for the wireless, infrastructure and networking markets. The strategic collaboration paves the way for high-volume manufacturing of critical components for coarse wavelength division multiplexing (CWDM) and dense wavelength division multiplexing (DWDM) applications...

1. Fundamental Quantum Mechanical Foundations

1.1 Quantum Spin Dynamics

Spintronics represents a revolutionary paradigm that fundamentally challenges traditional electronic technologies by exploiting the quantum mechanical spin property of electrons. Unlike conventional charge-based electronics, spin-based technologies leverage the intrinsic angular momentum of electrons, characterized by two quantum states: spin-up (|↑⟩) and spin-down (|↓⟩). This binary quantum nature provides an unprecedented foundation for information storage and processing, opening new frontiers in computational architecture.

The mathematical representation of spin dynamics is elegantly captured by the Heisenberg Hamiltonian:

H = -∑(J_ij * S_i · S_j)

This equation encapsulates the quantum mechanical interaction between spin operators, where J_ij represents the exchange coupling constant, and S_i and S_j describe spin operators at specific lattice sites. The fundamental interaction demonstrates the complex quantum mechanical spin correlation mechanisms that underpin spintronic technologies.

1.2 Spin-Orbit Coupling Phenomena

Spin-orbit coupling (SOC) emerges as a critical quantum mechanical interaction where an electron’s spin precession becomes intrinsically coupled with its orbital motion. This phenomenon introduces sophisticated spin-dependent electronic transport mechanisms that are crucial for advanced spintronic devices.

The field of spin-orbit coupling encompasses several profound physical manifestations. The Rashba effect represents a quantum mechanical spin splitting mechanism primarily observed in two-dimensional electron systems with broken inversion symmetry. This effect generates a spin-momentum locking phenomenon where electron spin becomes intrinsically linked to its momentum direction, creating unique quantum transport behaviors.

The Dresselhaus effect complements the Rashba mechanism, representing a bulk spin-orbit coupling phenomenon prevalent in non-centro-symmetric crystal structures. Originating from bulk inversion asymmetry, this effect generates spin-dependent electron scattering mechanisms that fundamentally deviate from traditional electronic transport models.

2. Magnetoelectric RAM: Advanced Architectural Insights

2.1 Magnetoelectric Coupling Mechanisms

Magnetoelectric RAM (MeRAM) represents a sophisticated memory paradigm that exploits the intricate coupling between magnetic and ferroelectric materials. The fundamental interaction can be described by a phenomenological free energy expression:

F = F_magnetic + F_electric + F_magnetoelectric

This sophisticated approach enables electric-field-induced magnetic state modulation with unprecedented precision, bridging quantum mechanical principles with advanced computational memory technologies.

The material design for effective magnetoelectric RAM demands a nuanced approach to material selection and interface engineering. Critical material characteristics include the magnetoelectric coefficient (α_ME), which quantifies the material’s ability to couple magnetic and electric polarization states. Magnetic anisotropy energy plays a crucial role in determining the stability of magnetic configurations, while ferroelectric polarization magnitude determines the efficiency of electric-field-based switching mechanisms.

2.2 Magnetic Tunnel Junction (MTJ) Architectures

Magnetic Tunnel Junctions (MTJs) represent the core computational element in MeRAM, utilizing quantum mechanical tunneling phenomena for information storage and transfer. The typical MTJ multilayer configuration consists of carefully engineered ferromagnetic electrodes separated by an ultrathin insulating barrier, enabling sophisticated quantum mechanical information processing.

3. Advanced Quantum Transport Mechanisms

3.1 Spin-Transfer Torque (STT)

Spin-transfer torque emerges as a sophisticated quantum mechanical mechanism for manipulating magnetic moments through spin-polarized current injection. The Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation provides a comprehensive mathematical framework for describing the complex magnetization dynamics inherent in this mechanism.

The quantum mechanical principles involve direct momentum transfer from spin-polarized electrons to magnetic moments within a material system. When a spin-polarized current passes through a magnetic multilayer structure, electron spins interact with local magnetic moments, exerting a torque that can rotate or manipulate the magnetic configuration with unprecedented precision.

3.2 Magnetoelectric Switching Dynamics

Electric-field-induced magnetic switching represents a pinnacle of quantum mechanical interface engineering. This sophisticated mechanism transcends traditional electronic switching by directly manipulating magnetic states through electric field application.

The underlying physics encompasses multiple interrelated quantum mechanical phenomena, including strain-mediated magnetic coupling, direct exchange interactions, and interfacial charge redistribution mechanisms. These complex interactions enable precise control of magnetic configurations through electrical means, representing a quantum leap in computational memory technologies.

4. Performance Characterization and Metrics

4.1 Advanced Performance Parameters

The evaluation of magnetoelectric RAM technologies requires a multidimensional approach that extends beyond traditional memory performance metrics. Key performance indicators include:

• Energy Consumption: Targeting switching energies below 0.1 picojoules per bit
• Write Latency: Approaching near-ballistic regime switching speeds of a single nanosecond
• Data Retention: Targeting retention times exceeding decade-long scales
• Endurance: Approaching or exceeding 10^12 write operations

4.2 Thermal Stability Considerations

Thermal stability represents a fundamental challenge in advanced memory technologies. The Arrhenius equation provides a mathematical framework for understanding magnetic state lifetime, relating it to material-specific energy barriers and operational temperatures.

5. Material Science Innovations

5.1 Emerging Magnetoelectric Materials

The frontier of MeRAM technologies hinges on material science innovations that push quantum mechanical engineering boundaries. Key approaches include:

• Multiferroic composites combining ferromagnetic and ferroelectric properties
• Engineered heterogeneous interfaces with atomically precise boundaries
• Topological magnetic materials providing inherent quantum decoherence protection
• Rare-earth metal substitutions enabling fine-tuned material properties

5.2 Nanostructuring Techniques

Advanced nanostructuring methodologies include:

• Molecular beam epitaxy (MBE) for atomic-layer-precise material deposition
• Pulsed laser deposition for creating complex material architectures
• Focused ion beam lithography for nanoscale structural modifications
• Atomic layer deposition (ALD) for ultra-thin, precisely controlled material layers

6. Industry and Research Implications

6.1 Technological Disruption Potential

MeRAM technologies offer transformative capabilities across multiple domains:

• High-performance computing with extraordinary energy efficiency
• Internet of Things (IoT) devices with ultra-low power consumption
• Neuromorphic computing architectures mimicking biological neural networks
• Bridging classical and quantum computational paradigms

6.2 Economic and Computational Impacts

• Projected market value: $500 million by 2028
• Potential 70% reduction in computational energy consumption
• Enabling more sustainable and efficient computing infrastructures

Conclusion

Spintronics and MeRAM represent a quantum leap in computational memory technologies, bridging fundamental quantum mechanical principles with advanced engineering methodologies. By leveraging sophisticated quantum mechanical interactions, these technologies promise to revolutionize computational architectures, offering unprecedented performance, energy efficiency, and computational capabilities.

Disclaimer: Technological developments are ongoing, and specific implementations may vary.

The post Spintronics and Magnetoelectric RAM: A Comprehensive Technical Exploration appeared first on ELE Times.

A few weeks ago, I told you about (among other things) the iPhone 16e, Apple’s latest “entry-level” smartphone and the pricier successor to the three-generation iPhone SE series:

I couldn’t resist noting that Google had responded to Apple’s news with a (temporary, as it turned out) price cut on its (then-)latest-generation entry-level smartphone, the Pixel 8a, to $399. That said, I’d already suspected (rumor-aided) that this likely wasn’t just a competitive counterpunch. Google was probably also doing some inventory-clearing in advance of a pending unveil of its own next-gen entry-level smartphone, presumably to be called the Pixel 9a.

The Pixel 9a reveal

I was right; this year Google didn’t even wait until the late May I/O conference to reveal it (that said, in retrospect the haste may not have been wise). Behold the Pixel 9a, which starts at $499:

and which (currently, at least) comes in four color options:

I chose the above image not only because it shows the color variants but because it also highlights one of the key differences between the Pixel 9a and its most recent three generational precursors. Look, for example, at the backside of the Pixel 8a:

Beginning with the Pixel 6 family, Google had switched to a backside style that grouped the camera (or multi-camera cluster), scene-illumination flash LED, microphone, and other related sensors into a horizontal raised bar, continuing that same style with “a” variants. With the Pixel 9a, conversely, Google seems to have returned to the (near-)flush approach exemplified by, for example, the Pixel 4a 5G handsets I owned prior to my current Pixel 7s:

I dunno why…mebbe the raised-bar approach made them more breakage-prone? Or mebbe they wanted it to look like an iPhone? Regardless, per Aalyia’s request , here’s a broader comparison table of the most recent two “a” generations, as well as the Pixel 9 introduced in-between them late last summer (to keep things simple, I left out the two Pixel 9 Pro variants):

	Pixel 8a	Pixel 9	Pixel 9a
Price	$499/$559	$799/$899	$499/$599
Storage	128 GB/256 GB	128 GB/256 GB	128 GB/256 GB
DRAM	8 GB (LPDDR5X)	12 GB (LPDDR5X)	8 GB (LPDDR5X)
Size	Height: 5.99 in (152.1 mm) Width: 2.86 in (72.7 mm) Depth: 0.35 in (8.9 mm)	Height: 6.02 in (152.8 mm) Width: 2.83 in (72 mm) Depth: 0.33 in (8.5 mm)	Height: 6.09 in (154.7 mm) Width: 2.89 in (73.3 mm) Depth: 0.35 in (8.9 mm)
Weight	6.63 oz (188g)	6.98 oz (198g)	6.56 oz (186g)
Screen	6.1-inch 20:9 aspect ratio 1080 x 2400 OLED at 430 PPI  60-120 Hz Up to 1400 nits (HDR) and up to 2000 nits (peak brightness)	6.3-inch 20:9 aspect ratio 1080 x 2424 OLED at 422 PPI 60-120Hz Up to 1800 nits (HDR) and up to 2700 nits (peak brightness)	6.3-inch 20:9 aspect ratio 1080 x 2424 pOLED at 422.2 PPI 60-120Hz Up to 1800 nits (HDR) and up to 2700 nits (peak brightness)
SoC	Google Tensor G3	Google Tensor G4	Google Tensor G4
CPU	Nona-core: 1× 2.91 GHz Cortex-X3 4× 2.37 GHz Cortex-A715 4× 1.7 GHz Cortex-A510	Octa-core: 1× 3.1 GHz Cortex-X4 3× 2.6 GHz Cortex-A720 4× 1.92 GHz Cortex-A520	Octa-core: 1× 3.1 GHz Cortex-X4 3× 2.6 GHz Cortex-A720 4× 1.92 GHz Cortex-A520
GPU	Mali-G715 MP7 890 MHz	Mali-G715 MP7 940 MHz	Mali-G715 MP7 940 MHz
NPU	3rd Gen Edge TPU	3rd Gen Edge TPU	3rd Gen Edge TPU
Cellular modem	Exynos 5300i	Exynos 5400c	Exynos 5300i
Front camera	13 MP camera ƒ/2.2 aperture 96.5° ultrawide field of view	10.5 MP Dual PD camera with autofocus ƒ/2.2 aperture 95° ultrawide field of view	13 MP camera ƒ/2.2 aperture 96.1° ultrawide field of view
Rear camera(s)	Dual rear camera system: optical zoom at 0.5x and 1x, digital zoom up to 8x 64 MP Quad PD wide camera ƒ/1.89 aperture 80° field of view 13 MP ultrawide camera ƒ/2.2 aperture 120° field of view	Dual rear camera system: optical zoom at 0.5x, 1x and 2x, digital zoom up to 8x 50 MP Octa PD wide camera ƒ/1.68 aperture 82° field of view 48 MP Quad PD ultrawide camera with autofocus ƒ/1.7 aperture 123° field of view	Dual rear camera system: optical zoom at 0.5x and 1x, digital zoom up to 8x 48 MP Quad PD Dual Pixel with closeup AF ƒ/1.7 aperture 82° field of view Optical + electronic image stabilization 13 MP ultrawide camera ƒ/2.2 aperture 120° field of view
Wireless charging	7.5W	15W	7.5W
Wired charging	18W USB-PD	27W USB-PD	23W USB-PD
Battery capacity	4492 mAh	4700 mAh	Typical 5100 mAh (minimum 5000 mAh)
Dust/water resistance	IP67	IP68	IP68

Pixel 9a observations

Several particularly interesting bits jump out at me:

• As I’d mentioned late last summer, Google had originally only planned for Gemini deep learning support to be enabled for the Pixel 8 Pro with 12 GBytes of RAM; the company subsequently developed a “Nano” variant of Gemini capable of being shoehorned into the 8 GBytes of RAM in other Pixel 8 versions. So, you might assume that the Pixel 9a, also with 8 GBytes of RAM, would also be Gemini-cognizant. And you’d be right…except this time, Google’s referring to the Gemini version as “Gemini Nano 1.0 XXS (extra extra small)”. Then again, the version available for Pixel smartphones with 12 GBytes or more of RAM is no longer just “Gemini Nano”, it’s “Gemini Nano XS (extra small)”. My guess as to what’s happening is just some rebranding of what already exists; as baseline Gemini becomes more feature-filled, the need to differentiate it from the version(s) running on phones and other resource-constrained devices therefore becomes more necessary.
• The selective mixing-and-matching within each device’s SoC is interesting. The Pixel 9a gets the Pixel 9’s CPU and other processing subsystems, but the cellular modem is a generational backstep, reverting to what was in the Pixel 8s (and 7s, for that matter). The modems and CPUs listed in this particular table are actually all fabricated on 4 nm Samsung processes, but I’m guessing that everything’s not integrated within a single die. Instead, the CPU and modem die are likely side-by-side (or alternatively sandwiched) within a common package, simplifying the mix-and-match process. Keep in mind, too, that whereas Google (generally speaking) is more forthright about its phones’ specs than is Apple, neither company publishes clock speeds. While my table shows the maximum documented speeds of various processing cores, it’s not guaranteed that they run at that speed in a particular system-implementation configuration.
• In many respects, the Pixel 9a is the latest in a long line of handsets derived from their earlier-announced, fuller-featured generational siblings. It swaps out the Pixel 9’s glass-and-aluminum frame back for plastic, for example, and its wireless charging support is conventional in power, therefore speeds, not “supercharged”. That said, there were some surprising deviations from usual form. The Pixel 9a is the only one of the three to explicitly list as features both optical and electronic image stabilization, for example, for its rear wide-angle camera. And its wired charging power-therefore-speed was nearly as fast as that of the Pixel 9, as well as being a significant improvement on the Pixel 8a.
• Further comparing the Pixel 9a to its direct forebear, the Pixel 8a, the aforementioned rear wide camera, for example, has also decreased in resolution by 25%, although both image sensors have equivalent 0.8µm pixel pitch (i.e., light-gathering capability). Plus, the new camera’s maximum aperture is larger, for improved low-light performance, further aided by the already-noted enhanced image stabilization support. The Pixel 9a offers slightly improved dust and moisture resistance than its Pixel 8a predecessor, too. That said, curiously, the 256GB version of the Pixel 9a costs $40 more than the 256GB Pixel 8a, $599 versus $559, although the 128GB versions of both handset generations are identically priced at $499.
• And check out that comparatively sizeable battery in the Pixel 9a versus either of the others! It’s particularly impressive given that the Pixel 9a is still lighter than the Pixel 8a. But what’s with the charge capacity variability; multiple battery suppliers, mebbe?

Pixel 9a vs iPhone 6e

Speaking of comparisons (and of Apple), how does the Pixel 9a stack up against the iPhone 16e? This analysis is simultaneously easier (from a hardware standpoint) and harder (from a usability perspective). Specs first; the Pixel 9a has (for example):

• A lower price tag ($499 vs $599, in both cases for versions with 256 GBytes of storage)
• A slightly larger display (6.3” diagonal versus 6.1”) with a 2x higher peak refresh rate (120 Hz versus 60 Hz), albeit at slightly lower resolution (1080 x 2,424 pixels/421ppi vs 1,170 x 2,532 pixels/460 ppi)
• Two rear cameras versus one, and
• A ~25% larger battery (5,100mAh versus 4,005mAh), along with
• Slightly more advanced Wi-Fi (6E vs 6) and Bluetooth (6 versus 5.3)

And now that Apple has indefinitely delayed the more personalized aspects of its Apple Intelligence capabilities, Google (with Gemini) has an advantage here as well, conceptually, at least. The thing is, though, AI doesn’t yet seem to be tangibly propelling smartphone sales. More generally, the fierce loyalty divide between Android and iOS users is akin to that between “blue” and “red” states. Take my household as an example; although originally a periodic “switcher”, I’ve settled on Android for a while now, although my tablets run iPadOS. Conversely, paraphrasing Charlton Heston, my wife would likely only give up her iPhone if you pried it from her cold, dead hands. And speaking of “indefinite delays”, Google (presumably driven by a decision made at the last pre-launch minute) is no longer saying exactly when the Pixel 9a will start shipping (only a nebulous “April”, and isn’t even yet accepting pre-orders for the handset, all due to an unspecified “component quality issue”.

Swollen battery

Maybe the problem’s with the battery? I jest (maybe), in transitioning (in closing) to the “distended” portion of this piece mentioned in the title. Long-time readers may remember that back in September 2020, I mentioned that in-parallel (fortuitously) with their replacement by Pixel 3as, my original Google Pixels were beginning to exhibit swollen-battery symptoms:

Well, look at what I noticed a couple of weeks ago on one of my Pixel 7s:

Lest you think that’s just an artifact of the case or the screen protector, here’s a “naked” view:

The left-side swell isn’t as pronounced:

which makes sense when, as iFixit’s teardown guide makes clear, you learn that the battery’s placement is right-side dominant:

This was my “work” phone, which was used less often (therefore spent more time just sitting trickle-charging) than its “personal” sibling. And although I had Adaptive Charging enabled, I hadn’t taken the extra step of limiting the peak charge point to 80% of total capacity.

Plus, the phone (purchased in June 2023) was beyond its one year of factory warranty support. That said, I’d fortunately also purchased Asurion’s 36-month extended warranty coverage at that same time. This writeup’s already in “extra innings”, so I’ll save the rest of the (good ending, mind you) story for another post at another time to come. Until then, please share your thoughts on what I’ve so-far discussed in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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