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Finding appropriate methods of cooling electronics allows engineers, designers and other professionals to prioritize sustainability by finding solutions that will make the products last longer and become more energy efficient.

Passive techniques are popular because they are usually less expensive and more reliable than active ones because there are no fans or other moving parts to break. What have researchers explored, and how can their findings improve future electronics designs?

Applying hot spot reducing methods

Graphene is a material known for being extraordinarily strong yet lightweight. Those studying it have also learned it can conduct and dissipate heat efficiently, leading engineers to want to learn more about its capabilities as a passive cooling mechanism in electronics.

One example associated with a European Union-funded project comes from Swedish startup Tenutec, which uses graphene as additives or multilayered films for passive cooling in electronics. The company stands out from others with its sustainable manufacturing method. It enables graphene production with a carbon footprint of only 0.85 kilograms of CO2 equivalents per kilogram. That is several hundred times less carbon-intensive than other well-established methods.

Figure 1 The use of graphene as additives or multilayered films has significant merits in passive cooling. Source: Tenutec

Additionally, its technique enables dispersion of graphene into one to three layers without harmful chemicals. Because the venture’s passive cooling methods eliminate hot spots in electronics, they also improve sustainability by lengthening products’ life spans.

This passive cooling work began during research at Sweden’s Chalmers University of Technology. Researchers developed and improved their graphene production method there, eventually realizing that the current market conditions and consumer demands made the technique marketable.

Regardless of the precise innovations applied, many electronics manufacturers want compact and effective solutions with the accompanying data to prove their worth. Another hot spot-eliminating technology can dissipate heat at levels of 1,000 watts per square centimeter, making it a good solution for devices’ power components.

Whether professionals use graphene sheets or alternatives to keep their devices at the right temperature, potential users will want assurances of effectiveness.

Improving performance of metal-organic frameworks

Numerous improvements in passive cooling options for electronics involve metal-organic frameworks (MOFs)—porous materials that pull water vapor from the air. However, they typically have low thermal conductivity. One research team sought to improve that characteristic by using a water adsorption process to control interfacial heat transfers from contacted surfaces to MOFs.

Figure 2 Metal-organic frameworks (MOFs) are porous materials that pull water vapor from the air. Source: IntechOpen

This group applied simulations and comprehensive measurements during their approach to determine its effectiveness. The results indicated that the water adsorption method made the interfacial thermal conductance approximately 7.1 times better than the MOFs performed without them.

The researchers also concluded that adsorbed water molecules within the MOFs formed dense channels, creating thermal pathways that moved heat away from the hot surfaces. They determined this cooling innovation created a sustainable way to regulate temperatures in electronics and other critical devices while simultaneously expanding possibilities that use MOFs for passive cooling.

Supporting sustainability while keeping electronics cool

Even as consumers use electronics on daily basis, many are increasingly concerned about the waste generated when those products stop working or get discarded. Similarly, they want manufacturers to offer solutions that work well while reducing environmental burdens.

Passive cooling technologies are central to these demands because electronics must exhibit adequate thermal management capabilities. Overheating can shorten their life spans and endanger users. However, when strategies meet sustainability needs while maintaining effectiveness, consumers and designers reap the benefits.

Ellie Gabel is a freelance writer as well as associate editor at Revolutionized.

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Semiconductors are the essential component fueling the growth of industries such as automotive, renewable energy, communications, information technology, defense, and consumer electronics. The rise of their importance began in the late 1950s when Jack Kirby and Robert Noyce invented integrated circuits (IC), which built electronic components and circuits on a common semiconductor base. ICs quickly replaced vacuum tube-based electronic equipment because they were more power efficient, saved space, and more reliable.

Over the past six decades, ICs have advanced significantly and are used in many industries as they are critical components in numerous products and processes. ICs can be multiple discrete components packaged together, such as digital logic circuits, microcontrollers, microprocessors, digital memory storage, analog circuits and amplifiers, radio frequency (RF) / microwave (MW) analog components and circuits, and integrated power circuits. This article focuses on using waveform generators to test various types of ICs.

IC design and testing are complex processes involving precision and expertise to meet required specifications. Engineers engage in iterations, optimizations, and validations to ensure the final IC achieves the desired performance and reliability. In Figure 1, the process begins with software modeling and simulation based on IC specifications. Subsequently, the design is etched onto a photomask and transferred to a silicon wafer during the wafer foundry stage. After wafer testing, the ICs are packaged and undergo functional testing to ensure they function correctly.

Figure 1 The IC design and test process flow including IC design and simulation, wafer processing, parametric testing, lead frame/wire bonding, package testing, and ending with functional test. Source: Keysight

During the design or front-end IC manufacturing stage, the ICs tend to be tested at the wafer level. Testing ICs at the upstream wafer-level process can be challenging, especially when using wafer-probing tools. However, it is necessary because the packaging process is costly and complex. Figure 2 shows wafer probing and testing in progress.

Figure 2 Wafer-level IC probing and testing where basic functional verifications can be performed such as catastrophic shorting, leakage, power supply, and general input / output conditions. Source: Keysight

At the wafer level, you can perform tests for basic function verifications such as catastrophic shorting, leakage, power supply, and general input / output conditions. Signal sources can come from programmable DC power supplies, source and measure units, and general-purpose waveform generators.

During the IC design stage, test engineers can perform noise, DC parametric, and S-parameter characterization work at wafer-level probing tests. This process drastically reduces the time to the first measurement and provides accurate and repeatable device and component characterization.

After the ICs are placed on lead frames, wire-bonded to their respective leads and encapsulated, they are in their final physical form. Tests are conducted to ensure that the packaged ICs meet packaging expectations, such as no short circuits, open or weak connections, proper electrical isolation between internal circuits, and more.

Waveform generators provide clean signals and controlled frequency and amplitude noise levels for signal integrity and low-frequency noise tests. Figure 3 shows how waveform generators can provide controlled simulated signals into ICs for an oscilloscope to test signal integrity.

Figure 3 The eye diagram of an IC signal integrity test where waveform generators can provide clean signals and controlled frequency and amplitude noise levels. Source: Keysight

Post-packaging functional testing, also known as end-of-line testing, is often complex and tedious. This process is the last testing stage, during which the ICs are extensively tested to ensure they meet specified performance and quality standards before they are shipped to customers.

Waveform generators generate complex variable patterns, real-world signals, and even extreme use-case signals to ensure that all ICs shipped meet the required performance specifications and functionality. Modern waveform generators are versatile in generating all kinds of signals, such as digital, analog, complex modulated, low to high frequency, burst, synchronized, and arbitrary waveform signals for all IC applications.

Waveform generators on the market have a wide range of specifications. Testing and characterizing ICs requires stringent specifications. IC design engineers need a source that produces a clean, low-distortion, stable, and reliable signal. The signal generated should not vary regardless of frequency or sample rate. Furthermore, certain waveform generator specifications for IC testing are important.

A clean signal source provides true and unadulterated signals without noise or interference from other foreign signals. The signals are measurable by the purity of a signal void of harmonic distortions and jitter. A clean and stable signal is necessary when testing ICs because engineers want:

• The best product specification: ICs require precise and accurate signals to characterize and validate their functions and performances. The more errors introduced from the signal source, the more degraded the product specification becomes due to measurement uncertainties.
• To avoid false test results: A stable signal source creates a consistent test process. Consequently, the test results can accurately characterize the behavior of the ICs. If the signal source is unstable, problems such as false test results affect downstream tests. Shipping the incorrectly characterized product to customers is the worst-case scenario.
• Repeatable and reliable performance: Clean signals will also provide optimized repeatability test conditions to gauge the true performance of ICs. They will not have unwanted harmonics and noise, rendering test results inaccurate. Furthermore, a test can be made more reliable by replacing a real-world signal with a signal created by a waveform generator.

Besides having clean signals to characterize the performance of IC devices, adding noise to test signals simulates real-world noisy transmission, crosstalk, and EMI. Instead of getting the best product performance specifications, adding noise stresses the IC under test and determines the robustness of the products.

Suitable waveform generators can produce variable noise bandwidth to control the frequency content of the test signal. Figure 4 illustrates that this approach enables controlled stress testing of the ICs under test.

Figure 4 Adding controlled noise into a test signal (top image) results in a noisy ECG signal (bottom image). Source: Keysight

Many applications require mixed-signal ICs, which are essentially ICs with digital and analog circuits built-in and packaged together. Applications that use mixed-signal ICs include analog-to-digital converters, digital-to-analog converters, power management circuits, microcontroller circuits, and physical parameter sensing measurements such as temperature, humidity, and pressure. Waveform generators can simulate both digital and analog signals to test mixed-signal ICs.

Modern waveform generators can generate arbitrary waveforms to simulate real IC test applications. These generators usually come with software applications that create arbitrary waveforms.

The most direct method for importing signals is digitizing a real-world test signal using an oscilloscope, saving it in a format that is readable with your software application, digitally manipulating or conditioning the test signal, and then transferring it to a waveform generator to regenerate the signal.

Another common method is to use waveform builder software to generate custom arbitrary waveforms and combining them into the desired simulated test signal. Some IC design engineers may want to generate the waveforms directly in MATLAB or Python programming and transfer those waveforms to the waveform generators. For example, Figure 5 shows how MATLAB understands the plotting of a complex waveform. The waveform is a simulation of a section of an electrocardiograph (ECG) heart signal showing part of the PQRST points. In fact, this waveform shows only the RST points for the purpose of creating a T-wave rejection test waveform. MATLAB can model waveforms using math equations and translate all these points into a complex ECG test signal.

Figure 5 Using math equations, assembling into a simulated cardio ECG test signal in MATLAB. Source: Keysight

Figure 6 shows the output of a cardio ECG test signal generated from MATLAB. The MATLAB software application offers options to send waveform points as a binary block to an arbitrary waveform function generator. The reason for sending a waveform as binary data rather than ASCII data is simple—the binary data is much smaller than the equivalent ASCII data.

Figure 6 MATLAB can transfer the above-simulated cardio ECG test signal into a waveform generator. Source: Keysight

These methods enable engineers to create the desired test signals for cataloging and storing in digital waveform libraries. This approach enables consistent and organized testing for many types of IC test applications.

Most modern waveform generators can play various segments of waveforms in sequence. Design engineers can build a playlist of test sequences with waveforms of incremental changes or good or bad signals to test the IC responses. Depending on your waveform generator’s capabilities, you can combine individual arbitrary waveform segments into user-defined lists or sequences to form longer, more complex waveforms.

Waveform generators are versatile test instruments essential throughout IC design and manufacturing processes. They can generate all kinds of signals, such as digital, analog, complex modulated, low to high frequency, burst, synchronized, and arbitrary waveform signals, for many types of IC applications.

Designers can take advantage of the powerful capabilities of waveform generators to create clean and stable signals as well as to control IC stress testing by adding incremental noise content to the test signals. Waveform generators can also generate all kinds of arbitrary waveforms to simulate real IC test applications, this is critical as ICs are getting smaller and integrate more complex functions.

Bernard Ang has been with Keysight Technologies (previously Hewlett Packard and Agilent Technologies) for more than 30 years. Bernard held roles in manufacturing test engineering, product engineering, product line management, product development management, product support management, and product marketing. He is currently a product marketer focusing on data acquisition systems, digital multimeters, and education product solutions. Bernard received his Bachelor of Electrical Engineering from Southern Illinois University, Carbondale, Illinois. 

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•  

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Company will be primary provider of fully optimized power system solution based on onsemi’s latest generation EliteSiC M3e platform

• onsemi and Volkswagen Group sign multi-year deal to supply solution for vehicle lineup across several brands
• onsemi will provide a full stack of silicon carbide technologies as part of an integrated module solution that can scale across all power platforms
• Volkswagen Group will benefit from onsemi’s plans to expand manufacturing in Europe would establish an end-to-end production facility for the traction inverter system

The post onsemi Selected to Power Volkswagen Group’s Next-Generation Electric Vehicles appeared first on ELE Times.

According to the wisdom of French philosopher Jean-Baptiste Alphonse Karr, “Plus ça change, plus c’est la même chose,” or “The more things change, the more they stay the same.” This adage holds significant relevance in the fast-paced world of the semiconductor industry. Currently, the industry is undergoing a profound technological shift fueled by diverse applications that mandate intricate custom chip designs.

Ground-breaking technologies such as artificial intelligence (AI), autonomous vehicles, edge processing and chiplets are triggering an avalanche of advancements in the semiconductor market. Pioneering technologies are paving the way for high-growth markets, maintaining a competitive edge for products and driving the demand for increasingly sophisticated systems-on-chips (SoCs) to power burgeoning applications.

As a result of design complexity and market competition, innovative chip development strategies have become essential for expedited market entry and revenue growth. Tapping into these technological advances is a strategic imperative to secure market leadership.

The established hybrid design landscape

Over the past two decades, OEMs, Tier 1 suppliers and system designers have embraced a hybrid chip design model, predominantly operating independently. These companies frequently resort to customer-owned tooling (COT) for chip design, subsequently engaging with back-end services companies and wafer production management teams.

The COT model necessitates the recruitment of specialized semiconductor engineers from various disciplines for SoC development—a challenging feat due to the scarcity and steep cost of engineers. To address this need, companies often outsource talent to help manage temporary workload peaks and meet specific skillset demands. However, this workaround may not lead to forming a permanent, skilled team.

Large enterprises and startup companies alike must pay closer attention to the severe financial implications of design errors, which can sabotage budgets and delay market entry. In a recent study, a leading EDA firm reveals that over 60% of all first-time designs require a silicon re-spin. With millions of dollars of NRE on the line each time, plus the cost of delayed time to market, the rising complexity in chip design significantly amplifies the risk of errors, making any mistake potentially career-ending.

Figure 1 A 2020 functional verification study conducted by Siemens EDA and Wilson Research Group shows only 32% of 2020’s designs claimed first-silicon success.

Against this backdrop, the tech landscape continues to experience growth from venture capital-backed startups, particularly in the AI realm. These agile companies often utilize the COT model but face similar hurdles in designing distinctive, complex chips for their products. The technical expertise required to create sophisticated SoCs often exceeds their core competencies.

This underscores the need for experienced partners’ guidance throughout the chip design journey. Also, they frequently cannot source wafers directly from the industry’s leading foundry, TSMC, and instead are routed to a Value Chain Alliance (VCA) partner for mask creation and wafer production management.

These trends are driving a resurgence of ASIC design companies that now focus on “design and supply” services, offering a broad spectrum of technologies for customers to choose from. These firms possess the technical skills to guide customers in making informed selections of third-party IP and comprehend chiplet interconnect requirements, sophisticated SoC power management, 3D packaging, and more.

In short, this minimizes risk with new chip implementations and corresponding financial impacts. So, a new generation of ASIC companies with broad experience and stable engineering teams is emerging, capable of providing solid technology recommendations.

The imperative for a revamped model

Companies can preempt potential setbacks by collaborating with the new generation of ASIC design and supply firms that can manage the entire silicon development process. This necessity is spurring a reevaluation of chip design strategies. The quest for unique differentiation and shorter development cycles is moving companies toward a collaborative relationship with their ASIC design partners.

This shift signals the demand for a new paradigm where companies are seeking alternatives capable of supporting the complete chip ecosystem, from inception to delivery. Adopting an integrated ASIC design and supply model offers significant advantages over traditional ASIC houses and reduces the investment associated with COT models.

An integrated ASIC design and supply model involves cross-functional teams collaborating closely with customers to define the entire semiconductor development and manufacturing process, including packaging, final testing and product lifecycle management.

Today’s SoCs are intricate, multi-billion-transistor devices custom-built for specific applications. The cost of developing such high-end chips can easily exceed $50 million, with the photomask set alone at advanced process nodes ranging from $10 million to $20 million. A collaboration with a technologically advanced, single-source ASIC design house can expedite chip development and help ensure first-time silicon success.

Figure 2 A single-source ASIC design house can expedite chip development and help ensure first-time silicon success. Source: Sondrel

Rich Wawrzyniak, principal analyst for The SHD Group, emphasizes the growing importance of ASIC-class services by stating, “In today’s complex technological landscape, ASIC-class services have become an essential part of the equation for handling advanced semiconductor design implementations.”

In the face of rapidly evolving technologies and the pressure to accelerate time to market, partnering with a single-source ASIC design and supply company appears increasingly beneficial. With its specialization in managing the entire chip development process, such a company can help chip designers architect their future and secure a competitive advantage.

Ian Walsh, Sondrel’s regional VP for America, is based in the company’s U.S. office in Santa Clara, California.

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Disclosure of Transactions in Own Shares – Period from Jul 15, 2024 to Jul 19, 2024

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announces full details of its common share repurchase program (the “Program”) disclosed via a press release dated June 21, 2024. The Program was approved by a shareholder resolution dated May 22, 2024 and by the supervisory board.

STMicroelectronics N.V. (registered with the trade register under number 33194537) (LEI: 213800Z8NOHIKRI42W10) announces the repurchase (by a broker acting for the Company) on the regulated market of Euronext Paris, in the period between Jul 15, 2024 to Jul 19, 2024 (the “Period”), of 254,850 ordinary shares (equal to 0.03% of its issued share capital) at the weighted average purchase price per share of EUR 38.2047 and for an overall price of EUR 9,736,472.80.

The purpose of these transactions under article 5(2) of Regulation (EU) 596/2014 (the Market Abuse Regulation) was to meet obligations arising from share option programmes, or other allocations of shares, to employees or to members of the administrative, management or supervisory bodies of the issuer or of an associate company.

The shares may be held in treasury prior to being used for such purpose and, to the extent that they are not ultimately needed for such purpose, they may be used for any other lawful purpose under article 5(2) of the Market Abuse Regulation.

Below is a summary of the repurchase transactions made in the course of the Period in relation to the ordinary shares of STMicroelectronics (ISIN: NL0000226223), in detailed form. 

Transactions in Period

Following the share buybacks detailed above, the Company holds in total 8,767,667 treasury shares, which represents approximately 1.0% of the Company’s issued share capital.

In accordance with Article 5(1)(b) of the Market Abuse Regulation and Article 2(3) of Commission Delegated Regulation (EU) 2016/1052, a full breakdown of the individual trades in the Program are disclosed on the ST website (https://investors.st.com/stock-and-bond-information/share-buyback).

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I’ve been intending for a while now to share my experiences with the first-generation Google Pixel Watch. And, with the second-generation successor already eight months old as I write these words in mid-June 2024, along with rumors of the third-generation offering already beginning to circulate, I figured it was now or never to actualize that aspiration! The two generations are fairly similar; I’ll point out relevant differences in the paragraphs that follow.

The first-gen Pixel Watch (black frame and black rubberized “active” band version shown above; other color combinations also offered, along with accessory bands made from other materials) was unveiled at the 2022 Google I/O conference and entered production that same October. Its development was predated by several key business moves by the company. In January 2019, smartwatch manufacturer (and Google partner) Fossil sold some of its IP to Google as well as transferring part of its R&D team to the acquiring company, all for $40 million. And that same November, Google announced that it planned to spend $2.1 billion to purchase Fitbit, an acquisition that finally closed in January 2021 after a lengthy U.S. Justice Department evaluation of potential antitrust concerns.

Next up, some personal history. As regular readers may remember, I’ve long been an admittedly oft-frustrated user of smartwatches from Google’s various partners (Huawei, LG and Motorola, to be precise), all based on a common Wear OS or precursor-branding Android Wear software foundation. I eventually bailed on them, instead relying on my long-running, Android smartphone-compatible (in contrast to Apple Watches, for example) Garmin and Withings smartwatches. But in doing so I’d foregone any hands-on testing of the newer Wear OS 3 (currently at v4, with v5 enroute) which blended in design elements of the legacy Tizen O/S from Google’s new smartwatch partner, Samsung, along with any personal evaluations of newer smartwatch SoCs from Qualcomm and Samsung.

The Wear OS drought ended when, last September, I saw that not only had Google dropped the price tag of the LTE-enhanced version of the Pixel Watch by $60, to $339.99, it was also tossing in two years of free Google Fi-supplied cellular data service:

After using cellular data for ~9 months now, it’s nice to have but not essential, at least for me. Were I regularly wearing the watch while exercising away from my smartphone, for example, I might feel differently. But given that my Pixel 7s are regularly in close proximity, direct Internet connectivity from the smartwatch isn’t a necessity, plus it incrementally impacts battery life whenever the watch is untethered from the phone and not on a known Wi-Fi network.

About that battery life…when I started using the smartwatch, I struggled to squeeze a full day of between-charges wear out of it. Now, thanks to both Google-supplied software updates and my fine-tuning of the power management settings, I can often go for 30 hours or more. And if I were to disable the twist-wrist-to-turn-on-backlight, relying solely on manual watch face taps to wake up the display, I’d likely be able to stretch the battery life even further.

That said, my Garmin watch only loses ~10% of its battery capacity per day; it’ll run for well beyond a week between charges as long as I’m not activating its GPS subsystem (of course).

And my Withings watch? I intentionally took it instead of the Pixel Watch with me to California last month so that I didn’t need to bother packing a charger; its svelte body is also easier than the alternative long-lasting Garmin to tuck underneath a buttoned-down dress shirt sleeve. Upon my return to Colorado five days later, its stored battery charge still reported 100% full.

By the way, you might have noticed something about the Pixel Watch in the more recent (earlier today, in fact) two on-wrist pictures I took of it. I switched from the default “active” band, which quickly started exhibiting visible usage evidence from being removed from and then reattached to my wrist 1x per day (for recharging), to a stretchable Spigen Lite Fit band. Also, although one of the standard watch faces (the cool-looking, IMHO, Concentric) is shown, I sometimes instead toggle to the third-party Pixel Minimal one I purchased, which (in spite of its seemingly contrary name) lets me squeeze even more info into the display: daily step count, heart rate, date, weather, and battery charge. For obvious reasons I’ve already noted, that last one’s important.

A bit more on the battery. The first-generation Pixel Watch leverages wireless charging, akin to that used by Apple’s various Watch models and generations:

This approach is admittedly convenient. But it’s also slow; it takes ~2 hours to fully charge the watch from a drained state, a not-insignificant percentage of the subsequent wear-before-charge-again time. To wit, the Pixel Watch 2 moved to a more traditional, Fitbit-like multi-pin-based connector, notably (from reviews I’ve seen) boosting charging speed in the process.

And the upcoming Pixel Watch 3, per leaked images, will not only be thicker but also come in a larger-face variant. One benefit of the form factor increase is room inside for a larger, higher capacity battery. Plus, as my wife, now with a Christmas-present Apple Watch Ultra replacement for her soon-obsoleted Series 4 (a pending demise I’d forecasted back when I bought the successor for her) says, “go big or go home” (translation: she likes her watches “chunky”).

Another notably difference between the two Pixel Watch generations is that whereas my first-gen model runs on a Samsung Exynos 9110 dual-core processor, the Pixel Watch 2 switches to a quad-core Qualcomm SW5100 SoC. That said, the performance of mine is perfectly acceptable (that said, I haven’t comparatively tried its successor yet!). Other enhancements with the second-generation model:

• A switch from a stainless steel to lighter aluminum body
• An enhanced-function cardiac sensor suite, and
• New skin temperature and electrodermal activity (EDA) stress sensors

similarly don’t provide sufficient upgrade motivation, at least for me.

In closing, two other oddities of note. For some unknown reason, the Pixel Watch isn’t compatible with the Wear O/S app that comes with Android. Instead, as part of the initial pairing process:

a dedicated Watch app gets installed.

Also, I can’t for the life of me get native Google Wallet support working with the watch:

Again, at worst a minor nuisance, since I usually also have a phone with me. Still…

What are your thoughts on Google’s branded Wear OS smartwatches, both in comparison to alternatives from other Wear OS licensees and those based on other smartwatch operating systems (including Fitbit’s)? Sound off in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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