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Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — says that its board of directors has determined and agreed with Gregg Lowe that in November he will depart from his roles as president & CEO and as a member of the board. Hence, with the support of a global executive search firm, the board is seeking to identify a permanent CEO...

Employing network-on-chip (NoC) technology in system-on-chip (SoC) designs has been proven to reduce routing congestion and lower power consumption. Now, a new NoC-enabled tiling methodology helps speed development, facilitates scaling, participates in power reduction technology and contributes to increased design reuse for SoCs targeting artificial intelligence (AI) applications.

For these discussions, we will assume that AI encompasses use cases such as machine learning (ML) and inferencing.

Soft and hard tiles

One challenge in engineering is that the same term may be used to refer to different things. The term “tile,” for example, has multiple meanings. Some people equate tiles with chiplets, which are small, independent silicon dies, all presented on a common silicon or organic substrate or interposer. Chiplets may be thought of as “hard tiles.”

By comparison, many SoCs, including those intended for AI applications, employ arrays of processing elements (PEs), which can be considered “soft tiles.” For example, refer to the generic SoC depicted in Figure 1.

Figure 1 High-level block diagram shows SoC containing a neural processing unit (NPU). Source: Arteris

In addition to a processor cluster comprising multiple general-purpose central processing units (CPUs), along with several other intellectual property (IP) blocks, the SoC may also contain specialized processors or hardware accelerators. These units include an image signal processor (ISP), a graphics processing unit (GPU) and a neural processing unit (NPU), designed for high-performance, low-power AI processing.

In turn, the NPU comprises an array of identical PEs. In the not-so-distant past, these PEs were typically realized as relatively simple multiply-accumulate (MAC) functions, where MAC refers to a multiplication followed by an addition. By comparison, today’s SoCs often contain PEs with multiple IPs connected via an internal NoC.

Implementing soft tiling by hand

In the common SoC scenario we are considering here, NoCs may be employed at multiple levels in the design hierarchy. For example, a NoC can be used at the top level to connect the processor cluster, ISP, GPU, NPU and other IPs. NoCs may be implemented in various topologies, including ring, star, tree, mesh and more. Even at the top level of the SoC hierarchy, some devices may employ multiple NoCs.

As has already been noted, each PE in the NPU may consist of multiple IPs connected using an internal NoC. Furthermore, all the PEs in the NPU can be connected using a NoC, typically implemented as a mesh topology.

The traditional hand-crafted approach to implementing the NPU starts by creating a single PE. In addition to its AI accelerator logic, the PE will also contain one or more network interface units (NIUs) to connect the PE to the main mesh NoC. This is illustrated in Figure 2a.

Figure 2 This is how designers implement soft tiling by hand. Source: Arteris

If we assume that the NPU specification calls for a 4×4 array of PEs, the designer will replicate the PE 16 times using a cut-and-paste methodology (Figure 2b). Next, NoC tools will be used to auto-generate the NoC (Figure 2c). During this process, the NoC generator automatically assigns unique identifiers (IDs) to each of the NoC’s switching elements. However, the NIUs in the PEs will still have identical IDs; that is, the default ID from the PE’s creation.

For the NoC to transfer data from source nodes to destination nodes, the NIU in each PE must have a unique ID. This requires the designer to hand-modify each PE instance to provide it with its own ID. In addition to being time-consuming, this process is prone to error, which can impact downstream testing and verification.

This hand-crafted tiling technique poses several challenges. For example, changes to the PE specification are often made early in the process. For each change, the designer has two options: (a) manually replicate the change across all PE instances in the array, or (b) modify only the original PE and then repeat the entire hand-crafted soft tiling process. Both options are time consuming and error prone.

Also, performing soft tiling by hand is not conducive to scaling. If it becomes necessary to replace the original 4×4 array with an 8×8 version, such as for a derivative product, the process becomes increasingly cumbersome and problematic.

NoC-enabled tiling

The phrase “NoC-enabled tiling” refers to an emerging trend in SoC design. This evolutionary approach uses proven, robust NoC IP to facilitate scaling, condense design time, speed testing and reduce design risk.

NoC-enabled tiling commences with the designer creating a single PE as before. In this case, however, the NoC tools can be used to automatically replicate the PEs, generate the NoC and configure the NIUs in the PEs, all in a matter of seconds. The designer only needs to specify the required dimensions of the array.

Figure 3 This is how NoC-enabled tiling is carried out. Source: Arteris

In addition to dramatically speeding the process of generating the array, this “correct by construction” approach removes any chance of human-induced errors. It also enables the design team to quickly and easily accommodate change requests to the PE early in the SoC development process. Furthermore, it greatly facilitates scaling and design reuse, including the creation of derivative designs.

An evolving market

Based on an analysis of AI SoC designs currently under development by their customers, the Arteris team has determined the relative use of soft tiling in key verticals and horizontals for AI today. This is illustrated in Figure 4, where the areas of the circles reflect the relative number of application use cases.

Figure 4 NoC-enabled tiling is shown in key verticals and horizontals for AI today. Source: Arteris

Designing multi-billion-transistor SoCs is time-consuming and involves many challenges. Some SoC devices, such as those intended for AI applications, may include functions like NPUs that comprise arrays of PEs. Here, NoC-enabled tiling is an emerging trend and it’s supported only by leading NoC IPs and tools.

Andy Nightingale, VP of product management and marketing at Arteris, has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm.

 

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• What is the future for Network-on-Chip?
• SoC design: When is a network-on-chip (NoC) not enough
• Network-on-chip (NoC) interconnect topologies explained
• Why verification matters in network-on-chip (NoC) design

The post Speeding AI SoC development with NoC-enabled tiling appeared first on EDN.

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The recent Design Idea “Getting an audio signal with a THD < 0.0002% made easy,” discloses a low THD sine generator which led me to dust off a design that I had published in AudioXpress magazine [1] (see Figure 1).

Figure 1 The “Simple Sineman” circuit [1] is based on a simpler version of the circuit having approximately -80dB THD [2].

Wow the engineering world with your unique design: Design Ideas Submission Guide

Requirements for an analog oscillator

Before getting into the detail of how this circuit works, it’s worth recalling certain requirements for an analog oscillator: a feedback circuit which, at the oscillation frequency fosc Hz, has a loop gain magnitude of unity and a phase shift of either 0 or a multiple of 360 degrees. One means of implementing this is to place a notch filter in the feedback loop of an op amp. You might be forgiven for thinking that fosc is at the filter’s notch frequency fnotch Hz. But obviously, infinite attenuation is not consistent with a unity gain loop. Not so obviously, the op amp’s internal compensation network adds a -90° phase shift to its inherent -180° inverting input-to-output phase shift. What is then needed for oscillation is a filter which, at fosc, exhibits both a -90° phase shift and has an attenuation of Aosc, where Aosc is the op amp gain magnitude at fosc. But how can we find a filter capable of meeting such precise constraints?

The “dual-T” notch filter

The innovative “dual-T” notch filter in Figure 1 saves the day. It’s made up of C1, C2, C3, R1, R2, R3A, and R3B. I had a need for a 2400-Hz oscillator and so chose the values shown. One way to place a notch at fnotch Hz is to use the following process and equations:

Choose a value C for C1, C2 and C3                                                (1)

and set R1 and R2 equal to 1 / (2π* fnotch*C*√3)                    (2)

set R3 = R3A + R3B equal to 12 / (2π* fnotch*C*√3)                   (3)

An analysis of this filter type shows that there is always a value of R3 which produces an infinite attenuation notch regardless of the variations of the other component values due to tolerances. Since there is clearly no attenuation at DC, this means that any attenuation from none to infinity can be had at some frequency. The analysis also shows that there is always some frequency below fnotch at which the phase shift is -90°. The appropriate value of R3 causes that phase shift to coincide with the necessary attenuation of Aosc at fosc. Figure 2 gives a feeling for some phase and gain magnitude responses of the filter as R3B is varied. Table 1 relates the oscillation and notch frequencies and values of R3 for a -90° phase shift at various attenuations Aosc.

Figure 2 Responses of the dual-T notch filter. To simulate practical variances from the ideal, capacitor values were randomly selected to be within 1% of 10 nF, and R1 and R2 to be within 0.1% of ideal values for a 2400-Hz fosc. A value of R3 that produced a 130 dB notch depth was calculated, and results are shown with it and with several slightly larger R3 values. -90° phase shifts with attenuations from 65 to 130 dB are evident for various R3 values.

Attenuation, dB	1 – fosc/fnotch	NOtol = 1 – fosc/fnotch
-90	0.01%	-0.01%
-80	0.03%	-0.02%
-70	0.11%	-0.05%
-60	0.35%	-0.18%
-50	1.07%	-0.56%

Table 1. Variations in the oscillation with respect to the notch frequencies and in R3 values for a -90° phase shift at various Aosc attenuations.

Knowing the values of fosc and Aosc, the value of fnotch can be calculated from Table 1. From this, the values of the capacitors and the resistors R1 and R2 can be calculated from equations (1) and (2). With 0.1% resistors for R1 and R2 and 1% capacitors, fnotch will be kept within a range of the tolerance product Stol = 1 +/- 1.01*1.001 ≈ 1.1% of the intended value. Note that regardless of component tolerances, there is always the option of adding a pot in series with either R1 or R2. The aggregate value of that pot plus resistor should have a range of Stol centered at the equation (2) value. The values and tolerances of R3A and R3B should be selected so that R3 can be adjusted to within Stol – NOtol (see Table 1) of the equation (3) value.

It’s worth noting that with the better-known twin-T notch filter [3], I was unable to meet the phase and attenuation requirements simultaneously by varying only a single resistor value. Even if this were possible, the capacitors in the dual T are conveniently identical, while the twin-T’s requirement of a value ratio of 2 limits capacitor choices. This is also a good time to mention that polystyrene capacitors offer the lowest harmonic distortion [4], with non-metalized polypropylene being a secondary choice.

Establishing oscillation amplitude

Of course, the elephant in the room is what I haven’t yet mentioned—the requirement for establishing an oscillation amplitude. One way of doing this is to parallel the R3 resistor plus pot with a non-linear resistor whose value varies inversely with signal level. Unfortunately, any such non-linearity increases harmonic distortion. So it makes sense to choose a non-linear component designed specifically for low harmonic distortion audio applications. The NE570 (an improved version of the SA571 seen in Figure 1) is a low harmonic distortion compressor/expandor IC intended for audio applications [5]. A block diagram of the part appears in Figure 3.

Figure 3 A block diagram of the function of the SA571 and NE570 compandor IC, curtesy of On Semiconductor.

As can been seen, the part has a “delta G” cell whose current gain is controlled by the capacitively filtered output of the rectifier. The capacitively-coupled inputs to both functions are connected in Figure 1 through resistors I’ve added to reduce the functions’ operating levels. These are driven by the output of the LME49720 op amp U2A. (The op amp provided with the SA571/NE570 is of the 741 type and should not be used in extremely low THD applications. Its output and one end of the 20K resistor R3 can be left unconnected. Its inverting input is connected to that of U2A.) Note the 1.8-V reference which is the unavoidable DC operating voltage of the delta G cell and both inputs of U2A.

The SA571/NE570 are dual parts, and use is made of the secondary unit. Its rectifier capacitor pin is grounded to disable its delta G cell, whose input is floating. The uncommitted side of its R3 is connected to its op amp output to produce a stable 3 VDC source. This source drives the Figure 1 R10 pot to supply a current to the THD trim pin. R10 is adjusted to null out the small amount of 2nd harmonic distortion produced by the delta G cell (and possibly by U2A). I powered the circuit from batteries for portability and added the LEDs to keep fresh 9-V batteries from exceeding the +/- 18 V maximum power supply ratings of the op amp. The SA571’s 30k resistor connecting the op amp inverting inputs to ground is unavoidable. With Figure 1’s R3, it biases that op amp’s output to approximately 4.5 V( (≈45k/30k + 1)*1.8 V ). This level can be reduced by connecting a resistor from the 3-V source to U2A‘s inverting input (not provided in the Figure 1 circuit). With or without this additional resistor, remember to keep a proper DC bias across output electrolytic capacitor C5.

The added passive components at the NE570 inputs are chosen to allow R3 to be adjusted for a 3 Vrms output from U2A, the level at which its datasheet indicates that that op amp exhibits the lowest THD.

Measuring distortion

To measure distortion, I attenuated the oscillator output’s fundamental by running the signal through a second dual T filter with a pot in series with each resistor. By laboriously tweaking each pot in turn, I was able to attenuate the fundamental by 70 dB. The filtered output was applied to an SR770 spectrum analyzer which can accurately measure signals within an 80 dB dynamic range. Tweaking the THD pot to minimize the 2nd harmonic level, I measured the levels of the oscillator harmonics and applied corrections for the filter attenuations at each frequency (see Table 2.) I then took the rms of the levels corrected for the attenuations of the second dual T filter and arrived at a THD more than 130 dB below the oscillator fundamental.

Harmonic Number	Filter Attenuation, dB
2	11.81
3	6.54
4	5.14
5	3.78
7	2.78
9	2.49

Table 2 Attenuation of higher harmonics by a dual-T filter tuned as described in the text to maximize attenuation of the oscillator fundamental.

The NE570 and LME49720 datasheets and parts are available online and through DigiKey. Small quantities of the NE570 for experimenters can be had from numerous eBay vendors.

I believe that it’s tough to beat the combination of simplicity and performance afforded by this design and welcome comments from anyone who builds and tests it.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content

• Getting an audio signal with a THD < 0.0002% made easy
• Measure an amplifier’s THD without external filters
• Ultra-low distortion oscillator, part 2: the real deal
• A simple circuit with an optocoupler creates a “tube” sound
• How to control your impulses—part 2

References

1. Paul, C, The Simple Sineman, audioxpress, November 2013, p. 52
2. Jung, “Gain Control 1C for Audio Signal Processing,” Ham Radio, 1977, no longer available.
3. https://learningaboutelectronics.com/Articles/Notch-filter-calculator.php#answer1
4. https://www.tedss.com/LearnMore/Polystyrene-Film-Capacitors offers a wide array of polystyrene capacitors
5. ON Semiconductor, NE570 datasheet, https://www.onsemi.com/pdf/datasheet/ne570-d.pdf

The post A simple, purely analog -130dB THD sine wave generator appeared first on EDN.

For third-quarter 2024, deposition equipment maker Aixtron SE of Herzogenrath, near Aachen, Germany has reported revenue of €156.3m (up 18.6% on €131.8m last quarter but down 5% on €165m a year ago). This is in the lower half of the guidance range of €150–180m, as the delivery of a major micro-LED-related project was postponed from Q3 to Q4/2024 at the customer’s request...

For third-quarter 2024, CVD Equipment Corp of Central Islip, NY, USA (a designer and maker of chemical vapor deposition, thermal processing, physical vapor transport, gas and chemical delivery control systems, and other equipment and process solutions for developing and manufacturing materials and coatings) has reported revenue of $8.2m, up 31.4% on $6.2m a year ago. Growth is due mainly to higher CVD Equipment system revenue and an increase in gas delivery system revenue by the SDC segment, plus $0.8m from a modification of a customer contract...

The US Department of Defense (DoD) has invested an additional $160m of funds from the Biden–Harris Administration’s ‘Creating Helpful Incentives to Produce Semiconductors (CHIPS) and Science Act’ to advance US microelectronics capabilities through the Microelectronics Commons, a collaborative national network of technology hubs. Following the award in September of $269m for 33 new technical projects and the award of just under $240m released a year previously to initially launch the eight hubs, the latest funding in October represents a milestone for the CHIPS Act’s mission to strengthen the USA’s global leadership in microelectronics and semiconductor manufacturing...

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In booth #810 at Supercomputing 2024 (SC24) in Atlanta, GA, USA (17–22 November), silicon photonics-based chip-to-chip optical connectivity firm Ayar Labs of San Jose, CA, USA is demonstrating a broad range of optical I/O implementations for AI scale-up fabrics. The firm’s optical I/O solution is said to eliminate the inefficiencies, high power consumption and increasing costs of copper interconnects and pluggable optics, boosting the performance and economics of AI infrastructure. At SC24, Ayar Labs is featuring its technology in various AI infrastructure concepts with Fujitsu Ltd, Intel Foundry, Corning Inc, Altera, and others...

Governor Greg Abbott says that the first Texas Semiconductor Innovation Fund (TSIF) grant of $4,120,000 has been extended to Intelligent Epitaxy Technology Inc (IntelliEPI) of Richardson, TX, USA — which manufactures molecular beam epitaxy (MBE)-grown epitaxial wafers for telecoms, photonics, radio frequency and microwave technologies — for its new 30,000ft2 wafer production facility in Allen, Texas, which is expected to create more than $41m in capital investment and to nearly triple the company’s annual wafer production. Abbott signed into law the Texas CHIPS Act in June 2023, establishing the TSIF as well as the Texas Semiconductor Innovation Consortium...

An ongoing semiconductor industry consolidation has been somewhat challenging for companies that consume analog chips in their designs. However, these conditions have created opportunities for startups to fill the gap, meeting design engineers’ needs on a smaller scale and keep the analog semiconductors industry vibrant.

Many companies using semiconductors need highly specific options, and it does not make sense for them to approach some of the industry’s largest companies. Many of those have minimum order requirements, so large chipmakers are usually unwilling to provide the level of customization required.

Here, startups like Orca Semiconductor are willing to serve designers seeking specialized hardware. Catering to that market is increasingly important, particularly as many OEMs explore ways to commercialize innovative new devices. If a proposed product seems too far-fetched, large semiconductor companies may not want to associate with it. Semiconductor executives in these large outfits may determine that it’s safer to continue working with well-established customers.

Orca’s first commercial product is an advanced power management integrated circuit (PMIC) for wearable devices. The component also has a battery-preserving feature that reduces current draw during inactive periods.

ASSP business model

The company’s CEO Andrew Baker clarified that Orca’s business model does not revolve around making custom chips in the traditional sense. Instead, it will make analog-based application-specific standard products (ASSPs) rather than focusing on custom silicon. The company’s leaders believe this will keep the business agile and free it from the slow decision-making processes that generally stifle innovation at larger analog chipmakers.

Figure 1 Orca Semi has recently unveiled an IO-Link transceiver for smart factory environments.

OEMs needing analog semiconductors rely on the way chipmaker’s resources are set up and are ready to serve them. However, the industry’s broader consolidation has made it more challenging for some would-be customers to find analog companies that will work with them.

Here, outfits like Spirit Electronics demonstrate what can happen when designers have more available options. Although not a startup, this business specializes in analog and mixed-signal ICs.

It provides design engineers with an alternative to the long lead times that other outlets often have. One thing that sets this company apart is that it manages its foundry services under one roof rather than outsourcing. That strategy gives it more control and allows the business to meet emerging needs.

Analog in machine learning

Another notable company in the analog design space is Aspinity. The company’s business model addresses the growing need for always-on devices, such as those that continually listen for inputs and respond accordingly.

Since such devices process all analog sounds and not just particular command words or other cues, they can be incredibly power-intensive. However, a notable characteristic of Aspinity’s components is how well they conserve energy.

Figure 2 Aspinity’s AML100 chip runs machine learning completely within the analog domain.

The company first gained attention by releasing an analog chip for machine learning. It consumes less than 20 microamps of power when determining the data’s relevancy. It also shrinks that information’s size more than 100 times, freeing up memory space on the respective device.

These examples show that startups and smaller companies have emerged to meet a need driven by the analog semiconductor industry’s consolidation. Not all electronic outfits can approach larger analog chipmakers with their orders, but the above-mentioned businesses are well-positioned to assist.

Related Content

• Aspinity Expands into Audio Event Detection
• AI Startup Aspinity Launches Low-Power Analog Chip
• Analog startup eyes ASSPs for wearables, smart factory
• Audio chip moves machine learning from digital to analog
• IO-Link transceiver bolsters smart factory productivity, intelligence

The post Startups eye opportunities amid analog industry consolidation appeared first on EDN.

Fabless company Wise-integration of Hyeres, France — which was spun off from CEA-Leti in 2020 and designs and develops digital-control of gallium nitride (GaN) and GaN integrated circuits for power conversion — has opened its North American Design & Development Center in Ottawa, Ontario, Canada. Led by Christian Cojocaru and staffed by experts in analog and digital technology design, the center will drive development of the firm’s design portfolio for the next generations of WiseGan...

A strategic collaboration has been announced to use micro-transfer printing (MTP) for the heterogeneous integration of the silicon photonics platform of analog/mixed-signal and specialty foundry X-FAB Silicon Foundries SE of Tessenderlo, Belgium with the indium phosphide (InP) chiplets of independent pure-play InP photonic integrated circuit (PIC) foundry SMART Photonics of Eindhoven, The Netherlands, enabling new capabilities for datacom and telecom applications...

Renesas Electronics Corporation has launched its latest innovation in the automotive semiconductor space: the fifth-generation R-Car X5H system-on-chip (SoC). Designed with 3-nanometer (nm) process technology, the R-Car X5H represents the industry’s first automotive multi-domain SoC built on such an advanced node. This SoC is set to redefine the capabilities of centralized electronic/electrical (E/E) architecture, supporting a range of automotive functions, from advanced driver assistance systems (ADAS) to in-vehicle infotainment (IVI) and gateway applications, all within a single chip.

The R-Car X5H SoC brings unprecedented levels of integration and performance, addressing the growing demand for efficient, powerful, and flexible compute solutions in software-defined vehicles (SDVs). With hardware-based isolation, chiplet extension capability, and extensive AI and graphics processing power, this new SoC series offers automotive original equipment manufacturers (OEMs) and Tier-1 suppliers a comprehensive platform for tackling the complexity of modern vehicle design and functionality.

Unmatched Processing Power and Efficiency

The R-Car X5H delivers AI acceleration of up to 400 TOPS (trillion operations per second) and GPU performance up to 4 TFLOPS, ensuring the SoC can handle demanding tasks in automated driving and infotainment. Featuring 32 Arm Cortex-A720AE CPU cores and six Arm Cortex-R52 dual lockstep CPU cores, this SoC achieves over 1,000K DMIPS for applications and more than 60K DMIPS for real-time processing. Manufactured using Taiwan Semiconductor Manufacturing Company’s (TSMC) 3-nm automotive-grade process, the SoC achieves 30-35% lower power consumption than its 5-nm counterparts. This significant efficiency enhancement not only lowers overall system costs but also extends vehicle range by reducing the need for additional cooling.

Chiplet Extensions for Enhanced Flexibility

A unique feature of the R-Car X5H is its support for chiplet extensions, allowing OEMs to add AI and graphics processing power as needed. Through the Universal Chiplet Interconnect Express (UCle), the SoC can integrate seamlessly with external processors, enabling AI performance scaling up to three or four times the native 400 TOPS. This flexibility provides OEMs and Tier-1 suppliers with customizable options to meet evolving vehicle demands, offering scalability for future performance upgrades across diverse vehicle platforms.

Robust Security with Mixed-Criticality Processing

In the automotive industry, safety remains paramount. The R-Car X5H uses hardware-based Freedom from Interference (FFI) technology to securely isolate critical safety functions, such as brake-by-wire, from other non-critical operations. This mixed-criticality processing enables secure, independent domains for safety-critical tasks, preventing failures from impacting vital vehicle functions. Coupled with real-time Quality of Service (QoS) management, the SoC dynamically prioritizes processing tasks to ensure optimal performance under varied conditions.

The Path Forward for Software-Defined Vehicles

As part of Renesas’ R-Car Gen 5 family, the R-Car X5H is designed to address the requirements of the SDV market. By centralizing processing, this SoC streamlines vehicle electronic systems, supporting cross-domain applications like ADAS, IVI, and body control. Renesas’ new R-Car Open Access (RoX) platform provides a development environment with essential hardware, operating systems, and tools for seamless SDV development. This platform accelerates development and enables continuous software updates, critical in the SDV era.

A Vision for Automotive Innovation

The R-Car X5H’s impact on automotive technology is underscored by Asif Anwar, Executive Director of Automotive Market Analysis at TechInsights, who notes that the shift to SDVs will drive the market for high-performance compute SoCs. With its advanced 3-nm process, Renesas’ new SoC enables OEMs to meet power and performance demands across vehicle platforms, enhancing the integration of critical features within zonal and centralized controllers.

Renesas is showcasing the R-Car Gen 5 platform at electronica 2024 in Munich, where the development environment will be demonstrated. This advancement in automotive compute technology paves the way for a new generation of vehicles defined by powerful, efficient, and adaptable SoCs.

The post Renesas Launches Industry-First 3nm Multi-Domain SoC for Automotive, Revolutionizing Software-Defined Vehicle Development appeared first on ELE Times.