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‘Nature Electronics’ Paper Details System That Blends Best Traits Of Once-Incompatible Technologies—Ferroelectric Capacitors and Memristors

Breaking through a technological roadblock that has long limited efficient edge-AI learning, a team of French scientists developed the first hybrid memory technology to support adaptive local training and inference of artificial neural networks.

In a paper titled “A Ferroelectric-Memristor Memory for Both Training and Inference” published in Nature Electronics, the team presents a new hybrid memory system that combines the best traits of two previously incompatible technologies—ferroelectric capacitors and memristors into a single, CMOS-compatible memory stack. This novel architecture delivers a long-sought solution to one of edge AI’s most vexing challenges: how to perform both learning and inference on a chip without burning through energy budgets or challenging hardware constraints.

Led by CEA-Leti, and including scientists from several French microelectronic research centers, the project demonstrated that it is possible to perform on-chip training with competitive accuracy, sidestepping the need for off-chip updates and complex external systems. The team’s innovation enables edge systems and devices like autonomous vehicles, medical sensors, and industrial monitors to learn from real-world data as it arrives adapting models on the fly while keeping energy consumption and hardware wear under tight control.

The Challenge: A No-Win Tradeoff

Edge AI demands both inference (reading data to make decisions) and learning (updating models based on new data). But until now, memory technologies could only do one well:

• Memristors (resistive random access memories) excel at inference because they can store analog weights, are energy-efficient during read operations, and the support in-memory computing.
• Ferroelectric capacitors (FeCAPs) allow rapid, low-energy updates, but their read operations are destructive—making them unsuitable for inference.

As a result, hardware designers faced the choice of favoring inference and outsourcing training to the cloud, or attempt training with high costs and limited endurance.

Training at the Edge

The team’s guiding idea was that while the analog precision of memristors suffices for inference, it falls short for learning, which demands small, progressive weight adjustments.

“Inspired by quantized neural networks, we adopted a hybrid approach: Forward and backward passes use low-precision weights stored in analog in memristors, while updates are achieved using higher-precision FeCAPs. Memristors are periodically reprogrammed based on the most-significant bits stored in FeCAPs, ensuring efficient and accurate learning,” said Michele Martemucci, lead author of the paper.

The Breakthrough: One Memory, Two Personalities

The team engineered a unified memory stack made of silicon-doped hafnium oxide with a titanium scavenging layer. This dual-mode device can operate as a FeCAP or a memristor, depending on how it’s electrically “formed.”

• The same memory unit can be used for precise digital weight storage (training) and analog weight expression (inference), depending on its state.
• A digital-to-analog transfer method, requiring no formal DAC, converts hidden weights in FeCAPs into conductance levels in memristors.

This hardware was fabricated and tested on an 18,432-device array using standard 130nm CMOS technology, integrating both memory types and their periphery circuits on a single chip.

The post French Team Led by CEA-Leti Develops First Hybrid Memory Technology Enabling On-Chip AI Learning and Inference appeared first on ELE Times.

Microchip’s MCP9604 thermocouple conditioning IC reduces the cost and complexity of in-line production applications that operate in high and low temperature extremes

Precision four-channel temperature measurement is critical for production-line applications ranging from chemical and food processing, manufacturing process control and medical and HVAC equipment to refrigerated, cryogenic and other carefully controlled environments. With the introduction of the MCP9604 integrated thermocouple conditioning IC, Microchip Technology has overcome a thermal measurement and integration barrier with the first single-chip, four-channel  I2C thermocouple conditioning IC to deliver up to ± 1.5°C accuracy and provide an alternative to discrete and multichip thermocouple conditioning solutions that can introduce errors and add system design complexity.

“For more than two centuries, the thermocouple has been a critical tool for measuring extremely high temperatures, but the necessary precision and accuracy could not be achieved with the level of integration and cost-effectiveness that is required for today’s demanding production-line applications,” said Keith Pazul, vice president of Microchip’s mixed-signal linear business unit. “Our device now delivers a combination of precision, integration and cost-effectiveness, helping reduce the need for as many as 15 discrete components and associated system design challenges.”

The MCP9604 device delivers its advanced measurement accuracy at four thermocouple locations by using higher-order NIST ITS-90 equations rather than the single-order linear approximations of analog amplifier designs. As an example, it achieves ninth-order accuracy with K-type thermocouples, all in one integrated chip containing the ADCs, cold junction compensation temperature sensors, amplifiers and other components required for the signal chain, temperature measurement and math engine.

Removing the need for external components simplifies PCB design, reduces bill of materials costs, and can help eliminate the weeks of costly, time-consuming and complex unit-by-unit in-line validation and calibration that discrete solutions require in the thermocouple measurement signal chain before they can begin reporting data to the host system.

The MCP9604 also offers flexibility and versatility by supporting the eight most common thermocouple types including the J option as well as the K option for operating at temperatures as low as
-200°C. In addition to supporting a wide, -200°C to +1372°C temperature range across a diverse range of industrial applications, the MCP9604 also supports I2C communication to allow easy integration with microcontrollers and other digital systems.

Building on Earlier Advancements

The MCP9604 builds on the release of Microchip’s single-channel thermocouple conditioning IC, the first all-in-one device to deliver up to ± 1.5°C accuracy. The core competencies that made this device possible have paved the way for the company’s four-channel single-chip MCP9604 device that delivers its digital temperature reading with industry-high accuracy levels for an I2C thermocouple conditioning device.

The post Four-Channel Thermocouple Measurement with Integrated Conditioning Now Possible with ±1.5°C System Accuracy appeared first on ELE Times.

Of course it's not GaN and doesn't output what it says. 5 volt output at maybe 2 amps if it feels like it. Guess the case is cheap to print on. submitted by /u/junktech [link] [comments]

КПІ ім. Ігоря Сікорського у Вроцлаві: нові можливості для віддалених лабораторій kpi пн, 09/29/2025 - 01:00

submitted by /u/m_user_name [link] [comments]

In this article, we'll solidify our understanding of the reactance modulator and Armstrong modulator circuits by working through a series of design problems.

submitted by /u/AutoModerator
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submitted by /u/Cautious-Ninja-000 [link] [comments]

This program gives you a database of all the discrete parts you have and allows you to browse by category, checkout the part's datasheet, product page, and more. I created this for my lab because I always knew I had previous components that I could use for new projects, but locating them and finding the specs were too time consuming. It was usually easier just to buy new parts. With this system, it's easy to store parts, locate them, evaluate them for your project, and check them out from inventory. The whole thing runs on a raspberry Pi and hosts the parts library digitally which can be accessed by anyone on the local network. The code and details can be found at the project GitHub. I have a lot more information there: github.com/grossrc/DigiKey_Organizer If you use the program, consider donating it would help me put a lot. Hope this is useful to you guys! submitted by /u/MaxwellHoot [link] [comments]

submitted by /u/Green-Pie4963 [link] [comments]

New sensing solutions, from pyroelectric infrared sensors to in-plane Hall-effect switches, help engineers improve performance and efficiency in space-constrained designs.

Рамкова угода про співпрацю та академічну мобільність між КПІ ім. Ігоря Сікорського та École Polytechnique KPI4U-2 пт, 09/26/2025 - 20:53

At the European Conference on Optical Communication (ECOC 2025) in Copenhagen, Denmark (29 September–1 October), the Optical Internetworking Forum (OIF), together with 35 participating member companies, is demonstrating how multi-vendor collaboration is delivering real-world interoperability and enabling the scale, speed and efficiency that future networks demand...

In booth C4107 at the European Conference on Optical Communication (ECOC 2025) in Copenhagen, Denmark (29 September–1 October), TRUMPF Photonic Components GmbH of Ulm, Germany (part of the TRUMPF Group) — which makes vertical-cavity surface-emitting lasers (VCSELs) and photodiodes for datacoms — is showcasing linear performance of its new PAM4 100Gbps, 850nm multimode VCSEL in collaboration with customer Optomind Inc of Suwon, South Korea, which provides optical interconnect solutions for data centers including artificial intelligence (AI) and high-performance computing (HPC) networks. Along with the VCSEL, TRUMPF also offers a 100G wideband (842–948nm) photodiode that can be used to further optimize the link...

In a live demo in booth C4107 at the European Conference on Optical Communication (ECOC 2025) in Copenhagen, Denmark (29 September–1 October), TRUMPF Photonic Components GmbH of Ulm, Germany (part of the TRUMPF Group) is unveiling its new 100G vertical-cavity surface-emitting laser (VCSEL)...

Motorola’s 68000 blended 32-bit power with a 16-bit bus, creating a balanced, orthogonal, and elegant architecture that powered everything from Macintosh to arcade machines.

Edge AI—enabling autonomous vehicles, medical sensors, and industrial monitors to learn from real-world data as it arrives—can now adopt learning models on the fly while keeping energy consumption and hardware wear under tight control.

It’s made possible by a hybrid memory system that combines the best traits of two previously incompatible technologies—ferroelectric capacitors and memristors—into a single, CMOS-compatible memory stack. This novel architecture has been developed by scientists at CEA-Leti, in collaboration with scientists at French microelectronic research centers.

Their work has been published in a paper titled “A Ferroelectric-Memristor Memory for Both Training and Inference” in Nature Electronics. It explains how it’s possible to perform on-chip training with competitive accuracy, sidestepping the need for off-chip updates and complex external systems.

 

The on-chip memory conundrum

Edge AI requires both inference for reading data to make decisions and learning, a.k.a. training, for updating models based on new data on a chip without burning through energy budgets or challenging hardware constraints. However, for on-chip memory, while memristors are considered suitable for inference, ferroelectric capacitors (FeCAPs) are more suitable for learning tasks.

Resistive random-access memories or memristors excel at inference because they can store analog weights. Moreover, they are energy-efficient during read operations and better support in-memory computing. However, while the analog precision of memristors suffices for inference, it falls short for learning, which demands small, progressive weight adjustments.

On the other hand, ferroelectric capacitors allow rapid, low-energy updates, but their read operations are destructive, making them unsuitable for inference. Consequently, design engineers face the choice of either favoring inference and outsourcing training to the cloud or carrying out training with high costs and limited endurance.

This led French scientists to adopt a hybrid approach in which forward and backward passes use low-precision weights stored in analog form in memristors, while updates are achieved using higher-precision FeCAPs. “Memristors are periodically reprogrammed based on the most-significant bits stored in FeCAPs, ensuring efficient and accurate learning,” said Michele Martemucci, lead author of the paper on this new hybrid memory system.

How hybrid approach works

The CEA-Leti team developed this hybrid system by engineering a unified memory stack made of silicon-doped hafnium oxide with a titanium scavenging layer. This dual-mode memory device can operate as a FeCAP or a memristor, depending on its electrical formation.

In other words, the same memory unit can be used for precise digital weight storage (training) and analog weight expression (inference), depending on its state. Here, a digital-to-analog transfer method, requiring no formal DAC, converts hidden weights in FeCAPs into conductance levels in memristors.

The hardware for this hybrid system was fabricated and tested on an 18,432-device array using standard 130-nm CMOS technology, integrating both memory types and their periphery circuits on a single chip.

CEA-Leti has acknowledged funding support for this design undertaking from the European Research Council and the French Government’s France 2030 grant.

Related Content

• Speak Up to Shape Next-Gen Edge AI
• AI at the edge: It’s just getting started
• Will Memory Constraints Limit Edge AI in Logistics?
• Two new runtime tools to accelerate edge AI deployment
• For Leti and ST, the Fastest Way to Edge AI Is Through the Memory Wall

The post Hybrid system resolves edge AI’s on-chip memory conundrum appeared first on EDN.

Took a 10s charger and slapped a 1800w boost converter on it that has cc/cv and goes up to 125v DC. Just need to add XT30/60 and 90 contacs on it so that I have different options for different batteries. Going to change out the 10s charger for a 1500w power supply and add a volt/amp/WH display and change the pot on cc for a similiar one that i have changed the cv pot for allready and put a 800w buck converter that has CC/CV to be able to charge smaller batteries than 10s also. submitted by /u/Whyjustwhydothat [link] [comments]

There are various ways to construct a motor, and the properties of that motor will depend on the construction choice. The series motor configuration has some desirable properties, but it can become quite dangerous to use if proper safety precautions are overlooked.

“Motors,” per se, is a complex subject. Variations in motor designs abound and lie well outside the scope of this essay. Rather, the goal here is to focus on just one aspect of one particular type of motor. To pay proper homage, Figure 1 shows three basic motor designs.

Figure 1 The three basic DC motor types, this article focuses on DC series motor.

Readers may study the first two at their leisure, but we will focus on the DC series motor highlighted in green and begin with an examination of its basic structure.

The DC series motor

A magnetic field is required. That field is provided by current-carrying coils that are wound over steel structures called “poles”. The number of poles may vary from design to design. Simple-mindedly, Figure 2 shows three examples of pole design: two poles, four poles, and six poles. Note the alternation of north (N) and south (S) magnetic polarities.

The armature is shown as a setup for four (Figure 2) paralleled paths of wires that are insulated from each other but tied at their ends. In the example shown, there are twenty-four armature conductors arranged in six groups of four conductors, or in four parallel paths, each.

Figure 2 The DC series motor structure showing two, four, and six poles with alternating N and S polarities.

It is conventional to use the letter “Z” to represent the number of armature conductors (twenty-four as shown) and the letter “A” to represent the number of paralleled conductors (four as shown) in each path. Please do not be confused by the fact that this “Z” does NOT refer to an impedance and that this “A” does NOT refer to an area.

As shown in Figure 3, we now look at the circuit of this structure.

The field coils, wrapped around each pole, are connected in series to form the field coil.

The armature conductor groups are wired in series, with their returns being made through the center of the armature, where their wire movement is slowest. By contrast, the outermost sections of the armature conductor groups move quite rapidly as they cross the magnetic flux lines of the poles and since they are all connected in series, they generate a summation voltage called the “back electromotive force” or the “back EMF”.

Figure 3 The DC series motor equivalent circuit, the series connections of the outermost sections of the armature conductor generating back EMF.

The current flowing in the field coil and the current flowing in the armature is the same current. There is no other place for the current to flow. The available torque of a DC series motor is therefore proportional to the square of that current. By using really heavy and large conductors for both, that current can be made very large, and the available torque can be made very high. Such motors are used in high torque applications such as engine starters, in heavily loaded and slow-moving lifting cranes, commuter railroad cars, and other such applications.

The governing equation for generating back EMF is as follows in Figure 4.

Figure 4 The governing equation for back EMF, where the back EMF equals the total magnetic flux multiplied by the rotational speed multiplied by the number of series-connected armature groups.

The total magnetic flux equals the flux per pole times the number of poles. The back EMF equals the total magnetic flux multiplied by the rotational speed multiplied by the number of series-connected armature groups, which, for our present example, will be six for our six-pole magnetic structure.

Connect the load!

Now comes the crucial point to remember about DC series motors.

For safety’s sake, no DC series motor should ever be operated without a mechanical load. A DC shunt motor or a DC compound motor can be safely operated without a mechanical load (separate discussions), but a DC series motor CANNOT be safely operated that way. 

When the DC series motor is operating, there will be some back EMF generated in the armature as shown in Figure 4. That back EMF will act in opposition to the input voltage in determining the field and armature current, as shown in Figure 3 and as follows:

However, suppose a DC series motor is allowed to run without a mechanical load as the DC series motor undergoes rotary acceleration and starts to gain rotational velocity. In that case, a current flow exists for which some measure of torque exists for which there will be some measure of angular acceleration. With no mechanical load, the rotor will always be rotationally accelerating and gaining in rotational velocity because there is then no load to take rotational energy away from that rotating armature.

As the armature accelerates, the back EMF tends to rise, which lowers the current flow, which lowers the magnetic flux, which lowers the torque, but the flux and the torque do not go to zero, and the rotational velocity will continue to rise. The rotational velocity will keep increasing, tending toward further raising the back EMF, which further reduces the current flow, which further reduces the magnetic field as the rotational velocity continues to increase, and so on and so on, but it is in a vicious cycle of rotary speed-up that constitutes a runaway condition. If there is no mechanical load on the armature, there will be no upper limit on the armature’s speed of rotation, and the DC series motor can and will destroy itself.

A story

It is stridently recommended that any mechanical load being driven by a DC series motor be coupled to that motor by a gear mechanism and never by a belt because a belt can break. If such a break occurs, the DC series motor will have no mechanical load, and as described, it will run away with itself.

This issue was taught to my class by my instructor, Dr. Sigfried Meyers, when I was in Brooklyn Technical High School in Brooklyn, NY. There was a motor lab area. Dr. Meyers told us of one day when there was no faculty supervision at hand, several students snuck into that lab and decided to hook up a lab motor in a series motor mode with no mechanical load. When they applied power, the motor did exactly as Dr. Meyers had warned that it would do, and the motor was destroyed.

As Mr. Spock would put it on Star Trek, that was “an undesirable outcome”.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

 Related Content

• Brushless DC Motors – Part I: Construction and Operating Principles
• DC Motor Drive Basics – Part 1: Thyristor Drive Overview
• Electric motor: types, operation modes
• Speed Control Unit Designed for a DC Motor

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