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My recent teardown of a rechargeable vape device was…wow…popular. I suspected upfront that it might cultivate a modicum of incremental traffic from the vape-using (and vape-curious) general public, but…wow. This long-planned follow-up focuses on non-rechargeable (i.e., disposable) vape counterparts, in part fueled by my own curiosity as to their contents but more generally and predominantly driven by my long-standing bleeds-green environmental outrage.

Here’s an example of what I mean, showcased in a recent Slashdot post that highlighted a writeup in The Guardian:

Thirteen vapes are thrown away every second in the UK — more than a million a day — leading to an “environmental nightmare,” according to research.

There has also been a rise in “big puff” vapes which are bigger and can hold up to 6,000 puffs per vape, with single use vapes averaging 600. Three million of these larger vapes are being bought every week according to the research, commissioned by Material Focus, and conducted by Opinium. 8.2 million vapes are now thrown away or recycled incorrectly every week.

From June 2025 it will be illegal to sell single-use vapes, a move designed to combat environmental damage and their widespread use by children. Vapes will only be allowed to be sold if they are rechargeable or contain a refillable cartridge.

But all types of vape contain lithium-ion batteries which are dangerous if crushed or damaged because they can cause fires in bin lorries or waste and recycling centres. These fires are on the rise across the UK, with an increase last year of 71% compared with 2022.

I have (at least) two questions:

• If there are a million toxic chemical- and metal-leaching vapes headed to landfills (if we’re lucky; many, more likely, are sent directly into the water table via casual, irresponsible discard wherever it’s convenient for the owner to toss ‘em) in the UK alone, what’s that number look like when extrapolated to a worldwide count? Truthfully, from a blood pressure standpoint, I’m not sure I want to know the answer to that one.
• And why are vapes that are “rechargeable or contain a refillable cartridge” (bolded emphasis mine) excluded from the upcoming UK ban? Why can’t (and shouldn’t) it instead be only those that are “rechargeable and contain a refillable cartridge”?

Rant off. One of the comments I posted as follow-up to last November’s initial entry in this vape-teardown series pointed readers to near-coincident published related coverage in Ars Technica:

Disposable vapes are indefensible. Many, or maybe most, of them contain rechargeable lithium-ion batteries, but manufacturers prefer to sell new ones. More than 260 million vape batteries are estimated to enter the trash stream every year in the UK alone. Vapers and vape makers are simply leaving an e-waste epidemic to the planet’s future residents to sort out.

To make a point about how wasteful this practice is—and to also make a pretty rad project and video—Chris Doel took 130 disposable vape batteries (the bigger “3,500 puff” types with model 20400 cells) found littered at a music festival and converted them into a 48-volt, 1,500-watt e-bike battery, one that powered an e-bike with almost no pedaling more than 20 miles.

The accompanying video is well worth your viewing time, IMHO.

and gave me the confidence to attempt my own teardown of conceptually similar vape devices, since Doel had confidently just ripped off the tip and back ends to get to their insides. Here’s the implement of destruction that I personally used:

And here are today’s victims, extracted from the trash as was the case with their rechargeable predecessor, and as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes (not to mention roll-away prevention purposes):

The upper one is actually (supposedly, although there are still loopholes, apparently) no longer available in the US. It’s the “4000 puff” Noms X product variant (and Mojito Mint flavor) of the Esco Bars brand, manufactured by the Chinese company Shenzhen Innokin Technology. And no, I have no idea what “Pastel Cartel” means. The lower vape is Mr Fog ‘s “2000 puffs” Max pro model (and Raspberry Grape Black Currant flavor).

Here are their respective tips:

And their bottoms:

The black-color bottom end of the Esco Bars vape is fixed in position; note the two holes for incoming-airflow purposes. You’ll shortly see what secondary function the one in the middle also serves; that said, I’m not sure of the purpose of the incremental smaller second offset one. The white-color end of the Mr Fog vape, conversely, can be rotated to user-adjust the airflow. The two vents are on the sides of the end piece; here’s how airflow adjustment operates:

and briefly jumping ahead in time mid-teardown, here’s how it’s implemented:

Let’s start the disassembly process with the Esco Bars device, as previously mentioned by wrenching the bottom piece off with my pliers (see what I did there?).

That black rectangular spongy piece went flying when I pulled the bottom piece off, but I’m guessing from the lingering indentations that it normally sits in-between that thing that looks like a microphone (and fits inside the circular middle portion of the bottom piece) and the battery. And about that “thing that looks like a microphone”…I was initially a bit flummoxed when I saw it (no, I never thought it was actually a microphone, although other folks were amusingly-to-me apparently convinced otherwise), until I realized that neither vape has an on-off switch. Instead, what you do to “turn them on” (i.e., power up the heating coil) is to suck on the tip, which vapers refer to as a “draw”.

This “thing that looks like a microphone”, apparently, is a “draw sensor”; it detects the resultant user-generated airflow that’s initiated from the bottom and (as is already obvious even with the battery still in place) passes from there through the gap between the battery and vape body. This Quora thread has all the details, including pictures of a sensor that looks just like the one in the Esco Bars vape (and the Mr Fog one, for that matter, prematurely ruining the surprise…sorry). I’m guessing that the red and black wires route to the sensor from the battery, and the blue one carries a signal sent by the sensor to the heating coil when airflow is detected.

By repeatedly shaking the vape device (with a foam cushion underneath, in case the contents went flying) I got the battery out of the case far enough:

that I was then able to get a grip on it with my fingers and pull it the rest of the way out:

The remainder of the internals remained stubbornly stuck at the rear end of the tube until I started twisting on the tip with the wrench:

At which point the translucent tube fell out the bottom, too. Disgusting (and oily, too), huh?

From my research (I’ve learned more than I ever wanted to about vapes the past 24 hours or so), inside the plastic tube are apparently nicotine salts, soaked in the flavored vape juice. Here’s the entirety of the insides, stretched out:

And here’s what you’ve all been waiting for, the battery specs, 3.7V and 5.55 Wh:

Now for the Mr Fog vape. Again, I started with the white bottom piece, which initially didn’t get me very far (although look; another “microphone”):

So, I switched to the tip, which didn’t get me much further along…and yuck, again:

Back to the bottom for more twisting, this time of the clear plastic piece that as I showed you earlier, the white bottom piece fits around. That’s better:

Once again, a combination of shaking and two-finger pinching-and-pulling got the battery out:

But this time I had to then push from the top to get the rest out:

Greasy, smelly mission completed:

And the battery specs: once again 3.7V, but this time only 4.07 wH/1100 mAh, reflective of the Mr Fog vape’s comparative “half the puffs” estimate versus the Esco Bars alternative.

In closing, what most surprised me, I guess, is that neither of these vapes use standard 18650 cells found in a diversity of other devices (although from some of my research, their limited spec’d peak output current capabilities might be a coil-heating hinderance or, worse, a thermal safety complication in this particular application), or even the less common 20400 ones showcased in the video at the beginning of this writeup. With that, I’ll wrap up, take a deep draw (of nicotine-free air, mind you) and await your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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• Diagnosing and resuscitating a set of DJI drone batteries

The post Disposable vapes: Unnecessary, excessive waste in cylindrical shapes appeared first on EDN.

Mining exploration company Nimy Resources Ltd of Perth, Western Australia has signed a non-binding memorandum of understanding (MoU) with Perth-based Curtin University to collaborate on advancing gallium-related research, development and production. The strategic partnership aligns with Nimy’s aim to become a key supplier in the rapidly expanding global gallium market...

Introduction: The Paradigm Shift in Semiconductor Packaging

As Moore’s Law faces physical limitations, the semiconductor industry is increasingly turning to advanced packaging solutions to sustain performance gains. Traditional monolithic scaling is no longer viable for delivering the power efficiency and computational throughput required by next-generation applications like artificial intelligence (AI), high-performance computing (HPC), 5G, and edge computing. Instead, innovations in heterogeneous integration, 2.5D and 3D packaging, chiplet architectures, and fan-out wafer-level packaging (FOWLP) are redefining performance metrics.

This article provides an in-depth analysis of cutting-edge packaging technologies, their impact on semiconductor performance, and real-world case studies from leading industry players such as Broadcom, Nvidia, and GlobalFoundries.

The Evolution of Advanced Packaging Technologies

1. 2.5D Integration: The Bridge Between Traditional and 3D Packaging

2.5D integration involves placing multiple semiconductor dies on a silicon interposer, allowing high-speed interconnections. Unlike conventional multi-chip modules (MCMs), 2.5D technology provides lower latency due to short interconnect distances, higher bandwidth through wide bus architectures, and reduced power consumption by eliminating long copper traces. These advantages make it an ideal solution for applications requiring high computational power and data transfer speeds.

Case Study

Broadcom’s 3.5D XDSiP for AI Acceleration Broadcom recently introduced 3.5D Extended Data Scale in Package (XDSiP) technology, enhancing AI chip interconnectivity using TSMC’s advanced packaging techniques. With production shipments expected by 2026, Broadcom aims to support hyperscale cloud providers in meeting AI’s high bandwidth demands by leveraging this innovative packaging solution.

2. 3D Stacking: The Revolution in Vertical Integration

Unlike 2.5D, 3D stacking vertically integrates multiple dies using Through-Silicon Vias (TSVs) and wafer-to-wafer bonding. This architecture significantly reduces data transmission delays, lowers power dissipation, and increases computational density. By enabling high-speed data transfer with minimal signal loss, 3D stacking is particularly useful for applications requiring fast processing speeds. Additionally, the smaller form factors allow for more compact semiconductor devices, while improved thermal efficiency is achieved through optimized heat dissipation layers.

Case Study

Nvidia’s CoWoS-L in AI Chips Nvidia’s latest AI processor, Blackwell, utilizes Chip-on-Wafer-on-Substrate Large (CoWoS-L) technology, moving beyond traditional CoWoS-S to enhance interconnect performance. This advancement is part of Nvidia’s broader strategy to improve AI workload efficiency and silicon utilization, ensuring faster and more efficient data processing capabilities.

3. Chiplet-Based Architectures: The Future of Modular Semiconductor Design

The industry is transitioning toward chiplet architectures, where small, specialized dies are interconnected within a package to increase performance flexibility and yield efficiency. Unlike monolithic designs, chiplets enable heterogeneous integration, allowing processors, memory, and accelerators to coexist within a single package. This approach reduces manufacturing costs by reusing tested chiplets while improving scalability by mixing process nodes within a package. Additionally, smaller die sizes contribute to better yield efficiency, ultimately enhancing semiconductor performance and reliability.

Case Study

AMD’s EPYC and Intel’s Meteor Lake AMD and Intel have embraced chiplet designs to improve scalability in their high-performance processors. AMD’s EPYC server CPUs leverage multiple CCD (Core Complex Die) chiplets, while Intel’s Meteor Lake integrates different chiplets for CPU, GPU, and AI acceleration, demonstrating the advantages of modular semiconductor design.

4. Fan-Out Wafer-Level Packaging (FOWLP): Enhancing Thermal and Electrical Performance

FOWLP extends the package beyond the die’s boundaries, increasing I/O density while maintaining a compact footprint. This method eliminates wire bonding, improving electrical and thermal properties. With higher bandwidth compared to traditional wire-bond packaging, FOWLP enhances signal integrity while providing better heat dissipation for high-power applications. Furthermore, reduced parasitic capacitance ensures minimal signal interference, making this packaging technique essential for next-generation semiconductor devices.

Case Study

Apple’s A-Series Processors Apple extensively uses FOWLP in its A-series chips, ensuring high-performance computing in iPhones and iPads with minimized power loss and improved thermal control. By integrating this packaging solution, Apple enhances both power efficiency and processing capabilities, delivering seamless user experiences.

Impact of Advanced Packaging on Semiconductor Performance

1. Performance Gains: Pushing Computational Boundaries

By reducing interconnect lengths and signal latency, advanced packaging significantly enhances processing speeds for AI and HPC applications. Improved memory bandwidth allows for faster data transfer, benefiting workloads such as AI model training and deep learning inference. Additionally, data center efficiency is greatly improved as power-hungry interconnect bottlenecks are minimized, ensuring higher computational throughput.

2. Power Efficiency: Addressing Thermal Constraints

Advanced packaging solutions lower power consumption by optimizing shorter interconnect paths that reduce energy dissipation. Better thermal management is achieved using advanced cooling layers, preventing overheating issues in high-performance applications. The integration of energy-efficient AI accelerators, such as low-power chiplets, further enhances power efficiency, ensuring sustainable semiconductor performance.

3. Miniaturization and Integration: The Path to More Compact Devices

With increasing demand for smaller form factors, advanced packaging enables higher transistor densities, improving device functionality. The integration of specialized components, such as RF, memory, and AI accelerators, allows for more efficient processing while maintaining compact device sizes. Heterogeneous system architectures facilitate multi-functional capabilities, paving the way for highly sophisticated semiconductor solutions.

Challenges in Advanced Packaging Adoption

1. Manufacturing Complexity

The fabrication of interposers and TSVs in advanced packaging incurs high costs due to precision alignment requirements. Yield challenges arise as the complexity of packaging increases, necessitating stringent quality control measures to ensure production efficiency.

2. Thermal Management Issues

As power density increases, overheating becomes a major challenge in advanced packaging. To counter this, new cooling solutions such as liquid and vapor chamber technologies are being explored to enhance heat dissipation and ensure thermal stability in high-performance devices.

3. Design & Validation Bottlenecks

With the rise of chiplet-based designs, EDA tools need advancements to model complex architectures accurately. Testing complexity also increases due to heterogeneous integration, requiring innovative validation techniques to streamline semiconductor development.

Future Trends in Semiconductor Packaging

1. Heterogeneous Integration at Scale

The future of semiconductor packaging lies in combining logic, memory, and RF components within a unified package. This integration will pave the way for neuromorphic and quantum computing applications, unlocking new possibilities in computational efficiency.

2. Advanced Materials for Packaging

High-performance substrates, such as glass interposers, are gaining traction for improving signal integrity. Additionally, the development of low-k dielectrics is expected to reduce capacitance losses, further enhancing semiconductor performance.

3. Standardization of Chiplet Interconnects

Industry efforts like UCIe (Universal Chiplet Interconnect Express) aim to create cross-compatible chiplet ecosystems, allowing seamless integration of different semiconductor components.

4. AI-Driven Automation in Packaging Design

Generative AI algorithms are optimizing power, performance, and area (PPA) trade-offs, accelerating semiconductor design processes. AI-enabled defect detection and yield improvement strategies are also becoming integral to advanced packaging manufacturing.

Conclusion: The Road Ahead for Semiconductor Performance Enhancement

Advanced packaging is reshaping the future of semiconductor design, driving performance improvements across AI, HPC, and mobile computing. As the industry continues to innovate, overcoming challenges in manufacturing, thermal management, and validation will be crucial in sustaining growth. The next decade will witness a convergence of materials science, AI-driven automation, and heterogeneous integration, defining a new era of semiconductor technology.

The post Advanced Packaging Solutions: Pushing the Limits of Semiconductor Performance appeared first on ELE Times.

Texas Instruments’ APEC-related releases are power management chips centered around supporting the AI-driven power demands in data centers. The releases include the first 48-V integrated hot-swap eFuse with power-path protection (TPS1685) and an integrated GaN power stage (gate driver + FET) in the industry-standard TOLL package. 

In a conversation with Priya Thanigai, VP and Business Unit Manager of power switches at Texas Instruments, EDN obtained some insights on meeting the needs of next-generation racks demanding the 48-V architecture.

Spotlight on data centers

Hot topics at APEC typically encompassed the use of wide bandgap semiconductors like silicon carbide (SiC) and gallium nitride (GaN) to yield higher efficiency subsystems in the steady electrification of technologies. Electrified end applications have spanned from e-mobility to industrial processes that are enabled by battery and smart grid advancements. 

Discussions this year have shifted more toward the power demands that generative AI has created for data centers. While much of the actual power consumption of these data centers remains secretive, it’s apparent that LLMs like ChatGPT and DeepSeek have created a substantial increase; the U.S. data center electricity usage tripled from 2014 to 2023 according to the U.S. department of energy (DoE). The number is anticipated to double or triple by 2028.

The international energy agency (IEA) also reported that data centers consumed ~1.4-1.7% of global electricity in 2022; this is also expected to double by 2026. According to the World Economic Forum, “the computational power needed for sustaining AI’s growth is doubling roughly every 100 days.”

Going nuclear

Hyperscalers are also making more apparent their plans to sustain the energy demands. In September 2024, plans to recommission the Three Mile Island nuclear plant were made public with a 20-year contract to help power Microsoft data centers. Other technology companies follow a similar nuclear path, augmenting power capabilities with small modular reactors (SMRs).

And as the semiconductor industry is feverishly fabricating chips that can efficiently run these compute-intensive training tasks through software-hardware codesign, the power demands continually soar. Further into the future, these nuclear reactors could be used with solid-state transformers to support data center processing.

The 48-V bus and beyond

The data center server room consists of a sea of IT racks supported by a sidecar that holds hot-swappable power supply units (PSUs) that facilitate replacing or upgrading a PSU without shutting down the server (Figure 1). These PSUs support much higher power densities moving from 6 kW with the 48-V bus to 100 MW with the 400-V bus.

Figure 1: Sidecar, IT rack, and supporting subsystems shown at the TI booth during APEC 2025. 

“While data centers have been ahead of the curve, cars are only now moving to 48 V,” said Thanigai. “But data centers have probably already been there for about a decade.” It’s just been very slow because earlier systems really didn’t need the compute power until LLMs exploded. Until then, it was only the high-end GPUs that needed that extra power at 48 V.

She mentioned how TI had been keeping a watchful eye on the relatively slow move from 12-V products for data centers 48-V and how recent pressures have brought on that inflection point. “Now we’re seeing more native 48-V systems ship and we’re talking about 400-V already,” Thanigai said. “So the transition from 12 V to 48 V may have taken a decade to hit the inflection point but 48 V to 400 V will probably be shorter and sharper because of how much energy is needed by data centers.”

Moving from discretes to integrated eFuses

Power path protection is tied directly to PSU reliability and is therefore a critical aspect of ensuring zero downtime deployments. The 48-V eFuse is a successor to the popular 12-V eFuse category; the shift to 48 V allows users to scale power to beyond 6 kW. 

“If you’re looking at the power design transition, generally power architectures will begin with discretes at the start of any design because they want to get a good feel of how to build something,” explained Thanigai. The building blocks of power path protection generally include the power FET, a gate or voltage drive to drive it, and components like a soft-start capacitor to control the inrush, comparators, and current-sense elements.

Thanigai described the moves toward more integration where the hot swap controller integrates the amplifiers, some of the protection features, and some of the smarts. However, there still remains an external FET and sensing element. 

“The last leg of the integration is eFuse where the FET, the controller, and all the smarts are in a single chip,” she said. “That’s a classic power design evolution, where you go from discrete to semi-integrated to fully integrated.” The TPS1685 eFuse includes protection features like rapid response to fault events with an integrated black box for fault logging. Then there is a user-configurable overcurrent blanking timer that avoids false tripping at peak inrush.

Advanced stacking for loads > 6 kW

Mismatches in the on-state resistance (Rdson) due to PCB trace resistance and comparator thresholds can create false tripping (Figure 2). The conventional discrete designs require power architects to hand calculate the margins to make sure the FETs are matched such that no single FET is taking on more thermal stress than the others.  

Figure 2: Discrete implementations require individual calculations per sense element and FET to take into account mismatches at each node; instead Rdson is actively adjusted via Vgs regulation and equal steady-state current across all devices is achieved through path resistance equalization. Source: Texas Instruments 

The IP in the TPS1685 eFuse actively measures and monitors the thermal stress at various areas of the FET within each of the eFuses and balances current between each automatically through a single-wire protocol. The integration designates one eFuse as the primary controller to monitor total system current by using the interconnected IMON pins, enabling active RDS(ON) shifting to ensure devices are current-sharing.

“You can basically stack unlimited eFuses,” said Thanigai, “We’ve shown up to 12 operational eFuses on a customer board and each of them can do 1 kW (~ 50 V @ 20 A), so we easily reach the 5-10 kW that you see with systems nowadays. But we can scale higher than that since there’s no upper limit.”

Figure 3: Image of 6 eFuses stacked in parallel on the top and bottom of a PCB to support a maximum load current of 120 A. 

Moving toward 400 V

When asked about the move toward supporting 400-V bus architectures, Thanigai responded, “There’s two aspects in these eFuses.” There’s the pure analog power domain, which is the FET architectures, and then there’s the digital domain which embodies smarts around the FET, she added.

All of the digital IP TI has developed scales from 12 V to 48 V to 400 V, and that while this particular device includes 48-V power FETs, TI is preparing to scale this up to 400 V.

Aalyia Shaukat, associate editor at EDN, has worked in the design publishing industry for six years. She holds a Bachelor’s degree in electrical engineering from Rochester Institute of Technology, and has published works in major EE journals as well as trade publications.

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The post Data center power meets rising energy demands amid AI boom appeared first on EDN.

Lumentum Holdings Inc of San Jose, CA, USA (which designs and makes optical and photonic products for optical networks and lasers for industrial and consumer markets) has been selected as a key contributor in NVIDIA’s silicon photonics ecosystem. Lumentum’s high-power, high-efficiency lasers have a crucial role in the development and deployment of new NVIDIA Spectrum-X Photonics networking switches...

Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA says that its portfolio of 3.2kW, 4.5kW and 8.5kW AI data-center power supply unit (PSU) designs exceed the new 80 PLUS ‘Ruby’ certification, focused on the highest level of efficiency for redundant server data-center PSUs...

Discrete device designer and manufacturer Nexperia of Nijmegen, the Netherlands (which operates wafer fabs in Hamburg, Germany, and Hazel Grove Manchester, UK) has added to its expanding e-mode GaN FET portfolio with 12 new devices intended to address the growing demand for higher efficiency and more compact systems...

Поїздка в Японію: тиждень у країні надсучасних технологій та стародавніх традицій Інформація КП вт, 03/18/2025 - 19:25

I’ve been working on this project for a while, and I’d like to share the progress here. I hope it will be interesting.This is ZX Spectrum 48k clone which I've designed and built myself. I've cheated a bit -- it has no video circuitry, HDMI video signal is generated by ZX-HD extension board(visible at the far side of the motherboard, I've bought it online). Next steps is USB keyboard adapter and 3D printed case. submitted by /u/Raynor-73 [link] [comments]

🍀 Інженерний тиждень «KPISchool» kpi вт, 03/18/2025 - 17:45

The venerable Stephen Woodward recently published the design idea (DI) “Flip ON flop OFF” that converts a momentary push button to a classic push-on, push-off switch. Figure 1 is an attempt to go further still in terms of economy.

The circuit shown in Figure 1 utilizes only one half of a dual D-type package and one more capacitor to the original parts count. It also incorporates an RC power on set (or reset), to guarantee the initial state of the switch when power is applied.

Figure 1 U1A debounces SW1 via R1 & C2 so U1A can reliably toggle.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The initial state of the switch is determined by the Set pin of U1A following the rising voltage on the power input due to the initial discharged state of C1. Capacitor C1 then charges towards ground leaving the flip-flop with the Q output high and the PMOS off.

Alternatively, this RC power on Set circuit can be wired to the Reset pin to change the initial power on state of the switch. The device ESD clamping diodes provide the capacitor discharge path when power is turned off.

The D-type flip-flop is essentially connected in the familiar way of Q-bar to D-input to form a bistable with each clock rising edge toggling the output state. However, in this case the combination of R1 and C2 form a delay network which prevents rapid changes on the D-input, thus effectively de-bouncing the switch by inhibiting state changes until C2 has charged/discharged to the state on the Q-bar output.

—Chris Nother built a discrete Tx/Rx for model aircraft at an early age, later discovering the dreaded “Mains Hum” in a home built “Dinsdale” Hi-Fi amplifier. Employed in R&D using the then newly available available CMOS logic from Motorola and Nat-Semi, career changes to Mainframe Computers, design of disk drive automated test equipment and storage solutions, finally turning full circle in retirement to the hobby that started it all.

Related Content

• Flip ON flop OFF
• Use an op amp as a set/reset flip-flop
• New VFC uses flip-flops as high speed, precision analog switches
• CMOS flip-flop used “off label” implements precision capacitance sensor

The post Latching D-type CMOS power switch: A “Flip ON Flop OFF” alternative appeared first on EDN.

Steel soldering is a metal-joining process used to bond steel components by melting a filler metal with a lower melting point than the steel itself. Unlike welding, which fuses the base metals together, or brazing, which uses higher temperatures, soldering operates at relatively low temperatures (typically below 450°C or 840°F). This makes it suitable for delicate applications where excessive heat could damage the materials.

Soldering steel is more challenging than soldering other metals like copper or brass due to steel’s oxidation properties and lower thermal conductivity. To ensure a strong joint, fluxes and specialized soldering materials, such as tin-lead or silver-based alloys, are commonly used.

How Steel Soldering Works

Steel soldering follows a systematic approach that involves surface preparation, application of heat, and bonding with the help of solder and flux. The key principle behind the process is capillary action, where the molten solder flows into the microscopic gaps between metal surfaces, creating a strong mechanical and electrical bond.

The success of steel soldering depends on various factors, including the type of flux, the choice of solder alloy, and the precision of temperature control. Proper surface cleaning and oxide removal are crucial to achieving a reliable bond, as steel tends to develop an oxide layer that inhibits solder adhesion.

Steel Soldering Process

The steel soldering process consists of several essential steps. First, surface preparation is crucial. The steel surfaces must be cleaned thoroughly using sandpaper, steel wool, or chemical cleaners to remove dirt, grease, and oxidation. Once cleaned, an appropriate flux, such as zinc chloride or rosin-based flux, is applied to prevent oxidation and promote solder flow.

Next, selecting the right solder and flux is important. Lead-free solder alloys such as silver-based or tin-copper alloys are recommended for environmental safety. The flux should be compatible with the solder alloy to ensure proper wetting and adhesion.

The heating process follows, where a soldering iron, torch, or induction heating is used to bring the steel to the required temperature. Uniform heating is necessary to avoid weak joints and improper solder flow. Once the joint reaches the solder’s melting point, the solder wire or paste is introduced. The molten solder then flows into the joint through capillary action.

After soldering, the joint should be allowed to cool naturally without disturbance to prevent cracking. Once cooled, residual flux and oxidation are removed using warm water or specialized cleaning agents to ensure long-term durability.

Steel Soldering Uses & Applications

Steel soldering finds applications in a wide range of industries due to its ability to create strong, reliable joints at low temperatures. In the electronics and electrical industry, it is used in circuit boards, connectors, and electrical components where steel parts need reliable connections. It is also utilized for shielding applications for electromagnetic interference (EMI) protection.

In the automotive and aerospace industries, steel soldering is employed in small, heat-sensitive components, such as sensors and electrical connectors. Aerospace applications require precise soldering of critical parts to maintain structural integrity.

The HVAC systems and plumbing industries also benefit from steel soldering, particularly in joining refrigeration coils, pipe fittings, and heat exchangers. This method provides leak-proof and corrosion-resistant joints essential for efficient system performance.

Additionally, steel soldering is widely used in jewellery making and artistic metalwork. It allows artisans to create custom metal pieces, repair jewellery, and design decorative steel structures while maintaining an aesthetically pleasing finish. The medical industry also utilizes steel soldering in the manufacturing of surgical instruments and medical devices, ensuring precise and biocompatible metal bonding.

Steel Soldering Advantages

Steel soldering offers several advantages over other metal joining methods, making it an ideal choice for specific applications. One major advantage is its low heat requirement. Unlike welding, which involves high temperatures that can cause warping or damage, soldering operates at much lower temperatures, preserving the integrity of delicate components.

Another significant benefit is its versatility. Steel soldering can be used on thin or intricate steel components without compromising their structural integrity. The process creates strong and reliable bonds that are resistant to corrosion, ensuring long-term durability.

Cost-effectiveness is another advantage, as soldering requires minimal equipment and energy compared to welding and brazing. This makes it an economical choice for small-scale manufacturing and repairs. Moreover, soldering is relatively easy to learn and perform, requiring minimal training and no specialized machinery, making it accessible to both professionals and hobbyists.

A notable safety advantage is that soldering does not require specialized protective equipment. Unlike welding, which necessitates protective gear against UV radiation and fumes, soldering is a safer process with fewer health hazards.

Steel Soldering Disadvantages

Despite its benefits, steel soldering has certain limitations. One major drawback is that soldered joints are not as strong as welded joints, making them unsuitable for high-load applications. Additionally, soldered joints have limited heat resistance and may fail under high temperatures, restricting their use in environments where elevated temperatures are a concern.

Another challenge is oxidation. Steel tends to form an oxide layer quickly, which can hinder solder adhesion. This requires the use of aggressive fluxes or pre-cleaning treatments to ensure a strong bond. Environmental concerns also arise with traditional lead-based solder, as it poses health and environmental risks, leading to a shift toward lead-free alternatives.

Lastly, some fluxes used in the soldering process leave corrosive residues that must be thoroughly cleaned to prevent long-term damage to the joint. Proper cleaning procedures are necessary to maintain joint integrity and prevent issues such as corrosion or weak bonding over time.

Conclusion

Steel soldering is a valuable technique for low-temperature metal bonding, offering numerous advantages in electronics, automotive, HVAC, and medical applications. While it has certain limitations, proper material selection, surface preparation, and soldering techniques can help achieve strong and reliable bonds. As advancements in soldering technology continue, steel soldering is becoming even more efficient and environmentally friendly, making it a crucial method in modern manufacturing and repair industries.

The post Steel Soldering: Definition, Process, Working, Uses & Advantages appeared first on ELE Times.

On 25 March, Tokyo-based Mitsubishi Electric Corp will begin shipping samples of a new 16W-average-power gallium nitride (GaN) power amplifier module (PAM) for 5G massive MIMO (mMIMO) base stations. Operating in the 3.6–4.0GHz band, it can be widely deployed in North America and East and Southeast Asia. As 5G networks expand from urban centers to regional areas, mMIMO base stations, especially 32T32R mMIMO base stations (consisting of 32 transmitters and receivers), are expected to be increasingly deployed. Mitsubishi Electric says that its 16W GaN PAM is particularly suited to 32T32R mMIMO base stations because it reduces both production costs and power consumption...

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has introduced the EPC2367, a next-generation 100V eGaN FET that delivers high performance and efficiency as well as lower system costs for power conversion applications...

Intelligent power and sensing technology firm onsemi of Scottsdale, AZ, USA has introduced the first generation of its 1200V silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET)-based SPM 31 intelligent power modules (IPMs). EliteSiC SPM 31 IPMs deliver the highest energy efficiency and power density in the smallest form factor compared with using Field Stop 7 IGBT technology, it is claimed, resulting in lower total system cost than any other leading solution on the market...

💼 Оголошується конкурс на заміщення посад наукових працівників kpi вт, 03/18/2025 - 11:00

Replaced for now. Phasing out this order equipment . submitted by /u/Switchlord518 [link] [comments]

Introduction

The demand for smaller, lighter, and more efficient AC/DC USB power delivery (PD) chargers is always a challenge for power-supply design engineers. Below 100 W, the quasi-resonant flyback is still the dominating topology, and gallium nitride (GaN) technology can push the power density and efficiency further.

However, providing bias power for the primary controller requires an auxiliary winding on the transformer as well as rectifying and filtering circuitry. To make things worse, the USB PD charger output voltage has a wide range. For example, the USB PD standard power range covers output voltages from 5 V to 20 V, and the latest USB PD extended power range allows the output voltage to go as high as 48 V. Since the auxiliary voltage is proportional to the output voltage, the bias voltage range on the primary controller will increase, requiring extra circuitry and degrading efficiency. In this power tip, I’ll introduce a self-biased flyback converter solution to address these design challenges.

Dealing with wide bias voltages

Figure 1, Figure 2, Figure 3, and Figure 4 show four different ways to deal with the wide bias voltage range in USB PD charger applications. Conventional methods include using a linear regulator, a tapped auxiliary winding, or even adding an extra DC/DC switching converter to regulate the bias voltage. All of these methods will increase component count, add cost, or increase power losses. Alternatively, self-biasing totally removes external components and increases efficiency.

Figure 1 Bias circuits for applications with wide output voltage ranges using a discrete linear regulator. Source: Texas Instruments

Figure 2 Bias circuits for applications with wide output voltage ranges using a tapped auxiliary winding. Source: Texas Instruments

Figure 3 Bias circuits for applications with wide output voltage ranges using boost converter. Source: Texas Instruments

Figure 4 Bias circuits for applications with wide output voltage ranges using a self-biased VCC. Source: Texas Instruments

VCC self-biasing

The flyback controller can always get bias power directly from the rectified AC input voltage, but this results in excessive power losses. The key to self-biasing is to harvest energy from the power stage, which can come from two sources. One is the switch-node capacitor stored energy; the other is energy stored in the primary-side winding of the transformer. As shown in Figure 5, an integrated self-biasing circuit can ideally do both, based on the input and output conditions.

Figure 5 The self-bias circuit harvests energy from the switch-node capacitance or magnetizing inductance. Source: Texas Instruments

Figure 6 shows the energy harvesting from the switch-node capacitor. This can save efficiency as it recycles the energy storage in switching node capacitor in every switching cycle. In cases such as AC low-line input when the reflected output voltage is identical to the input voltage, natural zero voltage switching will occur, and there is no energy in the switch-node capacitor, inductor energy harvesting will take effect, where a small portion of the primary switching current is directed to the VCC cap through an internal path.

Figure 6 VCC self-bias operation: (a) capacitor energy harvesting on the switching node and (b) inductor energy harvesting through the primary current. Source: Texas Instruments

Achieving auxless sensing

Many flyback controllers use the auxiliary winding to sense the input and output voltages and detect conditions such as output overvoltage or input undervoltage. With self-biased flyback converters, it is possible to use the switching-node voltage for input and output voltage sensing. As shown in Figure 7, the sensed voltage is the sum of the input and reflected output voltage. Since the average voltage across the primary winding is zero, the average of the switch-node voltage is equal to the input voltage.

For output voltage sensing, it can sample the reflected output voltage, and the controller needs to be informed of the exact turns ratio of the transformer with the use of a resistor-programmable pin [the TR pin in the Texas Instruments (TI) UCG28826].

Figure 7 Auxless voltage sensing where the sensed voltage is the sum of the input and reflected output voltage. Source: Texas Instruments

Once properly configured, self-biased devices such as the UCG28826 can accurately provide various protections like overpower and overvoltage protection. Figure 8 shows the UCG28826 in a USB PD application.

Figure 8 A self-biased USB PD design using the UCG28826 that can accurately provide various protections like overpower and overvoltage protection. Source: Texas Instruments

Figure 9 shows the overvoltage protection waveforms after intentionally disconnecting the feedback pin which is a single fault condition. The controller senses the output voltage and triggers overvoltage protection accordingly when the output ramps up to around 24.4 V for a nominal 20 V output.

Figure 9 Auxless sensing example for overvoltage protection. Channel 1 (CH1) is Vout and channel 2 (CH2) is Vsw. Source: Texas Instruments

Prototype and test result

Figure 10 shows the TI universal AC-input 65W dual USB type-C port USB PD charger reference design with an integrated GaN power switch. Due to the simplified self-bias feature and integrated GaN switch in the UCG28826, the reference design achieves a power density of 2.3 W/cm3 and 93.2% efficiency for the AC/DC stage. The auxless design also simplifies transformer manufacturing and reduces costs. Table 1 summarizes the design parameters of 65 W design for reference. 

Figure 10 A universal AC-input 65-W reference design board. Source: Texas Instruments

Parameter	Value
AC input voltage	90-264 VAC
Output voltage and current	5-20 V, 3.25 A maximum
Transformer	ATQ23-14
Turns ratio	7-to-1
Transformer inductance	200 µH
Switching frequency (full load)	90-140 kHz
Efficiency	93.2% at 90 VAC (AC/DC stage only)
Power density	2.3 W/cm3

Table 1 Universal AC-input 65W reference design parameters.

Simplified USB PD charger

A high-level integration with a controller and GaN switch can simplify USB PD charger design, but the bias circuitry for the controller and associated auxiliary winding on the transformer are still there, degrading efficiency and affecting size and cost. An integrated self-biasing circuit can eliminate that portion of the circuit and increase the power density for power supplies with wide-range outputs. Additionally, it is still possible to achieve proper input and output voltage sensing in the absence of an auxiliary winding on the transformer.

Max Wang is a systems engineer and Member, Group Technical Staff at Texas Instruments. He has over 18 years of experience in the power semiconductor and power-supply industries in computing, industrial, and personal electronics markets; specializing in isolated AC/DC and DC/DC applications. His design and research interests include high-efficiency and high-power-density power conversion, soft-switching converters, and GaN implementation in AC/DC converters. Max obtained a master’s degree in electrical engineering from Zhejiang University in 2006. He has worked at Delta, Power Integrations, Infineon and Texas Instruments.

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