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Rohde & Schwarz approved by USB-IF for USB 3.2 Gen 1 & Gen 2 transmitter and receiver compliance testing

ELE Times - Wed, 06/05/2024 - 14:37

The USB Implementers Forum (USB-IF) has approved the USB 3.2 Gen 1 & Gen 2 transmitter and receiver compliance test solution from Rohde & Schwarz, confirming that it meets the stringent requirements set by the standardization body. Manufacturers of USB devices preparing for official USB-IF certification can have full confidence in the accuracy and reliability of the test results produced by the test solution.

Rohde & Schwarz has received approval from the USB Implementers Forum for its USB 3.2 Gen 1 & Gen 2 transmitter (Tx) and receiver (Rx) compliance test solution. This approval underlines the company’s commitment to providing high-quality test and measurement solutions for the USB ecosystem.

The R&S RTP-K101 for Tx and R&S RTP-K102 for Rx enables manufacturers to test their USB devices for compliance with the USB 3.2 standard, using the R&S RTP oscilloscope from Rohde & Schwarz. The software option includes a range of test cases and scenarios that cover all aspects of electrical compliance testing of USB 3.2 Gen 1 & Gen 2 transmitters and receivers. They are implemented in the R&S ScopeSuite software, which controls all needed hardware to carry out these tests, including third-party bit error rate testers (BERT) required for receiver testing. R&S ScopeSuite features illustrated step-by-step instructions which guide users in terms of optimum setup and connection to test fixtures to obtain reliable test results in line with USB-IF test specifications.

The USB-IF is the industry body responsible for the promotion and development of the Universal Serial Bus (USB) standard. The organization oversees the development of USB technology standards and ensures that all USB-IF certified products meet the highest standards of interoperability and quality.

The R&S RTP-K101 for Tx and R&S RTP-K102 for Rx compliance test options for USB 3.2 Gen 1 & Gen 2 are available from Rohde & Schwarz and are part of the company’s extensive solutions portfolio for USB design and compliance testing. Rohde & Schwarz already has approval from the USB-IF for USB 2.0 transmitter and receiver testing as well as for USB cable and connector testing.

For more information on USB testing solutions from Rohde & Schwarz, go to: https://www.rohde-schwarz.com/_251317.html

The post Rohde & Schwarz approved by USB-IF for USB 3.2 Gen 1 & Gen 2 transmitter and receiver compliance testing appeared first on ELE Times.

E-Fill Electric Joins Forces with DevvStream to Drive Carbon Credit Generation from India’s EV Charging Network

ELE Times - Wed, 06/05/2024 - 14:12

Strategic Partnership Aims to Generate Carbon Credits from EV Charging Network, Revolutionizing India’s Electric Mobility Landscape.

As the world celebrates World Environment Day, E-Fill Electric, a pioneering provider of technology-driven electric vehicle (“EV”) solutions, and DevvStream Holdings Inc. (NEO: DESG) (OTCQB: DSTRF) (FSE: CQ0), a leading carbon credit project co-development and generation firm specializing in technology-based solutions,  announced a definitive agreement (the “E-Fill Agreement”) to leverage E-Fill Electric’s network of EV charging stations in India for carbon credit generation. This agreement is anticipated to establish a new revenue stream for E-Fill Electric, enabling the expansion of the company’s R&D and manufacturing capabilities.

E-Fill Electric will serve as a launch partner forDevvStream’s Electric Vehicle Charging Carbon Offset Program (“EVCCOP”) in India, which aims to accelerate electric mobility by generating revenue for EV charging network owners and operators. The program achieves this by producing and selling voluntary carbon credits, which are generated when EV owners charge their vehicles. The program is tailor-made for Charge Point Operators and Mobility Service Providers that own/operate Level 1, Level 2, or DC Fast Charging stations, public or private, for passenger vehicles or heavy-duty vehicles like e-buses and e-trucks. The average Level 2 EV charger generates approximately 40 credits per year with medium use, while a Level 3 EV charger generates approximately 500 credits annually, according to Company estimates.

Mayank Jain, CEO of E-Fill Electric, emphasized the strategic significance of this collaboration, stating, “DevvStream’s unparalleled expertise in carbon markets aligns seamlessly with our vision to foster the widespread adoption of EVs in India. Through the EVCCOP, we are poised to create a lucrative revenue stream while significantly reducing greenhouse gas emissions.”

“With India prioritizing the adoption and growth of domestic manufacturing of EVs, there is a significant need for expanded EV charging infrastructure to support this shift, and carbon markets present a massive untapped source of funding for technology providers like E-Fill Electric,” said Sunny Trinh, CEO of DevvStream. “DevvStream’s EVCCOP will allow E-FillElectric to create a lucrative new revenue stream from its existing EV charging network through the generation of high value carbon credits which can finance further network expansion. As progress continues toward DevvStream’s business combination with Focus Impact Acquisition Corp., we look forward to sharing additional updates related to the on boarding of additional partners into this and other DevvStream programs.”

DevvStream’s EVCCOP incentivizes EV charging through the production and sale of voluntary carbon credits. This innovative program caters to ChargePoint Operators and Mobility Service Providers, offering a compelling financial incentive to bolster EV infrastructure. With India witnessing a surge in EV adoption, the EVCCOP is poised to catalyze the nation’s transition to electric mobility.

The EVCCOP comes at a critical juncture for India, where EV sales are on the rise, fueled by government incentives and a growing emphasis on environmental sustainability. As India charts a course towards becoming a manufacturing hub for EVs, robust charging infrastructure is imperative to support this transition.

“E-Fill Electric is dedicated to empowering our partners in expanding EV charging infrastructure across India,” added Jain. “The revenues generated through the DevvStream program will provide a vital financial boost, enabling us to realize our vision of a cleaner, greener India.”

With over 12,000 public charging installations already in place, India’s EV charging landscape is primed for exponential growth. As the world commemorates World Environment Day, the collaboration between E-Fill Electric and DevvStream serves as a beacon of hope, showcasing the power of innovation to drive positive change for our planet and future generations.

The post E-Fill Electric Joins Forces with DevvStream to Drive Carbon Credit Generation from India’s EV Charging Network appeared first on ELE Times.

u-blox launches comprehensive Bluetooth Angle-of-Arrival solution to enable reliable indoor asset tracking

ELE Times - Wed, 06/05/2024 - 13:43

u-locate offers every necessary hardware, software and middleware component for indoor positioning, including support for interoperability with the omlox™ standard.

u-blox, a global provider of leading positioning and wireless communication technologies and services, has announced u-locate, a complete indoor positioning solution, offering the optimal combination of accuracy, cost and power consumption. Based on Bluetooth LE AoA (Angle-of-Arrival), u-locate delivers positioning accuracy levels down to 10 centimeters while ensuring extended tag battery lifetimes at an affordable price point.

The flexible and modular u-locate solution targets RTLS (real-time location system) solution providers and systems integrators, with end-user indoor tracking applications in warehousing, manufacturing, healthcare and many more. The easy-to-configure mobile application includes an extensive management support tool and anchors with self-aware orientation, removing the pain of complex solution installations and ensuring reduced times to market.

u-locate’s advanced AoA positioning algorithms deliver market-leading accuracy while reducing the cost of tracking assets, enabling a wider range of use cases. The combination of Bluetooth 5.1 technology with the optimized antenna configuration of u-locate delivers exceptional levels of positioning accuracy, without compromising power consumption. The u-locate solution scales easily as the end-user installation grows, and futureproofing is underpinned with OTA (over-the-air) software updates ensuring continuous access to new features and updates.

The flexible solution can be tailored according to the needs of the application, and consists of a positioning middleware (u-locateHub), a positioning engine (u-locateEngine), anchor points (u-locateAnchor) and tags (u-locateTag). It can be complemented with GNSS (Global Navigation Satellite System) products from u-blox, to guarantee seamless indoor and outdoor localization.

u-locateHub complies with the omlox global interoperability standard and its well-documented API platform contains various APIs, supporting integration with multiple vendor solutions. By joining omlox, u-blox recognizes the importance of contributing to a growing ecosystem, and promoting global interoperability of positioning solutions.

“We are delighted that u-blox is entering the omlox ecosystem, by adopting the standard into u-locate, its new RTLS solution for indoor positioning systems,” says Dr. Matthias Joest, Committee leader for omlox.  “omlox is the world’s first locating standard. It specifies flexible locating solutions that allow customers to benefit from lower integration costs, while ensuring future-proof setups. Having u-blox – recognized leader in locating technologies – as member and supporter of omlox, is a huge benefit for our fast-growing ecosystem.”

With u-locate, u-blox is leveraging its deep expertise in wireless connectivity and positioning technologies to address the growing need for high-performance positioning systems which reduce operational costs and maximize sustainability by optimizing inventory management along with material and people flows.

u-blox provides semiconductor chips, modules, and IoT services that reliably locate and connect everything. Our cutting-edge solutions drive innovation for the car of the future and the Internet of Things. Headquartered in Thalwil (Zurich), Switzerland, we have a global presence of 1,400 experts who enable our customers to build solutions for a precise, smart, and sustainable future.  

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Application For Maker Faire Rome 2024: Deadline June 20th

Open Electronics - Wed, 06/05/2024 - 13:25

Learn More About the Ideas, Makers + Projects at Maker Faire Rome 2024 Developing a multitude of technologies for the sustainability of the planet and for environmental care is imperative today. The depletion of natural resources and the need to conserve what remains have brought technological innovation into our lives, especially at events and expositions […]

The post Application For Maker Faire Rome 2024: Deadline June 20th appeared first on Open Electronics. The author is Boris Landoni

First Solar becomes solar industry’s first EPEAT Climate+ Champion

Semiconductor today - Wed, 06/05/2024 - 11:24
Cadmium telluride (CdTe) thin-film photovoltaic (PV) module maker First Solar Inc of Tempe, AZ, USA says that its Series 6 Plus and Series 7 TR1 products are the world’s first PV solar modules to achieve the EPEAT Climate+ designation, establishing a new benchmark for the solar technology and manufacturing industry...

NUBURU’s distributor Japan Laser Company installs BL250 BlueScan in Osaka office

Semiconductor today - Wed, 06/05/2024 - 11:16
NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — says that distributor Japan Laser Company (JLC) has installed a BL250 BlueScan system in the JLC Osaka office, to be used to demonstrate micro-welding and wire stripping to strategic electronic and medical device customers in the Japanese market...

Geely and ST set up joint lab and sign multi-year SiC device supply deal

Semiconductor today - Wed, 06/05/2024 - 11:07
STMicroelectronics of Geneva, Switzerland and China-based automobile and electric vehicle (EV) maker Geely Auto Group have signed a multi-year silicon carbide (SiC) supply agreement to accelerate their existing cooperation on SiC devices...

Elevating embedded systems with I3C

EDN Network - Wed, 06/05/2024 - 08:51

In modern electronics, embedded systems have become increasingly complex, incorporating a variety of sensors and components in many applications including IoT, computing, wearables and security-sensitive applications. To meet the growing requirements of these markets, the MIPI Alliance has developed the improved inter-integrated circuit® (I3C) interface. I3C is an advanced serial communication interface that offers a major upgrade in how electronic components can communicate with each other by providing faster communication rates, lower power consumption, and improved design flexibility. As a key component of an embedded system, microcontrollers (MCUs) are used to control application functions like sensor signal acquisition and closed-loop control. We will delve into several applications that can utilize an MCU with an I3C communication interface, offering a robust upgrade path and compatibility for I2C and SPI implementations. 

I3C and IoT applications

IoT touches nearly every facet of our daily routines, spanning from household gadgets to sophisticated building automation and wearable devices. These interconnected devices gather and exchange data, fundamentally shaping our digital ecosystem. Within IoT devices, different types of sensors play a pivotal role, measuring, monitoring, and relaying crucial physical attributes like temperature, humidity, pressure, and distance, among others.

The I3C protocol offers several benefits for networked sensor nodes. It enables high-speed communication, with speeds of up to 12.5 MHz in single data rate (SDR) mode. It also supports in-band interrupts and dynamic addressing. In dynamic addressing, a central controller assigns unique addresses to each connected device, preventing address conflicts. Compared to its predecessor I2C, I3C boasts faster speeds, a simpler 2-wire interface, a more efficient protocol structure, and operates at lower voltages to reduce power consumption. These improvements make I3C well-suited for efficiently managing multiple sensor nodes within a connected network.

Incorporating a low cost MCU with built-in I3C peripherals into IoT sensor nodes as an analog “aggregator” can enhance functionality and efficiency of the entire sensor network. In this setup, the MCU’s on-chip analog-to-digital converter (ADC) is utilized to convert readings from multiple analog sensors into digital values. These digital values can then be stored in the MCU’s internal memory for further analysis or organized for more efficient transmission. The aggregated sensor data is transmitted to the main controller via the I3C bus at intervals optimized for system efficiency.

The distinct advantage of I3C in sensor-based systems becomes apparent when considering its capacity to minimize component complexity, cost, and power consumption by necessitating fewer pins and wires compared to alternative communication interfaces. For system designers navigating the demanding IoT market landscape, a compact MCU with I3C communication interface emerges as an essential solution, facilitating the creation of successful IoT devices that align with market requirements.

Multiple protocols and multiple voltages in embedded devices

As technology requirements grow, embedded developers face increasing challenges with backward compatibility. This compatibility is crucial because it allows for embedded systems to be gradually updated, rather than completely redesigned. To help ease the transition to I3C, the new communication protocol addresses the limitations of I2C and SMBus, while using the same two pins as I2C for clock and data to maintain compatibility.

While I3C aims to be backward-compatible with I2C/SMBus protocols, the presence of an I2C/SMBus device on an I3C bus can affect bus performance, even with controller optimization for I3C devices. To resolve this, an MCU with an I3C module can serve as a bridge device, isolating I2C/SMBus target devices from the “pure” I3C bus. This maintains the integrity of the I3C bus, allowing the main I3C controller to communicate with I2C /SPI devices via the bridge MCU. Additionally, the MCU can consolidate interrupts from I2C /SMBus devices and transmit them to the main I3C controller using in-band interrupts, without additional pins or signals.

Embedded systems incorporate various components such as MCUs, sensors, and other circuits. Oftentimes, these components need to be connected to one another, yet they operate in different voltage domains. For instance, analog sensors typically operate at 5 V, while communication protocols like I2C and SMBus require 3.3 V. The I3C bus can even operate at 1 V to match the requirements of modern high-speed processors.

MCUs with a multi-voltage I/O (MVIO) feature resolve voltage incompatibility and eliminate the need for level shifters. This feature enables I3C and I2C /SMBus buses to operate at different voltages simultaneously. For instance, an MCU can run the I3C bus at 1 V while keeping the I2C /SMBus bus at a higher 3.3 V for compatibility with legacy devices.

As shown in Figure 1, Microchip’s PIC18-Q20 MCUs, with MVIO support, offer multiple communication protocols like I3C, SPI, I2C, and UART, and up to three independent operating voltage domains. This flexibility proves highly beneficial in complex networked environments where devices use different protocols and voltages, allowing embedded developers to maintain existing protocols while futureproofing their designs.

Figure 1 The PIC18-Q20 MCUs, with MVIO support, offer multiple communication protocols like I3C, SPI, I2C, and UART, and up to three independent operating voltage domains. This offers flexibility in networked environments where embedded devices may use different protocols and voltages. Source: Microchip

Modern computing infrastructure

People can easily underestimate how much we rely on data centers in our daily digital lives. From conducting business and financial transactions to browsing the internet, storing data, engaging in social networking, attending virtual meetings, and enjoying digital entertainment—all these activities are facilitated by data centers. These centers ensure that our data is safe, our internet is fast, and our digital services are always available.

At the core of the data center lies the modern blade server: a highly advanced computer designed to maximize space efficiency and optimize network performance on a large scale. Due to the crucial nature of their function, certain system tasks within each server chassis are delegated to a sideband controller. While the main processing unit focuses on managing the primary data flow, the sideband controller steps in to enhance network performance. It establishes a secondary communication channel to oversee individual server blades and handles important tasks such as monitoring system health, detecting faults, discovering and configuring devices, updating firmware, and conducting diagnostics without disrupting the main processor. This ensures smooth and efficient operation. Sideband management serves as a critical tool that can greatly enhance the reliability, availability and efficiency of data centers.

Solid state drives (SSDs) are also commonly used in data centers to store and quickly access data. The newest SSD form factor, SNIA® Enterprise and Datacenter Standard Form Factor (EDSFF), has adopted the I3C protocol for sideband communication as a natural upgrade from the existing SMBus protocol. I3C addresses the demand for faster performance, higher data transfer rates, and improved power efficiency. The high-speed communication of I3C enables faster bus management and configuration modifications for enhanced system responsiveness.

Flexible MCUs such as the PIC18-Q20 family (Figure 2) are particularly well-suited for system management tasks in data center and enterprise environments. With up to two separate I3C interfaces, these MCUs can easily connect to an SSD controller for performing system management tasks, as well as to a baseboard management controller (BMC) via a sideband connection. Moreover, with built-in legacy communication protocols like I2C/SMBus, SPI, and UART, these devices represent an ideal solution for both current and next-generation SSD designs.

Figure 2: The PIC18-Q20 family will easily connect to an SSD and BMC controller via a sideband connection. Source: Microchip

I3C’s growing ubiquity

The integration of the I3C protocol has emerged as an enabling force in embedded systems. The enhanced communication capabilities, lower power consumption, and compatibility with existing protocols make I3C a cornerstone for next-generation IoT and computing applications. By optimizing sensor functionalities in IoT devices and data center communication, the versatility of I3C when integrated into MCUs can provide a robust foundation for the modern electronic systems. The adoption of I3C is quickly growing in ubiquity, enabling enhanced performance, reliability, and efficiency.

Stephanie Pinteric and Ulises Iniguez are senior product marketing engineers in Microchip’s 8-bit MCU business unit.

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Removing coating on circuit board

Reddit:Electronics - Wed, 06/05/2024 - 04:58
Removing coating on circuit board

Hello, is there any way to remove.the water proof coating from this?

submitted by /u/jlgar
[link] [comments]

Efabless Welcomes Weebit Nano’s ReRAM to Its Custom Chip Design Platform

AAC - Wed, 06/05/2024 - 02:00
Weebit Nano and Efabless are teaming up to make it easier for chip designers to prototype intelligent devices using Weebit's advanced memory technology.

AMD Builds New Ryzen Processors on Zen 5 Architecture for Advanced AI

AAC - Wed, 06/05/2024 - 00:00
AMD’s two new processor offerings bring improved AI performance to ultra-light laptops and desktops alike.

Intel Launches New Data Center Processor Family at Computex 2024

AAC - Tue, 06/04/2024 - 17:00
The new processors promise 3:1 rack consolidation, 4.2x rack-level performance gains, and 2.6x performance per watt gains.

CGD adds new ICeGaN power IC packages with enhanced thermal performance

Semiconductor today - Tue, 06/04/2024 - 16:46
Fabless firm Cambridge GaN Devices Ltd (CGD) — which was spun out of the University of Cambridge in 2016 to design, develop and commercialize power transistors and ICs that use GaN-on-silicon substrates — has announced two new packages for its ICeGaN family of GaN power ICs that offer enhanced thermal performance and simplify inspection. As variants of the well-proven DFN style, both packages are said to be extremely rugged and reliable...

Image sensor embeds AI to explore image data

EDN Network - Tue, 06/04/2024 - 16:40

A new generation of CMOS image sensors can exploit all the image data to perceive a scene, understand the situation, and intervene by embedding artificial intelligence (AI) in the sensor. CEA-Leti researchers have reported this design breakthrough when demand for smart image sensors is growing rapidly due to their high-performance imaging capabilities in smartphones, automobiles, and medical devices.

The design breakthrough is built on a combination of hybrid bonding and high-density through silicon via (HD TSV) technologies, which facilitates the integration of various components like image sensor arrays, signal processing circuits and memory elements in image sensors with precision and compactness.

The design breakthrough is based on a three-layer test vehicle that featured two embedded Cu-Cu hybrid-bonding interfaces, face-to-face (F2F) and face-to-back (F2B), and with one wafer containing high-density TSVs. Source: CEA-Leti

Communication between the different tiers in an image sensor design necessitates advanced interconnection technology. The new design presented by CEA-Leti employs hybrid bonding due to its very fine pitch in the micron and sub-micron range. It also uses HD TSV, which has a similar density that enables signal transmission through the middle tiers.

“The use of hybrid bonding and HD TSV technologies contribute to the reduction of wire length, a critical factor in enhancing the performance of 3D-stacked architectures,” said Renan Bouis, lead author of the paper titled “Backside Thinning Process Development for High-Density TSV in a 3-Layer Integration.” He added that stacking multiple dies to create 3D architectures, such as three-layer imagers, has led to a paradigm shift in sensor design.

The paper presents the key technological bricks that are mandatory for manufacturing 3D, multilayer smart imagers capable of addressing new applications that require embedded AI. “This sets the stage to work on demonstrating a fully functional three-layer, smart CMOS image sensor, with edge AI capable of addressing high-performance semantic segmentation and object-detection applications,” said Eric Ollier, project manager at CEA-Leti and director of IRT Nanoelec’s Smart Imager program.

The Grenoble, France-based research house CEA-Leti is a major partner of IRT Nanoelec, an R&D institute also based in Grenoble, France.

It’s worth mentioning that at ECTC 2023, CEA-Leti scientists reported a two-layer test vehicle combining a 10-μm high, 1-μm diameter HD TSV and highly controlled hybrid bonding technology, both assembled in F2B configuration. Now, they have shortened the HD TSV to 6-μm height, which led to the development of a two-layer test vehicle exhibiting low dispersion electrical performances and enabling simpler manufacturing.

It’s mainly due to an optimized thinning process that allowed the substrate thickness to be reduced with favorable uniformity. “This reduced height led to a 40% decrease in electrical resistance, in proportion with the length reduction,” said Stéphan Borel, lead author of the paper titled “Low Resistance and High Isolation HD TSV for 3-Layer CMOS Image Sensors”. “Simultaneous lowering of the aspect ratio increased the step coverage of the isolation liner, leading to a better voltage withstand.”

Scientists at CEA-Leti are confident that this smart image sensor technology will enable a variety of new applications.

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5N Plus renews and increases CdTe materials supply agreement with First Solar

Semiconductor today - Tue, 06/04/2024 - 16:26
Specialty semiconductor and performance materials producer 5N Plus Inc of Montreal, Québec, Canada has renewed its supply agreement with First Solar Inc of Tempe, AZ, USA...

Виступ кандидата в ректори КПІ Петра Киричка

Новини - Tue, 06/04/2024 - 16:15
Виступ кандидата в ректори КПІ Петра Киричка
medialab вт, 06/04/2024 - 16:15

КПІмедіа в період агітації кандидатів у ректори проводить записи їхніх виступів.

Петро Киричок — професор, доктор технічних наук, директор Видавничо-поліграфічного інституту. Був проректором КПІ з навчально-наукової роботи.

Component tolerance sensitivities of single op-amp filter sections

EDN Network - Tue, 06/04/2024 - 15:38

Editor’s note: This DI invites the reader to reference custom Excel sheets for:

Please refer to these as you review this DI.
—Aalyia Shaukat

Several manufacturers offer op amp-based filter design tools [1-3]. Some tools choose off-the-shelf capacitor values, but others select non-standard ones. The option to alter passive component (resistor and capacitor) values while maintaining a given response is often limited, if available at all. Certain tools seem to consider the effects of particular passive component combinations on unwanted variations in filter responses, but others do not. Some limit designs to a specific set of filter characteristics (Butterworth, Bessel, Chebyshev) when filter design tables of quality factor (Q) and resonance frequency f0 (Hz) for other response types are readily available (see section 8.4  in [4] and [5]).

Wow the engineering world with your unique design: Design Ideas Submission Guide

This article addresses second-order op amp-based low, band, and high pass filter sections. A reference for many of the design equations used in the article can be found here [6]. Excel spreadsheets for each filter type allow the user to specify three defining characteristics: passband gain, Q, and resonance frequency f0. It requests the tolerances in percent of the capacitors and the resistors to be used. Each filter has a minimum of four passives, and so there is an infinite number of combinations of values which will satisfy the three characteristics. Because the difference between successive standard capacitor values is at least 10% while that for 1% resistors is only 2%, and because quality capacitors are generally more expensive, the user is given the option of specifying the two capacitors’ values rather than those of the resistors. This leaves it to the spreadsheet to calculate the latter. If desired, near exact resistor values can be implemented in a physical filter cheaply by using two standard parts.

The main purpose of this article is to demonstrate graphically and numerically how different sets of passive component values and tolerances contribute to unwanted variations in filter responses. From these, the user can readily select capacitor values which minimize the combination of a filter’s response sensitivity and component size and cost.

Types of passives used in filters

Before getting into a detailed discussion about sensitivity, it’s worth discussing the types of passive components (see [4] pp. 8.112-8.113) that should be used in filters. For SMD and through-hole applications, 1% metal film resistors are a good, inexpensive choice as are NPO ceramics (stay away from the monolithic, high dielectric value ceramics). For surface mount applications only, there are thin film capacitors. For through-hole, polystyrene, polypropylene, and Teflon capacitors are available. As for active components, this article assumes ideal op amps (which we know are difficult to source). The reference (see [4] pp. 8.114-8.115) gives a discussion of what is required of this component, the biggest concern of which is the gain available at f0 Hz. By “rule of thumb” this should exceed 4·Q2 for the filter by a factor of 10 or more.

But rather than dealing with a rule of thumb, it is recommended to start by simulating the filter using nominal value passive components and an op amp with no high frequency roll-off and a resonance frequency gain of 1000·4·Q2 or more. Then, reduce the gain and introduce a high frequency roll off until a response change is seen. Finally, an op amp with matching or superior characteristics can then be selected and used in a simulation for design confirmation.

Quantizing filter response variations due to component tolerances

Generally, a variation in a passive’s value will result in some change in filter response characteristics. If that change is small enough, there will be some sensitivity S which is a constant of proportionality relating the filter parameter y variation to the passive x’s change. To keep S dimensionless, it will be useful to relate fractional changes in the passive’s value to those of the parameter. Mathematically,

Solving for in the limit as Δx goes to zero, we have:

The instances of x that are of concern are the resistor and capacitor values that make up the filter. The instances of y are the defining filter parameters: passband gain, Q and ω0 = 2π·f0. The following is an example of how the various S values are computed for the low pass filter in Figure 1.

Figure 1 A sample lowpass filter used to compute various S values.

The frequency domain (s-plane) transfer function of the above filter is:

For such a section, this is equal to:

By equating like terms, the various parameters can be computed. But what is really needed is some total sensitivity of each y parameter to a complete filter design, one which involves all its passive components. One way to do this is to use the following equation:

This is the square root of the sum of the squares of the sensitivities of a specific y to each of the i component’s xi multiplied by the tolerance of xi in percent, pct_tolxi. This expression is useful for comparisons between the overall sensitivities of implementations with different sets of component values.

The general filter design approach

Refer to Figure 2 which shows the spreadsheet LPF.xlsx used for the design and analysis of low pass filters. Many of its characteristics are identical to the ones used in the high and bandpass spreadsheets.

Figure 2 A screenshot of the low pass filter spreadsheet where the yellow values are entered by the user, the orange cells are filter component values automatically calculated by the spreadsheet, the bottom parameters are intermediate calculation required by the spreadsheet, and columns F and G contain the sensitivity values. There is also a graph which ignores _ρ and displays a wide range of possible component values from which the user may choose.

The yellow values in column C rows 5 through 14 are the only values entered by the user. These include the filter characterization parameters Q, Gain, and f0; as well as the ratio _ρ = C1/C2 (take note of the comment associated with cell C10); values for C1 and RG (reference designators for the components in the schematic seen in columns B through D and rows 26 through 37); and the percent tolerances of the resistors (r_tol) and the capacitors (c_tol) intended to be used in the filter.

The orange cells, columns B and C, rows 20 to 24, are filter component values calculated by the spreadsheet from these user entries. Columns C and D, rows 43 to 48 contain some of the intermediate calculations required by the spreadsheet.

Columns F and G contain the , , and sensitivities associated with each component x. Only those which have non-zero effects on the total sensitivity parameters SQ, SGain, and Sω0 (also shown in these columns) are listed. Notice that the equation for every parameter calculated by the spreadsheet appears to the right of the parameter value. There is also a graph which ignores _ρ and displays a wide range of possible component values from which the user may choose.

Low Pass filter design

Now let’s take a look at the curves on the graph for parameters _ρ = _C1 /_C2 and sensitivities SQ and Sω0 which are parameterized by _r = _R2/(1/_R1a + 1/_R1b) for values from .01 to 100. These depend only on Q, Gain, and _r. all these are dimensionless.

The _ρ curve shows that for this particular filter, there are no solutions for values less than 4·Q2 = 4. (If you had entered such a value for _ρ, Excel would return the #NUM! error for many spreadsheet calculations.) The curve for Sensitivity of Gain, SGain, can’t be shown on a logarithmic scale—cell G25 shows it to be equal to zero. Why? The pass band (low frequency) Gain is 1, RF is zero, R1b is infinite (the spreadsheet shows it to be ridiculously large), and no passive components have any effect on Gain. (In a physical filter, there is still a sensitivity to the unity gain-configured op amp’s gain, which is actually less than unity due to its finite gain bandwidth product. Hence one of the reasons to simulate filter designs with the intended op amp.) Interestingly, the component sensitivities to Sω0 are independent of Q, _r, _ρ, and Gain for gains greater than or equal to unity, being dependent on tolerances r_tol and c_tol only. If Gain is unity, the only overall sensitivity that can be influenced is SQ, which is minimized in this case for _ρ = 4·Q2 = 4.

When 12.0E-9 is entered for _C1, the expression = 12/2.7 ≈ 4.44 for _ρ is close to 4 to allow the use of standard value capacitors. It will be seen that for low and high pass filters, the least sensitive choice is for a Gain of unity. Figure 3 shows what happens when the Gain requirement is increased by even a small amount to 1.5.

Figure 3 The low pass filter design of Figure 2 with the Gain parameter increased from 1 to 1.5.

Sω0 is unchanged as expected, but the best SQ has now more than doubled and SGain has made a showing, although it’s not much of a concern. The only good news is that _ρ = _C1/_C2 could be reduced to 2.2/1 and _C1 to 2.2E-9 (not shown in Figure 3) with no significant effect on SQ. A significant increase in Gain is definitely not recommended, as it causes a large jump in SQ, as can be seen in Figure 4.

Figure 4 Low Pass Filter screenshot with Gain jumping from from a value of 1 to 5, resulting in a large jump in SQ.

Such large gain values increase the best obtainable value of SQ by a factor of 6 in comparison to the Figure 3 design. The problem is compounded for higher values of Q and for component tolerances greater than 1%.

Low pass filter design summary

It’s no surprise that the best results will be obtained with the lowest tolerance passive components. There is little that can be done to influence the value of Sω0 which is constant for Gain values greater than or equal to unity, and which falls by small amounts only for smaller gains. Fortunately, its value is relatively small. For given values of Q and f0, the least sensitive low pass filter designs overall have a Gain of unity. For such a case, SGain is zero and SQ is at its minimum. Gains of unity or less leave SQ  unchanged, but can cause SGain to rise a small amount above the very stable Sω0. The real problem comes with Gain values greater than unity: Even slightly higher values cause SQ to increase significantly and overwhelm the contributions of SGain and Sω0, but they will reduce the minimum usable value of _ρ, which may be an acceptable tradeoff against increased SQ for some high Q cases. Generally, though, it’s wise to avoid Gain values much greater than unity, you can verify that the commonly recommended case of Gain = 2 to allow _ρ = 1 for equal capacitor values can produce a horrendous increase in SQ.

High pass filter design

Other than a few differences related to interchanging the treatments of R1 and R2 with those of C1 and C2, high pass filter design and the high pass filter design spreadsheet shown in Figure 5 are much like those for the low pass filter. The biggest differences are first, that parameterization of the graph’s curves is by _ρ = _C1/_C2 (assuming values from .01 to 100) rather than by _r = _R2/_R1. For the low pass, any value of _r produces a realizable result, while this is true for _ρ for the high pass. Second, there is no C1b/C1a voltage divider corresponding to the low pass filter’s R1b/R1a—there is only _C1. The introduction of a capacitive voltage divider would require a prior stage to drive a capacitive load, courting oscillation. And so, although the high pass filter cannot support Gain values less than unity, the high and low pass designs show significant similarities. A comparison between Figure 4 and Figure 5 graphs, which employ the same Q, Gain, and f0, show virtually identical results (with _ρ and _r switched).

Figure 5 High Pass Filter screenshot with the same Q, Gain, and f0 requirements as those of Figure 4.

High Pass filter design summary

The comments found in the “Low pass filter design summary” section apply here too, except that there is no option for Gain values less than unity.

Bandpass filter design

Although the least sensitive topology for component tolerances in high and low pass filters is the Sallen-Key, for the bandpass it’s the Delyannis-Friend (aka the multiple feedback configuration). A screenshot of the bandpass filter spreadsheet can be seen in Figure 6.

User data entry with the bandpass is much like that for the low and high pass cases, except that there is no _RG (and therefore no _RF). Once again, please be aware of the comments in the notes in columns D and E. If the background of cell C6 (filter Gain at resonance) is red, there are no realizable filters, calculations in columns C through G should be ignored, and the graph will be blank.

In some cases, the cell C6 background color will be the normal white, but filters will be realizable for certain smaller values of _ρ only, and the graph’s curves will be displayed accordingly. The curves might be absent, or partially or fully present, regardless of the value of _ρ in cell C10. But if C10’s background color is red, the _ρ-dependent calculations in columns C through G should be ignored. Figure 6 is an example where the filter Gain at resonance is close enough to the maximum possible value of 2·Q2 to render high values of _ρ (greater than 30) unrealizable.

Figure 6 A bandpass filter screenshot where user entry data (yellow) is similar to the low and high pass filter excel sheets.

Bandpass filter design summary

It’s surprising that the passive sensitivity curves can be shown to be almost completely independent of the user-specified filter Gain at resonance. This is because for a given Q and f0, the filter Gain is set by the ratio of R1a to R1b. The parallel combination of these components is independent of filter Gain, and the remainder of the filter sees no difference in other than signal level. (Designers should be aware that the op amp can easily clip at or near resonance with too high a gain.) Surprisingly, sensitivities are independent of Q. However, the higher the Q, the higher the op amp open loop gain must be to provide enough margin to accurately implement the required op amp closed loop gain. Simulation of the filter design using the op amp intended for it, or one with similar gain characteristics, is strongly recommended.

Looking at the sensitivity curves only, it could be concluded that the best choice would be for a _ρ of 1 or less. _ρ = 1 has the advantage of the smallest ratio _r = R2 / (R1a || R1b). But consider the Gain of op amp at resonance: Less gain is required at higher values of _ρ, putting less of a burden on op amp open loop gain requirements to provide enough margin to meet the closed loop gain requirement.

Higher values of _ρ increase the overriding SGain by only a small amount. Clearly, there is a rather large disadvantage to values of _ρ less than unity when the demand on op amp closed loop gain is considered. Perhaps the best choice is _ρ = 1. The matched capacitors can be any standard value, SGain is near its smallest value, _r is at its smallest value, and there is only a modest increase in the op amp closed loop (and therefore open loop) gain requirement.

Flexible passive component values

This article and its attendant spreadsheets provide an understanding of the sensitivities of pass band gains, Q’s, and resonance frequencies to the nearly infinite combinations of passive components that can make up low, band, and high pass, single op amp filters. The ability to implement designs using capacitors of readily available values is provided. It is hoped that filter designers will find these to be a useful set of tools whose features are not found elsewhere.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content


  1. Texas Instruments. WEBENCH® Filter Design Tool. https://webench.ti.com/filter-design-tool/design/8
  2. Analog Devices. Analog Filter Wizard. https://tools.analog.com/en/filterwizard/
  3. FilterLab Active Filter Designer. https://www.microchip.com/en-us/development-tool/filterlabdesignsoftware
  4. Zumbahlen, Hank. “Chapter 8: Analog Filters.” Linear Circuit Design Handbook. Elsevier, 2008, https://www.analog.com/en/resources/technical-books/linear-circuit-design-handbook.html.
  5. Williams, Arthur Bernard. Analog Filter and Circuit Design Handbook. McGraw-Hill, 2014.
  6. Jurišić, D., Moschytz, G. S., & Mijat, N. (2010). Low-Sensitivity Active-RC Allpole Filters Using Optimized Biquads. Automatika, 51(1), 55–70. https://doi.org/10.1080/00051144.2010.11828355
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