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The future of advanced packaging is not one universal package. It’s a technology platform capable of placing the right interconnect, material, die, memory stack, optical engine, and thermal structure at the right system boundary.

For many years, the design sequence appeared straightforward:

Design the chip → select the package → connect it to the board

That sequence is becoming less accurate. AI accelerators, high-bandwidth memory (HBM), chiplets, optical I/O, advanced cooling, and high-current power delivery are now so tightly coupled that the package can no longer be selected after the system architecture is largely complete.

The package increasingly determines:

• How the system can be partitioned
• How many chiplets can be integrated
• Where silicon-class interconnect density is required
• Where broader and lower-cost routing is sufficient
• How HBM is placed and connected
• Where electrical path should transition to optic
• How power reaches the compute elements
• How heat leaves the package
• How assembly can be manufactured, tested, repaired, and qualified

The package is no longer merely supporting the system. It’s defining what system can be built.

From package choice to packaging platform

Traditional packaging discussions often compare individual technologies:

• Should the design use a silicon interposer?
• Would a local silicon bridge be sufficient?
• Should fan-out redistribution replace part of the substrate?
• Should the system use 2.5D or 3D integration?
• Should optics remain at the front panel, move near the package, or become co-packaged?

These remain important questions, but they are no longer independent choices. A modern AI system may require several of these technologies at the same time.

A broad interposer may connect compute chiplets and HBM. Here, localized bridges may provide silicon-class density only at selected die boundaries. And fan-out redistribution may extend routing across a larger area. Next, vertical stacking may integrate cache, memory, control, or specialized processing. Then there are optical engines that may sit near the package edge.

A thermal structure may also need to remove highly non-uniform heat from several dies with different power densities. Finally, the system may also require test access, known-good-die strategies, repair paths, redundancy, and manufacturing flows that span several suppliers. This is why advanced packaging is moving from isolated process choices toward integrated technology platforms.

A platform does not force every product into one structure. It provides a coordinated set of technologies from which the system architect can select the right realization method for each boundary.

Vertical integration’s two meanings

The phrase vertical integration is often interpreted physically. But that is the first meaning.

Physical vertical integration

Dies, memory stacks, interconnect layers, optical engines, power-delivery structures, and thermal components are placed beside or above one another. This includes technologies such as:

• 2.5D integration
• 3D die stacking
• Package-on-package structures
• Through-silicon or through-glass vias
• Vertically-integrated power delivery
• Stacked memory and logic

Physical stacking is important because it can shorten interconnects, increase bandwidth density, reduce footprint, and place functions closer together. But there is a second meaning that may be even more important.

Technology platform integration

Different packaging technologies become coordinated elements within one ecosystem. A platform may combine:

• Broad-area fan-out routing
• Localized silicon bridges
• Full silicon interposers
• Vertical stacking
• System-in-package integration
• Co-packaged optics
• Assembly and bonding processes
• Package-level test
• Thermal and mechanical structures
• Manufacturing and reliability flows

In this model, vertical integration does not mean that every component must be stacked. It means the complete realization capability is integrated across design, materials, process, assembly, test, and system requirements. That is the deeper transition.

In other words, the future is not one package replacing all others. It’s a platform selecting the right precision, material, and integration method at each boundary.

Different boundaries need different precision

One of the most important architectural questions is: How much of the package truly requires silicon-class interconnect density?

A full silicon interposer can provide extremely dense routing and short connections across a broad area. But that precision comes with cost, area, yield, manufacturing, and mechanical consequences. Not every connection requires the same pitch or routing density.

Some die-to-die boundaries may require very fine-pitch interconnect. Other regions may only need moderate-density redistribution. Still others may be adequately served by an organic substrate or board-level connection.

A platform approach allows the package to become hierarchical: Silicon-class density where necessary.

• Fan-out or redistribution where broader routing is needed
• Substrate-level routing where lower density is sufficient

This avoids using the most expensive and complex technology everywhere. The objective is not maximum integration at every location; the objective is appropriate integration at every boundary.

Fan-out more than a package format

Fan-out packaging is often discussed as a package category. But within a larger platform, fan-out can perform several architectural roles. It can:

• Provide broad redistribution beyond the original die footprint
• Support heterogeneous die integration
• Reduce dependence on a large silicon interposer
• Connect local high-density regions to broader package routing
• Create a transition between chiplet-scale and substrate-scale interconnect
• Support system-in-package or package-on-package structures

Fan-out chip-on-substrate approaches can combine redistribution-layer density with the mechanical and routing capabilities of a larger package substrate. A fan-out bridge architecture can place localized silicon-class interconnect only where adjacent dies require it.

This allows precision to be concentrated rather than distributed uniformly across the complete package. That is not simply a manufacturing variation; it’s an architectural choice about where density should reside.

Bridges and interposers are complementary

Silicon bridges and full interposers are sometimes presented as competing technologies. They are better understood as different tools.

A broad interposer can provide:

• Dense routing across a large region
• Extensive die-to-die connectivity
• Controlled electrical paths
• Close integration between compute and HBM
• Broad placement flexibility

A local bridge can provide:

• Very high density at selected chiplet boundaries
• Reduced silicon area
• More localized precision
• Potentially lower cost for systems that do not require a full interposer
• A path to combine high-density and conventional routing within one package

The correct decision depends on:

• Die placemen
• Required pitch
• Routing density
• Signal reach
• Power delivery
• Thermal expansion
• Warpage
• Assembly tolerance
• Yield
• Test
• Cost

A packaging platform should therefore not declare one technology universally superior. It should allow the architecture to place each technology where it creates the greatest system value.

HBM makes package a compute boundary

HBM has already transformed the package. The connection between the accelerator and HBM is no longer a peripheral interface; it’s part of the compute architecture.

HBM placement determines:

• Achievable bandwidth
• Energy per bit
• Interposer or bridge requirements
• Package area
• Routing density
• Power delivery
• Thermal interaction
• Mechanical balance
• Yield and assembly complexity

As the number of HBM stacks grows, the package becomes larger and more difficult to manufacture. So, the system must manage:

• Interposer scale
• Reticle boundaries
• Die placement accuracy
• Warpage
• Underfill
• Bump reliability
• Heat-spreader geometry
• Non-uniform thermal loading
• Package-level test

The package is therefore not merely connecting compute to memory. It’s determining the physical shape of the compute system.

CPO an element of the platform

Co-packaged optics (CPO) is often treated as a separate technology story. But CPO cannot scale independently from advanced packaging. Moving the optical engine closer to a switch ASIC or accelerator may reduce electrical reach, SerDes power, and front-panel density pressure.

It also introduces new package-level responsibilities:

• EIC-to-PIC connectivity
• Optical attach
• Fiber routing
• Laser placement
• Wavelength control
• Thermal drift
• Calibration
• Optical test
• Compound yield
• Repairability
• Serviceability

A future AI package may combine:

• Compute dies
• HBM
• A full or partial interposer
• Localized bridges
• Fan-out redistribution
• Electrical I/O chiplets
• Optical engines
• External laser interfaces
• Power delivery structures
• Integrated cooling

CPO is therefore not simply another component added beside the ASIC. It changes the electrical, thermal, mechanical, manufacturing, test, and serviceability boundaries of the complete package. However, the package must create the environment in which optical performance can ensure repeatable system performance.

Optics moves inward only when the package platform can absorb the consequences of moving it inward. This is why CPO belongs inside the larger packaging-platform discussion.

Thermal architecture chosen with the package

As more functions move into the package, thermal design can no longer be treated as an external cooling problem. Different dies produce different heat fluxes. HBM, compute chiplets, I/O dies, optical engines, voltage-regulation structures, and control electronics may all have different temperature limits.

The package architecture determines:

• Which devices share a heat spreader
• Where thermal-interface materials are placed
• How bond-line thickness is controlled
• Whether a lid, cold plate, vapor chamber, or direct-liquid structure is required
• How mechanical pressure is distributed
• How thermal expansion affects interconnect reliability
• Whether optical alignment drifts with temperature

A package platform must therefore support more than electrical connectivity. It must coordinate the thermal path with the die placement, interconnect architecture, assembly process, and reliability requirements.

The best electrical placement may not be the best thermal placement; the best thermal placement may complicate fiber routing or package test. This is why package architecture is a system trade-off, not an isolated layout decision.

Power delivery also a package decision

AI systems require large current with rapidly changing load demand. As package power rises, the distance between voltage regulation, decoupling, power planes, and compute dies becomes increasingly important.

So, the package may need:

• Improved vertical power delivery
• Backside or near-die power structures
• Integrated voltage regulation
• Lower-inductance current paths
• More distributed decoupling
• Coordinated signal and return-current design

Power delivery interacts with:

• Chiplet placement
• HBM placement
• Interposer routing
• Thermal density
• Mechanical structure
• Package height
• Available routing layers

Manufacturing and test platforms

A package can be electrically attractive and still be difficult to manufacture. A platform approach must connect architecture choices to process capability. Questions include:

• Can the required die-placement tolerance be achieved?
• Can the redistribution layers be fabricated at the required scale and yield?
• Can the bridge or interposer be assembled without unacceptable warpage?
• Can underfill penetrate the available stand-off?
• Can thermal stack be controlled within bond-line limits?
• Can optical interface survive assembly and thermal cycling?
• Can each die be tested before integration?
• Can the completed assembly be tested after integration?
• Can failed modules be repaired or replaced?
• Can failed modules be repaired or replaced?

The package architecture is not complete when the drawing is complete. It’s complete when the process can repeatedly produce the intended geometry and performance. Manufacturing does not merely build the package; it creates the physical structure through which the system must operate.

Next, as the number of integrated dies increases, test complexity grows rapidly. A platform must account for:

• Known-good-die requirements
• Pre-bond test
• Post-bond test
• Interposer and bridge continuity
• Memory test
• Optical loopback
• Thermal calibration
• Power-delivery validation
• Fault isolation
• Repair or redundancy strategies

The challenge is especially severe when dies from different suppliers are integrated into one product. A failure in one small component can affect the yield of the entire assembly. This creates a compound-yield problem.

The value of a platform is therefore not simply that it offers several package technologies. It should also provide coordinated design rules, assembly flows, test access, metrology, failure analysis, and reliability evidence across those technologies.

System architecture now begins with workload

The new design sequence should begin with the workload and move downward into physical realization. Here, the deterministic chain encompasses:

• Workload requirements
• System partitioning
• Compute and memory placement
• Electrical and optical boundaries
• Package architecture
• Power and thermal architecture
• Manufacturing and test strategy
• Verified system performance

This reverses the older assumption that the package is selected near the end. The package platform must be taken into consideration from the beginning because it defines which partitioning options are physically and economically possible. A system architect cannot decide where compute, memory, optics, and power should reside without understanding the package technologies available to connect and sustain them.

Platform is not product

There is one important caution. A large portfolio of packaging technologies does not automatically produce a successful AI system. The platform provides options, but the product must still select and coordinate them correctly.

Adding more technologies can also increase:

• Process interactions
• Supplier dependencies
• Yield risk
• Test complexity
• Thermal coupling
• Mechanical stress
• Qualification burden
• Cost

The winning package will not be the one that includes the greatest number of advanced technologies. It will be the one that uses each technology only where its benefit exceeds its integration burden.

A local bridge may be better than a full interposer in one system. A full interposer may be essential in another. Near-packaged optical (NPO) may provide the right optical boundary for one product and CPO may be justified for another.

Vertical stacking may reduce latency but worsen thermal density. Fan-out may reduce cost but impose different warpage and process constraints. Therefore, the architecture must be selected based on system evidence, not technology enthusiasm.

Advanced packaging is no longer a menu of isolated process choices. It’s becoming the architecture through which compute, memory, electrical interconnect, optics, power delivery, cooling, manufacturing, and test are assembled into one realizable system.

The future is not one universal package. It’s an integrated technology platform capable of placing:

• Silicon-class density where it’s necessary
• Broader redistribution where it’s sufficient
• Vertical stacking where proximity creates value
• Optics where electrical reach becomes limiting
• Cooling where heat is generated
• Test access where failure must be isolated

The package is no longer selected after the system is defined. It increasingly determines which system architecture can be realized, manufactured, qualified, and scaled. The winning platform will not be the one that stacks the most technologies. It will be the one that places each technology where its system benefit exceeds its realization burden.

The chip defines capability. The package platform defines the system.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

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The post AI silicon: Package becoming system architecture appeared first on EDN.

This proposed design eliminates traditional additional requirements for AGC, AC coupling, and post amplification circuitry.

This Design Idea presents a simple op-amp-based sine wave oscillator that directly generates a low-impedance bipolar output of approximately 20 Vpp at frequencies above 100 kHz. The circuit was developed to directly drive an AD633 in an on–off keying (OOK) digital transmission system.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Many sinewave oscillators reported in the literature provide a unipolar output and require additional circuitry for automatic gain control (AGC), AC coupling, and post amplification to achieve the desired amplitude. The proposed circuit eliminates these requirements by directly generating a high-amplitude bipolar sinewave.

The circuit (Figure 1) consists of an LC tank connected in a feedback loop with an op-amp configured as an inverting amplifier with a gain set by the R3/R2 ratio. At the resonance frequency, fosc = 1/(2π√(L·Cs)), where Cs = C1 || C2, the LC network introduces 180° phase shift, while the inverting amplifier provides an additional 180°, resulting in a total loop phase shift of 360°, thus satisfying the Barkhausen phase condition.

Figure 1 This simple LC oscillator uses an op-amp and the intrinsic losses of the resonant tank to generate a stable low-distortion 20 Vpp sine wave without AGC.

The topology can be viewed as a simplified Colpitts oscillator in which the op-amp both sustains oscillation and compensates for the losses of the resonant network. A key practical advantage is that the oscillation amplitude is set by the op-amp closed-loop gain, primarily through the feedback resistor R3, allowing straightforward amplitude control without additional circuitry.

The prototype was implemented using the LT1357, a high-speed op-amp featuring high slew rate and wide gain-bandwidth product. In general, a wideband op-amp with sufficient slew rate and gain-bandwidth product is required, particularly as the oscillation frequency increases.

Resistor R1 is not critical in value and primarily serves to isolate the op-amp output from the LC tank, preventing degradation of the phase margin due to the reactive load. At resonance, assuming an ideal inductor, R1 is effectively in series with R2 and forms a voltage divider. Its value should therefore be kept small relative to R2 to limit attenuation of the LC network, but not so small as to excessively load the op-amp, resulting in a practical design trade-off.

At startup, the loop gain is greater than unity, allowing oscillation to build up from noise. As the amplitude increases, current in the LC tank also increases, leading to higher losses due to winding resistance and ferrite core dissipation. These losses introduce additional attenuation in the resonant network, progressively reducing the loop gain until it reaches unity.

At equilibrium, the energy provided by the op-amp exactly compensates for the tank losses, and the oscillation amplitude stabilizes. The op-amp remains in its linear region, and the resulting waveform is very close to an ideal sine wave, as confirmed by oscilloscope capture (Figure 2).

Figure 2 The waveform generated by the circuit is very close to an ideal sine wave.

The oscillation frequency remains essentially constant as the amplitude varies, indicating that inductance variation due to core nonlinearity is negligible. The circuit was built and tested experimentally (Figure 3).

Figure 3 The circuit was breadboarded, versus simply simulated, to more definitively validate its functionality.

The measured frequency is approximately 120 kHz, compared to a nominal value of about 124 kHz, with the difference mainly attributable to component tolerances, particularly in the ceramic capacitors and the inductor .

The value of R3 depends on the characteristics and quality factor of the inductor. In the prototype, the inductor was hand-wound on a ferrite toroid to obtain approximately 100 µH. When reproducing the circuit, R3 may require empirical adjustment depending on the specific inductor used.

This oscillator provides a simple and effective solution for generating low-distortion sine waves at medium–high frequencies, offering easy amplitude control via op-amp gain while eliminating the need for dedicated amplitude control circuitry and directly delivering a low-impedance bipolar output.

—Luca Bruno has a Master’s Degree in Electronic Engineering from Politecnico of Milano. He taught electronics and telecommunications for many years at ITI Hensemberger and has published numerous Design Ideas in EDN on analog and electronic circuit design.

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The post Op-amp LC oscillator uses tank losses for amplitude stabilization appeared first on EDN.

As a long-time analog-component and circuit “practitioner,” I view the schematic diagram as the starting point for almost any discussion of a design. It shows the signa flow, the primary ICs, other necessary but often underappreciated passive and active devices, the connectors, power source and distribution tree, and much more.

I sat down with the late circuit genius and prolific EDN contributor Jim Williams many years ago. See “This 30-ppm scale proves that analog designs aren’t dead yet” for just one of the many circuits he devised and explained in his articles published at EDN. As I sat down with him, he literally sketched out and talked through a clever yet conscientious design in real time; it was a master class in circuit explanation and exposition.

But lately I’ve been wondering to what extent we still need these schematics. In the era before large-scale analog ICs, a schematic was not only a diagram of what connected to what, but also a debug and troubleshooting guide. You could follow the signal flow from stage to stage, and separate the stages if needed, to see if a stage’s output corresponded correctly to its input.

A classic six-transistor AM-radio schematic makes this very clear (Figure 1).

Figure 1 This classic six-transistor AM radio has no processor, and its schematic diagram shows a linear signal flow from left to right, with RF stage/local oscillator, IF amplifiers, audio-stage driver, and audio power amplifier. Source: All American Five Radio

Things have changed; that’s for sure. Many electronic circuits now consist of a central processor, often with integrated analog I/O, plus perhaps a specialized network or other processor IC, along with connections to I/O including switches, displays, indicators, and similar. In other words, what we really need is an interconnection wiring diagram rather than a stylized schematic.

Consider a representative analog measurement function for an optical module for heart rate and blood oxygen (SpO2) measurement. Early units used a handful of individual devices, starting with the LED and its driver, going across to the phototransistor and its preamp, and then the rest of the signal chain that captured, conditioned, and digitized the output to show the relevant reading.

Now, the needed functions are largely integrated into a single IC such as the Analog Devices MAXM86161A, which includes the LED drivers, photodetector amplifier, analog and analog/digital functions, optical cancellation circuity, and I2C interface (Figure 2). All that’s missing is the user display, LED and photodetector, a soft on/off switch, and battery, plus a few capacitors and pullup resistors.

Figure 2 The MAXM86161A IC provides electro-optics for heart rate and blood oxygen monitoring, incorporating electrical and optical-friendly features. Source: Analog Devices

So, a product schematic diagram consists primarily of connections to that IC (Figure 3).

Figure 3 A highly integrated, tightly focused IC such as the MAXM86161A does not need many I/O connections. Source: Analog Devices

For this modest medical device, a hybrid block diagram/partial schematic is actually more informative, as it shows smaller-scale ICs with an independent processor (Figure 4).

Figure 4 A blend of conventional schematic diagram and high-level block diagram provides insight into system functionality and overall circuit action. Source: Microchip Technology

In many cases, the wiring diagram rather than the formal schematic is often of more use. When my microwave oven died, I opened the front panel out of curiosity and found both of those diagrams tucked inside (an unexpected but pleasant surprise). The below schematic (top) doesn’t really show what the wiring diagram clearly does (bottom). The innards are really a “mystery” control module with lots of connectors for keypad, display, safety interlock switches (lots of those), thermal overload switches and, of course, the magnetron tube that makes it all possible.

 

Figure 5 You can be the judge of which is more useful: the schematic diagram (top) or the wiring diagram (bottom) of this consumer microwave oven. Source: GE Appliances

Making it right

A good schematic tells the story of a design and shows how the different functional blocks relate to each other. For a not-so-good example, consider the one of Figure 6, also a heart rate and SpO2 monitor. It may have all the facts, but it certainly doesn’t tell the story at all.

Figure 6 This schematic of a heart rate and SpO2 monitor may be correct, but it’s hard to say; even if it is, it’s not very useful. Source: ResearchGate

It seems unnecessary to restate the obvious, but the guidelines for a good analog-centric schematic are simple. I have seen schematics from students which miss these points:

• Have signal flow from left-to-right to the extent possible.
• Use meaningful net names such as GND, SPI_CLK, SENSOR_OUT; designation such as Net_25 mean little. Even the circuit’s creator won’t remember these a few months later.
• Group components by function, such as power, processor, sensors, and interfaces. My personal peeve is when all the bypass and bulk capacitors—and there can be dozens—are clustered in one corner of the schematic connected between the power rail and ground, without any indication of which IC a particular capacitor is supporting. That may be electrically correct, but it’s terrible in terms of the story, and useless for the inevitable debug and troubleshooting process.

But wait…there’s a counter to the story

On one side, the increasing use of large-scale analog-centric ICs with 40, 50, or more contacts is changing the function of the schematic diagram. Does this mean that conventional schematics are going the way of the six-transistor radio?

That was my fear, but then I realized I was only looking at the situation through one end of the telescope, so to speak. If today and the future are all about highly integrated, multifunction analog-centric ICs, why do vendors collectively release hundreds of single-function analog ICs every year (and that’s doesn’t include the countless power discrete devices, controllers, and management devices)?

Three examples show the reality. There’s the Analog Devices ADG2712 quad SPST switch (top), the Texas Instruments LVx886 zero-drift, low-noise op amp with multiplexer-friendly inputs (middle), or the STMicroelectronics TSC1801 current-sense amplifier (bottom) shown in Figure 7.

Figure 7 Despite the trend towards much highly integrated analog ICs, vendors still introduce many small, single-function ones such as this quad SPST switch, specialized low-drift op amp, and current-sense amplifier. Source: Analog Devices, Texas Instruments, and STMicroelectronics

Each one of these implements a basic function that is essential yet would be difficult, if not impossible, to implement with the needed performance in a larger multifunction IC. In most cases, doing so would require excessive compromise in one or more parameters such as leakage, bias current, on resistance, drift, and stability. It’s a long list. By offering single-function analog ICs, the compromises related to process, design, packaging, and cost are minimized or at least easier to manage.

Of course, once you have a circuit with these components, you’re going to need a real, story-telling, signal-flow schematic. So maybe I am too worried.

What are your thoughts about the future of schematic diagrams? Will it fade away, morph somewhat, become an entirely new technical entity? Or will it remain pretty much as-is?

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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The post Do we still need schematic diagrams for analog circuits? appeared first on EDN.

Bluetooth and Wi-Fi combine to untether smartphone-to-car connections…this time with a Google, versus Apple, angle.

Last month, I took apart a third-party adapter that aspires to augment Apple’s CarPlay interface with wireless connectivity between iPhone and vehicle.

This time, I’ll be disassembling the other adapter I’d mentioned at the end of late January’s initial conceptual coverage, in this case intended to wirelessly bridge between a car and an Android-based handset using Google’s Android Auto protocol.

But once again, the originally planned hardware target of my dissection attention isn’t what you’ll actually be seeing today. Initially, I’d planned on taking apart the v1 AAWireless unit, which I’d bought several years back in its original Indiegogo crowdfunding form.

But then I remembered that AAWireless had notably iterated the hardware (and associated software) design in-between that initial version and what ended up going into full production where it was sold and stocked not only by the manufacturer but also retailers like Amazon. AAWireless has already moved on to its second-generation product, in fact.

Supplier switcheroo, part 2

I didn’t want to further limit the project’s relevance by focusing on the rarer premier version of the first-generation offering (which put the company on the map, mind you, but still…). Instead, today you’ll be seeing the insides of this adapter (model BY969C).

It came from a company named “Vnilrgle” (believe it or not, and despite the user manual variously alternatively mentioning “TERUNSOIU”, or maybe that’s “TERUNSOIL”, as the supplier) and cost me a whopping $9.99 plus tax (with free shipping) from Woot in late February (versus listing for $48.87 on Amazon as I write this). Here are more stock shots to whet your appetite.

As you may have already noticed from one of them, this adapter model was of particular interest to me because of its low price, its quality construction (belying the $10 I paid for it), and its integration of NFC functionality, which aspires to simplify the initial setup process.

I’ll start out with shrinkwrap-inclusive front and back shots, as-usual accompanied by a 0.75′′ (19.1 mm) diameter U.S. penny for size comparison purposes, and revealing additional labeling.

The shrinkwrap-clinging stickers are absent from the now-clear-plastic-less backside photo that follows.

Time to open ‘er up.

Some literature bits (here’s an online version of the user manual).

And an optional-use double-sided sticker for, as I also said last month, adhering the wireless adapter to the vehicle interior.

As with its Apple CarPlay-supportive predecessor, this one includes a USB-A-to-USB-C adapter.

And here is today’s patient standalone, viewed from top.

Bottom.

Cable-entry point.

And cable connector-end perspectives.

Sh-sh-sh-shattered

(Obligatory admittedly-obscure-to-at-least-some section header reference)

Now to get inside. You’ve likely already noticed the gap between the silver-color circumference of the device body and the clear flat regions, both of which I’d assumed were made of plastic (for NFC reception reasons). My attempts to insert a spudger were unsuccessful, however.

So, I stuck the device in my vise (see what I did there?) in preparation for an attempted hacksaw-cut of one side. Oops.

I guess that’s glass, not plastic. And I won’t be using this device post-teardown. Onward.

Now for the other side, with tap-assistance from a ball peen hammer.

See those four screws? Not anymore, you don’t.

And with them removed, we have achieved liftoff.

An “Ultra” foundation for the fortunate

Let’s look first at the PCB underside (based on a device orientation assumption that places the product logo on the NFC antenna “top” side, with the marking minutia on the “bottom” side).

At left in the three-area-dominant IC row is the system processor. I mentioned last month, generally speaking about the wireless Android Auto and/or CarPlay product category, that “these are commonly Arm-based”. Judging from the markings on top of this one, there’s no doubt as to whose CPU core(s) is/are inside.

I’d even go so far to guess Cortex-A7 in generation. But who makes it? A search on “BU2025021” brought up bupkis. And the only reference I found to an “A7 Ultra” was associated with this Vanzen dual Android Auto-plus-CarPlay wireless adapter.

Although…”Cotex”?

Anyhow, to its right is the presumed serial-interface (therefore eight-lead package) firmware storage NOR flash memory, from GigaDevice and marked as follows.

AP2133
5F1GQ5UEY1H
UG5131

“1G” is suggestive of a 1 Gbit capacity, but I can’t find a direct reference to the IC anywhere online; reader assistance is welcomed! GigaDevice also makes Arm-based SoCs, by the way, so the company also acting as the source for the “A7 Ultra” wouldn’t be a complete surprise to me.

If you’re wondering (assuming my guess is correct) why 128 Mbytes of storage is necessary to implement a seemingly elementary device like this, my answer is two-fold albeit related.

• It doesn’t just handle Android Audio protocol and USB-to-wireless bridge functions
• And that capacity isn’t solely devoted to code

Turns out there’s also a web server (and pages) running inside the device, used for firmware-update and broader technical support-outreach functions, as this user manual page documents.

In fairness, circling back for a moment, the CarPlay adapter I took apart last month offers similar capabilities. I finally dug up an online version of the user manual for it; here’s the relevant page.

What’s the frequency, Kenneth?

(Another obligatory admittedly-obscure-to-at-least-some section header reference)

Finally, at far right is the wireless communications subsystem, based on the AIC8800DC40 controller from AICSemi, a company previously unknown to me, and surrounded by embedded Wi-Fi and Bluetooth antennae. Once again referencing last month’s writeup, I’d written the following.

Two wireless broadcast links are necessary: 2.4 GHz Bluetooth for initial setup, and Wi-Fi for ongoing streaming. The latter is usually based on the 5 GHz band for higher transfer bandwidth, since range isn’t a concern in a diminutive vehicle interior.

But in that teardown, I’d only found one antenna, suggestive of Bluetooth-plus-Wi-Fi shared usage, therefore 2.4 GHz-only system functionality. And this time, a datasheet I found online for the AIC8800DC40 suggests that it has 2.4 GHz-only Wi-Fi capabilities, even though the device documentation makes the following claims.

Wi-Fi Bluetooth module frequency:
Bluetooth 2.4 GHz, Wi-Fi 2.4-5.8 GHz

So… In search of clarity, I went looking for an FCC ID, which I hoped would lead me to definitive certification documentation. Believe it or not, nowhere related to last month’s patient—packaging, literature, or device itself—had I been able to find an FCC ID reference, or even a product name that might indirectly point me to my desired certification-data prize. Here’s what Google AI Assistant rightly said in response to my search query on “WOLIOS carplay adapter FCC ID”.

The WOLIOS wireless CarPlay adapter does not have an official, dedicated FCC ID registration tied directly to the “WOLIOS” brand name. Budget-friendly online resellers like WOLIOS often rebrand generic white-label factory units (such as common smart dongles) that may display general CE/FCC compliance claims or use an unverified label rather than maintaining an authentic, searchable filing in the FCC ID Database.

Alrighty, then. This time I at last had a valid model code, BY969C. With it, I tracked down the FCC ID (2A5XO-BY969D), which as it turned out covered a variety of products with different model numbers, physical appearances and both Android Auto and CarPlay support, suggestive of common hardware differentiated via firmware. And yes, both 2.4 and 5.8 GHz beacon support.

Speaking of antennae, and in closing, let’s now flip the PCB over to its topside and more closely check out that NFC subsystem.

Sequentially detaching the antenna from the PCB, both from connector and adhesive perspectives, and then peeling off its accoutrements, results in the following image sequence.

Note the LED that shines through the NFC antenna center “hole” and out the top of the device.

And now to dispense with the foam (at least most of it) between the double-sided sticker and antenna itself.

A Google search on the “BY969-LS-V01-NFC-HXW” product code stamped on top of the NFC antenna was of no help whatsoever. Alas. Unless, that is, I’m mistaken and it’s actually a Textured Johnny Collar Sweater Polo from Original Penguin by Munsingwear, sold by (but sold out at, as I type this) J. Crew Factory stores.

With that final bit of silliness out of the way, I’ll wrap up for today. Sound off in the comments with your thoughts on Rolling Stones or R.E.M. songs, men’s sweaters or anything else discussed in this piece!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Adapter makes Google’s wireless Android Auto a reality appeared first on EDN.

Every engineer’s confidence in measurement rests on more than the instrument—it depends on the interface that ties instruments together into a working system. Standards like GPIB, USB, LXI, PXI, and VXI are not just acronyms; they are the lifelines that enable communication, synchronization, and scalability across labs and production floors.

Understanding these interfaces equips engineers to unlock the full potential of their tools, ensuring precision today while building readiness for tomorrow’s challenges. This fundamentals guide maps the evolution and role of these connections, showing how mastery of interfaces translates directly into mastery of measurement.

Interfaces as the backbone of measurement

Instrument interfaces are the quiet enablers of every test setup, defining how equipment communicates, synchronizes, and scales. From the legacy reliability of GPIB to the plug-and-play familiarity of USB, and from the networked flexibility of LXI to the modular power of PXI and VXI, these standards form the connective tissue of modern measurement.

Mastering them isn’t just about knowing acronyms; it’s about gaining the confidence to build systems that are precise, adaptable, and future-ready. By understanding the fundamentals of these interfaces, engineers equip themselves to unlock the full potential of their instruments and drive measurement forward with clarity and control.

Legacy heavyweights: GPIB and serial

Before “plug and play” became the industry standard, test and measurement benches relied on a rugged era of “plug and screw-in” connectivity, dominated by GPIB (IEEE-488) and serial interfaces. GPIB is instantly recognizable by its massive, 24-pin Centronics-style connector and notoriously stiff, heavily shielded cabling.

Despite its bulk, GPIB offered a unique, ingenious hardware feature: stackability. Because the cables featured a male connector on one side and a female on the other, engineers could literally stack five or six connectors directly on top of a single instrument port to daisy-chain devices together, keeping complex automated test systems organized.

Figure 1 The GPIB interface in the B2901B source/measurement unit (SMU) incorporates the device into automated test systems, enabling seamless communication with legacy controllers and peripheral hardware. Source: Keysight

Parallel to GPIB, traditional RS-232 and RS-485 serial communication typically relied on robust DB9 or DB25 D-Sub connectors to lock down data links. While these legacy ports were a staple of early automated test setups, modern instrument backplanes have largely phased out the bulky D-Sub form factor.

Today, you are much more likely to find an RJ-45 or USB-B port that “emulates” serial communication. Transitioning to these modern setups often requires specific adapter cables—such as the ubiquitous “Cisco blue cable”—bridging the gap between classic serial protocols and modern benchtop connectivity.

The modern bench: USB and Ethernet

If you have bought a piece of test equipment in the last 15 years, there is a 90% chance your back panel is dominated by USB and Ethernet connectivity. Unlike the fragile Type-A ports found on modern consumer electronics, most instruments standardize on the chunkier USB Type-B port (the classic “printer cable” connection).

It’s a deliberate choice by instrument designers; the Type-B architecture is physically much more robust, providing the mechanical stability needed to survive the constant plugging, unplugging, and cable-tugging common in a busy lab environment. However, navigating instrument USB ports requires a bit of spatial awareness.

While the Type-B port on the back is meant for raw PC control, many instruments feature a standard USB-A port right on the front panel. It’s crucial to remember that this is a “Host” port. It is there to let the instrument control peripheral devices—like saving screenshots to a thumb drive or hooking up a mouse for easier UI navigation—and cannot be used to interface the equipment directly with a computer.

That mechanical status quo is finally shifting, however, with the slow but steady arrival of USB-C on the test bench. While engineers initially feared its tiny footprint would be too fragile for heavy lab use, its massive data bandwidth and high power-delivery capabilities are proving too good to ignore.

Modern compact USB oscilloscopes and smart, battery-powered field instruments are increasingly adopting USB-C, allowing them to simultaneously stream high-speed sample data to a PC and pull operational power over a single, reversible cable.

LXI/Ethernet (RJ-45)

If USB is the king of close-range bench automation, Ethernet is the undisputed champion for remote testing, distributed systems, and distributed lab networks. Utilizing the standard 8P8C (RJ-45) jack, modern Ethernet-enabled instruments generally conform to the LAN eXtensions for Instruments (LXI) standard, transforming a simple local network into a highly synchronized, long-distance test environment.

But Ethernet brings an even bigger hardware advantage to the bench: galvanic isolation. Unlike USB connections, which share a common DC ground between the instrument and your PC, Ethernet architecture is inherently transformer-coupled. This creates a physical, magnetic barrier for electrical DC currents.

If you are working with high-power systems or floating measurements where your instrument’s chassis sits at a different electrical potential than your PC, Ethernet eliminates the risk of “ground loops.” It ensures that a sudden voltage spike or ground fault will not travel down the communication line and catastrophically blow up your PC’s motherboard.

Figure 2 Arrow points to the LXI port on the RIGOL DS1202Z-E rear panel. Source: Rigol

The unsung hero of automation: Digital I/O interface

While analog channels get all the glory for capturing waves and signals, the digital input/output (digital I/O) interface is the quiet workhorse that turns standalone Test & Measurement (T&M) instruments into fully automated systems. Think of it as the instrument’s binary nervous system. It uses simple high/low voltage signals (typically TTL or CMOS levels) to communicate with the outside world.

Through digital inputs, an instrument can listen for external triggers—like a sensor detecting that a device under test (DUT) is properly in place, or a companion machine signaling is ready. Conversely, digital outputs allow the instrument to command its environment, such as triggering an external laser, switching a relay, or flashing a red warning light if a test fails.

For engineering students and hobbyists transitioning from manual bench testing to automated production lines, mastering digital I/O is the crucial first step toward building smart, synchronized, and hands-free test environments.

Figure 3 The digital I/O interface is on the rear panel of the Keithley 2602B SMU. Source: dataTec

High-speed backbone: PXI, PXIe, and VXI

When benchtop space is at a premium and a handful of standalone instruments can no longer keep up with massive channel counts or ultra-high throughput demands, the “instrument” undergoes a physical evolution. While VXI served as the rugged, VMEbus-based grandfather of this movement in the late 1980s, modern high-density testing has largely migrated to PXI and PXI Express (PXIe).

In these automated test equipment (ATE) environments, traditional boxes give way to modular instrumentation systems like PCI eXtensions for Instrumentation (PXI) and PXI Express (PXIe). In these systems, instruments lose their front panels, screens, and individual power supplies, transforming into compact, modular cards that slide into a shared industrial rack.

These card-edge modules do not work alone; they require a dedicated chassis to provide the necessary power, cooling, and communication pathways, alongside a dedicated controller card that serves as the system’s “brain.” What truly separates PXI/PXIe from consumer-grade PC chassis, however, is its high-density “hard metric” backplane connector packed with hundreds of pins.

This backplane doesn’t just route high-speed PCIe data lanes; it features hardwired, dedicated hardware lines for precision triggering and 10 MHz/100 MHz reference clocks. By baking synchronization directly into the physical backplane copper, engineers can synchronize multiple instrument cards—such as digitizers and RF signal generators—with absolute precision, dropping timing skew down to the picosecond level.

Specialty and high-frequency sync

When you are pushing the boundaries of high-speed measurement, a fast data interface like USB or Ethernet simply isn’t enough; the inherent software latencies are far too unpredictable. For true phase alignment and precise event matching, you need physical, hardware-level timing synchronization. This is where dedicated coaxial connections on the back panel come into play, stripping away communication protocols in favor of raw, speed-of-light electrical pulses.

The most common tool for this job is the ubiquitous BNC (Trigger In/Out) connector—the classic, 50-Ω “push and twist” interface found on almost every piece of serious bench gear. These ports carry simple TTL voltage steps to command multiple instruments to start capturing data at the exact same microsecond, eliminating any jitter caused by PC software.

Right alongside the trigger ports, you will almost always find the 10-MHz reference In/Out BNC ports. These are used to completely override an instrument’s internal crystal oscillator. By daisy-chaining these reference lines, you can “lock” the internal timebases of every instrument on your bench to a single master clock—whether that is a high-end oscilloscope or an ultra-stable external rubidium or GPS disciplined clock—ensuring your entire test system drifts as one.

Here is a side note on why 10 MHz. Ten megahertz (10 MHz) became the universal reference frequency because it strikes the right balance between practicality and precision. It’s low enough to distribute cleanly over coaxial cables without distortion, yet high enough to be multiplied or divided into the ranges needed for synthesizers and RF systems.

Its adoption was reinforced by national time services, rubidium and cesium atomic clocks, and GPS-disciplined oscillators, all of which commonly output 10 MHz. As a result, nearly every serious instrument supports it, making 10 MHz the common language for locking multiple devices to a single master clock.

Engineering trade-off: Speed, distance, and ruggedness

Ultimately, choosing the right hardware interface is an exercise in balancing speed, distance, and ruggedness against the specific needs of your test setup. If you are building a permanent, high-throughput automated rack that requires absolute clock synchronization, scaling up to PXIe or building out an LXI-compliant Ethernet network is the gold standard.

Conversely, if you are just pulling a quick measurement at your desk or running a temporary validation test, the simplicity of USB remains king. There is no single “best” interface—only the right tool for the specific measurement topology at hand.

Navigating the “hidden” hardware premium

As you map out your test system, it’s worth keeping an eye on the budget for the often-overlooked physical layer accessories. While it’s easy to assume that hooking up an older, high-end GPIB-equipped spectrum analyzer to a modern PC is just a matter of a simple cable change, the “hidden” hardware costs can catch you off guard.

Because GPIB is a complex parallel bus, standard GPIB-to-USB controller adapters from reputable T&M vendors require dedicated, specialized chipsets inside the cable housing. Consequently, these controller cables can easily run anywhere from $500 to over $1,000 each.

Figure 4. NI GPIB-USB-HS interface translates legacy GPIB signals into a USB-compatible format to enable remote instrument control and data logging. Source: National Instruments

Don’t let these price tags discourage you from utilizing legacy gear, though. These rugged adapters are highly reliable, built to last for decades, and frequently retain their value on the secondary market. Alternatively, if you are working on a tighter budget, there are excellent open-source or lower-cost third-party controller alternatives available, ensuring you can still breathe modern life into classic, high-performance bench instruments without breaking the bank.

From bench to bus: Your turn to build

At the end of the day, every piece of iconic technology—from the Mars rovers to the smartphone in your pocket—started as a cluster of instruments connected to a test bench. Whether you are a seasoned automation engineer managing a massive PXIe chassis rack, or a curious maker setting up your very first USB oscilloscope at a home workbench, the interfaces you choose are the quiet enablers that bring your designs to life.

Don’t let the complex acronyms or the price tags of high-end adapters intimidate you; the fundamentals of data, grounding, and synchronization remain exactly the same. So, here is our challenge to you: look at the back panel of your gear, grab a cable, and push your bench a little further this week.

If you are a novice, try writing a basic script to pull a single voltage reading over USB. If you are a veteran, see if you can optimize your automated test cycle times by swapping a legacy serial link for LXI Ethernet. Every great piece of hardware engineering is built on the back of rigorous measurement. Go wire up your bench, automate your data, and show us what you are building.

What does your current test setup look like? Are you still rocking legacy GPIB gear via adapters, or have you fully migrated to an Ethernet-driven LXI bench? Drop a comment below and share your worst ground-loop horror stories or your slickest automated test setups!

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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• Why you should use LXI instruments in your next T&M system
• The USB takeover: Why modern T&M is moving to your pocket

The post Measurement basics: A field guide to instrument interfaces appeared first on EDN.

Oscilloscopes utilize both hardware and software tools to enhance the resolution of time measurements. Happily, most of the processing is transparent.

The primary display from an oscilloscope is amplitude versus time. Most of the focus when using oscilloscopes is on the vertical axis, including amplitude resolution, analog bandwidth, and vertical accuracy. The time axis does not seem to get equal billing. That’s because oscilloscope time bases are very good.

Timebase accuracy

The oscilloscope’s timebase generates the sampling clock, which samples the input signal at uniform time intervals at the sampling rate. The sampling rate and the length of the acquisition memory determine the horizontal scale factor. The timebase clock of an oscilloscope has a frequency accuracy generally specified in parts per million (ppm) or parts per billion (ppb).

For example, an instrument with a timebase specified as accurate to within ± 0.1 ppm (100 ppb). This means that any time interval, T, being measured is accurate to within ± 0.1/106 of the value of T. If the measured interval is one second, the uncertainty of the measurement is ±1×10-7 seconds or ±0.1 microseconds (ms).

Clock oscillators are subject to frequency drift over time. This timing uncertainty is cumulative and increases as the oscillator operates over longer periods. That drift, called aging, is usually specified as an additive uncertainty in frequency, expressed in parts per million per year (ppm/yr). A typical clock timebase accuracy specification might be ±0.1 ppm + 0.05 ppm/year. The time is measured from the instrument’s last calibration.

If the oscilloscope’s internal timebase is not as accurate as desired or if the oscilloscope’s operation must be synchronized with other instruments, many oscilloscopes include an external clock reference input. The external reference is usually generated from a very stable signal source at either 10 or 100 Megahertz (MHz), which is used to synchronize the internal timebase to the reference input to improve its accuracy.

Improving time resolution

The time resolution of a digitizing instrument, based only on the sampling clock frequency, would be the reciprocal of the sampling rate. An oscilloscope that samples at 40 gigasamples per second (GS/s) would have a time resolution of 25 picoseconds.

Oscilloscopes enhance hardware time resolution by using a specialized frequency counter called a time-to-digital converter (TDC). In real-time acquisition mode, the time-to-digital converter measures the time between the trigger event and the next sample.

In general, the trigger event and the sample clock are not synchronous. The time delay between these two events is uniformly distributed over the sampling period. The uniform distribution means that any time delay between zero and the sampling period is equally possible. The time delay for each acquisition is called the horizontal offset and is a characteristic of the acquired waveform. Figure 1 shows a horizontal offset measurement.

Figure 1 A typical measurement of the horizontal offset of an acquisition measuring time between the trigger point and the next sample point.

The figure shows an acquired waveform. The bright dots on the waveform indicate the real samples.

Horizontal relative cursors provide a visual measurement of the time between the trigger point and the next following sample and display the Δx value of 12.5 ps in the cursor readout field in the lower right corner. The TDC output provides an exact digital readout internally.

The time resolution of the TDC is much finer than the sample rate. In this specific example, it is five ps. The horizontal offset is used to align waveform samples for display and measurements. It is also used to combine multiple acquisitions of a periodic waveform into a random interleaved sampling acquisition.

Random interleaved sampling

Random interleaved sampling (RIS) is an acquisition mode that enhances the instrument’s time resolution when measuring multiple periodic waveforms with a stable trigger point. The oscilloscope acquires multiple waveforms, each with the same shape (Figure 2).

Figure 2 The horizontal offset, time delay between the trigger and the next sample, is uniformly distributed over the sampling period; multiple acquisitions show this variation.

Each acquired waveform has a horizontal offset uniformly distributed over the sampling period. Multiple acquired waveforms will each have a different horizontal offset. Examining the time difference between the trigger point and the first sample that follows in the figure illustrates this variation. Overlaying the twelve waveforms shows how they synthesize a waveform with an effectively higher sample rate (Figure 3).

Figure 3 Creating a composite waveform from multiple acquisition results in a higher effective sample rate.

The oscilloscope measures the horizontal offset of each waveform and categorizes them to select those whose values are multiples of the desired effective sampling rate. These selected waveforms are combined to form the RIS waveform (Figure 4).

Figure 4 This graph compares a real-time and RIS waveform.

The lower waveform in the figure is the real-time acquisition. Cursors mark a 25 ps sampling period of the real-time waveform.  The upper trace is the RIS acquisition. Note that there are five effective sample periods between the cursors; the effective sample rate is five times the 40 GS/s sample rate, or 200 GS/s. Remember that the RIS acquisition mode requires multiple repetitive acquisitions with the identical waveform using a stable trigger point.

Sequence mode

Sequence mode is another acquisition mode that uses the TDC. This mode is used to minimize the dead time between adjacent acquisitions. It is also applied to reduce the time between acquisitions. Sequence mode breaks the acquisition memory into a user-defined number of segments. Each segment holds a single acquisition. Since the oscilloscope does not need to display the trace between segments, the dead time between acquisitions is minimized.

The downside of this mode is that the time between segments is indeterminate as the instrument waits for the next acquisition trigger. To counter this, the oscilloscope marks the location, in time, of each segment in two ways.

First, it labels the start of each segment using the oscilloscope’s real-time clock to label each trigger time. The real-time clock has a resolution of one second, which is not practical for fast acquisitions. It also uses the TDC to measure the time delay of each trigger from the first trigger in the acquisition (Figure 5).

Figure 5 A sequence mode acquisition of five ultrasound pulsed bursts showing the sequence mode time stamps.

The figure shows a sequence-mode acquisition of five ultrasonic pulse bursts, each in its own segment. The sequence mode time stamps appear under the graphic display, including the absolute time from the oscilloscope’s real-time clock in the column labeled time. Additionally, it lists the time from the start of the first segment and the time between segments. These TDC-measured times are displayed with a resolution of one nanosecond.

The time stamps indicate the timing of the trigger events. It basically places each segment at a specific time. If each trigger event is an anomaly, then the time stamps provide the frequency of the anomalies, a bit of diagnostic information that often proves useful.

Interpolation

If the TDC is the hardware tool for precise time measurements, then interpolation is the software tool. Interpolation is a mathematical technique for increasing the effective sample rate of an acquired signal. Interpolation calculates intermediate sample values between the real-time samples. Interpolation is usually applied to the displayed data, but in many cases, it is incorporated into application-specific measurements.

Interpolation is also available as a math function and can be used to increase the time resolution of acquired waveforms. The oscilloscope used in this article offers sin x/x, linear, or cubic interpolation with sampling rate improvement from two to fifty calculated points per real-time sample.  Interpolation increases instrument processing time proportional to the number of interpolated samples.

On the positive side, interpolation can be applied to single-shot acquisitions. On the downside, interpolation requires that the data meet the Nyquist criteria and have a sample rate greater than twice the signal’s bandwidth. Failure to satisfy Nyquist can result in significant errors. From a data integrity perspective, it is essential to note that RIS data comprises all real samples, whereas interpolated data is a combination of real and calculated sample values.

Jitter measurements

Jitter is a short-term variation in the timing of a digital signal from its nominal value. Any timing parameter can be the subject of jitter analysis, and the main timing parameters considered are variations in width, period, and time-interval error (Figure 6).

Figure 6 This graphic gives examples of timing uncertainty in width, period, and time interval error jitter, including jitter measurements along with the histogram of time interval error.

Width or period jitter can be measured using the width and period measurement parameters, respectively. The jitter is evident in the statistical readouts for minimum (min), maximum (max), and standard deviation (sdev). The difference between the maximum and minimum is the range or peak-to-peak jitter. The standard deviation is the root-mean-square (RMS) jitter.

Time interval error (TIE) measures the difference between each actual waveform edge and the ideal location of that edge. The ideal edge locations are computed from the waveform’s mean frequency.  TIE can be thought of as the instantaneous phase of the signal.

 The time parameters period, width, and TIE are measured by determining the time between edges. For a period, it is the time between adjacent edges with the same slope. For the width measurement, it is the time between adjacent edges with different slopes. TIE measures the time between an acquired edge and an ideal edge. The measurement uses interpolation to achieve the highest possible time resolution (Figure 7).

Figure 7 A dual interpolator finds use in obtaining a more precise measurement time resolution.

The figure shows an edge defined by three real-time samples taken with a 10 GS/s sampling rate. The interpolator uses a cubic interpolation to fit several interpolated samples between each real-time sample. Then, the two samples that bracket the measurement threshold are used to perform linear interpolation to determine the time at which the measurement threshold is crossed. The resulting measurements in this example have a resolution better than 1 picosecond.

Jitter has both random and deterministic components.  Random jitter is associated with stochastic processes, such as noise, and is unbounded, meaning it increases with increasing observation time. Deterministic jitter is bounded, and its amplitude is limited with increasing observation time. The random components of jitter are studied using statistical tools, such as histograms.

Figure 6 shows the histogram of the TIE parameter. There are parameters intended to interpret histograms themselves. The histogram mean (hmean), mode (hmode), standard deviation (hsdev), and range (hrange) are examples of histogram-specific parameters.

Conclusion

Oscilloscopes utilize both hardware and software tools to enhance the resolution of time measurements. Improved time resolution is used both in displaying the data and in measurements. Happily, most of the processing is transparent and requires little user interaction to achieve good results.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

Related Content

• Using an oscilloscope’s time, frequency, and statistical measurement domains
• Basic oscilloscope operation
• Analyze noise with time, frequency, and statistics
• Oscilloscope special acquisition modes
• How to perform histogram analysis on your oscilloscope
• Basic jitter measurements using an oscilloscope
• Closing the gaps in your digital oscilloscope waveforms

The post Secrets of oscilloscope time measurements appeared first on EDN.

Odorless. Colorless. Tasteless. But certainly not harmless. Radon, in both air and ground water, is a health risk whose prevalence should be regularly assessed and, if necessary, dealt with.

Beginning last fall and continuing through early summer, my community built an emergency access road that links up with a state highway below us and provides an alternate escape path in case of fire or other calamity, a particularly appealing option for those (like me) whose homes are at the far end of the community.

Road construction involved, among other things, the use of dynamite to blast pathways through rocky hillsides. And shortly after road completion, I learned that a residence a few minutes’ walk away from us had tested positive for high radon levels and was in the process of installing a mitigation setup.

Were the two events—earth disturbance due to road construction and radon release—related? I don’t know, and I’m not forward enough to ask the neighbors, but it’s possible. Regardless, even though our home had successfully passed a radon test done as part of the pre-purchase inspection more than a decade ago, I was motivated to learn more about radon and then re-test the premises for myself to see if the situation had subsequently evolved in an adverse direction.

Uranium and radium decay

As usual, I began my education with a visit to Wikipedi’s radon entry.

Radon is a chemical element; it has symbol Rn and atomic number 86. It is a radioactive noble gas and is colorless and odorless. Of the three naturally occurring radon isotopes, only 222Rn has a sufficiently long half-life (3.825 days) for it to be released from the soil and rock where it is generated. Radon isotopes are the immediate decay products of radium isotopes.

Here’s more.

A common source of environmental radon is uranium-containing minerals in the ground. Radon can also occur in ground water, such as spring waters and hot springs. Radon trapped in permafrost may be released by climate-change-induced thawing of permafrosts, and radon may also be released into groundwater and the atmosphere following seismic events leading to earthquakes, which has led to its investigation in the field of earthquake prediction.

Seismic events leading to earthquakes…and possibly also dynamite blasts? Here’s where the prose turned worrisome.

Epidemiological studies have shown a clear association between breathing high concentrations of radon and incidence of lung cancer. Radon is a contaminant that affects indoor air quality worldwide. Because radon is denser than air it accumulates in basements and crawlspaces under dwellings. According to the United States Environmental Protection Agency (EPA), radon is the second most frequent cause of lung cancer, after cigarette smoking, causing 21,000 lung cancer deaths per year in the United States. About 2,900 of these deaths occur among people who have never smoked. While radon is the second most frequent cause of lung cancer, it is the number one cause among non-smokers, according to EPA policy-oriented estimates.

And finally, there’s this from the related Wikipedia entry for radon mitigation.

There is no proven link between radon in water and gastrointestinal cancers; however, extremely high radon concentrations in water can be aerosolized by faucets and shower heads and contribute to high indoor radon levels in the air.

Yikes!

Radeon prevalence varies across the United States and, more broadly, the world at large. It turns out that Denver, Colorado and surrounding regions have among the highest U.S. concentrations, as the following two related graphics show. The first documents the predicted fraction of U.S. homes having concentrations of radon exceeding the EPA’s recommended action level of 4 pCi/L. Note the orange region smack dab in the middle of Colorado, right where my residence is located.

And then there’s this one, which formats the data slightly differently, but ends up with the same essential outcome.

The most concise and clarifying data I came across related to my specific situation comes from an informative page (and a highly recommended read, even if you’re not a neighbor of mine) on the Jefferson County website.

Approximately 50% of homes in Jefferson County test above the EPA action level for radon every year.

It’s followed by this.

Radon is found throughout the U.S. and is particularly prevalent in Colorado. The U.S. Environmental Protection Agency (EPA) has ranked Colorado as a Zone 1 area, meaning the average house will exceed the EPA’s action level for indoor radon.

Once again: yikes! I guess that’s why I see mitigation setups (more on them later) like this one all over the community.

Testing scenarios and equipment options

The Jefferson County webpage on radon also includes these non-scientist explanation statements that I thought were enlightening.

Radon is an invisible, odorless, tasteless, cancer-causing gas that comes from the natural radioactive breakdown of uranium and radium in soil, rock and water. Radon enters buildings through cracks, holes and pipes in the foundation. All buildings contain some radon, but homes are the most concerning since that is where families spend most of their time.

There’s also this.

Radon is produced as a decay product from uranium and radium. This naturally occurring radioactive gas is found in most soil, rock, and groundwater. Since radon is a gas, the inert element can easily travel through cracks and pores without being chemically bound or attached to other elements. Voids and porous materials are found under every building, allowing radon easy entry.

Perhaps obviously, once again quoting from the Jefferson County website, “the test kit should be placed in the lowest occupied level (typically a basement) and in the normal breathing zone (about 2-6 ft. from the floor) and 3 ft. from windows, doors, vents, or anything that allows airflow.”

Preferably, in fact, windows, doors (especially screened) and other outside-air ventilation sources should be shut as much as possible through the entire multi-day testing cycle to minimize gas dilution and maximize negative pressure (aka, “stack effect”) flow into the home, thereby simulating the worst-case radon accumulation that would normally occur in winter and other closed-off times (that said, air conditioning systems are another common catalyst for high radon gas leakage into buildings).

Free radon test kits are available to me from both Jefferson County and the Colorado Department of Public Health and Environment and can also be bought from local hardware and home improvement stores and online retailers. Keep in mind, however, that the kit still needs to be sent in for post-test analysis, with results subsequently sent back to the submitter, all steps incurring delays.

Yet another gizmo-acquisition opportunity

Instead, especially since I’m a techie who can’t resist new toys, I decided to buy my own radon detector hardware. The Airthings Corentium Home 2 (stock photos and promo video follow) normally costs around $180, but I found one promotion-priced on the Resale (formerly Warehouse) area of Amazon’s website for $121.46.

Versus its first-generation predecessor, it supplements the integrated display with Bluetooth LE and SmartLink (Airthings’ proprietary wireless protocol) connectivity to a separate device.

And battery life extends from 1.5-2 years (3 AAA alkaline batteries) with the original Correntium to 2-3 years (two AA alkaline batteries).

Here’s my own unit, starting with outer packaging shots.

Now open, with the contents accompanied by a 0.75′′ (19.1 mm) diameter U.S. penny for size comparison purposes.

Inside, of course, is the Corentium Home 2, along with some literature (also found online here) and a silica gel packet.

Here’s the open backside; batteries are included, with only a thin slip of plastic needing to be removed to complete the connection. Activate them as the power source and start testing.

Mating and initial setup of the device with my smartphone—which subsequently receives periodic notifications from it—was uneventful.

And, after a preparatory 24-hour delay over which the device collected and averaged (but did not yet share with me) its initial data set, preliminary results were encouraging.

I kept the measurements going for nearly three weeks before capturing another screenshot set, and the good news thankfully kept coming.

The application (Android in my case, but iOS also available) displays trend graphs, too, useful to see how radon levels, along with also-measured humidity and temperature, varied over time.

Mitigation methodology

All well and good, though I plan to continue conducting going-forward measurements, since radon gas levels vary over time due to a variety of factors. But what if my results had been more concerning? Step one is to seal off as much as possible any soil-sourced radon gas leakage coming into the house through slab and foundation cracks; more substantial slab voids resulting from floor drains and sump pumps are also potential culprits, albeit harder-to-eliminate ones.

Next, strive to minimize negative pressure (stack effect) situations, where the inside-house air pressure is lower than that of the outside, generating a partial vacuum condition that pulls air in from below the residence in attempting to equalize the differential. Frequent, vigorous use of HVAC systems is a potential root cause of pressure imbalances, along with attic fans, bathroom and kitchen-cooking-appliance exhausts, and the like. Keeping windows and screen doors open whenever weather and broader seasonal temperatures afford this option, as earlier mentioned, is helpful albeit only as temporary workarounds.

The most significant mitigation measure, and one that per my earlier shared photo I see frequently around my community, involves the installation of an active soil depressurization system. A PVC pipe originating below the home’s foundation, commonly in combination with a continuously running inline fan, draws radon gas out and up to the roof where it’s safely exhausted, completely bypassing the residence interior (and its inhabitants) in the process.

A tutorial video I found online showcases an in-home mitigation system installation.

I found it interesting for two main reasons, among others:

• The system’s location: I’d previously only been familiar with exterior-visible setups such as the one in the earlier-shown photo. I now wonder how many more homes in my community have implemented radon mitigation, internally (and therefore invisible to me from the outside) in these latter cases.
• And the initial, albeit unsuccessful, attempt to rely solely on a passive system, later supplemented by an active fan to create sufficient incremental suction.

I’ll wrap up here and turn it over to you for narration of your radon-related experiences and broader thoughts in the comments. Thanks as always in advance for them!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Improve HVAC efficiency with accurate sensors
• My Geiger counter doesn’t count (sob sob)
• Design femtoampere circuits with low leakage, part 1 and part 2

The post Radon: Level detection, risk determination, and as-needed mitigation appeared first on EDN.

The Controller Area Network (CAN) extended data-field length (XL) specification—which has been standardized for years—now has the first commercially available CAN XL transceiver. Texas Instruments has unveiled the TCAN6062 CAN XL transceiver, which supports payloads of up to 2,048 bytes per frame and data rates up to 20 Mbps.

The CAN XL transceiver ensures that priority messages are delivered first and on time, facilitating performance critical to humanoid robots, industrial robots, and human-machine interface (HMI) systems. This allows system designers to leverage CAN XL to exchange data rapidly and reliably in applications ranging from industrial robotics to automotive safety.

Figure 1 The CAN XL technology is promising to open the door to a new era of applications. Source: Texas Instruments

The new CAN XL transceiver is also backward compatible with CAN flexible data rate (FD) and CAN signal improvement capability (SIC) operations. This ensures a seamless migration and enables design teams to evolve existing designs incrementally without requiring a full redesign.

Next, while CAN XL is better and cheaper than CAN FD, it can also tunnel Ethernet. So, the CAN XL transceiver allows engineers to consolidate communication layers and use Ethernet in mixed-network architectures with Transmission Control Protocol/Internet Protocol (TCP/IP) tunneling. That facilitates efficient transfers of diagnostics, sensor data, control traffic, and over-the-air (OTA) updates on a single network.

Figure 2 The TCAN6062 CAN XL transceiver helps reduce ringing by up to 80% in complex networks, simplifying validation in high-node architectures. Source: Texas Instruments

CAN has been the backbone of industrial communications for decades. However, industrial systems are now generating and demanding more data than ever before. That’s because applications require fast, deterministic communication to synchronize motion control, sensor feedback, and diagnostic data. That, in turn, leads to new networking requirements, and as a result, engineers often accept system-level trade-offs to compensate for bandwidth constraints.

Dwight Byrd, GM of Interface Products at TI, claims that the TCAN6062 CAN XL transceiver bridges that gap. “It offers engineers a path to higher-bandwidth networks while maintaining the proven reliability CAN is known for.”

“As industrial systems become more intelligent and interconnected, what we ask of our networks continues to evolve,” Byrd added. “Engineers need more data, higher speeds, and greater flexibility, all without compromising performance or reliability.

TI’s networking technology managers are confident that CAN XL will open the door to a new era of applications, enabling systems to deliver higher performance at a reasonable cost. And here, TI has the first-mover advantage.

Related Content

• DIY CAN Transceiver
• Addressing immunity requirements for CAN transceivers
• Implementing the CAN Protocol in 3G Equipment Designs
• CAN: Network for Thousands of Applications Outside Automotive
• Signal Chain Basics: Industrial Market Transitions to 3.3V CAN Transceivers

The post TI a first mover in CAN XL transceivers appeared first on EDN.

AI-driven demand underpins logic foundry and memory fab capacity constraints, leading to cost increases. Add tariffs to the mix, and Google and its competitors (not to mention end users) pay the price.

Last year’s Made By Google fall product launch event happened midday on August 20, moderated by Jimmy Fallon. Although I found value in the devices, software and services Google unveiled there, the un-traditional Tonight Show-styled format wasn’t particularly to my liking, a negative opinion shared by a notable number of others whose coverage I subsequently perused.

This year’s event, earlier today (August 12) as I write this, was once again celebrity-moderated, this time by Trevor Noah. But this time it took place in the evening, with the announcements notably preceding it; a flurry of blog posts had already hit Google’s website at 8 am MT, where I am. Feel free to draw your own conclusions as to the judged effectiveness (or, perhaps more accurate, lack thereof) of last year’s event And begging the question of why Google bothered doing this year’s event at all, save I suppose for the chance to see “live” demos, “softball” interviews and other such questionable-value content.

That said, the products themselves once again were notable, both in an absolute sense and relative to their prior-generation predecessors.

Befitting my engineering-dominated readership, I’ll as usual start out my coverage with the application processor, the Tensor G6, the intelligence nexus of the Pixel 11 smartphone series.

Power/performance balance (and profit) optimization

When I published last year’s event coverage, little was known at the time about the latest-generation Tensor G5 SoC save for its 3 nm TSMC fabrication source (a notable departure from Google’s longstanding foundry partnership with Samsung) and its eight-core CPU cluster mix: “one “prime” core, five mid-level ones, and two efficiency ones.” Beyond that, all Google was saying at the time was that, versus its Tensor G4 predecessor, it delivered the following updates.

• An up to 60% more powerful TPU
• A 34% faster on average CPU, and
• New security hardware

One year later, thanks to intensive developer engagement with the platform, we know much more about the Tensor G5 than we did before.

• CPU (8 total cores): 1x Arm Cortex-X4 at 3.78 GHz, 5x Arm Cortex-A725 at 3.05 GHz, 2x Arm Cortex-A520 at 2.25 GHz
• GPU: Imagination Technologies PowerVR (DXT-48-1536)

And now on “Day Zero” of the Tensor G6 era, what’s Google saying about it? Predictably, not much beyond another year’s worth of nebulous hand waving in comparison to the Tensor G5:

Tensor G6 features an upgraded CPU for 25% faster web browsing and 15% quicker app launches. Packing 50% more TPU compute and paired with the latest Gemini Nano model, Google Tensor G6 processes on-device AI tasks up to 3.5 times faster while using up to 3.5 times less energy.

But thanks to a leak sourced from embargoed media hands-on time with the Pixel 11 family, the following additional (and more specific) Tensor G6 specs, referencing Arm’s C-series cores, are also presumably accurate.

The Tensor G6 sports a seven-core configuration, with one prime “C1 Ultra” core clocked at 4.1GHz, four performance “C1 Pro” cores clocked at 3.4GHz, and two efficiency “C1 Pro” cores clocked at 2.65GHz. The GPU appears to be a PowerVR C-series variant with six compute units clocked at 1.3GHz.

One other silicon-related nuance also bears mention. Although, as previously mentioned, Google switched from Samsung to TSMC as its foundry source for the Tensor G5 last year, it stuck with Samsung’s Exynos cellular subsystem. This year, reportedly (although I haven’t yet seen definitive confirmation), this too has changed; Google’s supposedly now leveraging MediaTek M90 5G cellular IP.

Smartphone evolutionary modesty

Aside from the new colorways, you’d understandably likely be hard-pressed to discern a visual difference between Google’s latest handsets—the baseline Pixel 11, high-end Pixel 11 Pro and Pro XL, and book-style Pixel 11 Fold—and their 10th generation predecessors. Backs are once again all-glass. Displays are a bit brighter, and more scratch-resistant in the “Pro” variants. Camera bars are a bit more svelte (along with overall Fold thinness), and for “Pro” versions, embed a multicolor notification LED assembly surrounding the flash and branded “HiLight”. Particularly clever readers may have already noted the enhanced scratch-resistance association, since the notifications can only be seen when the phone is screen-down on a flat surface.

That all said, to the overall “supply constraints” theme of this writeup, I’ll point out that the Pixel 11 storage options now start at 256 GBytes; the entry-level 128 GByte variant of the Pixel 10 that I recently acquired isn’t offered this time around. In Google’s defense, Apple did the same thing a year ago with the iPhone 17 versus its iPhone 16 precursor, although in that earlier case the 2x capacity multiplier came for the same intro price as the 128 GByte prior-gen device.

This time the 256 GByte Pixel 11 price thankfully at least matches that of the year-ago 256 GByte Pixel 10, versus with an accompanying price increase as other smartphone suppliers are doing nowadays. Further to Google’s defense, note that a year ago any bill-of-materials cost increases were predominantly due to tariff impacts. Now, in contrast, supply constraints are additionally being felt to fuller effect. It’ll be curious to see how Apple handles both memory and TSMC foundry cost increases at its likely next-month announcement event; for one thing, the company will reportedly delay the launch of its baseline iPhone 18 until sometime next year.

In closing, at least for this section, one more memory-related twist bears mention. A year ago, I wrote, “Google also didn’t “hide” tariff costs by cutting RAM capacities (which would counterbalance its burgeoning AI ambitions, anyway)”. Well, this year they did. The lowest (256 GByte) storage capacity variants of the Pixel 11 Pro and Pro XL also have less RAM—12 GBytes vs 16 GBytes—than both their higher-capacity this-year siblings and same-capacity Pixel 10 predecessors, in the latter case with no accompanying generational price break. Admittedly, Google’s working hard on optimizing memory requirements for its on-device models, but still…

Watches and trackers

Last year’s Pixel Watch 4 was a notable update to its predecessor(s), as I wrote about at the time (although I’m still fiscally quite content with a recent update from my long-in-the-tooth first-generation wearable to “only” the Pixel Watch 3, more discussion of which I’ll save for another post another day). This year’s Pixel Watch 5 advancements are also more modest, notably including slight (~12%) CPU performance and battery capacity upticks along with an on-device AI-intended RAM upgrade from 2 GBytes to 3 GBytes, the latter leading to—you guessed it—an associated $50 price tag increment.

I’m not entirely sure why Google included a set of earbuds in its launch suite promo photo shown earlier this piece, as aside from a new Pixel Buds 2 (two years old) colorway option and pending firmware-delivered feature updates to both them and the Pixel Buds 2a (introduced a year ago), nothing’s new. Conversely, the most brand-new device released this week was the Pixel Tag, unsurprisingly supportive of Google’s Find My Device network and conceptually similar to (and a competitor of) Apple’s also-UWB-enhanced second-generation AirTag.

Hopefully, this wireless-connectivity enhancement suggests that we’ll be seeing broader support for UWB in both Google’s and other Android licensees’ handsets in the future. My biggest surprise here is that, unlike Motorola and other tracker manufacturers, Google didn’t also adopt an AirTag-clone form factor that would enable it to slot into the already sizeable and still steadily expanding AirTag ecosystem of luggage tags, stealth security setups and the like.

That’s what I’ve got for you today, folks. As always, please sound off with your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Made by Google 2026: This limited silicon-supply situation really sucks appeared first on EDN.

NoMIS Power has developed a 6.5-kV large-die SiC MOSFET that has demonstrated over 8 kV of blocking voltage, 90-mΩ on-resistance, and 55-A drain current. Based on the planar SiC technology used in its 3.3-kV devices, the 6.5-kV MOSFET extends the technology into the high-voltage class and provides a foundation for the company’s planned 10-kV MOSFETs and 20-kV SiC IGBTs.

NoMIS is sampling the 6.5-kV SiC MOSFET to U.S.-based customers, with standard-production devices scheduled for Q4 2026. The company plans to expand the 6.5-kV portfolio with additional on-resistance variants, small-die MOSFETs, hybrid junction-barrier Schottky FETs (JBSFETs), and standalone diodes for applications including HVDC power transmission, solid-state transformers, pulsed-power systems, rail traction, and megawatt-scale EV charging

The 6.5-kV devices build on the company’s 3.3-kV SiC MOSFET family, which is already in production, while 10-kV and higher-voltage MOSFETs, diodes, JBSFETs, and SiC IGBTs are in development.

For more information, visit the NoMIS Power Semiconductors and Modules webpage.

NoMIS Power

The post 6.5-kV SiC MOSFET reaches 8-kV blocking appeared first on EDN.

NEO.AI is a memory platform from NEO Semiconductor that overcomes SRAM and DRAM scaling limitations in AI memory systems. As part of the platform launch, NEO Semiconductor is introducing its X-SRAM technology for on-chip memory in GPUs and AI processors and reporting its latest progress on 3D X-DRAM, a high-capacity memory technology for HBM.

By replacing conventional six-transistor SRAM with a two-transistor architecture, X-SRAM enables up to 5 times higher memory density to support 1–2 GB of on-chip memory, according to NEO. The technology maintains SRAM-class performance and is compatible with advanced nanosheet CMOS processes. It also provides a path toward future monolithic 3D X-SRAM implementations.

Built on 3D NAND manufacturing processes, 3D X-DRAM delivers up to 10 times higher memory capacity than conventional DRAM, according to NEO. Successful proof-of-concept validation demonstrates its potential as a scalable and manufacturable solution for next-generation HBM.

For more information, visit the NEO X-SRAM webpage.

NEO Semiconductor 

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The KTS1630 5-A eFuse from Kinetic Technologies protects sensitive electronics against overcurrent, short circuits, and thermal faults. It is designed for consumer and industrial systems operating from 5-V and 12-V power rails, helping improve system safety and reliability. By detecting overcurrent conditions typically within 100 ns, the device can isolate faults before they can damage downstream circuitry.

An integrated MOSFET with a typical on-resistance of 31 mΩ from VIN to VOUT helps reduce conduction losses while supporting operation across a 4.5-V to 18-V input range, with a 20-V absolute maximum rating at VIN. The KTS1630’s adjustable 1-A to 5-A current limit allows designers to set the protection threshold for specific loads rather than relying on a fixed current-limit threshold. The eFuse also includes a dedicated control output for an external reverse-blocking MOSFET that prevents reverse current when the input supply is removed or the output voltage exceeds VIN.

A programmable output slew rate controls inrush current during startup, helping prevent input-supply droop, connector stress, and unintended system resets when large capacitive loads are connected.

Supplied in 10-pin, 3×3-mm VDFN packages, the eFuse is available in both auto-retry and latched-off versions.

KTS1630 product page 

Kinetic Technologies  

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A high-speed USB-to-UART bridge, MaxLinear’s Carmel MxL81434 supports console access and infrastructure management in AI data centers and hyperscale cloud environments. The highly integrated device includes USB 2.0 High-Speed (480 Mbps) connectivity, four independent UART channels operating at up to 15 Mbps each, an I2C master, and 32 GPIOs for server and rack-scale management designs.

Carmel extends MaxLinear’s USB-to-UART portfolio, increasing the maximum UART data rate to 15 Mbps and doubling the transmit and receive FIFO size. The 1024-byte FIFOs help sustain high throughput and reduce host processor overhead, while the integrated I2C master and 32 GPIOs consolidate management, monitoring, and debugging functions. Low-latency console connectivity supports faster system bring-up, recovery, diagnostics, and provisioning.

The USB-to-UART bridge provides ±15-kV HBM ESD protection for demanding server and data center environments.

Samples of the Carmel MxL81434 are expected to be available Q4 2026.

MaxLinear

The post Four-channel USB-UART IC boosts server management appeared first on EDN.

ROHM is offering the RTD-EVK-G2 evaluation kit, based on its second-generation terahertz-wave oscillation device. Built using resonant tunneling diodes (RTDs), the device delivers up to 40 µW of output power, four times that of the first-generation product. The kit enables companies and research institutes to evaluate terahertz-wave oscillation and detection for applications such as nondestructive testing, medical imaging, high-resolution radar sensing, material identification, and high-speed wireless communications.

Unlike conventional terahertz systems, which are costly and require large equipment, the RTD-EVK-G2 includes a sample device, cable, and evaluation board for evaluation in space-constrained settings. The terahertz device maintains the same 0.5×0.5-mm chip size and 4.0×4.3-mm PLCC package as the first-generation component. Compared with other terahertz generation methods, the RTD approach generates less heat and consumes less power.

Sales of the RTD-EVK-G2 kit are scheduled to begin in August 2026 at $3,300 per set. Contact a sales representative or visit the Rohm contact page for more information. Purchase of the evaluation kit requires signing a non-disclosure agreement with Rohm.

Rohm Semiconductor 

The post RTD terahertz evaluation kit quadruples output appeared first on EDN.

This circuit enables you to generate remote control PWM test signals with a (very) generic (and cheap) chip.

A recent Design Idea illustrated the application of an interesting chip (the LTC6992) to remote control (RC) PWM test signal generation. Being familiar with neither the application nor the chip, and despite being a (very) old dog, I decided to try to learn a new trick or two.  So I took a trip Through the Looking Glass into the LTC6992 datasheet.  Here’s what I found there.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Firstly, the LTC6992 is a very capable and consequently rather complex device.  Inevitably its datasheet is similarly complex and, frankly, more than a little confusing.  Which, of course, might be due to that old dog factor!  But moving along…

Secondly, it’s not inexpensive: ~$6 in singles, plus it needs an external precision regulator that adds another buck.

But worsetly (??? Ed.), it happens that the RC PWM application involves rather low, only 5% to 10%, PWM duty cycle numbers.  When you combine that with the LTC6992 datasheet’s specification (on page 4) of +/-3% typical duty cycle error, it becomes clear the LTC6992 is unlikely to be very happy (or accurate) in this application.

So I decided to work toward a Design Idea that would be more familiar (and friendly?), not needful of (too many) extra external components, (mainly) more accurate, and hopefully a bit cheaper.  Figure 1 shows what my labors achieved.

Figure 1 This Design Idea leverages a LMC555 as a variable duty cycle (1ms to 2ms = 5% to 10%), constant frequency (20ms = 50Hz) PWM oscillator.  Timing is ratiometric and therefore independent of V+ so no external voltage regulator is needed.

How it works is (roughly) sketched in Figure 2’s timing diagrams.

Figure 2 The PWM oscillation cycle alternates between the Threshold pin for the duration of the 1ms to 2ms ON halfcycle is adjusted by R1, and the Trigger pin for the 18ms to 19ms OFF halfcycle. C2 > C1 to compensate for D1 forward drop.

PWM duty cycle = (R2 + R1+)/(R1 + R2 + R3) = 5% to 10%.
Oscillation frequency = 1/(loge(3)C1(R1 + R2 + R3)) = 50Hz independently of R1 setting

D1 recharges C2 during the PWM on interval.  Z1 limits the output amplitude to TTL-safe levels. And given that LMC555s can be had for about a dollar in singles, I’d say the hoped-for price point box was also checked.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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The post Cheap and cheerful LMC555 RC PWM pulse generator appeared first on EDN.

AI has transformed the semiconductor industry’s pressure points. The conversation is no longer focused solely on designing faster chips. Instead, manufacturers are racing to ensure every part of the supply chain—from silicon wafer production to advanced packaging to global logistics—can support an unprecedented wave of demand.

This shift means evaluating more than process nodes and transistor density. For electronics engineers, supply chain resilience, packaging availability, and manufacturing capacity increasingly influence component selection, product schedules, and long-term design decisions.

AI changing wafer demand

The scale of that demand became clear in the second quarter of 2026, when global silicon wafer shipments reached a record 3,573 million square inches, up 7.4% year over year. AI servers, high-bandwidth memory (HBM), advanced logic, automotive electronics, and industrial semiconductors are all contributing to this wafer demand.

The current cycle differs significantly from previous semiconductor rebounds. After demand being shifted from smartphones or PCs, AI infrastructure is driving simultaneous growth across advanced logic, memory, and power devices.

According to SEMI, AI infrastructure continues to drive demand for leading-edge logic and memory devices, while the rapid expansion of hyperscale data centers is also increasing demand for power management ICs. As industrial markets recover and inventory levels normalize, semiconductor demand is becoming more balanced across multiple end-use sectors.

The impact extends well beyond cloud infrastructure. Consumer devices, such as smartphones and tablets, continue relying on advanced logic and memory, while automotive electronics for ADAS controllers, battery management systems, and zonal computing platforms are consuming larger volumes of semiconductors. Networking switches, 5G base stations, industrial PLCs and robotics controllers are also increasing silicon content, sustaining demand across multiple process nodes rather than only the most advanced technologies.

The broader demand profile has made supply planning more complex for design engineers. While AI accelerators rely on advanced process nodes, many supporting components—including power management ICs (PMICs), microcontrollers (MCUs), connectivity chips, and analog devices—continue to be manufactured on mature nodes. Modern electronic systems depend on both, making balanced capacity expansion critical across the semiconductor ecosystem.

300 mm fabs remain a priority

Silicon remains the primary raw material for manufacturing chips. After being refined into wafers, its electrical properties can be precisely engineered through controlled doping, making it the foundation of the transistors used in AI processors, memory devices, automotive electronics, and countless other semiconductor applications.

The semiconductor industry’s expansion continues to center on 300-mm wafer production because larger wafers enable manufacturers to produce more chips per fabrication cycle, improving throughput and reducing the cost per die. Those efficiencies make 300-mm fabs the preferred choice for advanced logic, memory, and other high-volume semiconductor devices.

That strategy is evident from the recent investments. GlobalWafers is preparing the next phase of expansion at its advanced 300-mm wafer facility in Sherman, Texas, in response to growing customer demand for domestically produced silicon wafers. The plant is the first advanced 300-mm silicon wafer facility built in the United States in over two decades, underscoring broader efforts to strengthen domestic semiconductor supply chains.

Simultaneously, foundries such as TSMC continue expanding advanced fabrication capacity to support AI processors, high-performance computing, and automotive semiconductor demand, highlighting the industry’s broader push to scale leading-edge manufacturing.

For electronics engineers, continued investment in 300-mm manufacturing should improve long-term wafer availability. However, securing leading-edge devices will also increasingly depend on how quickly packaging, testing, and logistics infrastructure expand alongside wafer production.

Logistics becoming the next constraint

Higher wafer output does not automatically translate into higher semiconductor availability. Modern semiconductor manufacturing depends on tightly synchronized movement of raw wafers, specialty gases, ultrapure chemicals, photomasks, lithography equipment, and finished devices across multiple continents. A disruption affecting any stage can slow production despite available fab capacity.

Transportation also introduces reliability challenges. Vibration during shipping can generate electrostatic charge through tribocharging, increasing the risk of electrostatic discharge (ESD) for sensitive semiconductor components if they are not properly protected. As wafer volumes continue rising, ESD-safe packaging and handling become increasingly important to ensure that devices arrive ready for assembly and deployment.

Advanced packaging has become another pressure point. AI processors increasingly rely on chiplets, 2.5D integration, HBM stacks, and sophisticated substrate technologies. Even if wafer fabrication keeps pace, shortages in packaging capacity or substrate availability can delay final product shipments.

Engineers designing products with leading-edge processors should evaluate supply chains beyond wafer availability. Long lead times for advanced substrates or packaging services can delay board assembly completion, even when silicon is available. As a result, packaging partners, OSAT capacity, substrate suppliers, and logistics resilience have become critical considerations alongside device specifications and performance.

Building resilience in future designs

Recent supply chain disruptions have encouraged semiconductor manufacturers to diversify production geographically while increasing regional investments in wafer fabrication, materials, and packaging. Government-backed semiconductor initiatives across North America, Europe, and Asia are helping expand domestic manufacturing ecosystems. These efforts reduce dependence on single-region supply chains while improving resilience against geopolitical and transportation risks.

The implications extend into product architecture. Selecting components with multiple qualified manufacturing sources and maintaining flexibility across process nodes can reduce exposure to future capacity constraints.

The record wafer shipment figures suggest upstream silicon availability is improving. However, transforming those wafers into finished electronic systems increasingly depends on synchronized investments across fabrication, advanced packaging, materials handling, and global logistics.

Keeping pace with growing AI demand will require more than expanding silicon wafer manufacturing. Engineers must also account for packaging capacity, logistics resilience, and supplier readiness throughout the design process.

Emily Newton is editor-in-chief of revolutionized.com.

 

 

 

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• The 300-mm Era Begins
• Inside IBM’s 300-mm fab
• Will 2024 be the year of advanced packaging?
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• One-stop advanced packaging solutions for chiplets

The post Record high wafer shipments. Can fabs keep pace? appeared first on EDN.

Analog and mixed-signal design at sub-5 nm nodes has reached a threshold where deterministic corner-based signoff and brute-force Monte Carlo can no longer simultaneously satisfy convergence speed, tail-yield condense, and engineering interpretability.

This paper examines QUINSIM’s Analog Uncertainty-Aware Design (AUAD) platform—a physics-informed, surrogate-driven uncertainty quantification engine that wraps existing SPICE and TCAD simulators as black boxes.

We characterize the mathematical architecture (sparse polynomial chaos expansion, R-Vine copula process modeling, Sobol variance decomposition, and efficient global optimization), quantify performance across six canonical analog verification benchmarks (SRAM, LNA/VCO, SAR ADC, automotive power IC, TCAD/GAA nanosheet, and timing closure), and analyze the structural transformation AUAD imposes on analog design economics, organizational workflows, and EDA ecosystem dynamics.

We conclude that AUAD is not an incremental acceleration of existing flows; it constitutes a new design epistemology in which uncertainty is a first-class object—characterized, propagated, decomposed, and optimized—rather than a late-cycle verification penalty.

Analog variability crisis at advanced nodes

Analog and mixed-signal design at sub-5 nm nodes has entered a regime where the statistical toolkit inherited from the 1990s—Gaussian corner models and brute-force Monte Carlo—can no longer simultaneously satisfy industrial signoff requirements. Three overlapping crises converge: non-Gaussian process physics, exponentially expensive tail convergence, and opacity of failure attribution. Together they constitute the analog variability crisis, a condition in which the standard toolkit cannot adequately address tail-yield confidence at acceptable engineering cost.

The physics of non-Gaussian variation

Classical statistical IC design rests on a Gaussian assumption inherited from diffusion-dominated transistor physics of the 1980s. In that regime, bulk MOSFET threshold voltage Vth was well-approximated as normally distributed, making a standard deviation σ extracted from wafer data a sufficient design lever. At sub-10 nm nodes, this approximation breaks down for fundamental physical reasons.

Random discrete dopant (RDD) fluctuations produce heavy-tailed, skewed Vth distributions whose kurtosis significantly exceeds the Gaussian value of three. Line-edge roughness (LER) in EUV-patterned FinFET fins creates systematic spatial correlations between adjacent devices that no single-transistor Gaussian model can express. FDSOI back-gate coupling creates strong nonlinear co-dependence between Vth and DVT0W parameters that Gaussian copulas severely underestimate.

The consequence is stark: every PDK σ value that rests on a Gaussian marginal is a physically incorrect model for the circuit’s actual failure space. Corner models compound the problem by treating process parameters as independently varying—an assumption falsified by the correlated etch and deposition physics of modern advanced nodes. A corner labeled “SS” (slow-slow) is a specification convenience, not a probabilistic claim about the failure boundary.

The convergence economics of deep-tail analysis

Monte Carlo convergence follows the 1/√ N law: to halve the estimation error on a yield metric, four times as many simulations are required. For SRAM static noise margin (SNM) qualification at 5σ—the product-level target for leading-edge memory—direct Monte Carlo requires on the order of 107 SPICE evaluations.

At a conservative 3 seconds per simulation on modern hardware, this translates to approximately 347 days of wall-clock compute per circuit per operating corner. Modern SRAM products span multiple corners, temperatures, and supply voltages, multiplying this burden by a factor of 10–50.

The attribution gap

Perhaps the least-discussed failure of conventional flows is epistemic. Monte Carlo can answer “what is the yield?” but not “which parameters are responsible, and by how much?” Answering the latter requires a highly-designed factorial experiment or auxiliary regression—both expensive and approximate.

In a 57-parameter FinFET PDK, attributing yield loss to a specific root cause without attributing yield loss to a specific root cause without analytical sensitivity tools means teams spend weeks on iterative knob-turning that is effectively uninformed trial and error.

This attribution gap directly inflates design cycle time. When the nominal design fails Monte Carlo signoff without variance decomposition, the team must rely on engineering intuition and costly re-simulation campaigns to identify root causes—a process that can consume months at advanced nodes.

Figure 1 In simulation budget comparison, see QUINSIM sPCE (~350 calls) vs. direct Monte Carlo (~10,000 shown; 107 for full 5σ) for a 57-parameter 5 nm FinFET SRAM SNM characterization. Source: QUINSIM

Why corners cannot patch the gap

For uncorrelated Gaussian parameters, an SS corner is geometrically remote from the actual 6σ failure hyperplane in a high-dimensional parameter space. For non-Gaussian parameters with nonlinear correlations, the SS corner may not even represent the worst-case direction—the actual failure mode may lie in a cross-parameter interaction that no PVT corner captures.

AUAD: Architecture and mathematical foundations

QUINSIM’s Analog Uncertainty-Aware Design platform is structured as a four-stage pipeline that treats the existing SPICE or TCAD simulator as an opaque black box—preserving compatibility with Cadence Spectre, Synopsys HSPICE, Mentor Eldo, and Synopsys Sentaurus without modification. As shown in Figure 2, uncertainty inputs are characterized from foundry data; adaptive sampling builds a sparse surrogate; sensitivity and yield surfaces are extracted analytically; and robust optimization acts directly on the uncertainty-aware objective.

Figure 2 In AUAD four-stage pipeline, each stage is analytically connected to the next: foundry data flows through copula characterization into sPCE training, then into zero-cost Sobol decomposition, and finally into EGO-based robust optimization—all without a single additional SPICE call beyond the initial adaptive sample set. Source: QUINSIM

Stage 1: Non-Gaussian joint distribution characterization

Real foundry measurement data for parameters such as Vth, Tox, Leff, and inter-device mismatch do not conform to Gaussian distributions. QUINSIM fits marginals using non-parametric kernel density estimation (KDE) or parametric heavy-tail distributions (Student-t, skew-normal). Joint dependence between parameters is captured using R-vine copulas—pair-copula constructions that model arbitrary bivariate relationships in a recursive tree structure, capturing nonlinear co-dependence that Gaussian or elliptical copulas systematically miss.

The Rosenblatt transformation maps correlated, non-Gaussian samples into independent uniform (then Gaussian) space where Polynomial Chaos Expansion is analytically valid. This is the technical key that makes sPCE applicable to real foundry data with correlated, non-Gaussian parameters, a capability absent from conventional Gaussian-input PCE tools.

Stage 2: Sparse polynomial chaos expansion surrogate

The circuit performance metric Y (SNM, ENOB, NF, efficiency…) is approximated as a polynomial functional of standardised process inputs Z:

Physical sparsity—circuits respond strongly to a small subset of parameters even in 50+ dimensional PDK spaces—combined with active-learning sample placement concentrates 100–500 simulator calls in the regions that maximally reduce surrogate error. The trained surrogate then evaluates in microseconds, enabling post-hoc Monte Carlo with 106–108 samples at negligible additional cost.

Stage 3: Analytical Sobol sensitivity and yield surface extraction

Global sensitivity indices—Sobol first-order and total-effect—are computed analytically from the PCE coefficients at zero additional simulation cost:

Figure 3 Example Sobol-derived metric importance ranking across six performance dimensions (efficiency, output swing, peak current, power factor, THD, EMI) for a power converter design. PF and Eff dominate the variance budget, immediately directing robust design effort to the parameters that matter most. The ranking costs zero additional simulations. Source: QUINSIM

Stage 4: Efficient global optimization (EGO)

With the surrogate trained and sensitivity indices computed, QUINSIM applies efficient global optimization (EGO) to maximize yield over the design parameter space. EGO uses a Kriging (Gaussian process) meta-model of the yield surface together with an expected improvement (EI) acquisition function: EI(x) = E[max(f(x) − f*, 0)]. This Bayesian optimization approach locates yield-maximizing design parameters in fewer than 200 evaluations for 50+ dimensional spaces—unachievable with classical gradient-based methods when the yield surface is non-convex or multimodal.

Benchmark use cases: Demonstrating AUAD impact

QUINSIM has constructed six canonical AUAD benchmarks spanning memory, RF, data conversion, automotive power electronics, and device-level TCAD calibration. These demonstrators collectively define the platform’s technical scope and establish its performance claims against reference instances from published literature and ICCAD benchmarks.

Figure 4 In this 6T SRAM bit-cell schematic at 5-nm FinFET, static noise margin (SNM) and write-margin jointly depend on all six transistors’ Vth, Tox, Leff, and mismatch. QUINSIM’s sPCE characterizes the full 5σ SNM failure surface from 350 adaptive Spectre calls, versus 107 for direct Monte Carlo. Source: QUINSIM

SRAM bit-cell: 5σ SNM in 350 simulations

The canonical AUAD challenge is SNM qualification for 5 nm 6T/8T SRAM. QUINSIM constructs a 57 parameter sPCE surrogate using 350 adaptive Spectre calls, recovers the full SNM probability density function including the 5σ tail, identifies three dominant failure drivers analytically (Tox, Vth_PMOS, Leff), and completes in under 4 hours on standard workstation hardware. The Sobol decomposition reveals Tox alone accounts for 38% of SNM variance—enabling targeted process control recommendations to the foundry that would be invisible to any Monte Carlo approach.

RF LNA/VCO: Capturing bimodal failure distributions

In 28/22 nm FDSOI, QUINSIM employs a Student-t copula to model the Vth–DVT0W co-dependence from back-gate coupling. The result is accurate prediction of a bimodal noise-figure distribution—an artifact of nonlinear coupling that Gaussian-assumption tools miss entirely. QUINSIMʼs design centering identifies a 15% yield improvement and locates the real 6σ worst-case operating point. Multimodal output distributions imply correlated input failure modes that only copula-based process models can resolve.

Figure 5 In FDSOI LNA and the resulting bimodal noise-figure distribution, the back-gate voltage VBG creates nonlinear Vth–DVT0W dependence. QUINSIM’s Student-t copula reveals a second failure mode (Mode 2) that a Gaussian process model misses, a production-impact failure invisible to conventional statistical signoff. Source: QUINSIM

High-speed SAR ADC: 150-parameter ENOB characterization

ENOB degradation in a SAR ADC arises from a correlated combination of capacitor mismatch, comparator offset, jitter, and reference noise. QUINSIMʼs structured high-dimensional sPCE handles 150 correlated parameters from 600 adaptive simulations, delivering the full ENOB probability density function and per-specification tail failure probability in 8 hours.

An equivalent Monte Carlo campaign spanning this 150-parameter space to 6σ confidence would require 3–4 weeks. The surrogate’s full distributional output also exposes ENOB distribution shape—skew, kurtosis, multi-mode structure—that pass/fail counting cannot reveal.

Automotive power IC: Joint process-temperature surrogates

Automotive-grade ICs (AEC-Q100 Grade 0) must operate from −40°C to +175°C. QUINSIM extends the uncertain parameter space to treat temperature as a continuous uncertain dimension, building joint process-temperature surrogates that deliver 100× cost reduction relative to a conventional Monte Carlo × PVT sweep. This is particularly relevant for SiC power stages, gate drivers, current sensors, and high voltage control loops, where tail-yield and reliability must be jointly evaluated across the full operating envelope, not at isolated corners.

TCAD/GAA nanosheet: Bayesian process calibration in 48 hours

TCAD calibration for a new process node currently requires 2–4 weeks of manual deterministic iteration to fit compact model parameters (BSIM-CMG, PSP) to measured I-V characteristics. QUINSIMʼs Bayesian calibration engine applies active learning to TCAD simulation scheduling, fits a posterior distribution over the full set of physical model parameters rather than a point estimate, and propagates that posterior uncertainty through the compact model extraction chain into a UQ-aware PDK (UQ-PDK). The result: 48-hour calibration cycles with honest uncertainty bounds on every PDK parameter.

Capabilities unlocked by AUAD

Beyond benchmark-level performance numbers, AUAD unlocks capabilities that are qualitatively unavailable within the Monte Carlo paradigm regardless of the compute budget applied.

Analytical variance budget decomposition

For a 57-parameter PDK space, conventional Monte Carlo can determine that yield is 97.2%—but not which parameters explain the 2.8% failure variance. QUINSIMʼs Sobol decomposition provides a ranked list of first-order and total-effect indices for every process parameter, computed analytically from sPCE coefficients at zero simulation cost. This transforms failure analysis from “simulate more” to “fix these three parameters in this priority order.”

Full probability density output instead of pass/fail counting

Surrogate-based UQ produces the full PDF of any circuit metric as a live design object. For a SAR ADC, this means designers see not just “mean ENOB = 11.2 bits, σ = 0.15 bits” but the complete distributional shape—whether it’s symmetric, heavy-tailed, or bimodal. This changes specification verification from a Gaussian-approximation exercise to a physics-honest probability assessment.

Robust design centering and optimization via EGO

EGO-based robust optimization acts on the yield surface, not the nominal performance surface. A design point that is optimal in nominal performance may sit on a steep yield cliff; a slightly sub-optimal nominal design may command a wide, flat yield basin. AUAD makes this trade-off visible and optimizable: in the FDSOI LNA benchmark, EGO-guided centering recovered 15% yield improvement that was invisible to nominal optimization. In timing-closure benchmarks, robust optimization produced higher shipping frequency with tighter but better-justified margins than guard-banding.

Partner-ready traceability and auditability

QUINSIMʼs analytical UQ framework produces structured, reproducible outputs: specific PCE coefficients, Sobol index tables, yield surface plots, failure-mode rankings—all derived from a documented mathematical procedure. For foundry partnerships, IP qualification packages, and AEC-Q100 automotive compliance dossiers, auditability of the statistical analysis is increasingly a contractual requirement. AUADʼs analytical traceability directly satisfies this requirement in a way that a random-seed-dependent Monte Carlo run cannot.

The irreversible transformation of analog IC design

AUAD is not a feature addition to existing EDA flows. It constitutes a structural transformation of how analog design decisions are made, justified, and communicated. Once a design team inhabits an environment where uncertainty is analytically characterized and continuously actionable, the prior workflow—simulate, margin, and iterate—becomes evidently inferior and institutionally difficult to defend.

From “simulate and margin” to “characterize, rank, optimize, explain”

The existing design-verification loop treats Monte Carlo as a late-stage checksum applied after nominal design completion. When the gate fails, the team iterates blindly without analytical guidance. In an AUAD workflow, the uncertainty model is active from the first design iteration: parameters are characterized from foundry data, the surrogate is trained after 100–500 simulation calls, and Sobol rankings immediately direct design effort. The loop compresses from months to days not because the simulator runs faster, but because engineering judgment is guided by quantitative attribution rather than intuition.

Figure 6 In traditional simulation-centric design loop (red) vs. AUAD design loop (blue/green), the structural difference is that AUAD delivers actionable attribution at every stage. Where the traditional loop requires months of blind re-simulation on signoff failure, AUAD’s Sobol-guided EGO reaches tape-out readiness in days. Source: QUINSIM

Economic consequences for design organizations

The commercial implications of a 1000× simulation reduction extend beyond throughput. Fewer SPICE simulations mean fewer licensed EDA seat-hours consumed, directly reducing the variable cost of advanced-node verification.

Faster yield diagnosis compresses design cycles currently measured in 18-24 months for leading-edge analog. Better yield prediction reduces unnecessary margin padding, and in volume production, even 1–2% yield recovery at advanced nodes translates to tens of millions of dollars in recaptured wafer value per year. QUINSIM positions these not as incremental improvements but as step-function changes in the economics of analog design.

EDA ecosystem dynamics: The intelligence layer

QUINSIMʼs black-box simulator wrapper positions it as an intelligence layer on top of, not in competition with, the SPICE simulation cores of Cadence, Synopsys, and Siemens EDA. Incumbents can embed the UQ engine as a differentiated variation-analysis module without displacing their core circuit simulation products. The roadmap QUINSIM publishes explicitly names a “Cloud SaaS, UQ-PDK marketplace” and positions the platform as an acquisition target in the €100–200M range—a signal of deliberate ecosystem positioning rather than standalone scaling.

Foundries and IP providers face an analogous opportunity. A UQ-PDK that exposes calibrated non-Gaussian marginals, copula dependence models, and Bayesian parameter posteriors is qualitatively richer than a conventional σ-table, enabling customers to achieve better first-silicon yield with fewer iterations—a tangible competitive differentiator in a market where design starts are competed on tool quality.

The transformation is irreversible

The historical pattern in EDA adoption suggests that once a design team experiences analytical yield attribution—knowing which parameters are responsible for yield loss and by how much, derivable in hours—returning to uninformed Monte Carlo iteration is institutionally unacceptable. The same dynamic played out when formal verification replaced simulation-only digital signoff, and when place-and-route tools supplanted manual floorplanning.

AUAD represents the analog equivalent of that transition: a shift from a compute-intensive empirical paradigm to a mathematically structured, interpretable, and continuously optimizable uncertainty framework.

The chips shipping in 2029 and beyond will be designed by teams who characterize, rank, optimize, and explain the uncertainty in their analog blocks from the first simulation run. Those teams will converge faster, yield higher, and signoff with tail-probability confidence that today’s Monte Carlo paradigm can not match. QUINSIM AUAD is the platform enabling this transition today.

Christophe Bianchi is CEO and founder of QUINSIM.

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The post Analog uncertainty-aware design: How it replaces Monte Carlo with certifiable yield intelligence appeared first on EDN.

A novel switch architecture caters to extended battery range coupled with robust protection and diagnostic strategies.

For automotive control units, the smart output switches operating contactor coils, lamps, solenoids, PTC (positive temperature coefficient) heater coils and the like form an indispensable “last mile” interface to the external world. Legacy solutions available from global automotive semiconductor companies suffer from the following weaknesses:

• No off-the-shelf power switch IC is currently available beyond 24 volts, whereas upcoming vehicle architectures are envisioning 48 VDC or higher buses to reduce the weight of associated copper wiring.
• They consume a minimum of two interface CPU pins per switch; one for the command output and another for the status input.
• “Short to power bus” protection is based on current limiting followed by a thermal trip, in the process often exceeding the absolute maximum junction temperature prior to the actual tripping event.
• The on-chip power device often has limited overvoltage and inductive transient capabilities, requiring external protection components.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The circuit in Figure 1 illustrates a solution that resolves all of these issues.

Figure 1 This design idea is primarily intended to depict a novel switch architecture that can cater to extended battery range coupled with robust protection and diagnostic strategies. It also uses only a single CPU pin-per-switch, as opposed to two CPU pins for legacy architectures. The load coil can be typically rated as a 48V DC, 122 mA contactor coil used for EV/HEV circuits for a 48 volt bus. A typical 12 volt automotive relay coil may draw 95 mA, while a 24 volt version can draw approximately 68 mA.

In this example circuit:

• Q1 = MMBTA 92-q
• Q2 = 2N2222
• Q3 = MMBTA 42-q
• D1,D2 = 1N4004
• D3 = 1N4148
• R1 = 47K ohm
• R2,R3 = 47K ohm
• R4 = 2.2 ohm
• R5 = 10K ohm
• R6 = 1K ohm
• C1 = C2 = 0.1 microfarad, 25 volts

The selection of components, resistor values etc. may need to be tailored to address the expected range of application loads, along with CPU and other logic voltage/current characteristics.

The heart of the circuit is the Q1-plus-Q3 latch. Q2 acts as constant current limit that prevents momentary thermal runaway that would otherwise destroy Q1 during a “short to power bus” event. In automotive application, a service engineer or production technician might accidentally short-circuit the output point (Q1 collector) to the power bus. Automotive norms dictate that the power switch must incorporate built-in short circuit protection to cover this and other scenarios.

When the CPU wants to switch on the load, it issues a rising-edge command through the C1-plus-R1 edge trigger circuit to the Q1-plus-Q3 latch. This command sets the latch output to its active low level, thus turning on the contactor coil load. The CPU pin can now reconfigure itself as a diagnostic status input, since the Q1-plus-Q3 latch now self-sustains at the “on” state without needing any further base current assistance from the CPU. The CPU pin, now acting as a diagnostic input, reads a “logic high status”, indicating that the latch output is healthy and powering the load as intended.

In case of an accidental short to power-bus event—in other words, the load coil facing a short circuit across itself—Q3 being a PNP transistor switches off due to its base emitter circuit in effect getting short-circuited (Figure 2). This “resets” the latch by turning off Q1, also saving it from the over-current condition.

Figure 2 This short-circuit protection field performance plot of the circuit shows its near-instantaneous trip mechanism for the output switch, which resets the associated latch.

Transistor Q2 limits the momentary rise in Q1 current at the short-circuit instant to a value of around 318 mA (700 mV/2.2 ohms). This abrupt current limit saves Q1 from destruction due to a thermal runaway before Q3 transistor’s turn-off can safely place it in an “off” state. The CPU diagnostic status input pin now reads a “logic low” level indicating that the latch is turned off, due to a short circuit fault at the output. Capacitor C2 provides ESD protection, along with noise interference filtering that may accidentally operate the latch.

Whenever the CPU needs to issue a turn-off command to a latched switch which is in an “on” state, it presents a logic low level at its output interface pin. This low-level voltage turns off the latch through diode D1. Diode D6 and resistor R1 suppress the inductive flyback transient. Diode D1 may be replaced by a suitable Schottky diode to ensure a robust turn-off of the latched switch.

Unlike legacy smart switch solutions, this circuit does not depend on thermal trip-based protection, hence its junction temperature remains absolutely stable. At the time of a short circuit, there will be an instantaneous current-limited spike. The architecture unburdens software from repeatedly monitoring and turning off the smart switch for short-circuit protection (in order to ensure a safe turn-off even before a thermal trip) as may be required for a legacy switch architecture. It instead repartitions the instant short-circuit protection task to the hardware trip circuit, leaving software to monitor and detect the the short-circuit event on an as-possible basis without worry about any real-time protection deadlines.

The circuit can alternatively be implemented in integrated circuit (IC) form, at least to a degree. A power switch element may alternatively be located at and connected to the IC from the outside if it can’t be packaged within the chip, which can still integrate the remainder of the low current driving, protection and diagnostic logic.

Vishwas Vaidya is a graduate of the Indian Institute of Technology in Delhi, India. Currently, he is self-employed as an engineering consultant and industry faculty member in the field of embedded systems for global automotive clients and high-repute academic institutions. Vishwas’ articles and research reports have appeared in many worldwide engineering publications.

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Predictive, generative, and agentic AI are not successive generations. They coexist inside enterprise systems, each placing fundamentally different demands on the underlying compute infrastructure.

• Predictive AI classifies, forecasts, and detects within defined boundaries (for instance, identifying a tumor or detecting fraud). GPUs and fixed-function accelerators handle these bounded workloads efficiently.
• Generative AI broadened this scope to text, code, and reasoning. Processor designers responded with a race for floating-point throughput, memory bandwidth, and high-speed interconnects under the assumption that inference was relatively simple: accept a prompt, run the model, and emit tokens.
• Agentic AI breaks that model-centric paradigm. A single task is partitioned among cooperating agents—one retrieves data, another analyzes it, a third writes code, and a fourth verifies policy compliance. The workload shifts from pure matrix multiplication to planning, branching, scheduling, synchronization, and repeated tool execution.
• Enterprise AI applies predictive, generative, and agentic capabilities to real-world business problems using proprietary data, strict access controls, and strict governance. It’s not merely a larger version of consumer generative AI; it is a distinct operating environment that fundamentally reshapes system architecture.

The enterprise context layer

A consumer chatbot relies primarily on pretraining weight memory and optional web search. An enterprise system must operate against information absent from pretraining: engineering specifications, financial ledgers, manufacturing logs, code repositories, and regulatory filings. It must simultaneously enforce who is authorized to see that information, which actions are permitted, and how the interaction is logged for audit.

To accomplish this, enterprise systems combine foundation models with retrieval-augmented generation (RAG), vector databases, knowledge graphs, identity management, policy engines, and workflow orchestration. Collectively, this forms an enterprise context layer, an architectural abstraction whose role is to retrieve relevant organizational knowledge, apply access rules, and ground model output in current operational facts.

An AI software stack is used to manage AI enterprise workloads and reshape AI system architectures. Source: Author

As a result, the question moves from “What does the model know?” to “What does the organization know, what is relevant to this task, and what is this user authorized to execute?“ This shift marks the transition from Inference 1.0 to Inference 2.0.

Comparing the differences between model-centric inference versus workload-centric inference illustrates the transition from Inference 1.0 to Inference 2.0. Source: Author

Consider an engineer at an automotive semiconductor company asking: “Which version of our Ethernet controller complies with ISO 26262 ASIL-D, and does it meet our latest customer requirements?”

The answer does not exist in a single model’s weights. Before reasoning begins, the system must perform vector searches across document management platforms, query a failure modes and effects (FMEDA) database, inspect product lifecycle management (PLM) systems, check source-code repositories, and parse customer change requests. Conventional software services, policy checkers, and foundation models then analyze compliance evidence and flag inconsistencies before an orchestration layer assembles a defensible response.

One query triggers multiple database accesses, security validations, model invocations, and tool executions. Inference is no longer a single forward pass; it’s an orchestrated, multi-domain workflow.

Redefining performance: “Time to a useful answer”

Inference 2.0 alters the practical definition of performance. Model training is throughput-driven, running parallel jobs across thousands of accelerators for weeks. Enterprise users, by contrast, demand rapid, context-accurate responses. A physician reviewing an urgent diagnostic report or an engineer analyzing a production fault cannot benefit from peak token throughput if the system spends seconds waiting on database queries, context loading, or security authorization.

If platform A generates tokens twice as fast as platform B, but platform B retrieves corporate context and coordinates agents with far less overhead, platform B will deliver the end result faster. The meaningful system metric becomes time to a useful answer.

In an enterprise environment, “useful” is strictly constrained by three factors:

1. Correctness: Output meets application-specific domain quality thresholds.
2. Authorization: Access and security rules are strictly enforced.
3. Traceability: Intermediate reasoning steps and supporting evidence are preserved for auditing.

Hardware and system-level bottlenecks

Accelerating matrix multiplication alone yields diminishing returns when non-tensor tasks dominate overall execution time (Amdahl’s Law). Inference 2.0 shifts bottlenecks to working memory management and systemic data movement.

Managing shared working context (KV cache)

LLM inference decode is inherently memory-bound: hardware spends more time moving weights and key-value (KV) cache tensors than performing math. Agentic workflows amplify this problem. A single agent request can fan out into dozens of model calls that share identical system prompts, tool definitions, governance rules, and retrieved context.

Reprocessing this common prefix on every call wastes compute and introduces massive latency. So, systems must implement advanced memory management strategies:

• Paged attention and virtual memory (for instance, vLLM): Allocating KV cache dynamically in non-contiguous memory blocks eliminates internal fragmentation and enables efficient prefix sharing across multiple parallel agents.
• Radix tree prefix caching: Retaining prompt prefixes, system policies, and retrieved documents in memory across requests allows intermediate calls to skip the prefill stage entirely.
• Speculative decoding: Leveraging smaller draft models to propose tokens while using large foundation models for verification reduces latency and conserves high-bandwidth memory (HBM) capacity. As context windows extend to millions of tokens, managing the KV cache hierarchy—deciding what stays in HBM, what offloads to system DDR5, and what gets evicted—becomes as critical to system capacity as peak FLOPS.

Interconnects, DPUs, and heterogeneous memory

Moving data across storage, host memory, and accelerators represents the primary energy and latency penalty in Inference 2.0. Addressing this requires moving beyond traditional PCIe topologies:

• Compute Express Link (CXL): It enables cache-coherent memory sharing and expansion between CPUs, accelerators, and pooled memory devices. By allowing accelerators to access main system memory or shared pools without traditional host-copy overhead, CXL eases HBM capacity pressure during massive multi-agent context retention.
• Data processing units (DPUs) and smart NICs: Offloading line-rate security filtering, identity checks, data encryption, and network serialization to DPUs frees host CPUs and GPUs to focus strictly on orchestration and tensor workloads.
• High-speed scale-Up fabrics: Technologies such as NVLink or Ultra Accelerator Link (UALink) are increasingly vital not just for model parallelism during training, but for rapid KV cache migration and intermediate state transfer between heterogeneous accelerators during inference routing.

The runtime and system orchestration challenge

Inference 2.0 requires the system runtime to act as a distributed resource manager:

• Heterogeneous scheduling: Runtimes must dynamically partition tasks—routing vector searches to specialized vector engines or CPUs, scheduling dense linear algebra on GPUs/ASICs, and executing policy checks on host cores.
• Multi-model serving and isolation: Enterprise runtimes must serve large foundation reasoning models concurrently with smaller, fine-tuned domain models. This demands strict spatial and temporal isolation to prevent low-priority background tasks from degrading real-time user requests.
• Network latency in the compute path: In training, networks synchronize gradient tensors across worker nodes. In Inference 2.0, the network carries prompts, embeddings, RAG chunks, tool outputs, and agent states directly in the critical path. Network latency directly translates to user-perceived response time.

Evolving benchmarks: Measuring what actually matters

Traditional benchmarks like MLPerf inference excel at isolating raw accelerator capability (for example, batch-1 token latency or offline throughput). However, they fail to capture retrieval delay, context switching overhead, network transport, security enforcement, or multi-agent orchestration.

Just as database evaluation evolved from raw CPU clock speeds to holistic transaction benchmarks (like TPC-C and TPC-H), AI benchmarking must evolve to evaluate complete enterprise workflows.

The Inference 2.0 benchmark suite concept

An enterprise-grade benchmark suite should evaluate system performance across realistic operational profiles:

1. End-to-end task completion time: Total elapsed time from initial query input to a fully formatted, authorized response.
2. Context reuse efficiency index: Measures how effectively a system reuses KV cache across multi-turn agentic fan-outs without re-executing prefill phases.
3. Traceability and audit overhead: Evaluates system degradation when capturing complete chain-of-thought, tool invocation, and data provenance logs required for enterprise compliance.
4. Mixed-workload quality-of-service (QoS): Tail-latency (p99) performance when running concurrent workloads (for instance, background vector indexing alongside interactive multi-agent reasoning). Quality and correctness must be reported alongside execution time to ensure speed is never prioritized at the expense of accuracy or security.

Beyond GPU: Building balanced AI systems

Matrix multiplication will remain a core computational requirement, and GPUs will continue to play a central role in AI infrastructure. Modern GPUs have evolved significantly, incorporating lower-precision formats, sparsity support, larger memory footprints, and advanced inference runtimes.

However, accelerating tensor execution alone is no longer sufficient when an increasing fraction of system time and energy is consumed by data movement, context management, network transport, and security validation.

The leading platforms of the Inference 2.0 era will be those engineered for system-level balance. Whether centered on GPUs, specialized ASICs, dynamic CPU-accelerator clusters, or CXL-enabled memory pools, the winning architectures will be judged on a single unified criterion: how efficiently the complete system transforms organizational knowledge into trusted, actionable decisions.

That is the architectural imperative of Inference 2.0.

Lauro Rizzatti is a business development executive with VSORA, a technology company offering silicon semiconductor solutions that aim to redefine silicon performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

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The post Inference 2.0: How enterprise AI is reshaping AI system architectures appeared first on EDN.

It’s not uncommon for a midsection to become soft and distended with advancing age. That said, when it happens to a battery, it’s potentially quite problematic.

In last week’s part 1, I took apart a third-party BLX-1 battery which had come with my Olympus (now OM System) OM-1 digital camera and which the manufacturer’s own BCX-1 charger refused to recognize as a valid recharge partner. Also recently augmenting my burgeoning gear inventory are two enthusiast-prized Olympus PEN-F Micro Four Thirds bodies (once again digital, not the film-based precursor), one in each color option offered by the manufacturer a decade ago when they were new.

Each came with a third-party BLN-1 battery (7.6 V, 1220 mAh). Supplier names differed but their physical appearances were identical, therefore suggestive of a common manufacturing source. I’ll be taking them both apart today to test my hypothesis. But why am I dissecting them at all?

Unlike the BLX-1, they seemingly still work fine, but they both arrived slightly swollen, with further distension likely after additional use and recharge cycles. The last thing I want is for an inexpensive, replaceable cell to end up permanently lodged in the battery compartment of an expensive, irreplaceable camera, so retirement and replacement was a priority for both!

Trust me when I say that all the cameras showcased in this two-part series are Micro Four Thirds models, Olympus-now-OM System to boot, is only a coincidence. I’ve had no shortage of mixed-at-best success in the past with third-party batteries for other manufacturers’ cameras, too.

Some Wasabi with your sushi?

I randomly picked the one from Wasabi Power, a common “clone” cell supplier, to disassemble first. As usual, I’ll start with some overview shots, accompanied by a 0.75′′ (19.1 mm) diameter U.S. penny for size comparison purposes. Top.

Bottom.

Four of the BLN-1 contacts—”+”, “-“, “I” and “T”—are marked the same (albeit in different ordering) as with the BLX-1. As I mentioned last time, published specifications for batteries like these are hard-to-impossible to come by, given that for various reasons the camera manufacturer doesn’t want to encourage third-party cloning.

That said, once again the functions of “+” and “-“ are likely related to the applied voltage and current involved in the fundamental cell-charging and -discharging (for camera powering) functions. “I”, typically standing for “information” or “identification”, references the interrogation initially done by both charger and camera after battery insertion and power-on, and ongoing from that point on, presumably implemented by a bidirectional single-data-pin serial communications protocol of some sort.

“T” typically references “temperature”, with the contact connected to an embedded negative temperature coefficient (NTC) thermistor or other sensor that monitors the internal cell(s) and alerts the charger to potential overheating. And this time there’s a fifth electrical contact, “S”. User research suggests that it was added in response to Japanese standards body guideline revisions that mandated a fuller shut-off of the accompanying charger after the battery reported it was “full”, thereby minimizing subsequent “vampire” power draw.

The BLX-1 battery disassembled in part 1 of this series is significantly newer in generation than the BLN-1 and presumably integrates this function along with others already supported over the “I” interface, thereby negating the ongoing need for a dedicated “S” contact.

Onward, redux. Once again, the other end is much less exciting, as are the sides.

Ongoing unexciting-dissection aspirations

And once again, a Sirens-like tempting, albeit ultrasonic-welded, seam around the battery’s circumference seems to be the most feasible pathway inside, the potential for sparks, smoke, flame, and other calamities aside. Danger, Will Robinson!

Phew!

This time, the batteries’ form factors aren’t cylindrical and plastic-covered as before, but rectangular and metallic; niftily-named prismatic, to be exact. Once again throwing caution to the wind, I pressed forward determinedly (albeit cautiously) with the disassembly.

Rubber strips again, this time tape- and paper-accompanied, to insulate the mini-PCB from the batteries’ terminals both mechanically and electrically.

Enough with the teasing; I know this is what you’re most interested in seeing, right?

The design is much more elementary than with the BLX-1 circuit board we saw in part 1. The eight-lead IC PCB-labeled as U2 is stamped as follows on top, below a cryptic company logo.

8822
E6H01

It’s another dual N-channel MOSFET. And then there’s six-lead U1 to its right, marked as follows.

CGKU

As with the BLX-1, per an earlier-referenced discussion, I’m guessing it’s a rudimentary battery-protection IC. Apparently recharge-balancing the two cells isn’t of concern in this specific case.

Speaking of which, let’s take a closer look at the markings on the two cells’ prismatic cases, which you’ve already glimpsed in prior images.

They match each other, and I suspect the last eight characters of each reference a September 2016 manufacturing date. Nearing 10 years old, I’m willing to forgive a bit of old-age swelling, no matter that it obviates any further use (that I’m comfortable taking a chance on, at least). No voltage or capacity specs; that said, I suspect they’re the relatively common 4.2 V (3.7 V nominal) variant in a serial-interconnect topology.

Testing a common-sourcing hypothesis

Now for its Newmowa-branded counterpart (is that a clever company logo, or what?), complete with scribbling on top from its prior owner (who apparently, like me, is also blessed to own a diversity of camera hardware models from various manufacturers, and needs to keep his batteries straight).

Trust me when I say that had I decided to keep the battery in service, cleaning off those contacts would have been my very next step!

Once more unto the breach, dear friends.

This time, interestingly, both cells’ cases are completely marking-free on both sides.

Although the means by which the cells are adhesively bonded both to each other and to the surrounding halves of the enclosure differ, there’s visually obvious commonality with respect to the respective mini-PCB layouts.

That said, the components are seemingly divergent from a sourcing standpoint (albeit functionally identical, at least likely). Here’s what’s atop eight-lead U2 this time:

SNE
5N20V
7H09 (don’t quote me on the accuracy of this last line; it’s pretty fuzzy)

Once again, it’s a dual N-channel power MOSFET. And six-lead IC U1 to its right? Again, don’t quote me definitively, but here’s my best shot post-cleanup with rubbing alcohol.

20DD
L607

And with that, after wrapping up all four cells (two from each of the two batteries) in insulating masking tape to ensure safe storage until after my writeup is published.

I’ll also wrap up for today. Shout out with your thoughts in the comments, please!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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