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New smart phones, earbuds and watches, this year with an added dash of memory price increases. It’s September in Cupertino again.

September 1 was Tim Cook’s last day as Apple’s CEO, after a 15-year tenure with that title. Hereafter he’ll be Executive Chairman of the board of directors, succeeded as CEO by John Ternus, former senior vice president of Hardware Engineering. And reflective of the changing of the guard, Cook was nowhere to be seen in this morning’s prerecorded launch event video, albeit in a brief cameo at the beginning.

Not because, I suspect, Cook’s got anything against product launches, although after having fronted so many of them by now, he’d certainly be entitled to a bit of burnout. Instead, I’m guessing he just wanted to make the passing of the baton as clean and obvious as possible.

Just like last year…and the year before it…and…Apple launched new and updated wearable and broader mobile products in September 2026 (which, I’ll note, has just started, so we might not be done with the month yet, far from the rest of the year). The biggest surprise this time around was that today’s unveilings weren’t the first in this year’s late-summer sequence, having been preceded by the release of new M-series SoCs and systems containing them late last month.

And speaking of M-series SoCs, there’s as-usual no shortage of commonality between those earlier latest-generation application processors for computers and high-end tablets and the one(s?) that rolled out today for high-end iPhones. Speaking of which…

The iPhone 18 Pro series

What do you do if rising DRAM and flash memory costs are clobbering your products’ bill-of-materials budgets? You focus your new-product energy on the stuff that’s most profitable already. And you do something else…which I’ll share in a minute. New stuff first. There’s no mainstream iPhone 18 yet, for the first time ever. But the high-end iPhone 18 Pro and Pro Max are here. And they’re priced $100 higher than were their forebears of similar memory capacities, along with adding an even higher-end (and higher-priced) 2 Tbyte storage tier.

That new SoC? It’s the A20 Pro. First-time 2 nm-fabricated by foundry partner TSMC. 50% higher memory bandwidth than the A19 Pro. Faster CPU (6 cores total, 2 “super” and 4 “efficiency) and GPU (seven cores total) subsystems than those in the A19 Pro. And a dual 16-core Neural Engine inference subsystem. Lessee…where have we heard this same messaging…two weeks ago, to be exact? Yessiree, it seems that once again there’s no shortage of shared DNA between the late-August M6 and today’s A20 Pro SoCs, albeit with varying dollops of various on-die resources, befitting varying platform cost, feature and performance requirements.

What I’m admittedly most excited about as an unabashed photography geek is the camera subsystem’s variable aperture (along with, by association, manual shutter speed setting) support for the rear main unit.

Yes, it enables more meaningful user control of exposure, particularly in low light environments (adjusting for bright-light settings can always alternatively be done via integrated or external neutral density filters, of course). But it also first-time affords user adjustment of depth of field, allowing for both shallow-depth “bokeh” effects and sharpness across a wider depth range than possible before.

Oh, and by the way…even though Apple delayed releasing the mainstream iPhone 18 (which, in saying so, I’m obviously assuming is still coming eventually), the company still found another way to use our credit cards and bank accounts as counterbalance to the higher semiconductor-content costs it was incurring. The iPhone 17 Pro and Pro Max are no more, of course. But the company’s still selling the baseline iPhone 17 and 16, the boutique iPhone Air, and the “cost-effective” (relatively speaking, at least) iPhone 17e. That said, post-Apple Store resurrection mid-day today, they all now cost $100 more than they did yesterday. Yay…???

The AirPods 5

Two years ago this same month, Apple released the 4th-generation AirPods in two flavors, $129 with only passive noise reduction (PNR, and not great, at that, given their imperfect ear-shape seal for many users), and $50 more for an active noise control (ANC)-supportive model. I’d love to see the comparative sales stat results between the two variants, but clearly the world has moved en masse to ANC since then.

To wit, Apple’s fifth-generation AirPods successors have dropped the PNR option, but the company’s marketeers can’t seem to quit the price-differentiation shtick completely. Want a conventional wired-charging case? That’ll cost you $129. How about a wireless charging-capable case option? $20 more, please. Maybe two years from now, Apple Marketing will realize that the world’s already moved en masse to Qi…oh, sorry, this is Apple…MagSafe…too. Wonder how they’ll try to extract more money out of our wallets next time? Reader prognostications are as-always welcomed in the comments!

Apple Watch Series 12 and Watch Ultra 4

Three key takeaways distinguish this year’s mainstream and high-end smartwatches from their prior years’ versions:

• An upgraded S11 processor, whose specifics were as-usual not revealed but likely include a sprinkle (or few) of deep learning inference acceleration, reflected in…
• AI as a first-time notable element in Apple’s smartwatch pitch this time, particularly focusing on ambient audio processing capabilities (including conversations, although Apple predictably maintains its “privacy by design” reassurance mantra) and thanks in no small part to a recently unveiled partnership with Google that has seemingly finally gotten Siri on track for something other than corporate embarrassment, and…
• The other notable AI-analyzed data set, an enhanced health sensor suite enabling, among other things, continues heart rate monitoring every five seconds, all day.

This year’s models are identically priced to their generational predecessors, surprisingly, although around 24 hours ago, I’d wondered if Apple was going to deal with its burgeoning semiconductor memory bill-of-materials burden in a different way. Beginning some time yesterday and continuing for quite a while, although subsequently corrected, the company’s entry-level Apple Watch SE 3 models all became “unavailable” for purchase.

Apple typically takes its online store down a few hours ahead of launch events to make the necessary tweaks in preparation and out of the public eye, but this was unprecedented. I’d wondered if Apple was planning on dropping the whole line, either because it wasn’t AI-capable and/or because memory cost increases had rendered it insufficiently profitable, and if someone had “pulled the plug” prematurely and highly visibly. But given that the Watch Series 3 had just been unveiled a year ago, the “yank” seemed premature. As, it turned out, it was. Maybe. Then again, maybe someone just decided to do a last-minute course-change. We’ll likely never know.

Back to the future

I guess John Ternus thought that instead of charting his own course, he’d use his first launch event to “channel” a predecessor’s past glory. Yes, he pulled out the memory closet a Steve Jobs “chestnut”, the “one more thing”. And of course, it was one of the worst kept secrets of recent Apple corporate strategy: the foldable iPhone. Although at least one thing was surprising about it: industry scuttlebutt had long branded it the “iPhone Ultra”, but instead it’s the “iPhone Duo”. Begging the question of what, if anything, the “iPhone Ultra” will be…but I digress.

It’s $1999 (and up, capacity-dependent). It won’t be available until next month (October). And like its iPhone 19 Pro siblings, it’s based on the A20 Pro Soc. But I don’t want to spend my precious few remaining paragraphs in this section talking about that. Instead, I want to talk about aspect ratios. Let’s start with my long beloved, in spite of chronic software bugs, Microsoft Surface Duo, an example of which still inhabits my storage closet in the hopes that someone will someday release a stable, robust-featured, reasonably current Android build for it or…dare I dream…Windows 11 for Arm with Wi-Fi and cellular data support? Be still my heart.

Yes, it was foldable. But no, unlike the iPhone Fold it wasn’t comprised of a single piece of bendable OLED internal “glass”. Instead, there was that jarring hinge in-between the two internal displays. And there was no external screen, either, so you had to unfold it to use it at all, even for basic smartphone tasks. But again, I digress. Look at its aspect ratio. Unfold it and, without rotating it 90°, you had a 7.36” wide by 5.72” tall screen (yes, I know, with a gap in the middle) perfect for reading eBooks in a style akin to that of actual books, watching movies, and the like.

Next, let’s look at the first-generation (2023) Google Pixel Fold, an example of which my wife bought me for my birthday earlier this year.

Same fundamental aspect ratio, this time with an added bonus: no midway gap. And this time, there was a third outer display, too.

But given overall system form factor dimensions, it was atypical in both size (5.8” diagonal) and (especially) aspect ratio in comparison to the ones in conventional smartphones. Atypical equals low volume. Low volume equals costly and supplier-option deficiency. All of which explains why second and subsequent-generation Pixel Folds have switched to “bifolds”, taller than before, albeit losing the unfolded “book” (or, if you prefer, movie screen) form factor in the process.

Now look at the iPhone Fold again. The “book” form factor is back (in black, aka “night sky”, as well as “star white”)!

Apple perhaps obviously has supplier leverage that Google doesn’t (or at least didn’t) have, so assuming customers buy into the design decision, I suspect it’ll play out better this time around. Agree or disagree, readers? Let me know your thoughts on this or anything else I’ve discussed here, in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• Microsoft’s Surface Duo: A software evolution testimonial, but for who?

The post The Microsoft-reminiscent iPhone Duo: How much customer holding-and-folding is necessary to keep Apple from folding on the experiment? appeared first on EDN.

Altera now provides post-quantum cryptography (PQC) support for Agilex 3 and Agilex 5 FPGAs, helping strengthen system security. The FPGAs’ reprogrammable architecture enables designs to evolve as new threats emerge and security requirements and cryptographic standards change. The devices form a scalable platform for embedded and edge applications by combining performance and power efficiency.

PQC-enabled secure boot authenticates trusted device configurations while protecting long-life systems against future quantum-era threats. A Secure Device Manager (SDM) provides additional security capabilities, including bitstream encryption for IP, physical anti-tamper support, key management, physically unclonable function (PUF) keys, embedded cryptographic cores, and platform attestation.

The PQC-enabled Agilex 3 and Agilex 5 devices are shipping today. Quartus Prime Pro Edition 26.1.1 includes a PQC software flow that simplifies implementation of post-quantum security protections.

Agilex 3 product page

Agilex 5 product page

Altera

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Two 600-V MOSFETs from AOS come in top-side-cooled packages with co-optimized electrical and thermal paths to maximize power density. The AOGT037V60DE2 and AOGT060V60DE2 αMOS E2 Super Junction MOSFETs feature a built-in fast body diode for enhanced robustness and reduced Qrr in high-stress applications.

The AOGT037V60DE2 has a maximum RDS(ON) of 37 mΩ and typical Qg of 146 nC, both at a VGS of 10 V. For the AOGT060V60DE2, the corresponding ratings are 60 mΩ and 85 nC under the same conditions. Both devices provide strong avalanche capability and in-rush current handling with a wide safe operating area (SOA).

AOS combines the αMOS E2 silicon with its GTPAK package to improve thermal performance through a top-side cooling pad, while gull-wing leads enhance board-level reliability. The MOSFETs are designed to prevent self-turn-on for reliable operation under dynamic conditions. Typical applications include rectifiers, solar inverters, motor drives, and industrial power systems using boost PFC, totem-pole PFC, LLC resonant, PSFB, and cyclo-converter topologies.

The AOGT037V60DE2 (600 V, 37 mΩ) and AOGT060V60DE2 (600 V, 60 mΩ) are now available in production quantities with a lead time of 16 weeks. Respective prices are $6 and $3 in quantities of 1000 units.

Alpha & Omega Semiconductor

The post AOS boosts power density with 600-V MOSFETs appeared first on EDN.

A SerDes chipset from EverProX, under its Silicon Line brand, aggregates two simultaneous MIPI D-PHY camera streams, each at up to 10 Gbps, over serialized links. As the first entry in the Silicon Line MIPI Serial Data Link (MSDL) family, the MSDL 20G dual-port chipset extends MIPI D-PHY connectivity to tens of meters.

Comprising the SL8582x serializer and SL8581x deserializer, the chipset overcomes the bandwidth, EMI, and reach limitations of conventional MIPI D-PHY while consuming less than 100 mW per link. It enables low-power connectivity between high-resolution cameras, displays, and processors.

The MSDL 20G supports up to two simultaneous single- or stereo-camera transmissions over one or two serialized links. Integrated VCSEL drivers and a transimpedance amplifier (TIA) enable optical links over tens of meters, while differential copper links can extend up to 2 meters. Typical power consumption is 71 mW per optical link and 87 mW per electrical link, excluding the integrated sideband SerDes.

The MSDL 20G (SL8582x/SL8581x) is sampling now to early-access customers in bare-die or 4×4-mm µBGA-78 packages. Evaluation kits are available now for link validation.

Silicon Line

The post Dual-port MIPI D-PHY SerDes delivers 20-Gbps bandwidth appeared first on EDN.

Marelli and Microchip have announced a display connectivity solution that uses the open-standard ASA Motion Link (ASA-ML) to stream graphics and video from a vehicle’s central computer directly to automotive displays. The companies say the approach can simplify display architectures, reduce system costs, and give automakers greater sourcing flexibility for software-defined vehicles.

Microchip is extending its ASA-ML products from camera connectivity to automotive displays, with Marelli providing the display-side integration. The demonstration uses Microchip’s VS7000 ASA-ML chipset to process and transmit graphics and video generated by the vehicle’s central computer over a high-speed standardized link. Marelli configures and optimizes the ASA-ML deserializer to decode the video stream directly at the display, simplifying the display-side electronics.

The ASA-ML connection supports data rates up to 16 Gbps and incorporates link-layer authentication and encryption. The open standard also enables interoperability among products from multiple technology providers, giving automakers greater sourcing flexibility.

For more information about Microchip’s ASA-ML solutions, visit the ASA Motion Link product page.

Microchip Technology 

Marelli

The post Marelli, Microchip extend ASA-ML to displays appeared first on EDN.

SECO has developed a 5-in. industrial HMI panel and a compact SBC, both based on the Qualcomm Dragonwing IQ-2390 processor. The Compact Vision 5 Dragonwing IQ-2390 and SBC-Dragonwing-IQ-2390 target industrial connected devices for HMI, control, vending, building automation, industrial vision, and other compact embedded applications.

With a quad-core CPU and 1.1-TOPS NPU, the Compact Vision 5 Dragonwing IQ-2390 is designed for applications requiring touch interaction, industrial reliability, and entry-level on-device AI. It integrates a 5-in. (800×480-pixel) touchscreen, 3D GPU, up to 4 GB of RAM, and 16 GB of eMMC storage in a 145.5×102.4×33.4-mm enclosure. The panel-mount unit supports Wi-Fi and Bluetooth and includes MIPI-DSI, RS-232, CAN, Gigabit Ethernet, and USB-C interfaces.

Aimed at custom embedded systems, the SBC-Dragonwing-IQ-2390 provides the same processing, memory, and connectivity as the Compact Vision 5 on a small 47×114-mm board. Both platforms run Clea OS, based on Yocto Linux, providing a software environment for development, deployment, and lifecycle management.

Register for the Early Access Program to receive information on evaluation options and next steps for the Compact Vision 5 Dragonwing IQ-2390 and SBC-Dragonwing-IQ-2390.

SECO

The post SECO pairs Dragonwing with HMI and SBC appeared first on EDN.

Courtesy of this circuit’s flexibliity, you can select and adjust both, one, or none of the channels of a dual digipot.

One huge advantage that digital potentiometers have over electromechanicals is, of course, the inherent flexibility the electronic interface provides versus the mechanical alternative. Figure 1 shows an example.

Figure 1 The 256-step (8-bit) resolution, dual-channel DPOT U2 can be programmed up/down with single step-per-push or auto-repeat (button held), with operating mode options including channel X or Y alone per switch S2’s position on X or Y, both ganged together with S2 in X&Y, or setting-protected (where accidental button pushing won’t disturb the setting) with S1 in LOCK.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Dual tandom pots have certainly existed for a very long time, and are sometimes extremely useful. Adusting the volume on a stereo sound system, or tuning a two-pole filter, are obvious examples. But when mechanical pots share a common shaft, of course, they must turn in lockstep together forever, whether that suits the application at hand perfectly. Or not.

Figure 1’s circuit allows U2’s dual pots to step together, singly, or not at all as determined by simple switches S1 (SPST) and S2 (SPDT three position with center off). Convenient autorepeat is accessed by holding the desired step UP/DOWN button depressed for longer than a half second.

Which is certainly a step up in flexibility.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

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The post Double DPOT programming: Parallel gang-up, singleton, or none appeared first on EDN.

A new flash cost calculator helps OEMs identify potential savings and explore alternative storage strategies for flash chips at a time when market conditions are putting growing pressure on memory costs. The calculator reduces component costs by selecting flash capacity closer to what the product actually requires, rather than paying for oversized managed components.

According to Gartner, NAND flash prices are forecast to rise 234% in 2026 with a meaningful pricing relief not expected until late 2027. But much of the industry conversation has focused on supply constraints and component prices, noted Steffan Schumacher, CEO of Tuxera. “The more important question is what engineers can do in response.”

Source: Tuxera

Schumacher added that the opportunity isn’t simply to source a cheaper component today, but to design storage architectures that use flash more efficiently and give manufacturers more choice as costs, availability, and technology inevitably change again. Here, Tuxera’s flash cost calculator gives OEMs greater flexibility in how they design and manage embedded storage.

In other words, the calculator increases sourcing flexibility by opening a wider choice of supported raw flash parts and vendors. It also reduces dependence on a single component roadmap. For instance, a product may need only 4 GB of storage, but manufacturers can face increasingly limited choices at lower eMMC capacities.

If the required capacity is no longer available, OEMs may be forced to move to a significantly higher-capacity alternative, potentially paying for far more storage than the product actually needs. Here, the calculator enables OEMs to move from managed flash such as eMMC to raw NAND. “Manufacturers cannot control NAND prices, component availability or suppliers’ product roadmaps, but they can build greater flexibility into how they use flash,” Schumacher said.

This design flexibility is crucial for manufacturers of automotive electronic control units (ECUs) and zone control units (ZCUs), smart meters, industrial equipment, and medical devices, where the impact comes not only from higher flash prices but also from the capacity options available to them. NAND flash prices and sourcing pressures are also likely to rise in edge AI and physical AI designs because devices will demand more storage and data infrastructure.

This is how the calculator works. OEMs can enter their required capacity, annual production volumes, and production lifetime to estimate potential savings, for instance, from moving from managed flash to right-sized raw flash. Moreover, they can enter their own supplier pricing to reflect their individual purchasing agreements.

The flash cost calculator is available now at Tuxera.com/flash-cost-calculator.

Related Content

• AI Triggers a New Memory Super Cycle
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• Flash vendors show pricing restraint in surging market
• The Truth About Memory Supply, Pricing and What Comes Next

The post Flash calculator promising cost savings, design flexibility appeared first on EDN.

OKW’s award-winning CONTROL-KNOBS for rotary potentiometers and encoders can now be specified customized and ‘production line ready’.

These ergonomic knobs, which won an iF DESIGN AWARD, are ideal for touch/click functions on menu-driven interfaces. Applications include measurement and control, medical/wellness, laboratory equipment, HVAC, communications, building control systems and Smart Factory technology.

CONTROL-KNOBS can now be specified custom machined and printed with legends, logos and graphics. OKW can also supply the knobs with laser marking – perfect for consecutive numbering or machine-readable QR codes, bar codes and DataMatrix codes. Other customization services include installation/assembly of accessories.

These ergonomic collet knobs combine a robust polycarbonate inner body with a soft-touch TPE outer shell for anti-slip operation. Functional grooves on the edge ensure a good grip.

CONTROL-KNOBS for rotary potentiometers and encoders (Source: OKW Enclosures Inc.)

CONTROL-KNOBS can be specified (as standard) with or without a pointer line on the side for fine scaling. Optional LED illumination and a translucent optic ring enable operation in low light conditions and further enhance the aesthetics. Energy-saving (5 V) SMD RGB LEDs allow individual illumination and colors.

The knobs are available in two diameters, ø36 mm and ø46 mm – both for 6 mm, 1/4″ boreholes – and in two standard colors: nero and volcano. Top covers and bases (accessories) can also be specified in these colors. Accessories also include round nuts and a spanner.

The minimum component specification for one CONTROL-KNOB without illumination is a knob and cover; a base can be added if required. A base and illumination kit (accessory) are essential for the LED backlit version. On request, OKW can supply the knobs with accessories pre-assembled.

For more information, view the OKW website: https://www.okwenclosures.com/en/Potentiometer-Tuning-knobs/Control-Knobs.htm

The post Control knobs are customizable and production-ready appeared first on EDN.

In a radio receiver, the analog-to-digital converter (ADC) sampling rate and the complexity of the analog anti-alias filter in front of it are not independent choices. A sampled system can uniquely represent signals only over a bandwidth of Fs/2, so any content falling outside the chosen Nyquist zone must be removed before it reaches the converter. The closer the sampling rate sits to the theoretical minimum, the narrower the filter’s transition band becomes, and the higher the filter order required to reach a given attenuation.

Sampling faster relaxes that filter. The reason designers do not simply sample much faster is the cost on the other side: a higher sampling rate means a more expensive converter and more data for the downstream FPGA or ASIC to process. The optimum sits wherever those two costs balance, and in a conventional signal chain, it’s the digital side that limits how far the balance can move.

That constraint changes when the converter itself performs the processing. ADCs are now available that integrate a DSP block alongside the ADC cores, providing decimation, digital downconversion (DDC), and IQ mismatch correction on chip.

Because the decimator reduces the output data rate, sampling faster no longer adds to the downstream burden; in fact, it can reduce it. The optimum moves toward higher sampling rates with relaxed analog filtering, and a significant portion of the digital front-end moves off the FPGA at the same time.

This article works through three radio receiver designs: a direct conversion receiver, a direct conversion receiver with digital channel selection, and an IF sampling receiver. These are each built around a 14-bit dual-channel ADC with an embedded DSP block from Silanna’s SD1148 family, which offers sample rates from 40 to 250 MS/s.

1. Direct conversion receiver

The direct conversion, or zero-IF, receiver architecture shown in Figure 1 uses a quadrature RF mixer that converts the RF signal directly to baseband. The signal chain starts with a band-select filter followed by a low noise amplifier (LNA), and the local oscillator (LO) is centered on the RF signal band.

Figure 1 Here is a simplified architecture of a direct conversion receiver. Source: Silanna

The mixer has two paths, one producing the in-phase (I) output and the other the quadrature (Q) output. So, a quadrature LO signal with sine and cosine components is required.

The baseband IQ signal path following the mixer typically consists of a programmable gain stage, an anti-alias filter, and finally the ADC. Many implementations include additional filtering along the signal chain and some amount of RF gain control. Channel selection can be either analog (by changing the LO frequency) or digital, in which case the LO frequency is fixed.

The entire band of interest is digitized by the ADC, and digital downconversion plus filtering are used to select the desired channel. Even with analog channel selection, channel-select filtering is often performed partially in the digital domain.

Implementation challenges

The direct conversion architecture does not have to deal with image rejection, as the signal is its own image. Its implementation challenges lie in LO feedthrough, 1/f noise, and gain transients. In the baseband, these issues are concentrated in the vicinity of DC and are most severe for systems using narrow channel widths, measured in kHz.

They are easier to deal with when using wider channel widths and modulations that are less sensitive to low-frequency content. When digital channel selection is used, placing the LO between channels largely solves them.

Another challenge is IQ mismatch: amplitude and phase mismatch between the I and Q components, which results in leakage between the I and Q signal paths. All baseband blocks, the mixer, and the LO contribute to this mismatch.

Differential gain errors between the I and Q paths in the mixer, amplifiers, and ADCs, together with the filter passband gain, contribute to gain mismatch. Phase mismatch is caused primarily by phase error between the LO sine and cosine components, by mismatch in the filter frequency response, and, to a lesser degree, by clock phase mismatch between the two ADCs.

Using dual devices for the amplifier and the ADC that are specifically designed for IQ applications significantly reduces the contribution from these blocks. Calibration is commonly required to suppress the remaining mismatch to a tolerable level. For signals with modest bandwidths, a frequency-independent calibration is typically sufficient.

Sampling rate and anti-alias filtering

ADC sampling-rate selection and baseband filtering are tightly coupled. Sampled systems, including ADCs, can uniquely represent signals only over a bandwidth of Fs/2, where Fs is the ADC sampling frequency. This condition is known as the Nyquist criterion.

If the ADC input contains spectral content in both the region from 0 to Fs/2 (the first Nyquist zone) and the region from Fs/2 to Fs (the second Nyquist zone), the sampling process folds frequency components from these regions onto one another. This effect is called aliasing and must be avoided. Either region can be used to place the signal of interest, but not both simultaneously.

The anti-alias filter is an analog filter placed in front of the ADC to suppress unwanted signal and noise content outside the selected Nyquist zone prior to sampling. When the signal band extends to Fs/2 − Δf, the frequencies that must be fully rejected by the filter begin at Fs/2 + Δf, giving a transition band 2Δf wide.

The narrower the transition band, the higher the filter order required to achieve a given attenuation. For this reason, it’s advantageous to increase the ADC sampling rate beyond the theoretical minimum stated by the Nyquist criterion in order to relax the filter specification. This margin is typically at least 30% and is often higher.

The trade-off is higher ADC cost and increased digital signal-processing requirements versus the cost and complexity of analog filtering. An ADC with an embedded DSP block offsets the digital processing burden, which shifts the optimum toward higher sampling rates with relaxed analog filtering.

Design example

The first example uses the dual ADC in a direct conversion receiver. The RF signal is a 26 MHz-wide band centered at 915 MHz. After downconversion, the baseband I and Q signals extend from 0 to 13 MHz. The ADC sampling rate is set to 65 MS/s, which provides a relaxed anti-alias filter transition band from 13 MHz to 52 MHz.

Figure 2 The above configuration represents a direct conversion receiver application. Source: Silanna

As shown in Figure 2, the DSP block offers adders and multipliers that can be programmed to correct the DC offset and the IQ gain mismatch. Hardware for IQ phase correction is also present. The user provides the control values for these blocks.

The DSP block includes a decimator that can be programmed for rates of two and four; in this case the rate is set to two. The decimation process includes a digital finite impulse response (FIR) low-pass filter whose passband is 40% of the output sampling rate, which here is 0.4 × 65 MHz/2 = 13 MHz, matching the requirement.

When a low-pass filter is applied to the I and Q paths separately, the combined effect produces a symmetric band-pass response centered at 0 Hz, resulting in a passband from −13 MHz to +13 MHz. Figure 3 shows the frequency-domain signals at each step of this direct conversion receive chain.

Figure 3 Here is how frequency domain signals look like in a direct conversion receiver. Source: Silanna

The decimator has reduced the output sampling rate to 32.5 MS/s. The combination of oversampling and digital filtering improves the signal-to-noise ratio by about 3 dB for every decimation factor of two.

One consequence is worth noting. Because the decimation filter suppresses signals in its stop band, it can affect the gain control loop of the system. If a strong signal is present at the ADC input, but is filtered out of the digital output, a loop that monitors the output might not detect that the ADC is starting to clip. This can be avoided by incorporating the overrange bit provided by the ADC into the gain control algorithm.

2. Direct conversion receiver with digital channel selection

The second example operates on the same 26 MHz RF band, now divided into four 6.5-MHz channels. The application receives one channel at a time, occasionally switching between channels.

Figure 4 The radio receiver design uses a built-in DDC to perform channel selection within the digitized band. Source: Silanna

The RF and analog portion of the receiver remains the same as in the first example. We enable the digital downconverter built into the ADC, shown in Figure 4, and tune the numerically controlled oscillator (NCO), which provides the digital LO to the center frequency of the desired channel. This shifts the selected channel to 0 Hz, as shown in Figure 5. The decimation factor can then be programmed to four, reducing the output sampling rate to 16.25 MS/s.

Figure 5 Frequency domain signals are shown in a direct conversion receiver using digital channel selection within the digitized band. Source: Silanna

We can also consider reducing the ADC sampling rate from 65 MS/s to the 50–55 MS/s range, which maintains reasonable anti-alias filter requirements while further reducing the output data rate. Using these DSP blocks offloads a significant amount of digital signal processing from the FPGA to the ADC, providing both cost and power savings.

3. IF sampling receiver

The third example uses an IF sampling radio architecture, which is essentially a superheterodyne receiver in which the second downconversion stage is implemented digitally. A simplified block diagram is shown in Figure 6. The RF signal is converted to baseband in two steps: first to an IF, where it is digitized, and then to baseband using a digital mixer.

Figure 6 IF sampling receiver converts RF signal to baseband in two steps. Source: Silanna

This architecture eliminates the IQ matching issues and the challenges in the vicinity of DC associated with direct conversion receivers. The improvement comes at a cost: the system must achieve image rejection, which typically requires more analog filtering.

In addition, the ADC input is at a higher frequency, which demands a higher-performance ADC and places tighter requirements on sampling-clock jitter. A common way to keep the ADC sampling rate reasonable is to locate the input signal in the second (or third) Nyquist zone. In the IF sampling receiver, the ADC input signal is real, requiring only a single ADC per receive chain instead of a dual-channel device.

Figure 7 IF sampling receiver is show with DSP’s DDC and decimation functions enabled. Source: Silanna

In this example, we process a 40 MHz RF signal in the 2.4 GHz ISM band. This requires an increased sampling rate than in previous examples, and the 210-MHz device from the same family was selected. The IF is chosen as 150 MHz, which places the image 300 MHz away from the desired signal at RF.

The ADC sampling rate is chosen as 200 MS/s, which centers the IF in the second Nyquist zone. Operating in higher Nyquist zones requires band-pass anti-alias filtering; in this case the lower stopband is from DC to 70 MHz, the passband is from 130 MHz to 170 MHz, and the upper stopband is from 230 MHz and above.

Figure 8 See the frequency domain signals in IF sampling receiver. Source: Silanna

The aliasing effect, which in this case is a useful feature of the sampling process, is used to bring the signal to a 50 MHz center frequency. It’s worth noting that a signal sampled from the second Nyquist zone appears spectrally inverted, so the alias that lands in the first Nyquist zone is flipped relative to the original. Figure 8 shows the spectrum of the signal throughout the signal chain.

Negative frequencies are typically omitted when dealing with real signals, as they are a mirror image of the positive frequencies. Here, however, it’s useful to note that the signal image in the negative frequencies is not flipped relative to the original analog signal. With this insight, we can enable the DDC and program the digital LO to −50 MHz. This rotates the spectrum by 50 MHz toward the positive frequencies, bringing the band to a 0-Hz center frequency with the proper orientation.

The image originally in the positive frequencies is now shifted toward Fs/2 and partially appears in the negative frequencies around −Fs/2. To remove this unwanted image and reduce excess bandwidth, the decimator must be enabled with a decimation factor of two or more. The 40-MHz signal bandwidth permits additional decimation, so the decimator is set to decimate-by-four.

This reduces the output sampling rate to 50 MS/s. Because we have translated a real signal into a complex one, we now have both I and Q components, which together carry the same data rate as a real 100 MS/s signal. The 40% decimator filter bandwidth results in a passband from −20 MHz to +20 MHz, a good fit for the 40-MHz signal band.

Common pattern in three RF architectures

The same pattern holds across all three architectures: moving decimation, digital downconversion, and IQ correction into the converter relaxes the analog filtering in front of it while reducing, rather than increasing, the data rate behind it.

In the direct conversion example, raising the sampling rate from 40 MS/s to 65 MS/s widened the anti-alias transition band by 2.8×, added 2.1 dB of oversampling gain, and still lowered the output data rate by 19%. In the channel-selection example, the output rate fell to 16.25 MS/s and the channel filter moved off the FPGA entirely. In the IF sampling example, a real 200-MS/s input became a complex 50 MS/s output with the unwanted image removed on chip.

The practical consequence is that the sampling-rate-versus-filter-order trade-off no longer must be settled in the analog domain alone. Where the digital front-end processing is effectively free, because it happens inside the converter, the optimum moves toward faster sampling and simpler analog filters, and a meaningful portion of the FPGA workload moves with it.

Mikko Waltari is director of data converter designs at Silanna.

Related Content

• Radio Architectures: ADCs and Receivers
• RF-sampling ADCs for multiband receivers
• A checklist for designing RF-sampling receivers
• Analyzing ADC Noise Impacts on Wireless System Performance
• ADC Parameters for Your Wideband Telecommunications Receiver

The post A comparison of traditional and DSP-enabled ADCs in radio receivers appeared first on EDN.

Butterworth response circuits come in both low- and high-pass versions, as well as ideal, Sallen-Key, emitter follower and DC accurate variants.

Many decades ago, I published a Design Idea about using equal value resistors and capacitors to implement a third-order active filter with the classic Butterworth response. This topology required two or three unity gain op-amps, depending on where the first-order RC section was located. And by swapping the positions of the resistors and capacitors, you could switch from a low-pass to a high-pass Butterworth response, while the 3 dB corner response remains the same at 1/(2*pi*R*C).

Wow the engineering world with your unique design: Design Ideas Submission Guide

The normalized Butterworth polynomial of S^3 + 2*S^2  + 2*S +1 can be factored into (S + 1)*( S^2 + S + 1), thereby revealing a multiplied first-order and second-order quadratic. In the original filter, the first-order section could be placed either ahead of or behind the second-order section, with the later yielding a two op-amp version; the op-amps are unity gain and provide isolation between the sections. These are the Type I versions.

A while back, I began working with different active filter topologies, including a revisit of the original Sallen-Key Type I version with an emitter follower implementation used much earlier in a car radar application. In the process, I discovered another filter version, where the factored Butterworth polynomial is directly implemented with a single op-amp. This approach, which also works with equal-value resistors and capacitors as well as an op-amp configured with a gain of 2, is called a Sallen-Key Type II. This particular configuration has a pass band gain of 2, while the Type I has a gain of 1.

The emitter follower version was implemented by replacing the unity gain op-amps in the Sallen-Key Type I with an emitter follower, and can use either two or three emitter followers similar to the op-amp version Type I. With both versions, the emitter followers can be complementary (NPN and PNP, or visa versa) which achieves a better effective input-to-output DC offset voltage, since the VBEs cancel. Since the emitter follower has a voltage gain of slightly less than unity, this characteristic causes the amplitude response to fall between Butterworth and Bessel regions, although the phase response follows the classic Butterworth.

While continuing my investigation of various active filters, another topology popped up that apparently dates way back to early 70s Fluke DMMs (digital multimeters). Known as the DC accurate second-order low-pass filter, it was utilized as a voltage reference noise filter. This filter is quite interesting in that the filtering is achieved by shunt capacitors working against an input series resistance; the active op-amp has no resistive connection to the input or output and therefore contributes no offset voltage or bias current.

It’s also interesting (to me, at least!) that if the op-amp 2*R resistor feedback resistance is implemented with two separate series resistors of value R, along with a shunt capacitor to ground installed between them, this configuration transforms into a third-order Butterworth low-pass filter with equal-value resistors and capacitors. If the shunt capacitor to ground is then removed, the filter reverts back to a second-order Butterworth, albeit with a lower corner frequency by a factor of 2/pi. I found it quite amazing that removing a shunt capacitor to ground actually lowers the corner frequency of a low-pass filter!

Figure 1 shows the various forms of these low-pass filters for simulations, including an ideal filter version with the Butterworth transfer function.

Figure 1 The various third-order active Butterworth response low-pass filters discussed in this Design Idea include ideal, Sallen-Key Type I and II, emitter follower and DC accurate variants.

Figure 2 shows LTspice AC simulation results, illustrating the limitations of the op-amp output impedance on the stop-band rejection. Note that the emitter follower version has slightly less than unity gain and a slight deviation from the ideal response, as expected.

Figure 2 In these LTspice linear AC low-pass filter simulations, note the stop band attenuation limits due to op-amp model finite output impedance.

Figures 3a and 3b  show actual lab measurements performed with a DSO (digital storage oscilloscope)/AWG (arbitrary waveform generator) combination, utilizing the built-in Bode feature, for various low-pass filters. Compare them with the previous simulations shown in Figure 2, and note the stop band limitations due to the finite op-amp output impedance.

Figure 3 Low-pass filter Bode measurements in the lab show stop band effects due to physical op-amp output impedance limitations (a, left). In the emitter follower version’s Bode plot, note that the DC gain is -0.6 dBV (b, right).

So far so good; this is getting increasingly fun for me as I move through these various active filter topologies, and hopefully you agree! The detailed analysis for each of these filter topologies, left as an exercise for the reader, is an interesting adventure that helps illustrate what’s going on. For now, there’s more exploration to come!

Now, lets swap the resistors and capacitors in each filter topology, thereby transforming each filter from a low-pass to a high-pass version (Figure 4). The only filter to complete this transformation with any negative effects whatsoever is the DC accurate version. With this particular filter, the DC isolation due to the shunt capacitors is now replaced with shunt resistors, which obviously couple the op-amp input and output offset to the filter output. Otherwise, this filter, like its peers, behaves as expected in its high-pass form.

Figure 4 Swapping resistors and capacitors results in high-pass versions of the circuits previously seen in Figure 1.

Figure 5 illustrates the simulation results with the resistor and capacitor swaps made to each previous filter type, thereby transforming it from a low-pass to a high-pass filter with the same characteristic (i.e., Butterworth) and 3dB corner of 1/(2*pi*R*C).

Figure 5 Shown here are simulations of the high-pass filter derivations of Figure 1’s circuits, i.e., the circuits shown in Figure 4, in each case achieved by swapping resistors (R) and capacitors (C).

Figure 6a and 6b are actual lab measurements which reveal some of the measurement setup and equipment limitations in dynamic range at the low-frequency end.

Figure 6 In these lab-based Bode high-pass filter measurements (again, a at left, b at right), note the dynamic range limitations at lower frequencies.

I hope that the Bode Plot lab measurements on actual hardware for both the various low-pass and high-pass filters, for comparisons with the simulation results, are helpful for you. The circuit were built using 1% tolerance resistors and 10% tolerance film capacitors, on plug-in protoboards. You can judge for yourselves as to whether the lab measurements and simulations are in reasonable agreement; reader thoughts on this topic or anything else regarding this Design Idea are welcomed in the comments. More generally, have fun with these active filters!

Michael A Wyatt is a life member with the IEEE and has continued to enjoy electronics ever since his childhood. Mike has a long career spanning Honeywell, Northrop Grumman, Insyte/ITT/Ex-elis/Harris, ViaSat and retiring (semi) with Wyatt Labs. During his career he accumulated 32 US Patents and in the past published a few EDN articles including Best Idea of the Year in 1989.

Related Content

• Dual amplifier active filters
• Toward better behaved Sallen-Key low pass filters
• Component tolerance sensitivities of single op-amp filter sections

 

 

The post Fun with third-order active filters appeared first on EDN.

The simplest explanation is likely the best, even if its validity isn’t always intuitively obvious in advance.

Speaking of USB-C, and the cables (including splitters) that connect to it to other things…

My long-in-the-tooth Intel-based 2018 Apple Mac mini is still sitting on my desk, humming to my right, even though its M2 Pro Apple Silicon-based successor has been sitting downstairs in storage awaiting its turn in the spotlight for going on three years now. The legacy hardware is no longer a candidate for new Apple operating system releases, but it’s still receiving bug fixes and security patches, until sometime in the second half of next year, if past-history trends remain valid. And as the saying goes, “if it works, don’t touch it” (I’d also be tempted to haul out the “a penny saved is a penny earned” quote, but since I’ve already bought its replacement…).

In conjunction with my transition to it from its 2014-era Mac mini predecessor roughly 2.5 years ago, I upgraded the two-display suite above it to a set of Dell P2415Q 4K LCDs.

The Mac mini leverages the displays’ HDMI inputs; a “Project Volterra” Windows-on-Arm dev kit 2023 stacked above it connects to those same LCDs over their DisplayPort connections, and front panel buttons toggle the displays between the two systems when running concurrently.

Look back at that 2018 Mac mini rear panel “stock” photo a couple of paragraphs ago, however, and you’ll only see one HDMI output, into which I’ve plugged a “straight” HDMI cable running directly to one of the LCDs. How, then, did I connect the system to the other display’s HDMI input? That’s where today’s teardown victim enters the picture.

It’s an Anker A8730 6’ USB-C to HDMI adapter cable; I’d bought and pressed it into immediate service way back in mid-2021. I sourced from Anker’s outlet store on eBay, where it cost $25.90 as a refurb. So, you can say I’ve gotten my money’s worth out of it! Speaking of fiscal topics, there’s a 0.75′′ (19.1 mm) diameter U.S. penny alongside in the second (and non-stock) image that follows, along with subsequent others, for size comparison purposes.

A multimedia-centric repurpose

How it works is (at least to me) an interesting story in and of itself. It fundamentally leverages a DisplayPort technology called “Alt Mode”, which repurposes USB 3.x’s “SuperSpeed” data and Configuration Channel (CC) lines to transport dedicated audio and video streams sourced from the graphics and sound subsystems. The CC leverage explains why, among other implementation reasons, it’s only applicable to USB-C, not also to prior-generation USB physical connector standards.

Macs don’t additionally support DisplayPort’s Multi-stream Transport (MST) mode, either in the operating system (generally) or in hardware (for newer Apple Silicon-based systems). If MST support had existed, it would have conceivable enabled me to extended-mode tether both displays to a single USB-C (or Thunderbolt 3, aka TB3, in this case) system connector, in combination with a separate inter-display connection. But again, per the system back panel photo, I had plenty of spare connector candidates available, not even counting those on the separate expansion hubs (the latter added subsequent to the snap of the earlier “stack” picture).

But what’s with all this DisplayPort talk? I thought we were discussing connecting the computer to a display’s HDMI input! We are, and that’s where the bulge surrounding the adapter cable’s HDMI connector end comes in. Conceptually, and I hope to definitively confirm today, inside is likely a DisplayPort to HDMI protocol-converting bidirectional transceiver; a particularly robust one, it seems, since the Anker A8730 touts 4K 60 Hz specs. HDMI once also had an “Alt” mode for USB-C, at least on specification paper, although actual products never made it to market.

Erratic function = dissection rationalization

Since the adapter cable had been operational in my abode since mid-2021 (and, considering it was a refurb, maybe even earlier than that with its original owner), why’d I decide to take it apart? Curiosity was as always one motivation, although I generally hold that particular urge at bay for as long as the gear remains operational. But this one had eventually failed, in another story-in-and-of-itself, through whose telling I aspire to also rationalize the “Occam’s Razor” title reference.

As previously mentioned, the 2018 Mac mini is still receiving periodic patches for its last-supported MacOS 15 “Sequoia” operating system release. A few updates ago, the left-side display of the pair (the one leveraging the Anker adapter) was no longer recognized by the system after the upgrade and subsequent reboot. Online research revealed that mine wasn’t a unique post-update quirk, and swapping the adapter cable to a different TB3 system connector got the display going again.

So, I figured that an obscure “Alt Mode” bug (specifically, since the first TB3 port still worked fine for generic data) introduced along with the upgrade had made it through Apple’s pre-release QA checks. This purported scenario was unsurprising albeit still disappointing, given that Intel-based Macs in general, and this system in particular, were on their “last legs” and likely no longer receiving their fair share of QA attention. Why my surmised bug only affected one TB3 port but not another wasn’t clear, but…

The next time I did an update, however, the exact same thing happened, this time to the second TB3 connector. Swapping the cable adapter back to the first TB3 connector didn’t resurrect the display. And I no longer had any other spare TB3 ports on the system available to try. At this point, I began to fear I had a fundamental system hardware degradation issue on my hands.

But after unplugging the cable adapter from the Mac mini and trying it with the “Project Volterra” system instead, where it also didn’t work, I was reassured by the now-nonfunctional repetition across multiple systems (and O/Ss) that a dead cable adapter was the likely culprit. An “Amazon Basics” cable adapter replacement fired up fine, sealing the Anker A8730’s fate.

What was behind the cable adapter’s initial failure, temporary resurrection, and eventual permanent demise? I hoped the pending teardown might provide visual Achilles’ Heel evidence (hold that thought). But I suspect it has something to do with MacOS’s use of display-supplied Extended Display Identification Data (EDID) information for software interface purposes versus Windows’ leverage of (when available) display-specific drivers.

My guess is that EDID (re-) enumeration in MacOS happens both when a display is first-time plugged into a new system connector and after each sufficiently impactful operating system update. In this particular case, the aforementioned DisplayPortHDMI bidirectional protocol translator in-between the system and display initially began operating erratically and eventually failed completely. But that’s just my conjecture; reader theories in the comments are as-always also welcomed!

Eyes-on conceptual validation (or not)

Speaking of tearing down, let’s dispense with further abstract chit-chat and get to dissecting, shall we? Here are a few more real-life device photos as prep. Packaging is long gone at this point, along with any potential originally accompanying literature. The USB-C end, to start.

With a product-code sticker behind it.

Intermediary cable markings next.

And now the bulge-augmented HDMI other end, starting with the seam-less cable-intro side.

The connector side conversely does have a visible seam at its circumference.

But attempts to surmount it with hair dryers and heat guns, along with spungers and such, were for naught. So, I escalated my attack by breaking out the hacksaw with hopeful deft technique.

That’s what I’m talking about!

For anyone following in my footsteps who prefers a less Neanderthal-reminiscent dissection approach, here’s the HDMI connector-surrounding piece I was unsuccessfully trying to extract earlier. Note specifically the locations of the retention tabs.

Finally, what you’re all most interested in, the PCB. As I’ve mentioned before, “top”, “bottom” and other orientation terms are particularly nebulous where HDMI is concerned. So instead, here’s the side corresponding to the wider HDMI connector edge.

Now zooming in for a closer look.

I was admittedly surprised to encounter a preponderance of passives, given that the most common adapter-usage orientation would have put this side on top, with the remaining (and proportionally higher heat-generating) stuff you’ll see next on the other side and below it. Given that heat rises (don’cha know), and that there’s no passive ventilation venting available, that’s a seeming premature failure-inducing decision. But not in my case, since the HDMI connector points downward with this display, not horizontally straight out the back as with many others.

Components of particular note include a five-lead SOT23-packaged step-down (buck) DC-DC converter at lower left, marked as follows.

JWA5J
91D5T

There’s also a “2R2” (2.2 µH) inductor to its immediate left, and a 27 MHz oscillator to its right. And what does that clock chip likely drive? Let’s flip the PCB over to the other side.

Now that’s more like it (unless you’re into passives, that is). Again, we zoom in for a closer look.

At lower left is Via Labs’ VL100, a (surprise, surprise…not…) DisplayPort USB-C Alt-mode controller. To its right is (surprise, surprise…truly, this time, at least a bit…) another oscillator, 24 MHz this time. Continuing to the right is, I’m guessing (readers?), a serial interface nonvolatile memory for code and data storage purposes, marked as follows.

125S40
BG17K8
P19030

In the lower right corner is another JWA5J DC/DC converter. Above it is (once again, no surprise) Paradise Technologies’ PS176 DisplayPort to HDMI video interface converter. And again for the passives fans among you, there are plenty more examples to see on this side of the PCB, too!

That’s a “wrap” for today, folks. Share your thoughts with me and your fellow readers in the comments, please!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• USB-C’s lingering incompatibilities and complexities, part 2: Splitter issues
• The 2025 WWDC: From Intel, Apple’s Nearly Free, and the New Interfaces Are…More Shiny?
• Connecting systems to displays with DVI, HDMI, DisplayPort: What we got here is failure to communicate
• USB: Deciphering the signaling, connector, and power delivery differences

The post Occam’s Razor and a USB-C to HDMI adapter appeared first on EDN.

Coolant level sensors may seem small, but they guard against big failures. In this Fun with Fundamentals entry, we break down how these devices keep engines—and engineers—from losing their cool.

On a blazing summer road trip, the dashboard warning light suddenly flickers on—a moment every driver dreads. Engines (and even modern EV battery packs) churn out enormous heat, and without coolant, the consequences are catastrophic.

But here’s the puzzle: how does your car know the coolant is running low before disaster strikes?

In this edition of Fun with Fundamentals, we’ll explore the humble coolant level sensor—a small but vital safeguard against meltdown.

ECL vs. CTS: Know the difference

Before diving in, keep in mind the critical distinction between an engine coolant level (ECL) sensor and a coolant temperature sensor (CTS), as mistaking one for the other is a common pitfall in automotive diagnostics. While both are vital to safeguarding your engine from catastrophic overheating, they serve entirely different functions.

ECL sensor is a fluid-monitoring device typically housed in the expansion tank to alert you when the coolant volume is dangerously low. On the other hand, CTS is a thermal resistor submerged directly in the engine’s coolant passages to constantly measure how hot the fluid is, sending real-time data to your dashboard gauge and engine control unit (ECU) to manage fueling and cooling fans.

A coolant temperature sensor is only useful when it’s bathed in liquid. If the coolant suddenly drains away, the sensor may end up reading the surrounding air—which can appear deceptively cool—while the engine itself is on the verge of meltdown. That’s where the coolant level sensor steps in: it provides an independent safeguard, alerting the driver to dangerously low fluid volume before heat damage spirals out of control.

Engineering approaches to level sensing

Automotive engineers have devised several clever ways to detect when coolant levels drop, each rooted in different physics. The most familiar is the magnetic float switch: a buoyant float with a magnet slides along a stem, triggering a reed or Hall‑effect sensor as the fluid rises and falls. It’s simple and time‑tested, though moving parts can wear or stick when exposed to degraded coolant.

Optical sensors take a higher‑tech route, using an infrared LED and prism to exploit total internal reflection. Surrounded by air, the light bounces back to the detector; submerged in coolant, the beam refracts outward, leaving the detector dark. This design eliminates moving parts and offers high accuracy, but contamination on the prism can cause false alarms.

Solid‑state conductive and capacitive sensors rely on the electrical properties of the fluid itself. Conductive probes complete a circuit only when immersed, while capacitive plates measure shifts in dielectric constant as coolant replaces air. These methods are robust and durable, though they demand careful calibration to account for varying coolant mixtures.

Finally, resistive coolant level sensors measure changes in electrical resistance as coolant wets or leaves the probe surface. In principle, they can provide a continuous indication of fluid height, but in automotive practice they are often used as threshold detectors because their accuracy depends heavily on coolant conductivity and electrode durability.

Variations in coolant chemistry, aging, and corrosion can cause drift, making them less reliable than capacitive or optical designs. Still, they remain attractive in cost‑sensitive applications, illustrating how even a “simple” level sensor embodies diverse physics and trade‑offs, balancing cost, reliability, and long‑term performance.

Figure 1 A solid-state capacitive coolant level sensor detects fluid presence by monitoring capacitance shifts relative to the media’s dielectric constant. Source: Rochester Sensors

Emerging sensor technologies

Beyond the classic float, optical, and capacitive designs, today’s vehicles are adopting more advanced approaches. Ultrasonic sensors use sound pulses to measure fluid levels with millimeter precision, making them ideal for EV battery cooling systems where continuous monitoring is critical.

Meanwhile, next‑generation capacitive sensors integrate digital outputs and on‑chip compensation, allowing them to adapt to different coolant chemistries and resist vibration over long service lives. Together, these innovations reflect a shift toward smarter, solid‑state sensing that not only detects low coolant but also feeds predictive diagnostics into modern vehicle networks.

Electric vehicles also introduce a new safety challenge: preventing coolant or water from entering the battery pack enclosure. Leak detection sensors integrated into the battery management system (BMS) are designed to sense even trace amounts of liquid.

By catching the smallest droplets of coolant or moisture, they trigger immediate alerts, so operators can act quickly—as coolant leaks into the battery enclosure can cause electrical faults or thermal runaway. This makes leak detection a critical complement to level sensing, safeguarding not just the engine but also the high‑voltage battery system.

Figure 2 A coolant leak detection sensor detects coolant leakage through variations in resistance values and sends a signal to the BMS to warn the driver. Source: Amphenol

Maximum pressure ratings

Beyond temperature and chemical resistance, coolant level sensors must survive the pressurized environment of modern cooling systems. Most automotive sensors are specified for maximum operating pressures in the range of 18–20 PSI, which aligns with typical radiator cap ratings.

Heavy‑duty capacitive designs, however, can tolerate up to 100 PSI, making them suitable for trucks, off‑road equipment, or specialized industrial cooling loops. Pressure resilience ensures that sensors continue to deliver reliable signals even when coolant systems are stressed by high loads, altitude changes, or extreme thermal cycling.

DC conductivity sensors for cold-start diagnostics

While continuous fluid monitoring typically relies on alternating current (AC) to prevent probe degradation, specific automotive applications utilize direct current (DC) conductivity sensors for targeted diagnostics. Because running a continuous DC current through an aqueous glycol mixture triggers electrolysis—rapidly corroding the metal electrodes—these two-pin DC sensors are engineered strictly for short-duration use at engine start.

By sampling the coolant’s electrical resistance for just a few moments when the ignition is turned on, ECU can safely verify adequate fluid volume before the vehicle departs, providing a highly cost-effective and reliable low-coolant safeguard without risking long-term sensor degradation.

Figure 3 A two-pin DC conductivity sensor monitors coolant levels during engine start-up to provide rapid, short-duration diagnostics. Source: Source: Amphenol

Design challenges for automotive engineers

Coolant sensors may look simple, but under‑the-hood realities make their design anything but trivial. Fluid doesn’t sit still; hard acceleration, sudden braking, and sharp cornering send it sloshing violently, which can trigger false alarms. Engineers counter this with clever tricks like software‑based slosh filtering delays or physical baffles inside the expansion tank.

Then there’s the chemistry. Coolant is a harsh cocktail of ethylene glycol, water, and corrosion inhibitors, all running at over 100°C under pressure. Materials must withstand years of exposure without cracking or leaching, which is why robust polymers like PA66 nylon or glass‑filled composites are common choices.

Finally, the economics of automotive design loom large. Saving even a dime per vehicle adds up across millions of cars, but reliability cannot be sacrificed. A failed sensor that leads to an overheated engine costs far more than the pennies saved, making the balance between cost and durability one of the toughest calls in sensor engineering.

Picture yourself tasked with designing a sensor that must survive years inside a hostile engine bay. Every bump in the road sends coolant sloshing unpredictably, every chemical in the mix is trying to corrode your materials, and every cent shaved off the bill of materials is scrutinized by the finance team.

Do you prioritize rugged polymers over cost savings? Do you trust software filtering to handle slosh, or add physical baffles that complicate the tank design? These are the trade‑offs real engineers wrestle with—and they highlight why a “simple” coolant sensor is anything but simple.

Future trends in coolant sensing

Looking ahead, coolant sensors are evolving beyond simple switches into smart diagnostic tools. Ultrasonic probes and advanced capacitive designs now deliver continuous, high‑accuracy readings, while digital outputs over CAN bus enable predictive maintenance and fleet monitoring. As electric vehicles demand tighter thermal control for batteries and power electronics, these innovations are reshaping coolant sensing into a critical part of next‑generation automotive safety and reliability.

Figure 4 XLS-1 series single point ultrasonic level sensor prevents false low-coolant alarms caused by reservoir sloshing and foam accumulation in automotive cooling systems. Source: Gems Sensors & Controls

A coolant level sensor may look like a trivial part, but much like an airbag, its importance only becomes obvious in the moment of crisis. Behind its simple exterior lies a blend of fluid dynamics, materials science, and electronics working together to prevent catastrophic failure. Just as brakes give drivers confidence to push forward, level sensors quietly ensure engines survive the heat.

Now it’s your turn: Have you ever had to design around fluid slosh, or do you have a story of a sensor that failed under pressure? Share your experiences—the toughest lessons often drive the best engineering solutions.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

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• Automotive: The latest on in-cabin sensing designs
• When can a sensor be used in an automotive system?
• Extreme automotive environment challenges sensor design
• Three trends driving the sensor boom in the automotive industry

The post Automotive coolant level sensors: Fundamentals to stay cool appeared first on EDN.

Be prepared to respond to “electrical overstress” claims from semiconductor suppliers by citing their own datasheet entries.

During my automotive embedded career, I was heading a product team controlling auxiliary functions of a diesel engine powertrain for passenger vehicles.

As you are likely already aware, a “Check Engine”  lamp illuminates on the driver dashboard in case of any malfunction with the engine or its control system. This activation alerts the driver, so that he or she can get the malfunction rectified before continuing the journey.

In one of our production batches, the vehicle assembly line technician started reporting “erratically and intermittently illuminating check engine lamp” as feedback. All of these vehicles were summarily rejected and blocked from further dispatch.

Do you have a memorable experience solving an engineering problem at work or in your spare time? Tell us your Tale

Tempers predictably flared all across the vehicle plant as the population of rejected vehicles grew rapidly. Curiously, our electronic control unit (ECU) associated with this function had been performing flawlessly for the last few years. It was a mystery to all of us why such a problem should crop up so suddenly.

When the failure was analyzed in our laboratory, it quickly became clear that the output driver IC pin used for driving the LED was pumping around 4 mA of current through the LED even in the “off” state! The datasheet had guaranteed a maximum leakage current value of around 0.5 mA. The output driver IC was apparently misbehaving, at least as far as the associated driving pin was concerned.

The IC semiconductor supplier’s application engineers were contacted and briefed about the problem. They later responded with a stock diagnosis of “electrical overstress” as the root cause.

“But what can ever ‘overstress’ your driver pin in such a simple circuit?,” we replied in attempting to counter the (lack of) logic behind their answer. “A simple short wire connects the ECU to the dashboard LED connector.”

“It must be electroshock discharge (ESD) events occurring during your electronic assembly, then,” they responded. “Sometimes ESD precautions are violated by the assembly technicians. We have faced such problems from a few customers in the past.”.

We clearly understood by this point that the semiconductor supplier team was trying to wriggle out of the situation without taking any responsibility or otherwise helping us. “How can so called ‘ESD events’ be partial only to a specific pin of your driver chip?,” we responded, in striving to alert them to the flaw in their reasoning. “It should have caused random failures across all units we’ve manufactured to date, and with all of the pins of your driver chip.” However, the supplier team clung to its reasoning, bringing the situation to an impasse.

Every passing day, our plant situation was getting more and more explosive, when I was struck by an idea. I asked our team to note down the alphanumeric production batch codes stamped on all of the culprit chips. To our surprise, all of them were identical! In contrast, the healthy chips all had other production batch codes.

We wrote an inquiry mail to the semiconductor company, asking them to decode the alphanumeric production batch code stamped on the culprit chips. Their answer was predictable: “It means: This chip was manufactured in country X and plant location Y, with month/year code as mm/yy.” Apparently, all of the culprit chips were manufactured at a specific plant location, where a production quality lapse was presumably leading to the disaster we were facing.

What was the way ahead? We pre-filtered out all of the culprit chips based on their production batch code, preventing them from being assembled on our boards. We also filtered them out of our supply chain by directing our distributors not to supply such chips to us. These steps solved the problem for once and all!

The lessons and insights behind this case are as follows:

• Be thorough with your circuit analysis. This means, among other things, completely understanding all datasheet entries for all key components.
• Prepare yourself to respond to “electrical overstress” responses from semiconductor suppliers by citing their own data sheet entries that support your design decisions.
• “Electrical overstress” can occur due to numerous possible causes, such as ESD, over voltage, over-current, excessive power dissipation etc. Your prior circuit analysis during design verification should rule out these possibilities. Encourage semiconductor supplier engineers to sign off your circuit analysis. This will reduce their chances of later claiming “electrical overstress” as a diagnosis.
• Be mindful of correlating production batch codes with culprit chips. During another of my experiences, this one more recent, I encountered randomly misbehaving CPU chips in one of the ECU failures I was analyzing. I was amazed to learn that all of these culprit CPUs also contained the same production batch codes. No semiconductor supplier will openly admit to quality issues in its own manufacturing plants, even if they’ll all hopefully take corrective action internally.
• Always keep in mind that a random root cause, such as ESD mishandling, cannot cause a consistent failure such the exact same pin misbehaving every single time.

Fortunately, we hit upon the corrective solution to the seemingly intractable field issue quite early, which otherwise would have led to a substantive loss of business for our vehicles and company.

Vishwas Vaidya is a graduate of the Indian Institute of Technology in Delhi, India. Currently, he is self-employed as an engineering consultant and industry faculty member in the field of embedded systems for global automotive clients and high-repute academic institutions. Vishwas’ articles and research reports have appeared in many worldwide engineering publications.

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The post Overstressed over an erratically flickering check-engine lamp appeared first on EDN.

Autonomous systems are making the transition from controlled pilot operations to large-scale deployment across transportation and industrial environments. Additionally, AI training facilities are scaling up to host thousands of AI agents operating concurrently to execute various tasks and build extensive training sets for AI models.

As these systems scale, most of the attention has focused on advances in compute, model performance, and system intelligence. One equally critical but often overlooked constraint is the network infrastructure, which will be required to transport massive amounts of data.

That challenge becomes apparent in environments where many untethered systems operate in close proximity. For example, in a robotaxi depot or factory floor, large numbers of mobile, autonomous systems generate and transfer data at the same time.

Here, the limiting factor is not simply bandwidth, but the network’s ability to sustain multiple high-throughput data streams within a confined physical area—effectively a problem of data density.

Figure 1 Wireless environments such as robotaxi depot hosting many untethered systems in proximity can’t sustain multiple high-throughput data streams within a confined physical area. Source: Peraso

Edge AI and the 10K challenge

In the early 2000’s, we faced what was called the “1000x challenge” as the data communications industry considered how to upgrade fixed and wireless networks to support high-speed access to human customers. As edge AI evolves, data demand is scaling in localized areas by at least another order of magnitude, presenting the 10,000x challenge.

Unlike human-oriented connected devices, which send human-digestible amounts of traffic, these systems continuously produce large datasets as part of normal operation. Cameras, LiDAR, radar, and other sensors capture detailed information about the physical world, often accumulating terabytes of data over short periods of time.

At the same time, the models that power these systems continue to grow. It’s common for operating models to reach several gigabytes and need regular updates to reflect new data and performance improvements. This creates a steady cycle of uploading raw data and downloading updated intelligence.

The effect is a network demand model, which is very different from human-driven demand. Traffic is less sporadic and is heavily upload-biased as systems dump their accumulated experience data. With numerous systems operating in a defined area, demand is constantly high in volume.

Data density becomes the limiting factor

When many autonomous systems operate in close proximity, a supporting wireless network is needed not only to provide high link speeds, but to do so consistently for every client system in the operating space. The defining factors for the network are not only link speed but also data density.

The constraint shows up clearly in places like autonomous vehicle depots, robotics-heavy factories, and AI training facilities. These environments concentrate large numbers of systems into relatively small areas. Each one generates data during operation, uploads it for processing, and receives updated models in return. When many systems follow this cycle at the same time, demand becomes highly synchronized.

Where wireless approaches fall short

If all autonomous systems were stationary, then more cables, fiber, switches, and routers could be installed to provide each device with its own multi-gigabit connection to the network. Mobile systems require wireless connectivity, and the analogy is that more access points or distribution nodes are required to increase data density.

This is where real physical constraints enter the picture: a fixed amount of frequency spectrum and bounds on the amount of data, which can be transported within that frequency space. That translates into very high-density data service that requires reuse of the allocated frequency over a small physical area.

The frequency reuse capability of any wireless technology is determined by how well neighboring access points and clients can isolate their signal from neighboring systems using the same frequency. In other words, a frequency reuse metric is defined by the ability of each terminal to focus its transmission energy, defined as antenna directivity, and the tolerance of each receiver to interference created by its neighbors, which is defined as a signal-to-noise-and-interference-ratio (SNIR) threshold.

Wi-Fi technologies in the sub-7 GHz spectrum, such as multiple-input and multiple-output (MIMO) and 4096 QAM modulation, have done an amazing job at increasing the capacity of each channel, pushing capacity close to the Shannon bound. However, this capacity comes with constraints. Maximum throughput requires very high SNIR use of wide channels, which are in short supply within the allocated spectrum. Moreover, designers must maintain high space-time diversity in order to support multiple MIMO streams.

Furthermore, the realization of high antenna directivity in a phased array configuration, which allows beam steering, is determined by the number and spacing of antenna elements. These factors scale with the carrier frequency, so antenna arrays for higher frequencies are proportionally smaller than antenna arrays for lower frequencies.

Wi-Fi systems generally have one antenna element for each spatial stream. Top-tier Wi-Fi systems can support 16 spatial streams, but rather than setting the antenna spacing at a distance of ʎ/2 for optimal beamforming, antenna spacing is optimized to provide the spatial diversity needed for MIMO operation.

Given a wavelength of 5 cm for a 6-GHz carrier, a square array of 16 elements would typically be 15 cm (1ʎ spacing) to 45 cm (3ʎ spacing) per side. These larger dimensions increase beamwidth and reduce spatial directivity. Additionally, each antenna element will be on the order of 0.5 to 1 ʎ (2.5 to 5 mm).

Since the ability of sub-7 GHz Wi-Fi to scale for high data-density is limited by the carrier frequency and subsequent antenna dimensions, we are led to consider millimeter wave frequencies, which can reduce the antenna element and array sizes by an order of magnitude. Two frequency bands for consideration are 28 GHz, as supported by 3GPP FR2 standards, and 60 GHz, as supported by 5G FR2-2 (or U) and “WiGig” IEEE 802.11ad/ay.

Figure 2 The 60-GHz technology ensures zero interference while operating many wireless networks in the same space simultaneously. Source: Peraso

5G mmWave technology can provide high throughput and high directivity, but some practical limitations impact its suitability for many edge AI applications. First, when considering the 28-GHz band, which represents the primary deployment of 5G mmWave equipment, it’s important to understand that it is a licensed band and is often heavily subdivided. Operation in this band for private networks will be complicated by the need to lease spectrum from the primary holder.

This consideration would not apply to 5G systems designed for the 60-GHz unlicensed band, but in reality, very little hardware has been developed supporting 60 GHz, as few operators want to deal with unlicensed band operation when they have heavily invested in swaths of protected spectrum.

A second consideration for any 3GPP-based equipment is cost. Designed to meet the needs of major network operators, a small cell, indoor node may cost $10 to $15k, and an outdoor RU can easily double the cost. Compared with the economy of WiGig-based 60 GHz, 3GPP-based solutions cannot actively address the edge AI scaling challenge.

WiGig meets high-density edge AI challenge

From inception, IEEE 802.11ad and subsequent 802.11ay standards, commonly known as WiGig, were designed to provide high data density. Leveraging up to 14 GHz of contiguous spectrum with a carrier wavelength of about 5 mm, small high directivity antennas at the access points and client terminals realize multi-gigabit throughput per channel with high isolation from neighboring connections. Furthermore, with no interference from common Wi-Fi, 60-GHz networks can be implemented with high confidence in the availability of clear channels.

In contrast to sub-7 GHz Wi-Fi, WiGig’s data capacity is not dependent on multi-stream MIMO, thus antenna elements can be spaced at ʎ/2 (about 2.5 mm) in order to provide optimal shaping of the antenna beam. With such a small wavelength, the number of antenna elements can also be reasonably scaled up to tailor the beamwidth for the required frequency reuse and resulting data density.

A new breed of integrated 60-GHz products demonstrates proven solutions to the data-density challenge. Providing RF and baseband ICs with compact PCB integrated antennas, these modules make it possible to develop and deploy systems where data density, reliable performance, and cost all matter.

From connectivity to data movement

As data density increases, we should not overlook the fact that it places greater demands not only on the wireless infrastructure, but also on the backend network resources and backhaul. That’s because datasets acquired by autonomous systems must be transported to the AI training engines, which will continuously evolve in terms of operating models and new models provided to the systems in the field.

Net capacity demand needs to be addressed throughout the network, which opens the opportunity for innovations in decentralized AI learning systems. That, in turn, places more learning resources close to the network edge. As this capability evolves, we envision a level of high integration between the wireless network and the local controller, which will ensure reliable data transfer for all domain clients.

Edge AI systems are increasing both the volume of data and the concentration of that data within physical environments. So, as deployments scale, performance will depend on how well networks handle these conditions.

Here, data density provides a useful way to think about the problem. It focuses attention on the limits that appear when many systems operate together, rather than looking at devices one at a time.

Wireless technologies that support high levels of spatial reuse and efficient short-range communication are well positioned to meet these demands. As edge AI continues to expand, those characteristics will matter more than incremental gains in peak speed alone.

Michael Hamilton is VP of business development at Peraso Inc.

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• Designing edge AI for industrial applications
• Edge AI powers the next wave of industrial intelligence
• Why Connectivity Has Become an Edge AI Design Decision
• Edge AI Is Forcing a Rethink of Predictive Maintenance Architecture

The post Data density: The constraint reshaping wireless for edge AI appeared first on EDN.

Why did some things happen? Why didn’t others…and what happened instead? To what extent (if at all) were the outcomes predestined? And what outcomes beg for further study?

Ten months back, as I’m writing these words in mid-August 2026, I never would have imagined the long and winding road that awaited me when I realized last October that a water hydrant replacement across the street had inadvertently led to a Comcast outage for my wife and I, along with our next-door neighbors.

The path from there to here has admittedly had no shortage of twists and turns, not to mention frustrations. But (fingers crossed that I don’t jinx myself by typing these words) we’re now at the point where we once again have stable service, thanks in no small part to the most recent technician interaction.

I’ve learned a lot along the way. And the combined fruits (hopefully not rotten) of my experiences and education will likely manifest in further editorial content for quite some time to come…

…starting today, with the latest (last?) entry in my recent series, which began with these pieces:

• Debugging intermittent Comcast, part 1: Scenario-setting
• Debugging intermittent Comcast, part 2: Remediation details

As I wrapped up part 2, I was three-plus weeks into my respite of resurrected broadband and television service stability. It’s now been exactly six weeks, and my connection has remained stable through weather both hot and moderate, and dry and rain-drenched, at least as far as I can tell. Brief outages that escape attention are always a possibility, although my Google Nest-based LAN, Blink cameras and TP-Link sensors, and QNAP NASs are generally quick to log and alert me to broadband drops. To that latter point, summer monsoon season is once again here with a heavy-lightning vengeance, so I’m also abundantly grateful for the newly added earth ground tether.

I’m going to subdivide this concluding (maybe) writeup into several main themed sections:

• Why did the most recent service visit’s technician tweaks seemingly do the trick?
• What’s with that mysterious Comcast-labeled box on the side of the house, not to mention the realtor’s mention of a second service feed put in by the prior owner?
• And why isn’t my broadband service even speedier than it already is?

Without further ado…

Hardware replacements, retirements, and most-likely effective candidates

As a brief reminder—read part 2 for the full details—the technician had swapped out an archaic (predating our home ownership) three-way splitter and 11-year-old (purchased and installed by me) MoCA PoE filter combo outside of our home.

The replacement hardware took the form of a filter-inclusive grounding block.

As I mentioned last time, the componentry inside either/both legacy pieces of gear could have degraded due to environmental extreme-temperature, moisture or other related exposure, and lightning EMP-induced damage. More likely, the splitter was inherently a culprit due to the unavoidable signal insertion loss through it. I realized after the technician left that he’d taken it with him, so I unfortunately can’t say whether it was a balanced or unbalanced splitter. This distinction is critical, both inherently and (in the latter case) depending on how it’s hooked up.

With a balanced splitter, each output “leg” incurs a symmetrical 4.77 dB (ideally, more in real life) per-output signal loss, per the decibel power ratio equation:

10log10(P2/P1)

Where P2 is the measured power and P1 is the reference power. In this case, the ratio is 3. Keep in mind, too, that real-life SNR loss varies across the operating frequency range, as well as being affected by overall non-ideal component behavior, vendor-to-vendor and splitter-to-splitter variability, and the like. Here, ~5.5 dB of per-“leg” loss for a balanced three-way splitter is therefore a more commonly quoted estimate.

An unbalanced three-way splitter, conversely, is in effect a chained combination of two two-way splitters. The “low loss” leg only passes through the first two-way splitter stage, with a ratio of 2, leading to an injected signal loss of (mathematically) 3.01 dB or (real-life) ~3.5 dB. Conversely, both of the “high loss” legs, in each case with the signal passing through both two-way splitter stages between the input and output, incur 6.02 dB (mathematical) or ~7 dB (real-life) losses.

Perhaps obviously, therefore, the signal strength received at the cable modem in the furnace room (for example) notably varied, depending not only on the Comcast-fed source strength, which we already knew had been degraded by our location at the end of the neighborhood “loop”, not to mention the late-2025 repairs and mid-2026 amplifier recalibration. It was also varied by whether the three-way splitter was balanced or unbalanced, and in the latter case, where each output “leg” went.

And don’t forget about the final two-way input signal split within the furnace room, to the cable modem and networked CableCARD triple-tuner receiver. At least this specific situation is better than in the three-way splitter past, when a MoCA device was also in the mix!

This analysis assumes, by the way, that the coax cabling itself wasn’t egregiously lossy. I still think the greatest benefit came from eliminating the splitter itself, not from eradicating any degradation caused by the short cable runs originally connected to the splitter and feeding both downstairs bedrooms, particularly since I’d had a 75 ohm terminator installed at the end of each to prevent reflections and other signal distortions.

Regardless, I’ll need to keep all these factors in mind if/when I decide to reactivate any-to-all of the downstairs MoCA nodes in the future.

And if you’re wondering about potential signal loss through the PoE filter, per the specs for both original (Holland Electronics MPOE-TM) and new (PPC Broadband POEGB-1G70CW) devices, the passband injection loss is miniscule (~1 dB, frequency-dependent), assuming proper operation, that is! Stopband loss is a different matter—40 dB or 70 db—but that’s by design, of course.

Cracking the coax code

Next, let’s definitively sort out all the cable and other hardware running around outside of the house. Last time, I’d surmised that the plastic box on one wall was likely associated with the house’s legacy Comcast service, and I’d provided a glimpse of the four-way switch within it.

Here are some more views of it.

Where do its four outputs go? One heads straight up and into the attic, which baffled me until I remembered the female coax connector on an internal kitchen wall in the middle of the house’s upstairs level. I suspect (and could, I suppose, confirm by crawling around in the dusty, precarious attic) that’s where the first cable ends up.

Another cable runs both above- (presumably due to post-installation soil erosion) and under-ground to the rear of the house, where it snakes underneath the lower deck and, I’m guessing, ends up at a wall-mounted coax connector in the downstairs family room. The third traverses the outer walls, first to one side where it splits, with one output cable heading to the upstairs master bedroom. The splitter’s other output cable continues its lengthy journey to the upstairs living room on the house’s other side.

And the fourth? It’s currently disconnected and coiled up nearby the box. I suspect it was what originally fed the downstairs bedrooms, having subsequently been replaced by the newer service feed from the street mentioned earlier.

Speaking of which, what’s feeding the four-way splitter? I’d always wondered about a cut piece of coax jutting out of the ground nearby the box.

Until, that is, I learned about the earlier-mentioned tap serving our and a neighbor’s residences.

Next to it (in the background of the prior photo) is another enclosure that I’d also long wondered about.

Note the coil of coax at its base. That’s, I suspect, from the original service feed.

Remember me mentioning in part 1 that I was baffled by the two cable spans that had apparently gotten severed? I’m guessing this is why old and new taps, next to each other, with the old cabling and hardware, are not removed after being taken out of service. I did definitively confirm, by the way, that there’s no ongoing service associated with the original coax cable topology, first by unscrewing the four-way-splitter input and seeing that my service didn’t go down.

I then attached the now-disconnected coax to a spare cable modem to confirm that it didn’t detect a valid service signal. Hitron Technologies makes, or maybe more accurately used to make, a portable battery-operated device that claims to more conveniently implement this valid service-or-not function. But I can’t find it anywhere at retail any longer, and the company is non-responsive to my outreach. That said, I’d still love to get my hands on one somehow!

Last mystery, at least for this section; what about the realtor’s aside at some point during the residence purchase process that the prior owner “had another line of service installed”? Comcast doesn’t (commonly, at least, more likely at all) grant customer requests for multiple from-street feeds for a single service account, specifically to preclude the otherwise-possible scenario of multiple concurrent in-use broadband modems. But keep in mind that this all happened more than a decade ago, when corporate policies may have been different (and mind you also involved a prior owner who’s now deceased and I therefore can’t ask).

What if only one of the two feeds had a modem connected to it? And what if the customer was pugnacious (as the prior owner was reputed to be)? Particularly given that the house was at the end of the “loop”, with associated degraded signal strength, did he convince Comcast to run a second line, feeding subsets of the house’s total TV service sockets from each?

From lingering past-history evidence, I’m pretty sure that the cable modem and tethered router were originally located in one of the downstairs bedrooms. But I’m aware from various neighborhood anecdotal factoids that the prior owner had active television service in multiple upstairs rooms, too. Maybe he set up the second line of service through a fictitious business listed at that same address. Or maybe he was just (impressively) pugnacious.

Regardless, although I’d initially theorized that the realtor had meant not “had another line of service installed” but “had a replacement other line of service installed”, I’m now more inclined to take her wording literally, although the newer feed is the only one now still “live”.

Next time: DOCSIS 3.1 and MoCA 2.5

Nearing 2,000 words, I realize I haven’t yet gotten (surprise! not…) to the originally planned “why didn’t my service get better” portion of this treatise. For now, I’ll concisely cut to the chase. Even though the technician had wrapped up his early-July visit with an excited prediction, “wait until you see how fast your Internet access will be now!”, I eventually realized that Comcast’s speed tier options at my location only extended to a high-end “1.2 Gbps” downstream option.

I’m currently on the next-highest tier, the “Gigabit Plus” plan, with maximum documented downstream bandwidth of 1.3 Gbps and peak upstream bandwidth of 35 Mbps.

Earlier, I showed you a fairly typical bandwidth test result: ~850 Mbps down and ~42 Mbps up (the latter higher than promised, I’ll note). My router more generally does an automated speed test every few days, and scanning back over a month’s worth of data, the highest seen downstream bandwidth was 890 Mbps, along with a 43.3 Mbps upstream measurement.

To be clear, this speed is plenty fast for our needs. What I’m most happy about, of course, is its now-resurrected “dial tone” permanence. And given that both my current cable modem and router offer “only” 1 GbE inter-device connections, I’ll never see anything more than ~950 Mbps downstream (accounting for Ethernet protocol overhead) anyway.

That all said, being an engineer, I’m prone to tinkering regardless. Prior to doing sobering account research and fueled by technician enthusiasm, I did a bunch of testing rounds and learned a bunch in the process, all of which I’ll plan to pass along next time. Until then, and as always, I welcome your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Debugging intermittent Comcast, part 1: Scenario-setting
• Debugging intermittent Comcast, part 2: Remediation details
• Will a location change improve my MoCA?
• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• A quest for faster upstream bandwidth

The post Debugging intermittent Comcast, part 3: Retrospective analysis appeared first on EDN.

Magnetoresistive RAM (MRAM) memory—which combines RAM-like access with non-volatility to help simplify design architectures—is making headway in aerospace, defense, and other demanding systems. Take the case of Teledyne HiRel Semiconductors, part of Teledyne Aerospace & Defense Electronics, which has added Everspin’s PERSYST STT-MRAM to its non-volatile memory portfolio for aerospace, defense, and industrial applications.

The Chandler, Arizona-based Everspin Technologies is a supplier of commercially available MRAM solutions. Its 256-Mb PERSYST spin-transfer torque MRAM (STT-MRAM) is a non-volatile memory that combines RAM-like speed with the ability to retain data through power loss, system resets, and unexpected interruptions.

Spin-transfer torque (STT) technology manipulates the spin of electrons with a polarizing current to establishe the desired magnetic state of a magnetic tunnel junction (MTJ). Source: Everspin Technologies

Teledyne HiRel will initially offer Everspin’s 256-Mb PERSYST STT-MRAM as part of its memory offerings for military and aerospace systems, targeting applications such as avionics, VPX and single-board computer platforms, radar and electronic warfare payloads, satellite electronics, and autonomous systems. The tie-up will eventually expand to other PERSYST STT-MRAM products, including 64-Mb and 128-Mb options.

Teledyne HiRel will back these MRAMs with product guidance, screening flows, qualification documentation, procurement support, and obsolescence management. This will allow the collaboration to provide design engineers with screening expertise and supply continuity, ensuring availability, lifecycle planning, and long-term supply.

Why MRAM in aerospace and defense

MRAM can replace or complement NOR flash in applications that need faster updates or power-loss-safe storage. It can also reduce a design’s reliance on battery-backed SRAM, hold-up power, or capacitor-backed memory schemes.

In other words, it helps simplify architectures that would otherwise require separate volatile memory, non-volatile storage, backup power, wear-leveling strategies, or complex data-protection circuitry. “PERSYST MRAM delivers a unique combination of endurance, instant-on data retention, and high-performance operation,” said Sanjeev Aggarwal, president and CEO of Everspin Technologies.

That’s critical in aerospace and defense designs, which require memory solutions that can sustain long operating lifecycles and provide reliable performance in harsh environments. So, this partnership between MRAM supplier Everspin and Teledyne HiRel could help lower barriers to adopting MRAM in mission-critical systems for aerospace and defense applications.

Teledyne HiRel will start shipping PERSYST MRAM products from its Milpitas, California, facility in the fourth quarter of 2026.

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The post MRAMs accelerate adoption in aerospace and defense designs appeared first on EDN.

Melexis has introduced a 5-V variant of its MLX90381 Triaxis pico-resolver for compact motor systems that rely on a 5-V supply. As motors become smaller and mechanical space more constrained, integrating accurate rotor position sensing becomes more challenging, particularly when end-of-shaft sensing is not possible. The MLX90381’s resolver-based position sensing provides greater flexibility in sensor positioning than TMR-based solutions, making it suitable for automotive, alternative mobility, and robotics motor applications.

Housed in a compact DFN-6 package measuring 2.0×2.5×1.0 mm, the MLX90381 combines Triaxis Hall technology with high-speed sine and cosine analog outputs. Its ability to sense magnetic flux density in three dimensions and use selectable X/Y, X/Z, or Z/Y magnetic axis pairs allows flexible sensor placement relative to the rotating magnet. In side-of-shaft and through-shaft motor designs, the sensor can be placed below or close to the magnetic track, reducing mechanical constraints and simplifying PCB placement and tolerance management in compact assemblies.

The MLX90381 5-V provides a 2-µs output refresh rate and measures rotational speeds above 50,000 rpm for precise rotor position detection in DC, BLDC and PMSM motors. Programmable sensitivity and filter bandwidth enable performance optimization, while I²C supports device configuration and production calibration.

Samples of the MLX90381 5-V are available now. Target use cases include e-valves, robotic actuators, cadence sensing, and motor applications for braking, steering, and seating.

MLX90381 product page

Melexis

The post Resolver enables flexible motor sensor placement appeared first on EDN.

NVIDIA’s Jetson Orin Nano 2 system-on-module delivers nearly twice the inference performance of its predecessor, the Jetson Orin Nano Super. The performance boost comes from improved Tensor Cores and higher memory bandwidth. Nano 2 also maintains the same compact form factor as the Nano Super while consuming 40% less power in 15-W mode.

The robotics computer enables developers to build robots, delivery and inspection drones, and vision AI systems with advanced generative AI capabilities. NVIDIA says the Nano 2 combines up to 78 TOPS of AI performance, 8 GB of memory, and an 8-core Arm CPU in a cost-effective, power-efficient design.

Built on NVIDIA’s open software stack and supported by Jetson agent skills and a rich AI ecosystem, Jetson Orin Nano 2 allows developers to run the latest large language models (LLMs) and vision language models optimized for memory-efficient edge inference. These include open models such as NVIDIA Cosmos, NVIDIA Nemotron, Gemma 4, and Qwen 3.

The NVIDIA Jetson Orin Nano 2 module and developer kit are expected to be available in the first half of 2027.

NVIDIA

The post Robotics computer doubles edge AI performance appeared first on EDN.

SECO announced early access to hardware samples of its SOM-SMARC-Dragonwing-IQ8 module for industrial edge AI applications. Developed with Arduino and Qualcomm, the SMARC 2.1.1 module enables the transition from Arduino Ventuno Q prototyping to production-oriented architectures for AI-enabled robotics, smart machines, industrial vision, HMI, and machine control.

The system-on-module leverages the Qualcomm Dragonwing IQ-8275 processor, with AI acceleration options of up to 40 TOPS to meet various performance and price points. It provides up to 32 GB of LPDDR5/LPDDR5X memory and up to 1 TB of UFS 3.1 flash storage. Connectivity interfaces include Gigabit and 2.5-Gigabit Ethernet, PCIe Gen4, MIPI-CSI, and CAN-FD.

Developers can build and validate designs on the Ventuno Q and use the Arduino App Lab to port them to the SOM-SMARC-Dragonwing-IQ8. The module runs Clea OS, based on Yocto Linux, providing a consistent software baseline for secure lifecycle management, OTA updates, and connected device scalability.

A limited number of SOM-SMARC-Dragonwing-IQ8 samples are expected to be made available to select customers and partners for evaluation. Register here to receive updates on priority access.

SOM-SMARC-Dragonwing-IQ8 product page 

SECO

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