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Engineers are redefining energy by looking not at massive grids but at the overlooked flows around us. Rain gutter generators that channel storm runoff, tap-mounted turbines spinning with household water, and balcony-scale wind turbines catching urban breezes prove that power can be harvested wherever motion exists.

These micro power generators embody the spirit of engineering empowerment, transforming ordinary infrastructure into sustainable energy assets. By designing systems that thrive on the smallest currents, engineers are not just solving technical challenges; they are enabling a future where autonomy, resilience, and sustainability are built into the everyday fabric of life.

Harnessing gravity: Micro hydro power

You don’t need a colossal dam to tap into hydroelectricity—gravity and flowing water are enough. Whenever water moves downward, whether from a rooftop gutter or a household faucet, it carries kinetic energy that can be captured and converted into usable current.

Micro hydro systems thrive on small vertical drops, known as “head,” which create surprising pressure even in everyday settings. A rain gutter turbine, often built around a miniature Pelton wheel, can be placed at the base of a downspout so that rainfall from a two-story home delivers enough head to charge an outdoor battery bank, turning stormwater into renewable energy storage.

Faucet hydros, on the other hand, are pocket-sized turbines that screw directly onto sinks or showerheads, producing between 5-V and 12-V DC—the perfect range for powering smart water temperature displays, LED bathroom lighting, or other low-voltage gadgets. Together, these simple setups prove that even the smallest streams of water can be harnessed to generate clean electricity, making hydro power accessible at the scale of everyday living.

Figure 1 Micro-hydroelectric power generators convert kinetic energy from small water streams into sustainable electrical power. Source: Author

Catching the breeze: Urban wind

Just as falling water can be harnessed for energy, moving air offers another everyday source of clean electricity. Standard windmills are massive, but compact vertical axis wind turbines (VAWTs) are reshaping the landscape for residential use. Unlike the towering three-blade giants on hillsides, these turbines resemble kinetic sculptures, blending into urban settings while quietly generating power.

Their design makes them safer for birds, more tolerant of turbulent wind bouncing off fences or house walls, and ideal for small spaces where airflow is unpredictable. With the ability to charge 12-V batteries, they provide reliable energy for garden sheds, security cameras, or other low-voltage systems, proving that even the breezes swirling through neighborhoods can be transformed into practical power.

Figure 2 Mini wind turbines harvest kinetic energy from turbulent urban breezes to provide localized renewable power. Source: Author

Harvesting the invisible: RF and Wi-Fi

If water and wind can be turned into electricity, why not the invisible waves that surround us every day? It may sound like science fiction, but it’s pure physics: electromagnetic energy from routers, cell towers, and radio stations constantly fills the air. RF energy harvesters capture this ambient power using a specialized antenna called a rectenna, which converts radio frequency signals into direct current. The output is small—usually measured in microwatts (𝜇𝑊)—but it’s enough to sustain ultra-low-power devices.

Imagine a moisture sensor in your garden that never needs a battery because it feeds on the Wi-Fi signal leaking from your window, or a network of “batteryless” sensors quietly monitoring conditions without ever needing replacement. By tapping into the invisible spectrum, RF harvesting extends the idea of micro power generation into the realm of everyday signals, proving that even the unseen can be harnessed for sustainable living.

Figure 3. The AEM30940 PMIC manages energy extraction from piezoelectric, micro-turbine, or high-frequency RF sources. It simultaneously charges a storage element while providing two independently regulated output voltages to power system components. Source: e-peas

Power from difference: Thermal energy

Just as water and wind can be harnessed for electricity, temperature itself can drive power generation through the Seebeck Effect. When one side of a material is hot and the other is cold, electrons begin to move, creating a voltage difference that can be captured as usable current.

This principle is already at work in stove-top generators found in many off-grid cabins, where a thermoelectric fan sits with its base on a hot wood stove and its top cooled by surrounding air. The temperature gradient produces enough electricity to spin the fan, circulating warmth throughout the room without external wiring.

On a smaller scale, wearable thermoelectric generators (TEGs) are emerging as a way to harvest body heat, powering fitness trackers and other low-power devices directly from the warmth of your skin. By turning everyday temperature differences into electricity, thermal energy harvesting extends the reach of micro power generation into both rustic cabins and modern wearables, proving that even the contrast between hot and cold can be transformed into sustainable current.

Figure 4 Stove-top thermoelectric generators convert waste heat into usable electricity. Source: TEG

Sunbeams to volts: The “magic” of micro-solar

At its heart, solar is the only micro-generator that feels like literal magic: it has zero moving parts, no loud turbines, and it runs on nothing but daylight. The fundamental “trick” is simply catching photons to knock electrons loose, creating a silent flow of power. Today, this technology is defined by “energy independence in a box,” where ultra-portable power stations—utilizing long-lasting LiFePO4 batteries and AI-driven energy management—allow anyone to build a personal power grid in minutes.

We’ve come a long way from the flimsy calculators of the 90s. From high-efficiency bifacial panels that harvest light from both sides to the emergence of perovskite-silicon tandem cells that pack 25% more power into the same small footprint, solar micro-generators provide a fuel-free alternative to traditional engines.

Whether it’s a balcony-mounted micro-inverter system or a foldable camping mat, solar is no longer just a “green” alternative; it’s the most reliable, scalable tool for decentralized power in our modern world. It’s basically like having a tiny, silent utility company that you can carry in your backpack.

Figure 5 N-type TOPCon dual-glass bifacial solar panels maximize energy harvesting by capturing incident sunlight on the front surface while simultaneously absorbing reflected light from the rear. Source: Author

Power of a pulse: Stepping into piezo power

While solar catches light, piezoelectric generators catch movement. The fundamental principle is almost toy-like in its simplicity: certain materials, like specialized ceramics or crystals, generate an electric spark when you squeeze or deform them.

In the world of micro-generation, this means turning everyday “wasted” energy—like the thud of a footstep, the vibration of a passing train, or even the pulse of a finger on a keyboard—into usable volts. Today’s technology has miniaturized this into “energy harvesting skin” and thin-film polymers that can be embedded into everything from smart sneakers to bridge supports.

Unlike solar, which needs the sun, or wind, which needs a breeze, piezo power only needs action. It’s the ultimate “hidden” generator, silently sipping energy from the vibrations of the world around us. While a single “squeeze” might only power a tiny sensor or a wireless signal, scaling this tech into “smart floors” or wearable fabrics is turning the human body and our infrastructure into a living, breathing power plant. It’s the fundamentals of physics turned into a literal “walk in the park” for renewable energy.

Figure 6 Cantilever piezoelectric harvesters convert mechanical strain from bending and vibrations into usable electrical energy. Source: Smart Material

Designing lean systems for ultra-low power

For engineers and makers, the frontier of micro power isn’t just about capturing energy; it’s about designing lean, ultra-low-power systems that thrive on the tiniest trickles of current. By leveraging efficient voltage regulators, sleep-mode microcontrollers, and energy-aware communication protocols, you can stretch microwatts into meaningful work.

Smart design tricks—like duty-cycling sensors, harvesting capacitors for short bursts, and matching generator output to the load—transform fragile prototypes into reliable systems. Today’s ecosystem of modular rectennas, plug-and-play thermoelectric modules, and ultra-low-power ICs makes experimentation easier than ever, giving designers the tools to tailor micro power generators for domains ranging from smart homes to wearables.

Power your world with micro generators

Today’s maker landscape is rich with possibilities: micro hydro turbines, mini vertical-axis wind kits, piezo energy harvesters, and even RF harvesting modules are widely available online, often bundled as DIY systems that simplify setup for hobbyists. Many components—Pelton wheels, turbine housings, and airflow vanes—can be 3D-printed from open-source designs, making customization affordable and accessible.

Dedicated ICs such as ultra-low-power boost converters, energy harvesting PMICs, and rectifier-regulator modules are designed to stabilize and store trickle currents, while plug-and-play thermoelectric generators extend experimentation into thermal domains. With kits, printable parts, and specialized electronics at hand, building micro power generators across water, wind, signal, heat, light, and vibration/impact sources has become a practical weekend project rather than a distant engineering challenge.

The possibilities are here and the tools are ready—so why wait? Shock your imagination, spark your designs, and start building micro power generators that turn everyday forces into lasting energy solutions.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Micro Hydro Generator
• Energy Harvesting Block Diagram
• Micro-Harvesting Will Not Power Our Planet
• What’s Happening in the World of Micro-Energy Harvesting?
• Platform design for testing vibration to electrical power generators

The post Micro power generators: Turning everyday flows into energy appeared first on EDN.

The market for commercial autonomous vehicles (AVs) is poised for explosive growth over the coming decade, and 4D imaging radar has a key part to play. 4D radar, which offers a 4D view combining distance, velocity, position, and vertical resolution, will help AV companies deploy autonomous fleets in real-world environments faster while also building the potential to scale such deployments rapidly.

The autonomous truck market alone is set to rocket from $50.8 billion this year to $158.7 billion in 2035, at a compound annual growth rate of 13.5%, according to a research report by MarketsandMarkets. With technology the key driver of growth, according to the researcher, the adoption of advanced sensors such as 4D radar, alongside high-performance computing platforms and AI-based software, is vital to this expansion.

However, one of the key challenges facing the sector is that 4D radar solutions have, until now, tended to operate as closed systems, meaning that access to the raw data is limited. Newer systems, such as bitsensing’s AIR4D imaging radar, will help enable developers and AV companies to continuously refine vehicles’ perception models and validate their performance.

In turn, this will accelerate the path from testing new systems to safe and large-scale deployment in real-world fleets. This will drastically speed up the commercialization of AVs worldwide.

In contrast to sensors such as LiDAR and camera sensors, radar offers key advantages that will be vital to driving real-world use in the commercial vehicle sector. It is safe, cost-effective, and proven, and it is already widely incorporated into advanced driver-assistance systems (ADAS) to offer the velocity accuracy needed for ADAS functions such as automatic emergency braking. This is a well-known technology and already evolving into more advanced 4D systems, suited for commercial vehicles.

Radar systems work in all weather conditions (cameras, for example, struggle in fog and low-light conditions as well as over longer ranges). The latest radar systems work comfortably at ranges of more than 200 meters and have low power consumption. The technology can easily be integrated into vehicle systems, with manufacturers already building systems designed specifically for the commercial AV market.

4D radar delivers high-resolution, real-time environmental mapping and integrates with cameras to deliver a comprehensive perception system. (Source: Adobe Stock) The 4D advantage

The reason 4D radar is so important for the rapid commercialization of AV technology is that it enables the rapid classification of different kinds of road users (for instance, pedestrians, buses, and cars). This will play an important role in enabling trucks, buses, and robotaxis to move safely through city streets, whether in Level 2 or 3 autonomy (where driving is conditionally automated) and moving toward Level 4 autonomy (where driving is highly automated, with vehicles capable of driving fully autonomously in real-world settings without the assistance of a human driver).

The reason 4D radar is so powerful is that it instantly senses distance, velocity, and position, along with vertical resolution. This means that anything “seen” by the vehicle has not only movement but also shape and altitude. This allows vehicle systems to sense how quickly an object is moving and rapidly categorize it as a certain class of vehicle, such as a motorbike or truck, or a pedestrian.

The rapid adoption of 4D radar will be a key growth driver in commercial AVs. Today, some robotaxis already ship with more than 20 advanced 4D sensors, and this will become a key trend across the market for commercial vehicles. Analysis by ResearchAndMarkets found that 169 million radar sensors shipped globally in 2024, translating into 0.8 long-range radars per vehicle and rising to one per vehicle by 2030.

The adoption of regional regulatory mandates (such as the EU’s Vehicle General Safety Regulations) is also helping to accelerate the growth of commercial AVs. The latest radar sensors offer both horizontal and vertical resolution, enhancing obstacle-detection and collision-avoidance capabilities. This means they can cope with any road conditions and any weather conditions, complying with the new regulations.

Built for commercial vehicles

To really drive the commercial AV market forward, it’s also vital that sensors are purposely designed for full autonomy, rather than being repurposed from devices for the consumer market. Today, many 4D radars were developed for use in ADAS, rather than being built from the ground up for full driverless functionality.

To truly deliver the information that AVs need, these systems should be optimized to deliver 4D sensor data directly to the AI models in these vehicles. They should also be optimized for power and heat efficiency. These features will be vital for real-world operation.

Going forward, a camera-plus-radar architecture will also be crucial to offering a viable path to curbing per-vehicle sensor costs. This will help to drive faster AV deployment on roads around the world. These are some of the design factors that we have also considered with our own work, including with the AIR4D imaging radar.

The AIR4D imaging radar is purpose-built for AVs, which is critical for full autonomy. (Source: bitsensing Inc.) Increasing accuracy

The latest radar sensors build on the strengths of the technology to offer higher performance than rival sensors, such as LiDAR and cameras, with long-range detection up to 300 meters and the ability to operate in near-total darkness. This allows commercial vehicles to maintain awareness even on poorly lit roads in the middle of the night.

The ability to measure direct velocity per object is also helping to enable faster and more accurate decision-making, with the latest radar sensors able to measure the speed and direction of vehicles, cyclists, and pedestrians in real time. This means that radar alone can provide full spatial accuracy. With previous generations of 3D radars, other sensors were relied on to create a “full” image of the objects moving in the surrounding environment.

Today, AVs equipped with 4D radar can build a high-resolution, real-time spatial picture of their environment across all four dimensions. This is what safe autonomous driving demands. With 4D radars penetrating even snow and rain and able to integrate with cameras, radar is the foundation of a comprehensive perception system, which will be the building block of autonomous driving.

Toward safer bus fleets

There are many factors that make radar sensors appealing in a commercial context, especially the “weather-proof” nature of the technology. Commercial fleets, such as the use case of buses in Korea, are already adopting radar-based technology through initial pilot schemes, with further plans to expand fully to intercity bus routes.

Critically, these ADASes have modularity at their heart, with features that can be easily added to existing vehicles. These functions, such as forward-collision warning, enable buses to precisely detect vehicles and pedestrians, even in the most demanding environments or roads.

A 4D future

The dawn of the commercial AV era is upon us today, and to drive forward into this future, it’s clear that 4D imaging radar has a vital role to play. Not only will 4D radar help to overcome the limitations of previous sensors, such as LiDAR and cameras, but it also transcends the limitations of previous radar systems, with the latest sensors purpose-built for seamless integration into the fleets of tomorrow.

The post Why 4D imaging radar is critical to AV commercialization appeared first on EDN.

Have you heard of the golden ratio? Well, what about the gold-colored guitar fret ratio?

I’ve been listening lately to classical guitar musicians on YouTube. Such skill and artistry is utterly astonishing. After a while, though, I got curious about how the guitars were made and how they achieved their frequency outputs. I noticed something. I took a screen shot of a guitar’s strings and fretboard and, by counting pixels, I measured the dimensions seen in Figure 1:

Figure 1 Guitar fret positioning is definitely not random, acoustically speaking.

I then looked at the ratios of a string’s fret-to-base length (my choice of term) to that of the next shorter one (Figure 2):

Figure 2 Length ratios: the ratio of each fret position taken in pixels divided by that of the next fret closer to the base is the ratio of the frequencies of each note of the string. That ratio is nominally 2^(1/12) =1.05946… which is approximated in each and every case. The average of the calculations as shown here comes to 1.058422 which is only 0.1% in nominal error.

I discovered that in spite of my crudeness in using the pixels, the ratios come out very close to the twelfth root of two. That ratio is the ratio of adjacent note frequencies of a tempered musical scale. If the full length of a string is taken as “Do” in its particular key, the fret positions yield the twelve-tone-scale arrangement of notes seen in Figure 3. In hindsight, I guess I should have intuitively known this but I didn’t. I do now.

Figure 3 Tempered scale: taking the full length of each string as the note “Do” as in Do-Re-Mi-Fa-Sol-La-Ti-Do scaling, we see how each fret position corresponds to one of the twelve notes (including sharps and flats) of the Western culture’s twelve-tone scale.

It should be noted that singer Jimmie Rodgers once admitted that he couldn’t really play the guitar as he performed, so he tuned the six strings of his guitar to be in open string harmony. Then when he was performing, he would keep one finger, his thumb, across all six strings at the same time across the fretboard. Since all six strings followed the above length versus note pattern, the six strings were always in harmony. He was using a single, movable chord.

Watch how his left hand does that in the following YouTube videos and enjoy the music.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Earplugs ready? Let’s make some noise!
• A pitch-linear VCO, part 1: Getting it going
• A pitch-linear VCO, part 2: taking it further

The post Guitar Frets appeared first on EDN.

Part 2 of this series covered the user-space tooling stack—cxl, ndctl, daxctl, numactl, lspci, and setpci—and walked the boot path from power-on through DRAM training, DVSEC and HDM reporting, decode programming, CDAT delivery, ACPI table handoff, and OS driver binding. It framed each stage as a validation gate so you can tell whether a failure is rooted in link training, capacity reporting, firmware tables, or policy—not only in application behavior.

Part 3 turns that framework into hands-on practice. You will learn how CXL memory may surface as system RAM or Device DAX, when to use daxctl and boot parameters such as efi=nosoftreserve, how to confirm expander memory as a distinct NUMA node, how to decode key lspci fields for link health and CXL.mem enablement, and how to drive targeted traffic with numactl and standard stress tools. So, you can separate transport defects from NUMA misconfiguration before closing bring-up or sign-off on CXL Type 3 device validation.

Integration modes: System RAM and Device DAX

CXL Type 3 host-managed memory may integrate in more than one way. The platform and kernel can expose it as conventional system RAM, or as persistent-memory-class capacity that surfaces as Device DAX character devices (for example /dev/dax0.0). The daxctl utility and libdaxctl can reconfigure those DAX instances; for example, switching a region to system-RAM mode so the same physical capacity behaves like normal DRAM instead of a raw DAX mapping, subject to firmware and driver support.

To reconfigure a device that appears as /dev/daxX.Y to system RAM:

sudo daxctl reconfigure-device –mode=system-ram daxX.Y

Firmware can mark some memory ranges in the system map as EFI “soft reserved.” Think of that map as the machine’s inventory of RAM, soft-reserved means, “this range exists, but do not treat it as ordinary free RAM yet.”

That pattern is common when capacity comes from persistent memory (PMEM) or CXL Type 3 expanders, because the platform often wants the OS to decide later whether that capacity should behave like normal DRAM or be exposed as a Device DAX mapping (a special character device such as/dev/dax0.0). By default, Linux honors those soft reservations, which leaves the memory set aside instead of freely handing it to applications as regular RAM.

The boot parameter efi=nosoftreserve changes that policy. It tells the kernel: do not keep soft-reserved areas reserved so the OS can bring that capacity online in the mode operators want (typically system RAM) when the firmware’s soft-reserve marking does not match the deployment goal.

Use efi=nosoftreserve only when your platform vendor or bring-up guidance says it’s appropriate. Applied without that context, it can change how capacity appears (RAM vs DAX), affect NUMA topology, and complicate debugging when firmware and OS expectations disagree.

Verifying NUMA topology

Use numactl to confirm the expander enumerates as its own NUMA node:

numactl -H

Figure 1 Sample numactl -H output on a two-socket system with 2 CXL devices, where each CPU is a NUMA node with native DRAM. Node 0 and node 1 show socket-local DRAM and the CXL devices appear as node 2 and node 3 with 128 GB of memory (each) and no local CPUs. This memory-only NUMA node pattern is common for Type 3 expanders and is the baseline for placement-aware testing. Source: Author

Initial sanity checks with lspci

lspci shows whether the CXL endpoint is present and reports vendor/device ID, class codes, PCIe link width and speed, and related DVSEC register status. It’s a fast first check before chasing firmware decode, driver bind, or memory-onlining issues.

lspci | grep -i cxl

lspci -s <BDF> -vvvv

Decoding key lspci fields

Device link width and speed

LnkCap and LnkSta should match expectations (for example speed 32GT/s, width x16). Unexpected degradation signals an unstable link and issues at the electrical layer. This must be resolved before proceeding further.

Figure 2 lspci output showing the negotiated PCIe link speed and width for a CXL Type 3 endpoint. Source: Author

CXL capabilities and status

CXL DVSEC blocks use Vendor ID 0x1E98 and a DVSEC ID identifying the structure type. A healthy device advertises both CXL.io and CXL.mem under CXLCap/CXLCtl. If CXL.mem is disabled (CXLCtl Mem-), possible causes include DRAM enumeration failure or the host failing to assign address space. HDMCount 0 is a red flag. When memory enumeration fails, verify DIMM compatibility and mounting, and use vendor SDKs to probe internal controller registers via out-of-band access where available.

Figure 3 CXL DVSEC capability and control fields showing CXL.io and CXL.mem enablement, HDM decoder configuration, and active memory ranges. Source: Author

Address range and Active bit

Device firmware can be set up to include the entire HDM in one range or split it into two. The range fields reflect the size and which range is active. Range fields should translate to the full HDM size with Valid+ and Active+ set. Otherwise, it indicates that DDR negotiation or mapping failed. For initial bring-up, set the decoder and mailbox timeout values to their maximum supported settings to avoid premature failures during DDR negotiation.

Driver and kernel modules

Kernel driver in use should be cxl_pci. To verify kernel version, kernel 6.3 and above are recommended. During link stability testing, unlink drivers as required by your test procedure.

The cxl CLI tool for CXL memory expander bring-up

The cxl command-line utility is the user-space front-end to libcxl, shipped with the ndctl project on most Linux distributions. It walks the kernel CXL sysfs hierarchy, which includes buses, ports, endpoints, memdevs, decoders, and regions and prints structured as JSON output.

It complements lspci, which shows transport and DVSEC state at the PCI layer, and daxctl or numactl, which show how onlined memory capacity is exposed to applications. Reach for cxl after dmesg if the firmware, CXL driver, and user-visible memory policy do not agree.

What cxl exposes

At a high level, cxl list reports the objects the Linux CXL core registers under /sys/bus/cxl/devices/; root buses, switch and root ports, endpoints tied to PCI functions, memory devices (mem0, mem1, …), host-managed device memory decoders, and regions that may span one or more expanders. For single-LD Type 3 cards, the first sanity check is usually whether a memdev appears with a non-zero ram_size, a host BDF, and decoders or regions in a committed decode_state after platform firmware has programmed HDM and asserted mem_enable.

Essential commands during bring-up and sanity testing

Initial discovery

Run these early in bring-up to confirm the kernel bound cxl_pci and registered at least one memdev:

cxl list -M

cxl list -M -u

Look for memdev entries with ram_size, serial, host (PCI BDF), and numa_node when memory is onlined. An empty list or zero-sized memdev often means the device is present on the bus but not yet consumable—trace back to HDM validity, decode programming, or driver bind before chasing application issues.

Topology and decoder verification

After link-up and driver bind, verify the decode path from root port through endpoint decoders:

cxl list -vvu

cxl list -D -d endpoint -u

cxl list -P -p switch,endpoint -m memX -u

Use -vvu for buses, ports, decoders, regions, and target mapping in one view. Filter by memX or by PCI BDF (cxl list -M -m 0000:bb:dd.f) when multiple expanders or a switch is present. Decoder listings should show plausible Host Physical Address (HPA) windows and a committed state before you treat CXL-attached DRAM as usable system memory.

Region and exposure mode checks

When the platform surfaces expander memory through a CXL region and DAX subsystem, confirm how capacity is configured before running daxctl or numactl tests:

cxl list -R -RXu

cxl list -r regionN -RXu

The daxregion section reports chardev names (for example dax0.0), mode (devdax versus system-ram), and memblock onlining progress. This tells you whether the next step is daxctl reconfigure-device, memory hotplug onlining, or NUMA verification with numactl -H.

Enable, disable, and health

Type 3 expanders usually auto-enable by default. These commands matter after manual disable, hot-reset recovery, or scripted regression gates:

cxl enable-memdev mem0

cxl disable-memdev mem0

cxl list -m mem0 -H -u

enable-memdev revalidates HDM decoders and CXL.mem enablement along the port hierarchy. The -H health listing exposes maintenance, media, and error counters when the device supports mailbox health reporting—useful during long stress runs alongside dmesg and RAS logs.

Suggested bring-up command sequence

A practical first-pass sanity script on a booting system:

lspci | grep -i cxl

lspci -s <BDF> -vvvv

cxl list -M -u

cxl list -vvu

cxl list -R -RXu

cxl list -m mem0 -H -u

numactl -H

Together, these commands separate device not seen (lspci) with details of DVSEC that can be parsed for information of interest, device seen but not registered (no memdev in cxl list), decode not committed (decoders/regions), and memory online but misconfigured (numactl shows wrong node or missing capacity). That layering matches the validation mindset used throughout the “Bring-up and testing of systems with CXL Type 3 memory expanders” series.

Keeping kernel pages off CXL memory

CXL expander memory should be treated as a migratable capacity tier, not as interchangeable DRAM. Slab caches, page tables, and other non-migratable kernel structures must stay on local socket memory because they cannot be demoted or migrated and would suffer higher latency and reliability risk on CXL.

Online CXL capacity in ZONE_MOVABLE

The primary remedy is to defer CXL expander capacity only into ZONE_MOVABLE on a discrete, CPU-less NUMA node. After confirming the device with cxl list and daxctl list, reconfigure it as system RAM with the default movable policy as we saw previously.

sudo daxctl reconfigure-device –mode=system-ram daxX.Y

daxctl onlines new blocks as movable by default; avoid –no-movable. Only move blocks assigned to CXL memory to ZONE_MOVABLE. This must be done carefully; determine the NUMA node assigned to a CXL device, use the sysfs interface, /sys/devices/system/node/node2/memory*, to determine which blocks are assigned to the CXL memory and only apply the ZONE_MOVABLE attribute to those blocks by looping over the respective CXL nodes. It’s important to note that CXL memory range onlined in ZONE_MOVABLE is not eligible for 1-GB Gigantic Page allocation.

Page temperature and tiered memory placement on CXL systems

Hot, warm, and cold pages

In CXL-enabled tiered memory systems, pages are commonly classified by access frequency over a sliding time window rather than by a fixed label. Hot pages are touched often enough to affect performance while cold pages are allocated but remain idle for minutes or longer.

Production studies report that a large share of allocated memory, often well over half, can be cold in short windows. Warm pages sit between those extremes: accessed occasionally or likely to be re-accessed soon, so they tolerate slower tiers better than hot data, but still benefit from promotion if they heat up.

TPP further notes that page type matters. Anonymous heap and stack pages tend to run hotter than file-backed cache and tmpfs, and temperature can flip quickly as pages are allocated and freed, so static placement fails.

Why page placement is critical

CXL expander memory is reachable with byte-addressable semantics but at higher latency and often lower effective bandwidth than socket-local DRAM. If the OS treats all NUMA nodes as equivalent, hot working sets can land on CXL, new allocations compete with cold data for fast DRAM, and capacity-bound workloads that should tolerate tiering still lose double-digit performance.

TPP reports up to roughly 18% performance improvement over default NUMA balancing on CXL-tiered platforms, and production analyses show sharp latency-sensitivity once the hot footprint exceeds what local DRAM can hold.

For CXL Type 3 bring-up, correctness may pass with memory online, but performance sign-off requires verifying not only that CXL capacity exists, but that hot, warm, and cold pages are landing on the intended tiers under the policies that the user fleet actually runs.

Default Linux policies

Default policies start simple: allocate preferentially from local DRAM and spill to the CXL NUMA node only when fast-tier capacity is exhausted. The kernel’s NUMA balancing (numa_balancing) enables and configures automatic, page-fault–based balancing. Setting it to NUMA_BALANCING_MEMORY_TIERING (value 2) tells the kernel to treat the NUMA nodes as tiers and promote frequently accessed (“hot”) pages into the fast tier.

echo 2 > /proc/sys/kernel/numa_balancing

Memory-tier demotion (numa_demotion_enabled) under reclaim pressure moves cold pages to the slow tier instead of swapping them to disk.

echo 1 > /sys/kernel/mm/numa/demotion_enabled

Zone reclaim mode is a Linux kernel parameter that controls how aggressively the system reclaims memory from a local NUMA node when that specific node runs out of memory, rather than allocating memory from other remote nodes. It accepts one of the specified policies or a combination. Typical production knob will enable all reclaim policies.

echo 7 > /proc/sys/vm/zone_reclaim_mode

The above setting should not be used in all conditions. It’s highly recommended that the user try combinations of the above settings with benchmarks that closely resemble the workloads and use the combination that works best.

Tools for traffic generation and performance validation

While a detailed discussion of each benchmark and the traffic type deserve a separate discussion, some common benchmarks and tools are mentioned below that should help the reader get started.

Memory structural test

Memtester

Latency

Intel Memory Latency Checker (MLC) for x86 platforms

Bandwidth

Google Stressful Application Test (SAT/GSAT/stressapptest)

Google Multichase – pointer chasing benchmark

TPCH with DuckDB

Heimdall

When expander memory appears as its own NUMA node, numactl+membind forces traffic onto CXL-attached DRAM.

numactl –cpubind=0-15 –membind=2 <command to run memory traffic>

The example below runs on node 0 CPUs but allocates memory on node 2. CXL memory (see Part 1, Figure 2); swapping –membind between 0 and 2 gives a direct local-DRAM versus CXL comparison. On single-socket systems, the CXL device may enumerate as NUMA node 1.

Matching CXL link width to memory bandwidth

When sizing a CXL memory expander, usable bandwidth is not simply the PCIe/CXL rate on the connector. Traffic crosses two stages: the host-facing PCIe/CXL link and the DDR channels behind the Type 3 controller. End-to-end bandwidth is therefore the lesser of the two.

Effective Bandwidth = min(PCIe/CXL link bandwidth, DDR bandwidth behind CXL)

Recycled DDR4 is often slower, or with fewer active channels than native DDR5. Subsequently, the DRAM side can limit throughput before a full-width link saturates. In that case, a x16 link may not add much, and an x8 (or narrower) link can already match what DDR4 sustains. This frees up lanes, cutting expander cost and power, and leaving host I/O for GPUs, NICs, and other devices. Size the link to the slower of the two bandwidths, not to the maximum PCIe generation width.

A cross-layer validation mindset

CXL Type 3 memory expanders offer a practical way to grow capacity and effective memory bandwidth for data- and memory-intensive workloads where traditional DDR scaling is constrained by I/O, cost, and signal integrity. But successful deployment is not only a silicon or link problem.

Host-visible expander memory remains physically and administratively distinct from socket-local DRAM, so discovery, NUMA topology, performance, and RAS must be validated as a cross-layer problem spanning CPU, firmware, kernel parameters, device firmware, and user-space policy.

This three-part series outlined system context and platform prerequisites; the boot timeline from power through DVSEC, decode/mem_enable, CDAT/DOE, ACPI tables, and driver attach; and user-space tooling plus transport-level checks for CXL.mem enablement and HDM validation.

Future work includes switched and multi-device topologies, CXL 3.x pooling models, formal compliance automation, and standardized regression coupling protocol evidence with OS topology and workload QoS.

Acknowledgment

The author thanks Linux CXL kernel developers (the detailed notes and exchanges in lwn.net are extremely valuable), the open-source CXL community, the CXL Consortium, and platform engineers at CXL memory expander vendors and hyperscalers. Any errors remain the author’s own.

Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).

Editor’s Note

The views and content of the article are the author’s own and not affiliated to any of his current or previous employers.

Related Content

• Stripped Down CXL Scales Memory Wall
• CXL Efforts Focus on Memory Expansion
• CXL Adds Port Bundling to Quench AI Thirst
• CXL: The key to memory capacity in next-gen data centers
• From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)

The post Test, debug, and validation of CXL memory expanders appeared first on EDN.

Yours truly can’t try to do the splits without ending up in the hospital, and suspects many of you would find the maneuver equally complicated-to-impossible…as does, it turns out, USB.

In last week’s initial post of this series, I discussed ongoing imperfections in the latest-generation USB-C standard, specifically with respect to single-source-to-sink interconnect, and encompassing power transfer, data interchange, and both-simultaneously setups.

• Nebulous-at-best identified cable capabilities and their user impacts
• Polarity dependencies on resultant performance
• The broader pros and cons of an industry standard which encourages compliance but doesn’t require independently assessed compatibility

In doing so, I was following up on other points already raised in my prior coverage, based on multiple case studies personally experienced by me.

• USB: Deciphering the signaling, connector, and power delivery differences
• USB Power Delivery: incompatibility-derived foibles and failures
• USB 3: How did it end up being so messy?

That includes the necessity for “sink” devices using USB-C for power-input purposes (including charging of embedded batteries) to connect solely to power sources via USB-A-to-USB-C adapter cables, versus newer and more logical dual-ended USB-C alternatives, in order to achieve proper-operation outcomes. Such workarounds presumably result from subpar USB Power Delivery (USB-PD) implementations.

At the conclusion of that prior post, I wrote:

I’ve got one more notable USB-C-related implementation-challenge situation to discuss, but after just passing through 2,000 words, I’m going to save it for next week’s part-two post.

Background to my curiosity

That’s where today’s follow-up blog comes in. Specifically, if you haven’t already figured it out from the title and subhead, I’m going to cover splitters, which assist in interconnecting a single source with multiple “sinks”, again with power, data, or both transfer aspirations.

My main impetus for recent interest in the topic is the portable power stations from EcoFlow and others that I’ve been acquiring, using, testing, and writing about of late. Take, for example, the EcoFlow RIVER 2 that I first covered in detail in February 2025.

It has only two USB-A power outputs, both 12 W max (industry-standard 5V@2.4A, absent any proprietary QC enhancements). And although its USB-C facilities are USB-PD cognizant (5/9/12/15/20V@3A, 60 W max), there’s only one of them. So, if my wife and I both want to fast-recharge our smartphones via USB-C during an extended power outage, for example, how might we be able to accomplish this without arm-wrestling or a shouting match? With a splitter, of course.

Here’s one example of the concept, an early “category creator” market entrant, Anker’s 140W 2-in-1 USB-C to USB-C cable.

We’ll revisit it later in this piece. It comes in 4’ and 6’ length options and black and white color variants and is analyzed in detail in this Reddit thread and linked teardown.

Proportional power allocation (or not)

Back in prior-generation USB days, specifically for power splitting purposes, the implementation and usage were reasonably straightforward. The only source output voltage option was 5 V. The output current was whatever the source max’d out at. And the parallel-connected “sinks” consumed whatever subset of the available electrons each of them could successfully allocate to itself.

The only notable issues (unless I’m overlooking something; readers, let me know in the comments) with this elementary implementation were practical:

• Each “sink” device might recharge slower than if it had the source all to itself.
• Some of the “sinks” might not work reliably because their available allocated percentage of the current was insufficient for requisite power and/or recharge purposes.
• Others might not work because they required a voltage higher than 5 V (Apple laptops, for example, something I learned while researching adapters for part 1 of this series).
• And in the opposite-trend direction, if the source was subpar in its design, the high aggregate “sink” current demand might result in excessive output voltage drop sufficient to take all connected power destinations offline.

With USB-C (specifically, USB-PD), things unsurprisingly have gotten a “bit” more complicated. As my colleague Bill Schweber noted in his recent treatise on the topic, “USB-PD allows for multiple loads to be charged at the same time, each with different requirements”. And of course he’s right. But, then again, only with a properly implemented USB-PD ecosystem.

To wit, I’ve also come across plenty of case study examples on Reddit and elsewhere detailing situations, both hypothetical in their proposed root causes and confirmed by postmortem analysis, wherein someone plugged a laptop into one output of a splitter followed by a mouse, keyboard or some other more elementary device into the other output, a second device which (incorrectly) was then also subjected to the first device’s required high voltage and promptly emitted “magic smoke”, followed by demise.

So, what’s a splitter supplier to do? (At least) three options exist, as I see it:

• Bail on USB-PD and power everything by 5V@3A only (with already-discussed consequent potential functional issues).
• Negotiate with every connect device and run ‘em all at the lowest voltage that they all have in common. Safe? Sure. But also functional interruption-prone with every splitter output-tethered device connection and removal. Want your SSD to power-cycle mid-write each time something else mates with or detaches from the splitter? Me neither.
• Or follow the USB-PD spec to the nth degree, aspiring for per-splitter-output voltage and current optimization to the capabilities and preferences of the associated connected “sink” device, and hoping that your silicon and software “building block” suppliers have adequately accounted and compensated for all possible edge and corner cases.

Good luck with that, product developers and users alike.

Selective data directionality

Ready for our next implementation complication? What, if anything, do you do about your customers’ potential desires for the connection between the splitter input and any/all output(s) to transport not only power but also data? In all the product implementations I’ve come across so far (stay tuned for the details to come shortly), bidirectional USB 2.0 (480 Mbps) rates are best-case supported, either assigned consistently to a dedicated output connector or to “the first output to connect to a device,” not simultaneously to all possible splitter outputs. But why?

Keep in mind that, akin to the passive Ethernet splitters that I discussed recently, there’s no active switching going on here. That’s what more complex (and costly) USB hub devices are for, if it’s what you need. Instead, once again, (at least) three implementation options exist with humble splitters, again as I see it (sound off in the comments, readers, if I overlooked or conversely overstated something):

• Bail on data carriage and focus only on power transfer. You’ll still need to comprehend the Configuration Channel (CC) signals if you want to support USB-PD, however.
• Pick a splitter output and run the bidirectional data solely and consistently between it and the input.
• Or decide that the first device that connects to the splitter’s multiple outputs is the only one that has the opportunity, if it chooses to take advantage of it, to leverage not only power but also bidirectional data transfer facilities. And what happens when that device later disconnects from the splitter? Unclear.

Case study implementation diversity

I’ve so far collected four USB-C splitters in recent months, for both personal-use and teardown purposes. As you’ll see shortly, they handle both power and data transfer very differently, a divergence scenario that I find very interesting, as it implies leverage of different reference designs if not entirely different chip-supplier foundations (therefore the teardown angle).

In alphabetical order, beginning with the product you’ve already been introduced to earlier:

• Anker 2-in-1 USB-C to USB-C cable
  • Length options: 4’ and 6’
  • Color options: black and white
  • Outputs: 2
  • Power carriage: 140 W (max). “When two devices are used simultaneously, the first device plugged in receives higher power. The actual power each device receives depends on its power needs.”
  • Data carriage: USB 2.0 (480 Mbps) to first connected device
• Belkin 2-in-1 USB C to USB c Cable
  • Length: 5’
  • Color options: black and white
  • Outputs: 2
  • Power carriage: 140 W (max). “With two devices, smart power sharing splits power and the first device plugged in may get priority.”
  • Data carriage: USB 2.0 (480 Mbps) to first connected device

• Baseus Flash 2 in 1 USB C cable
  • Length: 4.9’
  • Color: black and white
  • Outputs: 2
  • Power carriage: 100 W (max)
  • Data carriage: USB 2.0 (480 Mbps)
    • Note: data transfer is apparently supported only in the latest v2 design. Conversely, with the seemingly initial product version I’d purchased back in September 2024, “Please note that this cable is designed specifically for charging purposes and does not support data transfer or video signal transmission.”

• MPATIBY 4 in 1 USB C cable
  • Length: 5’
  • Color: Black and grey (the version I own: various other options also available)
  • Outputs: 4
  • Power carriage: 5V-only: “The usb c multi charging cable does NOT support fast charging.”
  • Data carriage: USB 2.0 (480 Mbps), consistently and only to one of the outputs, with a uniquely labeled connector.

Online expertise recommendations, and in conclusion

Back in the early days of USB-C, when Nexus smartphones and M1 Apple Silicon-based laptops were getting destroyed by dodgy cables, hubs, chargers and other third-party implementations (or at least that’s what Apple was blaming), an engineer at Google named Benson Leung was the “knight in shining armor” that everyone was relying on to both publicly shame the miscreants and tell users what they should be buying instead. Benson’s seemingly still at Google and remains active on Reddit re USB-C matters, even though his Linkedin profile reports he’s now primarily working on other stuff.

More generally, I consistently found myself directed toward relevant discussion threads on the UsbCHardware subreddit (for which Benson is one of the moderators) as I was web searching while researching various topics in preparation for writing this piece, links to several of which I’ve already shared in both parts of this writeup series. Quality time spent there to get up to speed, while as-usual-for-Reddit filtering out the cruft, is recommended for any USB-C devotee.

And with that, I’ll wrap up for today. As always, I welcome your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• USB-C’s lingering incompatibilities and other complexities, part 1: Direct-connect complications
• USB: Deciphering the signaling, connector, and power delivery differences
• USB Power Delivery: incompatibility-derived foibles and failures
• USB 3: How did it end up being so messy?
• USB-C and Power Delivery: Too much of a good thing?

The post USB-C’s lingering incompatibilities and complexities, part 2: Splitter issues appeared first on EDN.

The aerospace industry is undergoing a profound power architecture shift. For decades, radiation-hardened (rad-hard) silicon MOSFETs were the undisputed workhorses of spaceborne DC-DC converters. However, as modern satellite payloads demand higher efficiency, tighter density, and lower mass, silicon is hitting its physical limits.

Enter gallium nitride (GaN) high electron mobility transistors (HEMTs). Boasting a wider bandgap, superior electron mobility, and inherent robustness against certain radiation mechanisms, GaN is the key to unlocking next-generation space power densities. Yet, translating these raw material advantages into flight-ready, highly reliable hardware requires a deep understanding of its unique driving requirements and its interaction with rad-hard pulse width modulation (PWM) controllers.

The rad-hard landscape: Silicon vs. GaN

Space radiation hazards generally fall into two categories: Total ionizing dose (TID) and single event effects (SEE).

In silicon MOSFETs, TID causes a build-up of trapped holes in the thick gate oxide, leading to a severe negative shift in threshold voltage (Vth) and increased leakage current. On the other hand, GaN HEMTs lack a traditional gate oxide, utilizing a Schottky or p-GaN gate structure instead. Because there is no oxide to trap charges, rad-hard GaN devices exhibit exceptional inherent tolerance to TID, often surviving exposure well past 100 krad(Si) to 1 Mrad(Si) with minimal parameter shifts.

While GaN shines under TID, SEE is where the engineering nuances lie. Silicon MOSFETs are susceptible to single event burnout (SEB) and single event gate rupture (SEGR) due to heavy ion strikes creating parasitic bipolar conduction paths or destroying the gate oxide.

But GaN HEMTs don’t suffer from traditional SEB or SEGR because they are majority-carrier devices without parasitic bipolar structures. However, they are prone to single event transients (SETs) and catastrophic degradation at high drain-to-source voltages (VDS). Under heavy ion bombardment, localized high electric fields near the drain can cause high-current leakage paths. Consequently, a VDS derating of 30% to 50% of the maximum rated voltage is standard practice for spaceflight GaN applications.

Alex Lidow, CEO and co-founder of Efficient Power Conversion (EPC), notes the physical limitations of legacy materials: “Silicon has had a glorious 60-year run, but it has hit its theoretical performance wall. In space applications, where every gram of weight translates directly to launch cost, GaN isn’t just an alternative—it’s an absolute architectural necessity.”

Driving the delicate GaN gate

The primary challenge when designing a flight-ready GaN converter is managing the gate drive. Silicon MOSFETs typically feature a comfortable gate threshold of 2 V to 4 V and can tolerate gate voltages up to ±20 V. GaN HEMTs are far less forgiving:

• Low threshold voltage: GaN devices typically turn on at a mere 1.5 V to 2.0 V.
• Fragile gate rating: The absolute maximum gate-to-source voltage (VDS) is often capped at a tight -5 V to +6 V.
• Ultra-low gate charge (QG): GaN switches an order of magnitude faster than silicon. While this minimizes switching losses, it introduces severe dv/dt and di/dt sensitivities.

If the gate drive circuit experiences even minor parasitic inductance, the rapid dv/dt transition can couple back through the device’s Miller capacitance (CGD), generating a transient voltage spike on the gate. If this spike exceeds 1.5 V, it triggers a catastrophic spurious turn-on (shoot-through), potentially destroying the power stage. Conversely, if the gate driver overshoots beyond 6 V due to ringing, the gate permanently degrades.

Interfacing with heritage PWM controllers

Because dedicated rad-hard GaN-integrated drivers are still emerging, power engineers frequently pair discrete rad-hard GaN FETs with established, flight-proven rad-hard analog PWM controllers.

These heritage controllers were designed to drive the heavy, capacitive gates of silicon MOSFETs, delivering output swings from 0 V to 12 V or higher. Interfacing these high-voltage controllers with a delicate 5-V GaN gate requires a meticulously designed intermediate drive stage and layout discipline.

• Voltage clamping: Direct connection is catastrophic. Engineers must employ a high-speed level shifter or a dedicated, rad-hard gate driver buffer (for example, ISL71020M) that accepts standard PWM logic levels and provides a tightly regulated 5-V drive output.
• Asymmetric gate resistance (RG): The gate resistor network must be split into separate turn-on (Rgon) and turn-off (Rgoff) paths via a diode-resistor network. Rgon is optimized to purposefully slow down the turn-on dv/dt to suppress gate ringing. Rgoff is kept near 0 Ω to provide a low-impedance hold-down path, ensuring the gate remains firmly below the threshold voltage during rapid drain voltage transitions.
• Dead time management: GaN HEMTs lack a native body diode; so, they conduct in reverse through the channel when the gate is off. During this dead time, the reverse voltage drop (VSD) can be quite high (2 V to 3 V). If the PWM controller introduces excessive dead time, efficiency penalties from reverse conduction negate the switching advantages of GaN. Therefore, designers must utilize PWM controllers with highly precise programmable dead-time control or implement an external low-forward-drop Schottky diode in parallel.

In my years managing power electronics design, I have watched countless clean schematics fall apart under the oscilloscope simply because an engineer treated a fast wide-bandgap loop layout like a legacy 100-kHz silicon board.

When marrying a heritage 12-V PWM architecture to a 5-V gate, your layout must be an absolute work of art. Parasitic inductance can easily destroy the gate on the very first pulse if the loop area isn’t locked down.

Packaging innovation and real-world use cases

The unique performance GaN metrics are actively reshaping the size, weight, and power (SWaP) equation across various orbital profiles.

In satellite bus power, utilizing isolated GaN-based flyback or forward topologies allows engineers to push switching frequencies past 500 kHz—up from the standard 100 kHz legacy limit—directly translating to a 60% reduction in magnetics volume. In point-of-load (POL) converters, synchronous buck configurations supply core logic rails for spaceborne FPGAs and deep-space processing computers with near-zero reverse recovery losses. Furthermore, in space robotics and motor control, three-phase GaN inverter stages enable compact, motor-integrated electronics housings that bypass heavy shielded cabling.

To support these high-frequency applications, manufacturers have developed innovative, low-inductance packaging structures specifically engineered to eliminate the internal bond wires that cripple traditional high-reliability packages.

Vendor landscape and flight heritage

Navigating the space-qualified GaN marketplace requires examining components that meet the rigorous screening levels required for aerospace reliability. Below are three design case studies.

1. EPC Space

The EPC Space family of devices commands a long track record in commercial-volume rad-hard discrete GaN deployment. Its enhancement-mode (eGaN) discrete FETs (such as 60-V EPC7014) and integrated power modules have accumulated an impressive lineage, with thousands of devices actively operating in orbit since January 2019. These components are heavily utilized in LEO small-sat constellations and GEO communication platforms, powering intermediate bus converters and high-speed pulsed laser drivers for autonomous LiDAR systems.

Figure 1 EPC Space’s hermetic packaging replaces traditional wire bonds with broad, low-profile bottom contact pads to eliminate loop inductance. Source: EPC

2. Infineon Technologies

Infineon’s CoolGaN family represents the entry of traditional military-standard (MIL-PRF-19500) JANS-grade rigor into the wide-bandgap space ecosystem. Leveraging its heritage in spaceborne silicon MOSFETs, Infineon modernized GaN packaging by removing wire bonds entirely. It PowIR-SMD package delivers a 49% footprint reduction compared to legacy housings and reduces internal parasitic package inductance by 97%—dropping to a mere 0.1 nH. This nearly eliminates internal gate ringing, allowing clean interfacing with fast PWM controllers.

Figure 2 The PowIR-SMD technology minimizes internal parasitic inductance down to 0.1 nH via an advanced die-free construction. Source: Infineon

Regarding the validation of these advanced architectures, a high-reliability engineering expert at Infineon stated: “Removing internal wire bonds was the final frontier for GaN in space. By developing a die-free, surface-mount package like PowIR-SMD, we didn’t just solve thermal management—we completely neutralized the parasitic gate inductance that historically caused engineers to shy away from high-speed wide-bandgap switches in critical flight hardware.”

3. Renesas

Renesas entered the space-qualified GaN arena by executing a brilliant ecosystem play: combining its decades-long legacy of rad-hard analog power management with high-reliability GaN FETs like ISL73024SEH. These devices are frequently designed alongside dedicated multi-phase synchronous PWM controllers—such as the ISL73847SEH—to form the fundamental backbone of spaceborne core power bricks.

Figure 3 The Renesas/Intersil radiation-hardened GaN family is engineered in rugged, space-qualified ceramic flatpacks optimized for severe thermal environments. Source: Renesas

Achieving mission success

While designing deep space profiles, we must ruthlessly enforce gate-clamping rules. Designing radiation-hardened GaN converters for space applications is ultimately an exercise in managing extremes. GaN offers game-changing thermal and volumetric efficiencies, but its unforgiving gate drive margins and extreme switching speeds mandate a departure from legacy silicon layout rules.

The accumulated flight data from the GaN industry pioneers has rewritten the rulebook for space power systems, dispelling early engineering anxiety through years of anomaly-free orbital operation. When carefully controlled by a robust, rad-hard PWM controller, these devices provide a mature, predictable, and remarkably rugged path toward achieving unparalleled power density in the cosmos.

Bharrat Mehta, a senior space scientist, is former deputy project director of Indian Space Research Organization (ISRO).

 

 

Related Content

• GaN Transistor for Space Missions
• Infineon unveils rad-hard GaN transistors
• Deep Space Challenges Rad-Hard IC Development
• Test and Measurement Priorities for GaN-Based Power Electronics
• GaN in Space: Unlocking Efficiency and Performance in Satellite Systems

The post Rad-hard GaN converters: Design insights for space hardware appeared first on EDN.

The RTC 27 Click board from Mikroe provides ultra-low-power timekeeping with alarm, watchdog, and timestamp functions. Based on the mikroBUS add-on board socket standard, it integrates the NXP PCF8525 nano-power CMOS real-time clock and calendar chip with an I2C interface. The board is the 2000th member of the Click family, enabling developers to quickly build proof-of-concept designs, prototypes, and embedded applications.

Using the PCF8525’s default temperature compensation engine and integrated temperature sensor, the RTC 27 Click corrects crystal frequency drift, achieving typical ±30-ppm accuracy across temperature and up to 5× better timekeeping than an uncompensated RTC design. It provides time and calendar information, including year, month, day, weekday, hour, minute, second, and 1/100 second.

The RTC 27 Click operates with 3.3-V and 5-V logic voltage levels, while the PCF8525 consumes a typical 64 nA in timekeeping mode with a 3.3-V supply. This makes the board well suited for battery-powered and always-on designs, including portable instruments, wearables, industrial systems, and IoT applications.

The RTC 27 Click is available from Mikroe and its distributors with single-unit pricing of $19.

RTC 27 Click product page 

Mikroe

The post Low-power RTC simplifies embedded timekeeping appeared first on EDN.

Voyager Wingman from Axelera AI is an AI-powered assistant that works with the Voyager Toolkit to accelerate AI application development. It enables developers to interact with the Voyager SDK and Axelera’s documentation using natural language to build, debug, and optimize AI inference pipelines. In internal testing, Wingman achieved 20% to 30% higher accuracy than general-purpose AI coding tools such as Claude Code.

Developing AI applications for dedicated hardware involves tasks such as model export and compilation, pipeline configuration, performance tuning, analytics, and output visualization. To streamline these workflows, Voyager Wingman focuses on four key areas:

• Application development. Natural language generation of computer vision pipelines, including AI models, pre-processing and post-processing steps, and multi-stage pipelines.
• Performance optimization. Recommendations for compiler settings and other optimizations to improve application performance on Axelera hardware.
• Debugging. Assistance with identifying and resolving configuration errors, device detection problems, and model compilation failures.
• Documentation assistance. Natural language access to information on supported operators, APIs, runtime behavior, and configuration syntax.

Voyager Wingman is available through the Axelera Developer Community and Customer Portal. The web-based chat service includes a free credit allowance for developers, while the standalone application is free with the developer’s own LLM API key. For more information, visit the Voyager SDK and Wingman page.

Axelera AI

The post AI assistant optimizes inference pipelines appeared first on EDN.

Rapidus and Cadence are collaborating to advance agentic AI for advanced SoC design and accelerate design turnaround time. The effort integrates the Cadence InnoStack AI Super Agent with the Rapidus AI-Agentic Design Solution (Raads), combining Cadence’s agentic AI orchestration technology with Rapidus’ AI-native design and manufacturing ecosystem for advanced-node semiconductors. According to Rapidus, the approach targets up to a 2× reduction in design turnaround time over conventional design flows.

Rapidus is extending its Raads AI-agentic design environment with the introduction of Raads Navigator and Raads Indicator to enhance quality assurance and help designers resolve design issues. Integrated with the InnoStack AI Super Agent, the new capabilities enable agentic design orchestration across key SoC workflows, automating and coordinating tasks from early architectural exploration through implementation and signoff. The integration allows teams to better manage advanced-node complexity and improve design predictability.

The InnoStack AI Super Agent is available from Cadence. Raads is part of Rapidus’ AI-native foundry ecosystem for customers developing advanced-node semiconductor designs.

Cadence

Rapidus

The post Rapidus, Cadence partner on agentic SoC AI appeared first on EDN.

Melexis has expanded its MLX90412 family of single-coil fan drivers with a device that provides smoother motor control for higher-power fans. Optimized for the cooling requirements of data center infrastructure, AI workstation GPUs, industrial power supplies, and home appliances, the MLX90412-D features code-free configuration via integrated I²C-programmable memory.

With a peak drive current of 2.2 A, the device supports fan designs up to approximately 18 W at 12 V and 35 W at 24 V. Its improved motor-control algorithm enables smooth start/stop operation, reduces acoustic noise, and extends fan lifetime. Revised proportional-integral (PI) regulation ensures stable operation even at very low speeds, while multiple start/stop profiles accommodate different application requirements.

By integrating a Hall sensor, motor controller, and driver in a single IC, the MLX90412-D provides an alternative to MCU-based discrete fan and pump control implementations. Configurable parameters include start-up profiles, speed curves, and FG/RD signal output options, allowing designers to fine-tune fan operation without firmware development.

Samples of the MLX90412-D in a 3.3-mm DFN10 package are available now.

MLX90412 product page

Melexis

The post Fan driver delivers smooth motor control appeared first on EDN.

Version 3.0 of Microchip’s VectorBlox Accelerator SDK simplifies FPGA-based AI implementation by supporting sparse neural networks. Available free of charge, the VectorBlox SDK and associated CoreVectorBlox IP form an integrated toolchain that streamlines the optimization, compilation, and deployment of convolutional neural network (CNN) models on PolarFire FPGA and SoC platforms.

Designed to scale across different model sizes and multiple AI workloads, VectorBlox enables customers to consolidate vision and sensor AI functions on a single low-power FPGA. Sparsity-based model compression reduces compute and memory requirements by skipping zero-valued operations, improving inference performance while lowering power consumption.

VectorBlox SDK 3.0 integrates with Microchip’s Libero SoC Design Suite and provides broad AI model support for TensorFlow, TensorFlow Lite, ONNX, and OpenVINO.

VectorBlox SDK product page 

Microchip Technology 

The post FPGA SDK enables sparse AI models appeared first on EDN.

Convert a 4-20 mA signal to 0-20mA and deliver it to a grounded load with no additional power supply needed.

Recently, EDN kindly published a design of mine for a micropower 4-20 to 0-20mA current loop converter. Shortly thereafter, in the grand tradition of the Design Idea circuit collaboration kitchen, also-frequent contributor Jayapal Ramalingam made a (challenging!) suggestion. He commented that the design might be more useful if, instead of needing an (albeit very small) local power supply, it was revised so as to need no local supply at all.  It was a good point.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The challenging part, of course, was that this meant the converter would have to run solely from power stolen (more or less invisibly, hence “phantom”) from the same 4-20mA signal it was working to convert.  Sneaky.  And tricky. I puzzled over JR’s intriguing suggestion until (eventually) a possible solution emerged from my muddled mental mist.  Figure 1 shows the outcome of my foggy fancy: a “phantom power” converter:

Figure 1 In this circuit, the 4-20mA input current is converted to a 0-20mA output while relying solely and exclusively on the input current for (phantom) power. Power-theft-related error is minimized by recycling the same 100µA that runs the opamps to also bias precision voltage reference Z2.  Asterisk’d resistors are 0.5% or better.

Here’s how it works. Comparisons of Figure 1 to the circuit in the earlier design:

reveal many obvious similarities, but a critical difference (other than no power supply in the “current” case) is how the precision shunt voltage reference is biased.  In the prior circuit, since it runs from a constant local supply voltage, a simple resistor sufficed.  But here, if we assume a 34v range of acceptable loop supply, the 80µA required by the TLV431 at 6v could become 900µA at 40v, creating a cringe-worthy (and likely unacceptable) ~5% conversion error.  Yikes!

Current recycling, however, improves accuracy of the conversion function to Iout = 1.249(Iin – 4mA)  = 0 to 19.9mA as Iin = 7 to 20mA.  The malingering 0.5% of full-scale error is the penalty paid for phantom power.  After all, active devices, by definition, must be fed.  And while 0.5% accuracy isn’t quite phantasmagorical, maybe it’ll do.

Other picky phantom phacts include the IR LED wired in series with Q2’s emitter.  It’s not there to make light, which we couldn’t see anyway, but rather to use its 1v minimum forward voltage to help accommodate A2’s ~200mV minimum output that sits atop Z2’s 1.24v.  Likewise dictated by opamp limitations is the boost of R1 to 249 ohms and its minimum sensed voltage to 1v. This accommodates the 2244’s common mode topping out at 900mv below the positive rail.

In conclusion, thanks JR!

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• 4mA-20mA to 0mA-20mA converter’s current mirror drives grounded load
• Triple-duty current loop calibrator
• Double-duty current loop transmitter
• Full circle current loops: 4mA-20mA to 0mA-20mA

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For the past decade, the artificial intelligence landscape followed a remarkably simple recipe: if you wanted better AI, you built larger models, fed them more data, and added more GPUs. The formula worked, and it worked spectacularly.

Every new generation of hardware enabled larger neural networks, and larger neural networks broadened their reach. What began as image recognition evolved into agents capable of writing essays, generating software code, and creating realistic images and videos. The world grew accustomed to a simple equation: more GPUs meant more intelligence.

However, in the past couple of years, something changed. As we enter the fourth generation of AI—enterprise AI—the industry is discovering that the old recipe is no longer sufficient. The problem is not that GPUs have become obsolete. Far from it: GPUs will remain indispensable for training the giant, diverse models that underpin modern AI.

The problem is that enterprise AI asks these machines to solve a fundamentally different problem, and the assumptions that drove the generative AI revolution are starting to break down.

Enterprise AI operates by a different set of rules

Most people still think of AI as a chatbot: ask a question, receive an answer, end of interaction. That model defined the generative AI era. Enterprise AI, however, plays by different rules.

Imagine an AI assistant embedded inside a company. It starts the day by reading emails, analyzing spreadsheets, interpreting charts, reviewing contracts, listening to conference calls, and consulting internal databases. It collaborates with other AI agents, prepares reports for employees, and continuously updates its understanding as new information arrives. This is no longer a sequence of isolated interactions; it is continuous reasoning.

AI never truly stops working. It shifts constantly between tasks, maintains context over long stretches of time, and makes thousands of small decisions throughout the day. That may sound like a subtle difference.

But from a computing perspective, it changes everything.

Why GPU architectures struggle with enterprise AI inference

For years, AI systems were optimized for one metric: floating-point operational throughput, or FLOPS. The goal was straightforward: maximize the computation performed every second. GPUs excel at this because they were originally designed to process thousands of identical operations simultaneously.

Rendering video game graphics demanded enormous parallelism, and that same parallelism proved extraordinarily effective for training neural networks. Training, after all, is a highly parallel problem: huge volumes of data can be processed at once, and GPUs thrive under these conditions.

Inference is a different story. Inference is the stage where AI produces answers for users in real time. Unlike training, every new token generated by a large language model depends on the token that came before it. There is no shortcut around this sequential dependency. No matter how many GPUs are thrown at the problem, the system still generates one token at a time.

This is where a new bottleneck emerges. For decades, engineers focused on increasing computational performance while memory performance advanced at a far slower pace. Processors became extraordinarily fast; memory did not keep up. This imbalance is known as the memory wall.

Today, the memory wall stands as one of AI’s most stubborn obstacles. Large language models contain hundreds of billions of parameters, and some already contain trillions. Those parameters cannot fit inside a processor. Every time the model generates a response, it must continuously retrieve information from memory. Increasingly, AI systems spend more time moving data than performing calculations. In fact, in many deployments, far more energy is consumed transporting information than computing the answer.

This reality exposes a fundamental weakness of the GPU-centric approach. GPUs were built to maximize parallel computation; they were never designed to minimize data movement. During the generative AI era, the limitation could be partially hidden by batching many user requests together. Large batch sizes kept GPUs busy and delivered impressive throughput numbers.

Enterprise AI changes the economics

An AI assistant participating in a meeting cannot wait for hundreds of requests to accumulate before responding. A medical system helping a physician interpret an image cannot afford noticeable delays. An AI agent coordinating supply chains or financial operations cannot pause while batches form. Enterprise AI demands immediate responses. Latency becomes far more important than throughput.

Here lies the trap for GPU-based inference: to meet the latency constraints of the application, the GPU is forced to operate with small batches, and small batches impact the very utilization that made the GPU economical in the first place. The architecture is not broken; it’s simply being asked to run against its own design assumptions, and its performance degrades significantly as a result.

This shift is forcing the industry to ask a different question. Instead of asking how many operations a processor can execute per second, engineers are increasingly asking how quickly information can move through the system. It may sound like a small distinction. It is, in fact, a critical architectural change.

For years, AI hardware was designed around compute: the processor sat at the center of the system, and memory existed primarily to feed it. That philosophy is beginning to reverse. Fast memory access is becoming the center of architecture.

The goal is no longer to build faster arithmetic units. It is to increase data bandwidth and shrink the distance information must travel. Every millimeter matters because every movement consumes energy, introduces latency, and limits scalability.

The memory-centric revolution: From adding FLOPS to moving bytes faster

This realization is driving a remarkable wave of innovation across the semiconductor industry. Some companies are building processors with enormous amounts of on-chip memory to keep data local. Others are developing specialized inference engines optimized for autoregressive token generation.

New architectures activate only the portions of a model required for a given task, avoiding unnecessary computation altogether. At the same time, researchers are exploring near-memory and in-memory computing, two approaches that bring computation physically closer to where the data resides.

Among the many pioneers proposing new architectures, a few stand out. Cerebras has demonstrated that placing an entire processor on a single silicon wafer can dramatically reduce latency and communication bottlenecks. Groq has focused on highly deterministic, low-latency inference rather than peak throughput.

d-Matrix attacks the memory problem directly by bringing memory and computation closer together. SambaNova is exploring reconfigurable dataflow architectures, while Etched has aggressively specialized its hardware for transformer models.

Beyond GPUs: Rewriting the rules of AI inference

Another example is a next-generation inference architecture. It rests on three interconnected and mutually reinforcing innovations: a memory-centric design philosophy; a high-bandwidth, low-latency, deterministic pipelined data flow; and a hybrid compute fabric that fuses large arrays of tensor cores with on-the-fly reprogrammable DSP cores. Together, they address the fundamental bottlenecks that have long constrained the performance, efficiency, and scalability of AI inference hardware.

The first innovation, the memory-centric approach, marks a fundamental departure from conventional inference architectures. Traditional systems lean heavily on multi-level KV (key-value) caches shuttled through external memory, introducing latency and energy overhead each time the compute engines retrieve or update cached values.

The KV cache is not eliminated. Instead, its economics is transformed. Massive arrays of local registers, positioned in extreme physical proximity to their corresponding compute engines, allow the architecture to hold far larger contexts and model parameter sets close to the compute fabric, making every KV cache access dramatically more efficient.

This reduction in data travel distance cuts memory access latency, relieves pressure on the memory bus, and yields gains in power efficiency. The result is an architecture that sustains higher throughput while consuming less energy, an advantage in large-scale deployments where energy costs and thermal management dominate operational concerns.

The second innovation, the high-bandwidth, low-latency pipelined data flow, addresses the inefficiencies inherent in the single instruction, multiple threads (SIMT) execution model that dominates GPU-based inference today. SIMT architectures impose a heavy memory tax: threads must frequently synchronize and stall while waiting for memory operations to complete, burning both time and power.

By replacing SIMT with a deeply pipelined data flow, the chip ensures that data moves continuously and predictably through the compute stages, eliminating synchronization stalls and sharply reducing the latency and power penalties of traditional GPU memory access patterns. The pipelined approach also delivers deterministic, real-time inference performance, an increasingly important requirement as AI systems move into latency-sensitive applications such as enterprise AI, autonomous driving, robotics, and real-time speech.

The third innovation, the hybrid tensor core and DSP compute fabric, adds a new dimension of computational power and flexibility. Tensor cores are highly optimized for the dense matrix and vector operations that dominate transformer inference, but many workloads also require specialized signal processing, custom activation functions, and non-standard numerical transformations that tensor cores handle poorly.

By augmenting the tensor core arrays with reconfigurable DSP cores, reprogrammable on the fly and driven by a rich instruction set in which every instruction executes in a single clock cycle, the hardware can adapt dynamically to the computational demands of each model and each inference task.

This versatility carries weight for agentic AI. Pre- and post-processing tasks that would normally fall to the host CPU can be executed locally on the accelerator, minimizing CPU-accelerator traffic and freeing host compute capacity for other work. It also future-proofs the architecture against a model landscape that refuses to stand still.

Taken together, these three innovations from VSORA offer a purpose-built solution for modern, scalable AI inference in data centers and at the edge. The result is greater efficiency, lower latency, and broader adaptability than conventional GPU-centric approaches that translates into a lower cost structure and higher ROI for cloud service providers.

On the verge of next architectural transition

Computing history teaches that architectural transitions occur whenever a dominant technology encounters the limits of its original design assumptions. For decades, CPUs were the universal solution until graphics workloads grew so demanding that GPUs emerged as a new specialized architecture. Today, GPUs face a similar moment. They are not being replaced; they are being complemented.

The winners of the next AI race will not necessarily be the companies that build the largest clusters of GPUs. They will be the companies that build systems capable of the smartest data access and management, consuming less energy, responding faster, and reasoning more efficiently.

Lauro Rizzatti is a business development executive with VSORA, a technology company offering silicon semiconductor solutions that aim to redefine silicon performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

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Reach into your pocket and find your keys without looking. You just did something no robot can reliably do. You couldn’t see into your pocket, yet your fingers sorted keys from coins and lint, registered the weight and the cut edges, and closed around the right object. That was touch, quietly doing the kind of work that sight simply cannot.

Artificial intelligence (AI) has learned to see. It has learned to listen. Increasingly, it can reason, plan, converse, and generate sophisticated solutions to complex problems. Yet despite astonishing advances in foundational models and robotic computer vision, the next generation of intelligent machines remains constrained by a surprisingly simple limitation: ask a robot to pick up a paper cup, a grape, or a crumpled receipt, and the illusion breaks. It hesitates. It crushes the cup or drops the grape. The brain got smart far faster than the hands did.

This limitation isn’t because robots lack intelligence. It’s because they lack touch. For decades, AI has largely been about perception—understanding the world through images, language, and sound. Physical AI systems—that must operate and interact directly in the real world—reshape the challenge entirely. Instead of simply interpreting the world, intelligent machines must interact with it. They must grasp, manipulate, assemble, lift, carry, and collaborate efficiently and safely alongside people.

The gating modality for physical AI, therefore, is no longer being able to see. It’s being able to feel. Vision gave robots a view of the world. Touch, or multimodal sensing, is what will finally let them reach into it.

Figure 1 Physical AI doesn’t stop at perception. Multimodal sensing integrates vision, touch, and edge AI to enable robots to understand, adapt to, and safely interact with the physical world in real time. Source: Synaptics

The shift from perception to interaction

The last decade has been dominated by extraordinary progress in perception technologies. Computer vision systems now recognize objects with remarkable accuracy. Large language models (LLMs) can break down complicated tasks into logical sequences of actions. Robots increasingly understand what they are looking at.

Seeing and understanding, however, is not the same as taking action. A warehouse robot may correctly identify hundreds of products on a shelf yet struggle to remove a flexible package without crushing it. A humanoid robot may recognize a wine glass instantly but fail to grasp it securely and with the carefulness required of a fragile object.

To understand the shift from perception to interaction, it helps to contrast two flavors of autonomy by comparing autonomous vehicles with robotic manipulation. A self-driving car spends nearly all its effort avoiding contact. For an autonomous vehicle, touching something usually represents failure.

A robotic hand exists for precisely the opposite purpose. Its job is to make contact deliberately, continuously, and intelligently. Every successful grasp depends not simply on locating an object, but on understanding how that object responds when the instant contact is made. That information cannot be seen. It must be felt.

Vision plans, touch executes

Researchers increasingly describe robotic manipulation with a simple phrase: vision is for planning, and touch is for execution. Vision excels at global understanding. Cameras determine where objects are located, estimate pose, classify materials, and plan trajectories. They provide the strategic overview necessary for intelligent action.

But the moment robotic digits close around an object, vision begins to fail. The contact point disappears behind the hand itself. Cameras cannot observe friction. They cannot determine whether a paper cup is slightly damp, whether a cardboard box is heavier than expected, or whether a glass has begun slipping between two fingertips.

These are not visual problems. They are tactile problems. Humans solve them effortlessly. We tighten our grip on a slippery glass before it falls. We pick up an egg and instinctively apply exactly enough force—not too little, not too much. We rarely think about these abilities because our nervous system performs them automatically. For robots, they remain among the hardest problems in engineering.

Figure 2 Touch happens fast and intelligence happens faster. In just 70 milliseconds, multimodal touch sensing and edge AI transform raw tactile signals into intelligent grip control for safer, more dexterous robots. Source: Synaptics

The next robotics frontier: The science of the “slip”

Picture a condensation-slicked glass of water in your hand, eyes closed. As it begins to slide, you don’t need to see it to react. Your fingertips pick up a faint change in vibration and pressure, and your brain issues a “smart squeeze”—just enough extra force to arrest the slide without shattering the glass. The whole loop, from sensation to correction, runs below the level of conscious thought.

That loop is one of the hardest things to reproduce in a robot. Machines can compute trajectories, yet they remain clumsy about the feel of friction. The traditional answer was pre-programmed rigidity: apply a fixed grip force and hope the object—steel or sponge—cooperates.

Today’s physical AI system developers, however, look for something more subtle: the moment, invisible to the eye, when a stable hold begins to come apart. Contrary to intuition, objects rarely transition instantly from being secure to being dropped. Slip begins gradually.

At microscopic scales, every surface consists of tiny peaks and valleys. As force builds across a contact patch, the outer regions begin slipping while the center continues gripping. Engineers call this incipient slip, and detecting it early transforms robotic control. Instead of reacting after failure, robots can intervene before failure occurs.

This failure intervention requires two complementary sensing systems that mirror the layered design of human skin. A slower channel continuously measures pressure, shear forces, and load distribution across the fingertip. A much faster channel listens to high-frequency vibrations that signal the earliest stages of slipping. Together they create something remarkably similar to the layered sensing architecture found in human skin. One channel feels pressure, the other hears friction.

Only by combining both can a robot understand what’s actually happening at the point of contact.

Figure 3 Physical AI is a continuous feedback loop, not a one-time decision. True physical AI is possible when vision, touch, and edge intelligence work together in a continuous cycle of sensing, thinking, acting, and adapting. Source: Synaptics

Why touch changes everything

A useful multimodal sensing system must answer four fundamental questions.

First, has contact actually occurred? Millimeter-scale positioning errors matter. A robot must know the precise instant it touches an object rather than empty space.

Second, how much force is being applied? Picking up a steel bracket requires entirely different forces than handling fruit, laboratory samples, or medical devices.

Third, is the object beginning to slip? Perhaps the most important capability of all is detecting incipient slip—the microscopic changes that occur before an object falls.

Fourth, how does it feel? While the internet contains unlimited visual data, it contains almost no tactile experience data. No image can tell an AI application what wet glass feels like, how fabric stretches, or how friction changes as an object rotates within a grasp. The only way to learn these interactions is through physical contact. Touch provides ground truth: rich, labeled physical data about what real contact feels like, which is precisely what physical AI systems require.

Intelligence belongs at the edge

Touch also changes where intelligence must live. Unlike language models, tactile decisions cannot wait hundreds of milliseconds for cloud processing or centralized computation. If a glass begins slipping, every millisecond matters. Human grip corrections occur in roughly 70 milliseconds. A robot that must transmit raw sensor data to a central processor before deciding how to respond has already lost valuable time.

Instead, tactile intelligence must move to the edge. Each fingertip becomes an intelligent sensing node, interpreting pressure, force, and vibration locally before sending only meaningful events to higher-level control systems. This architecture mirrors biology: individual nerve endings process local information before communicating with the brain. The brain receives distilled information about events that matter rather than monitoring every sensory receptor continuously.

Physical AI increasingly requires the same distributed architecture. Vision determines the objective. Local intelligence manages contact. Higher-level AI coordinates the task. Touch increases the likelihood that each task is executed successfully.

Physical AI architecture: Reliability is more important than resolution

Much of today’s discussion around robotic touch as the path to dexterous machines focuses on sensor resolution. Resolution matters, but reliability matters more. Building an impressive laboratory demonstration that executes large numbers of touch events is relatively straightforward. Building a tactile sensor that performs accurately after millions of grasps in factories, warehouses, and hospitals is vastly more difficult.

Every tactile technology has weaknesses. Soft materials wear. Temperature changes electrical characteristics. Motor noise contaminates tiny signals. Elastomers gradually develop hysteresis, remembering previous deformations instead of returning instantly to baseline.

Optical sensors produce exceptionally rich data but require bulky camera systems. Magnetic sensing performs beautifully until exposed to external magnetic fields. Piezoelectric materials detect vibration extraordinarily well but cannot measure static force.

The challenge is not finding a perfect sensing modality. The challenge is engineering reliable systems that compensate for imperfections while surviving years of real-world use. Success requires expertise that extends well beyond robotics to materials science, signal processing, embedded intelligence, silicon design and manufacturing, firmware, and systems engineering, all working together as a single discipline. Ultimately, reliability—not raw sensitivity—is what determines whether physical AI scales beyond research laboratories.

Why this moment matters

The urgency surrounding physical AI development is driven by timing. In industrial applications, for example, humanoid robots are moving from prototypes toward mass commercial deployment according to industry research analysts. Conservative estimates from Goldman Sachs Research predict 1.4 million active humanoids will be working in global manufacturing, warehouses, and logistics by 2035. Morgan Stanley projects an even higher trajectory, citing massive production scale and adoption of 13 million service robots working along humans in the same timeframe.

The opportunity extends even further. Prosthetic limbs require tactile feedback to restore natural function. Data collection systems need tactile sensing to train future manipulation models.

Large-area robotic skin improves safe collaboration between humans and machines. Every application depends upon extracting trustworthy physical information from an inherently noisy world, and regardless of form factor, every Physical AI system eventually encounters the same bottleneck: hands or more precisely, contact.

Whether a machine uses five-fingered humanoid hands, industrial grippers, or specialized end effectors, it must regulate force, detect slip, and manipulate objects safely. Touch, therefore, becomes a foundational capability rather than an optional enhancement.

From digital to physical intelligence: Relying on touch for physical AI

History suggests that every major computing revolution has been enabled by a new interface. The graphical user interface transformed personal computing. The touchscreen transformed mobile computing. Touch now appears poised to transform robotics.

Just as computer vision unlocked autonomous perception, tactile intelligence will unlock autonomous manipulation. The companies that succeed in this technology space will not simply build better sensors. They will build complete sensing systems that combine advanced materials, embedded intelligence, signal processing, edge AI, robust manufacturing, and decades of experience extracting reliable information from imperfect physical environments. That combination—not any single breakthrough—will define the next generation of physical AI.

Physical AI is often described as giving machines a brain. In reality, we have spent the past decade building remarkably capable brains. What robots still lack is a nervous system: the ability to feel force, sense friction, recognize instability before failure, and transform contact into understanding.

The future of intelligent machines will not be determined solely by larger models or more powerful processors. It will be determined by whether those machines can interact with the physical world with the same confidence that humans have.

Vision gave AI the ability to understand the world. Touch will give it the ability to change it.

Satish Ganesan joined Synaptics in November 2019 and serves as senior VP and GM of Edge Interface & Sensing Division and Chief Strategy Officer. Prior to Synaptics, Satish served as chief product officer of Keyssa, a wireless startup focused on short-range connectivity. He also held several executive positions at Broadcom and Xilinx.

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This easy-to-build PWM source is a handy testing tool for hobbyists, technicians, engineers and other RC-based device developers.

I work at a university where I’m charged with designing and developing all manner of circuits and systems for students, faculty, researchers, and the like. These circuits include a diversity of projects relying on the standard remote control (RC) pulse-width modulation (PWM) signal for their operation.

Wow the engineering world with your unique design: Design Ideas Submission Guide

This signal is generally defined as a TTL pulse train having a frequency of 50Hz and a width ranging from 1ms to 2ms. While these parameters can be programmed into most waveform generators, alternatively having a small, dedicated-function gizmo at the ready can prove to be really convenient! Figure 1 shows what I came up with.

Figure 1 The standard RC PWM signal used to control a myriad of devices is usually obtained using transmitters and receivers. This alternative RC servo operator circuit implements a convenient alternative jig that simplifies attaining various testing objectives.

Components C1, U1, and C2 comprise a low dropout 5V regulator. More generally, any 5V regulator IC can be employed, so long as the dropout is under a volt. Typically, RC servos run on 6V, though some will run on as many as 8V. The nominal input, indicated as 6V here, is forwarded to the servo output for convenient experimentation as shown.

The PWM source is based on Analog Devices’ nice-and-simple LTC6992-1. The trick is selecting the right resistor values, which are shown in Figure 1. Rather than generate a PCB, I soldered up the circuit using proto-board, through-hole components, and adapter boards for both ICs. If done on a PCB using surface-mount components, the entire circuit will take up only about 1 in2.

I don’t personally keep an RC transmitter and receiver combo in my lab. Even if I did, I’d need someone to manipulate the controls while I measured the values of interest on the system I’m developing. With this handy alternative circuit, I can run all my tests without human assistance, not to mention without the RC hardware. It has proven useful on numerous occasions.

Mike Potash is the electronics technician for the College of Engineering at Embry-Riddle University in Daytona Beach, Florida.

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Siemens EDA has snapped up a San Diego startup to complement its digital design and implementation capabilities with AI-powered exploration for advanced system-on-a-chip (SoC) architectures. Precision Innovations, a privately held EDA company, helps semiconductor engineering teams evaluate architectural and design trade-offs early in the SoC design cycle for faster time to silicon.

At a time when chip designers face rapidly increasing SoC complexity and the need to explore new architectures faster and more efficiently, Precision Innovations’ AI-powered early design exploration technology is expected to enhance Siemens’ EDA portfolio by accelerating time to silicon and improving power, performance and area (PPA).

The acquisition aims to bring AI-driven chip planning to a much broader set of semiconductor teams. Source: Siemens EDA

Precision Innovations, founded in San Diego, California, in 2019, develops EDA software built on the open-source OpenROAD framework to help engineers evaluate design feasibility, reduce design iterations, and accelerate time to market. “Together, we can help designers leverage AI to evaluate thousands of design options earlier in the process and focus on innovation where it matters most,” said Tom Spyrou, CEO of Precision Innovations.

Precision Innovations will become part of Siemens EDA’s Digital Design Creation software team to complement the company’s end-to-end digital flow that spans architecture, implementation, and the full silicon lifecycle management of SoCs. “With Precision Innovations joining Siemens, we will expand our ability to support customers as they face rapidly increasing SoC complexity and the need to explore new architectures faster and more efficiently,” said Ankur Gupta, executive VP of IC portfolio at Siemens EDA.

The acquisition, subject to customary conditions, is expected to complete in the third quarter of 2026.

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Linear variable differential transformers (LVDTs) stand out as one of the most reliable displacement sensors in modern engineering. By converting linear movement into proportional electrical signals, they deliver unmatched accuracy and repeatability across demanding environments—from aerospace control systems to industrial automation lines. Their rugged, non-contact design ensures long service life, while their ability to resist electrical noise makes them indispensable wherever precision and stability are paramount.

This article highlights how LVDTs operate, why they define precision sensing, and what are their key applications.

At the heart of an LVDT is a movable ferromagnetic core that shifts within a coil assembly, inducing voltage changes that correspond directly to displacement. This elegant mechanism defines LVDT’s reputation for precision sensing, enabling engineers to capture minute movements with exceptional accuracy and repeatability.

That reliability translates into critical applications: stabilizing aircraft control systems, guiding industrial automation processes, and supporting delicate medical instrumentation. By combining robust design with noise-resistant performance, LVDTs continue to set the benchmark for displacement measurement across diverse fields.

The electromagnetic elegance of LVDTs

Well, let’s dig deeper into the rabbit hole of LVDT design. Beyond the straightforward coil-and-core mechanism lies a finely tuned balance of electromagnetic principles that ensures linearity and stability across a wide measurement range.

Its differential signal output scales cleanly with displacement, canceling common-mode noise and making LVDTs remarkably resilient in harsh environments. This blend of simplicity and sophistication explains why they remain the sensor of choice when precision, durability, and repeatability are non-negotiable.

In practice, an LVDT is a widely used electromechanical transducer that converts the rectilinear motion of a mechanically coupled object into a proportional electrical signal. Its structure features a primary winding centered between two symmetrically spaced, identically wound secondary windings, forming the stationary coil assembly of the sensor.

The moving element is a separate tubular armature—called the core—made of magnetically permeable material. Free to slide axially within the hollow bore of the coil, the core is mechanically linked to the object under measurement. The bore provides ample radial clearance, ensuring no physical contact between the core and coil.

As the core shifts position, the magnetic coupling between the primary and each secondary winding changes, producing displacement-dependent voltage signals that deliver a precise electrical representation of the object’s position.

Figure 1 Pencil drawing illustrates the cutaway view of a basic LVDT. Source: Author

The primary winding is shown at the center of the LVDT. Two secondary coils are wound symmetrically on either side of the primary coil for short-stroke LVDTs, or concentrically over the primary coil for long-stroke versions. The two secondary windings are typically connected in a series-opposed (differential) configuration, ensuring that the output signal accurately reflects the core’s displacement.

In operation, the LVDT’s primary winding is energized by an alternating current of suitable amplitude and frequency, referred to as the primary excitation. The resulting electrical output is a differential AC voltage between the two secondary windings, which varies with the axial position of the core inside the coil. To make this signal more practical, it’s typically converted by electronic circuitry into a higher-level DC voltage or current.

Note that the two secondary windings are connected in series but wound in opposite directions—a series-opposed configuration that ensures the differential output accurately reflects the core’s displacement. For most industrial LVDTs, datasheets assume this series-opposed arrangement. In high-reliability sectors, however, the windings are often kept separate to enable more advanced error-correction techniques.

Figure 2 Schematic illustrates the circuit model of a basic LVDT. Source: Author

How an LVDT works: The silent precision of linear sensing

An LVDT operates as a specialized transformer with a single primary winding, two identical secondary windings, and a movable ferromagnetic core. The core slides axially within the assembly, linked to the monitored component by a push rod. When the primary winding is energized, its magnetic field induces voltages in the secondary coils.

Because these coils are connected in series-opposition, the output is zero when the core is centered at the null position. As the core shifts, magnetic coupling increases in one secondary and decreases in the other, producing a differential output voltage proportional to displacement. The direction of movement is indicated by the phase of the output signal relative to the primary excitation.

To summarize, an AC LVDT is a variable-reluctance transducer that operates by energizing a primary coil with a constant AC supply to induce a magnetic field. This flux is coupled through a moving armature to two secondary coils which are wired in series opposition.

When the armature is at the null position (dead center), the magnetic flux is distributed equally between both secondaries, causing their output to cancel out perfectly. However, as the shaft shifts closer to one coil, the energy in that coil increases relative to the other; by measuring this differential output, the sensor precisely determines the shaft’s position and direction within the tube at all times.

Figure 3 LVDT AC miniature free core position sensors monitor and track the linear motion or position of a target. Source: HGSI

LVDT mechanical configurations: The art of precision displacement

Modern LVDTs are available in three primary mechanical configurations to suit different integration needs. Free (unguided) armature LVDTs utilize a core that moves freely within the bore; because the core is not physically restrained by the sensor, it’s ideal for high-speed dynamic applications where near-zero friction is required.

Captive (guided) armature LVDTs feature internal bearings to maintain core alignment, preventing lateral wear and simplifying installation in industrial automation. Finally, spring-loaded (forced) LVDTs employ an internal spring to maintain contact with the specimen, making them the go-to choice for gauging and QC applications where a permanent mechanical link to the test object is not possible.

Each variety offers a unique trade-off between mechanical simplicity and operational precision.

LVDTs: Key features and operational benefits

LVDT stands as a premier electromechanical transducer, primarily distinguished by its friction-free operation; since the movable core does not touch the coil assembly, there is zero mechanical wear, ensuring an exceptionally long lifetime and high reliability. This physical decoupling allows for infinite resolution, enabling the detection of sub-micron displacements limited only by the signal-conditioning electronics, while its single axis sensitivity ensures that cross-axial movements do not interfere with measurement accuracy.

The design’s separable coil and core mechanism simplifies integration into complex machinery, and its environmentally robust construction allows it to thrive in extreme temperatures or high-vibration settings. Furthermore, LVDT provides remarkable null point stability for consistent zero-referencing, a fast dynamic response capable of tracking rapid changes in position. And, most importantly, an absolute output that retains the correct position data immediately upon power-up, even if the core moved while the system was inactive.

Support electronics: From AC physics to DC simplicity

Although an LVDT is technically a transformer, it requires specialized AC excitation—typically a few volts RMS at several kilohertz—rather than standard line power. Supplying this excitation is a key role of LVDT signal-conditioning electronics, which also convert low-level AC outputs into high-level DC signals, decode directional information from the 180° phase shift at the null point, and provide precise electrical zero adjustments.

These electronics are available in multiple forms, from chip-level components for OEM integration to modular boards and full laboratory instruments. Some LVDTs incorporate integral electronics for simplified “DC-in, DC-out” operation, but such self-contained units may be unsuitable for extreme environments where heat, vibration, or space constraints can compromise internal circuitry.

Figure 4 Datasheet excerpt shows an in-line amplifier transforming LVDT displacement into a directly proportional DC signal. Source: MTS

As a quick side note, LVDT is the technical acronym for the component itself—linear variable differential transformer—while LVDT displacement sensor is often used in industrial catalogs to distinguish it from other measurement technologies, such as capacitive or eddy-current sensors. This descriptive naming helps engineers quickly identify the device’s primary function as a tool for tracking linear position, even though both terms refer to the same electromagnetic hardware.

LVDT signal conditioning: Differential vs. ratiometric

Back to the signals, when choosing how to process an LVDT signal, the main difference lies in how the system handles fluctuations in power. Differential input AC signal conditioning is the more straightforward approach, where the sensor simply measures the difference in voltage between its two secondary coils to determine position. While effective, it has a notable weakness: if the input power (excitation voltage) fluctuates even slightly, the output reading will change as well, potentially leading to errors.

Ratiometric signal conditioning is a more sophisticated method designed to eliminate those errors. Instead of just looking at the difference between the coils, it compares that difference to the total sum of the voltage from both coils. By calculating this ratio, the system automatically cancels out any inconsistencies in the power supply. This makes ratiometric conditioning much more stable and reliable for high-precision tasks, as the measurement stays accurate even if the environment gets hot or the input voltage drifts.

Figure 5 This standalone universal LVDT signal conditioner supports any LVDT sensor with 4, 5, or 6 wires, as well as RVDT or 3-wire half-bridge sensors. Source: Lab Systems

It’s worth noting that an LVDT measures straight-line (linear) displacement, whereas a rotary variable differential transformer (RVDT) measures angular (rotary) displacement.

Precision in motion—From floor to space

From machine tools and robotics to aerospace and space-borne instrumentation, LVDTs remain the gold standard for precise, contactless position measurement. Their rugged construction, infinite resolution, and immunity to wear make them indispensable wherever accuracy must endure vibration, temperature extremes, or time itself.

For today’s makers and engineers, the story doesn’t end at the sensor—modern signal-conditioning ICs such as Analog Devices’ AD598 and Texas Instruments’ PGA970 bring excitation, demodulation, and calibration into compact solutions, while discrete signal-handling circuits continue to offer flexibility for custom designs and extreme environments.

And for those who venture into DIY territory, crafting the coil-core assembly demands patience, precision winding, and careful alignment—skills that embody the very discipline of engineering. Whether you’re building a robotic actuator, a precision test rig, or a satellite mechanism, LVDT proves that elegant physics and smart electronics can turn motion into measurable insight.

I’m ready for a larger displacement of detail in future posts, but at this time, that’s all. Take this knowledge forward—experiment, prototype, and innovate with LVDTs, integrated ICs, discrete signal handlers, and even your own hand-built coil assemblies. Push your designs from the lab bench to the factory floor, and even to orbit. The next breakthrough in precision engineering could start with your hands.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Precision in motion: The engineering value of LVDTs appeared first on EDN.

Bluetooth and Wi-Fi combine to untether smartphone-to-car connections…at least until the former’s battery drains, that is.

At this year’s beginning, EDN published my overview and hands-on impressions of Apple’s CarPlay and Google’s Android Auto standards, which enable a vehicle radio or automotive head unit to be a display and controller for an iOS or Android device, respectively. Historically, both protocols leveraged a wired USB-based interface between mobile device and vehicle to accomplish the integration objective, for latency, bandwidth and interference-prevention reasons. Newer vehicle models switch to Bluetooth (for initial discovery and connection) and Wi-Fi (for ongoing transmission) communication, enhancing convenience. And bridging these two approaches are wireless adapters that mate an untethered phone to the tethered vehicle.

At the end of that prior coverage, I wrote, “FYI, I’ve also got two single-protocol wireless adapter candidates sitting in my teardown pile awaiting attention.”

Today I’ll analyze the insides of a CarPlay wireless adapter, albeit not the “unit from the Luckymore Store” that I initially planned on disassembling. Next month, I plan to take apart a wireless adapter that implements the Android Auto protocol. And I’ll subsequently wrap up my dissections with a dual-protocol wireless adapter functionally akin to the one still in use in my wife’s Land Rover.

Supplier disappearance and switcheroo

Here again is the wireless CarPlay adapter I’d originally intended as today’s patient.

Right now, as I write these words, it lists for $44.17 on Amazon’s website. But when I bought it in mid-December, it was on sale for $2.99 plus tax, with free shipping. Although the merchant subsequently reported to both Amazon and me that it had shipped, it never actually arrived. And I wasn’t the only one that had this same underwhelming seller experience. Yes, I got my $3.12 back eventually.

I subsequently picked up this WOLIOS adapter (which apparently also came in white), well-reviewed but seemingly no longer available for sale as I write this, from Amazon’s Warehouse-now-Resale section for $11.85 in late February.

Gotta love these conceptual teardown images. And no, I don’t definitively know what “5G” means, either, although I suspect they’re referencing “5 GHz” Wi-Fi.

And, wrapping up the “stock content” suite, a promo video (which, alas, I can’t figure out how to embed) can be found here.

Overview introductions

Now for some real-life photos, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes, and of the product packaging first:

Next, what’s inside:

The red disc is an optional sticker for adhering the wireless adapter to the vehicle interior. The included USB-A (female) to USB-C (male) adapter for newer-vehicle use is a nice touch:

And now for our patient:

The hole in the center allows the status LED inside to shine through, as conceptually shown in the prior “stock” images. And the seam around the rim? I’m betting that’s our path inside.

Stubborn adhesive

Speaking of paths to the insides, let’s dive in.

Abundant exposure to my wife’s hair dryer on “high” (both temperature and fan speed) helped, but only a little. I resisted using my heat gun as it might have been melt-inducing overkill.

The last bit of the panel stubbornly refused to dismantle, so I eventually turned to a cutter tool.

Finally free, courtesy of a needle-nose pliers, albeit resulting in PCB mars.

This side’s much more interesting:

The embedded antenna at upper right is curious. As previously noted, two wireless broadcast links are necessary: 2.4 GHz Bluetooth for initial setup, and Wi-Fi for ongoing streaming. The latter is usually based on the 5 GHz band for higher transfer bandwidth, since range isn’t a concern in a diminutive vehicle interior. But I only see one antenna here.

Did the manufacturer figure out some way to passably enable it to support both bands? Or is there another one somewhere that I’m overlooking? Or does this particular design, in contrast to “Wireless Compability [sic]: 5.8 GHz Radio Frequency” spec claims to the contrary, leverage 2.4 GHz Wi-Fi instead? Or…???

Equally baffling is the user-inaccessible switch in the lower left corner (with the status LED to its right, in the middle of the lower edge). What’s the switch for? And then there’s the unmarked square IC enigma above and to the switch’s right (and LED’s left). I assume it’s the application processor, and that it runs at 24 MHz (courtesy of the marked oscillator to its left).

But who makes it, and what’s its specific product code? Another mystery. These are commonly Arm-based, with Chinese fabless suppliers Allwinner and Rockchip common sources (so says Google AI Overviews, at least), although this reverse-engineered unit from early and ongoing-leading adapter supplier Carlinkit reportedly leverages a Freescale (now NXP Semiconductors) SoC, the i.MX6 UltraLite.

To its right, and to the left of (and slightly below) the aforementioned antenna(e) assembly, is a Winbond W25Q128 128 Mbit serial flash memory, presumably housing the user-upgradeable system firmware image. And then there’s the even larger shiny-shield covered square IC below the antenna(e). This one’s easier to figure out, thanks to the careful application of a flat-head screwdriver acting as a lever.

It’s Realtek’s RTL8733, supporting the device’s wireless subsystem. The RTL8733 comprehends both Bluetooth and dual-band Wi-Fi transceiver functionality and presumably operates in conjunction with the mystery application processor to implement the adapter’s wireless-to-USB wired bridge functionality.

That’s all I’ve got for you today, folks. As always, let loose with your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Adapter makes CarPlay connectivity wireless appeared first on EDN.

It took 100 years to come to fruition, but this recently created fluid enables non-magnetic electrostatic-based motors.

Say the word “motor” to most engineers and they almost always associate it with magnetics of some type, whether the term is explicitly stated or not. Of course, not all electrically powered motors use magnetism: piezoelectric motors use that well-known principle and the voltage-driven elongation of a crystal, and there are also tiny MEMS-based motors.

Still, magnetics is front of mind for most cases, with motors that take electric current and power and transform it into a magnetic force that drives the rotor. (Come to think of it, there are also pneumatic and hydraulic motors often used by mechanical engineers, often with some electronic control – but that’s another story for another day.)

That’s why a recent development led by a team at the Institute of Science Tokyo may change our thinking about non-magnetic motors. They have developed a rotary motor based on electrostatic forces rather than the usual electromagnetic ones. Using a ferroelectric fluid, motors that previously required fairly high voltages on the order of 1000 V can operate at much lower voltages. (Not familiar with ferroelectric fluids, or have them confused with ferrofluids? See the sidebar at the end.)

A critical factor in their approach is that the force generated by electricity is not limited to attraction along the direction of the applied voltage. Instead, there is also a force that acts perpendicular to that direction, creating a sideways-pushing force. In conventional materials, this sideways force is extremely weak and has long been considered too small to utilize and, as a result, has attracted little attention.

However, the team demonstrated that the sideways electrostatic force can, under the right conditions, become surprisingly strong. They placed the fluid between two electrodes separated by only a few millimeters and applied a voltage. The result was striking: the liquid was pushed sideways and moved nearly 10 centimeters even against gravity. When the same experiment was performed with conventional liquids, this motion did not occur; the effect appeared only with the ferroelectric fluid.

Another interesting finding was how the force increased. In ordinary materials, increasing the voltage does not easily lead to a large increase in force. In contrast, with the ferroelectric fluid, even a small increase in voltage led to a proportional increase in force. Through detailed deep-physics analysis, the team found that the electric field causes the molecules in the liquid to align in an ordered way, generating the sideways-pushing force.

Using ferroelectric nematic liquid crystals, they were able to show that transverse electrostatic force (TEF) can elevate the fluid between electrodes with a gap of 2.5 millimeters (mm) up to more than 80 mm at only 28 V/mm, corresponding to a stress greater than 1000 newtons/m2 (Figure 1).

Figure 1 Direct observation of the TEF produced interesting results. (a) Experimental setup where TEF is balanced with the gravitational force. Voltage-dependent fluid heights at a 10mm gap under applied voltages of 0 V (b), 50 V (c), 100 V (d), and 150 V (e). Note that the zero-point height is 1 cm on the ruler. (f) Case of a 2.5mm gap at DC 80 V. (g) Height of fluid, H, plotted as a function of the applied voltage V for 1.0 (green), 2.5 (pink), 5.0 (yellow), and 10mm (purple). The data for silicone oil and nematic liquid crystal 4-cyano-4′-pentylbiphenyl (5CB) at 80 V at a 2.5mm gap are shown as a gray bullet. (h) Generated stress, σ⊥, plotted as a function of the applied electric field E. (The inset is a magnification at a 1.0mm gap.) (Image source: Springer Nature)

This discovery led to a next logical next step: if this force can push, could it also be used to create rotation? The answer is yes, and they developed a prototype motor that does not use magnets, a metal rotor, or rare-earth metals (Figure 2).

Figure 2 A prototype plastic ferroelectric motor successfully implemented rotation (Left: angled view; Right: bottom view with the lower electrode removed to reveal the resin rotor) (Image source: Institute of Science Tokyo)

The structure can also be simpler and lighter. Because the rotating part can be made of resin rather than metal, devices can be made lighter and respond more quickly. The absence of magnetic materials also means it can be used where having these materials in proximity to other system parts can induce magnetic noise or distortions.

Additional tests were done to assess both stability and scalability for the TEF-based approach (Figure 3).

Figure 3 Testing of TEF scalability and stability further confirmed concept viability. (a) Lifting a resin weight (circled in white) by TEF generated in a ferroelectric fluid, before a DC voltage was applied (upper) and after lifting for 22mm upon application of DC 20 V (lower). The mass was 5 mg, constrained between the electrodes. The interelectrode  distance was fixed at 1.0mm. (b) Experimental setup for testing TEF scalability and stability. A tensile-testing machine holds a 3D-printed resin piece whose base area is 100mm2. The resin piece is immersed in the ferroelectric fluid reservoir to a depth of 1 mm; the aluminum parallel-plate electrodes of 56 mm length were fixed at a distance of 2.5 mm. The temperature was controlled by heaters with thermocouples inserted into the reservoir. The temperature of the ferroelectric fluid was directly measured by a thermocouple immersed in the fluid. (c) Time-course measurement of TEF under 60 V DC using the tensile-testing machine experiment setup shown in (b). Generated TEF, F⊥, was plotted as a function of time t. The force represented by the red line is the five-point moving average before and after the raw data shown in gray. (Image source: Springer Nature)

Of course, the true endpoint of this project was not just to explore these fluids but make something that at least initially appears potentially useful, such as an electric motor. To do this, they built a motor roughly analogous to a DC stepper motor by following three basic design rules (Figure 4):

1. The fundamental components should consist of three pairs of stators and two rotors.
2. The width of the rotor should be longer than that of the stator but shorter than the sum of the width of the stator and the space between stators.
3. The relationship between the total number of stators and rotors should be an integer multiple of 3:2.

Figure 4 The ferroelectric motor’s novel design followed three basic rules. (a) (Upper) Case of the width of a mover being shorter than that of the electrodes. (Lower) The case of the width of a mover being longer. (b) A fundamental configuration of electrodes for continuous movement. The number in the upper-left corner of each panel corresponds to the phases of the pulse shown at the bottom. (c) CAD designs and photographs of the rotor (bottom inset) and the stator (top inset). The position of the upper stator in the CAD designs is not the actual position for clarity. The outer diameter, each pole’s length, and thickness of the rotor are 18 mm, 4 mm, and 1 mm, respectively. The stator consists of three-layered electrodes (U, V, and W poles) with two insulating layers. The outer diameter, each pole’s length, and total thickness of the rotor are 28 mm, 4 mm, and 2.1 mm, respectively. The length of the overlapping part of the poles of the rotor and the stator is about 3.5 mm. The gap between the upper and lower stators is 2 mm. (d) External view of the assembled motor. (Image source: Springer Nature)

Their prototype ferroelectric motor consists of a 3-phase 24-pole stator with an 11.25° electrode angle and a 3.75° space angle between stators and a single-phase 16-pole rotor with a 12.5° electrode angle and a 10° space angle. It was driven with a 3-phase, 60-V square wave with a duty ratio of 33%.

Most electrostatic motors studied thus far required a high applied electric field of several 10–100 MV/m; in contrast, the ferroelectric motor rotated with an electric field as weak as 0.03 MV/m (here, 60 V/2 mm), which means that a driving voltage as low as one-thousandth of that figure could be used.

The most important advantage of this ferroelectric motor over ordinary electromagnetic motors is that it does not require a voltage to be applied to the rotor, which means that the rotor can be made of resin instead of metal, making it lightweight and reducing inertia. In addition, because the rotor does not need to be energized, mechanisms such as carbon brushes and slip rings are unnecessary.

The work is fully detailed in their paper “Huge transverse Maxwell stress in ferroelectric fluids and prototyping of new ferroelectric motors” published in Nature’s Communication Engineering (why there – I can’t say). It includes the associated deep-physics analysis as well as links to some “action” videos.

Do you think there’s a future for these electrostatic motors, or will real-world considerations hinder their advance? Or will they be like ferrofluids, and find uses far removed from their design objectives?

Sidebar: Ferroelectric fluids and ferrofluids

The history and development of ferroelectric fluids is a 100-year journey from an early 20th-century theoretical prediction culminating in 21st-century reality. In 1916, physicist Max Born predicted that if a fluid’s molecules possess a strong enough electric dipole, they would naturally form a spontaneously polar (ferroelectric) fluid that can withstand thermal fluctuations.

The concept of a polar, electric-field-responsive liquid was finally transformed into reality in 2017 when scientists experimentally produced the first stable ferroelectric nematic liquid crystals. They successfully synthesizing and identifies the elusive ferroelectric nematic phase in a highly polar rod-shaped molecular material (known in chemistry as RM734). This experimentally proved the existence of 3D fluids with stable, switchable macroscopic electric polarization. (See Science Advances, Development of ferroelectric nematic fluids with giant-ε dielectricity and nonlinear optical properties (2021).)

Ferroelectric fluids are easily confused with ferrofluids, but they are very different. Ferrofluids are colloidal suspensions of magnetic nanoparticles (like iron oxide) in a carrier oil and they respond to magnetic fields. They were developed by NASA’s Steve Papell in 1963 as a liquid rocket fuel that could be drawn toward a fuel pump in a weightless environment by applying a magnetic field. Although that application didn’t work out, these ferrofluids found other uses such as liquid seals around spinning drive shafts and in loudspeakers to remove heat from the voice coil while also passively damping the movement of the cone. In contrast, ferroelectric fluids (FNLCs) are pure or mixture-based 3D molecular fluids. They have spontaneous electric polarity and respond natively to electric fields.

—Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors and signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing, and he also developed significant mechanical-engineering insight while designing control electronics for large materials-testing systems.

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The post A ferroelectric-fluid motor may challenge magnetic-motor designs appeared first on EDN.

USB-C will be 22 years old next month, from a published-specification standpoint. Yet it’s still rife with implementation imperfections. Why? Start with the words “published specification”.

One of the many upsides to my now-dual roles as both contributing and associate editor at EDN is deeper-than-prior insight into what topics, and what content pieces focused on those topics, perform particularly well from various website metrics standpoints. This includes my own stuff, of course; I’m not going to share how it does, either in an absolute sense or relative to my colleagues’ contributions, and I’ll also leave you to decide for yourselves whether that silence is driven by humility, embarrassment, or some combination of the two

I begin with this background information by means of introducing one particular piece of EDN content whose enduring stellar performance I will share with you. Week after week, I’m amazed to repeatedly see the article USB Pinout, Wiring and How It Works perpetually parked at the upper stratum of the site traffic spectrum. What’s particularly mind-blowing to me is that the article’s original publication date was January 26, 2010. Clearly, USB is a topic of enduring interest to you, our treasured readership, for oft-obvious reasons!

The latest generation

The date of this article’s initial appearance in EDN is intriguing for another reason; it arrived 4.5 years ahead of the publication of the version 1.0 specification for USB Type‑C, aka USB-C, and therefore doesn’t include mention of this latest generation of the standard. USB-C usage has subsequently become pervasive, courtesy of factors such as its two-fold rotational (and broader two-end) connector symmetry, in combination with higher data bandwidth (extended beyond USB 3.0, introduced in prior USB connector form factors) and higher power (Power Delivery, i.e., USB-PD, building on a proprietary Qualcomm Quick Charge foundation) transfer capabilities.

Yours truly, for example, has crafted three USB-C-focused pieces in recent years (along with innumerable other more minor mentions), the first one focused on the technology, including its generational development history, and the latter two sharing my personal (underwhelming, to be precise) experiences with it:

• USB: Deciphering the signaling, connector, and power delivery differences
• USB Power Delivery: incompatibility-derived foibles and failures
• USB 3: How did it end up being so messy?

And speaking of popular writeups, my cohort Bill Schweber followed up my USB-PD piece with his own technology treatise:

• USB-C and Power Delivery: Too much of a good thing?

We’re now more than two decades beyond that initial publication date for USB Type‑C Specification 1.0, and I’d love to be able to say that all (or even most) initial implementation warts have been effectively mitigated at this point. I’d love to be able to say that…but I’d be lying if I did. All three of my earlier noted USB-C advancements—connector symmetry, data bandwidth, and power carriage—will unfortunately be demonstrated as enduringly imperfect in the following paragraphs, in fact. Without further ado…

Identity indecision

Let’s start with the fundamentals. Does a particular USB-C cable carry only power? Or power plus data? How much power? And at what peak data transfer rate, if any? Sadly, the answer to these few elementary questions is often consistently unsatisfying, along the lines of “Duh…I dunno. Plug it in, test it and find out for yourself. Then stick an info label on it so you don’t forget.”

Take, for example, this cable:

which came bundled with an inexpensive computer docking station I recently acquired, specifically to test out (and then tear down) its touted DisplayLink capabilities:

By means of association with the specs of its docking station companion, I can make the following cable feature set assumptions:

• Power-plus-data support
• 100W peak power carriage
• 5 Mbps peak data transfer rate

So, if I only use it with the docking station going forward, I’ll inherently likely know what it can (and can’t) do. But what if the dock dies or the cable more broadly get separated and tossed in a drawer with others? It’s unmarked in its entirety, thereby providing no visual notification of its capabilities (and limitations). This unfortunately quite common anonymity rationalizes the recent unveil of the open-source, albeit MacOS-only (and Apple Silicon-only) from a compiled-code standpoint, WhatCable utility, for example:

And even if I was able to retain the original packaging and documentation associated with the cable, those info supplements might still not suffice. Take this cable, which I’d purchased as part of a six-pack from Woot in March 2022 for $17.97, as illustration of the concept:

The cable itself is again a blank slate, specification-wise. And although in this case the connectors are embossed, they’re still meaningfully information-deficient:

What about the box? It’s of little-to-no assistance, either. The front panel claims that it’s “USB 2.0”, which infers (at least to folks with sufficient technical “chops” to decode the terminology, a scant sliver of the overall consumer community, and still not definitively) that it also supports power-plus-data, albeit the latter only rudimentarily, with a 480 Mbps transfer rate.

And what about power carriage? For that we need to turn to the back panel of the box:

Note the “5V⎓3A” terminology at the top, which translates to a 15W peak power spec. That multiplicative exercise outcome stands in stark contrast to the product page, which states that the cable is 60W-capable (therefore explaining the four-plus-year old scribble from yours truly that you’ll see in the picture). I’ve never encountered a 15W USB-C to USB-C cable, in fact, only 60W ones (along with higher-power variants such as 100W, 140W and 240W), although plenty of 15W USB-A (the current-limiting connector) to USB-C cables alternatively exist.

When I reported the discrepancy to Woot after receiving the initial six-cable (three-box) shipment, customer support told me to keep ‘em and sent me free replacements, whose packaging was labeled in exactly the same (incorrect) way. Eventually, I got a full refund and ended up with 12 gratis, albeit power carriage-dubious, cables for my trouble. In revisiting the product page just now while writing this section, I noticed that Woot eventually appended a correction (albeit, the engineer in me is compelled to point out, using the “=” symbol instead of the correct “⎓”…current and voltage being completely different things, don’cha know):

Please note the Amazon Basics box might state “5V=3A”. This is just a standard industry specification for USB-C cables. HOWEVER, these cables do support charging up to 60W (20V=3A) if paired with a charging brick capable of supporting 60W charging and a device capable of receiving 60W charging.

Beware the upside down

This last case study for today also originated in a several-year-old personal experience. As USB-C approached critical marketplace mass, peripheral equipment (mass storage devices, headsets and other audio equipment, etc.) increasingly shipped by default with integrated USB-C connectors versus USB-A with predecessor gear variants. Sometimes, the manufacturer also bundled a USB-C to USB-A adapter for connection to legacy computers and the like, albeit with tradeoffs such as:

• 5 Mbps (USB 3.0) peak transfer speeds, and
• Negation of USB-PD support that might be minimally beneficial, if not functionally flat-out necessary, since only USB-C includes the necessary communication channel (CC) signals for initial protocol handshaking. Strictly speaking, per the USB-PD specification, modulation on the USB-A-supported Vbus and Vgnd signals could also be used for this purpose, but real-life adoption of this alternative technique is scant-to-nonexistent.

Other times, however, to save a few bill-of-materials cents (not to mention avoiding additional expensive technical support sessions), the peripheral manufacturer would dispense with the backwards-compatible adapter, requiring the customer to as-needed alternatively purchase it standalone. So it was that I picked up a set of two inexpensive ($8.09 total) XAOSUN USB-C female to USB-A male adapters from Amazon, since at the time (and, to a lesser degree, even today), the majority of the computers in my stable met the “legacy” (USB-C-less) criteria:

Good news: they support up-to-10 Mbps peak transfer rates, versus the nominal 5 Mbps speed spec’d for others’ adapters. Bad news: this happens only when the peripheral connector is inserted in one of USB-C’s two possible orientations. In the other (also unmarked) orientation, the adapter will pass through data at only USB 2-compatible 480 Mbps peak speeds:

Please note that this USB-C to USB Adapter only supports single-sided 10Gbps high-speed transmission. The Type-C female port allows you to switch between USB 3.1 speed and USB 2.0 speed with a simple flip of the Type C plug. Now you can enjoy unparalleled transmission quality from your devices!

The manufacturer classifies this explanation under an “Easy to Use” category on the Amazon product page listing. I profoundly disagree. Again, as a “techie” I have awareness from past experience of how 10 Mbps (or even 5 Mbps, for that matter) speeds should be perceived by a user, so if things are proceeding slower than expected, I’ll instinctively realize that I need to:

• Cancel the current in-process operation
• Disconnect the peripheral
• Flip the connector by 180° and re-insert, and
• Restart the operation

Conversely, even fundamentally knowing that there’s a problem, far from remembering what’s causing it and how to recover from it, is well beyond the capabilities of the average consumer.

And stepping back, why is this even happening? The answer’s in the “single-sided 10 Gbps” phrasing. As discussed at length in Reddit threads (for example) such as the following:

• What does “single-sided” 10Gbps mean in this adapter?
• Any reliable USB-C (female) to USB-A (male) adapters yet?

this limitation is fundamentally driven by cost-reduction moves made by the manufacturer, specifically in passively routing only one set of SuperSpeed differential source pins to the USB-A destination. Routing both sets of source pins, thereby enabling SuperSpeed operation in both possible USB-C orientations, necessitates active circuitry such as Via Labs’ VL160 or a successor or competitor.

Certification vs compliance

Why do situations like the ones described in this writeup, along with those in prior USB-C coverage from me (reminder: listed at the beginning of this piece, as well as the end), occur at all? Isn’t this something that the USB-IF (Implementers Forum) should be dealing with? The answer to this question lies in the differentiation between “compliance” and “certification”. Although USB-IF encourages compliance (via member workshops, testing by independent labs and other means) to “provide reasonable measures of acceptability”, the organization’s specifications are freely published and available for download and implementation by everyone.

Strictly speaking, manufacturers (and products from those companies) are allowed to license and use the USB-IF logo set only if they’ve successfully passed compliance testing. But by now we’ve all likely come across companies that stick the FCC logo on devices and their packaging even though it’s highly unlikely that those products have even applied for FCC certification, far from achieving it (with an omitted FCC certification ID one obvious tip-off). USB logos are presumably also being used in a similarly cavalier manner.

Retailers can also put pressure to bear on suppliers; some require proof of USB-IF compliance determination before they’re willing to stock a particular product (not to mention a broader manufacturer full product suite), for example. And an excessive return rate can also be effective in compelling a retailer to drop a product, not to mention the company that developed it. Still, at the end of the day this fundamentally remains a caveat emptor situation for consumers.

I’ve got one more notable USB-C-related implementation-challenge situation to discuss, but after just passing through 2,000 words, I’m going to save it for next week’s part-two post. Until then, I welcome your thoughts in the comments on anything I’ve so far discussed!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• USB Pinout, Wiring and How It Works
• USB: Deciphering the signaling, connector, and power delivery differences
• USB Power Delivery: incompatibility-derived foibles and failures
• USB 3: How did it end up being so messy?
• USB-C and Power Delivery: Too much of a good thing?

The post USB-C’s lingering incompatibilities and other complexities, part 1: Direct-connect complications appeared first on EDN.