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TSMC’s 2-nm chip fabrication process, widely known as N2, is on track for production in 2025, according to the details provided by the company at its 2023 North America Technology Symposium in Santa Clara, California. Taiwan’s mega-fab will also add two variants to its N2 technology in 2026: N2P with backside power delivery and N2X for high-performance computing.

The N2 and its variants will be the first manufacturing nodes at TSMC to employ the gate-all-around (GAA) transistors—which TSMC calls nanosheet transistors—to boost performance, energy efficiency, and transistor densities for logic, SRAM, and analog circuits. The GAA technology facilitates lower leakage current as gates are present on all four sides of the channel. Moreover, GAA transistors boost the ability to adjust the channel width for higher performance or lower power consumption.

Figure 1 The announcement of two N2 variants was one of the most prominent highlights of the symposium. Source: TSMC

At the symposium, TSMC claimed that its new nanosheet transistors already meet 80% of the target performance specs, while the average yield of a 256-Mb SRAM is currently above 50%. And the semiconductor foundry still has two years to improve these figures.

According to TSMC, N2 will offer 10% to 15% more performance at the same power as N3 or a 25% to 20% power reduction at the same clocks. The fab also claims that for a mixed chip—comprising logic, SRAM and analog—N2 will accomplish 15% higher density than N3E, an enhanced version of the N3 fabrication node.

Figure 2 The symposium mostly provided details about N2 process node, which was announced last year. Source: TSMC

While the details about TSMC’s N2 technology have been seeping through for a while, what’s new is the announcement about the two new versions of the N2 fabrication node as this advanced fabrication technology extends into 2026. TSMC, which began researching the 2-nm chip fabrication process in 2020, has pursued this cutting-edge chip manufacturing technology relentlessly over the past years.

Below are some details about N2 fabrication node variants—N2P and N2X—which are expected to go into production in 2026, and the chips manufactured on these nodes will likely arrive in 2027.

1. N2P fabrication node

Earlier, when TSMC announced N2 production plans with a nanosheet design, it vowed to add backside power delivery to a future version; that version of 2-nm fabrication has been named N2P. It’s just like PowerVia and BSPDN fabrication technologies from Intel and Samsung, respectively, sandwiching transistors between the power delivery network and the signal network in order to improve transistor performance and reduce power consumption.

Backside power delivery, which decouples I/O and power wiring by moving power rails to the back, addresses challenges like elevated via resistances in the back-end-of-line (BEOL). So, at a time when chipmakers have been fighting resistances in chip power delivery circuitry, backside power delivery enhances transistor performance, reduces their power consumption, and eliminates some potential interference between data and power connections.

Applied Materials estimates that backside power delivery facilitates 20% to 30% logic cell area reductions. Though TSMC hasn’t provided any specifics about N2P technology, a report published in AnandTech claims that backside power rails could account for double-digit transistor density improvements and a single-digit efficiency boost.

2. N2X fabrication node

TSMC is also prepping N2X, a fabrication process tailored for high-performance computing (HPC) devices such as high-end CPUs and GPUs, which need higher voltages and clock speeds. N2X will come after N2P, so information is even more scarce about this N2 variant for HPC applications.

Will Intel catch up?

It’s worth mentioning here that Intel is following a similar trajectory for the 2-nm fabrication process on its 20A process, which also features backside power delivery technology. Intel is planning to take its 2-nm PowerVia fabrication node to volume production in late 2024, and if the Santa Clara, California-based chipmaker is able to execute that successfully, it will leave TSMC behind by nearly two years in the race for implementing backside power delivery.

However, that’s in question, given Intel’s track record in executing cutting-edge process nodes and its challenges in securing the latest extreme ultraviolet (EUV) lithography equipment from ASML. Nevertheless, TSMC has a second contender in the nanometer race besides Samsung.

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• TSMC’s 3-nm progress report: Better than expected
• TSMC approaching 1 nm with 2D materials breakthrough
• A closer look at TSMC’s 3-nm node and FinFlex technology

The post TSMC adds two variants to 2-nm node, will Intel catch up? appeared first on EDN.

Self-heated thermal airflow sensors are simple, cheap, rugged, and sensitive. However, they exhibit an airspeed to sensor temperature response (King’s Law) that is very nonlinear, as shown in Figure 1. 

Figure 1 The TO-92 junction temperature delta versus air speed at 320mW showing the nonlinear relationship between airflow and sensor temperature.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The Figure 1 curve conforms to the empirical formula below, relating junction temperature to power dissipation and airspeed for a self-heated transistor in TO-92:

Tj = Pd(Zj + 1/(Cs + K√Sa))

where:
Tj = junction temperature rise above ambient (oC)
Pd = junction power dissipation (W)
Zj = junction-to-case thermal impedance = 44°C/W
Cs = still-air case-to-ambient conductivity = 6.4 mW/°C
K = “King’s Law” thermal diffusion constant = 0.75 mW/°C/√fpm
Sa = air speed in fpm

Figure 2 shows a practical thermal sensor circuit organized around a Darlington transistor pair: Q1 and Q2.

Figure 2 The self-heated Darlington thermal airflow sensor.

Q1 plays the role of self-heated sensor. Its Vbe tempco converts temperature into voltage at -1.5mV/oC. LM10 200mV reference A1 regulates Q1 current to 0.2V/R3 = 67 mA, thereby forcing Q1’s power dissipation to a constant 67 mA * 4.8 V = 320 mW. The resulting ambient versus junction temperature differential provides an airspeed readout as it cools from 64oC at 0 fpm, to 22oC at 2000 fpm, with a corresponding 63 mV rise in Vbe from 654 mV at 0 fpm to 717 mV at 2000 fpm.

Meanwhile, Q2 provides airspeed-independent ambient temperature compensation.

Feedback through R4 and the accompanying resistor network set a 0-2000 fpm = 0-5 V scale factor with R6 providing zero-flow adjustment. But if meaningful conversion and acquisition of the flow signal are to happen, something will have to be done about that hideous nonlinearity. 

Figure 3 is that something.

Figure 3 The nonlinear VFC is shown, with U1 configured in a 555 astable topology and a Vin resistor network, providing a solution for the previous nonlinearity.

U1 is configured in a fairly typical 555 astable topology, except that the Vin resistor network acts to offset Vthr proportionately to Vin. Thus, as Vin moves from 0 to 5 V, corresponding to an airspeed excursion from 0 to 2000 fpm, the maxima of the Vthr timing ramp begin moving from just barely above the 2/3V+ threshold (corresponding to ~0 Hz), while the minima approach that limit (corresponding to ~2000 Hz). So, as Vin increases in response to increasing airspeed, the timing ramp at pin 6 has a steadily decreasing amplitude. This increases the rate of Hz versus fpm to cancel the opposite behavior of King’s Law (Figure 4’s red curve).

The resultant strongly nonlinear V to F conversion curve provides reasonable linearity compensation of Figure 2’s sensor strongly nonlinear response, as shown in Figure 4’s blue curve to yield a net 1 Hz = 1 fpm calibration.

Figure 4 The linearized VFC airflow response (blue) where the increasing rate of Hz versus fpm cancels the nonlinear effects of King’s Law to yield a 1 Hz = 1 fpm calibration.

Finally, Figure 3’s Q1 PNP current source probably needs a word of explanation. Its ~-2mV/ oC Vbe temperature dependence, in combination with the surrounding Rs, causes its collector current to have an ~+0.3%/oC tempco, which would seem to be a bad thing for conversion accuracy. But it’s just the opposite, Q1’s tempco improves the accuracy of the air speed measurement by compensating for the variation of air density with temperature.

According to ol’ Jacques Clapeyron’s 1834 Ideal Gas Law (PV = nRT), air density (molecules per unit volume = n/V), and therefore heat capacity per unit volume, is inversely proportional to absolute temperature (n/V = P/R/T). Therefore, an accurate measurement of air speed, which is proportional to air volume, implies a direct relationship to absolute temperature, equaling about +0.3%/oC at “room” temperature. Rising ambient temperature causes Q1’s rising collector current to speed up U1’s oscillation frequency by just that factor.

So. Kudos to Q1.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a ways. In all, a total of 64 submissions have been accepted since his first contribution was published in 1974.

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The post Nonlinearities of Darlington airflow sensor and VFC compensate each other appeared first on EDN.

The optoelectronic logic element AND, OR and XOR is considered, the output signal of which can be inverted when the input control signal is applied, thereby converting the logic element into NAND, NOR and XNOR.

Among the assortment of logic chips, there are known chips whose power can be turned on or off by feeding a control signal to one of the inputs of the chip.

The principle of creating a universal optoelectronic logic element with input optical switching of AND/NAND, OR/NOR and XOR/XNOR functions will be discussed below.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The optoelectronic logic element, Figure 1, contains three input control switches of optoelectronic pairs U1.1, U2.1 … U6.1 (optronic pairs are highlighted in color for clarity), made on transistors Q1, Q3 and Q5.

Figure 1 Optoelectronic logic element of universal purpose with optical switching of output functions.

In the absence of input signals, current flows through the LEDs of the optocoupler pairs U2.1, U4.1 and U6.1. When high-level signals are applied to the inputs X1, X2 and F (Mode), the optocouplers switch: current flows through the LEDs of the optocouplers U1.1, U3.1 and U5.1.

When high-level signals are applied to the inputs X1, X2 or F (Mode), the optocoupler pairs switch: current flows through the LEDs of the optocoupler pairs U1.1, U3.1 or U5, respectively, to the input signal.

The receiving part of the logic element contains photodiodes of optocouplers, resistors, as well as output stages on transistors Q2, Q4 and Q6.

When the “Log. 1” and/or “Log. 0” level signals are applied to the control inputs X1, X2 or F (Mode), the signals at the outputs Y1 AND, Y2 OR and Y3 XOR change in accordance with Table 1.

Table 1 Truth table of a universal purpose optoelectronic logic element with optical switching of output functions.

Another simpler version of the implementation of a universal purpose optoelectronic logic element with an input optical switching of functions is shown in Figure 2.

Figure 2 A simpler implementation of a universal purpose optoelectronic logic element with an input optical switching of functions.

The input and receiving parts of the device can be powered from separate power sources (to provide galvanic isolation of input and output) or a single power source.

Such an optoelectronic logic element can be placed in a conventional case DIP10, Figure 3.

Figure 3 Possible type of the housing of a universal optoelectronic logic element chip.

For a visual indication of the involved input F, instead of the diode D3, an LED (Mode indicator) shown in Figures 1 and 2 can be used.

Michael A. Shustov is a doctor of technical sciences, candidate of chemical sciences and the author of over 750 printed works in the field of electronics, chemistry, physics, geology, medicine, and history.

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The post Universal purpose optoelectronic logic element with input optical switching of AND/NAND, OR/NOR and XOR/XNOR functions appeared first on EDN.

TSMC’s 3-nm fabrication nodes mark the final generation of FinFET-based manufacturing processes as the foundry’s 2-nm process nodes will incorporate nanosheets, also known as gate-all-around (GAA) transistors. The mega-fab’s recent 2023 North America Technology Symposium provided ample information on the latest for 3-nm chip manufacturing process nodes.

The information about the baseline 3-nm node, N3, which is currently in production, and details about an enhanced version, N3E, to be launched in the second half of 2023, was made available last year. The N3 node features up to 25 extreme ultraviolet (EUV) layers while using double-patterning on some of them to facilitate higher logic and SRAM transistor density than TSMC’s N5 fabrication node.

On the other hand, N3E utilizes up to 19 EUV layers while not relying on EUV double patterning, which reduces fabrication complexity and costs. However, while N3E offers a wider process window and better yields, it provides lower logic density than N3. As a result, it’s less attractive for chip designs aiming for density and area gains.

Now TSMC is adding new variants to the N3 roadmap to further diversify the 3-nm process technology to meet chip designers’ diverse needs. Below is a brief outline of the three nodes TSMC unveiled at the symposium in Santa Clara, California: N3P, N3X and N3AE.

Figure 1 The 3-nm fabrication nodes have been diversified into a range of processes to meet the needs of a wide range of chips. Source: TSMC

1. N3P fabrication node

N3P, a refinement of N3E, lowers power consumption and bolsters performance and density by adjusting the optical performance of its scanners. In other words, it’s an optical shrink of N3E, providing 5% more speed at the same leakage, 5-10% power reduction at the same speed, and 1.04X more chip density.

N3P’s key objective is to optimize transistor density by building on N3E and improving transistor characteristics. TSMC claims that this 3-nm will boost transistor density by 4% for a mixed-chip design, which according to the foundry, is a chip consisting of 50% logic, 30% SRAM, and 20% analog circuits. N3P, projected to be one of TSMC’s most popular N3 nodes, will be available in the second half of 2024.

2. N3X fabrication node

N3X, tailored for high-performance computing devices like CPUs and GPUs, offers at least 5% higher clock speeds than N3P. While more tolerant of higher voltages, this node enables IC designers to crank up the clock speeds in exchange for higher overall leakage. According to TSMC, the N3X will support around 1.2 V, which is quite high for a 3-nm chip fabrication process.

N3X is a performance-focused node tailored for high-performance computing (HPC) processors for whom power leakage is less of an issue. These processors are commonly used in server-grade hardware with hefty cooling systems. Still, chip designers will have to make an effort to keep these power-hungry processors in check.

It’s also worth noting that N3X will offer the same transistor density as N3P, and its key value proposition is prioritizing performance and maximum clock frequencies for HPC applications. TSMC sources claim that N3X will be production ready in 2025. According to some industry insiders, Intel’s Celestial GPUs will be among the first to use the N3X fabrication node.

Figure 2 The N3P and N3X nodes diversify the fabrication process in terms of chip density and higher voltage tolerance, respectively. Source: TSMC

3. N3AE fabrication node

N3AE or “Auto Early” enables automotive applications on advanced chip manufacturing process technology. It offers automotive process design kits (PDKs) based on N3E and will be available in 2023. The fully automotive-qualified N3AE process will be unveiled in 2025.

Editor’s Note: This is part 1 of the blog series about TSMC’s new fabrication nodes and associated technologies. Part 2 will delve into TSMC’s roadmap for N2 process nodes.

Related Content

• TSMC’s 3-nm Push Faces Tool Struggles
• TSMC Details The Benefits of Its N3 Node
• TSMC’s 3-nm progress report: Better than expected
• TSMC approaching 1 nm with 2D materials breakthrough
• A closer look at TSMC’s 3-nm node and FinFlex technology

The post TSMC upends 3-nm roadmap with three new nodes appeared first on EDN.

I’ve long used, written about and even dismantled various models (and generations of models) of Roku streaming devices. As I write these words, in fact, there are five of ‘em residing in various rooms of my abode. But my office is Roku-less—not reflective of any particular anti-Roku bias, mind you; I’m just striving for evaluation diversity. Instead, connected to a multi-input HDMI switch (and from there to an ancient but still functional large-screen LCD computer monitor) there’s a Google Chromecast with Google TV, which from now on I’ll mostly refer to as the CGTV to keep character count down, and which longstanding readers with long memories may remember made my 2020 holiday shopping-recommendations list:

Specifically, mine’s one of the original 4K resolution-capable units introduced in September 2020, not the newer (September 2022) and less expensive ($29.99 vs $49.99) albeit “only” 1080p-max “HD” model. As I mentioned in that late-2020 writeup, I’d actually paid $89.99 for mine, bundled with 6 months of Netflix service…which unexpectedly ended up getting extended to a year of Netflix service. I like the CGTV a lot; I wish it supported the Android Xfinity Stream app (I can’t help but chuckle when I see Google tech support suggesting that folks sideload the app instead), but right next to it is an Xbox 360 acting as a Comcast-fed Media Center Extender that’s connected to another input of that same HDMI switch, so no biggie.

I actually purchased two CGTV hardware-plus-service bundles; I planned on using the other one when traveling, until I realized that unlike Rokus, there’s no integrated web browser that enables you to log a CGTV into hotel Wi-Fi. Sigh. Regardless, I got a year’s worth of Netflix with that one, too. Do the math and, yes, I only recently started paying for Netflix again ;-). But wait, there’s more! My Google Store account was limited to two “bundles”, but thanks to a separate $10-off coupon, I bought a third 4K CGTV for $39.99, specifically with today’s teardown in mind.

Before diving in, a clarification. You’ve probably already noticed that I’m specifically referring to this as the “Chromecast with Google TV”. This device isn’t solely a streaming media adapter like Google’s conventional Chromecasts (a first-generation one of which I already tore down a few years ago) or even the 4K-compatible Ultra model, all of which are dependent on a tablet, smartphone, computer or other streaming content source. The CGTV, like its Roku siblings, can also act as a streaming adapter, but it’s fundamentally intended to be a standalone device.

Elucidation over, let’s as usual begin with some outer box shots:

Open the lid and the first thing you’ll see inside are two smaller boxes, one obviously labeled as containing the CGTV, the other holding the companion remote control:

Underneath them is a bit of literature:

And underneath that are the power adapter and cable, along with a set of AAA batteries for the remote control:

Here are some images of the various box-content bits, in some cases, accompanied by a 0.75″ (19.1 mm) diameter and 0.06” (1.52 mm) thick U.S. penny for size comparison purposes:

Note the 5V/1.5A power requirement of the CGTV:

Now about that remote control…

It’s somewhat unique in that it comprehends both Bluetooth and IR (infrared) protocols, along with containing a microphone for voice control as an alternative to the various front buttons. Bluetooth is for connectivity to the CGTV, which is nice because it doesn’t require line-of-sight. And since the CGTV’s HDMI 2.0 output supports the CEC (Consumer Electronics Control) protocol, you can also use the remote to manage power on/off, volume and input selection for a HDMI-connected TV or soundbar (assuming, of course, that it’s also HDMI-CEC cognizant). Alternatively, if the TV or soundbar is IR-based, the CGTV’s remote can also directly manage it; the CGTV software embeds common control code sets, which you configure in the device settings for your specific IR-based product. Here are photos of it absent its protective baggie:

Sorry, folks, but that’s all you’re going to see of the remote. I want to keep it intact as a spare, just in case the primary ever gets lost between the sofa cushions, doncha know.

On to the CGTV:

The product dimensions, direct from Google’s published specs, are “6.4 x 2.4 x 0.5 in (162 mm x 61 mm x 12.5 mm), not including cables or accessories” and the weight is “56.7 g (2 oz)”. A majority of that total 6.4” length, perhaps obviously is the HDMI cable; the main body is 3” long. Here are some overview shots:

And here’s a closeup of the bottom-side product markings, including the all-important FCC IC, A4RGZRNL (the FCC ID for the newer “HD” version of the CGTV, conversely, is A4RG454V):

Wireless protocols supported by the CGTV, thereby explaining the FCC certification necessity, include (again from Google’s published specs):

• 11ac Wi-Fi (2.4 GHz/5 GHz) with WPA2 support (for network connectivity)
• Bluetooth 4.2 (for the remote control)

Before I forget, by the way, you can also network-connect the CGTV via wired Ethernet. How, you might ask, since there’s no Ethernet port on the device itself? Well, Google also sells a separate $19.99 accessory power adapter with integrated Ethernet connectivity:

Alternatively, I’ve personally tested and confirmed that a USB-C hub (one with an Ethernet port, of course) can also be used to implement wired network connectivity, assuming it also supplies sufficient power to the CGTV. This approach offers the added bonus of supplementing (via the hub’s integrated USB ports for flash “thumb” drives, SD slots for memory cards, and the like) the CGTV’s limited available (especially after O/S updates and apps) on-board storage capacity.

Back to our patient. You’ve likely already noticed the seam around the sides. That’s our path to the insides. My unit ended up being more sturdily glued, therefore less easy to crack open, than this one apparently was, but with patience as my guide I finally got inside with minimal cosmetic-or-more collateral damage (at least I think so; keep reading):

Check out all that blue thermal paste! Note that we’re looking at the (supposed) top of the device, which I mention in the spirit of “heat rises”. That said, given that the CGTV is designed to dangle from the horizontally (right-side-up or upside-down; I’ve encountered both) or vertically aligned HDMI connector of a television, orientation cues are somewhat meaningless.

The topside heatsink covering the PCB is held in place by four screws:

Remove them and the heatsink wriggles right off, revealing…yay, more thermal paste!

Next, let’s detach the HDMI cable (which represents yet another departure from the earlier-linked other teardown video, for which the attachment mechanism was seemingly more complex; this one popped right off):

With all six screws and the HDMI cable removed, the PCB comes right out of the remaining bottom half of the case:

Interestingly, particularly given my earlier orientation-is-essentially-meaningless observation, there’s no thermal paste between the heat sink and case insides this bottom-side time:

Although, once you wriggle the heatsink off, you’ll once again find plenty of paste inside:

Let’s get it off, aided by some rubbing alcohol, although it flaked off pretty much all by itself using only a fingernail:

At center is the system SoC, Amlogic’s S905. I find its inclusion curious, for both selection and location reasons. It’s the exact same processor found in the Spotify Car Thing, the subject of one of last month’s teardowns. And it’s on the underside of the PCB—recall my earlier “heat rises” and “no bottom-side heatsink-to-case paste” comments, somewhat counterbalanced by my earlier “orientation is somewhat meaningless for something that dangles” comment. That said, we’ll soon see how else Google tackles the SoC heat dissipation challenge.

Below the Amlogic S905 is a Hynix H9HCNNNBKUMLHR-NME 16 Gbit LPDDR4-3733 SDRAM. And to the left, sequentially left-to-right, are the power-and-status LED, the hardware reset switch, and the underside of the USB-C connector.

Speaking of sides, after flipping the PCB back over to its topside:

and cleaning off the paste as much as possible:

several more ICs come into view. The first, in the upper right quadrant of the PCB, was paste-less from the start; it’s a Samsung KLM8G1GETF-B041 8 GByte eMMC flash memory. Again, this is eerily similar to the recently dissected Spotify Car Thing, which also included eMMC-based nonvolatile storage, albeit 4 GBytes in capacity and sourced from Toshiba/Kioxia in that case. Conversely, there’s more deviation in the volatile memory realm; the Car Thing’s SDRAM was 4 Gbit in capacity, 933 MHz in speed, DDR3L in technology type, and Etron-sourced.

Below the eMMC is the CGTV’s wireless connectivity nexus, a Broadcom-then-Cypress Semiconductor-now-Infineon Technologies BCM43598 “single-chip IEEE 802.11 b/g/n MAC/baseband/radio with integrated Bluetooth 5.1 compliance”, quoting from the datasheet. Below it, as well as above the eMMC, are the two associated PCB-embedded antennae. And to the right of both chips is another blue blob of thermal paste, whose function may not be intuitively obvious. Its location corresponds to that, on the other side of the PCB, of the Amlogic S905, and embedded in it are various passives commonly found intermingled in the ball grid array (in this particular case) or other pinout layout underneath CPUs. I therefore deduce that it’s a topside (again, “heat rises”) supplemental means of removing heat generated by the SoC.

Finally, what of the “resurrection opportunity” mention in the title of this teardown? As you may have already noticed, I didn’t have to rip the top off any Faraday Cages this time; more generally, my disassembly of the device (including the pry-apart of the two halves of the clamshell case) was non-destructive…at least I think it was. I’m going to wait until this writeup is published, in case I need to snap any additional and/or replacement photos, etc., then I’ll clean off the rest of the old thermal paste and replace it with fresh grey goo, put the insides back in place and glue the two halves of the case back together, and see if it lives again.

An appropriate aspiration given that I’m writing these words on the eve of the fourth Sunday of Lent, yes? Keep an eye out for a success-or-not epilogue in the comments. And speaking of which, I as-always welcome your thoughts there, too!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post Google’s Chromecast with Google TV: Car accessory similarity, and a post-teardown resurrection opportunity? appeared first on EDN.

TSMC is bolstering its existing relationships with EDA companies by having their design tools certified for its N3E and N2 process nodes. Top EDA firms have announced a range of new certifications and collaborations with long-time partner TSMC coinciding with the TSMC 2023 North America Technology Symposium.

At the event, TSMC provided details about its 3-nm and 2-nm chip manufacturing process nodes called N3 and N2, respectively. While N3 is a baseline node, N3E is an enhanced version with reduced cost and better yield; it’s expected to be introduced in the second half of 2023. On the other hand, the N2 process node is on track for production in 2025.

The readiness of digital and custom/analog EDA flows and related process design kits (PDKs) for these advanced nodes will be crucial for TSMC in successfully launching these advanced process nodes. The trio of large EDA houses seem onboard, and below is a synopsis of their undertakings to prepare for the N3E and N2 process nodes.

1. Cadence

Cadence Design Systems claims its digital and custom/analog flows have been certified to support TSMC’s new Design Rule Manual (DRM) for the fab’s N3E and N2 nodes. The two companies have jointly delivered PDKs for N3E and N2 processes to facilitate mobile, artificial intelligence (AI), and hyperscale computing IC designs at these advanced nodes. Cadence has collaborated with TSMC on its complete RTL-to-GDS flow for use with TSMC’s N3E and N2 nodes.

Figure 1 The digital implementation and signoff flow supports a variety of new design features, including native hybrid cell row optimization from synthesis to signoff engineering change order (ECO) for optimal power, performance and area (PPA), cell pin alignment, and connection support. Source: Cadence

Cadence has also announced the tapeout of its 16G UCIe 2.5D advanced package IP on TSMC’s N3E process node. The UCIe IP facilitates chiplet for die-to-die communication, which is becoming increasingly critical in AI and machine learning (ML), mobile, automotive, storage and networking applications, currently driving the need to move from monolithic integration to system-in-package (SiP) chiplets.

2. Siemens EDA

Siemens EDA’s Calibre nmPlatform tool for IC verification sign-off is fully certified for TSMC’s N3E and N2 processes. The two companies have also joined hands to certify Siemens’ mPower analog software for transistor-level electromigration and IR drop (EM/IR) sign-off for TSMC’s N3E process.

Figure 2 The Calibre platform for IC verification sign-off has been certified for TSMC’s N3E and N2 nodes. Source: Siemens EDA

Then there is the Analog FastSPICE platform for circuit verification of nanometer analog, RF, mixed-signal, memory, and custom digital circuits, which has achieved TSMC certification for the foundry’s N5A, N3E, and N2 processes. The EDA toolmaker has also upgraded its Tanner software, which helps IC designers lay out analog and mixed-signal ICs.

3. Synopsys

Synopsys will deliver digital and custom design EDA flows on TSMC’s most advanced node, the N2 process, which leverages nanosheet transistors to offer up to 15% speed improvement at the same power or 30% power reduction at the same speed when compared with TSMC’s N3E process.

Sanjay Bali, VP of Strategy and Product Management for the EDA Group at Synopsys, acknowledged that the latest N2 process is pushing the edge of design physics. He said collaboration on N2 builds on the company’s certified EDA and IP solutions for TSMC’s 3-nm process technology with several dozen successful tapeouts. For example, Bali mentioned the in-chip process, voltage and temperature (PVT) monitor IP to boost N3 designs.

In October 2022, Synopsys provided details of its certifications for TSMC’s N3E process. Besides certified design flows and IP readiness, Synopsys is working closely with TSMC to scale physical verification in the cloud while using the Synopsys IC Validator product for N3E on the Synopsys Cloud software-as-a-service offering. That allows chip designers to access unlimited CPU capacity in the cloud for faster physical verification iterations.

Figure 3 IC Validator, a physical verification signoff solution, offers distributed processing scalability to over 4,000 CPU cores. Source: Synopsys

For AI-driven design enablement, Synopsys’ DSO.ai technology and Fusion Compiler have also been validated for multiple N3E test cases with better PPA and faster design closure.

Related Content

• TSMC’s 3-nm Push Faces Tool Struggles
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• TSMC approaching 1 nm with 2D materials breakthrough
• A closer look at TSMC’s 3-nm node and FinFlex technology

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Nexperia’s PSC1065K SiC Schottky diode comes in a real-2-pin (R2P) TO-220-2 plastic package that enhances reliability in high-voltage applications at temperatures up to 175 °C. This industrial-grade device has a repetitive peak reverse voltage (VRRM) of 650 V, forward current (IF) of 10 A, and non-repetitive peak forward current (IFSM) as high as 440 A.

The merged PiN Schottky (MPS) structure of the PSC1065K adds robustness against surge currents and eliminates the need for additional protection circuitry. Additionally, the PSC1065K offers temperature-independent capacitive switching and zero forward and reverse recovery behavior. These features reduce system complexity and enable hardware designers to achieve higher efficiency with smaller form factors in rugged high-power applications.

Nexperia offers its 650-V, 10-A SiC Schottky diodes in four high-voltage compliant R2P packages with higher creepage distance. These R2P packages include DPAK, D2PAK, TO-247-2, and TO-220-2, designated the PSC1065-H, -J, -L, and –K, respectively. Applications for these devices include switched-mode power supplies, AC/DC and DC/DC converters, battery-charging infrastructure, uninterruptible power supplies, and photovoltaic inverters.

PSC1065K product page

Nexperia

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Two MEMS-based oscillators, the SiT1623 and SiT1625 from SiTime, provide a high-temperature, low-power timing reference for automotive connectivity protocols. Both of the AEC-Q100 qualified devices perform under extreme conditions and provide the robust system performance and stability required in harsh automotive environments.

Grade 1 oscillators operate over a temperature range of -40°C to +125°C and can be used for automotive ADAS, electronic control units, and infotainment systems. The SiT1623 offers 9 commonly used fixed frequencies between 8 MHz and 50 MHz, while the SiT1625 offers a choice of 12 fixed frequencies between 8 MHz and 100 MHz. Frequency stability for both parts is ±25 PPM (85°C), ±30 ppm (105°C), and ±50 ppm (125°C). RMS phase jitter is 750 fs for the SiT1623, dropping to 500 fs for the SiT1625.

The SiT1623 and SiT1625 consume 1.8 mA and 2.3 mA, respectively, when operating at 1.8 V. Four industry-standard packaging options are available: 1.6×1.2 mm, 2.0×1.6 mm, 2.5×2.0 mm, and 3.2×2.5 mm.

Engineering samples of the SiT1623 and SiT1625 oscillators are available now to qualified customers. General sampling will be available in July 2023. Volume production is expected in early 2024.

SiT1623 product page

SiT1625 product page

SiTime

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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The R&S ESMW monitoring receiver covers a frequency range of 8 kHz to 40 GHz with a real-time bandwidth of up to 2 GHz. Useful for fixed and mobile spectrum monitoring, the instrument’s ITU-compliant RF performance and modular upgradability enable it to measure both current and future wideband signals in high-density spectrum environments.

The ESMW calculates real-time spectrum by applying FFT signal processing with at least 50% overlap. Signals as short as 75 ns can be reliably detected with 100% probability of intercept (POI) and full amplitude accuracy. A panorama scan option for the ESMW enables the instrument to perform spectral scans with speeds of up to 2.6 THz/s and adjustable frequency resolution. With a real-time bandwidth of 2 GHz, panorama scans are perceived as almost real-time operation.

In addition to standalone operation, the ultra-wideband ESMW can be used to upgrade existing R&S radio monitoring systems thanks to backward compatibility with the company’s ESMD and ESME wideband monitoring receivers. Its open remote-control interfaces and well-documented output data formats also enable integration into various third-party systems.

ESMW product page

Rohde & Schwarz 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Guerrilla RF announced the release of two high-linearity gain blocks for infrastructure applications, such as 5G base stations, automotive telematics, and cellular repeaters. Extending the gain coverage of GRF’s existing portfolio of general-purpose RF/microwave gain blocks, the GRF2010 and GRF2011 GaAs pHEMT amplifiers provide nominal gain levels of 10 dB and 15 dB. Since all of the gain blocks come in 1.5×1.5-mm DFN-6 packages, existing designs can be modified to achieve different levels of gain, linearity, and noise figure.

When operating with a nominal 5-V bias and single match covering 400 MHz to 4000 MHz, the GRF2010 draws 90 mA of current while delivering a gain of 10 dB, OIP3 linearity of 36 dBm, OP1dB compression level of 20 dBm, and a noise figure of 3.1 dB. The GRF2011, with a single match tune of 700 MHz to 3800 MHz, increases the gain offering to 15.2 dB with OIP3 linearity of 40 dBm, OP1dB compression of 22.7 dBm, and a lower noise figure of 2 dB. Both devices can be tuned to operate over lower frequencies reaching down to 50 MHz.

Samples and evaluation boards for the GRF2010 and GRF2011 gain blocks are available now, with prices starting at $0.85 each in lots of 10,000 units.

GRF2010 product page

GRF2011 product page

Guerrilla RF 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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A 24-Gb/s Graphics Double Data Rate 6 (GDDR6) PHY IP core from Rambus enables a high-bandwidth memory interface for AI/ML, graphics, and networking applications. At 24 Gb/s per pin, the GDDR6 PHY offers a maximum bandwidth of 96 GB/s for each GDDR6 memory device. It can be paired with the Rambus GDDR6 digital controller IP to provide a complete GDDR6 memory interface subsystem.

Available in advanced FinFET nodes for ASIC or SoC integration, the GDDR6 PHY IP core is fully compliant with the JEDEC GDDR6 (JESD250C) standard and supports two independent 16-bit–wide channels. The PHY leverages the manufacturer’s high-speed signal integrity and power integrity expertise and is optimized for systems requiring high-bandwidth and low latency, such as generative AI.

A DFI 3.1 style interface allows easy integration of the PHY core with the memory controller. While the Rambus GDDR6 PHY and GDDR6 controller can be used together, these cores can also be licensed separately to work with third-party GDDR6 controller or PHY solutions. The Rambus GDDR6 PHY is supplied as a fully characterized hard macro (GDSII), along with complete design views and documentation.

GDDR6 PHY product page  

GDDR6 controller product page  

Rambus

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Silicon carbide (SiC) technology continues to make headlines, and the latest byte has come with Bosch’s acquisition of a U.S. fab in Roseville, California. More importantly, Bosch will invest $1.5 billion to upgrade TSI Semiconductor’s manufacturing facility, and by 2026, the fab will start producing 200-mm SiC wafers.

That resonates with the proposition echoed at APEC 2023 in Orlando, Florida in March: Take old silicon fabs and upgrade them with SiC-specific tools. Here, it’s worth mentioning that the front end of SiC manufacturing isn’t much different from silicon power devices like IGBTs.

TSI, founded in 1984, produces large volumes of chips on 200-mm silicon wafers for applications ranging from mobility to telecommunications to energy. It has a workforce of 250 people, and after the retooling phase, the fab will have roughly 10,000 square meters of clean-room space.

Source: Bosch

The deal also underscores a critical fact: Bosch is bolstering its semiconductor business in general and SiC investment in particular. In summer 2022, the German manufacturing giant announced to invest 3 billion euros in its semiconductor business in Europe. Bosch has also hinted about being a contender for the federal U.S. funds from the CHIPS and Science Act as well as state and local incentives. Furthermore, it has been stated that the initial $1.5 billion investment in SiC manufacturing in Roseville is only the starting point.

Earlier in 2021, Bosch began working on SiC components while using proprietary processes to mass-produce them at its Reutlingen plant near Stuttgart. The company expects to have extended its clean-room space in Reutlingen from roughly 35,000 to more than 44,000 square meters by the end of 2025.

Bosch’s move is significant at a time when there is a huge demand for electric vehicles (EVs), and SiC semiconductors are increasingly becoming a technology choice for EV inverters and other crucial building blocks like on-board charging (OBC). The United States is the second largest automobile market, and given the rapid uptick in demand for SiC semiconductors, this deal comes at a pivotal time.

Moreover, at a time when the substrate and wafer costs have become a major stumbling block in SiC’s mass advancement, a new player joining the fray may accelerate the efforts for creating the economy of scale for SiC wafers.

Related Content

• SiC and GaN: A Tale of Two Semiconductors
• The diverging worlds of SiC and GaN semiconductors
• SiC and resurgence of semiconductor vertical integration
• Silicon carbide (SiC) and the road to 800-V electric vehicles
• APEC 2023: SiC moving into mainstream, cost major barrier
• Silicon carbide’s wafer cost conundrum and the way forward

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The good folks from whom you obtained your SPICE tool have made all kinds of assumptions in setting up their device models. However, some of those assumptions might not agree with some of the published data sheets for the simulated devices. We can see this peril just by looking at one very simple example.

Those famous words of the character “Sportin’ Life” in George Gershwin’s opera “Porgy and Bess” have an applicability here that Mr. Gershwin never envisioned.

Please consider this excerpt from a respected supplier’s datasheet for the 1N4148 diode in Figure 1.

Figure 1 An excerpt from the 1N4148 datasheet. Source: John Dunn

One might assume from this chart that if 100 µA of reverse current flow were acceptable, one could apply up to 100 volts of reverse voltage across the diode. With that assumption in hand, I can picture myself happily using the 1N4148 at 100 volts as I go ahead with a SPICE simulation of my design. Then to my embarrassment, I would find that my simulation does not work.

In looking for the reason for my failure, I might set up a SPICE simulation to trace the characteristic curve of the 1N4148 which would yield the result in Figure 2.

Figure 2 Characteristic curve examination for the 1N4148 used at 100 volts. Source: John Dunn

I would discover that the 1N4148 in my version of SPICE exhibits reverse breakdown with an application of only 80 volts which is nowhere near the 100 volts of my supplier’s data sheet.

Looking at two steady state conditions would provide the breakdown confirmation (Figure 3).

Figure 3 A confirmation of the reverse voltage breakdown of the 1N4148. Source: John Dunn

At 79 volts, the 1N4148 simulation carries a little more than 14 µA but if I take that reverse voltage up to 81 volts, the current shoots up to more than one ampere.

Just for fun, I took the reverse voltage up to 100 volts and the simulation current rose to 30.91 amperes. Try to picture a puny little 1N4148 trying to carry that much current. The device would be dissipating more than three kilowatts.

What was that flash?

The object lesson of all this is that if you are pushing a component to anywhere near a maximum rating and you are using a simulation tool to evaluate your design, make sure that your simulation models conform to your assumptions and conform to published data about each and every component’s rated maximums.

They might not.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

 Related Content

• Don’t rely on the automatic settings of your SPICE simulator
• Where to stimulate when you simulate
• It’s time to SPICE up your life!
• A lesson in delta-sigma conversion
• Simulation trouble: Bode plotting an oscillator

The post The device model matches the published data—that ain’t necessarily so appeared first on EDN.

Total harmonic distortion (THD) is the harmonic distortion present in a signal, defined as the ratio of the root-mean square (RMS) amplitude of a set of higher harmonic frequencies to the RMS amplitude of the first harmonic, or fundamental frequency. Equation 1 expresses THD:where Vn is the RMS value of the nth harmonic and V1 is the RMS value of the fundamental component.

In power systems, these harmonics can cause problems ranging from telephone transmission interference to conductor degradation; therefore, it is important to control the total THD. A lower THD means a lower peak current, less heating, lower electromagnetic emissions, and less core loss in motors.

Reducing THD needs a power factor correction (PFC), which is required for AC/DC power supplies that have input power greater than 75 W. PFC forces the input current to follow the input voltage such that the electronics load draws a sinusoidal current waveform that contains minimal harmonics.

THD requirements have become stricter, especially in server applications. The Modular Hardware System-Common Redundant Power Supply (M-CRPS) specification [1] defines a very strict THD requirement across the entire load range, as shown in Table 1. This is much stricter than the previous CRPS THD specification.

Table 1 The M-CRPS THD specification. Source: Texas Instruments

Meeting such strict THD specifications is a big challenge in PFC designs where traditional loop tuning may not be enough. In this article, I’ll suggest a few extra methods to help reduce THD.

 Make sure that the sensed signals are clean

The PFC controller senses the AC input voltage, inductor current and PFC output voltage. These sensed signals need to be clean; otherwise, they will affect THD. For example, because the AC input voltage signal generates a sinusoidal current reference, any spikes on the sensed signal will cause current reference distortion and affect THD.

Although the output voltage (VOUT) signal is not used for generating a current reference, it can affect THD because the spikes on VOUT will cause a ripple on the voltage-loop output, which affects the current-loop reference and eventually THD. If the spike’s magnitude is large enough, it may trigger a voltage-loop nonlinear gain, significantly raising THD.

One common practice is to put a decoupling capacitor close to the sense pin of the controller. You will have to carefully select the capacitance such that it will effectively reduce the noise but not cause too much delay. Using a digital infinite impulse response filter to process the sensed VOUT signal will further reduce the noise; because the PFC voltage loop is slow, the extra delay caused by this digital filter is acceptable.

For AC voltage sensing, however, it is not recommended to add a digital filter because it will cause a delay on the current reference. In this case, you can use a firmware phase-locked loop (PLL) to generate an internal sine wave signal in phase with the AC voltage, and then use that generated sine-wave signal to modulate the current reference. Since the PLL-generated sine wave is clean, even if there is some noise on the sensed AC voltage, the current-loop reference will also be clean.

Reduce the current spikes at AC zero crossing

Current spikes at AC zero crossing are an inherent issue for the totem-pole bridgeless PFC. These spikes can be so big that it becomes impossible to pass M-CRPS THD specifications. I’ve analyzed the root cause of these spikes [2], and noted that a pulse-width modulation (PWM) soft-start algorithm, as shown in Figure 1, will effectively reduce them.

Figure 1 Gate signal timing for AC zero crossing. Source: Texas Instruments

In this solution, when VAC changes from a negative to a positive cycle after AC zero crossing, active switch Q4 turns on first with a very small pulse width, then gradually increases to the duty cycle (D) generated by the control loop. A soft start on Q4 gradually discharges the switch-node drain-to-source voltage (VDS) to zero. Once Q4’s soft start is complete, synchronous transistor Q3 starts to turn on. It begins with a tiny pulse width and gradually increases until the pulse width reaches 1-D. When Q4’s soft start is complete and Q3’s soft start begins, the low-frequency switch Q2 turns on.

The zero-crossing detection could be undesirably triggered by noise. For safety purposes, at the end of the half AC cycle, turn off all of the switches. This leaves a small dead zone that will prevent the input AC from short-circuiting. The transition from the AC positive cycle to the negative cycle is the same. Figure 2 shows the test result.

Figure 2 Current waveforms without and with a PWM soft start: the traditional control method (a) and PWM soft start (b). Source: Texas Instruments

Reduce voltage-loop effects

The double-line frequency ripple on the voltage-loop output can affect the current reference and thus THD. To reduce this frequency ripple effect as much as possible—while at the same time not sacrificing the load transient response—you could add a digital notch (band-stop) filter between the VOUT sensed signal and the voltage loop. This notch filter can effectively attenuate the double-line frequency ripple while still passing all other frequency signals, including the sudden VOUT change caused by the load transient. The load transient will not be affected.

Another approach is to sense VOUT at the AC zero-crossing instance. Since the VOUT value at AC zero-crossing instance Vout_zc(t) equals its average value and it is a “constant” in steady-state, it is the perfect feedback signal for voltage-loop control. To handle the load transient, use this voltage-loop control law:

If ((Vref – Vout(t) < Threshold)
{
              Error = Vref – Vout_zc(t);
              VoltageLoop_output = Gv(Error, Kp, Ki);
}
Else
{
              Error = Vref – Vout(t);
              VoltageLoop_output = Gv(Error, Kp_nl, Ki_nl);
}

If the instantaneous VOUT error is small, use the VOUT value at the AC zero-crossing instance Vout_zc(t) and small proportional-integral (PI) loop gain Kp, Ki for voltage-loop compensator Gv. When a load transient occurs causing an instantaneous VOUT error greater than the threshold, use the instantaneous Vout(t) value and PI loop gain Kp_nl, Ki_nl for Gv to rapidly bring VOUT back to its nominal value.

Oversampling

The PFC inductor current is a saw wave with DC offset in each switching cycle; the current then goes to a signal-conditioning circuit such as an operational amplifier to make the signal suitable for the PFC control circuit. However, this signal-conditioning circuit does not provide sufficient attenuation to the input current ripple. The current ripple still appears at the output of the amplifier. If this signal is sampled only once in each switching period, there is no perfect, fixed location where the signal represents the average current all of the time. Thus, with a single sample, it is very difficult to achieve good THD.

To get a more accurate feedback signal, I recommend an oversampling mechanism. Figure 3 shows that it is possible to evenly sample the current feedback signal eight times in every switching cycle, average the results, and send them to the control loop. This oversampling effectively averages the current ripple out such that the measured current signal gets closer to the average current value. Also, the controller becomes less sensitive to noise—both signal noise and measurement noise. Oversampling is one of the most effective ways to reduce current waveform distortions.

Figure 3 Oversampling eight times in every switching cycle. Source: Texas Instruments

 Duty-ratio feedforward

The basic idea of duty-ratio feedforward control [3] is to pre-calculate a duty ratio, then add this duty ratio to the feedback controller. For a boost topology operating in continuous conduction mode, Equation 2 gives the duty ratio (dFF) as:

This duty-ratio pattern effectively produces a voltage across the switch whose average over a switching cycle is equal to the rectified input voltage. A regular current-loop compensator changes the duty ratio around this calculated duty-ratio pattern.

Figure 4 depicts the resulting control scheme. After using Equation 2 to calculate dFF, it is then added to the traditional average current-mode control output (dI). You could then use the final duty ratio (d) to generate a PWM waveform to control PFC.

Figure 4 Average current-mode control with dFF. Source: Texas Instruments

Since the majority of the duty cycle is generated by duty-ratio feedforward, the control loop only adjusts the calculated duty slightly. This technique can help improve THD for applications with a limited controller loop bandwidth.

AC cycle skipping

In general, it’s harder to meet light-load THD requirements than heavy-load THD requirements; this is especially true for the 5% load THD requirement in the M-CRPS specification. If the PFC meets all other THD requirements except at a 5% load, even if you have tried all the methods mentioned so far, an AC cycle-skipping method can help.

Think of AC cycle skipping as a special burst mode: when the load is less than a pre-defined threshold, the PFC enters this mode and, depending on the load, skips one or more AC cycles. In other words, the PFC turns off for one or more AC cycles and turns back on for the next AC cycle. The turn-on and turn-off instance is at the AC zero crossing such that the whole AC cycle is skipped. Since PFC turn-on and turn-off at current equal zero, there is less stress and electromagnetic interference. AC cycle skipping is different than the traditional PWM pulse-skipping burst mode, where you skip PWM pulses randomly.

The number of AC cycles to skip is reverse-proportional to the load; the less load, the more AC cycles skipped. Figure 5 shows the skipping of one AC cycle. Channel 1 is the AC voltage, and channel 4 is the AC current.

Figure 5 AC cycle skipping at a light load. Source: Texas Instruments

When the PFC turns off because the current is zero, THD is zero. Since the PFC needs to compensate for the turn-off period, it delivers a large amount of power when it turns on, which is greater than the average value. Essentially, this operates the PFC either at medium load, or completely turns off. Since THD is much lower at a middle load than at a light load, light-load THD is reduced.

Test results

I implemented the methods described in this article on a 3-kW totem-pole bridgeless PFC [5] controlled by a Texas Instruments C2000 microcontroller. Figure 6 shows the THD test result at 240 VAC.

Figure 6 THD test results. Source: Texas Instruments

The THD not only meets the latest M-CRPS THD specifications but also has plenty of margin, which guarantees that the PFC will meet specifications during mass production, even with hardware tolerance.

Bosheng Sun is a systems, application firmware engineer at Texas Instruments.

 Related Content

• Power Tips #115: How GaN switch integration enables low THD and high efficiency in PFC
• Power Tips #114: A potential firmware mistake may lead to control instability
• Power Tips #113: Two simple isolated power options for 8 W or less
• Power Tips #112: Onboard fixtures for fault testing

References

1. The Open Compute Project. n.d. Open Possibilities. Accessed April 10, 2023.
2. Sun, Bosheng. “How to Reduce Current Spikes at AC Zero Crossing for Totem-Pole PFC.” Texas Instruments Analog Design Journal article, literature No. SLYT650, 4Q 2015.
3. Van de Sype, D.M., Koen De Gusseme, A.P.M. Van den Bossche, and J.A. Melkebeek. “Duty-Ratio Feedforward for Digitally Controlled Boost PFC Converters.” Published in IEEE Transactions on Industrial Electronics 52, no. 1 (February 2005): pp. 108-115.
4. Sun, Bosheng. “AC Cycle Skipping Improves PFC Light-Load Efficiency.” Texas Instruments Analog Design Journal article, literature No. SLYT585, 3Q 2014.
5. Texas Instruments. n.d. “3-kW, 180-W/in3 Single-Phase Totem-Pole Bridgeless PFC Reference Design with 16-A Max Input.” Texas Instruments reference design No. PMP23069. Accessed April 10, 2023.

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The modern farm has been both blessed and cursed by the advancement of technology. Modern agricultural and horticultural techniques have enabled higher crop yields with smaller footprints supporting ever-growing populations. However, the quality of today’s farm fresh food has been deteriorating, while the quantity is still not enough to keep farmers profitable.

The agriculture industry is inherently unstable. This is largely due to the impact of external environmental circumstances on yield from year to year. The desire for more consistency and sustainability in agriculture is driving the adoption of another kind of modern technology in this industry (Figure 1). Enter the smart farm.

Figure 1 Farmers can remotely monitor crops and livestock health, providing valuable information that ensures consistency in the agricultural industry. Source: Microchip

The availability of networked livestock monitoring systems has increased the number of healthy animals, leading to improved quality of food. Soil and plant health monitors provide farmers with the ability to monitor crop health to levels of detail not previously possible. Thanks to today’s embedded networked sensor systems, the “smart farm” of the future will have the tools and capabilities needed to increase yield and profitability while still supporting the quality levels required by discerning customers.

The information that is gathered from these sensors can help guide farmers in making the best decisions for their farms, allowing them to nurture crops and livestock to higher productivity levels while decreasing the use of water, pesticides, and fertilizer. This can help reduce the farm’s impact on its natural environment and improve the quality of the land; thus, ensuring sustainability for generations to come.

Embedded and wireless key enablers

Simply put, the principal solution for ensuring sustainability in the modern farm is to supply usable information to farmers. Due to the innovation of today’s embedded and wireless technologies, this objective can be achieved by implementing massive arrays of low-cost networked sensors. These sensors will typically monitor on-location conditions—temperature, pH, moisture, activity data and GPS coordinates—from farmland or livestock. Next, these sensors will transmit this data via wireless communication networks such as 4G/5G cellular and LoRa to a centralized and typically cloud-based database.

The data can then be accessed online by any Internet-connected device, and quickly analyzed to determine if corrective actions are needed. This allows a farmer to access the farm’s analytics from anywhere in the world.

Networked sensor nodes are not a new concept; but to ensure a level of performance and reliability in this uniquely difficult space, some key requirements must be met. First, they need a reliable power source, which is a challenging situation to resolve since a farm does not come with 1,000-foot extension cords.

Nodes would need to be battery-powered and efficient enough to last months or even years without battery replacement. This challenge requires high system efficiency which is typically achieved by implementing a microcontroller (MCU)-based system that can manage various complex tasks without heavy core CPU usage and power down when the system is inactive.

Second, sensor nodes on the smart farm need to remain operable in harsh, remote areas and perhaps even be attached to animals. The entire system is exposed to the elements which requires practical but innovative solutions to ensure robustness and functionality. Nodes would need to remain in the field for long periods of time and require very little hardware service. All software updates need to be completed remotely and securely. This requires reliable remote connectivity via the most common wide area networking (WAN) infrastructure at the farm’s locale.

When designing networked systems destined for smart farm applications, engineers must anticipate an incredibly wide variety of plants and animals being monitored. Plant health monitoring systems may measure various environmental conditions—including water levels, soil conditions, pH levels and light levels—while livestock trackers may incorporate GPS coordinates, gait monitors, pulse oximeters, and other sensors that monitor key health data points.

In either case, an ideal commercial solution would be a common base node design that can be easily adapted to the needs of the individual farm at the time of purchase. To achieve this, the base node must be flexible enough to interface with a wide variety of analog and digital sensors.

Another, more difficult design challenge concerns the wide variety of engineering disciplines needed to implement in such a system. Smart farm component designers or engineering teams need to have expert-level experience in classical embedded design techniques, RF communication—including the ins-and-outs of LoRa, Wi-Fi, and cellular topology—and network security in addition to being well-versed in cloud infrastructure.

Enter 8-bit MCUs

The path to scaling smart farm infrastructure starts in a place that isn’t commonly thought of when discussing cutting-edge applications. Since the vast majority of sensor nodes on the smart farm are battery powered, remotely located and sporadically maintained, the optimal control solution must involve the most power-efficient microcontrollers on the planet.

The 8-bit MCUs have been with us for 50 years, and while they have always been the lowest-power option for most embedded tasks, the newest devices have been modernized to directly address the needs of smart agricultural and horticultural systems. Among the many new features, the core independent peripherals (CIPs) available on PIC and AVR microcontrollers are a “force multiplier” for embedded design.

CIPs can act independently from the chip’s CPU, which allows designers to set them up to handle common and repetitive tasks with the lowest amount of power consumed. An additional benefit that CIPs provide in low-maintenance environments is their ability to help designers increase system reliability. Since CIPs are programmed as though they were tiny FPGAs included with the MCU, they are effectively immune to software excursions such as stack overflows or underflows.

Interfacing with a wide variety of digital and analog sensors using the same Internet-connected base node controller can be a challenge. Fortunately, there are modern MCUs that are designed for this very application while minimizing external componentry. Such MCUs offer SPI and I2C interfaces for digital sensor connectivity as well as differential analog-to-digital converter (ADC) with programmable gain amplifier (PGA) and digital-to-analog converter (DAC) for a high level of sensor flexibility (Figure 2). This gives designers the freedom to build highly customizable and modular sensor nodes for smart farm applications.

Figure 2 Small, efficient MCUs are key to sustainability in smart farming. Source: Microchip

Alongside the modernization of MCU architectures, their accompanying development hardware and software environments have also come a long way. For engineering teams at small companies where embedded systems, RF antenna design and cloud connectivity are not all core competencies, rapid prototyping boards are life savers. This provides designers with an easy example to follow and even includes a GitHub repository with firmware to connect with popular cloud providers.

Remote sensor technology

Today’s agriculture and horticulture industries are undergoing a technological revolution. Access to plant and animal health data via the Internet in real-time is transforming the way farms are run, with a result of ever-higher yields and increased land viability (Figure 3).

Figure 3 The 8-bit MCU-enabled remote sensor technology to monitor farm health ensures that crops receive the necessary care to thrive. Source: Microchip

At the forefront of this revolution is “available anywhere” cloud connectivity, but its foundation will continue to be built with the venerable 8-bit microcontroller. Modern MCU architectures, such as AVR and PIC with CIPs, will be key components to bridge the gap between sensor and cloud for developers of sustainability-enhancing products—now and into the future.

Grace San Giacomo is an engineer at Microchip Technology’s 8-bit microcontroller business unit.

Related Content

• IoT in Agriculture and Farming
• Building the Open-Source Connected Farm
• The Rise of Digital and Precision Agriculture
• Sensors, Networks Enable Precision Agriculture
• Precise Positioning Improves Automated Agriculture

The post How 8-bit MCUs enable smart farm technology appeared first on EDN.

After announcing to increase prices of its processor IPs and joining hands with Intel for tying its mobile system-on-chip (SoC) designs with the 18A process of Intel Foundry Services (IFS), Arm has come up with another major pre-IPO initiative. According to a Financial Times story, Arm has embarked upon the most advanced chipmaking effort to demonstrate the power and capabilities of its designs to the wider market.

It’s worth mentioning that Arm has built some test chips in the past with partners such as Samsung and TSMC, but that was largely aimed at enabling software developers to gain familiarity with Arm’s new products. This one is a more advanced undertaking than ever before; a solutions-engineering team will lead the development of prototype chips for mobile devices, laptops, and other electronics applications.

Kevork Kechichian will lead this solutions-engineering team for building prototype chips. He joined Arm’s executive team in February 2023 after previous stints at NXP and Qualcomm, where he oversaw the development of Qualcomm’s Snapdragon chips.

It’d be interesting to watch how chip suppliers—Arm’s customers—respond to this move. People at Arm are quick to point out that the Cambridge, UK-based company has no plans to sell or license the chip and that it’s only working on a prototype. It’s crucial because Arm has hugely benefited from its position as being chip supplier agnostic, selling processor IP cores to chip designers while not directly competing with them.

However, Arm has recently telegraphed signs that it’s open to overhauling its decades-old business model. For instance, in its recently published annual report, Arm acknowledged that its significant customer base concentration is a major risk to its business. In 2022, Arm’s top 20 customers accounted for 86% of its revenues. That’s crucial in the backdrop of Arm’s current legal dispute with Qualcomm, one of its largest customers.

On the surface, the move looks akin to Google’s benchmarking of smartphone hardware for Android OS with the Pixel phone. Brady Wang, a semiconductor analyst with Counterpoint Research, told Financial Times that the move is similar to Google building Pixel phones and Microsoft launching Surface laptops. Arm sources also claim that the new team building prototype chips is aiming to expand on the company’s existing efforts to enhance the performance and security of designs and bolster developer access to its IP products.

However, when seen in the backdrop of SoftBank’s push for growth and seeking out changes to its commercial practices, the implications of this move could go far beyond the intentions telegraphed by Arm in the Financial Times story. Far more could unravel soon as Arm nears its IPO.

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• Designing With ARM–Looking back and looking forward
• Product How To: DFT strategy for ARM processor-based designs

The post Arm’s prototype chips: What it means for the IC industry? appeared first on EDN.

Back in the fall of 2019, I mentioned that I’d recently switched from longstanding-wearing a series of Wear OS-based smartwatches to regularly donning Garmin’s fēnix 5 instead:

Roughly 3.5 years later, the fēnix 5 remains my smartwatch “daily driver”. Why? This excerpted paragraph from my earlier writeup concisely summarizes the reasoning:

The fēnix 5 loses only about 10% of its charge each day under normal operating conditions, translating to more than a week between recharges…This all is, in a word, liberating. I can wear it like a watch, not like a vampiric battery-sucking mobile electronics device, but I still benefit from the really important stuff that makes smartwatches great, such as notifications of incoming emails, texts, phone calls, and voicemails, and reminders about upcoming appointments.

I’m also pleasantly surprised at how well the watch’s integrated (i.e., non-user-replaceable, at least not officially) battery has held up. Then again, when you’re only recharging it once a week or thereabouts, the battery charge cycle count doesn’t escalate rapidly. That said, although a week-plus is still a heck of a lot better than “less than a day”, I’ve long wondered how much longer a watch developer could stretch the recharge latency without significantly hampering the watch’s “smart” aspects, via clever design, implementation techniques and the like.

Enter Withings’ Steel HR, whose intro dates from the January 2017 CES. Here’s a stock photo:

And here’s a company-published video:

France-based Withings may not be a familiar name to some of you. The company, founded in 2008, was acquired by Nokia in April 2016 and became independent again (accompanied by a resurrection of the original brand name) two years later. Withings focuses predominantly on consumer electronics devices with a health “angle”; they’re probably best known for their line of “smart” body scale products. And yes, for any of you who regularly follow CES coverage, they also introduced the U-Scan, a toilet-installed urine analysis device, in Las Vegas this year. Engadget’s…err…hands-on testing video is hilarious (IMHO), well worth a 5+ minute watch:

Unsurprisingly, Withings also develops and sells fitness trackers along with health-tailored smart watches such as the Steel HR. It normally costs $179.99, which gave me pause, but when I found one in “Used-Very Good” condition on the Warehouse area of Amazon’s site for less than half that price, $79.84 ($99.80 minus a 20%-off promotion), I couldn’t resist. Here’s what it looks like on my wrist; mine’s the 40 mm black face and silver body color combo option with the standard silicone wristband (my wife also got me leather and metal bands for Christmas):

The mechanical hands are a classy touch, at least to this old-timer, and are one key aspect of the long battery life. The lower circular inset on the face is also mechanical in nature and provides easy access to the current day’s step count status (remember the earlier mentioned health angle?). But it’s the upper circular inset, the fundamental difference between the two images, that likely caught your eye. It’s a low-power monochrome OLED display. By default, it’s off. Press the crown, and it activates and illuminates for a user-configurable time duration. Sequentially press the crown while the display is active, and the watch cycles through various operating mode options (again, user-configurable, both display-or-not and order):

• Date and time
• Heart rate
• Steps
• Distance
• Active calories
• Notifications on/off toggle (global…keep reading)
• Battery level
• Alarm
• Stopwatch
• Timer
• And various workout modes (after an initializing long-press of the crown)

First-time pairing with my Google Pixel 4a 5G was brain-dead easy (and a firmware update was awaiting me), and ongoing Bluetooth connectivity is rock solid. Here’s a collection of initial-setup screenshots I captured, for your perusal (some of them contain lingering pop-ups for the prior screen capture’s Android notification in the lower left corner; just overlook this cruft):

About that battery level…it’s the crux of the Steel HR’s appeal to me. Withings estimates it’ll deliver up to 25 days (more than three weeks) of battery life between charges. To date, I haven’t worn mine for more than a few days at a time; that said, I haven’t seen the battery level drop below 100% yet. Tradeoffs? Sure. The electronic display is a miniscule percentage of the total watch face area, not its entirety; you’re probably not going to want to read an incoming text message on it, far from a full-length email.

Speaking of incoming text messages and other things, specifically notifications related to them, they’re conversely my sole notable frustration with the Steel HR. You can selectively enable and disable on-watch notifications on a per-smartphone-app basis—yes to text messages but no to email, for example. But, unlike with my Garmin, which I keep permanently in “do not disturb” mode, with the Steel HR you can’t disable haptic vibration for active notifications in order to rely solely on display notifications. A constantly vibrating widget on my wrist is the fast track to a straightjacket in a padded room, so I’ve got all notifications perpetually “off”. Withings engineers, please add a “mute” capability in a future software update, no matter that I might end up missing some notifications if I depend solely on the diminutive OLED!

Other than that (OK, a display of the current temperature at my location would also be nice), and with the qualifier that, as I said in my prior writeup:

Wearables are, unsurprisingly, a highly personal decision; what works great for one person may be lousy to another, and visa versa, due to feature-selection and -prioritization individuality.

I’m personally delighted with the Steel HR (here’s another—note, dated—review perspective). It delivers on pretty much everything I expect a wearable to do:

• Tell me the time and date
• Track and display my daily step count, and my pulse rate (both immediate and trending)
• In combination with a GPS-inclusive tethered smartphone, log distance traveled
• Timer-alert me when my steaks are ready to turn, for searing purposes, and
• Wake me up from a nap (if I selectively enable notifications, as previously discussed) as well as track my sleep statistics

Your thoughts on this and similar reduced-function but correspondingly expanded-battery life wearables, versus their beefier-featured but more charger-dependent counterparts, are welcomed in the comments. Or anything else that my discussion here has spurned, of course!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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• Teardown: A smartwatch with an athletic tradition
• Apple Watch: Smart but not smart enough

The post Withings’ long-running smart watch: Just don’t call it a swatch appeared first on EDN.

With dimensions of just 120×120×24 mm, the Vista-X90 Plus adaptive long-range lidar unit from Cepton easily fits behind a vehicle’s windshield. It can also be seamlessly embedded into the automobile’s roof, headlamps, or fascia. Compared to its predecessor the Vista-X90, the Vista-X90 Plus is 62% slimmer and enables over a 58% reduction in sensor footprint.

Doubling the data rate of the Vista-X90, the slim Vista-X90 Plus achieves high resolution for improved perception. A real-time software-tunable region of interest allows the sensor to maintain an optimized balance between performance and power efficiency across various driving scenarios.

Vista-X90 Plus has a 90° horizontal field of view and a maximum detection range of 200 m at 10% reflectivity. Angular resolution is 0.07° within the region of interest. This automotive-grade ISO 26262 ASIL B-compliant unit consumes less than 13 W of power, making it suitable for all types of passenger cars, as well as electric vehicles.

Aimed at automotive OEMs to enable the safe deployment of next-generation ADAS, the Vista-X90 Plus costs under $500 in volume quantities.

Vista-X90 Plus product page

Cepton

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Semtech’s SX9376 specific absorption rate (SAR) sensor optimizes RF control while maintaining compliance with global SAR standards for 5G-enabled consumer devices. The IC automatically adjusts system-level RF emissions, allowing connected devices to operate at peak performance with improved connectivity.

A member of the company’s PerSe Connect portfolio of human-sensing chips, the SX9376 accommodates eight sensor inputs to support multiple antennas. This simplifies sensor design without compromising performance and regulatory compliance. The chip is compatible with various antenna designs, allowing its integration into 5G mobile devices like smartphones, tablets, and laptops.

The SX9376’s high-resolution analog front end provides capacitance resolution down to 0.74 aF and capacitance offset compensation of up to 600 pF. Built-in temperature correction minimizes false triggers caused by both noise and temperature.

The PerSe Connect SX9376 SAR sensor comes in a 1.8×1.9×0.55-mm QFN package. Log in or register at mySemtech to access product documentation.

SX9376 product page

Semtech

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Operating over a temperature range of -40°C to +105°C, SimpleLink CC33xx Wi-Fi 6 ICs from TI provide stable connections across more than 220 access points. These companion ICs work with TI and other companies’ MCUs and processors that support Linux or real-time operating systems, enabling wireless communication for such use cases as building automation, EV charging systems, and medical equipment.

The CC3300 is a Wi-Fi 6-only device, while the CC3301 is a combination Wi-Fi 6 and Bluetooth Low Energy 5.3 device. Both 2.4-GHz chips feature orthogonal frequency-division multiple access (OFDMA) and target wake time (TWT) to improve efficiency and conserve power. The SimpleLink parts also support Wi-Fi Protected Access (WPA) security features, including WPA3 cryptographic technologies for personal and enterprise networks and secure boot with firmware authentication.

Samples of the CC33xx companion ICs are available in QFN packages, with prices starting at $1.60 in lots of 1000 units. Volume production is expected in Q4 2023. An evaluation board, the BP-CC3301, is available for purchase on TI’s website for $39.

CC33xx product page

Texas Instruments

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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