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Updated: 2 hours 52 min ago

Instrument improves oscilloscope calibration

Fri, 04/05/2024 - 16:01

A multichannel oscilloscope calibration system, the Fluke 9500C automates time-consuming testing to maintain scope accuracy and reliability. The 9500C provides simultaneous output on all channels and can be fully automated with MET/CAL software for hands-free operation.

A core component of the 9500C mainframe is the 9540C active head. Each mainframe can control up to five heads, enabling the calibration of a 4-channel oscilloscope with an external trigger. The ability to actively drive all four active heads at the same time with simultaneous output results in faster test times and eliminates lead changes.

The compact 9.4×4.6×2.2-cm active head generates calibration signals at the oscilloscope input. It enables the 9500C to deliver various signals: DC levels up to ±220 V, calibrated amplitude square waves up to 210 V pk-pk from 10 Hz to 100 kHz, and leveled sinewaves from 0.1 Hz to 4 GHz with precisely controlled pulse edges.

If full automation is not immediately required, the 9500C can be configured with just a few, or even one, active head. Additional heads can be easily added as needs change. To request a price quote, use the link to the product page below.

9500C product page

Fluke Calibration 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Reference designs offer LoRa gateway solutions

Fri, 04/05/2024 - 16:00

LoRa Corecell full-duplex gateway reference designs from Semtech are tailored to address applications operating in the U.S. 915-MHz and China 490-MHz ISM bands. Both the SX1302CFD915W1-H (915-MHz) and SX1302CFD490GW1 (490-MHz) reference designs leverage Semtech’s LoRa Core SX1302 digital baseband IC and SX1255/7 RF transceiver.

The reference design files are available to download from the Semtech website. While evaluation kits are not offered for purchase, the hardware used in the design comprises a Corecell board populated with the LoRa Core chips, a duplexer, and a Raspberry Pi. The design supports full-duplex operation with eight uplink channels and one downlink channel.

Using the capabilities of the SX1302 baseband IC, the uplink channels can detect up to 64 LoRa packets and simultaneously demodulate 16 125-kHz LoRa packets with spreading factors between SF5 and SF12. The SX1302 also provides one 125/250/500-kHz demodulator for single SF operation and one (G)FSK demodulator for legacy applications.

The gateway implementation achieves a tenfold reduction in power compared to the previous generation of LoRa baseband ICs. With a discrete power amplifier and low-noise amplifier, transmit output power at the antenna port can be up to +27 dBm. Receive sensitivity can be as low as -140.8 dBm for the U.S. 915-MHz band and -137.4 dBm for the China 490-MHz band.

To learn more about the LoRa Corecell full-duplex gateway reference designs, read Semtech’s blog here.

SX1302CFD915GW1-H product page

SX1302CFD490GW1 product page


Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Smart gate driver controls automotive motors

Fri, 04/05/2024 - 15:59

Toshiba’s SmartMCD series of gate drivers with embedded MCUs offers sensorless control of three-phase BLDC motors in automotive applications. The first entry in the series, the TB9M003FG combines a 32-bit Arm Cortex-M0 core, 64 kbytes of flash memory, and power control functions for driving N-channel power MOSFETs in drive systems for water pumps, oil pumps, fans, and blowers.

The integration of a microcontroller helps reduce design size and component count, while enabling complex motor control. To minimize the load on the MCU, the gate driver employs a vector engine and hardware for sensorless sinewave control. Communication interfaces include a LIN transceiver and controller, two full-duplex serial interfaces (UARTs), and one SPI-I/F.

The TB9M003FG is AEC-Q100 Grade 0 qualified and operates over a temperature range of -40°C to +175°C. Toshiba has started volume shipments of the SmartMCD TB9M003FG gate driver. A reference design using the TB9M003FG in a motor drive circuit for automotive body electronics is available here.

TB9M003FG product page 

Toshiba Electronic Devices & Storage 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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LoRa module aims to simplify wireless design

Fri, 04/05/2024 - 15:59

The integrated Type 2GT multiband LoRa radio module from Murata reduces IoT device complexity and streamlines the certification process. It provides LoRa and Long Range-Frequency Hopping Spread Spectrum (LR-FHSS) communication over sub-GHz and 2.4-GHz ISM bands, as well as the satellite S-Band.

Along with Semtech’s LR1121 RF transceiver, the Type 2GT module contains a temperature-compensated crystal oscillator, a second 32-kHz crystal, an RF switch, and an RF matching network. Communication interfaces include SPI and multiple GPIOs. Housed in a 9.98×8.70×1.74-mm metal LGA package, the Type 2GT operates over a temperature range of -40°C to +85°C with a supply voltage of 1.8 V to 3.6 V.

The Type 2GT radio module is certified to European CE and American FCC standards, the Japanese TELEC standard, and the Canadian IC standard. Designers can reuse the module’s RF test reports across different certification authorities, easing compliance challenges.

Samples of the Type 2GT LoRa transceiver are available now. The part has also entered mass production.

Type 2GT product page

Murata Manufacturing 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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The ML-enabled edge MCUs available in three design tiers

Thu, 04/04/2024 - 20:10

A new family of microcontrollers optimized for machine learning (ML) applications at the edge claims to enable real-time command and response, eliminating the need for cloud connections while substituting high-performance microprocessors.

Infineon Technologies has unveiled the next generation of PSOC microcontrollers that are AI-enabled for real-time responsiveness in connected home devices, wearables, and industrial applications. The new PSOC Edge E8 series of MCUs—E81, E83, and E84—facilitates compute responsive AI while balancing performance and power requirements and providing embedded security for Internet of Thing (IoT), consumer, and industrial applications.

Figure 1 The new edge MCUs enable developers to quickly move from concept to product and facilitate ML-enabled IoT, consumer, and industrial applications. Source: Infineon

The PSOC Edge E81 utilizes the Arm Helium DSP technology and Infineon’s NNLite Neural Network (NN) accelerator. It uses a combination of Cortex-M55 plus DSP for the high-performance domain and Cortex-M33 and DSP for the low-power domain. E81 microcontrollers are primarily targeted at cost-effective design solutions.

The PSOC Edge E83 and E84 microcontrollers, while offering the same combination for high-performance and low-power domains, also use the Arm Ethos-U55 micro-NPU processor and provide a 480x improvement in ML performance compared to existing Cortex-M systems. At the same time, E83 and E84 use the NNlite accelerator for ML applications in the low-power compute domain.

The microcontroller trio

Steve Tateosian, senior VP of industrial MCUs for IoT, wireless and compute business at Infineon, spoke to EDN before the release of PSOC Edge E8 series MCUs. He said that the ML-enabled edge MCU classification aims to facilitate the right product for the right application at the right price point. He quoted a thermostat as an example to explain how these MCU tiers work.

With an E81 microcontroller, a basic thermostat may have an LCD doing cloud-based natural language recognition. On the other hand, a mid-range thermostat may want to recognize voice locally by implementing natural language on device itself, thus removing cloud from the equation altogether. That’s an E83 microcontroller.

Finally, for Nest-like high-end devices, designers can add features like gesture and motion control as well as low-power graphics display—up to 1028×768—for a rich graphical user interface (GUI). “All three devices support voice/audio sensing for activation and control, while the E83 and E84 MCUs deliver increased capabilities for advanced HMI implementations, including ML-based wake-up, vision-based position detection, and face/object recognition,” said Tateosian.

Figure 2 Three ML-enabled PSOC edge MCUs aim to facilitate the right product for the right application at the right price point. Source: Infineon

“Designers can create a cost-effective solution with E81, but if they want to add a stronger ML acceleration hardware, they move to E83,” he added. “They can use E84 if they want to add graphics support.”

Design support services

All three edge MCUs support extensive peripheral sets, on-chip memory, robust hardware security features and a variety of connectivity options including USB HS/FS with PHY CAN, Ethernet, WiFi 6, BTBLE, and Matter. “The PSOC Edge E8 series MCUs feature a rich peripheral mix with many options in terms of in-memory as well as external memory support,” Tateosian said.

When designing ML applications on edge devices, engineers must be conscious of the amount of code in general,” he added “So, the amount of memory as well as the type of memory located on the MCU are critical.” These MCUs offer an elegant solution in terms of on-chip RAM encompassing SRAM and RRAM content.

Hardware design support includes an evaluation base board with Arduino expansion header, sensor suite, BLE connectivity for provisioning and Wi-Fi for smartphone, and cloud connectivity. On the software side, the new PSOC Edge E8 series MCUs are compatible with the earlier versions of PSOC for edge MCUs to ensure that design engineers can reuse their software investments.

Moreover, Infineon’s ModusToolbox software platform provides a collection of development tools, libraries, and embedded runtime assets to complement the development experience. It also integrates Imagimob Studio, which Infineon acquired through its purchase of the Swedish firm last year. It delivers end-to-end ML development capability spanning from data to model deployment.

Infineon will demonstrate the capabilities of this MCU series for AI and ML applications at Embedded World in Nuremberg from 9 to 11 April 2024.

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Solar-mains hybrid lamp

Thu, 04/04/2024 - 17:52


Solar day lamps (SDL) are simple and cost-effective. A few examples of SDLs have been described in [1], [2] and [3]. An SDL without any energy storage element suffers from frequent changes in the light intensity. Also, a backup is required after sunset. The design of a hybrid lamp is given here. It uses solar PV panels and mains power sources and provides constant light output. This design can utilize solar energy even when the panel output is down to 10%. Proportionately, that much load is reduced on the mains supply.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Block diagram

The block diagram of proposed hybrid lamp is shown in Figure 1. It consists of an array of LEDs lamps: A1 to A9. Each of these lamps consists of five, 1 W white LEDs connected in series. These LEDs are controlled using the LED driver circuits.

Figure 1 Block diagram of the hybrid lamp design with 9 LEDs lamps where each lamp consists of five, 1 W white LEDs connected in series and all LEDs are controlled using LED driver circuits.

LEDs are powered using a 30 watt-peak (Wp) PV panel as well as from an adapter (AC-DC converter) as shown in Figure 1. The LED drivers are controlled through 9 digital output (DO) pins of the MCU. Solar panel voltage Vpvs is sensed using a potential divider circuit and is connected to the ADC input pin of MCU. Similarly, current flowing through the first LED array A1 is sensed and is connected to another ADC pin. The adapter output voltage VMF is sensed using potential divider circuit and is connected to a digital input (DI) pin of the MCU. This is a digital signal which is used to sense whether adapter power is available or not. One more DO pin is connected to the “adapter standby mode” pin to reduce power consumed by the adapter when all arrays are powered from solar panel and adapter is on no load.

Circuit Diagram

Figure 2 shows the circuit diagram. The adapter output VM is connected to the top (red) rail of the circuit. After passing through diode D19 (1N5822), voltage VMD is applied to the circuit. Similarly, the middle rail (yellow) is connected to the solar panel output Vpv. After passing through diode D20, voltage Vpvd is applied to the circuit. A big filter capacitor C2 (10000 µF 35V) is connected across panel terminals. This capacitor will eliminate sudden changes in panel voltage so that the firmware runs smoothly.

Figure 2 Circuit diagram of the proposed hybrid lamp where the adapter output VM is connected to the top (red) rail of the circuit and to the solar panel output Vpv is connected to the middle rail (yellow).

LED driver circuit for array A1 is shown in full detail. Array A1 consists of 5 white LEDs connected in series. It is connected to the ground terminal through R1; a 10 Ω, 2 W resistor. The voltage drop across R1 (Ipv1) is connected to ADC1 (pin 24) of the MCU IC3 ATMEGA 8 as shown in Figure 3. A1 is driven by two PNP transistors T3 and T4 (2N4033). Transistor T3 is controlled by the digital output PD0 of the MCU through NPN transistor T1 (BC546). The PD0 signal is inverted using the NOT gate of IC1 (74HCT04). This signal drives transistor T2 which drives T4.

When PD0 is LOW → T3 OFF, T4 ON (A1 on solar and green indicator LED2 ON)
When PD0 is HIGH → T3 ON, T4 OFF (A1 on mains and red indicator LED1 ON)

In the same way, remaining arrays A2 to A9 are controlled through their respective digital output signals. Note that resistors R2 to R9 are connected to the anodes of the LED array. This is done to reduce the wiring, as single ground wire connects to all the cathodes of the last LEDs of A2 to A9.

Figure 3 The MCU connection diagram.

The MCU and LED driver circuits are powered using regulator IC4 (LM7805). It’s input is connected to both VMD and Vpvd power rails through D21, D22, R77 and R78. Hence, 5 volts is available on either solar or mains power sources.

Figure 4 shows the circuit diagram of all digital outputs. It includes two 74HCT04 ICs, IC1 and IC2, for inverting a total of 9 digital output signals. The 18 output lines are connected to the LED driver circuits through 18 diodes D1 to D18 (1N4148). Figure 5 shows the assembled PCB with LED driver circuits and the MCU interface.

Figure 4 Interconnection diagram of all digital outputs, 18 output lines are connected to the LED driver circuits through 18 diodes (D1 to D18).

Figure 5 Assembled PCB showing LED driver circuits and MCU interface.

 Adapter (AC-DC converter) selection

Figure 6 shows the adapter used in the prototype having output voltage of 18 V. However, ideally to match the voltage at max power (Vmp) of the solar panel we need 17.5 V. One diode in series can drop the voltage by about 0.7 V. There are adapters available which have provisions for adjusting the output voltage within ±10% tolerance. Using this type of adapter, it is possible to set the output voltage to 17.5V.

Figure 6 Photographs of the 30 Wp, 2’ x 2’ solar panel (top) and 18V, 3 A adapter (bottom). A diode is used to drop the voltage closer to the ideal 17.5 V to match the Vmp of the solar panel.

 Specifications and calculations

The solar panel specifications are as follows:

  1. Power Rating (P) = 30 Wp
  2. Voltage at MAX Power (Vmp) = 17.5 V
  3. Current at MAX Power (Imp) = 1.714 A

The calculations for the LED lamp are as follows:

  1. Forward voltage of white LED = 3.12 V
  2. Current through array A1 = [17.5 – (5 x 3.12)] / 10Ω = 0.19 A
  3. Power consumed by array A1 = 17.5 * 0.19 = 3.325 W
  4. Power consumed by 9 LED arrays = 9 x 3.325 = 29.9 W


As discussed earlier, the hybrid lamp draws power from both solar PV panels and the adapter. If both supplies are present, then it runs a maximum power point tracking (MPPT) algorithm to maximize solar power. Table 1 shows the operating modes.

Table 1 Operating modes of the hybrid lamp. If both supplies are present, the design runs an MPPT algorithm to maximize solar power.


The following are the variables used for the algorithm:

  • n: Number of arrays which are PV Powered (n = 9 is initially set to handle full solar power)
  • PV_POWER: power drawn from PV panel
  • PRESENT_MODE: present mode of operation
  • NEW_MODE: new mode of operation

The permissible numerical values of PRESENT_MODE and NEW_MODE are as follows where valid value(s) of n are indicated in the brackets for each mode:

  • 0: Solar Day Lamp mode (n = 9)
  • 1: Mains Powered mode (n = 0)
  • 2: MPPT (n varies from 1 to 9)


The following are the constants used for the algorithm:

  • POWER_MIN: The minimum value of power. If PV power is < POWER_MIN, then declare solar not present. (POWER_MIN = 1 W or 1600 counts)
  • P_DELTA: This value is used for generating hysteresis. (P_DELTA = 1 W OR 1600 Counts)
  • VPV_MIN: This value is used for checking whether PV power is available or not. PV Power is not available if Vpv < VPV_MIN. (16 V OR 800 Counts of ADC0)


The following is the data used for the algorithm:

  • Array P(n): This data is used by the algorithm to control LED lamps A1 to A9. Table 2 shows the array of constants defined over 10 power levels.

Table 2 An array of constants defined for 10 power levels.

ADC details

The following are the ADC specifications. A count of 1024 corresponds to a 5 V input to the ADC pin:

  • ADC resolution: 10 bits (1024 counts)
  • ADC reference voltage = 5 V

Vpv calculations

Solar panel output Vpv calculations are as follows:

  • VPV_MIN = 16 V (when MPPT is running, Vpv is maintained above VPV_MIN)
  • ADC input voltage for VPV_MIN = 16 * 0.2444 = 3.91 V
  • ADC count for 3.91 V = (1024/5) * 3.91 = 801

VPV_MIN calculations

VPV_MIN calculations are as follows:

  • VPV_MIN = 16 V (when MPPT is running, Vpv is maintained above VPV_MIN)
  • ADC input voltage for VPV_MIN = 16 * 0.2444 = 3.91 V
  • ADC count for 3.91 V = (1024/5) * 3.91 = 801

 Ipv calculations

Solar panel output current Ipv calculations are as follows:

  • Panel power at maximum power point = 30 W
  • Current at maximum power point = 30/17.5 = 1.714 A
  • When all arrays A1 to A9 are ON, Current through each array = 1.714/9 = 0.19 A
  • Drop across 10 Ω resistor R1 = 10 * 0.19 = 1.9 V
  • ADC Count for 0.19 Amp = (1024/5) * 1.9 = 390 count

Power calculations

Finally, the power calculations can be seen below:

  • Read ADC0 → Count for VPVS
  • Read ADC1 → Count for IPV1
  • PV_POWER_32 = ADC0 * ADC1 * n
  • PV_POWER = PV_POWER_32 / 64 (Shift right by 6 bits)
  • PV power generated when one array is ON = 876 * 390 = 341640 counts
  • PV power generated when 9 arrays are ON (30W) = 341640 * 9 = 3074760 counts

To limit the resolution to 16 bits, the counts are divided by 64:

  • Count for 30 W -> 3074760 / 64 = 48043.125
  • Count for 1 W -> 48043/ 30 = 1601.4375 Count or 1600 approx

Flow charts

The flow charts required for development of embedded firmware are given in Figure 7, Figure 8, Figure 9, and Figure 10. At power ON, the algorithm initializes timer, ports, modes and enables timer interrupt. The algorithm is executed inside the timer interrupt service routine.

Figure 7 Initialization flow chart where at power ON, algorithm initializes timer, ports, modes and enables timer interrupt.

Figure 8 A portion of the interrupt service routine where the algorithm is executed.

Figure 9 The rest of the interrupt service routine where the algorithm is executed.

Figure 10 The MPPT flow chart that is run if both supplies are present.

 Fabrication and testing

The LED lamp metal core PCBs (MCPCBs) were mounted on three aluminum channels. The aluminum channels absorb the heat generated by these PCBs and provide structural support. The controller PCB is mounted on the back side of the LED array. The working of hybrid lamp is captured in the photographs shown in Figure 11 and Figure 12 where the lamps are working on 100% solar power and 100% mains power respectively. The lamp is placed in front of a mirror to check the light output from LED array. Simultaneously, we can see the PCB and the indicator LEDs. From these two Figures, it is clearly seen that we get same light output whether the array is solar powered or mains powered.

Figure 11 Lamp working on 100% solar energy (all green indicator LEDs are ON).

Figure 12 Lamp working on 100% mains power (all red indicator LEDs are ON).

In order to capture the dynamic workings of the lamp, when the solar energy is varying and the MPPT algorithm is running, see the video below.

In this video, we are able to see LED array light output in the mirror and also observe the indicator LEDs changing from green to red and vice versa sequentially. In this case, the solar panel is rotated in the sunlight to vary the PV power generated. This video confirms that the MPPT algorithm is working properly as the LED array gives a constant light output when there is wide variation in solar power. One green LED is ON, meaning 11% of the energy is coming from solar. So, depending upon the number of green LEDs that are ON, we can calculate the percentage reduction in the load on the mains power supply.

When the whole array is running on solar power, we can make the digital output line going to the standby input of the adapter high (refer to Figure 1). Thus, reducing the power consumed by the adapter under no-load condition. Please note that this feature has not been implemented in the present code.

 Power ASIC design

The hardware complexity can be reduced by designing a dedicated power ASIC. The main features of the proposed ASIC are as follows:

  1. Number of LED driver circuits: 16
  2. MAX Voltage rating of drivers : 50 V
  3. MAX current rating of each driver: 0.5 A
  4. Regulated control power supply: 5 V, 1A
  5. Sensing circuits for: Vpvs, Ipv1, VM

 Design of a 500 W fixture

Based on the hybrid lamp design given here, a larger lighting fixture can be designed. Here, an example of such a system, which uses a single 500 Wp solar panel is given. The high-level details of proposed design are as follows:           

  1. PV panel specifications: 500 Wp, Vmp = 35 V, Imp = 14.2 A
  2. LED lamp power rating:11 Watts (11 white LEDs connected in series)
  3. Number of lamps: 64 (8 x 8 array)
  4. Number of ASICs required: 4

This lighting fixture can be installed in large shopping centers, hospitals, offices etc., where it will provide constant light while maximizing the utilization of available solar energy. Even on a cloudy day it can reduce the load on the mains supply by 10 to 20%. Such a system will have an ROI of 3 to 4 years. Furthermore, it offers many other benefits such as decentralized design, very short wiring, lower transmission losses and provides light in the daytime if the mains power fails.  

Vijay Deshpande recently retired after a 30-year career focused on power electronics and DSP projects, and now works mainly on solar PV systems.

Related Content and references:

  1. Solar day lamp designs use passive and active current limiting circuits
  2. Solar day lamp designs provide low-cost lighting solutions, Part 1
  3. Solar day lamp designs provide low-cost lighting solutions, Part 2
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No floating nodes, Part 2

Wed, 04/03/2024 - 16:13

Some of the commentary in response to Part 1 on this topic suggested that the two 1 pF capacitors, C4 and C5, had to be put in series for lack of availability of 0.5 pF parts.

A simulation of that presented circuit is seen as follows:

Figure 1 The circuit with a floating node and its Bode plot simulation.

Part selections differ somewhat from the original. These op-amps are virtual, the JFET is merely an available part from the simulation software and the diode represents the original photodiode. For all of that, these are all close enough. Please note the Bode plot of this configuration.

To keep using the pair of 1 pF capacitors, the following schematic is the same as above but with the addition of one more resistor, R8, in parallel with C4.

Figure 2 The circuit without a floating node (an additional resistor R8 added in parallel with C4) and its Bode plot simulation.

At 10 MΩ, resistor R8 provides a DC path for the formerly floating node to keep that node’s voltage from unpredictably shifting. Note that the Bode plot for this modified circuit is indistinguishable from the plot seen before.

Other options for tethering the formerly floating node exist as well. For example, R8 could be tied from the C4 and C5 junction to ground, again, with no visible effect on the Bode plot.

The best choice is best left to the designer.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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A groovy apparatus for calibrating miniature high sensitivity anemometers

Tue, 04/02/2024 - 16:54

Anemometers are an important category of environmental sensor. Articles about their design, data capture, and linearization have comprised topics featured in EDN Design Ideas, several quite recently.

Less well covered, however, has been the topic of accurate, inexpensive, (even improvisational) methods for their testing and calibration.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The calibration method shown here is suited for sensitive, low air speed, miniature, solid-state thermal airflow sensors with full-scale ranges up to 250 fpm (2.8 mph), two of which are illustrated in Figure 1 and Figure 2. This type is particularly useful in applications like HVAC setup and forced-convection cooling airflow distribution measurement and monitoring.

Figure 1 GO/NOGO thermal low speed airflow sensor, ON/OFF airspeed threshold is set by R4.

Figure 2 Linearized battery powered low speed thermal anemometer.

 The airspeed measured by any anemometer is relative to the instrument. Whether it’s the air or the anemometer (or both) that’s actually moving is irrelevant. This simple calibrator consists of a repurposed phonograph turntable capable of accurate operation at the traditional rotational speeds of 33.3, 45, 78 rpm, and of course, zero. See Figure 3.

Figure 3 “Groovy” anemometer calibrator built from salvaged phonograph.

 Conveniently, the diameter of a standard phonograph record is one foot. So, an airspeed sensor mounted on the periphery of an ordinary discarded vinyl record will be moved through the air at:

Air speed (feet per minute) = π * RPM
33.3 rpm = 105 fpm
45 rpm = 141 fpm
78 rpm = 245 fpm

 Connections between the rotating anemometer sensor, external (stationary) power supply, and instrumentation are easily provided by a simple slipring commutator improvised from standard 3.5-mm 4-circuit audio jack and plug. The former is supported by an inverted plastic funnel glued to the record while the latter is affixed to the tone arm. Some light lubrication on the plug may be beneficial in minimizing potentially problematic drag on the turntable motor.

A suitable counterweight positioned diametrically opposite to the sensor under test can help balance the turntable against static (weight) and dynamic (centripetal) forces acting on the rotating circuitry.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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The LED-based BR40: A bulb begging for placement that’s drafty

Mon, 04/01/2024 - 17:24

When I did my first teardown of a LED-based light bulb nearly eight years ago, I figured it’d be a one-and-done. In coming to that premature conclusion, however, I didn’t consider the added functionality (such as network connectivity) enabled by the reduced power draw of the LED illumination subsystem versus that of the incandescent precursor. And I also didn’t take into account the diversity of functions (dimmable, three-way, etc.) and legacy form factors that LED upstarts would need to support. Here’s the to-date teardown list, which doesn’t even count LED illumination sources that aren’t bulb-shaped, like touch-activated and motion-sensing panels:

Today’s teardown “victim” falls into the “legacy form factor” category. About three years ago, I decided to swap out around a dozen and a half (so far) of the nearly three dozen total mix of BR30 and BR40 incandescent bulbs that were already installed and in use in ceiling “cans” throughout the house when we bought it. The bulbs I’ve to date converted to all-BR40 LED successors had two common characteristics:

  • They were easy to reach using only a conventional ladder (which, you’ll soon see, has been handy for not only initial but also ongoing access purposes), and
  • They were in locales, such as the kitchen and my office, that saw frequent use, therefore particularly benefitting from LED conversion from a power consumption standpoint.

Speaking of which, here’s one of the “daylight” (5000K color temperature) replacements installed in my office, both off:

and dimly illuminated:

While I can’t definitively say that I’ve noticed a tangible drop in our residence utility bill post-swap, I certainly now feel better about turning (and keeping) the lights on than I did before. That said, the transition hasn’t been perfect. To my earlier “dimly illuminated” comment, all the multi-bulb circuits I’ve converted so far are “fed” by dimmer switches, thereby necessitating dimmer-compatible LED lights. Specifically, I’d bought a couple of these Sunco bulb 10-packs:

to leave me with some spares inventory, which I’d hoped I wouldn’t need to tap into for a while. Check out this conceptual cutaway of what mine supposedly look like inside:

Granted, mine are 17W/100W equivalents, not the 7W/50W equivalent one shown here. Regardless…hold that thought 😉

Are they “zero flickering”? Not exactly. The bulk of the time I try to use them? Yes, actually. But…well, let me start by requoting a portion of my December 2023 teardown (this time with grammatical corrections made by yours truly to the original source):

Most dimmers installed today are designed to be used with high-power circuits to drive traditional filament lamps which were all quite uniform and dimmable by just a voltage change. LED lamps, on the other hand, are low-power and more complex. An LED bulb is a solid-state product that has built in circuitry (called a driver) that takes high-voltage AC input current and converts it to low-voltage DC current to drive the LEDs. Furthermore, driver specifications are not uniform across the LED industry.

There are many different types of dimmers installed in homes and offices, of various specifications (e.g., resistive; leading-edge and trailing-edge and electronic). So, when using new LED lamps with existing dimmers, matching old technology with new can be challenging.

 The drivers in dimmable LED lamps may work with many types of dimmers but not all. For instance, LED lamps tend to work better with trailing-edge dimmers rather than leading-edge dimmers. An existing dimmer may also have a minimum load that is too high for an LED lamp. For example, a 60 W filament lamp may use a dimmer that has a minimum load of 25 W, but the replacement LED has a power rating of 6.5 W – below the level required by the dimmer. Dedicated LED dimmers conversely have a very low minimum power rating.

The dimming experience can also be different with LED. Overall, the LED dimming performance is regulated by the capability of the LED driver/chip and the compatibility of the dimming circuit. Since there are a huge number of possible combinations of lamps and dimmers, it is very difficult to produce an LED lamp that works in all dimming environments.

LEDs currently have a lower dimming range than a filament lamp – LEDs currently dim down to about 10% of the total light output whereas filaments may go down to 1-2%. Low-voltage transformers as used with MR16 12V spotlights also add to the complexity.

Some of the issues that may occur when a dimmer is incompatible with an LED lamp are:

  • Flickering – Lamps will flicker (can also occur if a non-dimmable lamp is used).
  • Drop-out – No light output at the end of the scale.
  • Dead travel – When the dimmer is adjusted, there is no matching change in light output (light may not dim to acceptable level).
  • Not smooth – The light output may not go from dim to bright [editor note: and/or vice versa] linearly.
  • Multiple lamps – issues may become apparent when multiple lamps are added.
  • Damage or failure – LED driver, circuit or LED is damaged or fails.
  • Load below minimum – The power load of the LED lamp is below the minimum required by the dimmer.
  • Mixed models – Different models of LED will likely have different drivers, since drivers behave differently this could result in dimming issues.

I’ve personally experienced variants of several of these imperfections so far:

  • One/multiple/all the bulbs in a given circuit will turn on only dimly, and flicker-filled, even at a supposed “full power” dimmer switch position.
  • One-to-multiple of the bulbs won’t turn on at all, even with the others fully illuminated.
  • Dimming the circuit causes one-to-multiple of the bulbs to either turn completely off or to stubbornly remain fully illuminated.
  • etc.

The “fix” in all these cases? Turn them all off and back on again.


And regarding my earlier “spares inventory, which I’d hoped I wouldn’t need to tap into for a while” comment…again, reality hasn’t matched the hype. I’m reminded of the comment left by reader “vandamme0” to that previous December 2023 teardown:

Today I learned…that you can make outrageous lifetime claims based on single diode reliability at optimum temperature, and nobody calls you out on it because nobody keeps receipts for 18 years, 50,000 hours, or whatever you claim.

So far over the past three years, I “think” I’ve had three BR40 LED bulbs fail (which, if you’ve already done the math, you realize compelled me to buy more spares). Keeping in mind that “electronics things that break make great teardown candidates”, I held onto them, one of which is showcased here. That failure rate may not seem bad in the grand scheme of things, until you realize that:

  • They represent ~20% of the population of LED bulbs that I initially installed, and
  • None of the remaining BR30 and BR40 incandescent bulbs, all of which again were already installed and in operation when we arrived here a decade ago, have failed.

When I say “failed”, I should clarify. They “sorta” failed. After I’d turn on a bank of lights for a while, one of the bulbs would spontaneously turn off completely. Turning the bank of lights off and back on again wouldn’t immediately resuscitate it. But if I waited a while, the bulb would come back on…again, only for a while. I noticed that if I unscrewed it and removed it from the “can” it’d resurrect more quickly. Regardless, as time went on, the offender would fail more rapidly and take longer to revive; eventually, I’d just give up, grab the ladder, and swap it out.

The most likely potential failure mechanism, I suspect (and you may have already discerned), is heat. Incandescent bulbs get quite warm in ventilation-deficient “cans”, mind you, but the only thing they’re “cooking” is their filaments. With LED bulbs, on the other hand, there’s not only the LEDs themselves to consider but also all the circuitry in the base. And in a ceiling “can” there’s one other factor to consider; the bulb is pointing downward, which means that (as with similarly oriented CFL bulbs I’ve used and disassembled in the past) the heat rising off the LED array ends up baking the circuitry in the base above it. Lest you wonder, by the way, if I’m using my bulbs in an inadvisable configuration, this “stock” Sunco photo should set your mind at ease:

Enough setup; let’s dive into the dissection. I’ll as-usual start with some overview shots, accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

Some closeups of the markings around the side:

And finally, the tip of the base, both coin-accompanied and standalone:

Last time, the globe (I belatedly realized, to my dismay) was:

  • Glass
  • Sealed, and
  • Gas-filled

This time, conversely, it was plastic and definitely not sealed:

Providing a convenient pathway to the interior:

Mission accomplished:

Rim variance around the circumference:

And now what you’re all really here to see:

Removing those two screws in the earlier photos didn’t get me very far:

so, I redirected my attention to the base:

That’s more like it:

Here’s another closeup of the front of the PCB “plate”, this time unencumbered by its prior surroundings, revealing the ring of “daylight” colored LEDs, a smattering of other circuitry (the IC at left marked BP5178F is the LED constant current driver, while the one at bottom right labeled TB120S is the bridge rectifier, both from unknown manufacturers), and the pass-through connection for the two wires on the other side:

But what’s that other two-lead pass-through connector for? Let’s flip the plate over:

It’s…umm…an electrolytic capacitor:

At this point, with no lack of intentional snark, I’ll reinsert the conceptual cutaway from earlier:

Giggle snort 😉

We’re almost done; let’s get that metal “dish” (acting primarily as a heatsink, methinks…note the thermal paste residue) under the “plate” off to see if there’s anything underneath of note:

And the answer is…nope. That’s all, folks!

As always, your thoughts are welcome in the comments!

Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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Are ghiplets the next evolution stage in GPU designs?

Mon, 04/01/2024 - 13:24

When GPUs are implemented in a chiplet arrangement, can they be called ghiplets? Semiconductor industry professional Chetan Arvind Patil thinks so. In his blog “The Rise of Semiconductor Ghiplet,” Patil outlines the benefits of GPUs in chiplet architectures compared to monolithic GPU designs currently struggling with lower yield rates for large and complex GPU devices.

In other words, all the rendering is handled by chiplets instead of a big-compute GPU. Take the case of AMD’s Radeon RX 7000 series, one of the first chiplet-based GPUs, which incorporates a large graphics die and several memory dies. The Silicon Valley-based semiconductor firm is now considering using even more chiplets in a GPU design.

Figure 1 The Navi 31 GPU, part of the Radeon RX 7000 series, is based on the RDNA 3.0 chiplet architecture and is built on TSMC’s 5-nm manufacturing process. Source: AMD

The “ghiplet” approach has an inherent benefit for high-compute applications like artificial intelligence (AI): memory dies can be spread around the main GPU die. Thus, the ghiplets can help create a compute-memory balance. The modularity of chiplets helps optimize specific functions like memory handling.

Besides memory, chiplets offer faster and more efficient data handling with advanced interconnect implementation. This is specifically relevant for high-performance computing (HPC) applications in AI, data analytics, and scientific research.

GPUs have been slow to migrate to chiplets; GPU powerhouse Nvidia says that its recently launched graphics device Blackwell is not a chiplet. Despite much speculation, Nvidia has stuck to its monolithic guns for now. That’s partly because GPUs are far more complex than CPUs.

However, as GPUs move beyond graphics and gaming, chiplets could bring a lot of flexibility and scale to GPU designs. So, AMD archrival Intel has entered the ghiplet space with its Max Series GPUs. It has over 100 billion transistors packaged in 47 different chiplets—Intel calls it tiles—with up to 128 GB of memory.

Figure 2 The Max Series GPU, codenamed Ponte Vecchio, incorporates EMIB 2.5D and Foveros 3D packaging technologies and stacks chiplets or tiles on top of one another for greater processor density. Source: Intel

The suitability of the modularity in chiplet architectures for GPU designs seems a no-brainer. AMD and Intel have already jumped the fray, and Nvidia’s move is much awaited. Especially when AI applications and their need for memory capacity paired with GPUs increasingly calls for a compute-memory balance.

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Are FinFETs coming to an end?

Fri, 03/29/2024 - 06:54

FinFETs redefined chip design when they came onto the scene more than a decade ago. While these nonplanar transistors are still the unofficial industry standard, they may be nearing the end of their life. So, electronics engineers may need to prepare for an incoming shift.

The first chips using FinFETs came out in 2011, letting semiconductors safely venture into sub-25-nm territory. At that time, this architecture was a sort of saving grace for Moore’s Law, because planar transistors led to too much current leakage for geometries below 100 nm to be sustainable.

Figure 1 FinFETs replaced the planar transistor design with a 3D architecture to overcome the limitations of traditional planar transistors. Source: AnySilicon

However, FinFETs are now facing a problem like the planar technologies that came before them. Power leakage and signal interference issues are becoming more common obstacles as device form factors continue to shrink and performance demands rise. Consequently, many key industry players are starting to consider alternate transistor architectures.

As helpful as FinFETs are compared to their predecessors, they have severe power routing constraints at smaller geometries. Engineers typically work around these restrictions through different channel widths and spacing. That works well in many applications, but this strategy has limits of its own.

Because gates must reach the insulator between fins, sufficient space between each channel must be available. As a result, engineers can quickly run into scalability issues since there are 15 nm to 20 nm between each fin. Adding more channels inherently means adding inactive areas, leading to a tradeoff between current routing and physical space.

Gate-all-around (GAA) transistors

A potential solution has emerged in the form of gate-all-around (GAA) transistors. GAA architecture reverts to planar form factors, but instead of using a flat channel flush with the insulator, it uses silicon ribbons surrounded by the gate on all sides.

Just as FinFETs let engineers place multiple fins next to each other, GAAs enable vertical channel stacking. Notably, this method still requires space between each ribbon. However, because it capitalizes on verticality, each one can cover a longer horizontal space. Alternatively, engineers could design taller but narrower transistors to leave more room on the chip for other components.

Another key advantage of GAA design is that the gate contacts the channel on all four sides. Consequently, it provides more control over higher currents, just as FinFETs did in relation to conventional planar architectures.

Figure 2 In GAA transistor structure, the gate can come into contact with the channel on all sides, which makes continuous scaling possible. Source: Lam Research

GAAs are still relatively new, but they’re already showing signs of becoming standard. Samsung led the charge, announcing a switch to GAAFETs in 2022. Intel, which put FinFETs on the map, will release its GAA technology later in 2024, along with a backside power technology.

Several obstacles remain. Some reports hold that Samsung is struggling to achieve high yields with its GAAFET technology. Other foundries have more long-term release windows for their GAA chips, so whether GAA technology will be able to overcome these challenges remains unclear.

Despite these road bumps, the industry is clearly moving toward GAAs. So, electronics designers should familiarize themselves with this technology before the shift happens to adapt to the changing market.

Transition on the gate

Just as FinFETs redefined semiconductor architecture in the 2010s, GAAFETs could do the same within the next decade. While much of this transition is still up in the air, most signs seem to be pointing that way.

Electronics engineering is a continually evolving field. Therefore, engineers must stay abreast of developments like this to ensure they can capitalize on the innovations that revolutionize the industry.

Ellie Gabel is a freelance writer as well as an associate editor at Revolutionized.

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Renesas builds RISC-V MCUs with own core

Thu, 03/28/2024 - 20:11

General-purpose 32-bit MCUs in the R9A02G021 group from Renesas employ an internally developed RISC-V CPU core. Renesas has designed and tested the new RISC-V core independently and implemented it in a commercial product that is available worldwide.

R9A02G021 MCUs enable embedded systems designers to develop low-power, cost-sensitive applications based on the RISC-V open-source instruction set architecture (ISA). The devices target such end markets as IoT sensors, consumer electronics, medical devices, small appliances, and industrial systems. They are also supported by a full-scale development environment and a network of toolchain partners.

The CPU core runs at 48 MHz and achieves a performance rating of 3.27 CoreMark/MHz. Power consumption is 162 µA/MHz when active, dropping to just 0.3 µA in standby with a wakeup time of 4 µs. Other features of the R9A02G021 group include:

  • Memory: 128 KB code flash, 16 KB SRAM, and 4 KB data flash
  • Serial communications interfaces: UART, SPI, I2C, SAU
  • Analog peripherals: 12-bit ADC and 8-bit DAC
  • Temperature range: -40°C to 125°C
  • Operating voltage range: 1.6 V to 5.5V

Packaging options for the R9A02G021 MCUs include 16-pin WLCSP and 24-pin, 32-pin, and 48-pin QFN. Devices are available now through global distributors.

R9A02G021 product page

Renesas Electronics 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Motor control MCUs pack ample flash memory

Thu, 03/28/2024 - 20:10

Toshiba has added eight devices to the M4K group of TXZ+ 32-bit MCUs offering extended flash memory and four different packaging options. Outfitted with 512 kbytes or 1 Mbyte of code flash memory, the MCUs address the need for large program capacity in IoT motor control applications. They also offer firmware over-the-air updating.

With 1 Mbyte of code flash divided into two separate 512-kbyte areas, the MCUs enable firmware rotation using memory swapping. While instructions are being read from one area, updated code can be programmed into the other area simultaneously.

In addition to the expanded flash memory, the devices also boost RAM capacity to 64 kbytes. They are powered by an Arm Cortex-M4 core running at up to 160 MHz and provide UART, tSPI, and I2C interfaces. Three 12-bit ADCs, three advanced motor control circuits, and a vector engine allow the MCUs to control three motors, even in 64-pin packages.

M4K microcontrollers can be used to control AC motors, brushless DC motors, and inverters in home appliances, power tools, and industrial equipment. Packaging options include QFP100, LQFP100, and two different size LQFP64 types.

TXZ+ M4K group product page

Toshiba Electronic Devices & Storage 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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100-V Schottky rectifiers aid efficiency

Thu, 03/28/2024 - 20:10

Twenty-eight 100-V trench Schottky rectifiers from ST increase efficiency and power density in power converters operating at high switching frequencies. Target applications for the portfolio of devices include power supplies for telecom, server, and smart metering equipment, as well as automotive LED lighting and low-voltage DC/DC converters.

According to the manufacturer, the diodes reduce rectifier losses with forward-voltage and reverse-recovery characteristics that enable increased power density with high efficiency. Forward voltage is 50 mV to 100 mV better than comparable planar diodes, depending on current and temperature conditions. Changing to these new devices can increase efficiency by 0.5%.

Variants in the family cover eight current ratings ranging from 1 A to 15 A. Multiple surface-mount package types are available in both industrial and automotive grades. Automotive parts are AEC-Q101 qualified for operation over a temperature range of -40°C to +175°C and manufactured in PPAP-capable facilities. Diodes are 100% avalanche tested in production to ensure device robustness and system reliability.

All of the parts are available now in DPAK, SOD123 flat, SOD128 flat, SMB flat, and PSMC (TO-227A) packages. Volume prices start at $0.107 for the 1-A STPST1H100ZF in the SMD123 flat package.

To access the datasheets for the 28 trench Schottky rectifiers, click here.


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Buck-boost MOSFET meets USB PD 3.1 demands

Thu, 03/28/2024 - 20:09

Occupying a small footprint to ease PCB design, the AONZ66412 MOSFET from Alpha & Omega targets buck-boost converters in USB PD 3.1 EPR applications. While the 3.1 Extended Power Range specification enables power delivery up to 240 W over a USB Type-C cable and connector, the AONZ66412 addresses the most commonly used power range of up to 140 W at 28 V.

The AONZ66412 combines two 40-V N-channel MOSFETs arranged in a half-bridge configuration within a symmetric XSPairFET 5×6-mm package. When used to replace two single 5×6-mm DFN packages, the compact AONZ66412 reduces PCB area, improves efficiency, and simplifies the layout of a 4-switch buck-boost architecture.

Alpha & Omega’s XSPairFET DFN is a bottom-side source package. Each high-side and low-side MOSFET provides a maximum on-resistance of 3.8 mΩ. The source of the low-side MOSFET is directly linked to a large paddle on the lead frame. This setup enhances thermal performance by enabling direct connection of the paddle to the PCB’s ground plane. When tested, the AONZ66412 demonstrated 97% efficiency at 1 MHz under typical USB PD 3.1 EPR conditions with a 28-V input, 17.6-V output, and 8-A load.

The AONZ66412 dual MOSFET costs $1.56 each in lots of 1000 units. It is available now in production quantities with a lead time of 16 weeks.

AONZ66412 product page

Alpha & Omega Semiconductor 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Aspinity strengthens AI-based automotive security

Thu, 03/28/2024 - 20:08

Aspinity has launched a dashcam evaluation kit and a suite of smart analogML algorithms for parked vehicle monitoring. The hardware/software offerings leverage the company’s always-on AML100 analog machine learning processor. The near-zero power AML100 enables continuous monitoring for extended periods without impacting the vehicle’s battery or requiring an external power source.

The company recently demonstrated a dashcam with a single microphone and an AML100 processor. The setup uses an acoustic-only trigger and analogML algorithms trained to identify automotive security events. According to Aspinity, the solution detects events more accurately than dashcams outfitted with a standard G-sensor. Surveillance algorithms detect such events as jiggling of the door handle, a neighboring car door opening into the vehicle, runaway shopping cart hitting the side of the car, and window glass breaking, while ignoring sounds from events unrelated to the vehicle.

Based on the AML100-REF-1 wireless, battery-operated reference module, the dashcam evaluation kit enables deployment and evaluation in the cabin of a vehicle. It consumes <50 µA in always-on mode and eliminates the video recording of false events that waste power.

To learn more about Aspinity’s AML100 monitoring solutions for automotive security, click here.


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Single phase mains cycle skipping controller sans harmonics

Thu, 03/28/2024 - 16:43

In electrical heating applications, resistive heaters are powered through phase angle-controlled SCR/triac circuits to vary the applied voltage/power to maintain the required temperature.

Phase angle control produces a lot of harmonics leading to power line disturbances.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1’s circuit gives a simple and cost-effective solution without introducing harmonics. This controller skips a certain number of power cycles in between, to vary power to the heaters.

Figure 1 Circuit schematic of mains cycle skipping controller, this controller skips a certain number of power cycles in between, to vary power to the heaters.

In this typical design, 10 full cycles are taken as base. Timer U3 (555) through R2, R4, and C1 decides this by giving output pulses with an interval of  200 ms, which is the width of 10 full AC cycles of a 50 Hz AC mains (for a 60 Hz mains, this will be 166.6 ms). These pulses trigger U4 (555) monostable to produce pulses with an adjustable width within 200 ms, by adjusting potentiometer RV1. This pulse train controls an optotriac with zero cross detector U2 (MOC3033) to trigger triac U1 (BTA25-600BW). The triac conducts for the duration of “off pulse widths” produced by U4. Thus, these conduction periods allow the selected number of voltage cycles to pass through and impress on load. During “on pulse widths”, the triac does not conduct and skips the voltage cycles. Simulated waveforms can be seen in Figure 2 with two full cycles being skipped and Figure 3 with five full cycles being skipped.

Figure 2
Simulated waveforms with the U3 timer output (yellow), U4 timer output (blue), and heater voltage (pink). Eight full cycles are impressed on load, skipping two full cycles as decided by the RV1 potentiometer position.

Figure 3 Simulated waveforms with the U3 timer output (yellow), U4 timer output (blue), and heater voltage (pink). Five full cycles are impressed on load, skipping five full cycles as decided by another RV1 potentiometer position.

As an example, if a 40 ms width is chosen by RV1, which corresponds to 2 full cycles of a 50 Hz mains, the triac will not conduct for 2 voltage cycles and will conduct for 8 full cycles and pass to the load. Thus, two cycles are skipped. This operation repeats. Thus, load power is controlled by skipping a selected number of voltage cycles. As AC cycles passed to load are full cycles, unwanted harmonics are eliminated.

Normally such controllers are realized with an MCU and software, the novelty of this circuit realizing the  same function without using the MCU, thus making it simple with low cost components.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

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Parsing PWM (DAC) performance: Part 4 – Groups of inhomogeneous duty cycles

Wed, 03/27/2024 - 16:29

Editor’s Note: This is a four-part series of DIs proposing improvements in the performance of a “traditional” PWM—one whose output is a duty cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to produce a DAC. The first part suggests mitigations and eliminations of common PWM error types. The second discloses circuits driven from various Vsupply voltages to power rail-rail op amps and enable their output swings to include ground and Vsupply. The third pursues the optimization of post-PWM analog filters. This fourth part pursues the optimization of post-PWM analog filters.

 Part 1 can be found here.

 Part 2 can be found here.

 Part 3 can be found here.

Recently, there has been a spate of design ideas (DIs) published (see Related Content) which deals with microprocessor-generated pulse width modulators driving low-pass filters to produce DACs. Approaches have been introduced which address ripple attenuation, settling time minimization, and limitations in accuracy. This is the fourth in a series of DIs proposing improvements in overall PWM-based DAC performance. Each of the series’ recommendations is implementable independently of the others. This DI addresses PWM sequence modifications which ease low pass analog filtering requirements.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The tyranny of resolution vs response time

The combination of PWM clock frequency Fclk Hz and the number of bits b of PWM resolution dictates the lowest frequency (Fclk·2-b Hz) output component of a standard PWM. Over all the possible duty cycles, this component is also the largest and therefore the most challenging for an analog filter to suppress. For a given Fclk, the more bits of resolution, the longer the settling time will be of a filter which provides adequate suppression. But there is a way around this limitation.

Suppose a standard 8-bit PWM whose output is either 0 or 1 is configured for a duty cycle of (arbitrarily) 121/256. The first 121 states in a 256-state cycle would be 1 and the remaining 135 would be 0’s. But what if the first 128 states started with 60 ones and the last 128 states started with 61 ones? Let’s call this the “split-in-two” PWM. These two sequences have been offset in amplitude slightly so that they can be clearly seen on a graph shown in Figure 1.

Figure 1 Output sequences of standard and split-in-two 8-bit PWMs with the same clock frequency, period, and duty cycle (121/256).

The blue waveform represents the standard PWM and the orange one is the split-in-two PWM. Why might the latter be advantageous? Consider the spectra of the two PWMs seen in Figure 2.

Figure 2 Frequency content of standard and split-in-two 8-bit PWMs with the same clock frequency, period, and duty cycle (121/256).    

The energy in the first harmonic of the split-in-two PWM is negligible in comparison with that of the standard PWM. The necessary attenuation for the first harmonic has been significantly lessened, and that which was required is now applied to the harmonic at double the frequency. A less aggressive attenuation-with-frequency analog filter can now be employed, resulting in a shorter settling time in response to a change in duty cycle.

Another way to look at this is to double the split-in-two PWM period to 512 states to produce a 9-bit PWM. As shown in Figure 3, the spectra of the two PWMs are almost identical because the time domain waveforms are almost identical—they differ only in that every other 256-bit sequence, one additional one-state replaces a zero-state. The higher resolution 9-bit PWM produces a small amount of energy (less than 1%) at half the frequency of the 8-bit’s fundamental. Any analog low pass filter with adequate suppression of the 8-bit fundamental frequency will more than sufficiently attenuate the signal at half that frequency.

Figure 3 Frequency content of a standard 8-bit PWM of duty cycle 121/256 and a split-in-two 9-bit PWM of duty cycle (121.5/256). They share the same clock, but the split-in-two’s period is twice the standard PWM’s.

The super-cycle

We can think of the split-in-two as generating a “super-cycle” consisting of two cycles of 2b states, each having at least S one-states, with 0 ≤ S < 2b. In one cycle, one zero-state could be swapped for a one-state if the total number of ones in the super-cycle is odd. This is a (b+1)-bit PWM with a period of 2b+1 states. But there is no reason to stop at two. There can be a super-cycle of 2n cycles where n is any integer. With each cycle capable of optionally swapping one zero-state for a one-state, this leads to a PWM super-cycle with a resolution of 2b+n bits. But unlike standard, non-super-cycle PWMs whose maximum spectral energy component is at fclk/2b+n Hz, the super-cycle’s is at a much higher fclk/2b Hz. As with the specific case of the split-in-two, this eases analog filtering requirements and results in a shorter settling time.

It’s worth thinking of a super-cycle as consisting of the sum of two different sequences. One is the S-sequence in which every cycle consists of an identical sequence of S contiguous one-states. The other is the X-sequence where each cycle optionally swaps the first zero-state following the last one-state with another one-state. The X-sequence has X one-states where 0 ≤ X < 2n. The duty cycle of the super-cycle is then (2n·S + X)/2b+n.

When n = 1 for a super-cycle, there is only one cycle where an extra one-state can reside. But when n > 1, X is also greater than one and the question becomes how to distribute the X ones among the 2n cycles so as to minimize the super-cycle’s energy at low frequencies. The fine folks at Microchip who manufacture the SAM D21 microcontroller not only have figured this out for us, but they have also implemented it in hardware [1]! For this IC, it is necessary only to write the values of X and S to separate registers to implement a super-cycle PWM; the hardware does the rest unsupervised. Fortunately, it is simple for almost any microprocessor to augment a standard PWM to implement a super-cycle. For each PWM cycle, the duty cycle count must be modified so that immediately after the sequence of S ones, the first zero gets changed to a one if and only if the following C expression is true for that cycle:

MASK & (cycleNbr * X) > MASK – X

Here, MASK = 2n– 1, X is as before, and cycleNbr is the numeric position of the cycle in the super-cycle. Figure 4 is a graph of the magnitudes of the lowest 32 harmonics of an n = 4, b = 8 super-cycle PWM. The graph provides evidence of the benefit of this approach.

Figure 4 First 32 harmonics of an n=4, b=8 super-cycle PWM. Spectra are displayed for X=1 through 8. (Spectra of X=9 through 15 are the same as those shown.)

The X-sequence’s energy is relatively low, having only 0 through 2n-1 one-states, but it also presents the lowest frequency component, fclk/2n+b Hz. The S-sequence generally contains the most energy by far (except for instances of very small duty cycles), but its smallest frequency component is noticeably higher at Fclk/2b Hz. Among the X sequences, X = 1 gives the largest amplitude for its first harmonic: 2-11 at fclk/2n+b Hz. The S sequence’s spectrum starts at the X sequence’s harmonic number 24 = 16 and produces its largest amplitude of 2/π for that harmonic when S = 211. If this were a standard PWM (an n = 0 super-cycle—no super-cycle at all that is, just a normal PWM), then that amplitude of 2/π would appear at frequency which is 16 times lower. The standard PWM presents a much more severe filtering problem. Its filter would take a lot longer to settle in response to a duty cycle change because of the much larger amount of low frequency attenuation required.

Comparing the filters for (n+b)-bit standard and super-cycle PWMs

The filtered AC steady state time-domain contributions of both the standard and the super-cycle (with its X and S sequences) PWMs should be less than some fraction α of the voltage of the PWMs’ one-state. A reasonable value of α is 2-(n+b+1), ½ LSB. This translates to an attenuation factor of 1/4 at the first harmonic of the X sequence. It is fortunate that even a simple two-component R-C filter meeting this requirement will sufficiently attenuate all higher X sequence harmonics, so there are no additional constraints to meet to suppress them. The 16th X harmonic frequency is that of the first S harmonic. Its PWM energy requires an attenuation factor of (π/2)·2-(n+b+1) at a 50% duty cycle. Again, any low pass filter meeting this requirement will adequately attenuate the remaining S-sequence harmonics. For an Fclk = 20 MHz, Figure 5 and Figure 6are graphs of the frequency and time domain step responses of 3rd order filters (two op-amps, 3 resistors, and 3 capacitors) meeting these requirements for standard 12-bit and super-cycle n = 4, b = 8  (12-bit) PWMs.

Figure 5 The frequency responses of filters for standard and super-cycle n = 4 bit PWMs with 12 bits of resolution. The maxima of the peaked waveforms are the maximum responses allowed for the filters at the peaked frequencies. The filters ensure that the steady state time domain energy at their outputs is less than ½ LSB of Full Scale.

Figure 6 The log of the absolute value of time responses of filters for standard and super-cycle n = 4 bit PWMs with 12 bits of resolution. The much shorter settling time of the super-cycle PWM is clearly evident.

 Easing low pass analog filter requirements

When partnered with an appropriate analog filter, an approach to PWM embodiment available in hardware in an existing microprocessor [1] offers significantly shorter settling times than does a standard PWM. This approach can be implemented with the aid of a small amount of software in almost any microcontroller.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

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  1. https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-D21DA1-Family-Data-Sheet-DS40001882G.pdf(See section
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Power Integrations’ gallium nitride (GaN) story

Wed, 03/27/2024 - 12:04

Gallium nitride (GaN) power semiconductors continue to push the boundaries of high-voltage electronics, as evident at this year’s Applied Power Electronics Conference (APEC) in Long Beach, California. GaN devices are moving beyond fast chargers for cell phones, tablets, and game machines into the realm of automotive, renewable energy, and industrial applications.

At APEC 2024, during his plenary presentation titled “Innovating for Sustainability and Profitability,” Power Integrations CEO Balu Balakrishnan revealed that his company had been shipping GaN switches for two to three years in high volume before anybody knew it. “We never advertised our GaN technology because we saw it as a means to an end to deliver high efficiency and performance.”

Figure 1 Balakrishnan talked about his company’s GaN history and future roadmap at APEC 2024. Source: Power Integrations

That was quite a revelation because, according to Omdia, Power Integrations was the number one supplier of GaN power semiconductors in 2022, with nearly 17% market share. Moreover, in October 2023, Power Integrations unveiled a 1,250 V GaN IC; it claims power conversion efficiency as high as 93% while enabling highly compact flyback power supplies that can deliver up to 85 W without a heatsink.

Earlier, in March 2023, the Silicon Valley-based power semiconductor supplier released a 900-V GaN IC as part of its InnoSwitch3 family of flyback switcher ICs. It delivers up to 100 W with better than 93% efficiency and eliminates the need for heat sinks.

Figure 2 The 1,250-V GaN power supply IC is part of the company’s InnoSwitch flyback switcher ICs. Source: Power Integrations

Power Integrations claims to be the first to market with high-volume shipments of GaN-based power-supply ICs in 2019. A GaN switch, integrated with a controller and everything else in a single package, was first used in a notebook adapter design. “Two customers were very suspicious, saying there is no way you can have that level of efficiency with silicon,” Balakrishnan told the APEC audience. “So, we had to tell them under a non-disclosure agreement (NDA).”

“Efficiency is going to be the mantra in power electronics for a long time,” he added. Balakrishnan also said that GaN will eventually be less expensive than silicon for high-voltage switches. “There is no fundamental reason why it won’t be cost-effective in the long run.”

However, he clarified that GaN will replace silicon in certain areas. “Everybody thinks it will replace silicon, but GaN won’t replace silicon in controllers and digital circuitry,” he added. Balakrishnan and his engineers at Power Integrations also believe that GaN will get to the point where it’ll be very competitive with SiC while being less expensive to build.

As Balakrishnan noted, GaN has been talked about for a long time, but the challenge was operating reliably on high voltage. It’s ascent to voltages as high as 900 V, 1,250 V, and potentially even higher voltages shows that GaN is ready for commercial limelight.

Consequently, stakes for GaN semiconductor players, including Power Integrations, are getting higher as well.

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Who knew? Wearables can be excessive skin-heat sources, too.

Tue, 03/26/2024 - 15:39

You might think that a smart watch or fitness wearable would not be a thermal concern for users. After all, they only have small rechargeable batteries and sip that battery’s energy to extend operating time as much as possible, typically at least 24 hours.

Their heat dissipation is many orders of magnitude less than that of a CPU, GPU, or other processor-core device cooking along at tens and even hundreds of watts. Nonetheless, wearables can be highly localized sources of heat and therefore cause potential skin problems.

I hadn’t thought about the extent of this localized heating on skin due to wearables until I coincidentally saw several items on the subject. The first was an IEEE conference article re- posted at InCompliance magazine, “Reduced-Order Modeling of Pennes’ Bioheat Equation for Thermal Dose Analysis.” The second was an article in Electronics Cooling, “Thermal Management and Safety Regulation of Smart Watches.”

The first paper was intensely analytic with complicated thermal models and equations, and while I didn’t want to go through it in detail, I did get the overall message: you can get surprisingly high localized skin heating from a wearable.

It pointed out that the simple term “skin” actually comprises four distinct tissue layers, and each is unique in its geometric, thermal, and physiological properties. The outermost layer is the exposed epidermis, beneath it is the dermis which is the “core” of the skin, then the subcutaneous fat (hyodermis) layer, and finally, the inner tissue muscle and bone, Figure 1.

Figure 1 The term “skin” really refers to a four-layer structure, where each layer has distinctive material, thermal, and other properties, most of which are hard to measure. Source: Cleveland Clinic

Damage to the skin is analyzed by the extent of partial or complete necrosis (death) of each layer. While that’s more than I wanted to know, I was curious about the assessment of skin damage.

It turns out that there is, as expected, a quantitative assessment of thermally induced damage and it is based on cumulative exposure at various temperatures. This thermal dose is estimated as cumulative equivalent minutes at 43°C, or CEM43°C, which provides a time and duration number:

Where T is tissue temperature, t is time, and R is a piecewise-constant function of temperature with:

 R(T) = 0.25 for T ≤ 43°C and = 0.5 for T > 43°C.

So far, so good. The rest the of lengthy paper delved into models of heat flow, heat spreading through the skin, transforming surface data into three-dimensional data, and more. The analysis was complicated by the fact that heat flow through the layers is hard to measure and model, especially as the skin layers are anisotropic (the flow is different along different axes).

Cut to the chase: even a modest self-heating of the wearable can cause skin damage over time, and so must be modeled, measured, and assessed. How much heating is allowed? There are standards for that, of course, such as IEC Guide 117:2010, “Electrotechnical equipment – Temperatures of touchable hot surfaces.”

What to do?

Knowing there’s a problem is the first step to solving it. In the case of wearables, the obvious solution is to reduce dissipation even further, which would also increase run time as an added benefit. But efforts are underway to go beyond that obvious approach.

Coincident with seeing the two cited articles, I came across an article in the scholarly journal Science Advances, “Ultrathin, soft, radiative cooling interfaces for advanced thermal management in skin electronics.” A research team led by City University of Hong Kong has devised a photonic, material-based, ultrathin, soft, radiative-cooling interface (USRI) that greatly enhances heat dissipation in devices.

Their multifunctional composite polymer coating offers both radiative and non-radiative cooling capacity without using electricity and with advances in wearability and stretchability. The cooling interface coating is composed of hollow silicon dioxide (SiO2) microspheres for improving infrared radiation along with titanium dioxide (TiO2) nanoparticles and fluorescent pigments, for enhancing solar reflection. It is less than a millimeter thick, lightweight (about 1.27g/cm2), and has robust mechanical flexibility, Figure 2.

Figure 2 Overview of the USRI-enabled thermal management for wearable electronics. (A) Exploded view of the components and assembly method of the ultrathin, soft, radiative-cooling interface (USRI). (B) Photographs of a fabricated USRI layer (i) and that attached on the wrist and hand (ii). (C) Thermal exchange processes in wearable electronics seamlessly integrated with a USRI, including radiative (thermal radiation and solar reflectance) and nonradiative (convection and conduction) contributions, as well as the internal Joule heating. (D) Comparison of cooling power from the radiative and nonradiative processes in wearable devices as a function of the above-ambient temperature caused by Joule heating. (E) Conceptual graph capturing functional advantages and potential applications of USRI in wearable and stretchable electronics. Source: City University of Hong Kong

When heat is generated in a wearable fitted with this thermal interface, it flows to the cooling interface layer and dissipates to the ambient environment through both thermal radiation and air convection. The open space above the interface layer provides a cooler heat sink and an additional thermal exchange channel.

To assess its cooling capacity, they conformally coated the cooling interface layer onto a metallic resistance wire functioning as a heat source, Figure 3. With a coating thickness of 75 μm, the temperature of the wire dropped from 140.5°C to 101.3°C, compared with uncoated wire at an input current of 0.5 A with a 600-μm thickness, it dropped to 84.2°C for a temperature drop of more than 56°C. That’s fairly impressive, for sure.

Figure 3 Passive cooling for conductive interconnects in skin electronics. (A) Exploded view of a USRI-integrated flexible heating wire. (B) Photographs of the flexible heating wire before and after coating with the USRI, showing their seamless and robust integration under bending, twisting, and folding. (C) Thermal exchange processes of the USRI-coated flexible heating wire. (D and E) Measured temperature variation of the USRI-integrated flexible heating with varied interface thickness (D) and interface area (E) under different working currents. The colored shaded regions depict simulation results. (F) Image of the USRI-integrated flexible heating wire and corresponding infrared images of such devices with different thicknesses and areas. The working current was kept at 0.3 A. (G and H) Statistics of cooling temperatures of two USRI-coated flexible heating wires working at a current varying from 0.1 to 0.5 A. Both the thickness and the interface area present significant differences between the control and USRI groups (P = 0.012847 for interface thickness, P = 0.020245 for interface area, n = 3). (I) Temperature distribution of USRI-integrated flexible heating wires with varied thickness, area, and current. Source: City University of Hong Kong

Have you had to worry about excessive heat dissipation in a wearable, and the risks it might bring? Were you aware of the relevant regulatory standards for this phenomenon? How did you solve your problem?

Bill Schweber is an EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features.

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