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Due to their versatility, ease of design, and low cost, flyback converters have become one of the most widely used topologies in power electronics. Its structure derives from one of the three basic topologies—specifically, buck-boost topology. However, unlike buck-boost converters, flyback topologies allow the voltage output to be electrically isolated from the input power supply. This feature is vital for industrial and consumer applications.

Among the different control methods used to stabilize power converters, the most widely used control method is peak current mode, which continuously senses the primary current to provide important protection for the power supply.

Additionally, to obtain a higher design performance, it’s common to regulate the converter with the output that has the highest load using a technique called cross-regulation.

This article aims to show engineers how to correctly design the control loop that stabilizes the flyback converter in order to provide optimal functionality. This process includes minimizing the stationary error, increasing/decreasing the bandwidth as required, and increasing the phase/gain margin as much as possible.

Closed-loop flyback converter block diagram

Before making the necessary calculations for the controller to stabilize the peak current control mode flyback, it’s important to understand the components of the entire closed-loop system: the converter averaged model and the control loop (Figure 1).

              Figure 1 Here is how the components look in the entire closed-loop system. Source: Monolithic Power Systems

The design engineer’s main interest is to study the behavior of the converter under load changes. Considering a fixed input voltage (VIN), the open-loop transfer function can be modeled under small perturbations produced in the duty cycle to study the power supply’s dynamic response.

The summarized open-loop system can be modeled with Equation 1:              (1)

Where G is the current-sense gain transformed to voltage and GC(s) and GCI(s) are the transfer functions of the flyback converter in terms of output voltage and magnetizing current response (respectively) under small perturbations in the duty cycle. GαTS is the modeling of the ramp compensation to avoid the double-pole oscillation at half of the switching frequency.

Flyback converter control design

There are many decisions and tradeoffs involved in designing the flyback converter’s control loop. The following sections of the article will explain the design process step by step. Figure 2 shows the design flow.

Figure 2 The design flow highlights control loop creation step by step. Source: Monolithic Power Systems

Control loop design process and calculations

Step 1: Design inputs

Once the converter’s main parameters have been designed according to the relevant specifications, it’s time to define the parameters as inputs for the control loop design. These parameters include the input and output voltages (VIN and VOUT, respectively), operation mode, switching frequency (fSW), duty cycle, magnetizing inductance (LM), turns ratio (NP:NS), shunt resistor (RSHUNT), and output capacitance (COUT). Table 1 shows a summary of the design inputs for the circuit discussed in this article.

Table 1 Here is a summary of design inputs required for creating control loop. Source: Monolithic Power Systems

To design a flyback converter compensator, it’s necessary to first obtain all main components that make the converter. Here, HF500-40 flyback regulator is used to demonstrate design of a compensator using optocoupler feedback. This device is a fixed-frequency, current-mode regulator with built-in slope compensation. Because the converter works in continuous conduction mode (CCM) at low line input, a double-pole oscillation at half of the switching frequency is produced; built-in slope compensation dampens this oscillation, making its effect almost null.

Step 2: Calculate parameters of the open-loop transfer function

It’s vital to calculate the parameters of the open-loop transfer function and calculate the values for all of the compensator’s parameters that can optimize the converter at the dynamic behavior level.

The open-loop transfer function of the peak current control flyback converter (also including the compensation ramp factor) can be estimated with Equation 2:

      (2)

Where D’ is defined by the percentage of time that the secondary diode (or synchronous FET) is active during a switching cycle.

The basic canonical model can be defined with Equation 3:              (3)

Note that the equivalent series resistance (ESR) effect on the output capacitors has been included in the transfer function, as it’s the most significant parasitic effect.

By using Equation 2 and Equation 3, it’s possible to calculate the vital parameters.

The resonant frequency (fO) can be calculated with Equation 4:

              (4)

After inputting the relevant values, fO can be calculated with Equation 5:              (5)

The right-half-plane zero (fRHP) can be estimated with Equation 6:              (6)

The q-factor (Q) can be calculated with Equation 7:              (7)

After inputting the relevant values, Q can be estimated with Equation 8:              (8)

The DC gain (K) can be calculated with Equation 9:              (9)

After inputting the relevant values, K can be estimated with Equation 10:              (10)

The high-frequency zero (fHF) can be calculated with Equation 11:

              (11)

It’s important to note that with current mode control, it’s common to obtain values well below 0.5 for Q. With this in mind, the result of the second-degree polynomial in the denominator of the transfer function ends up giving two real and negative poles. This is different from voltage-control mode or when there is a very large compensation ramp, which results in two complex conjugate poles.

The two real and negative poles can be estimated with Equation 12:              (12)

The new open-loop transfer function can be calculated with Equation 13:              (13)

The cutoff frequency (fC) can be estimated with Equation 14:              (14)

The following sections will explain how the frequency compensator design achieves power supply stability and excellent performance.

Step 3: Frequency compensator design

Once the open-loop transfer function is modeled, it’s necessary to design the frequency compensator such that it achieves the best performance possible. Because the frequency response of the above transfer function has two separate poles—one at a low frequency and one at a high frequency—a simple Type II compensator can be designed. This compensator does not need an additional zero, which is not the case in voltage-control mode because there is a double pole that produces a resonance.

To minimize the steady-state error, it’s necessary to design an inverted-zero (or a pole at the origin) because it produces higher gains at low frequencies. To ensure that the system’s stability is not impacted, the frequency must be at least 10 times lower than the first pole, calculated with Equation 15:

           (15)

Due to the ESR parasitic effect at high frequencies, it’s necessary to design a high-frequency pole to compensate for and remove this effect. The pole can be estimated with Equation 16:

(16)

On the other hand, it’s common to modify the cutoff frequency to achieve a higher or lower bandwidth and produce faster or slower dynamic responses, respectively. Once the cutoff frequency is selected (in this case, fC is increased up to 6.5 kHz, or 10% of fSW), the compensator’s middle-frequency gain can be calculated with Equation 17:           (17)

Once the compensator has been designed within the frequency range, calculate the values of the passive components.

Step 4: Design the compensator’s passive components

The most common Type II compensator used for stabilization in current control mode flyback converters with cross-regulation is made up of an optocoupler feedback (Figure 3).

Figure 3 Type-II compensator is made up with optocoupler feedback. Source: Monolithic Power Systems

The compensator transfer function based on optocoupler feedback can be estimated with Equation 18:          (18)

The middle-frequency gain is formed in two stages: the optocoupler gain and the adjustable voltage reference compensator gain, calculated with Equation 19:

(19)

It’s important to calculate the maximum resistance to correctly bias the optocoupler. This resistance can be estimated with Equation 20:     (20)

The parameters necessary to calculate RD can be found in the optocoupler and the adjustable voltage reference datasheets. Table 2 shows the typical values for these parameters from the optocoupler.

Table 2 Here are the main optocoupler parameters. Source: Monolithic Power Systems

Table 3 shows the typical values for these parameters from the adjustable voltage reference.

Table 3 The above data shows adjustable voltage reference parameters. Source: Monolithic Power Systems

Once the above parameters have been obtained, RD can be calculated with Equation 21:              (21)

Once the value of R3 is obtained (in this case, R3 is internal to the HF500-40 controller, with a minimum value of 12 kΩ), as well as the values for R1, R2, and RD (where RD = 2 kΩ), RF can be estimated with Equation 22:   (22)

Where GCOMP is the compensator’s middle frequency gain, calculated with Equation (17). GCOMP is used to adjust the power supply’s bandwidth.

Because the inverted zero and high-frequency pole were already calculated, CF and CFB can be calculated with Equation 23 and Equation 24, respectively.         (23)           (24)

Once the open-loop system and compensator have been designed, the loop gain transfer function can be estimated with Equation 25:           (25)

Equation 25 is based on Equation 13 and Equation 18.

It’s important to calculate the phase and gain margins to ensure the stability of power supply.

The phase margin can be calculated with Equation 26:          (26)

After inputting the relevant values, the phase margin can be calculated with Equation 27:          (27)

If the phase margin exceeds 50°, it’s an important parameter necessary to comply with certain standards.

At the same time, the gain margin can be approximated with Equation 28:            (28)

Equation 29 is derived from Equation 25 at the specified frequency:     (29)

In this scenario, the gain margin is below -10dB, which is another important parameter to consider, particularly regarding compliance with regulation specifications. If the result is close to 0dB, some iteration is necessary to decrease the value; otherwise, the performance is suboptimal. This iteration must start by decreasing the value of the cutoff frequency.

This complete transfer function provides stability to the power supply and the best performance made possible by:

• Minimizing steady-state error
• Minimizing ESR parasitic effect
• Increasing bandwidth of power supply up to 6.5 kHz

Final design

After calculating all the passive component values for the feedback loop compensator and determining the converter’s main parameters, the entire flyback can be designed using the flyback regulator. Figure 4 shows the circuit’s final design using all calculated parameters.

Figure 4 Here is how the final design circuit schematic looks like. Source: Monolithic Power Systems

Figure 5 shows the bode plot of the complete loop gain frequency response.

Figure 5 Bode plot is shown for the complete loop gain frequency response. Source: Monolithic Power Systems

Obtaining the flyback averaged model via small-signal analysis is a complex process to most accurate approximation of the converter’s transfer functions. In addition, the cross-regulation technique involves secondary-side regulation through optocoupler feedback and an adjustable voltage reference, which complicates calculations.

However, by following the four steps explained in this article, a good approximation can be obtained to improve the power supply’s performance, as the output with the heaviest load is directly regulated. This means that the output can react quickly to load changes.

Joan Mampel is application engineer at Monolithic Power Systems (MPS).

Related Content

• Power Tips: Compensating Isolated Power Supplies
• Details on compensating voltage mode buck regulators
• Power Tips #139: How to simplify AC/DC flyback design with a self-biased converter
• Modeling and Loop Compensation Design of Switching Mode Power Supplies, Part 1
• Modeling and Loop Compensation Design of Switching Mode Power Supplies, Part 2

The post Design a feedback loop compensator for a flyback converter in four steps appeared first on EDN.

The XDP711-001 48-V digital hot-swap controller from Infineon offers programmable SOA current control for high-power AI servers. It provides I/O voltage monitoring with an accuracy of ≤0.4% and system input current monitoring with an accuracy of ≤0.75% across the full ADC range, enhancing fault detection and reporting.

Built on a three-block architecture, the XDP711-001 integrates high-precision telemetry, digital SOA control, and high-current gate drivers capable of driving up to eight N-channel power MOSFETs. It is designed to drive multiple MOSFETs in parallel, supporting the development of power delivery boards for 4-kW, 6-kW, and 8-kW applications.

The controller operates within an input voltage range of 7 V to 80 V and can withstand transients up to 100 V for 500 ms. It provides input power monitoring with reporting accuracy of ≤1.15% and features a high-speed PMBus interface for active monitoring.

Programmable gate shutdown for severe overcurrent protection ensures shutdown within 1 µs. With options for external FET selection, one-time programming, and customizable fault detection, warning programming, and de-glitch timers, the XDP711-001 offers flexibility for various use cases. Additionally, its analog-assisted digital mode maintains backward compatibility with legacy analog hot swap controllers.

The XDP711-001 will be available for order in mid-2025. For more information on the XPD series of protection and monitoring ICs, click here.

Infineon Technologies 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Qualcomm unveiled the Snapdragon G series, a lineup of three chips for advanced handheld, dedicated gaming devices. The G3 Gen 3, G2 Gen 2, and G1 Gen 2 SoCs support various play styles and form factors, enabling gamers to play cloud, console, Android, or PC games.

Snapdragon G3 Gen 3 is the first in the G Series to support Lumen, Unreal Engine 5’s dynamic global illumination and reflections technology, for Android handheld gaming. Gen3 Gen 3 offers 30% faster CPU performance, 28% faster graphics, and improved power efficiency over the previous generation. Wi-Fi 7 support reduces latency and boosts bandwidth.

Snapdragon G2 Gen 2 is optimized for gaming and cloud gaming at 144 frames/s, delivering 2.3x faster CPU performance and 3.8x faster GPU capabilities compared to G2 Gen 1. It also supports Wi-Fi 7 for faster, more reliable connections.

Snapdragon G1 Gen 2 targets a wider audience, supporting 1080p at 120 frames/s over Wi-Fi. Designed for cloud gaming on handheld Android devices, it boosts CPU performance by 80% and GPU performance by 25% for smooth gameplay.

Starting this quarter, OEMs like AYANEO, ONEXSUGAR, and Retroid Pocket will release devices powered by the Snapdragon G series. For more details on all three platforms, click here.

Qualcomm Technologies

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Microchip’s AVR SD entry-level MCUs feature built-in functional safety mechanisms and a dedicated safety software framework. Intended for applications requiring rigorous safety assurance, they meet ASIL C and SIL 2 requirements and are developed under a TÜV Rheinland-certified functional safety management system.

Hardware safety features include a dual-core lockstep CPU, dual ADCs, ECC on all memory, an error controller, error injection, and voltage and clock monitors. These features reduce fault detection time and software complexity. The AVR SD family detects internal faults quickly and deterministically, meeting Fault Detection Time Interval (FDTI) targets as low as 1 ms to enhance reliability and prevent hazards.

Microchip’s safety framework software integrates with MCU hardware features to manage diagnostics, enabling the devices to detect errors and initiate a safe state autonomously. The AVR SD microcontrollers serve as main processors for critical tasks such as thermal runaway detection and sensor monitoring while consuming minimal power. They can also function as coprocessors, mirroring or offloading safety functions in systems with safety integrity levels up to ASIL D/SIL 3.

Prices for the AVR SD microcontrollers start at $0.93 each in lots of 5000 units, with lower pricing for higher volumes.

AVR SD product page

Microchip Technology 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Nexperia has expanded its GaN FET portfolio with 12 new E-mode devices, available in both low- and high-voltage options. The additions address the demand for higher efficiency and compact designs across consumer, industrial, server/computing, and telecommunications markets. Nexperia’s portfolio includes both cascode and E-mode GaN FETs, available in a wide variety of packages, providing flexibility for diverse design needs.

The new offerings include 40-V bidirectional devices (RDS(on) <12 mΩ), designed for overvoltage protection, load switching, and low-voltage applications such as battery management systems in mobile devices and laptop computers. These devices provide critical support for applications requiring efficient and reliable switching.

Also featured are 100-V and 150-V devices (RDS(on) <7 mΩ), useful for synchronous rectification in power supplies for consumer devices, DC/DC converters in datacom and telecom equipment, photovoltaic micro-inverters, Class-D audio amplifiers, and motor control systems in e-bikes, forklifts, and light electric vehicles. The release also includes 700-V devices (RDS(on) >140 mΩ) for LED drivers and power factor correction (PFC) applications, along with 650-V devices (RDS(on) >350 mΩ) suitable for AC/DC converters, where slightly higher on-resistance is acceptable for the specific application.

To learn more about Nexperia’s E-mode GaN FETs, click here.

Nexperia

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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NVIDIA’s Spectrum-X and Quantum-X silicon photonics-based network switches connect millions of GPUs, scaling AI compute. They achieve up to 1.6 Tbps per port and up to 400 Tbps aggregate bandwidth. NVIDIA reports the switch platforms use 4x fewer lasers for 3.5x better power efficiency, 63x greater signal integrity, 10x higher network resiliency at scale, and 1.3x faster deployment than conventional networks.

Spectrum-X Photonics Ethernet switches support 128 ports of 800 Gbps or 512 ports of 200 Gbps, delivering 100 Tbps of total bandwidth. A high-capacity variant offers 512 ports of 800 Gbps or 2048 ports of 200 Gbps, for a total throughput of 400 Tbps.

Quantum-X Photonics InfiniBand switches provide 144 ports of 800 Gbps, achieved using 200 Gbps SerDes per port. Built-in liquid cooling keeps the onboard silicon photonics from overheating. According to NVIDIA, Quantum-X Photonics switches are 2x faster and offer 5x higher scalability for AI compute fabrics compared to the previous generation.

NVIDIA’s silicon photonics ecosystem includes collaborations with TSMC, Coherent, Corning, Foxconn, Lumentum, and SENKO to develop an integrated silicon-optics process and robust supply chain.

Quantum-X Photonics InfiniBand switches are expected to be available later this year. Spectrum-X Photonics Ethernet switches will be coming in 2026 from leading infrastructure and system vendors. Learn more about NVIDIA’s silicon photonics here.

NVIDIA

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Frequent design idea (DI) contributor Nick Cornford recently published a synergistic pair of DIs “A pitch-linear VCO, part 1: Getting it going” and “A pitch-linear VCO, part 2: taking it further.”

Wow the engineering world with your unique design: Design Ideas Submission Guide

The main theme of these articles is design techniques for audio VCOs that have an exponential (a.k.a. linear in pitch) relationship between control voltage and frequency. Great work Nick! I became particularly interested in the topic during a lively discussion (typical of editor Aalyia’s DI kitchen) in the comments section. The debate was about whether such a VCO could be built around the venerable 555 analog timer. Some said nay, others yea. I leaned toward the latter opinion and decided to try to put a schematic where my mouth was. Figure 1 is the result.

Figure 1 555 VCO discharges timing cap C1 completely to the negative rail via a Reset pulse.

The nay-sayers’ case hinged on a perceived inability of the 555 architecture to completely discharge the timing capacitor, C1 in Figure 1. They seemed to have a good argument because, in its usual mode of operation, the discharge of C1 ends when the trigger input level is crossed. This normally happens at one third of the supply rail differential and one third is a long way from zero! But it turns out the 555, despite being such an old dog, knows a different trick, it involves a very seldom used feature of this ancient chip: the reset pin 4.

The 555 datasheet says a pulse on reset will override trigger and also force discharge of C1. In Figure 1, R3 and C2 provide such a pulse when the OUT pin goes low at the end of the timing cycle. The R3C2 product ensures the pulse is long enough for the 15 Ω Ron of the Dch pin to accurately evacuate C1. 

And that’s it. Problem solved as sketched in Figure 2.

Figure 2 The VCO waveforms; reset pulses at the end of each timing cycle, and is triggered when Vc1 = Vcon, to force an adequately complete discharge of C1.

Figure 3 illustrates the resulting satisfactory log conformity (due mostly to my shameless theft of Nick’s clever resistor ratios) of the resulting 555. VCO, showing good exponential (linear in pitch) behavior over the desired two octaves of 250 to 1000 Hz.

Figure 3 Log plot of the frequency versus control voltage for the two-octave linear-in-pitch VCO. [X axis = Vcon volts (inverted), Y axis = Hz / 16 = 250 Hz to 1 kHz]

In fact, at the price of an extra resistor, it might be possible to improve linearity enough to pick up another half a volt and half an octave on both ends of the pitch range to span 177 Hz to 1410 Hz. See Figure 4 and Figure 5.

Figure 4 R4 sums ~6% of Vcon with the C1 timing ramp to get the improvement in linearity shown in Figure 5.

Figure 5 The effect of the R4 modification showing a linearity improvement. [X axis = Vcon volts (inverted), Y axis = Hz / 16]

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• A pitch-linear VCO, part 1: Getting it going
• A pitch-linear VCO, part 2: taking it further
• VCO using the TL431 reference
• Ultra-low distortion oscillator, part 1: how not to do it.
• How to control your impulses—part 1
• A two transistor sine wave oscillator

The post Can a free running LMC555 VCO discharge its timing cap to zero? appeared first on EDN.

This year during APEC, much of the focus on the show floor revolved around data center tech, with companies showcasing high-density power supply units (PSU), battery backup units (BBU), intermediate bus converters (IBC), and GPU solutions (Figure 1). 

Figure 1: Up to 12 kW Infineon PSU technology leverages a mixture of the CoolSIC, CoolMOS, and CoolGaN technologies. 

The motivation comes from the massive power demand increase that the generative AI, in particular, LLMs have brought on, shooting up the 2% of global power consumption from data centers to a projected 7% by 2030. This power demand originates from the shift from the more 120 kV (single-phase AC) stepped down to 48 V to 250-350 kV (three-phase AC) stepped down to 400 VDC rails attached to the rack and distributed from there (to switches, PSUs, compute trays, switch trays, BBUs, and GPUs).

Infineon’s booth presented a comprehensive suite of solutions from the “power grid to the core.” The BBU technology (Figure 2) utilizes the partial power converter (PPC) topology to enable high power densities (> 12 kW) using scalable 4 kW power converter cards.

Figure 2: Infineon BBU roadmap, using both Si and GaN to scale up the power density of the converters with high efficiencies. Source: Infineon

The technology boasts an efficiency of 99.5% using lower voltage (40 V and 80 V) switches to increase figure of merit (FOM) and yield efficiency gains. The solutions are aimed at meeting space-restrictions of modern BBUs that are outfitted with more and more batteries and hence less space for the embedded DC/DC converter.

Their latest generation of vertical power delivery modules feature a leap in GPU/AI card power delivery, offering up to 2 A/mm2. These improvements create massive space-savings on the already space-constrained AI cards that often require 2000 A to 3000 A for power-hungry chips such as the Nvidia Blackwell GPU.

Instead of being mounted laterally, or alongside the chip, these devices deliver power on the underside of the card to massively reduce power delivery losses. The backside mounting does come with its profile restraints; there is a max height of 5 mm to facilitate heatsink mounting on the other side of the board, so these modules must maintain their 4-mm height. 

The first generation of the dual-phase module featured the silicon device that sat on top of the substrate with integrated inductors and capacitors to achieve 1 A/mm2, or 140A max,  in a 10 x 9 mm package. This was followed by a dual-phase module that featured a 1.5 A/mm2, or 160 A max, improvement within 8 x 8 mm dimensions. Embedding the silicon into the substrate to have only one PCB is what contributed to the major space-savings in this iteration (Figure 4). 

Figure 4: The second generation of Infineon vertical power delivery modules mounted on the backside of GPU PCB deliver a total of 2000 A. An Infineon controller IC can also be seen providing the necessary voltage/current through coordination with the vertical power delivery modules and chip.

The third generation just released has brought on two more power stages for a quad-phase module for 2 A/mm2, or 280 A max, in the 10 x 9 mm space; doubling the current density of the first generation in the same space (Figure 5). 

Figure 5: Third generation of Infineon vertical power delivery modules are mounted on the backside of GPU PCB delivering a total of 2,000 A. 

Custom solutions can go beyond this, integrating more power stages in a single substrate. Other enhancements include bypassing the motherboard and direct-attaching to the substrate in the GPU since PCB substrate materials are lossy for signals with high current densities.

However, this calls for closer collaboration with SoC vendors that are willing to implement system-level solutions. High current density solutions are in the works with Infineon, potentially doubling the current density with another multi-phase module.

The Navitas booth also showed two form factors of PSUs: a common redundant power supply (CRPS) form factor and a longer PSU that meets open compute project (OCP) guidelines and compiled to the ORv3 base specification (Figure 6). The CRPS solution delivers 4.5 kW with two-stages including a SiC PFC end and GaN LLC and offers titanium level efficiency.

Figure 6: Typical rack is shown with RAM, GPU, PSUs, and airflow outlet with barrel fans. The PSUs conform to the CRPS and provide redundancy to encourage zero downtime in the event of transient faults, brownouts, and blackouts.

Hyperscalers or high performance compute (HPC) applications that utilize the OCP architecture can install PSUs in a row to centralize power in the rack. The Navitas PSU offered for this datacenter topology offers up to 8.5 kW with up to a 98% efficiency using a three-phase interleaved CCM totem pole SiC PFC and three-phase GaN LLC (Figure 7).

Figure 7: Navitas 8.5 kW PSU is geared toward hyperscalers using both Gen-3 Fast SiC and GaNSafe devices.

Aalyia Shaukat, associate editor at EDN, has worked in the design publishing industry for six years. She holds a Bachelor’s degree in electrical engineering from Rochester Institute of Technology, and has published works in major EE journals as well as trade publications.

Related Content

• Data center power meets rising energy demands amid AI boom
• Telecom/Datacom 48V: Have no fear; 400V is here
• Power Tips #139: How to simplify AC/DC flyback design with a self-biased converter
• Data center next generation power supply solutions for improved efficiency

The post Data center solutions take center stage at APEC 2025 appeared first on EDN.

My recent teardown of a rechargeable vape device was…wow…popular. I suspected upfront that it might cultivate a modicum of incremental traffic from the vape-using (and vape-curious) general public, but…wow. This long-planned follow-up focuses on non-rechargeable (i.e., disposable) vape counterparts, in part fueled by my own curiosity as to their contents but more generally and predominantly driven by my long-standing bleeds-green environmental outrage.

Here’s an example of what I mean, showcased in a recent Slashdot post that highlighted a writeup in The Guardian:

Thirteen vapes are thrown away every second in the UK — more than a million a day — leading to an “environmental nightmare,” according to research.

There has also been a rise in “big puff” vapes which are bigger and can hold up to 6,000 puffs per vape, with single use vapes averaging 600. Three million of these larger vapes are being bought every week according to the research, commissioned by Material Focus, and conducted by Opinium. 8.2 million vapes are now thrown away or recycled incorrectly every week.

From June 2025 it will be illegal to sell single-use vapes, a move designed to combat environmental damage and their widespread use by children. Vapes will only be allowed to be sold if they are rechargeable or contain a refillable cartridge.

But all types of vape contain lithium-ion batteries which are dangerous if crushed or damaged because they can cause fires in bin lorries or waste and recycling centres. These fires are on the rise across the UK, with an increase last year of 71% compared with 2022.

I have (at least) two questions:

• If there are a million toxic chemical- and metal-leaching vapes headed to landfills (if we’re lucky; many, more likely, are sent directly into the water table via casual, irresponsible discard wherever it’s convenient for the owner to toss ‘em) in the UK alone, what’s that number look like when extrapolated to a worldwide count? Truthfully, from a blood pressure standpoint, I’m not sure I want to know the answer to that one.
• And why are vapes that are “rechargeable or contain a refillable cartridge” (bolded emphasis mine) excluded from the upcoming UK ban? Why can’t (and shouldn’t) it instead be only those that are “rechargeable and contain a refillable cartridge”?

Rant off. One of the comments I posted as follow-up to last November’s initial entry in this vape-teardown series pointed readers to near-coincident published related coverage in Ars Technica:

Disposable vapes are indefensible. Many, or maybe most, of them contain rechargeable lithium-ion batteries, but manufacturers prefer to sell new ones. More than 260 million vape batteries are estimated to enter the trash stream every year in the UK alone. Vapers and vape makers are simply leaving an e-waste epidemic to the planet’s future residents to sort out.

To make a point about how wasteful this practice is—and to also make a pretty rad project and video—Chris Doel took 130 disposable vape batteries (the bigger “3,500 puff” types with model 20400 cells) found littered at a music festival and converted them into a 48-volt, 1,500-watt e-bike battery, one that powered an e-bike with almost no pedaling more than 20 miles.

The accompanying video is well worth your viewing time, IMHO.

and gave me the confidence to attempt my own teardown of conceptually similar vape devices, since Doel had confidently just ripped off the tip and back ends to get to their insides. Here’s the implement of destruction that I personally used:

And here are today’s victims, extracted from the trash as was the case with their rechargeable predecessor, and as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes (not to mention roll-away prevention purposes):

The upper one is actually (supposedly, although there are still loopholes, apparently) no longer available in the US. It’s the “4000 puff” Noms X product variant (and Mojito Mint flavor) of the Esco Bars brand, manufactured by the Chinese company Shenzhen Innokin Technology. And no, I have no idea what “Pastel Cartel” means. The lower vape is Mr Fog ‘s “2000 puffs” Max pro model (and Raspberry Grape Black Currant flavor).

Here are their respective tips:

And their bottoms:

The black-color bottom end of the Esco Bars vape is fixed in position; note the two holes for incoming-airflow purposes. You’ll shortly see what secondary function the one in the middle also serves; that said, I’m not sure of the purpose of the incremental smaller second offset one. The white-color end of the Mr Fog vape, conversely, can be rotated to user-adjust the airflow. The two vents are on the sides of the end piece; here’s how airflow adjustment operates:

and briefly jumping ahead in time mid-teardown, here’s how it’s implemented:

Let’s start the disassembly process with the Esco Bars device, as previously mentioned by wrenching the bottom piece off with my pliers (see what I did there?).

That black rectangular spongy piece went flying when I pulled the bottom piece off, but I’m guessing from the lingering indentations that it normally sits in-between that thing that looks like a microphone (and fits inside the circular middle portion of the bottom piece) and the battery. And about that “thing that looks like a microphone”…I was initially a bit flummoxed when I saw it (no, I never thought it was actually a microphone, although other folks were amusingly-to-me apparently convinced otherwise), until I realized that neither vape has an on-off switch. Instead, what you do to “turn them on” (i.e., power up the heating coil) is to suck on the tip, which vapers refer to as a “draw”.

This “thing that looks like a microphone”, apparently, is a “draw sensor”; it detects the resultant user-generated airflow that’s initiated from the bottom and (as is already obvious even with the battery still in place) passes from there through the gap between the battery and vape body. This Quora thread has all the details, including pictures of a sensor that looks just like the one in the Esco Bars vape (and the Mr Fog one, for that matter, prematurely ruining the surprise…sorry). I’m guessing that the red and black wires route to the sensor from the battery, and the blue one carries a signal sent by the sensor to the heating coil when airflow is detected.

By repeatedly shaking the vape device (with a foam cushion underneath, in case the contents went flying) I got the battery out of the case far enough:

that I was then able to get a grip on it with my fingers and pull it the rest of the way out:

The remainder of the internals remained stubbornly stuck at the rear end of the tube until I started twisting on the tip with the wrench:

At which point the translucent tube fell out the bottom, too. Disgusting (and oily, too), huh?

From my research (I’ve learned more than I ever wanted to about vapes the past 24 hours or so), inside the plastic tube are apparently nicotine salts, soaked in the flavored vape juice. Here’s the entirety of the insides, stretched out:

And here’s what you’ve all been waiting for, the battery specs, 3.7V and 5.55 Wh:

Now for the Mr Fog vape. Again, I started with the white bottom piece, which initially didn’t get me very far (although look; another “microphone”):

So, I switched to the tip, which didn’t get me much further along…and yuck, again:

Back to the bottom for more twisting, this time of the clear plastic piece that as I showed you earlier, the white bottom piece fits around. That’s better:

Once again, a combination of shaking and two-finger pinching-and-pulling got the battery out:

But this time I had to then push from the top to get the rest out:

Greasy, smelly mission completed:

And the battery specs: once again 3.7V, but this time only 4.07 wH/1100 mAh, reflective of the Mr Fog vape’s comparative “half the puffs” estimate versus the Esco Bars alternative.

In closing, what most surprised me, I guess, is that neither of these vapes use standard 18650 cells found in a diversity of other devices (although from some of my research, their limited spec’d peak output current capabilities might be a coil-heating hinderance or, worse, a thermal safety complication in this particular application), or even the less common 20400 ones showcased in the video at the beginning of this writeup. With that, I’ll wrap up, take a deep draw (of nicotine-free air, mind you) and await your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post Disposable vapes: Unnecessary, excessive waste in cylindrical shapes appeared first on EDN.

Texas Instruments’ APEC-related releases are power management chips centered around supporting the AI-driven power demands in data centers. The releases include the first 48-V integrated hot-swap eFuse with power-path protection (TPS1685) and an integrated GaN power stage (gate driver + FET) in the industry-standard TOLL package. 

In a conversation with Priya Thanigai, VP and Business Unit Manager of power switches at Texas Instruments, EDN obtained some insights on meeting the needs of next-generation racks demanding the 48-V architecture.

Spotlight on data centers

Hot topics at APEC typically encompassed the use of wide bandgap semiconductors like silicon carbide (SiC) and gallium nitride (GaN) to yield higher efficiency subsystems in the steady electrification of technologies. Electrified end applications have spanned from e-mobility to industrial processes that are enabled by battery and smart grid advancements. 

Discussions this year have shifted more toward the power demands that generative AI has created for data centers. While much of the actual power consumption of these data centers remains secretive, it’s apparent that LLMs like ChatGPT and DeepSeek have created a substantial increase; the U.S. data center electricity usage tripled from 2014 to 2023 according to the U.S. department of energy (DoE). The number is anticipated to double or triple by 2028.

The international energy agency (IEA) also reported that data centers consumed ~1.4-1.7% of global electricity in 2022; this is also expected to double by 2026. According to the World Economic Forum, “the computational power needed for sustaining AI’s growth is doubling roughly every 100 days.”

Going nuclear

Hyperscalers are also making more apparent their plans to sustain the energy demands. In September 2024, plans to recommission the Three Mile Island nuclear plant were made public with a 20-year contract to help power Microsoft data centers. Other technology companies follow a similar nuclear path, augmenting power capabilities with small modular reactors (SMRs).

And as the semiconductor industry is feverishly fabricating chips that can efficiently run these compute-intensive training tasks through software-hardware codesign, the power demands continually soar. Further into the future, these nuclear reactors could be used with solid-state transformers to support data center processing.

The 48-V bus and beyond

The data center server room consists of a sea of IT racks supported by a sidecar that holds hot-swappable power supply units (PSUs) that facilitate replacing or upgrading a PSU without shutting down the server (Figure 1). These PSUs support much higher power densities moving from 6 kW with the 48-V bus to 100 MW with the 400-V bus.

Figure 1: Sidecar, IT rack, and supporting subsystems shown at the TI booth during APEC 2025. 

“While data centers have been ahead of the curve, cars are only now moving to 48 V,” said Thanigai. “But data centers have probably already been there for about a decade.” It’s just been very slow because earlier systems really didn’t need the compute power until LLMs exploded. Until then, it was only the high-end GPUs that needed that extra power at 48 V.

She mentioned how TI had been keeping a watchful eye on the relatively slow move from 12-V products for data centers 48-V and how recent pressures have brought on that inflection point. “Now we’re seeing more native 48-V systems ship and we’re talking about 400-V already,” Thanigai said. “So the transition from 12 V to 48 V may have taken a decade to hit the inflection point but 48 V to 400 V will probably be shorter and sharper because of how much energy is needed by data centers.”

Moving from discretes to integrated eFuses

Power path protection is tied directly to PSU reliability and is therefore a critical aspect of ensuring zero downtime deployments. The 48-V eFuse is a successor to the popular 12-V eFuse category; the shift to 48 V allows users to scale power to beyond 6 kW. 

“If you’re looking at the power design transition, generally power architectures will begin with discretes at the start of any design because they want to get a good feel of how to build something,” explained Thanigai. The building blocks of power path protection generally include the power FET, a gate or voltage drive to drive it, and components like a soft-start capacitor to control the inrush, comparators, and current-sense elements.

Thanigai described the moves toward more integration where the hot swap controller integrates the amplifiers, some of the protection features, and some of the smarts. However, there still remains an external FET and sensing element. 

“The last leg of the integration is eFuse where the FET, the controller, and all the smarts are in a single chip,” she said. “That’s a classic power design evolution, where you go from discrete to semi-integrated to fully integrated.” The TPS1685 eFuse includes protection features like rapid response to fault events with an integrated black box for fault logging. Then there is a user-configurable overcurrent blanking timer that avoids false tripping at peak inrush.

Advanced stacking for loads > 6 kW

Mismatches in the on-state resistance (Rdson) due to PCB trace resistance and comparator thresholds can create false tripping (Figure 2). The conventional discrete designs require power architects to hand calculate the margins to make sure the FETs are matched such that no single FET is taking on more thermal stress than the others.  

Figure 2: Discrete implementations require individual calculations per sense element and FET to take into account mismatches at each node; instead Rdson is actively adjusted via Vgs regulation and equal steady-state current across all devices is achieved through path resistance equalization. Source: Texas Instruments 

The IP in the TPS1685 eFuse actively measures and monitors the thermal stress at various areas of the FET within each of the eFuses and balances current between each automatically through a single-wire protocol. The integration designates one eFuse as the primary controller to monitor total system current by using the interconnected IMON pins, enabling active RDS(ON) shifting to ensure devices are current-sharing.

“You can basically stack unlimited eFuses,” said Thanigai, “We’ve shown up to 12 operational eFuses on a customer board and each of them can do 1 kW (~ 50 V @ 20 A), so we easily reach the 5-10 kW that you see with systems nowadays. But we can scale higher than that since there’s no upper limit.”

Figure 3: Image of 6 eFuses stacked in parallel on the top and bottom of a PCB to support a maximum load current of 120 A. 

Moving toward 400 V

When asked about the move toward supporting 400-V bus architectures, Thanigai responded, “There’s two aspects in these eFuses.” There’s the pure analog power domain, which is the FET architectures, and then there’s the digital domain which embodies smarts around the FET, she added.

All of the digital IP TI has developed scales from 12 V to 48 V to 400 V, and that while this particular device includes 48-V power FETs, TI is preparing to scale this up to 400 V.

Aalyia Shaukat, associate editor at EDN, has worked in the design publishing industry for six years. She holds a Bachelor’s degree in electrical engineering from Rochester Institute of Technology, and has published works in major EE journals as well as trade publications.

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The post Data center power meets rising energy demands amid AI boom appeared first on EDN.

The venerable Stephen Woodward recently published the design idea (DI) “Flip ON flop OFF” that converts a momentary push button to a classic push-on, push-off switch. Figure 1 is an attempt to go further still in terms of economy.

The circuit shown in Figure 1 utilizes only one half of a dual D-type package and one more capacitor to the original parts count. It also incorporates an RC power on set (or reset), to guarantee the initial state of the switch when power is applied.

Figure 1 U1A debounces SW1 via R1 & C2 so U1A can reliably toggle.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The initial state of the switch is determined by the Set pin of U1A following the rising voltage on the power input due to the initial discharged state of C1. Capacitor C1 then charges towards ground leaving the flip-flop with the Q output high and the PMOS off.

Alternatively, this RC power on Set circuit can be wired to the Reset pin to change the initial power on state of the switch. The device ESD clamping diodes provide the capacitor discharge path when power is turned off.

The D-type flip-flop is essentially connected in the familiar way of Q-bar to D-input to form a bistable with each clock rising edge toggling the output state. However, in this case the combination of R1 and C2 form a delay network which prevents rapid changes on the D-input, thus effectively de-bouncing the switch by inhibiting state changes until C2 has charged/discharged to the state on the Q-bar output.

—Chris Nother built a discrete Tx/Rx for model aircraft at an early age, later discovering the dreaded “Mains Hum” in a home built “Dinsdale” Hi-Fi amplifier. Employed in R&D using the then newly available available CMOS logic from Motorola and Nat-Semi, career changes to Mainframe Computers, design of disk drive automated test equipment and storage solutions, finally turning full circle in retirement to the hobby that started it all.

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Introduction

The demand for smaller, lighter, and more efficient AC/DC USB power delivery (PD) chargers is always a challenge for power-supply design engineers. Below 100 W, the quasi-resonant flyback is still the dominating topology, and gallium nitride (GaN) technology can push the power density and efficiency further.

However, providing bias power for the primary controller requires an auxiliary winding on the transformer as well as rectifying and filtering circuitry. To make things worse, the USB PD charger output voltage has a wide range. For example, the USB PD standard power range covers output voltages from 5 V to 20 V, and the latest USB PD extended power range allows the output voltage to go as high as 48 V. Since the auxiliary voltage is proportional to the output voltage, the bias voltage range on the primary controller will increase, requiring extra circuitry and degrading efficiency. In this power tip, I’ll introduce a self-biased flyback converter solution to address these design challenges.

Dealing with wide bias voltages

Figure 1, Figure 2, Figure 3, and Figure 4 show four different ways to deal with the wide bias voltage range in USB PD charger applications. Conventional methods include using a linear regulator, a tapped auxiliary winding, or even adding an extra DC/DC switching converter to regulate the bias voltage. All of these methods will increase component count, add cost, or increase power losses. Alternatively, self-biasing totally removes external components and increases efficiency.

Figure 1 Bias circuits for applications with wide output voltage ranges using a discrete linear regulator. Source: Texas Instruments

Figure 2 Bias circuits for applications with wide output voltage ranges using a tapped auxiliary winding. Source: Texas Instruments

Figure 3 Bias circuits for applications with wide output voltage ranges using boost converter. Source: Texas Instruments

Figure 4 Bias circuits for applications with wide output voltage ranges using a self-biased VCC. Source: Texas Instruments

VCC self-biasing

The flyback controller can always get bias power directly from the rectified AC input voltage, but this results in excessive power losses. The key to self-biasing is to harvest energy from the power stage, which can come from two sources. One is the switch-node capacitor stored energy; the other is energy stored in the primary-side winding of the transformer. As shown in Figure 5, an integrated self-biasing circuit can ideally do both, based on the input and output conditions.

Figure 5 The self-bias circuit harvests energy from the switch-node capacitance or magnetizing inductance. Source: Texas Instruments

Figure 6 shows the energy harvesting from the switch-node capacitor. This can save efficiency as it recycles the energy storage in switching node capacitor in every switching cycle. In cases such as AC low-line input when the reflected output voltage is identical to the input voltage, natural zero voltage switching will occur, and there is no energy in the switch-node capacitor, inductor energy harvesting will take effect, where a small portion of the primary switching current is directed to the VCC cap through an internal path.

Figure 6 VCC self-bias operation: (a) capacitor energy harvesting on the switching node and (b) inductor energy harvesting through the primary current. Source: Texas Instruments

Achieving auxless sensing

Many flyback controllers use the auxiliary winding to sense the input and output voltages and detect conditions such as output overvoltage or input undervoltage. With self-biased flyback converters, it is possible to use the switching-node voltage for input and output voltage sensing. As shown in Figure 7, the sensed voltage is the sum of the input and reflected output voltage. Since the average voltage across the primary winding is zero, the average of the switch-node voltage is equal to the input voltage.

For output voltage sensing, it can sample the reflected output voltage, and the controller needs to be informed of the exact turns ratio of the transformer with the use of a resistor-programmable pin [the TR pin in the Texas Instruments (TI) UCG28826].

Figure 7 Auxless voltage sensing where the sensed voltage is the sum of the input and reflected output voltage. Source: Texas Instruments

Once properly configured, self-biased devices such as the UCG28826 can accurately provide various protections like overpower and overvoltage protection. Figure 8 shows the UCG28826 in a USB PD application.

Figure 8 A self-biased USB PD design using the UCG28826 that can accurately provide various protections like overpower and overvoltage protection. Source: Texas Instruments

Figure 9 shows the overvoltage protection waveforms after intentionally disconnecting the feedback pin which is a single fault condition. The controller senses the output voltage and triggers overvoltage protection accordingly when the output ramps up to around 24.4 V for a nominal 20 V output.

Figure 9 Auxless sensing example for overvoltage protection. Channel 1 (CH1) is Vout and channel 2 (CH2) is Vsw. Source: Texas Instruments

Prototype and test result

Figure 10 shows the TI universal AC-input 65W dual USB type-C port USB PD charger reference design with an integrated GaN power switch. Due to the simplified self-bias feature and integrated GaN switch in the UCG28826, the reference design achieves a power density of 2.3 W/cm3 and 93.2% efficiency for the AC/DC stage. The auxless design also simplifies transformer manufacturing and reduces costs. Table 1 summarizes the design parameters of 65 W design for reference. 

Figure 10 A universal AC-input 65-W reference design board. Source: Texas Instruments

Parameter	Value
AC input voltage	90-264 VAC
Output voltage and current	5-20 V, 3.25 A maximum
Transformer	ATQ23-14
Turns ratio	7-to-1
Transformer inductance	200 µH
Switching frequency (full load)	90-140 kHz
Efficiency	93.2% at 90 VAC (AC/DC stage only)
Power density	2.3 W/cm3

Table 1 Universal AC-input 65W reference design parameters.

Simplified USB PD charger

A high-level integration with a controller and GaN switch can simplify USB PD charger design, but the bias circuitry for the controller and associated auxiliary winding on the transformer are still there, degrading efficiency and affecting size and cost. An integrated self-biasing circuit can eliminate that portion of the circuit and increase the power density for power supplies with wide-range outputs. Additionally, it is still possible to achieve proper input and output voltage sensing in the absence of an auxiliary winding on the transformer.

Max Wang is a systems engineer and Member, Group Technical Staff at Texas Instruments. He has over 18 years of experience in the power semiconductor and power-supply industries in computing, industrial, and personal electronics markets; specializing in isolated AC/DC and DC/DC applications. His design and research interests include high-efficiency and high-power-density power conversion, soft-switching converters, and GaN implementation in AC/DC converters. Max obtained a master’s degree in electrical engineering from Zhejiang University in 2006. He has worked at Delta, Power Integrations, Infineon and Texas Instruments.

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Printed circuit boards (PCBs) have come a long way over the years. Electronics design engineers must stay aware of the latest developments to understand how they might soon incorporate them into their work.

For instance, as more products require PCBs and the demand continues rising, so have concerns about reducing e-waste. Fortunately, promising ideas have recently emerged, showing the exciting possibilities.

Biodegradable substrates

Some people take inspiration from nature when figuring out how to reduce waste. That was the case for a university team that uses leaves’ natural structure to create biodegradable substrates that could change PCB designs.

Conventional PCB substrates contain glass fiber-reinforced epoxy resin. They are typically not recyclable, making people eager to find a more sustainable solution. These researchers discovered it through quasi-fractal lignocellulose structures, which act as scaffolds for leaves’ living cells. The group realized they could also bind solution-processable polymers. Tests showed this alternative can tolerate soldered circuitry manufacturing and supports innovative thin-film devices.

Additionally, once the PCB substrate is no longer usable, users can sustainably dispose it by allowing it to break down in soil or processing the component in biogas plants to recover some of its precious metals for reuse.

In another effort to tackle e-waste, researchers developed a PCB that people can recycle several times with virtually no material loss. Their experiment showed it performed as well as those made from traditional materials.

The group developed a solvent that turns a class of sustainable polymers into a jelly-like substance without harming the solid components left behind. Users can then pick them out for recycling. This approach allows them to recover 98% of the polymers, 91% of the recycling solvent, and all the glass fiber.

Moving ahead with flexible PCBs

Electronics designers and others are also interested in moving away from rigid PCBs and prioritizing flexible ones when possible. This improvement enables better application versatility and helps users produce smaller, more complex devices.

Next, mechanical engineers have developed a pioneering way to create the circuits necessary for electronic connections inside devices from wearable health trackers to robots. Those working on this project believe progress with soft circuits could revolutionize how engineers use and create electronic devices. Additionally, currently available flexible PCBs require few or no wires, reducing connection failures.

This team created a production process that uses liquid-metal microdroplets to make a stair-like structure when adding vias and planar interconnects. The method allows them to enable electrical connections across layers without physically drilling into the material, as previous options required.

Experiments suggested engineers could use the microdroplet application technique on several materials or build multiple layers to suit individual device specifications. This method is also efficient; researchers were able to make several vias in less than a minute. In one case, they made a dual-layer soft circuit with nine LEDs on the top and nine connected sensors on the bottom. This component had 21 liquid-metal connectors and was only as thick as a sheet of paper.

PCBs will continue evolving

These are some of the many examples of engineers’ ongoing efforts to make PCBs more aligned with today’s devices and the industry’s priorities. Electronics design engineers should remain aware of these innovations and continually explore how they might implement these possibilities into future projects.

Ellie Gabel is a freelance writer as well as an associate editor at Revolutionized.

 

 

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The Renesas RZ/V2N quad-core MPU integrates an AI accelerator, achieving up to 15 TOPS of AI inference using pruning technology. Pruning reduces memory usage and increases computing efficiency by removing parts of the AI inference process. The MPU also includes an image signal processor and two MIPI CSI-2 camera interfaces for enabling endpoint vision AI.

With the RZ/V2N, the RZ/V series expands to cover markets from the low-end RZ/V2L (0.5 TOPS) to the high-end RZ/V2H (up to 80 TOPS). At just 15 mm², the RZ/V2N is significantly smaller than the high-end RZ/V2H, reducing the mounting area by 38%. It also delivers a power efficiency of 10 TOPS/W.

Along with the DRP-AI3 accelerator, the RZ/V2N features four Arm Cortex-A55 cores, a Cortex-M33 core, and an Arm Mali-C55 image signal processor (ISP). Its dual MIPI CSI-2 interfaces support two cameras, enabling double-angle image capture for improved spatial recognition, precise human motion analysis, and fall detection. A dual-camera setup can also capture images from different locations, allowing a single chip to count cars in a parking lot and recognize license plates.

The RZ/V2N microprocessor will be available from Renesas and its authorized distributors starting March 19, 2025.

RZ/V2N product page

Renesas Electronics 

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An indirect time-of-flight sensor, the AF0130 from onsemi offers long-distance measurements and 3D imaging of fast-moving objects. It features a depth processing ASIC beneath its pixel area, which rapidly calculates depth, confidence, and intensity maps from laser modulated exposures.

The AF0130, part of the Hyperlux ID sensor family, combines global shutter and iToF technology for precise, high-speed depth sensing. It measures phase shifts in reflected VCSEL light, capturing four light phases in one exposure for enhanced accuracy. A global shutter reduces ambient IR noise, while onboard depth processing and memory enable real-time results without external memory or a high-performance processor.

onsemi states that the AF0130 enables depth sensing up to 30 meters—four times the range of standard iToF sensors. The 1.2-Mpixel CMOS sensor features 3.5-µm BSI pixels in a 1/3.2-in. optical format. A variant, the AF0131, delivers the same performance but excludes on-chip depth processing for manufacturers preferring off-chip depth calculation.

Availability for the AF0130 and AF0131 sensors was not provided at the time of this announcement.

AF013X product page

onsemi

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Kinetic’s KTB4800 2.4-MHz, 3-A buck regulator delivers fast transient response with precise switching frequency. Its OptiComp adaptive on-time PWM control scheme maintains a nearly constant switching frequency despite input and output voltage variations.

Compared to typical current-mode PWM schemes, OptiComp enables quick response to line and load transients while ensuring excellent stability and wide bandwidth. This reduces output voltage droop and overshoot for dynamic loads, even with minimal output capacitance.

The KTB4800 buck regulator supports a range of applications, including CPU and GPU cores, DSPs, DDR memory, I/O power, and sensor/analog supplies. Its output voltage is I²C-programmable from 0.6 V to 3.345 V. The regulator features soft-start and dynamic voltage scaling (DVS) with multiple programmable ramp rates, along with selectable forced-PWM and auto-skip modes for light-load efficiency.

The KTB8400 OptiComp switching regulator is available now for order from Mouser Electronics and other distributors.

KTB8400 product page

Kinetic Technologies

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Housed in a small SO8L package, Toshiba’s TLP5814H gate driver photocoupler provides an active Miller clamp for driving SiC MOSFETs. Its built-in clamp circuit directs Miller current from the gate to ground, preventing short circuits without requiring a negative voltage. This enhances system safety while reducing external circuitry for a more compact design.

The TLP5814H delivers a peak output current of +6.8 A/-4.8 A, with the Miller clamp providing a typical channel resistance of 0.69 Ω and a peak sinking current of +6.8 A. Its -40°C to +125°C operating range is achieved by enhancing the infrared LED’s optical output and optimizing the photodetector design for better optical coupling efficiency. This makes the device well-suited for industrial equipment with strict thermal requirements, such as PV inverters and uninterruptible power supplies.

Key specifications for the TLP5814H include:

The TLP5814H’s compact 5.85×10×2.1-mm package enhances layout flexibility while providing an 8.0-mm creepage distance for high-insulation applications.

Toshiba has begun volume shipments.

TLP5814H product page

Toshiba Electronic Devices & Storage

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Microchip’s PIC32A 32-bit MCUs feature an FPU coprocessor that performs both 32-bit and 64-bit operations for math-intensive tasks. Operating at 200 MHz, they also integrate high-speed analog peripherals to minimize external component requirements.

Two 12-bit ADCs, with conversion rates up to 40 Msamples/s, are complemented by three 5-ns analog comparators and 12-bit pulse density modulation DACs. The MCUs also include three rail-to-rail 100-MHz op amps with a slew rate of 100 V/µs. These features enable cost-effective edge sensing and control, making the PIC32A series well-suited for automotive, industrial, consumer, AI/ML, and medical applications.

To ensure safe software execution in embedded control systems, the PIC32A MCUs offer a range of hardware safety and security features. These include ECC on flash and RAM, Memory Built-In Self-Test (MBIST), I/O integrity monitors, fail-safe clock monitor, immutable secure boot, and flash access control.

Prices for the PIC32A microcontrollers start at less than $1 each in volume quantities.

PIC32A product page

Microchip Technology

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Imagine that you have a voltage source in series with some source resistance feeding power to a variable load. The relationship between load voltage, load current, and cell current can be drawn as follows in Figure 1.

Figure 1 The load voltage versus cell and load current for a circuit where the voltage source is in series with some source resistance feeding power to a variable load.

If by multiplying load voltage times load current, we examine power delivery to the load versus load resistance where the result is a curve that looks like an upside-down soup bowl (Figure 2).

Figure 2 Power to the load (load voltage*load current) versus cell and load current.

For some specific source resistance value, we can plot a horizontal line on our graph (Figure 3).

Figure 3 Adding a specific numerical value for the source resistance.

If we next add a curve to plot the varying load resistance value (Figure 4), we find that the point of maximum power delivery to the load corresponds to equality between the load resistance to the source resistance. Of course, this is expected to be so, but we should also note that the equality of interest is really between the load resistance and the dynamic value of the source resistance as opposed to that part’s value of static resistance.

Figure 4 Discovery of the peak power point by finding the equality between the load resistance to the source resistance.

This last remark may seem trivial, but as we shall now show, it is NOT trivial at all.

From Linear Technology (a name of fond memory today) at this now inoperative URL, we had the following sketch of a photovoltaic (PV) assembly’s characteristics shown in Figure 5.

Figure 5 Solec S-70C PV panel power curve while facing the sun.

Graphically extracting some numbers from the current versus voltage curve and fitting a descriptive equation to those numbers, we find the following in Figure 6.

Figure 6 A numerical representation of the PV device shown in Figure 5.

Again, we multiply the load voltage times the cell and load current to see the curve of the power delivery to the load and we also draw the dynamic resistance of the photovoltaic device (Figure 7).

Figure 7 Current, power and dynamic resistance curves for the Solec S-70C PV device, the dynamic resistance of the PV here is no longer the static horizontal line we saw in Figure 3.

Note now that the dynamic resistance of the photovoltaic device is not a horizontal line. The dynamic resistance of the photovoltaic device is now a variable. We also note that the power curve is no longer symmetrical but has instead taken a lean over to the viewer’s right.

Identifying the point of maximum power to the load or identifying the peak power point, we see the following in Figure 8.

Figure 8 Discovery of the peak power point for the Solec S-70C PV device.

We find that the peak power point is located where the load resistance equals the dynamic source resistance of the PV device.

If you want to get as much power delivery as possible out of a PV device, the load resistance needs to match the dynamic source impedance of that device.

Please note that in order to make these sketches more viewable, the vertical axis presentation of resistance is not linear in Ohms but has been made proportional to log (1+Ohms).

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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Lip-Bu Tan, who has exposure to both chip design and chip manufacturing worlds due to his CEO stint at EDA powerhouse Cadence, is taking the reins of Intel after Pat Gelsinger was forced out by the Intel board a few months ago. Sally Ward-Foxton takes a closer look in her EE Times piece at what led to Tan’s appointment. She argues that his former leadership roles make him a suitable person to lead Intel, currently torn between its shrinking position in CPU design and its ambitious foray into the foundry business.

Read the full story at EDN’s sister publication, EE Times.

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