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The Controller Area Network (CAN) extended data-field length (XL) specification—which has been standardized for years—now has the first commercially available CAN XL transceiver. Texas Instruments has unveiled the TCAN6062 CAN XL transceiver, which supports payloads of up to 2,048 bytes per frame and data rates up to 20 Mbps.

The CAN XL transceiver ensures that priority messages are delivered first and on time, facilitating performance critical to humanoid robots, industrial robots, and human-machine interface (HMI) systems. This allows system designers to leverage CAN XL to exchange data rapidly and reliably in applications ranging from industrial robotics to automotive safety.

Figure 1 The CAN XL technology is promising to open the door to a new era of applications. Source: Texas Instruments

The new CAN XL transceiver is also backward compatible with CAN flexible data rate (FD) and CAN signal improvement capability (SIC) operations. This ensures a seamless migration and enables design teams to evolve existing designs incrementally without requiring a full redesign.

Next, while CAN XL is better and cheaper than CAN FD, it can also tunnel Ethernet. So, the CAN XL transceiver allows engineers to consolidate communication layers and use Ethernet in mixed-network architectures with Transmission Control Protocol/Internet Protocol (TCP/IP) tunneling. That facilitates efficient transfers of diagnostics, sensor data, control traffic, and over-the-air (OTA) updates on a single network.

Figure 2 The TCAN6062 CAN XL transceiver helps reduce ringing by up to 80% in complex networks, simplifying validation in high-node architectures. Source: Texas Instruments

CAN has been the backbone of industrial communications for decades. However, industrial systems are now generating and demanding more data than ever before. That’s because applications require fast, deterministic communication to synchronize motion control, sensor feedback, and diagnostic data. That, in turn, leads to new networking requirements, and as a result, engineers often accept system-level trade-offs to compensate for bandwidth constraints.

Dwight Byrd, GM of Interface Products at TI, claims that the TCAN6062 CAN XL transceiver bridges that gap. “It offers engineers a path to higher-bandwidth networks while maintaining the proven reliability CAN is known for.”

“As industrial systems become more intelligent and interconnected, what we ask of our networks continues to evolve,” Byrd added. “Engineers need more data, higher speeds, and greater flexibility, all without compromising performance or reliability.

TI’s networking technology managers are confident that CAN XL will open the door to a new era of applications, enabling systems to deliver higher performance at a reasonable cost. And here, TI has the first-mover advantage.

Related Content

• DIY CAN Transceiver
• Addressing immunity requirements for CAN transceivers
• Implementing the CAN Protocol in 3G Equipment Designs
• CAN: Network for Thousands of Applications Outside Automotive
• Signal Chain Basics: Industrial Market Transitions to 3.3V CAN Transceivers

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AI-driven demand underpins logic foundry and memory fab capacity constraints, leading to cost increases. Add tariffs to the mix, and Google and its competitors (not to mention end users) pay the price.

Last year’s Made By Google fall product launch event happened midday on August 20, moderated by Jimmy Fallon. Although I found value in the devices, software and services Google unveiled there, the un-traditional Tonight Show-styled format wasn’t particularly to my liking, a negative opinion shared by a notable number of others whose coverage I subsequently perused.

This year’s event, earlier today (August 12) as I write this, was once again celebrity-moderated, this time by Trevor Noah. But this time it took place in the evening, with the announcements notably preceding it; a flurry of blog posts had already hit Google’s website at 8 am MT, where I am. Feel free to draw your own conclusions as to the judged effectiveness (or, perhaps more accurate, lack thereof) of last year’s event And begging the question of why Google bothered doing this year’s event at all, save I suppose for the chance to see “live” demos, “softball” interviews and other such questionable-value content.

That said, the products themselves once again were notable, both in an absolute sense and relative to their prior-generation predecessors.

Befitting my engineering-dominated readership, I’ll as usual start out my coverage with the application processor, the Tensor G6, the intelligence nexus of the Pixel 11 smartphone series.

Power/performance balance (and profit) optimization

When I published last year’s event coverage, little was known at the time about the latest-generation Tensor G5 SoC save for its 3 nm TSMC fabrication source (a notable departure from Google’s longstanding foundry partnership with Samsung) and its eight-core CPU cluster mix: “one “prime” core, five mid-level ones, and two efficiency ones.” Beyond that, all Google was saying at the time was that, versus its Tensor G4 predecessor, it delivered the following updates.

• An up to 60% more powerful TPU
• A 34% faster on average CPU, and
• New security hardware

One year later, thanks to intensive developer engagement with the platform, we know much more about the Tensor G5 than we did before.

• CPU (8 total cores): 1x Arm Cortex-X4 at 3.78 GHz, 5x Arm Cortex-A725 at 3.05 GHz, 2x Arm Cortex-A520 at 2.25 GHz
• GPU: Imagination Technologies PowerVR (DXT-48-1536)

And now on “Day Zero” of the Tensor G6 era, what’s Google saying about it? Predictably, not much beyond another year’s worth of nebulous hand waving in comparison to the Tensor G5:

Tensor G6 features an upgraded CPU for 25% faster web browsing and 15% quicker app launches. Packing 50% more TPU compute and paired with the latest Gemini Nano model, Google Tensor G6 processes on-device AI tasks up to 3.5 times faster while using up to 3.5 times less energy.

But thanks to a leak sourced from embargoed media hands-on time with the Pixel 11 family, the following additional (and more specific) Tensor G6 specs, referencing Arm’s C-series cores, are also presumably accurate.

The Tensor G6 sports a seven-core configuration, with one prime “C1 Ultra” core clocked at 4.1GHz, four performance “C1 Pro” cores clocked at 3.4GHz, and two efficiency “C1 Pro” cores clocked at 2.65GHz. The GPU appears to be a PowerVR C-series variant with six compute units clocked at 1.3GHz.

One other silicon-related nuance also bears mention. Although, as previously mentioned, Google switched from Samsung to TSMC as its foundry source for the Tensor G5 last year, it stuck with Samsung’s Exynos cellular subsystem. This year, reportedly (although I haven’t yet seen definitive confirmation), this too has changed; Google’s supposedly now leveraging MediaTek M90 5G cellular IP.

Smartphone evolutionary modesty

Aside from the new colorways, you’d understandably likely be hard-pressed to discern a visual difference between Google’s latest handsets—the baseline Pixel 11, high-end Pixel 11 Pro and Pro XL, and book-style Pixel 11 Fold—and their 10th generation predecessors. Backs are once again all-glass. Displays are a bit brighter, and more scratch-resistant in the “Pro” variants. Camera bars are a bit more svelte (along with overall Fold thinness), and for “Pro” versions, embed a multicolor notification LED assembly surrounding the flash and branded “HiLight”. Particularly clever readers may have already noted the enhanced scratch-resistance association, since the notifications can only be seen when the phone is screen-down on a flat surface.

That all said, to the overall “supply constraints” theme of this writeup, I’ll point out that the Pixel 11 storage options now start at 256 GBytes; the entry-level 128 GByte variant of the Pixel 10 that I recently acquired isn’t offered this time around. In Google’s defense, Apple did the same thing a year ago with the iPhone 17 versus its iPhone 16 precursor, although in that earlier case the 2x capacity multiplier came for the same intro price as the 128 GByte prior-gen device.

This time the 256 GByte Pixel 11 price thankfully at least matches that of the year-ago 256 GByte Pixel 10, versus with an accompanying price increase as other smartphone suppliers are doing nowadays. Further to Google’s defense, note that a year ago any bill-of-materials cost increases were predominantly due to tariff impacts. Now, in contrast, supply constraints are additionally being felt to fuller effect. It’ll be curious to see how Apple handles both memory and TSMC foundry cost increases at its likely next-month announcement event; for one thing, the company will reportedly delay the launch of its baseline iPhone 18 until sometime next year.

In closing, at least for this section, one more memory-related twist bears mention. A year ago, I wrote, “Google also didn’t “hide” tariff costs by cutting RAM capacities (which would counterbalance its burgeoning AI ambitions, anyway)”. Well, this year they did. The lowest (256 GByte) storage capacity variants of the Pixel 11 Pro and Pro XL also have less RAM—12 GBytes vs 16 GBytes—than both their higher-capacity this-year siblings and same-capacity Pixel 10 predecessors, in the latter case with no accompanying generational price break. Admittedly, Google’s working hard on optimizing memory requirements for its on-device models, but still…

Watches and trackers

Last year’s Pixel Watch 4 was a notable update to its predecessor(s), as I wrote about at the time (although I’m still fiscally quite content with a recent update from my long-in-the-tooth first-generation wearable to “only” the Pixel Watch 3, more discussion of which I’ll save for another post another day). This year’s Pixel Watch 5 advancements are also more modest, notably including slight (~12%) CPU performance and battery capacity upticks along with an on-device AI-intended RAM upgrade from 2 GBytes to 3 GBytes, the latter leading to—you guessed it—an associated $50 price tag increment.

I’m not entirely sure why Google included a set of earbuds in its launch suite promo photo shown earlier this piece, as aside from a new Pixel Buds 2 (two years old) colorway option and pending firmware-delivered feature updates to both them and the Pixel Buds 2a (introduced a year ago), nothing’s new. Conversely, the most brand-new device released this week was the Pixel Tag, unsurprisingly supportive of Google’s Find My Device network and conceptually similar to (and a competitor of) Apple’s also-UWB-enhanced second-generation AirTag.

Hopefully, this wireless-connectivity enhancement suggests that we’ll be seeing broader support for UWB in both Google’s and other Android licensees’ handsets in the future. My biggest surprise here is that, unlike Motorola and other tracker manufacturers, Google didn’t also adopt an AirTag-clone form factor that would enable it to slot into the already sizeable and still steadily expanding AirTag ecosystem of luggage tags, stealth security setups and the like.

That’s what I’ve got for you today, folks. As always, please sound off with your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Made by Google 2026: This limited silicon-supply situation really sucks appeared first on EDN.

NoMIS Power has developed a 6.5-kV large-die SiC MOSFET that has demonstrated over 8 kV of blocking voltage, 90-mΩ on-resistance, and 55-A drain current. Based on the planar SiC technology used in its 3.3-kV devices, the 6.5-kV MOSFET extends the technology into the high-voltage class and provides a foundation for the company’s planned 10-kV MOSFETs and 20-kV SiC IGBTs.

NoMIS is sampling the 6.5-kV SiC MOSFET to U.S.-based customers, with standard-production devices scheduled for Q4 2026. The company plans to expand the 6.5-kV portfolio with additional on-resistance variants, small-die MOSFETs, hybrid junction-barrier Schottky FETs (JBSFETs), and standalone diodes for applications including HVDC power transmission, solid-state transformers, pulsed-power systems, rail traction, and megawatt-scale EV charging

The 6.5-kV devices build on the company’s 3.3-kV SiC MOSFET family, which is already in production, while 10-kV and higher-voltage MOSFETs, diodes, JBSFETs, and SiC IGBTs are in development.

For more information, visit the NoMIS Power Semiconductors and Modules webpage.

NoMIS Power

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NEO.AI is a memory platform from NEO Semiconductor that overcomes SRAM and DRAM scaling limitations in AI memory systems. As part of the platform launch, NEO Semiconductor is introducing its X-SRAM technology for on-chip memory in GPUs and AI processors and reporting its latest progress on 3D X-DRAM, a high-capacity memory technology for HBM.

By replacing conventional six-transistor SRAM with a two-transistor architecture, X-SRAM enables up to 5 times higher memory density to support 1–2 GB of on-chip memory, according to NEO. The technology maintains SRAM-class performance and is compatible with advanced nanosheet CMOS processes. It also provides a path toward future monolithic 3D X-SRAM implementations.

Built on 3D NAND manufacturing processes, 3D X-DRAM delivers up to 10 times higher memory capacity than conventional DRAM, according to NEO. Successful proof-of-concept validation demonstrates its potential as a scalable and manufacturable solution for next-generation HBM.

For more information, visit the NEO X-SRAM webpage.

NEO Semiconductor 

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The KTS1630 5-A eFuse from Kinetic Technologies protects sensitive electronics against overcurrent, short circuits, and thermal faults. It is designed for consumer and industrial systems operating from 5-V and 12-V power rails, helping improve system safety and reliability. By detecting overcurrent conditions typically within 100 ns, the device can isolate faults before they can damage downstream circuitry.

An integrated MOSFET with a typical on-resistance of 31 mΩ from VIN to VOUT helps reduce conduction losses while supporting operation across a 4.5-V to 18-V input range, with a 20-V absolute maximum rating at VIN. The KTS1630’s adjustable 1-A to 5-A current limit allows designers to set the protection threshold for specific loads rather than relying on a fixed current-limit threshold. The eFuse also includes a dedicated control output for an external reverse-blocking MOSFET that prevents reverse current when the input supply is removed or the output voltage exceeds VIN.

A programmable output slew rate controls inrush current during startup, helping prevent input-supply droop, connector stress, and unintended system resets when large capacitive loads are connected.

Supplied in 10-pin, 3×3-mm VDFN packages, the eFuse is available in both auto-retry and latched-off versions.

KTS1630 product page 

Kinetic Technologies  

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A high-speed USB-to-UART bridge, MaxLinear’s Carmel MxL81434 supports console access and infrastructure management in AI data centers and hyperscale cloud environments. The highly integrated device includes USB 2.0 High-Speed (480 Mbps) connectivity, four independent UART channels operating at up to 15 Mbps each, an I2C master, and 32 GPIOs for server and rack-scale management designs.

Carmel extends MaxLinear’s USB-to-UART portfolio, increasing the maximum UART data rate to 15 Mbps and doubling the transmit and receive FIFO size. The 1024-byte FIFOs help sustain high throughput and reduce host processor overhead, while the integrated I2C master and 32 GPIOs consolidate management, monitoring, and debugging functions. Low-latency console connectivity supports faster system bring-up, recovery, diagnostics, and provisioning.

The USB-to-UART bridge provides ±15-kV HBM ESD protection for demanding server and data center environments.

Samples of the Carmel MxL81434 are expected to be available Q4 2026.

MaxLinear

The post Four-channel USB-UART IC boosts server management appeared first on EDN.

ROHM is offering the RTD-EVK-G2 evaluation kit, based on its second-generation terahertz-wave oscillation device. Built using resonant tunneling diodes (RTDs), the device delivers up to 40 µW of output power, four times that of the first-generation product. The kit enables companies and research institutes to evaluate terahertz-wave oscillation and detection for applications such as nondestructive testing, medical imaging, high-resolution radar sensing, material identification, and high-speed wireless communications.

Unlike conventional terahertz systems, which are costly and require large equipment, the RTD-EVK-G2 includes a sample device, cable, and evaluation board for evaluation in space-constrained settings. The terahertz device maintains the same 0.5×0.5-mm chip size and 4.0×4.3-mm PLCC package as the first-generation component. Compared with other terahertz generation methods, the RTD approach generates less heat and consumes less power.

Sales of the RTD-EVK-G2 kit are scheduled to begin in August 2026 at $3,300 per set. Contact a sales representative or visit the Rohm contact page for more information. Purchase of the evaluation kit requires signing a non-disclosure agreement with Rohm.

Rohm Semiconductor 

The post RTD terahertz evaluation kit quadruples output appeared first on EDN.

This circuit enables you to generate remote control PWM test signals with a (very) generic (and cheap) chip.

A recent Design Idea illustrated the application of an interesting chip (the LTC6992) to remote control (RC) PWM test signal generation. Being familiar with neither the application nor the chip, and despite being a (very) old dog, I decided to try to learn a new trick or two.  So I took a trip Through the Looking Glass into the LTC6992 datasheet.  Here’s what I found there.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Firstly, the LTC6992 is a very capable and consequently rather complex device.  Inevitably its datasheet is similarly complex and, frankly, more than a little confusing.  Which, of course, might be due to that old dog factor!  But moving along…

Secondly, it’s not inexpensive: ~$6 in singles, plus it needs an external precision regulator that adds another buck.

But worsetly (??? Ed.), it happens that the RC PWM application involves rather low, only 5% to 10%, PWM duty cycle numbers.  When you combine that with the LTC6992 datasheet’s specification (on page 4) of +/-3% typical duty cycle error, it becomes clear the LTC6992 is unlikely to be very happy (or accurate) in this application.

So I decided to work toward a Design Idea that would be more familiar (and friendly?), not needful of (too many) extra external components, (mainly) more accurate, and hopefully a bit cheaper.  Figure 1 shows what my labors achieved.

Figure 1 This Design Idea leverages a LMC555 as a variable duty cycle (1ms to 2ms = 5% to 10%), constant frequency (20ms = 50Hz) PWM oscillator.  Timing is ratiometric and therefore independent of V+ so no external voltage regulator is needed.

How it works is (roughly) sketched in Figure 2’s timing diagrams.

Figure 2 The PWM oscillation cycle alternates between the Threshold pin for the duration of the 1ms to 2ms ON halfcycle is adjusted by R1, and the Trigger pin for the 18ms to 19ms OFF halfcycle. C2 > C1 to compensate for D1 forward drop.

PWM duty cycle = (R2 + R1+)/(R1 + R2 + R3) = 5% to 10%.
Oscillation frequency = 1/(loge(3)C1(R1 + R2 + R3)) = 50Hz independently of R1 setting

D1 recharges C2 during the PWM on interval.  Z1 limits the output amplitude to TTL-safe levels. And given that LMC555s can be had for about a dollar in singles, I’d say the hoped-for price point box was also checked.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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The post Cheap and cheerful LMC555 RC PWM pulse generator appeared first on EDN.

AI has transformed the semiconductor industry’s pressure points. The conversation is no longer focused solely on designing faster chips. Instead, manufacturers are racing to ensure every part of the supply chain—from silicon wafer production to advanced packaging to global logistics—can support an unprecedented wave of demand.

This shift means evaluating more than process nodes and transistor density. For electronics engineers, supply chain resilience, packaging availability, and manufacturing capacity increasingly influence component selection, product schedules, and long-term design decisions.

AI changing wafer demand

The scale of that demand became clear in the second quarter of 2026, when global silicon wafer shipments reached a record 3,573 million square inches, up 7.4% year over year. AI servers, high-bandwidth memory (HBM), advanced logic, automotive electronics, and industrial semiconductors are all contributing to this wafer demand.

The current cycle differs significantly from previous semiconductor rebounds. After demand being shifted from smartphones or PCs, AI infrastructure is driving simultaneous growth across advanced logic, memory, and power devices.

According to SEMI, AI infrastructure continues to drive demand for leading-edge logic and memory devices, while the rapid expansion of hyperscale data centers is also increasing demand for power management ICs. As industrial markets recover and inventory levels normalize, semiconductor demand is becoming more balanced across multiple end-use sectors.

The impact extends well beyond cloud infrastructure. Consumer devices, such as smartphones and tablets, continue relying on advanced logic and memory, while automotive electronics for ADAS controllers, battery management systems, and zonal computing platforms are consuming larger volumes of semiconductors. Networking switches, 5G base stations, industrial PLCs and robotics controllers are also increasing silicon content, sustaining demand across multiple process nodes rather than only the most advanced technologies.

The broader demand profile has made supply planning more complex for design engineers. While AI accelerators rely on advanced process nodes, many supporting components—including power management ICs (PMICs), microcontrollers (MCUs), connectivity chips, and analog devices—continue to be manufactured on mature nodes. Modern electronic systems depend on both, making balanced capacity expansion critical across the semiconductor ecosystem.

300 mm fabs remain a priority

Silicon remains the primary raw material for manufacturing chips. After being refined into wafers, its electrical properties can be precisely engineered through controlled doping, making it the foundation of the transistors used in AI processors, memory devices, automotive electronics, and countless other semiconductor applications.

The semiconductor industry’s expansion continues to center on 300-mm wafer production because larger wafers enable manufacturers to produce more chips per fabrication cycle, improving throughput and reducing the cost per die. Those efficiencies make 300-mm fabs the preferred choice for advanced logic, memory, and other high-volume semiconductor devices.

That strategy is evident from the recent investments. GlobalWafers is preparing the next phase of expansion at its advanced 300-mm wafer facility in Sherman, Texas, in response to growing customer demand for domestically produced silicon wafers. The plant is the first advanced 300-mm silicon wafer facility built in the United States in over two decades, underscoring broader efforts to strengthen domestic semiconductor supply chains.

Simultaneously, foundries such as TSMC continue expanding advanced fabrication capacity to support AI processors, high-performance computing, and automotive semiconductor demand, highlighting the industry’s broader push to scale leading-edge manufacturing.

For electronics engineers, continued investment in 300-mm manufacturing should improve long-term wafer availability. However, securing leading-edge devices will also increasingly depend on how quickly packaging, testing, and logistics infrastructure expand alongside wafer production.

Logistics becoming the next constraint

Higher wafer output does not automatically translate into higher semiconductor availability. Modern semiconductor manufacturing depends on tightly synchronized movement of raw wafers, specialty gases, ultrapure chemicals, photomasks, lithography equipment, and finished devices across multiple continents. A disruption affecting any stage can slow production despite available fab capacity.

Transportation also introduces reliability challenges. Vibration during shipping can generate electrostatic charge through tribocharging, increasing the risk of electrostatic discharge (ESD) for sensitive semiconductor components if they are not properly protected. As wafer volumes continue rising, ESD-safe packaging and handling become increasingly important to ensure that devices arrive ready for assembly and deployment.

Advanced packaging has become another pressure point. AI processors increasingly rely on chiplets, 2.5D integration, HBM stacks, and sophisticated substrate technologies. Even if wafer fabrication keeps pace, shortages in packaging capacity or substrate availability can delay final product shipments.

Engineers designing products with leading-edge processors should evaluate supply chains beyond wafer availability. Long lead times for advanced substrates or packaging services can delay board assembly completion, even when silicon is available. As a result, packaging partners, OSAT capacity, substrate suppliers, and logistics resilience have become critical considerations alongside device specifications and performance.

Building resilience in future designs

Recent supply chain disruptions have encouraged semiconductor manufacturers to diversify production geographically while increasing regional investments in wafer fabrication, materials, and packaging. Government-backed semiconductor initiatives across North America, Europe, and Asia are helping expand domestic manufacturing ecosystems. These efforts reduce dependence on single-region supply chains while improving resilience against geopolitical and transportation risks.

The implications extend into product architecture. Selecting components with multiple qualified manufacturing sources and maintaining flexibility across process nodes can reduce exposure to future capacity constraints.

The record wafer shipment figures suggest upstream silicon availability is improving. However, transforming those wafers into finished electronic systems increasingly depends on synchronized investments across fabrication, advanced packaging, materials handling, and global logistics.

Keeping pace with growing AI demand will require more than expanding silicon wafer manufacturing. Engineers must also account for packaging capacity, logistics resilience, and supplier readiness throughout the design process.

Emily Newton is editor-in-chief of revolutionized.com.

 

 

 

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• The 300-mm Era Begins
• Inside IBM’s 300-mm fab
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• One-stop advanced packaging solutions for chiplets

The post Record high wafer shipments. Can fabs keep pace? appeared first on EDN.

Analog and mixed-signal design at sub-5 nm nodes has reached a threshold where deterministic corner-based signoff and brute-force Monte Carlo can no longer simultaneously satisfy convergence speed, tail-yield condense, and engineering interpretability.

This paper examines QUINSIM’s Analog Uncertainty-Aware Design (AUAD) platform—a physics-informed, surrogate-driven uncertainty quantification engine that wraps existing SPICE and TCAD simulators as black boxes.

We characterize the mathematical architecture (sparse polynomial chaos expansion, R-Vine copula process modeling, Sobol variance decomposition, and efficient global optimization), quantify performance across six canonical analog verification benchmarks (SRAM, LNA/VCO, SAR ADC, automotive power IC, TCAD/GAA nanosheet, and timing closure), and analyze the structural transformation AUAD imposes on analog design economics, organizational workflows, and EDA ecosystem dynamics.

We conclude that AUAD is not an incremental acceleration of existing flows; it constitutes a new design epistemology in which uncertainty is a first-class object—characterized, propagated, decomposed, and optimized—rather than a late-cycle verification penalty.

Analog variability crisis at advanced nodes

Analog and mixed-signal design at sub-5 nm nodes has entered a regime where the statistical toolkit inherited from the 1990s—Gaussian corner models and brute-force Monte Carlo—can no longer simultaneously satisfy industrial signoff requirements. Three overlapping crises converge: non-Gaussian process physics, exponentially expensive tail convergence, and opacity of failure attribution. Together they constitute the analog variability crisis, a condition in which the standard toolkit cannot adequately address tail-yield confidence at acceptable engineering cost.

The physics of non-Gaussian variation

Classical statistical IC design rests on a Gaussian assumption inherited from diffusion-dominated transistor physics of the 1980s. In that regime, bulk MOSFET threshold voltage Vth was well-approximated as normally distributed, making a standard deviation σ extracted from wafer data a sufficient design lever. At sub-10 nm nodes, this approximation breaks down for fundamental physical reasons.

Random discrete dopant (RDD) fluctuations produce heavy-tailed, skewed Vth distributions whose kurtosis significantly exceeds the Gaussian value of three. Line-edge roughness (LER) in EUV-patterned FinFET fins creates systematic spatial correlations between adjacent devices that no single-transistor Gaussian model can express. FDSOI back-gate coupling creates strong nonlinear co-dependence between Vth and DVT0W parameters that Gaussian copulas severely underestimate.

The consequence is stark: every PDK σ value that rests on a Gaussian marginal is a physically incorrect model for the circuit’s actual failure space. Corner models compound the problem by treating process parameters as independently varying—an assumption falsified by the correlated etch and deposition physics of modern advanced nodes. A corner labeled “SS” (slow-slow) is a specification convenience, not a probabilistic claim about the failure boundary.

The convergence economics of deep-tail analysis

Monte Carlo convergence follows the 1/√ N law: to halve the estimation error on a yield metric, four times as many simulations are required. For SRAM static noise margin (SNM) qualification at 5σ—the product-level target for leading-edge memory—direct Monte Carlo requires on the order of 107 SPICE evaluations.

At a conservative 3 seconds per simulation on modern hardware, this translates to approximately 347 days of wall-clock compute per circuit per operating corner. Modern SRAM products span multiple corners, temperatures, and supply voltages, multiplying this burden by a factor of 10–50.

The attribution gap

Perhaps the least-discussed failure of conventional flows is epistemic. Monte Carlo can answer “what is the yield?” but not “which parameters are responsible, and by how much?” Answering the latter requires a highly-designed factorial experiment or auxiliary regression—both expensive and approximate.

In a 57-parameter FinFET PDK, attributing yield loss to a specific root cause without attributing yield loss to a specific root cause without analytical sensitivity tools means teams spend weeks on iterative knob-turning that is effectively uninformed trial and error.

This attribution gap directly inflates design cycle time. When the nominal design fails Monte Carlo signoff without variance decomposition, the team must rely on engineering intuition and costly re-simulation campaigns to identify root causes—a process that can consume months at advanced nodes.

Figure 1 In simulation budget comparison, see QUINSIM sPCE (~350 calls) vs. direct Monte Carlo (~10,000 shown; 107 for full 5σ) for a 57-parameter 5 nm FinFET SRAM SNM characterization. Source: QUINSIM

Why corners cannot patch the gap

For uncorrelated Gaussian parameters, an SS corner is geometrically remote from the actual 6σ failure hyperplane in a high-dimensional parameter space. For non-Gaussian parameters with nonlinear correlations, the SS corner may not even represent the worst-case direction—the actual failure mode may lie in a cross-parameter interaction that no PVT corner captures.

AUAD: Architecture and mathematical foundations

QUINSIM’s Analog Uncertainty-Aware Design platform is structured as a four-stage pipeline that treats the existing SPICE or TCAD simulator as an opaque black box—preserving compatibility with Cadence Spectre, Synopsys HSPICE, Mentor Eldo, and Synopsys Sentaurus without modification. As shown in Figure 2, uncertainty inputs are characterized from foundry data; adaptive sampling builds a sparse surrogate; sensitivity and yield surfaces are extracted analytically; and robust optimization acts directly on the uncertainty-aware objective.

Figure 2 In AUAD four-stage pipeline, each stage is analytically connected to the next: foundry data flows through copula characterization into sPCE training, then into zero-cost Sobol decomposition, and finally into EGO-based robust optimization—all without a single additional SPICE call beyond the initial adaptive sample set. Source: QUINSIM

Stage 1: Non-Gaussian joint distribution characterization

Real foundry measurement data for parameters such as Vth, Tox, Leff, and inter-device mismatch do not conform to Gaussian distributions. QUINSIM fits marginals using non-parametric kernel density estimation (KDE) or parametric heavy-tail distributions (Student-t, skew-normal). Joint dependence between parameters is captured using R-vine copulas—pair-copula constructions that model arbitrary bivariate relationships in a recursive tree structure, capturing nonlinear co-dependence that Gaussian or elliptical copulas systematically miss.

The Rosenblatt transformation maps correlated, non-Gaussian samples into independent uniform (then Gaussian) space where Polynomial Chaos Expansion is analytically valid. This is the technical key that makes sPCE applicable to real foundry data with correlated, non-Gaussian parameters, a capability absent from conventional Gaussian-input PCE tools.

Stage 2: Sparse polynomial chaos expansion surrogate

The circuit performance metric Y (SNM, ENOB, NF, efficiency…) is approximated as a polynomial functional of standardised process inputs Z:

Physical sparsity—circuits respond strongly to a small subset of parameters even in 50+ dimensional PDK spaces—combined with active-learning sample placement concentrates 100–500 simulator calls in the regions that maximally reduce surrogate error. The trained surrogate then evaluates in microseconds, enabling post-hoc Monte Carlo with 106–108 samples at negligible additional cost.

Stage 3: Analytical Sobol sensitivity and yield surface extraction

Global sensitivity indices—Sobol first-order and total-effect—are computed analytically from the PCE coefficients at zero additional simulation cost:

Figure 3 Example Sobol-derived metric importance ranking across six performance dimensions (efficiency, output swing, peak current, power factor, THD, EMI) for a power converter design. PF and Eff dominate the variance budget, immediately directing robust design effort to the parameters that matter most. The ranking costs zero additional simulations. Source: QUINSIM

Stage 4: Efficient global optimization (EGO)

With the surrogate trained and sensitivity indices computed, QUINSIM applies efficient global optimization (EGO) to maximize yield over the design parameter space. EGO uses a Kriging (Gaussian process) meta-model of the yield surface together with an expected improvement (EI) acquisition function: EI(x) = E[max(f(x) − f*, 0)]. This Bayesian optimization approach locates yield-maximizing design parameters in fewer than 200 evaluations for 50+ dimensional spaces—unachievable with classical gradient-based methods when the yield surface is non-convex or multimodal.

Benchmark use cases: Demonstrating AUAD impact

QUINSIM has constructed six canonical AUAD benchmarks spanning memory, RF, data conversion, automotive power electronics, and device-level TCAD calibration. These demonstrators collectively define the platform’s technical scope and establish its performance claims against reference instances from published literature and ICCAD benchmarks.

Figure 4 In this 6T SRAM bit-cell schematic at 5-nm FinFET, static noise margin (SNM) and write-margin jointly depend on all six transistors’ Vth, Tox, Leff, and mismatch. QUINSIM’s sPCE characterizes the full 5σ SNM failure surface from 350 adaptive Spectre calls, versus 107 for direct Monte Carlo. Source: QUINSIM

SRAM bit-cell: 5σ SNM in 350 simulations

The canonical AUAD challenge is SNM qualification for 5 nm 6T/8T SRAM. QUINSIM constructs a 57 parameter sPCE surrogate using 350 adaptive Spectre calls, recovers the full SNM probability density function including the 5σ tail, identifies three dominant failure drivers analytically (Tox, Vth_PMOS, Leff), and completes in under 4 hours on standard workstation hardware. The Sobol decomposition reveals Tox alone accounts for 38% of SNM variance—enabling targeted process control recommendations to the foundry that would be invisible to any Monte Carlo approach.

RF LNA/VCO: Capturing bimodal failure distributions

In 28/22 nm FDSOI, QUINSIM employs a Student-t copula to model the Vth–DVT0W co-dependence from back-gate coupling. The result is accurate prediction of a bimodal noise-figure distribution—an artifact of nonlinear coupling that Gaussian-assumption tools miss entirely. QUINSIMʼs design centering identifies a 15% yield improvement and locates the real 6σ worst-case operating point. Multimodal output distributions imply correlated input failure modes that only copula-based process models can resolve.

Figure 5 In FDSOI LNA and the resulting bimodal noise-figure distribution, the back-gate voltage VBG creates nonlinear Vth–DVT0W dependence. QUINSIM’s Student-t copula reveals a second failure mode (Mode 2) that a Gaussian process model misses, a production-impact failure invisible to conventional statistical signoff. Source: QUINSIM

High-speed SAR ADC: 150-parameter ENOB characterization

ENOB degradation in a SAR ADC arises from a correlated combination of capacitor mismatch, comparator offset, jitter, and reference noise. QUINSIMʼs structured high-dimensional sPCE handles 150 correlated parameters from 600 adaptive simulations, delivering the full ENOB probability density function and per-specification tail failure probability in 8 hours.

An equivalent Monte Carlo campaign spanning this 150-parameter space to 6σ confidence would require 3–4 weeks. The surrogate’s full distributional output also exposes ENOB distribution shape—skew, kurtosis, multi-mode structure—that pass/fail counting cannot reveal.

Automotive power IC: Joint process-temperature surrogates

Automotive-grade ICs (AEC-Q100 Grade 0) must operate from −40°C to +175°C. QUINSIM extends the uncertain parameter space to treat temperature as a continuous uncertain dimension, building joint process-temperature surrogates that deliver 100× cost reduction relative to a conventional Monte Carlo × PVT sweep. This is particularly relevant for SiC power stages, gate drivers, current sensors, and high voltage control loops, where tail-yield and reliability must be jointly evaluated across the full operating envelope, not at isolated corners.

TCAD/GAA nanosheet: Bayesian process calibration in 48 hours

TCAD calibration for a new process node currently requires 2–4 weeks of manual deterministic iteration to fit compact model parameters (BSIM-CMG, PSP) to measured I-V characteristics. QUINSIMʼs Bayesian calibration engine applies active learning to TCAD simulation scheduling, fits a posterior distribution over the full set of physical model parameters rather than a point estimate, and propagates that posterior uncertainty through the compact model extraction chain into a UQ-aware PDK (UQ-PDK). The result: 48-hour calibration cycles with honest uncertainty bounds on every PDK parameter.

Capabilities unlocked by AUAD

Beyond benchmark-level performance numbers, AUAD unlocks capabilities that are qualitatively unavailable within the Monte Carlo paradigm regardless of the compute budget applied.

Analytical variance budget decomposition

For a 57-parameter PDK space, conventional Monte Carlo can determine that yield is 97.2%—but not which parameters explain the 2.8% failure variance. QUINSIMʼs Sobol decomposition provides a ranked list of first-order and total-effect indices for every process parameter, computed analytically from sPCE coefficients at zero simulation cost. This transforms failure analysis from “simulate more” to “fix these three parameters in this priority order.”

Full probability density output instead of pass/fail counting

Surrogate-based UQ produces the full PDF of any circuit metric as a live design object. For a SAR ADC, this means designers see not just “mean ENOB = 11.2 bits, σ = 0.15 bits” but the complete distributional shape—whether it’s symmetric, heavy-tailed, or bimodal. This changes specification verification from a Gaussian-approximation exercise to a physics-honest probability assessment.

Robust design centering and optimization via EGO

EGO-based robust optimization acts on the yield surface, not the nominal performance surface. A design point that is optimal in nominal performance may sit on a steep yield cliff; a slightly sub-optimal nominal design may command a wide, flat yield basin. AUAD makes this trade-off visible and optimizable: in the FDSOI LNA benchmark, EGO-guided centering recovered 15% yield improvement that was invisible to nominal optimization. In timing-closure benchmarks, robust optimization produced higher shipping frequency with tighter but better-justified margins than guard-banding.

Partner-ready traceability and auditability

QUINSIMʼs analytical UQ framework produces structured, reproducible outputs: specific PCE coefficients, Sobol index tables, yield surface plots, failure-mode rankings—all derived from a documented mathematical procedure. For foundry partnerships, IP qualification packages, and AEC-Q100 automotive compliance dossiers, auditability of the statistical analysis is increasingly a contractual requirement. AUADʼs analytical traceability directly satisfies this requirement in a way that a random-seed-dependent Monte Carlo run cannot.

The irreversible transformation of analog IC design

AUAD is not a feature addition to existing EDA flows. It constitutes a structural transformation of how analog design decisions are made, justified, and communicated. Once a design team inhabits an environment where uncertainty is analytically characterized and continuously actionable, the prior workflow—simulate, margin, and iterate—becomes evidently inferior and institutionally difficult to defend.

From “simulate and margin” to “characterize, rank, optimize, explain”

The existing design-verification loop treats Monte Carlo as a late-stage checksum applied after nominal design completion. When the gate fails, the team iterates blindly without analytical guidance. In an AUAD workflow, the uncertainty model is active from the first design iteration: parameters are characterized from foundry data, the surrogate is trained after 100–500 simulation calls, and Sobol rankings immediately direct design effort. The loop compresses from months to days not because the simulator runs faster, but because engineering judgment is guided by quantitative attribution rather than intuition.

Figure 6 In traditional simulation-centric design loop (red) vs. AUAD design loop (blue/green), the structural difference is that AUAD delivers actionable attribution at every stage. Where the traditional loop requires months of blind re-simulation on signoff failure, AUAD’s Sobol-guided EGO reaches tape-out readiness in days. Source: QUINSIM

Economic consequences for design organizations

The commercial implications of a 1000× simulation reduction extend beyond throughput. Fewer SPICE simulations mean fewer licensed EDA seat-hours consumed, directly reducing the variable cost of advanced-node verification.

Faster yield diagnosis compresses design cycles currently measured in 18-24 months for leading-edge analog. Better yield prediction reduces unnecessary margin padding, and in volume production, even 1–2% yield recovery at advanced nodes translates to tens of millions of dollars in recaptured wafer value per year. QUINSIM positions these not as incremental improvements but as step-function changes in the economics of analog design.

EDA ecosystem dynamics: The intelligence layer

QUINSIMʼs black-box simulator wrapper positions it as an intelligence layer on top of, not in competition with, the SPICE simulation cores of Cadence, Synopsys, and Siemens EDA. Incumbents can embed the UQ engine as a differentiated variation-analysis module without displacing their core circuit simulation products. The roadmap QUINSIM publishes explicitly names a “Cloud SaaS, UQ-PDK marketplace” and positions the platform as an acquisition target in the €100–200M range—a signal of deliberate ecosystem positioning rather than standalone scaling.

Foundries and IP providers face an analogous opportunity. A UQ-PDK that exposes calibrated non-Gaussian marginals, copula dependence models, and Bayesian parameter posteriors is qualitatively richer than a conventional σ-table, enabling customers to achieve better first-silicon yield with fewer iterations—a tangible competitive differentiator in a market where design starts are competed on tool quality.

The transformation is irreversible

The historical pattern in EDA adoption suggests that once a design team experiences analytical yield attribution—knowing which parameters are responsible for yield loss and by how much, derivable in hours—returning to uninformed Monte Carlo iteration is institutionally unacceptable. The same dynamic played out when formal verification replaced simulation-only digital signoff, and when place-and-route tools supplanted manual floorplanning.

AUAD represents the analog equivalent of that transition: a shift from a compute-intensive empirical paradigm to a mathematically structured, interpretable, and continuously optimizable uncertainty framework.

The chips shipping in 2029 and beyond will be designed by teams who characterize, rank, optimize, and explain the uncertainty in their analog blocks from the first simulation run. Those teams will converge faster, yield higher, and signoff with tail-probability confidence that today’s Monte Carlo paradigm can not match. QUINSIM AUAD is the platform enabling this transition today.

Christophe Bianchi is CEO and founder of QUINSIM.

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The post Analog uncertainty-aware design: How it replaces Monte Carlo with certifiable yield intelligence appeared first on EDN.

A novel switch architecture caters to extended battery range coupled with robust protection and diagnostic strategies.

For automotive control units, the smart output switches operating contactor coils, lamps, solenoids, PTC (positive temperature coefficient) heater coils and the like form an indispensable “last mile” interface to the external world. Legacy solutions available from global automotive semiconductor companies suffer from the following weaknesses:

• No off-the-shelf power switch IC is currently available beyond 24 volts, whereas upcoming vehicle architectures are envisioning 48 VDC or higher buses to reduce the weight of associated copper wiring.
• They consume a minimum of two interface CPU pins per switch; one for the command output and another for the status input.
• “Short to power bus” protection is based on current limiting followed by a thermal trip, in the process often exceeding the absolute maximum junction temperature prior to the actual tripping event.
• The on-chip power device often has limited overvoltage and inductive transient capabilities, requiring external protection components.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The circuit in Figure 1 illustrates a solution that resolves all of these issues.

Figure 1 This design idea is primarily intended to depict a novel switch architecture that can cater to extended battery range coupled with robust protection and diagnostic strategies. It also uses only a single CPU pin-per-switch, as opposed to two CPU pins for legacy architectures. The load coil can be typically rated as a 48V DC, 122 mA contactor coil used for EV/HEV circuits for a 48 volt bus. A typical 12 volt automotive relay coil may draw 95 mA, while a 24 volt version can draw approximately 68 mA.

In this example circuit:

• Q1 = MMBTA 92-q
• Q2 = 2N2222
• Q3 = MMBTA 42-q
• D1,D2 = 1N4004
• D3 = 1N4148
• R1 = 47K ohm
• R2,R3 = 47K ohm
• R4 = 2.2 ohm
• R5 = 10K ohm
• R6 = 1K ohm
• C1 = C2 = 0.1 microfarad, 25 volts

The selection of components, resistor values etc. may need to be tailored to address the expected range of application loads, along with CPU and other logic voltage/current characteristics.

The heart of the circuit is the Q1-plus-Q3 latch. Q2 acts as constant current limit that prevents momentary thermal runaway that would otherwise destroy Q1 during a “short to power bus” event. In automotive application, a service engineer or production technician might accidentally short-circuit the output point (Q1 collector) to the power bus. Automotive norms dictate that the power switch must incorporate built-in short circuit protection to cover this and other scenarios.

When the CPU wants to switch on the load, it issues a rising-edge command through the C1-plus-R1 edge trigger circuit to the Q1-plus-Q3 latch. This command sets the latch output to its active low level, thus turning on the contactor coil load. The CPU pin can now reconfigure itself as a diagnostic status input, since the Q1-plus-Q3 latch now self-sustains at the “on” state without needing any further base current assistance from the CPU. The CPU pin, now acting as a diagnostic input, reads a “logic high status”, indicating that the latch output is healthy and powering the load as intended.

In case of an accidental short to power-bus event—in other words, the load coil facing a short circuit across itself—Q3 being a PNP transistor switches off due to its base emitter circuit in effect getting short-circuited (Figure 2). This “resets” the latch by turning off Q1, also saving it from the over-current condition.

Figure 2 This short-circuit protection field performance plot of the circuit shows its near-instantaneous trip mechanism for the output switch, which resets the associated latch.

Transistor Q2 limits the momentary rise in Q1 current at the short-circuit instant to a value of around 318 mA (700 mV/2.2 ohms). This abrupt current limit saves Q1 from destruction due to a thermal runaway before Q3 transistor’s turn-off can safely place it in an “off” state. The CPU diagnostic status input pin now reads a “logic low” level indicating that the latch is turned off, due to a short circuit fault at the output. Capacitor C2 provides ESD protection, along with noise interference filtering that may accidentally operate the latch.

Whenever the CPU needs to issue a turn-off command to a latched switch which is in an “on” state, it presents a logic low level at its output interface pin. This low-level voltage turns off the latch through diode D1. Diode D6 and resistor R1 suppress the inductive flyback transient. Diode D1 may be replaced by a suitable Schottky diode to ensure a robust turn-off of the latched switch.

Unlike legacy smart switch solutions, this circuit does not depend on thermal trip-based protection, hence its junction temperature remains absolutely stable. At the time of a short circuit, there will be an instantaneous current-limited spike. The architecture unburdens software from repeatedly monitoring and turning off the smart switch for short-circuit protection (in order to ensure a safe turn-off even before a thermal trip) as may be required for a legacy switch architecture. It instead repartitions the instant short-circuit protection task to the hardware trip circuit, leaving software to monitor and detect the the short-circuit event on an as-possible basis without worry about any real-time protection deadlines.

The circuit can alternatively be implemented in integrated circuit (IC) form, at least to a degree. A power switch element may alternatively be located at and connected to the IC from the outside if it can’t be packaged within the chip, which can still integrate the remainder of the low current driving, protection and diagnostic logic.

Vishwas Vaidya is a graduate of the Indian Institute of Technology in Delhi, India. Currently, he is self-employed as an engineering consultant and industry faculty member in the field of embedded systems for global automotive clients and high-repute academic institutions. Vishwas’ articles and research reports have appeared in many worldwide engineering publications.

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The post Automotive low side output switch architecture suitable for 8 to 48 volt buses and beyond appeared first on EDN.

Predictive, generative, and agentic AI are not successive generations. They coexist inside enterprise systems, each placing fundamentally different demands on the underlying compute infrastructure.

• Predictive AI classifies, forecasts, and detects within defined boundaries (for instance, identifying a tumor or detecting fraud). GPUs and fixed-function accelerators handle these bounded workloads efficiently.
• Generative AI broadened this scope to text, code, and reasoning. Processor designers responded with a race for floating-point throughput, memory bandwidth, and high-speed interconnects under the assumption that inference was relatively simple: accept a prompt, run the model, and emit tokens.
• Agentic AI breaks that model-centric paradigm. A single task is partitioned among cooperating agents—one retrieves data, another analyzes it, a third writes code, and a fourth verifies policy compliance. The workload shifts from pure matrix multiplication to planning, branching, scheduling, synchronization, and repeated tool execution.
• Enterprise AI applies predictive, generative, and agentic capabilities to real-world business problems using proprietary data, strict access controls, and strict governance. It’s not merely a larger version of consumer generative AI; it is a distinct operating environment that fundamentally reshapes system architecture.

The enterprise context layer

A consumer chatbot relies primarily on pretraining weight memory and optional web search. An enterprise system must operate against information absent from pretraining: engineering specifications, financial ledgers, manufacturing logs, code repositories, and regulatory filings. It must simultaneously enforce who is authorized to see that information, which actions are permitted, and how the interaction is logged for audit.

To accomplish this, enterprise systems combine foundation models with retrieval-augmented generation (RAG), vector databases, knowledge graphs, identity management, policy engines, and workflow orchestration. Collectively, this forms an enterprise context layer, an architectural abstraction whose role is to retrieve relevant organizational knowledge, apply access rules, and ground model output in current operational facts.

An AI software stack is used to manage AI enterprise workloads and reshape AI system architectures. Source: Author

As a result, the question moves from “What does the model know?” to “What does the organization know, what is relevant to this task, and what is this user authorized to execute?“ This shift marks the transition from Inference 1.0 to Inference 2.0.

Comparing the differences between model-centric inference versus workload-centric inference illustrates the transition from Inference 1.0 to Inference 2.0. Source: Author

Consider an engineer at an automotive semiconductor company asking: “Which version of our Ethernet controller complies with ISO 26262 ASIL-D, and does it meet our latest customer requirements?”

The answer does not exist in a single model’s weights. Before reasoning begins, the system must perform vector searches across document management platforms, query a failure modes and effects (FMEDA) database, inspect product lifecycle management (PLM) systems, check source-code repositories, and parse customer change requests. Conventional software services, policy checkers, and foundation models then analyze compliance evidence and flag inconsistencies before an orchestration layer assembles a defensible response.

One query triggers multiple database accesses, security validations, model invocations, and tool executions. Inference is no longer a single forward pass; it’s an orchestrated, multi-domain workflow.

Redefining performance: “Time to a useful answer”

Inference 2.0 alters the practical definition of performance. Model training is throughput-driven, running parallel jobs across thousands of accelerators for weeks. Enterprise users, by contrast, demand rapid, context-accurate responses. A physician reviewing an urgent diagnostic report or an engineer analyzing a production fault cannot benefit from peak token throughput if the system spends seconds waiting on database queries, context loading, or security authorization.

If platform A generates tokens twice as fast as platform B, but platform B retrieves corporate context and coordinates agents with far less overhead, platform B will deliver the end result faster. The meaningful system metric becomes time to a useful answer.

In an enterprise environment, “useful” is strictly constrained by three factors:

1. Correctness: Output meets application-specific domain quality thresholds.
2. Authorization: Access and security rules are strictly enforced.
3. Traceability: Intermediate reasoning steps and supporting evidence are preserved for auditing.

Hardware and system-level bottlenecks

Accelerating matrix multiplication alone yields diminishing returns when non-tensor tasks dominate overall execution time (Amdahl’s Law). Inference 2.0 shifts bottlenecks to working memory management and systemic data movement.

Managing shared working context (KV cache)

LLM inference decode is inherently memory-bound: hardware spends more time moving weights and key-value (KV) cache tensors than performing math. Agentic workflows amplify this problem. A single agent request can fan out into dozens of model calls that share identical system prompts, tool definitions, governance rules, and retrieved context.

Reprocessing this common prefix on every call wastes compute and introduces massive latency. So, systems must implement advanced memory management strategies:

• Paged attention and virtual memory (for instance, vLLM): Allocating KV cache dynamically in non-contiguous memory blocks eliminates internal fragmentation and enables efficient prefix sharing across multiple parallel agents.
• Radix tree prefix caching: Retaining prompt prefixes, system policies, and retrieved documents in memory across requests allows intermediate calls to skip the prefill stage entirely.
• Speculative decoding: Leveraging smaller draft models to propose tokens while using large foundation models for verification reduces latency and conserves high-bandwidth memory (HBM) capacity. As context windows extend to millions of tokens, managing the KV cache hierarchy—deciding what stays in HBM, what offloads to system DDR5, and what gets evicted—becomes as critical to system capacity as peak FLOPS.

Interconnects, DPUs, and heterogeneous memory

Moving data across storage, host memory, and accelerators represents the primary energy and latency penalty in Inference 2.0. Addressing this requires moving beyond traditional PCIe topologies:

• Compute Express Link (CXL): It enables cache-coherent memory sharing and expansion between CPUs, accelerators, and pooled memory devices. By allowing accelerators to access main system memory or shared pools without traditional host-copy overhead, CXL eases HBM capacity pressure during massive multi-agent context retention.
• Data processing units (DPUs) and smart NICs: Offloading line-rate security filtering, identity checks, data encryption, and network serialization to DPUs frees host CPUs and GPUs to focus strictly on orchestration and tensor workloads.
• High-speed scale-Up fabrics: Technologies such as NVLink or Ultra Accelerator Link (UALink) are increasingly vital not just for model parallelism during training, but for rapid KV cache migration and intermediate state transfer between heterogeneous accelerators during inference routing.

The runtime and system orchestration challenge

Inference 2.0 requires the system runtime to act as a distributed resource manager:

• Heterogeneous scheduling: Runtimes must dynamically partition tasks—routing vector searches to specialized vector engines or CPUs, scheduling dense linear algebra on GPUs/ASICs, and executing policy checks on host cores.
• Multi-model serving and isolation: Enterprise runtimes must serve large foundation reasoning models concurrently with smaller, fine-tuned domain models. This demands strict spatial and temporal isolation to prevent low-priority background tasks from degrading real-time user requests.
• Network latency in the compute path: In training, networks synchronize gradient tensors across worker nodes. In Inference 2.0, the network carries prompts, embeddings, RAG chunks, tool outputs, and agent states directly in the critical path. Network latency directly translates to user-perceived response time.

Evolving benchmarks: Measuring what actually matters

Traditional benchmarks like MLPerf inference excel at isolating raw accelerator capability (for example, batch-1 token latency or offline throughput). However, they fail to capture retrieval delay, context switching overhead, network transport, security enforcement, or multi-agent orchestration.

Just as database evaluation evolved from raw CPU clock speeds to holistic transaction benchmarks (like TPC-C and TPC-H), AI benchmarking must evolve to evaluate complete enterprise workflows.

The Inference 2.0 benchmark suite concept

An enterprise-grade benchmark suite should evaluate system performance across realistic operational profiles:

1. End-to-end task completion time: Total elapsed time from initial query input to a fully formatted, authorized response.
2. Context reuse efficiency index: Measures how effectively a system reuses KV cache across multi-turn agentic fan-outs without re-executing prefill phases.
3. Traceability and audit overhead: Evaluates system degradation when capturing complete chain-of-thought, tool invocation, and data provenance logs required for enterprise compliance.
4. Mixed-workload quality-of-service (QoS): Tail-latency (p99) performance when running concurrent workloads (for instance, background vector indexing alongside interactive multi-agent reasoning). Quality and correctness must be reported alongside execution time to ensure speed is never prioritized at the expense of accuracy or security.

Beyond GPU: Building balanced AI systems

Matrix multiplication will remain a core computational requirement, and GPUs will continue to play a central role in AI infrastructure. Modern GPUs have evolved significantly, incorporating lower-precision formats, sparsity support, larger memory footprints, and advanced inference runtimes.

However, accelerating tensor execution alone is no longer sufficient when an increasing fraction of system time and energy is consumed by data movement, context management, network transport, and security validation.

The leading platforms of the Inference 2.0 era will be those engineered for system-level balance. Whether centered on GPUs, specialized ASICs, dynamic CPU-accelerator clusters, or CXL-enabled memory pools, the winning architectures will be judged on a single unified criterion: how efficiently the complete system transforms organizational knowledge into trusted, actionable decisions.

That is the architectural imperative of Inference 2.0.

Lauro Rizzatti is a business development executive with VSORA, a technology company offering silicon semiconductor solutions that aim to redefine silicon performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

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The post Inference 2.0: How enterprise AI is reshaping AI system architectures appeared first on EDN.

It’s not uncommon for a midsection to become soft and distended with advancing age. That said, when it happens to a battery, it’s potentially quite problematic.

In last week’s part 1, I took apart a third-party BLX-1 battery which had come with my Olympus (now OM System) OM-1 digital camera and which the manufacturer’s own BCX-1 charger refused to recognize as a valid recharge partner. Also recently augmenting my burgeoning gear inventory are two enthusiast-prized Olympus PEN-F Micro Four Thirds bodies (once again digital, not the film-based precursor), one in each color option offered by the manufacturer a decade ago when they were new.

Each came with a third-party BLN-1 battery (7.6 V, 1220 mAh). Supplier names differed but their physical appearances were identical, therefore suggestive of a common manufacturing source. I’ll be taking them both apart today to test my hypothesis. But why am I dissecting them at all?

Unlike the BLX-1, they seemingly still work fine, but they both arrived slightly swollen, with further distension likely after additional use and recharge cycles. The last thing I want is for an inexpensive, replaceable cell to end up permanently lodged in the battery compartment of an expensive, irreplaceable camera, so retirement and replacement was a priority for both!

Trust me when I say that all the cameras showcased in this two-part series are Micro Four Thirds models, Olympus-now-OM System to boot, is only a coincidence. I’ve had no shortage of mixed-at-best success in the past with third-party batteries for other manufacturers’ cameras, too.

Some Wasabi with your sushi?

I randomly picked the one from Wasabi Power, a common “clone” cell supplier, to disassemble first. As usual, I’ll start with some overview shots, accompanied by a 0.75′′ (19.1 mm) diameter U.S. penny for size comparison purposes. Top.

Bottom.

Four of the BLN-1 contacts—”+”, “-“, “I” and “T”—are marked the same (albeit in different ordering) as with the BLX-1. As I mentioned last time, published specifications for batteries like these are hard-to-impossible to come by, given that for various reasons the camera manufacturer doesn’t want to encourage third-party cloning.

That said, once again the functions of “+” and “-“ are likely related to the applied voltage and current involved in the fundamental cell-charging and -discharging (for camera powering) functions. “I”, typically standing for “information” or “identification”, references the interrogation initially done by both charger and camera after battery insertion and power-on, and ongoing from that point on, presumably implemented by a bidirectional single-data-pin serial communications protocol of some sort.

“T” typically references “temperature”, with the contact connected to an embedded negative temperature coefficient (NTC) thermistor or other sensor that monitors the internal cell(s) and alerts the charger to potential overheating. And this time there’s a fifth electrical contact, “S”. User research suggests that it was added in response to Japanese standards body guideline revisions that mandated a fuller shut-off of the accompanying charger after the battery reported it was “full”, thereby minimizing subsequent “vampire” power draw.

The BLX-1 battery disassembled in part 1 of this series is significantly newer in generation than the BLN-1 and presumably integrates this function along with others already supported over the “I” interface, thereby negating the ongoing need for a dedicated “S” contact.

Onward, redux. Once again, the other end is much less exciting, as are the sides.

Ongoing unexciting-dissection aspirations

And once again, a Sirens-like tempting, albeit ultrasonic-welded, seam around the battery’s circumference seems to be the most feasible pathway inside, the potential for sparks, smoke, flame, and other calamities aside. Danger, Will Robinson!

Phew!

This time, the batteries’ form factors aren’t cylindrical and plastic-covered as before, but rectangular and metallic; niftily-named prismatic, to be exact. Once again throwing caution to the wind, I pressed forward determinedly (albeit cautiously) with the disassembly.

Rubber strips again, this time tape- and paper-accompanied, to insulate the mini-PCB from the batteries’ terminals both mechanically and electrically.

Enough with the teasing; I know this is what you’re most interested in seeing, right?

The design is much more elementary than with the BLX-1 circuit board we saw in part 1. The eight-lead IC PCB-labeled as U2 is stamped as follows on top, below a cryptic company logo.

8822
E6H01

It’s another dual N-channel MOSFET. And then there’s six-lead U1 to its right, marked as follows.

CGKU

As with the BLX-1, per an earlier-referenced discussion, I’m guessing it’s a rudimentary battery-protection IC. Apparently recharge-balancing the two cells isn’t of concern in this specific case.

Speaking of which, let’s take a closer look at the markings on the two cells’ prismatic cases, which you’ve already glimpsed in prior images.

They match each other, and I suspect the last eight characters of each reference a September 2016 manufacturing date. Nearing 10 years old, I’m willing to forgive a bit of old-age swelling, no matter that it obviates any further use (that I’m comfortable taking a chance on, at least). No voltage or capacity specs; that said, I suspect they’re the relatively common 4.2 V (3.7 V nominal) variant in a serial-interconnect topology.

Testing a common-sourcing hypothesis

Now for its Newmowa-branded counterpart (is that a clever company logo, or what?), complete with scribbling on top from its prior owner (who apparently, like me, is also blessed to own a diversity of camera hardware models from various manufacturers, and needs to keep his batteries straight).

Trust me when I say that had I decided to keep the battery in service, cleaning off those contacts would have been my very next step!

Once more unto the breach, dear friends.

This time, interestingly, both cells’ cases are completely marking-free on both sides.

Although the means by which the cells are adhesively bonded both to each other and to the surrounding halves of the enclosure differ, there’s visually obvious commonality with respect to the respective mini-PCB layouts.

That said, the components are seemingly divergent from a sourcing standpoint (albeit functionally identical, at least likely). Here’s what’s atop eight-lead U2 this time:

SNE
5N20V
7H09 (don’t quote me on the accuracy of this last line; it’s pretty fuzzy)

Once again, it’s a dual N-channel power MOSFET. And six-lead IC U1 to its right? Again, don’t quote me definitively, but here’s my best shot post-cleanup with rubbing alcohol.

20DD
L607

And with that, after wrapping up all four cells (two from each of the two batteries) in insulating masking tape to ensure safe storage until after my writeup is published.

I’ll also wrap up for today. Shout out with your thoughts in the comments, please!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

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The post Dissecting third-party camera batteries, part 2: Swelling appeared first on EDN.

Over the last two months, we mapped out how USB-C, Power Delivery (PD), vehicle-to-load (V2L), and high common-mode transit immunity (CMTI) are reshaping the landscapes of test and measurement and electric vehicles (EVs). The next challenge is practical: how do you translate those high-level architectural requirements into a schematic that works and a PCB layout that passes?

This post delivers the essential design clues—the component choices, layout constraints, and rule-of-thumb practices—that bridge concept to copper. It’s about moving from theory to implementation, giving engineers the confidence to build USB-C and PD systems that meet compliance while surviving real-world stress.

Designing for high CMTI: Turning ratings into real layout rules

To maintain high CMTI on a real board, the isolation barrier is non-negotiable. Specialized digital isolators—either capacitive-based or magnetic-based—are engineered to withstand the brutal transient voltage spikes in the range of kV/𝜇s without corrupting USB data streams. These devices form the shield that keeps common-mode noise from bleeding across domains.

Placement is equally critical: the isolator must straddle a deliberate, wide physical gap on the PCB. That gap is a true keep-out zone; no copper traces, power planes, or ground planes are allowed to cross it. The isolator alone bridges the divide, ensuring that the high-speed USB signals remain intact even under aggressive switching events. This disciplined layout practice is what turns theoretical CMTI ratings into reliable, repeatable board-level immunity.

Figure 1 Application diagram of ISOUSB211 reveals how the isolation barrier prevents data corruption caused by ground loops and power-stage switching noise. Source: Texas Instruments

Implementing USB-C and PD controllers: The schematic clues

Moving from standard USB to USB-C with Power Delivery—and even V2L—requires dedicated silicon. At the simplest level, configuring a USB-C port hinges on the CC pins. If the design is a power sink, such as a basic test and measurement instrument, you must place 5.1 kΩ pull-down resistors (Rd) on both CC1 and CC2 pins.

Conversely, if the design is a source, pull-up resistors (Rp) are required to advertise available current. For higher-power PD or bidirectional V2L applications, engineers should resist the temptation to code the complex negotiation state machines inside a general MCU.

Instead, a standalone USB-PD controller IC is the right choice—it encapsulates the protocol logic, manages the timing, and ensures compliance, freeing the system MCU to focus on application-level tasks. This division of labor is what makes USB-C and PD designs robust and certifiable in practice.

Figure 2 This simplified block diagram of the MAX77958 IC details the USB Type-C CC detection and Power Delivery protocol implementation. Source: Analog Devices

The 90-Ω differential layout: The PCB clues

High-speed USB signaling in USB 3.x and USB4 behaves much more like RF than low-speed digital. If the layout is off, compliance failures are inevitable. The first design clue is impedance control: the D+/D– or TX/RX traces must be routed as a matched differential pair with a strict target of 90 Ω. Deviations here directly translate into eye-diagram collapse and failed certification.

The second clue is geometry for ESD protection. In harsh EV and lab environments, transient voltage suppressor (TVS) diodes must sit physically as close as possible to the USB-C connector pins. The ESD spike must be absorbed at the connector entry point—before it can travel down the trace and reach sensitive silicon. This placement discipline ensures that compliance isn’t just theoretical but survives the real-world surge events that USB-C designs inevitably face.

Figure 3 Hand-drawn illustration of an eye diagram highlights the mask keep-out zone at the center. This stylized ‘open eye’ demonstrates the compliant signal quality expected in USB 2.0 links when the differential pair achieves routing near the 90-Ω target. Source: Author

Tips from the bench: What datasheets don’t mention

While mapping out your schematic and tracking your traces, keep these three notorious real-world layout traps in mind. They are the most common culprits behind first-revision PCB failures:

• Guard the CC pins against high-voltage shorts

Inside the microscopic geometry of a USB-C receptacle, the Configuration Channel (CC) pins sit directly adjacent to the high-voltage VBUS power pins. A slightly tilted cable insertion, a worn-out connector, or a bit of metallic debris can instantly short a 20-V VBUS line straight into a CC pin. Standard 3.3-V or 5 V-MCU inputs will instantly fry.

The fix: Always specify standalone USB-PD controllers featuring integrated 24 V short-to-VBUS protection on the CC lines.

• Tame the VBUS hot-plug voltage ringing

When a user hot-plugs a live Power Delivery adapter into your board, the parasitic inductance of the USB-C cable slams into the input capacitance of your PCB. This creates an LC circuit that can ring up to twice the nominal voltage, turning a standard 20-V PD profile into a destructive 40-V spike that easily ruptures downstream buck regulators.

The fix: Anchor the VBUS entry point with a heavy-duty, high-voltage TVS diode or an over-voltage protection (OVP) eFuse paired with a minimum of 10 uF of bulk ceramic capacitance to dampen the surge.

• Ban via stubs on your 90-Ω pairs

Achieving a strict 90 Ω target impedance requires flawless trace geometry. Every time a high-speed TX/RX or D+/D- pair hops between PCB layers through a via, it hits an impedance speed bump. Worse yet, if a trace transitions from the top layer to a middle layer, the remaining unused barrel of the via hangs off the signal path like an antenna. This “via stub” creates severe RF reflections that can collapse your eye diagram entirely.

The fix: Route high-speed USB lines on a single layer whenever possible. If layer transitions are absolutely non-negotiable, limit them to a maximum of two, place adjacent ground return vias right next to them to preserve the return path, and enforce back-drilling on multi-layer boards to eliminate the stubs.

This bench-level awareness is what keeps your first spin from becoming a costly lesson in overlooked physics.

Closing 3-month power and signal loop

Month 1 and month 2 set the destination, showing how USB-C, Power Delivery, V2L, and high CMTI are reshaping test and measurement and EV platforms. Month 3 provided the map: the schematic clues, resistor choices, isolation gaps, and PCB layout rules that turn concepts into copper.

The takeaway is clear: these design rules tie the journey together, moving from vision to verified hardware. By closing the loop with practical guidance, engineers are equipped not just to understand USB-C and PD, but to implement them with confidence in real boards and systems.

Carry these power and signal rules into your next design cycle; apply the resistor networks, enforce the isolation gaps, and route those 90-Ω pairs with precision. Share your own board-level lessons with peers and keep expanding the collective toolkit that transforms ambitious USB-C and PD concepts into reliable, compliant hardware.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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Live wire power poles present obvious danger to wildlife, but emergency response plans for such events unfortunately seem to be inadequate.

The following screenshot image (Figure 1) shows a black bear that actually managed to climb to the top of a power utility pole. The location was along Route 56 in New Mexico. While the bear was alive at the moment this image was captured, it was later electrocuted by the power lines, which reportedly carried 7200 volts.

Figure 1 Trapped bear unfortunately ends up electrocuted and deceased.

There have been several stories about this event. A link to one of them can be found here.

The danger that live wire power poles can present to wildlife, to birds in particular, has been addressed before. Please see here.

Quite frankly, I never expected that such an animal could get itself into trouble like that, yet I recently watched a PBS nature program where a black bear was seen effortlessly climbing a tree while hunting prey.

There are stories online of similar prior incidents having taken place. Here, it was speculated that since the event happened adjacent to a roadway, the bear might have been spooked by a passing vehicle and sought refuge by climbing that pole.

Emergency response plans for such events seem to be inadequate. Since they are already known to occur, however regularly or sporadically, I would have expected proper emergency response plans to have long ago been put in place, to turn electric power off and to then safely rescue the endangered animal(s). Instead, I see very little sign of emergency preparedness.

The emergency response operator in this case gave a verbal recitation along the line of “there’s nothing they can do.” There’s nothing that bear can do either, at least not anymore.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Bear on a power pole appeared first on EDN.

Every embedded project eventually needs to address similar challenges around how much storage should be allocated to the operating system, how much should be reserved for applications, how much capacity should be allocated for system and diagnostic logs, and whether there is enough space for future software updates.

These decisions are usually made early in development, long before the first product reaches the field.

For years, that approach served the embedded industry well. Software changed relatively slowly after deployment, applications performed clearly defined functions, and storage requirements were stable enough that engineers could make sensible decisions upfront and rarely revisit them.

Today, many teams are discovering those decisions don’t last nearly as long as they used to. Products that once received only occasional firmware updates now continue evolving throughout operational lifetimes that often exceed 15 years. The hardware stays the same, but the software keeps changing.

Moving beyond static partitions

Static storage partitioning solved an important engineering problem. Applications were isolated from one another, storage behaviour was predictable, and engineers knew exactly where critical software and data would reside. In embedded systems, that level of determinism remains valuable. Today, the challenge is that software-defined systems rarely evolve evenly.

One application may barely change throughout the life of a product. Another may double in size over several software releases. At the same time, logging requirements increase, configuration data expands, and new AI models arrive years after the original storage layout was designed.

Eventually, the symptoms become familiar. One partition starts running out of space while another still has capacity that will probably never be used. Software teams spend time optimizing storage layouts instead of developing new functionality. Hardware that still has usable flash becomes constrained because it cannot be used where it’s needed most.

Why overprovisioning isn’t a long-term answer

One obvious response is to reserve more storage during development. Many embedded platforms already include generous safety margins for exactly this reason. If engineers don’t know which applications are likely to grow over the next decade, the safest option is often to allocate additional storage to all of them. That approach reduces immediate risk, but it also leaves flash capacity permanently tied to assumptions that may never prove correct.

As software-defined products become more complex, and flash prices continue to rise, this strategy becomes increasingly difficult to justify. Industry analysts have reported significant increases in NAND and NOR flash prices over the past year, meaning every additional gigabyte contributes to higher hardware costs. As a result, overprovisioning has become a bill-of-materials (BoM) consideration.

The impact of software updates

Over-the-air (OTA) updates illustrate the problem particularly well. Reliable update strategies require storage for downloading, validating, and, if necessary, rolling back software when something goes wrong. Traditional A/B partitioning addresses this by maintaining duplicate software images so that the previous version remains available until the update has been verified. This means significant amounts of flash remain reserved for situations that occur only during the update process.

A/B partitioning remains a proven and widely adopted approach because it provides a straightforward and reliable rollback mechanism if an update fails. The trade-off is that maintaining two complete software images requires a significant amount of flash to remain reserved for the update process.

As software-defined systems become more capable, that approach can increase storage requirements, enlarge software downloads, and add to the cost and complexity of deploying updates across connected devices. With flash prices continuing to rise, many engineering teams are beginning to question whether permanently reserving that capacity remains the right trade-off for every platform.

Looking at storage differently

Rather than treating storage as a collection of permanently assigned partitions, more engineers are beginning to view it as a managed system resource. This is where the concept of a dynamic data layer becomes useful.

One of the challenges it addresses is static storage allocation. Instead of permanently assigning flash to individual applications, storage can be managed as a shared resource. Applications remain isolated through mechanisms such as subvolumes, while quotas define how much storage individual workloads may consume and reservations ensure critical functions always retain guaranteed capacity.

This allows storage to adapt as software evolves. Capacity that would otherwise remain stranded in one partition can be made available elsewhere, improving utilization without sacrificing isolation or predictability.

Rethinking OTA architectures

The data layer also creates opportunities to rethink how over-the-air updates are managed. Traditional A/B partitioning remains a robust and widely adopted approach because it provides a straightforward rollback mechanism if an update fails. However, maintaining duplicate software images permanently reserves a significant amount of flash capacity.

Snapshot-based approaches provide an alternative. Rather than storing two complete software images, the file system tracks changes at the block level so only modified data needs to be written during an update.

The pre-update snapshot provides a reliable rollback point while reducing storage overhead, download size, and update effort. As flash prices continue rising, more engineering teams are evaluating these techniques as another way to improve storage efficiency without compromising reliability.

Flexibility still requires discipline

Dynamic storage management doesn’t remove the engineering constraints embedded systems have always depended on. Deterministic behavior remains essential as critical applications still require guaranteed resources. Functional safety, reliability, and predictable recovery mechanisms continue driving architectural decisions.

The objective isn’t to make storage dynamic for its own sake but to recognize that software is no longer static in the way it was when many of today’s storage architectures were originally conceived. As systems continue to evolve throughout their operational lifetime, storage management must evolve with it.

A different role for the data layer

Storage has traditionally been viewed as supporting infrastructure. Once the partition layout was complete, attention naturally shifted to processors, applications, and communications.

Software-defined systems are changing that perspective. The data layer is becoming a more active part of system architecture because it influences how efficiently software can evolve throughout the life of a product. It affects update strategies, application growth, storage utilization, and long-term maintainability just as much as raw flash capacity.

Instead of asking whether today’s applications fit into today’s partition layout, engineers are beginning to ask whether the storage architecture itself is capable of supporting software that hasn’t yet been written. While the answer will differ from one platform to another, what seems increasingly clear is that storage can no longer be designed around the assumption that software remains static after deployment.

Embedded systems have entered an era of continuous software evolution, and the architectures beneath them need to evolve for the same reality.

Sami Kassimäki is product manager at Tuxera.

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I like to read about research innovations even if most of them don’t represent in an advance that can be commercialized or even leveraged to boost technology in general. Sometimes, the work that the team has done demonstrates innovation, discusses ways they addressed and hopefully resolved problems, and even gives insight into areas where there are remaining barriers to overcome.

That’s the case with a research paper I came across on use of paper as a substrate of passive electronic components and interconnects. In the work, “High-Density Papertronics via Laser-Written Hydrophilicity on Hydrophobic Parchment Paper” published at ACS Applied Materials & Interfaces, researchers discuss the long path they have taken to develop their latest effort in paper electronics—dubbed “papertronics”—with the use of standard parchment paper as a substrate for passive electronic elements.

This project builds heavily on other work the team has done under Professor Seokheun “Sean” Choi of the Department of Electrical and Computer Engineering at Binghamton University’s Thomas J. Watson College of Engineering and Applied Science (New York State). They have investigated the use of paper to create fully biodegradable circuit elements such as batteries, sensors, and other components.

The papertronic devices are intended to be low cost, environmentally friendly, and suitable for applications such as single-use medical patches that power using sweat, water, or even saliva as their working fluid. While paper-based electronics of various types are being investigated in many labs, this group has done a significant amount of leading-edge work in this area with a lengthy track record.

Their previous attempts to build passive circuit elements used chromatography paper as a substrate; this paper is a specialized, high-purity cellulose material widely used as the stationary phase to separate mixtures of chemical substances, inks, or plant pigments via capillary action. Unlike everyday normal paper, which contains fillers and sizing agents that interfere with fluid movement, chromatography paper has a consistent texture, controlled thickness, and predictable capillary action, vital for accurate laboratory results.

That approach proved the concept but revealed a stubborn limitation: the wax barriers used to define circuit features blurred and spread when heated, limiting the smallest achievable features to about a millimeter. That kept circuits large—on the scale of tens of centimeters—and prevented the kind of compact, tightly packed designs needed for practical applications.

Rethinking the problem

Their new approach required a radical shift. Instead of hydrophilic chromatography paper, they switched to hydrophobic parchment paper, and using a laser to selectively create hydrophilic channels rather than wax to create hydrophobic barriers, the team inverted the entire fabrication paradigm (Figure 1).

Figure 1 By targeting the parchment paper with a laser, Professor Choi and his team removed the silicone coating to expose water-absorbing cellulose fibers. The channels then act as microscopic highways that guide water-based conductive inks to form electronic circuits. Source: Binghamton University

Note that parchment paper—also called “baking paper”—is a heat-resistant, silicone-coated paper used in cooking and baking as a non-stick, greaseproof surface; you can buy it at almost any supermarket as well as from cooking-supply sources. But there’s some potential for verbal confusion here; the research team is using silicone-based paper as the substrate rather than more-familiar “silicon.” Silicone, of course, is a synthetic rubber-like substance made by combining silicon with oxygen, carbon, and hydrogen.

They developed hybrid paperfluidic-electronic techniques that exploit parchment paper’s capillary action to wick functional materials into predefined regions, yielding components such as resistors, capacitors, inductors, and interconnects (Figure 2).

Figure 2 Conceptual illustration of wax-printed versus laser-induced papertronics. In row (a), wax-printed papertronics on hydrophilic cellulose paper highlights the multiple fabrication steps required for hydrophilic pattern formation via single-sided wax printing and thermal penetration (i) and hydrophilic patterning via asymmetric double-sided wax printing and thermal penetration (ii). In row (b), molten-wax spreading during thermal penetration inherently blurs feature boundaries and limits the achievable resolution. Laser-induced papertronics on hydrophobic parchment paper demonstrates a simplified, low-temperature fabrication workflow that enables direct hydrophilic patterning without wax spreading or high-temperature processing (i) and the realization of high-density papertronic circuits with narrow hydrophilic channels and tightly spaced insulating regions (ii). Source: ACS Publications

The result is circuit features as small as 250 micrometers wide with 300-micrometer spacing—a twofold to threefold improvement over the best wax-based methods, and small enough to fit complete filter circuits into a footprint measured in millimeters rather than centimeters.

The differences due to the inverted thinking are clear: with chromatography paper, they were fighting against molten wax spreading through the paper. With their laser approach and parchment paper, the pattern is defined by the laser spot size and stays exactly where they put it. There is no spreading, no blurring, and no uncertainty.

Critically, all of the functional inks used in the work are water-based and free of toxic metals or organic solvents. The circuits are biodegradable, breaking down in soil within weeks, and can be incinerated to ash in seconds if rapid disposal is needed. For applications that require longer operational lifetimes, a thin silicone encapsulation layer protects the devices from humidity and mechanical damage without affecting their electrical performance.

Fabrication technique

As a first step, they used Fourier-transform infrared (FTIR) spectroscopy to determine the chemical composition of the pristine parchment paper, the surface modifications induced by laser treatment, and the effect of “ink” deposition. Laser irradiation induces pronounced photothermal and photochemical modifications to the parchment paper surface, which they assessed as well.

They then used laser modification to convert selected regions into ink-guiding hydrophilic microchannels. The localized laser-induced heating modifies the surface chemistry and microstructure without requiring additional chemical coatings, fillers, or high-temperature treatments.

Using a 50-watt CO2 laser, the laser power and scan speed were systematically tuned to optimize local heating and patterning of silicone-coated parchment paper. It took a significant amount of trial and error to find the optimum power and speed pairing. With a high-power and low-scan speed, the laser overheated the substrate, burning through the hydrophilic cellulose layer and cutting the paper. At low power and high speed, the silicone coating was only partially removed or not removed at all, thus preventing proper penetration of the functional materials.

Critically, these laser-defined hydrophilic features exhibit no lateral spreading, enabling minimum feature sizes and spacings that approach the theoretical resolution limit of the optical system. This strategy enables unprecedented high-density patterning, robust pattern reproducibility, and device-scale miniaturization for a significant leap beyond what is achievable with wax printing or traditional paperfluidic techniques.

For ink used to define conductive traces and electronic components, they used poly (3,4-ethylenedioxythiophene)-poly (styrenesulfonate), known as PEDOT:PSS, with controllable viscosity and density. For many reasons, PEDOT:PSS is widely used in research projects. Using these formulations resulted in limited lateral spreading on the order of micrometers within 3D cellulose fiber network.

Then there’s performance

They constructed printed resistors, interdigitated capacitors, low-loss interconnects, and integrated low- and high-pass RC filters within a single paper layer, exhibiting predictable, tunable electrical behavior consistent with circuit theory. The conductive lines have a width of ∼250 μm and a line spacing of ∼300 μm, corresponding to a PCB pitch of ∼550 μm.

The team demonstrated the platform’s versatility by fabricating a complete set of electronic components on paper: resistors whose resistance can be tuned over three orders of magnitude simply by adjusting the ink formulation; interconnects with sheet resistance as low as approximately one ohm per square, rivaling rigid electronic systems; capacitors tunable from microfarads to millifarads; and fully functional low-pass and high-pass RC filters whose frequency response closely matches theoretical predictions.

For example, the resistor values were independently controlled through three parameters: ink concentration, dimethyl sulfoxide (DMSO) content, and resistive line length. The laser-defined hydrophilic channels acted as deterministic templates that confined conductive inks, while the surrounding silicone-coated parchment remained hydrophobic and electrically insulating. This spatial confinement decoupled electrical tuning from uncontrolled ink spreading and penetration, enabling predictable and reproducible resistor geometries.

Note that DMSO is a poor electrical conductor on its own because it’s a molecular liquid without free ions or electrons. However, when ionic compounds like salts or acids are dissolved in it, it acts as a polar aprotic solvent that readily dissociates those ions, allowing the resulting solution to conduct electricity.

The laser-defined hydrophilic channels act as templates that confine conductive inks, while the surrounding silicone-coated parchment remains hydrophobic and electrically insulating. This confinement decouples electrical tuning from uncontrolled ink spreading and penetration, enabling predictable and reproducible resistor geometries.

Overall, the resistance of the paper-based resistors can be continuously tuned over a broad range from approximately tens of ohms to several kilohms (Figure 3).

Figure 3 For paper-based resistors, schematic illustrates how laser-defined paper resistors are tuned by three independent parameters: ink concentration, DMSO addition, and resistor geometry (a). Optical microscopy image (i) and SEM image of the A–A′ cross-section of a representative resistor (ii) show that PEDOT:PSS is precisely confined within the laser-treated hydrophilic region and surrounded by untreated hydrophobic parchment paper (b). Measured resistance of resistors is fabricated with varying ink volumes, where PEDOT:PSS was systematically diluted with deionized water to concentrations of 100%, 75%, and 50%, plotted as a function of resistor length (c). Resistance as a function of DMSO concentration in the PEDOT:PSS matrix is shown with weight percentages ranging from 2% to 20%, plotted as a function of resistor length (d). Data in (c) and (d) represent mean ± standard error from at least 10 independent measurements per data point. Solid lines are least-squares linear fits. Source: ACS Publications

For capacitors, conductive PEDOT:PSS electrodes were precisely patterned into interdigitated fingers using laser-induced hydrophilic channels, while the surrounding silicone-coated parchment remains hydrophobic and electrically insulating. The capacitance increases monotonically with the number of interdigitated fingers, reflecting the enlarged effective electrode surface area and reduced ionic diffusion distance inherent to the interdigitated geometry.

They achieved capacitance values spanning from the low microfarad regime to over 1.2 millifarads (Figure 4). The ability to modulate capacitance over nearly three orders of magnitude using only electrolyte composition and electrode geometry demonstrated the exceptional tunability of this capacitor platform.

Figure 4 For paper-based capacitors, schematic illustrates a laser-defined interdigitated capacitor fabricated on hydrophobic parchment paper (a). Optical microscopy image (i) and SEM image of the A–A′ cross-section of a representative capacitor (ii) show that conductive PEDOT:PSS ink is precisely confined within the laser-treated hydrophilic regions to form interdigitated electrode fingers, while the surrounding parchment paper remains hydrophobic and electrically insulating (b). Measured capacitance of capacitors fabricated with varying H3PO4 concentrations in the PVA gel electrolyte is plotted as a function of electrode finger number (c). Galvanostatic charge–discharge (GCD) curves are measured at a constant current of 2 μA after different numbers of charge–discharge cycles (d). Capacitance retention as a function of cycling number demonstrates the cycling stability of the paper-based capacitor (e). Source: ACS Publications

Interconnects and filters

The capillary scheme was also used to create interconnects, leading to what can be considered as “integrated circuits”. To demonstrate circuit-level integration, they fabricated first-order low-pass and high-pass RC filters.

All of the hydrophilic regions were defined in a single laser step, and components were sequentially deposited using paper stencils. The first-order low-pass RC filter composed of a series resistor and a shunt capacitor (Figure 5).

Figure 5 For paper-based RC filters fabricated on parchment paper, part A shows a low-pass RC filter: schematic illustration (a), circuit diagram (b), and photograph of the low-pass filter fabricated on parchment paper (c). Frequency-dependent gain plots for low-pass filters with different resistance values (46 Ω, 95 Ω, and 150 Ω) demonstrate low-pass cutoff behavior (d). Part B shows a high-pass RC filter: schematic illustration (a), circuit diagram (b), and photograph of the high-pass filter fabricated on parchment paper (c). Frequency-dependent gain plots for high-pass filters with different resistance values (15 Ω, 46 Ω, and 95 Ω) demonstrate high-pass cutoff behavior (d). Source: ACS Publications

Since the resistor, capacitor electrodes, and interconnects required different ink formulations and additives, each printing step is performed using a dedicated paper stencil. Despite this, the overall process remains low-temperature and highly reproducible.

They also assessed environmental aspects and biodegradability. Although parchment paper incorporates a thin silicone coating to give it hydrophobicity, the substrate is predominantly cellulose-based with the silicone layer accounting for only a minor fraction of the total material volume (typically <2 μm in thickness).

As a result, degradation is governed primarily by the underlying cellulose fiber network. The silicone coating, while more persistent in natural environments, is widely recognized as biocompatible and chemically inert, and its limited mass minimizes its environmental burden.

But no transistors, at least not yet

The team’s paper is quite detailed with respect to the underlying materials science, elemental physics and chemistry, and other considerations. They also acknowledge a significant shortcoming; thus far, no active devices such as transistors.

I applaud their willingness to switch from one type of paper and fabrication to a very different scheme when the first approach reached a dead end. It takes an open mind to start over and re-assess what is working and what is not.

Based on their track record with various embodiments of papertronic devices, I wouldn’t be surprised if they get the needed funding to further pursue their work toward papertronic transistors using what they have learned thus far. That would certainly be impressive.

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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Attempted prohibitions of foreign-sourced products based solely on theoretical claims, absent irrefutable supportive factual evidence, only invites domestic-supplier favoritism accusations.

Last year I went on a “bit” of a(nother) drone-buying binge. Following up on the first-generation DJI Mavic Air I’d bought in mid-2021.

And the two DJI Mini 3 Pro drones (once again, accompanied by an abundance of accessories) I’d acquired in mid-2024.

I got two more gently-used drone gear sets from Lensrentals in 2025; the computer vision-based collision avoidance surround-enhanced and LiDAR-augmented Mini 4 Pro.

Followed by a first-person view (FPV) “cinewhoop” drone, the first-generation DJI Avata.

And in-between those two acquisitions, chronologically speaking, was the first-generation DJI Neo I bought from Amazon in a three-battery kit configuration.

What was behind this seeming conspicuous consumption behavior? Curiosity, for one thing; FPV operation, for example, was something that had captured my interest ever since I first saw the famous “Right Up our Alley” video more than a half-decade ago.

An essentially autonomous (albeit optionally still traditionally controllable) drone with a starting price just slightly more than $100 was also intriguing, both personally and professionally.

And I’ve already mentioned the feature set enhancements the Mini 4 Pro offers over its Mini 3 Pro precursor, which were insufficient temptation in 2024 but which I succumbed to a year later once I came across a sufficiently discounted like-new version.

Heavy is the hand that holds the crown

That all said, scarcity fears were admittedly also a factor, driven by seemingly inevitable pending government regulation-driven bans on DJI drones, along with other image capture-capable devices from the company, such as vlogging and action cameras. Back in mid-2024, the U.S. House of Representatives had passed legislation introduced a year-plus earlier, which banned further sales of drones from DJI and other suppliers deemed too friendly to the Chinese Communist Party, despite a longstanding absence of any tangible (public, at least) evidence supportive of this stance.

Although, subsequently introduced in the U.S. Senate, it was never voted on, therefore not becoming a law. But that outcome was a false solace; U.S. Customs began blocking imports of DJI drones and other products that same October.

By mid-2025, U.S. retailer inventories of existing DJI devices had notably evaporated. And the company didn’t even bother formally introducing newer drones such as the Mavic 4 Pro, Mini 5 Pro, Neo 2, Avata 360 and Lito 1/X1 in the United States. That all said, as it turns out, the final ruling from the U.S. Federal Communications Committee (FCC), announced two days before Christmas 2025 (believe it or not), admittedly wasn’t as egregious as initially feared (although a further retroactive-recall carve-out remains in place).

Imports of future-announced drones, including future generations of existing drone lines, were prohibited. But existing drones were once again green-lit for shipment and sale, including ongoing firmware updates (for at least a few more years) and broader usage (subject to existing FAA regulations) for products already in customer hands. Which is why you can now find the Mavic 4 Pro, Mini 5 Pro, Neo 2, and Avata 360 for sale at some U.S. retailers.

But only some. Notably, DJI not only subsequently sued the FCC but doesn’t include its latest products on the U.S. version of its online store. Even legacy drones remain unavailable; they’re “out of stock”.

Equally disruptive, the company won’t honor warranty claims coming from U.S. residents for products purchased through third parties. And speaking of which, some large U.S. retailers, such as Amazon (but not others such as Adorama and B&H Photo Video, interestingly), are continuing to decline to inventory and sell the latest DJI drones themselves, although they’ll act as marketplaces and shippers for others.

Meanwhile, DJI is reportedly rebranding its products as coming from “shell” companies to dodge restrictions (at least temporarily). You can still buy anything you want, including supposed banned newer drones such as the Lito 1 and X1, from outside-U.S. sellers via eBay, Mercari, and other online marketplaces. And if you know anyone in Canada or Mexico, or briefly pop across the border or more broadly travel internationally yourself, you can also get your unconstrained DJI “fix” that way. So how much of a ban on new drones is it, really?

What happened to free markets?

Am I suggesting that the U.S. government’s actions are completely misguided? Not at all. Obviously, the People’s Republic of China is a leading adversary, with a vested interest in collecting any and all surveillance information, whether audio, visual, and/or otherwise. And ironically, effective May 1, 2026, China itself has banned all drone sales and rentals in Beijing, the capital, along with restrictions on the broader storage of drones and drone components within the city. So, for one of its leading companies to complain about sales and usage restrictions elsewhere in the world is a “bit” of a “doth protest too much” situation, methinks.

That said, as I’ve mentioned previously, DJI’s longstanding greater-than-90% market share in consumer drones also can’t (or at least shouldn’t) be overlooked, as it reflects both the sizeable installed base and ongoing customer preference. Notable, as well, is the fact that other drone companies such as Skydio have already withdrawn from the broad market, focusing solely on enterprise opportunities going forward.

So, even if the U.S. government had hoped to use a DJI ban to boost the fortunes of alternative domestic suppliers, that supply doesn’t currently exist. And regarding the security angle, while I get it (though I’d still welcome indisputable proof of it) for gear that can directly live-stream audio and images using DJI’s own applications, I remain baffled as to why such bans extend to devices that aren’t directly Internet-connectable, especially those (such as gimbals) with no native multimedia data-capture capabilities.

Anyway, it’s not just consumers like me that’ll be affected. Here, off the top of my head and in no particular order save for how they streamed out of my noggin, are examples of business and civic entities already making notable use of drones, with broader near-term expansion planned.

• Restaurants and chains
• Food-and-other delivery services
• Law enforcement, including border patrol
• Fire spotters and fighters
• Ranchers and farmers
• Medical facilities
• Utility companies
• Filmmakers
• Researchers of all sorts
• Musicians and other performers

To wit, here’s just one recent case study from just a few miles to the east of me:

Are many of them currently using DJI-branded equipment? You bet. Can at least some of them switch to non-DJI drones in the future, assuming sufficient supply exists? I suppose. But at what cost? Not insignificant. And can all, or even many, afford the incremental investment? Doubtful.

Thereby likely explaining, at least in part, why what was initially seen as a planned full-stop ban ended up scaled back to a going-forward prohibition…but still…consider, for example, repair and replacement-parts availability impacts, along with aforementioned warranty-coverage issues.

Other conceptually similar, more recent actions by various U.S. government entities involve restrictions on routers and cellular hotspots, along with some (but not all) connected vehicles, solar inverters and robots of all sorts…but this writeup is already running long, so I’ll save those for another day. For now, I welcome reader perspectives in the comments on the issues I’ve raised here!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• The (more) modern drone: Which one(s) do I now own?
• Aftermarket drone remote ID: Let’s see what’s inside thee

The post Drone bans harm customers and don’t actually close the door appeared first on EDN.

Montage Technology has introduced the M88MX6852, a CXL 3.2 Memory eXpander Controller (MXC) chip for AI infrastructure and data center applications. The device has entered trial production and has been integrated into next-generation CXL products developed by memory module manufacturers including Samsung and SK hynix.  It is also designed for interoperability with Intel Xeon and AMD EPYC server platforms.

By converting host CXL memory requests into DDR commands in real time, the M88MX6852 manages data exchange between the host processor and DDR5 memory. It supports multiple CXL memory expansion form factors, including PCIe AIC cards and EDSFF modules, enabling memory expansion, sharing, pooling, and tiering.

The M88MX6852 integrates a CXL controller, dual DDR5-8000 controllers, two RISC-V processor subsystems, and an on-chip PVT sensor. Its CXL controller complies with the CXL 3.2 specification, including CXL.mem and CXL.io protocols, as well as CXL 1.1 and CXL 2.0. Based on a PCIe 6.2 interface, it achieves data rates up to 64 GT/s over eight lanes.

Montage Technology provides an SDK along with analysis and testing tools to support product development, system validation, and production ramp.

M88MX6852 product page

Montage Technology 

The post CXL controller scales server memory appeared first on EDN.

Innodisk’s DDR5 Multiplexed Rank DIMM (MRDIMM) uses a multiplexed registering clock driver and a multiplexed data buffer to achieve data rates up to 12,800 MT/s. By enabling simultaneous access to two ranks, the memory module increases bandwidth by 60% compared to conventional DDR5-8000 registered DIMMs (RDIMMs). The architecture reduces memory controller load and lowers latency, improving performance for AI model training, LLM inference, cloud computing, and robotic automation.

Designed to fit standard 287-pin DDR5 RDIMM slots, the Innodisk DDR5-12800 MRDIMM simplifies system upgrades. Built-in eFuse and TVS safeguard against power surges, while the integrated multiplexed registering clock driver and data buffer support stable high-speed data transmission. The company says the module’s energy-efficient design minimizes power consumption, supporting the sustainability goals of modern data centers.

The DDR5-12800 MRDIMM will be available in Q4 2026 with capacities ranging from 32 GB to 128 GB.

Innodisk

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