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Adding the long-first-pulse malady in less traditional 555 astable topologies including CMOS- and bipolar-based oscillators that generate 50:50 symmetrical square waves.

A previous Design Idea, “Gated 555 astable hits the ground running” offered a fix for the problem of the excessively long first pulse that’s generated by traditional topology 555 astable circuits on start up when gated by the RESET pin from oscillation-off to oscillation-on. See Figure 1 and Figure 2.

Figure 1 The problem—the first oscillation cycle has a too-long first pulse on start-up, when gated by the RESET pin from oscillation-off to oscillation-on.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 2 The fix via C2 charge injection on oscillation startup to equalize pulse length.

However, unaddressed in this design idea is the fact that less traditional 555 astable topologies also suffer from the same long-first-pulse malady. Important examples of such circuits are oscillators that generate 50:50 symmetrical square waves, such as Figure 3.

Figure 3 The long first-pulse problem also occurs in a 50:50 square wave topology popular for CMOS 555s.

Happily, the same fix from “Gated 555 astable hits the ground running” works in this genre of oscillators too, as illustrated in Figure 4.

Figure 4 C2 charge injection fix applied to CMOS 50:50 square wave oscillator.

So, the problem is solved for CMOS 555 square wave generators. But what about their bipolar kin?

Despite their age, bipolar 555s still get designed into contemporary applications. The reasons for the choice include advantages like higher supply voltage rating (18 V vs 15 V) and greater output current capability (hundreds vs tens of mA) than CMOS types. But they do need to be wired up somewhat differently—for example with an extra resistor (as described in a previous Design Idea “Add one resistor to give bipolar LM555 oscillator a 50:50 duty cycle“)—when a 50:50 square wave output is required. See Figure 5.

Figure 5 Bipolar 555 in gated 50:50 square wave configuration.

The C2 charge injection trick will still work to correct Figure 5’s first pulse, but there’s a complication. When held reset, Figure 5’s circuit doesn’t discharge the timing capacitor all the way to zero, but only to Vz where:

Vz = R3(R2 + R3)-1 V+
= 0.184 V+

Therefore, our old friend C2 = C1/2 won’t work. What’s needed is a smaller charge injection from a smaller C2 = 0.175 C1 as Figure 6 shows.

Figure 6 C2 charge injection first-pulse fix modified for bipolar 555 square wave generation.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Gated 555 astable hits the ground running
• Add one resistor to give bipolar LM555 oscillator a 50:50 duty cycle
• 555 triangle generator with adjustable frequency, waveshape, and amplitude; and more!
• The NE555 current spike

The post More gated 555 astable multivibrators hit the ground running appeared first on EDN.

At CES 2024, a French startup is presenting the notion of frugal code in embedded software by identifying and quantifying the optimization potential of the code. WedoLow, a spinoff from three research laboratories—IETR, INSA, and Inria in Rennes, France—will demonstrate how its automated software solution works for automotive applications ranging from advanced driver assistance systems (ADAS) to autonomous driving (AD) to in-vehicle infotainment systems.

WedoLow claims that its solution addresses complexity in embedded software by diagnosing and checking the code rapidly throughout the development process. That’s how it ensures if the code is fully optimized and if gains can be obtained in terms of speed of execution or energy consumption.

Source: WedoLow

Complexification of code in embedded software

At a time when applications are becoming larger and codes increasingly voluminous and complex, embedded systems are obviously no exception. That inevitably complexifies the work of developers, who now face a growing risk of delays with consequences for the efficiency and performance of their applications.

According to a 2020 survey from Sourcegraph, 51% of developers say they have more than 100 times the volume of code they had 10 years ago. Furthermore, 92% of developers say the pressure to release software faster has increased.

Take the case of the automotive industry, where cars have 200 million lines of code today and are expected to have 650 million by 2025. According to a McKinsey report titled “Outlook on the automotive software and electronics market through 2030,” the automotive software market is already worth more than 31 billion dollars and is forecast to reach around 80 billion in 2030.

The use of embedded software in the automotive sector has been constantly increasing since the introduction of anti-lock braking system (ABS) more than 40 years ago. So, gains in embedded software’s speed of execution and energy consumption will result in more responsive systems and longer battery life, which are crucial aspects for electric and autonomous mobilities.

How software works

WedoLow claims that its beLow software suite enables developers to understand the structure of a code and identify the parts that can be rewritten to generate more efficiency and performance. It’s enabled by optimization techniques that identify and quantify the potential optimization of the code at any stage of its development.

They build a line-by-line or function-by-function optimization strategy and obtain an optimized code rapidly and automatically. For example, WedoLow quotes a 23% gain in execution speed on the filtering of signals emitted by sensors on a road vehicle transmission system. Next, it helped achieve a 95% gain in execution speed on the processing of data and filtering of signals emitted by different sensors in battery management system (BMS) software.

Besides embedded software, WedoLow also aims to address the hosted software segment for server and cloud applications. Here, the French upstart conducted a test with an aerospace group on the processing of satellite images, reducing the software’s energy consumption by 18%.

WedoLow is presenting its frugal code solution at CES 2024; product launch is scheduled in the second quarter of 2024.

Related Content

• Embedded Basics
• All Things Embedded
• 8 pillars of embedded software
• Programming embedded systems: automatic code generation
• 5 essential tips and tricks for building rock-solid embedded software

The post CES 2024: Creating a frugal code in embedded software appeared first on EDN.

Introduction

In Power Tips #116, I talked about how to reduce the total harmonic distortion (THD) of a power factor correction (PFC). In this power tip, I will talk about another important criterion to evaluate PFC performance: the power factor, defined as the ratio of real power in watts to the apparent power, which is the product of the root mean square (RMS) current and RMS voltage in volt amperes, as shown in Equation 1:

The power factor indicates how efficiently energy is drawn from the AC source. With a poor power factor, a utility needs to generate more current than the electrical load actually needs, which causes elements such as breakers and transformers to overheat, in turn reducing their life span and increasing the cost of maintaining a public electrical infrastructure.

Ideally, the power factor should be 1; then the load appears as a resistor to the AC source. However, in the real world, electrical loads not only cause distortions in AC current waveforms, but also make the AC current either lead or lag with respect to the AC voltage, resulting in a poor power factor. For this reason, you can calculate the power factor by multiplying the distortion power factor by the displacement power factor:

where φ is the phase angle between the current and voltage and THD is the total harmonic distortion of current.

As the THD requirement gets lower, the power factor requirement gets higher. Table 1 lists the power factor requirements in the recently released Modular Hardware System-Common Redundant Power Supply (M-CRPS) base specification.

Table 1 M-CRPS power factor requirements

Equation 2 shows that to improve the power factor, the first thing to do is to reduce the THD (which I discussed in Power Tips #116). However, a low THD does not necessarily mean that the power factor is high. If the PFC AC input current and AC input voltage are not in phase, even if the current is a perfect sine wave (low THD), the phase angle φ will result in a power factor less than 1.

The phase difference between the input current and input voltage is mainly caused by the electromagnetic interference (EMI) filter used in the PFC. Figure 1 shows a typical PFC circuit diagram that consists of three major parts: an EMI filter, a diode bridge rectifier, and a boost converter.

Figure 1 Circuit diagram of a typical PFC that consists of an EMI filter, diode bridge rectifier, and a boost converter. Source: Texas Instruments

In Figure 1, C1, C2, C3, and C4 are EMI X-capacitors. Inductors in the EMI filter do not change the phase of the PFC input current; therefore, it is possible to simplify Figure 1 into Figure 2, where C is now a combination of C1, C2, C3 and C4.

Figure 2 Simplified EMI filter where C is a combination of C1, C2, and C3. Source: Texas Instruments

The X-capacitor causes the AC input current to lead the AC voltage, as shown in Figure 3. The PFC inductor current is , the input voltage is , and the X-capacitor reactive current is . The total PFC input current is , which is also the current from where the power factor is measured. Although the PFC current control loop forces  to follow , the reactive current of leads  by 90 degrees, which causes  to lead . The result is a poor power factor.

This effect is amplified at a light load and high line, as  takes more weight in the total current. As a result, it is difficult for the power factor to meet a rigorous specification such as the M-CRPS specification.

Figure 3 X-capacitor  causes the AC current to lead the AC voltage. Source: Texas Instruments

Fortunately, with a digital controller, you can solve this problem through one of the following methods.

Method #1

Since  makes the total current lead the input voltage, if you can force the  to lag  by some degree, as shown in Figure 4, then the total current  will be in phase with the input voltage, improving the power factor.

Figure 4 Forcing  to lag so that the total current  will be in phase with the input voltage. Source: Texas Instruments

Since the current loop forces the inductor current to follow its reference, to let  to lag , the current reference needs to lag . For a PFC with traditional average current-mode control, the current reference is generated by Equation 3:

where A is the voltage-loop output, B equals 1/VAC_RMS2, and C is the sensed input voltage VAC(t).

To delay the current reference, an analog-to-digital converter (ADC) measures , the measurement results are stored in a circulate buffer. Then, instead of using the newest input voltage (VIN) data, Equation 3 uses previously stored VIN data to calculate the current reference for the present moment. The current reference will lag ; the current loop will then make  lag . This can compensate the leading x-capacitor  and improve the power factor.

The delay period needs dynamic adjustment based on the input voltage and output load. The lower the input voltage and the heavier the load, the shorter the delay needed. Otherwise  will be over delayed, making the power factor worse than if there was no delay at all. To solve this problem, use a look-up table to precisely and dynamically adjust the delay time based on the operating condition.

Method #2

Since a poor power factor is caused mainly by the EMI X-capacitor , if you calculate  for a given X-capacitor value and input voltage, then subtract  from the total ideal input current to form a new current reference for the PFC current loop, you will get a better total input current that is in phase with the input voltage and can achieve a good power factor.

To explain in detail, for a PFC with a unity power factor of 1,  is in phase with . Equation 4 expresses the input voltage:

where VAC is the VIN peak value and f is the VIN frequency. The ideal input current then needs to be totally in phase with the input voltage, expressed by Equation 5:

where IAC is the input current peak value.

Since the capacitor current is , see Equation 6:

Equation 7 comes from Figure 2:

Combining Equations 5, 6 and 7 results in Equation 8:

If you use Equation 8 as the current reference for the PFC current loop, you can fully compensate the EMI X-capacitor , achieving a unity power factor. In Figure 5, the blue curve is the waveform of the preferred input current, iAC(t), which is in phase with . The green curve is the capacitor current, iC(t), which leads  by 90 degrees. The dotted black curve is iAC(t) ‒ iC(t). The red curve is the rectified iAC(t) ‒ iC(t). In theory, if the PFC current loop uses this red curve as its reference, you can fully compensate the EMI X-capacitor  and increase the power factor.

Figure 5 New current reference with iAC(t) (blue), iC(t) (green), iAC(t) ‒ iC(t) (red),and rectified iAC(t) ‒ iC(t) (red). Source: Texas Instruments

To generate the current reference as shown in Equation 8, you’ll first need to calculate the EMI X-capacitor reactive current, iC(t). Using a digital controller, an ADC samples the input AC voltage, which the CPU then reads in the interrupt loop routine at a fixed rate. By calculating how many ADC samples are in two consecutive AC zero crossings, Equation 9 determines the frequency of the input AC voltage:

where fisr is the frequency of the interrupt loop and N is the total number of ADC samples in two consecutive AC zero crossings.

To get the cosine waveform cos(2πft), a software phase-locked loop generates an internal sine wave that is synchronized with the input voltage, making it possible to obtain the cosine waveform. Use Equation 6 to calculate iC(t), then subtract from Equation 7 to get the new current reference.

Reshaping the current reference at the AC zero crossing area

These two methods let lag in order to improve the power factor; however, they may cause extra current distortion at the AC zero crossing. See Figure 6. Because of the diode bridge rectifier used in the PFC power stage, diodes will block any reverse current. Referencing Figure 6, during T1 and T2, VAC(t) is in the positive half cycle, but the expected iL(t) (the dotted black line) is negative. This is not possible, however, because the diodes will block the negative current, so the actual iL(t) remains zero during this period. Similarly, during T3 and T4, vAC(t) becomes negative, but the expected iL(t) is still positive. iL(t) also will be blocked by the diodes, and remains at zero.

Correspondingly, the current reference needs to be at zero during these two periods; otherwise the integrator in the control loop will build up. When the two periods are over and current starts to conduct, control loop generates a PWM duty cycle bigger than required, causing current spikes. The red curve in Figure 6 shows what the actual iL(t) would be with a diode bridge, and the red curve should be used as the current reference for the PFC current loop.

Figure 6 Final current reference curve where the red curve shows what the actual iL(t) would be with a diode bridge and should be used as the current reference for the PFC current loop. Source: Texas Instruments

Optimizing power factor

A poor power factor is mainly caused by the X-capacitor used in the PFC EMI filter, but it is possible to compensate for the effect of X-capacitor reactive current by delaying the inductor current. Now that you can use one of the two methods to delay the inductor current, you can combine them with guidance in Power Tips #116 to meet both a high-power factor and a low THD requirement.

Bosheng Sun is a systems, applications and firmware engineer at Texas Instruments.

Related Content

• Power tips #116: How to reduce THD of a PFC
• Power Tips #123: Using a double-boost converter to extends the power range of high-conversion-ratio designs
• Power Tips #122: Overview of a planar transformer used in a 1-kW high-density LLC power module
• Power Tips #121: Improving phase-shifted full-bridge efficiency using an active snubber

The post Power Tips #124: How to improve the power factor of a PFC appeared first on EDN.

A new system-on-chip (SoC) demonstrated at CES 2024 in Las Vegas claims to run multi-modal large language models (LLMs) at a fraction of the power-per-inference of leading GPU solutions. Ambarella is targeting this SoC to bring generative AI to edge endpoint devices and on-premise hardware in video security analysis, robotics, and a multitude of industrial applications.

According to the Santa Clara, California-based chip developer, its N1 series SoCs are up to 3x more power-efficient per generated token than GPUs and standalone AI accelerators. Ambarella will initially offer optimized generative AI processing capabilities on its mid to high-end SoCs for on-device performance under 5W. It’ll also release a server-grade SoC under 50 W in its N1 series.

Generative AI will be a step function for computer vision processing that brings context and scene understanding to a variety of devices such as security installations and autonomous robots. Source: Ambarella

Ambarella claims that its SoC architecture is natively suited to process video and AI simultaneously at very low power. So, unlike a standalone AI accelerator, they carry out highly efficient processing of multi-modal LLMs while still performing all system functions. Examples of the on-device LLM and multi-modal processing enabled by these SoCs include smart contextual searches of security footage, robots that can be controlled with natural language commands, and different AI helpers that can perform anything from code generation to text and image generation.

Les Kohn, CTO and co-founder of Ambarella, says that generative AI networks are enabling new functions across applications that were just not possible before. “All edge devices are about to get a lot smarter with chips enabling multi-modal LLM processing in a very attractive power/price envelope.”

Alexander Harrowell, principal analyst for advanced computing at Omdia, agrees with the above notion and sees virtually every edge application getting enhanced by generative AI in the next 18 months. “When moving generative AI workloads to the edge, the game becomes all about performance per watt and integration with the rest of the edge ecosystem, not just raw throughput,” he added.

The AI chips are supported by the company’s Cooper Developer Platform, where Ambarella has pre-ported and optimized popular LLMs. That includes Llama-2 as well as the Large Language and Video Assistant (LLava) model running on N1 SoCs for multi-modal vision analysis of up to 32 camera sources. These pre-trained and fine-tuned models will be available for chip developers to download from the Cooper Model Garden.

Ambarella also claims that its N1 SoCs are highly suitable for application-specific LLMs, which are typically fine-tuned on the edge for each scenario. That’s unlike the classical server approach of using bigger and more power-hungry LLMs to cater to every use case.

With these features, Ambarella is confident that its chips can help OEMs quickly deploy generative AI into any power-sensitive application ranging from an on-premise AI box to a delivery robot. The company will demonstrate its SoC solutions for AI applications at CES in Las Vegas on 9-12 January 2024.

Related Content

• Getting a Grasp on AI at the Edge
• How to Make Generative AI Greener
• Putting AI into the Edge Is a No-Brainer; Here’s Why
• How generative AI puts the magic back in hardware design
• Edge AI accelerators are just sand without future-ready software

The post Chips taking generative AI to edge reach CES floor appeared first on EDN.

While refurbishing an ageing audio mixer, I decided that the level meters needed special attention. Their rather horrible 100 µA edgewise movements had VU-type scales, the drive electronics being just a diode (germanium?) and a resistor. Something more like a PPM, with a logarithmic (or linear-in-dBs) scale and better dynamics, was needed. This is a good summary of the history and specifications of both PPMs and VU meters.

Wow the engineering world with your unique design: Design Ideas Submission Guide

It occurred to me that since both peak detection and log conversion imply the use of diodes, it might be possible to combine those functions, at least partially.

Log conversion normally uses either a transistor in a feedback loop round an op-amp or a complex ladder using resistors and semiconductors. The first approach requires a special PTC resistor for temperature compensation and is very slow with low input levels; the second usually has a plethora of trimpots and is un-compensated. This new approach, sketched in Figure 1, shows the first pass at the idea, and avoids those disadvantages.

Figure 1 This basic peak log detector shows the principals involved and helps to highlight the problems. (Assume split, non-critical supply rails.)

As with all virtual-earth circuits, the input resistor feeds current into the summing point—the op-amp’s inverting input—which is balanced by current driven through the diodes by the op-amp’s output. Because the forward voltage across a diode (VF) is proportional to the logarithm of the current flowing through it (as described here), the op-amp’s output voltage now represents the log of the input signal. Positive input half-cycles cause it to clamp low at VF, which we ignore, as this is a half-wave design; for negative ones, it swings high by 2VF.

Driving that 2VF through another diode into the capacitor charges the latter to VF, losing a diode-drops’-worth in the process. (No, the VFs don’t match exactly, except momentarily, but no matter.) The meter now shows the log of negative-input half-cycle peaks, the needle falling back as the capacitor discharges through the meter.

As it stands, it works, with a very reasonable span of around 50 dB. Now for the problems:

1. The integration, or attack time, is slow at ~70 ms to within 2 dB of the final reading.
2. The return or decay time is rather fast, about a second for the full scale, and is exponential rather than linear.
3. It’s too temperature-sensitive, the indication changing by ~5 dB over a 20°C range.

While this isn’t bad for a basic, log-scaled VU-ish meter, something snappier would be good: time for the second pass.

Figure 2 This upgraded circuit has a faster response and much better temperature stability.

A1 buffers the input signal to avoid any significant load of the source. C1 and R1 roll off bass components (-3 dB at ~159 Hz) to avoid spurii from rumbling vinyl and woodling cassette tapes. Drive into A2 is now via thermistor Th1 (a common 10k part, with a ꞵ-value of 3977), which largely compensates for thermal effects. C2 blocks any offset from A1, if used. (Omit the buffer stage if you choose, but the input impedance and LF breakpoint will then vary with temperature, so then choose C2 with care.) Three diodes in the forward chain give a higher output and a greater span. A2 now feeds transistor Tr1, which subtracts its own VBE from the diodes’ signal while emitter-following that into C2, thus decreasing the attack time. R2 can now be higher, increasing the decay time. Figure 3 shows a composite plot of the actual electronic response times; the meter’s dynamics will affect what the user sees.

Figure 3 This shows the dynamic responses to a tone-burst, with an attack time of around 12 ms to within 2 dB of the final value, and the subsequent decay.  (The top trace is the ~5.2 kHz input, aliased by the ’scope.)

The attack time is now in line with the professional spec, and largely independent of the input level. While the decay time is OK in practice, it is exponential rather than linear. 

The response to varying input levels is shown in Figure 4. I chose to use a full-scale reading of +10 dBu, the normal operating level being around -10 dBu with clipping starting at ~+16 dBu. For lower maximum readings, use a higher value for Th1 or just decrease R2, though the decay time will then be faster unless you also increase C3, impacting the attack time.

Figure 4 The simulated and actual response curves are combined here, showing good conformance to a log law with adequate temperature stability.

The simulation used a negative-going ramp (coupling capacitors “shorted”) while the live curve was for sine waves, with Th1 replaced by a 1% 10k resistor and R2 adjusted to give 100 µA drive for +10 dBu (6.6 Vpk-pk) input. I used LTspice here to verify the diodes’ performance and to experiment with the temperature compensation. (Whenever I see a diode other than a simple rectifier, I am tempted to reach for a thermistor. This is a good primer on implementing them in SPICE, with links to models that are easily tweakable. “Other compensation techniques are available.”) The meter coil has its own tempco of +3930 ppm/°C, which is also simulated here though it makes little practical difference. Just as well: might be tricky to keep it isothermal with the other temperature-sensitive stuff.

Simple though this circuit is, it works well and looks good in operation. (A variant has also proved useful in a fibre-optic power meter.) The original meters, rebuilt as in Figure 2, have been giving good service for a while now, so this is a plug-in breadboard rehash using a spare, similar, meter movement, with extra ’scoping and simulation. It’s possible to take this basic idea further, with still-faster attack, linear decay, adjustable span, better temperature compensation, and even full-wave detection—but that’s another story, and another DI.

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

 Related Content

• Audio levels, dBu, dBV, and the gang: What you need to know
• Signal Chain Basics #73: Audio metering, enjoying the VU
• Volume-unit meter spans 60-dB dynamic range
• Squashed triangles: sines, but with teeth?
• Laser simulator helps avoid destroyed diodes
• Multi-decade current monitor the epitome of simplicity

The post Simple log-scale audio meter appeared first on EDN.

Not so long ago, artificial intelligence (AI) inference at the edge was a novelty easily supported by a single neural processing unit (NPU) IP accelerator embedded in the edge device. Expectations have accelerated rapidly since then. Now we want embedded AI inference to handle multiple cameras, complex scene segmentation, voice recognition with intelligent noise suppression, fusion between multiple sensors, and now very large and complex generative AI models.

Such applications can deliver acceptable throughput for edge products only when run on multi-core AI processors. NPU IP accelerators are already available to meet this need, extending to eight or more parallel cores and able to handle multiple inference tasks in parallel. But how should you partition expected AI inference workloads for your product to take maximum advantage of all that horsepower?

Figure 1 Multi-core AI processors can deliver acceptable throughput for edge applications like scene segmentation. Source: Ceva

Paths to exploit parallelism for AI inference

As in any parallelism problem, we start with a defined set of resources for our AI inference objective: some number of available accelerators with local L1 cache, shared L2 cache and a DDR interface, each with defined buffer sizes. The task is then to map the network graphs required by the application to that structure, optimizing total throughput and resource utilization.

One obvious strategy is in processing large input images which must be split into multiple tiles—partitioning by input map where each engine is allocated a tile. Here, multiple engines search the input map in parallel, looking for the same feature. Conversely you can partition by output map—the same tile is fed into multiple engines in parallel, and you use the same model but different weights to detect different features in the input image at the same time.

Parallelism within a neural net is commonly seen in subgraphs, as in the example below (Figure 2). Resource allocation will typically optimize breadth wise then depth wise, each time optimizing to the current step. Obviously that approach won’t necessarily find a global optimum on one pass, so the algorithm must allow for backtracking to explore improvements. In this example, three engines can deliver >230% of the performance that would be possible if only one engine were available.

Figure 2 Subgraphs highlight parallelism within a neural net. Source: Ceva

While some AI inference models or subgraphs may exhibit significant parallelism as in the graph above, others may display long threads of operations, which may not seem very parallelizable. However, they can still be pipelined, which can be beneficial when considering streaming operations through the network.

One example is layer-by-layer processing in a deep neural network (DNN). Simply organizing layer operations per image to minimize context switches per engine can boost throughput, while allowing the following pipeline operations to switch in later but still sooner than in purely sequential processing. Another good example is provided by transformer-based generative AI networks where alternation between attention and normalization steps allows for sequential recognition tasks to be pipelined.

Batch partitioning is another method, providing support for the same AI inference model running on multiple engines, each fed by a separate sensor. This might support multiple image sensors for a surveillance device. And finally, you can partition by having different engines run different models. This strategy is useful especially in sematic segmentation, say for autonomous driving where some engines might detect lane markings. Others might handle free (drivable) space segmentation, and some others might detect objects (pedestrians and other cars).

Architecture planning

There are plenty of options to optimize throughput and utilization but how do you decide how best to tune for your AI inference application needs? This architecture planning step must necessarily come before model compile and optimization. Here you want to explore tradeoffs between partitioning strategies.

For example, a subgraph with parallelism followed by a thread of operations might sometimes be best served simply by pipelining rather than a combination of parallelism and pipelining. Best options in each case will depend on the graph, buffer sizes, and latencies in context switching. Here, support for experimentation is critical to determining optimal implementations.

Rami Drucker is machine learning software architect at Ceva.

Related Content

• Five AI Inference Trends for 2022
• How to Make Generative AI Greener
• Key technologies push AI to the edge
• Adding Low-Power AI/ML Inference to Edge Devices
• The Advantages of At-Memory Compute for AI Inference

The post Partitioning to optimize AI inference for multi-core platforms appeared first on EDN.

I learned to drive in 1966 when I lived in Nashua, New Hampshire. At that time, it was a major traffic violation to drive a car with “dazzling lights”. That piece of common sense seems to no longer apply in this modern era.

This front-page article in Figure 1 was recently published in our local newspaper, Newsday.

Figure 1 Front page of a recent issue of Newsday highlighting the hazards of bright LED headlights.

The article’s author describes the extremely dangerous issue of visual interference being experienced by drivers here on Long Island, but elsewhere as well in my own opinion.

Just as an example, this second image in Figure 2 was captured in a local diner. I was having dinner, and I could see my chicken cutlet, but the visual impact of high brightness LEDs from a nearby business is self evident.

Figure 2 The glare from high brightness headlights in a local Long Island diner.

I wrote an e-mail to the Newsday article’s author as shown below. I allowed myself to vent a little, but the issue is of grave concern to me. The email can be seen in Figure 3.

Figure 3 A letter from myself (John Dunn) to the editor of the “Glaring Issue on LI Road” article published in Newsday.

There is another LED abuse being committed by some homeowners as illustrated below in Figure 4.

Figure 4 Abusive lighting from nearby home blinding neighbors, pedestrians, and passing traffic.

This form of abuse has been enabled by the ready availability at Home Depot, Ace Hardware and so forth, of LED light sources with 5000°K color temperature. Light being emitted from such fixtures can be highly penetrating and intrusive. By comparison, LED illumination at a color temperature of 2700°K to 2800°K approximates the color temperature delivered by an incandescent lamp. Such lighting doesn’t tend to cause visual stress.

The lights shown in Figure 4 have are being turned on roughly an hour after sunset and are allowed to remain lit until 10 or 11 PM. If they were any part of a security system, they would be lit all through the night to facilitate camera imaging, but they’re not. For a variety of unrelated reasons, I submit that these lights are being used as a tool for neighborly harassment.

To me, this is a form of trespass, but there is no way of my awareness to restrain such behavior. With merely the flick of a switch, the glaring light is imposed on its intended victim. To my knowledge, there are no laws governing such misanthropy and even if there were such laws, there would be no way to achieve effective enforcement.

The only practical remediation I can imagine would be the discontinuation of 5000 °K LED products. Quartz halogen lamps and high wattage incandescent lamps have been recently discontinued for good reasons so I see no reason why that logic should not be further applied.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• The headlights and turn signal design blunder
• Headlights and turn signals, part two
• The ‘too brights’
• LED tail lights
• Preventing deformed light-bulb filaments

The post The dangers of light glare from high-brightness LEDs appeared first on EDN.

Cyber resilience has long been a key focus for industry leaders, but the stakes have been raised with the rapid acceleration of quantum computing. Quantum computing is a cutting-edge innovation that combines the power of computer science, physics, and mathematics to rapidly perform complex calculations outside the realm of classical computing. Expected to be commercialized by 2030, it offers incredible potential to further digitalize key industries and redefine the role technology plays in geopolitics. The possibilities of the post-quantum era cannot be understated.

While quantum computing can positively serve humanity in a myriad of ways, it also brings concerning cybersecurity threats. In turn, the U.S. government and security leaders have called for accelerated post-quantum cryptography (PQC) migration. President Biden signed the Quantum Computing Cybersecurity Preparedness Act after visiting IBM’s quantum data center in October 2022. In addition, NIST, CISA, and NSA recently advised organizations to develop PQC readiness roadmaps.

The message is clear: quantum-powered cyberattacks are of growing concern, and maintaining resilience in the face of this new threat is different than anything we’ve faced before.

Breaking down the threat

Quantum computing’s biggest double-edged sword is its ability to quickly and easily solve complex algorithms intended to safeguard systems and data. Quantum computers are exceptionally fast, utilizing specialized hardware components that leverage quantum physics to outpace current supercomputing technology.

For example, IBM and UC Berkeley recently collaborated on a quantum computer that performs calculations quicker and more accurately than supercomputers at Lawrence Berkeley National Lab and Purdue University. While this newfound speed might seem like a good thing, it’s also exceedingly dangerous.

Additionally, quantum computers have an innate ability to compromise legacy public key infrastructure (PKI) cryptographic algorithms, the type of algorithms utilized by most of today’s classical computing systems. By leveraging Shor’s Algorithm, quantum computers are able to factor and then decipher these PKI-based algorithms and bypass security controls.

Between their unmatched speed and ability to compromise most of the security measures utilized today, quantum computers are a huge threat to modern enterprises and, as such, new quantum resistant PKI encryption and cyber resiliency solutions are needed to mitigate risk.

Post-quantum cryptography

Due to the imminent threat of quantum computing, we’re seeing more and more organizations adopt post-quantum cryptography (PQC). At its core, PQC migration is about shifting away from legacy PKI-based cryptography to post-quantum cryptography that will be resilient to quantum computer attacks.

It’s worth noting here that bad actors are adopting a ‘steal now, decrypt later’ stance that puts significant confidential data stored on the cloud today at risk of future disaster as more and more capable quantum computers come online.

The shift to PQC is necessary and timely, especially since the existing security standards many organizations use today do not implement PQC infrastructure that protects against quantum computing attacks. For example, widely used security standards like Trusted Platform Modules (TPMs), IEC 62443, and ISO/SAE 21434 do not require PQC algorithms. Systems and devices built today to these specifications will not have what is needed in the future to be quantum safe.

While the transition to PQC won’t be immediate, we’re making exceptional progress. The U. S. National Institute of Standards and Technology (NIST) is in the process of an ongoing competition to find the best PQC algorithms to replace legacy PKI algorithms. The trials started in 2016 and, in July 2022, they announced four candidates for standardization, plus additional candidates for a fourth round of analysis. These four candidates—as well as the fourth-round selection—will become the new NIST-approved encryption standards.

Implementing PQC at scale

With quantum computers likely arriving sooner than anticipated, organizations must start constructing their own PQC migration roadmaps to build resilience for post-quantum attacks. NIST’s first standardized PQC algorithms are expected to be ready in 2024; however, organizations must begin making changes to their production and manufacturing efforts now to streamline migration once available. Through the integrated adoption of field programmable gate arrays (FPGAs), organizations can position themselves to facilitate PQC migration for a post-quantum future now.

FPGAs contain “crypto agile” capabilities that deliver enhanced protection. With flexible programmability and parallel processing functions, they can enable developers to easily update existing systems and hardware with new PQC algorithms for adherence to evolving standards. Further, FPGAs accelerate complex mathematical functions to enhance system performance and protection.

While quantum computing’s potential to revolutionize our world is massive, it’s overshadowed by the technology’s dangerous ability to dismantle cybersecurity and encryption. As we enter this new post-quantum world, cyber resilience is taking on a new meaning, one that demands our unwavering commitment to securing our systems, data, and infrastructure in the face of quantum-powered challenges. Now, maintaining resilience means implementing post-quantum cryptography facilitated by FPGAs to withstand attacks from quantum computers.

The need for PQC cannot be emphasized enough and it’s imperative that governments, industries, and organizations actively collaborate to implement solutions, such as those available today with FPGAs that safeguard our digital future from quantum-powered threats.

Eric Sivertson is VP of security business at Lattice Semiconductor.

Related Content

• The Basics Of Quantum Computing
• Post-Quantum Cryptography: Are You Ready?
• Securing the Internet of Things in a Quantum World
• Hardware security entering quantum computing era
• U.K. Conference Accelerates Post-Quantum Cryptography Standards Review Process

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Ceva is bolstering its RivieraWaves portfolio of wireless connectivity IP with Wi-Fi 7 IP for high-end consumer and industrial IoT applications. Incorporating both PHY and MAC functions, the Wi-Fi 7 IP is available now for access points, with an optimized station implementation slated for later this year.

The embeddable IP leverages the key features of the IEEE 802.11be standard, including 4K quadrature amplitude modulation (QAM), multi-link operation (MLO), and multiple resource units (MRUs). 4K QAM provides a substantial increase in throughput compared to the 1K QAM of Wi-Fi 6. MLO introduces dynamic channel aggregation, seamlessly combining heterogeneous channels from the same or different bands to navigate interference and boost throughput. MRU stitches together punctured or disjointed resource units within the same band to increase throughput and reduce latency.

Other features of the RivieraWaves Wi-Fi 7 IP include:

• 2×2 MU-OFDM(A) transmitter and receiver supporting 802.11be, up to MCS13-2SS
• 2×2 MU-MIMO for client-dense environments
• Beamforming to maximize link budget in multi-antenna systems
• Full MAC software stack, supporting the latest security standards including WPA3 and China’s WAPI
• Compatible with the EasyMesh standard for interconnectivity between different APs
• Advanced Packet Traffic Arbiter (PTA) functionality for Wi-Fi & Bluetooth connectivity coexistence

RivieraWaves Wi-Fi 7 IP is backward-compatible with previous Wi-Fi generations. It employs a flexible RF interface that enables integration with radio circuitry from multiple Ceva partners or a licensee’s own radio technology.

For more information on the RivieraWaves Wi-Fi IP portfolio, click here.

Ceva

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A DDR5 registering clock driver (RCD) from Rambus, the RCD4-GA0A boosts data rates to 7200 MT/s, a significant increase over DDR5 devices operating at 4800 MT/s. Intended for registered DIMMs, the driver chip can accelerate performance in generative AI and other advanced data-center workloads.

The RCD4-GA0A supports a clock rate of up to 3.6 GHz, corresponding to its data rate of up to 7200 MT/s. It also accommodates double data rate (DDR) and single data rate (SDR) buses, providing clocks and command/address (CA) signals to the DRAM devices in registered DIMMs. The driver supports two independent subchannels per registered DIMM and two physical ranks per subchannel. For high-capacity registered DIMMs, the driver supports up to 16 logical ranks per physical rank.

Rambus began sampling the RCD4-GA0A registering clock driver to major DDR5 memory module manufacturers during the fourth quarter of 2023. The company also offers a serial presence detect (SPD) hub and temperature sensor for use with its DDR5 RCDs.

For more information about the Rambus lineup of DDR5 chips, click here.

Rambus

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Two 600-V N-channel super-junction MOSFETs from Alpha & Omega incorporate a body diode for robustness and fast reverse recovery. Based on the company’s aMOS5 technology, the AOK095A60FD (TO-247) and AOTF125A60FDL (TO-220F) provide an on-resistance of 95 mΩ and 125 mΩ, respectively.

The power MOSFETs are optimized to meet the high-efficiency needs of DC/DC converters (LLC, PSFB, TTF) and solar inverters. aMOS5 FETs are engineered with a strong intrinsic body diode to handle hard commutation scenarios. This proves useful during abnormal conditions such as short circuits or start-up transients, where the freewheeling body diode operates in reverse recovery mode.

In tests conducted by Alpha & Omega engineers, the body diodes of the AOK095A60FD and AOTF125A60FDL survived high di/dt under abnormal system conditions, even at elevated junction temperatures of up to 150°C. Tests also showed that the devices’ turn-off energy is noticeably lower than competing devices, which contributes to higher efficiency under light or mid-load conditions.

Both parts are available now in production quantities, with a lead time of 16 weeks. The AOK095A60FD and AOTF125A60FDL cost $3.75 and $3.22 each, respectively, in lots of 1000 units.

AOK095A60FD datasheet

AOTF125A60FDL datasheet 

Alpha & Omega Semiconductor 

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Simplifying device interoperability, Murata’s Type 2FR tri-radio connectivity module supports Matter over Wi-Fi, Matter over Thread, and Matter over Ethernet. The module integrates NXP Semiconductors’ RW612 wireless MCU in a 12×11-mm package that is approximately 50% smaller than a discrete implementation.

Well-suited for smart home devices and appliances, as well as industrial automation and smart city applications, the Type 2FR supports various communication protocols. These include dual-band 2.4 GHz/5 GHz Wi-Fi 6, Bluetooth Low Energy 5.3, IEEE 802.15.4 for low-rate wireless networks, and Ethernet.

Along with a 260-MHz Arm Cortex-M33 core, 1.2 MB of RAM, and 16 MB of flash memory, the module features NXP EdgeLock security technology. EdgeLock offers secure boot, debug, and firmware updates, as well as hardware cryptography. Additionally, NXP MCUXpresso software tools help speed development and reduce time-to-market.

Murata will showcase the Type 2FR tri-radio module at next week’s CES 2024 trade show. Samples will be available at the same time. A datasheet was not available at the time of this announcement.

Murata

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BrainChip will demonstrate its Akida neuromorphic processor enabled by Microchip’s embedded 32-bit processor boards at next week’s CES 2024 trade show. The company will display the ability of Akida, running on Microchip’s SAMx71 Ultra and SAMA7G54-EK boards, to perform always-on machine learning tasks, such as keyword spotting and visual wake words.

Keyword spotting leverages neural networks to recognize keywords, like “Hey Siri.” Visual wake word detection classifies the presence of individuals in images for such applications as in-home security and smart doorbells.

“We look forward to demonstrating the potential and ease of integrating Akida for always-on machine learning applications on embedded devices at CES,” said Rob Telson, VP of Ecosystem and Partnerships at BrainChip. “By combining our innovative neuromorphic processor and models with Microchip’s high-performance MPUs and boards, you can deliver compelling solutions to the market to serve the rapidly growing demand for TinyML at the edge.”

Rod Drake, corporate VP of Microchip’s MPU32 and MCU32 business units, added, “In this collaborative showcase with BrainChip, we will illustrate how our customers can leverage the advantages of next-generation AI to enable low-power, high-performance machine learning applications on our embedded platforms.”

BrainChip Holdings 

Microchip Technology 

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