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Ordinary bipolar junction transistors can sometimes be precision sensors.

When you think of precision components, you usually don’t (and probably shouldn’t) think of general-purpose bipolar junction transistors.  Are GP BJTs cheap and versatile?  Unquestionably yes.  But are their characteristics, current gain, bias voltage, etc., precise and predictable to a fraction of a percent?  Sadly (and maybe even laughably) no.  But not entirely so.  A dramatic exception is the ΔVbe effect, in which ordinary small signal BJTs can function in simple circuits as 0.1% precision absolute temperature sensors, as shown in an earlier Design Idea.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The  ΔVbe effect depends solely on the ratio of applied currents, independent of their absolute magnitudes.  It has an amplitude of 1/5050 volts per Kelvin and 1/9090 volts per Rankine per current ratio decade.  Figure 1 shows how this simple math can be exploited to turn most any 3 ¾ digital multimeter with a 300mV range into a versatile and accurate 0.1° resolution thermometer switchable between Celsius and Fahrentheit scales:

Figure 1 Switch U1a and current mirror Q2Q3 apply an excitation current ratio of 10.23:1 to the 9-sensor transistor string.  The string is tapped at 5 x 200uV/°C = 1mV/°C and 9 x 111uV/°F = 1mV/°F.

Here’s how it works. Multivibrator U1b and switch U1a drive current mirror Q2Q3 with a square wave current signal.  Its two states have a precise ratio of 101.01 = 10.23:1.  The current mirror applies this signal to the 9-transistor temperature sensing string.  There, the ΔVbe effect causes each transistor to develop 200uV per Kelvin and 111uV per Rankine, summing to 1mV/°K at the 5-transistor tap and 1mV/°R at the 9-transistor tap.

The S1a section of the DPDT switch S1 allows appropriate tap selection for the desired temperature scale.  Meanwhile, the S1b section selects the appropriate Z1 derived 0° offset: 273mV for Celsius and 460mV for Fahrenheit. The D1R6 dummy load balances the currents passed by the two sides of the U1a switch, equalizing its Ron voltage losses.  Current mirror lovers will no doubt notice that the Q2Q3 mirror, consisting as it does of unmatched transistors with no emitter degeneration, probably lacks an accurate gain ratio. But that’s okay.  It doesn’t need one.

Remember that the ΔVbe effect depends solely on the ratio of applied currents and is unaffected by of their absolute magnitudes.  So the mirror’s gain can vary over a wide range without significantly affecting temperature measurement accuracy.  V+ can likewise wander harmlessly from 7 to 20 volts.  A simple 9 volt battery will therefore work well and, since the total current draw is less than 2mA, will last for hundreds of hours of continuous operation.

Multivibrator U1b provides asymmetrical ~7kHz timing for synchronous sensor excitation and precision AC signal rectification by U1c.  Asterisked resistors should be +/- 0.1% precision types to preserve accuracy.

Yes.  Those ordinary dime-a-throw GP BJTs are really that good.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content 

• ΔVbe thermometer outputs 1mV/°C without calibration or op amps
• ΔVbe + DMM = Celsius, Kelvin, Fahrenheit, and Rankine thermometer
• BJT is accurate sensor for absolute temperature in Kelvin and Rankine
• Temperature compensation with a simple resistance temperature detector
• A temperature-compensated, calibration-free anti-log amplifier

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Implementation of software-defined vehicles (SDV) has changed significantly over the past decade, but the need for in-field upgrades and new features has remained constant. As OEMs move from legacy architectures to SDVs, they will need to add new capabilities over time to deliver a more differentiated user experience.

At the same time, ECU consolidation and the need for more headroom for future use cases are increasing compute demands. Microcontroller unit (MCU) manufacturers have responded by moving to smaller process nodes, enabling higher performance in a more cost-effective way.

However, while MCUs are evolving fast, memory—embedded non-volatile memory (eNVM) in particular—is being left behind. In many cases, memory still relies on outdated specifications from the days of distributed architectures, where most ECUs never saw firmware upgrades after release.

This creates an important question for the auto industry. If vehicles are expected to receive in-field bug fixes, performance improvements and entirely new features over time, is your SDV’s eNVM ready?

How SDVs shape the customer experience

Before we answer this question, it’s important to consider how SDVs shape the customer experience. Faster over-the-air (OTA) updates mean less vehicle downtime, lower power use during the update and a lower battery state-of-charge (SoC) requirement while starting an OTA upgrade process. When issues are found, the ability to deliver fixes quickly reduces customer frustration and improves confidence in the vehicle.

With the right technology, SDVs can also offer a lower total cost of ownership while improving the overall experience. But for that to be achieved, it needs to be easier for SDVs to support larger applications, more data-heavy features and ongoing software updates without driving up memory needs or development cost.

In short, the platform must support frequent improvements without getting in the way of the vehicle’s long-term success, and that means more efficient eNVM is required.

Specifications that need to be addressed

There are two eNVM specifications that impact user experience and total cost of ownership: endurance and write speed (write time and erase time).

Endurance determines how many times memory can be rewritten over the life of the vehicle. In today’s MCUs, code memory is often rated for about 1,000 write cycles, while data memory, which is usually a very small subset of total eNVM, is typically rated for around 100,000. Those limits have changed very little over time, even though SDVs now depend on frequent updates, bug fixes and new features delivered long after launch. As update demands increase, higher endurance becomes essential.

Page size also matters. Many eNVMs only support page-level writes, which means updating even a single byte require rewriting an entire page, which can typically be sized between 64 bytes to 512 bytes. That increases wear, wastes memory and adds software complexity, especially when page sizes are large.

For SDVs to support more data-intensive use cases over time, memory needs to offer much higher endurance along with smaller page sizes or byte-level write capability. That reduces memory overhead, simplifies software design, and makes future upgrades far more practical.

Impact of temperature on endurance and retention

In eNVM technologies, temperature matters just as much as raw endurance and retention. That’s because eNVM hardware can degrade when writes happen at high temperatures, which is a real concern for vehicles receiving OTA updates. A car parked in extreme summer heat may still need a firmware update, for example, and customers should not have to worry about whether the vehicle is too hot to update safely. For SDVs, memory needs to deliver reliable endurance and data retention across the full operating temperature range over the life of the vehicle.

Write and erase times also have a direct impact on the customer experience. In many eNVM technologies, memory must be erased before it can be rewritten, and erase times are often even longer than write times.

That may have been acceptable when programming mainly happened in the factory, but in SDVs it can mean longer update times, more downtime, and added software constraints during normal vehicle operation. Faster writes and eliminating the need for erase cycles would make updates quicker, reduce performance penalties, and simplify software design.

Why MRAM stands out

When comparing embedded memory options for SDVs, including embedded charge-trap flash, PCM, RRAM and MRAM, the key question is which technology can best support frequent updates, long life, and a good customer experience. MRAM stands out because it addresses many of the limitations of older embedded non-volatile memory technologies. It can support scalable memory sizes at smaller technology nodes like 16 nm, needed for zonal, domain and consolidated vehicle architectures, while remaining practical from a cost and reliability standpoint.

MRAM works differently from traditional memory technologies. Instead of storing data through charge, material movement or phase change, it stores data using magnetic states. That matters because magnetic storage does not wear out in the same way as many other non-volatile memory approaches.

As a result, MRAM is well suited for the durability, update frequency, and long-term reliability that SDVs require. MRAM supports 20 years of data retention at 150⁰C ambient temperature, well within the requirements of today’s automotive applications.

Figure 1 MRAM stands out because it addresses several limitations of older embedded non-volatile memory technologies. Source: NXP

A solution that meets the needs of SDVs

MRAM is also a strong fit for SDVs because it combines very high endurance with fast write speeds, up to 20 times faster write speed than traditional embedded memory. Unlike many other embedded memory technologies, it does not require an erase step before writing, which helps enable much faster updates and reduces vehicle downtime.

Its endurance is high enough to support frequent firmware updates and heavy data writes up to 1 million cycles with little or no need for wear leveling in most use cases. Just as importantly, its performance and retention remain reliable over the full life of the vehicle.

These strengths also make new SDV use cases more practical. MRAM, with its fast write and high endurance capabilities can enable new use cases, especially data-intensive applications such as AI and machine learning. It also makes it easier to load software dynamically based on how the vehicle is being used.

In short, MRAM-based MCUs help automakers deliver faster updates, support more flexible software architectures, and add new capabilities over time without compromising the customer experience.

Figure 2 The MRAM-based MCUs like S32K5 help automakers deliver faster updates, support more flexible software architectures, and add new capabilities. Source: NXP

Put simply, underlying hardware technology, and eNVM in particular, must evolve to unlock the true potential of SDVs. Memory write speed and endurance can be make-or-break capabilities for a competitive user experience and the ability to rollout new features consistently. MRAM, with its crucial improvements to endurance and speed, is the eNVM technology truly capable of bringing this SDV vision to life.

Sachin Gupta is senior director of sales and business development for automotive at NXP Semiconductors.

Related Content

• MRAM debut cues memory transition
• The Rise of MRAM in the Automotive Market
• MRAM, ReRAM Eye Automotive-Grade Opportunities
• MRAM Maker Everspin Remembers Its Industrial Roots
• Architectural opportunities propel software-defined vehicles forward

The post Making the case for MRAM in software-defined vehicles appeared first on EDN.

The Design, Automation & Test in Europe (DATE) Conference in Verona in April showed an EDA research community moving with real momentum into the AI era. The strongest signal from the conference was that AI is no longer a separate topic sitting beside chip design. It’s now shaping the workloads, architectures, design tools, verification flows, and security questions that will define the next phase of semiconductor development.

The conference was upbeat because the direction is clear and the opportunity is substantial. Heterogeneous compute, RISC-V, chiplets, AI accelerators, agentic EDA, structured specifications, and AI-assisted verification are all advancing at the same time. The challenge is significant: these systems must be designed, verified, secured, and trusted.

However, DATE 2026 showed that the research community is already developing the methods, tools, and flows needed to address that challenge. For Europe, the opportunity is not simply to catch up with existing EDA capability, but to help lead the next wave of AI-enabled, verification-aware, and trustworthy semiconductor design.

This also re-frames the European sovereignty discussion. There are three distinct parts: sovereignty in processor design, sovereignty in EDA tools, and sovereignty in next-generation AI+EDA capability. Processor design is being opened up by RISC-V, chiplets and design-enablement platforms.

EDA-tool sovereignty is more challenging, because advanced-node signoff depends on mature commercial tools, process design kits (PDKs), verification IP, and foundry-qualified flows. The strongest near-term opportunity is therefore AI+EDA capability: building the methods, benchmarks, structured specifications, secure deployment models, and verification-aware AI flows that will define the next generation of design automation.

Conference context and program messaging

DATE 2026 provided a useful view of where semiconductor research is moving as AI, EDA, advanced architectures, verification, and security begin to converge. DATE is not the Design and Verification Conference (DVCon), with its practitioner focus on verification methodology and commercial tool use. It is not the Design Automation Conference (DAC), where the exhibition floor is often as important as the technical program. DATE is research-led, with the papers, focus sessions, tutorials, keynotes, and European project sessions forming the center of gravity.

That research-led character matters. It makes DATE a good indicator of topics that are still forming before they become mature tool flows or standard industry practice. The commercial ecosystem was clearly present with Cadence, Synopsys, Qualcomm, Arm, Infineon, Micron, STMicroelectronics, Tenstorrent, Axelera AI, Real Intent, and others represented in the sponsor list. However, the tone was less product marketing and more ecosystem development.

A key takeaway was that AI is now present as a workload, a design objective, a design-assistance technology, a verification challenge, and a security risk. The individual sessions differed in emphasis, but the common thread was the same: the next phase of EDA will be shaped by the interaction between AI, heterogeneous architectures, verification, security, and trust.

DATE 2026 included 325 regular papers and 91 extended abstracts across the D, A, T, and E research tracks, giving 416 accepted research-track outputs. The program offered 41 main technical sessions, three Best Paper Award candidate sessions, two late-breaking-result sessions, five keynotes, 10 focus sessions, five workshops, four special-day sessions, and four embedded tutorials.

The geographical distribution was also significant. DATE is European in location and culture, but the research paper base reflects the global semiconductor research map. By country-affiliated appearances in technical paper-like entries, China, plus Hong Kong and Taiwan, accounted for 247 appearances, or 44.7%. Europe, plus the U.K., accounted for 133 appearances, or 24.1%. The U.S. accounted for 94 appearances, or 17.0%, with the rest of the world at 79 appearances, or 14.2%.

Using a broad classification, roughly 27% of the technical country-affiliated appearances had some AI connection. Most of this was hardware-for-AI: accelerators, compute-in-memory, large language model (LLM) inference, edge AI, photonic AI, and memory systems. AI applied directly to verification, test generation, fuzzing, coverage, and security validation was closer to 2.7% of the technical program. This shows that AI-for-verification is currently a specialist part of the larger AI-related research activity.

AI as workload, tool, and risk

The opening keynote from Luc Van de Hove of IMEC set out one of the central pressures: AI models are evolving faster than semiconductor hardware development, creating bottlenecks that require new compute architectures and semiconductor platforms. In this framing, AI is a key demand changing the hardware stack.

At DATE, AI appeared in at least four roles. First, AI is the workload driving accelerators, compute-in-memory structures, chiplets, photonics, and energy-efficient platforms. Focus session FS02, “Architecting Intelligence: Next-Gen Acceleration for Generative AI,” and TS36, “Next-Generation Memory Systems for AI Acceleration,” were good examples. Second, AI is becoming a design tool, with LLMs, agents, and machine-learning-driven optimization applied to routing, placement, high-level synthesis (HLS), analog sizing, and lithography simulation.

Third, AI is changing the research process itself, as raised in the keynote from Rolf Drechsler from the University of Bremen in Germany. Fourth, AI is becoming a security and trust problem, since AI-guided verification tools can introduce risks such as adversarial manipulation, biased test generation, or hallucinated security guidance.

The AI-for-EDA message was therefore not simply that AI will automate design. AI can accelerate parts of the design and verification flow, while also creating systems and flows that are harder to verify, explain, secure, and certify.

Future platforms are heterogeneous

A repeated architectural message was that general-purpose compute is no longer sufficient for many target workloads. The program included strong content on AI accelerators, chiplets, 3D integrated circuits (3DIC), RISC-V vector extensions, photonic accelerators, quantum and high-performance computing (HPC) coupling, FPGAs, high level synthesis (HLS), open chiplet ecosystems, and domain-specific processors.

RISC-V appeared prominently as an instruction set architecture (ISA), especially where openness, customization, and verification interact. It appeared in open-source cores such as Rocket, BOOM, XiangShan, and Snitch; in vector-extension verification; in processor fuzzing; in cryptographic accelerators; in SoC security; and in lightweight wearable systems. This is consistent with the broader RISC-V opportunity: the open ISA makes architectural experimentation easier but also increases the verification responsibility for each implementation and extension.

The Cornell University keynote by Zhiru Zhang on accelerator design and programming described a familiar problem. Performance and efficiency increasingly come from specialized accelerators, but there is a widening gap between how accelerators are designed and how they are programmed. That gap is an EDA problem because the design flow needs to connect architecture, programmability, verification, performance estimation, and software maintenance.

Quantum was also treated as a systems topic rather than as isolated physics. Nvidia’s Bettina Heim described NVQLink, coupling GPU real-time processing with quantum processors at sub-microsecond latency for error correction and control. A focus session covered MLIR, QIR, and intermediate representations for quantum-classical compilation. The point for EDA is that quantum-classical systems create problems in compilation, control, architecture, timing, and verification. These are recognizable EDA problems, even if the devices are different.

Verification and security become first-class constraints

The third major theme was the convergence of verification, security, and open ecosystems. DATE treated verification and security as part of the same scalability problem. As systems become heterogeneous, AI-driven, and assembled from chiplets and third-party IP, functional correctness, security validation, explainability, and certification overlap.

The verification panel (session FS06), “Who Is Best Suited to Do Verification?”, framed rising re-spin rates and verification cost as a central industry problem. The hardware security focus session argued that heterogeneous SoCs, CPUs, and accelerators create attack surfaces too large for manual analysis alone. The AI-for-verification thread included coverage-driven test generation, reinforcement-learning-guided concolic (concrete + symbolic) testing, processor fuzzing, SystemVerilog Assertion (SVA) generation, and agentic security assistants.

This work is still emerging. However, the direction is clear: verification needs more automation, and that automation needs to be tool-grounded, measurable, and traceable. A generated test, assertion, or security recommendation is useful only if it connects to coverage, formal results, simulation results, reviewable traces, or other engineering evidence.

AI for RTL and verification

A specialist but important cluster was AI applied to register-transfer level (RTL) design. This included LLM-generated Verilog, closed-loop RTL repair, multi-agent design flows, HLS-to-RTL pathways, and benchmark contamination. The volume was small, roughly 2-3% of the technical program, but the technical direction was important.

The field has moved beyond asking an LLM to write Verilog. The more credible flows put verification in the loop: generate RTL, run checks, estimate correctness, repair errors, and preserve equivalence. VeriBToT (session TS07.1) combined self-decoupling and self-verification for modular Verilog generation.

EstCoder (TS22.9) used a collaborative agent flow with a functional-estimation agent scoring generated RTL before accepting or correcting it, reporting up to 9% improvement in RTL correctness. LiveVerilogEval (TS29.1) addressed benchmark contamination and found that LLM performance degraded significantly on dynamically generated benchmarks, suggesting that static benchmarks may have overstated current capability.

The sponsor-hosted executive session on EDA agentic AI provided a useful industrial view. Agentic AI is moving from demonstrations toward production flows with RTL checking and fixing, specification-to-testbench construction, and synthesis-to-GDSII flows identified as near-term use cases. The hard constraints are determinism, traceability, IP protection, tool integration, and signoff confidence.

The AI-for-verification work showed the same pattern. The best examples were closed-loop and tool-grounded, not generic prompt-based test generation. ChatTest (TS22.7) used a multi-agent LLM framework with a structured Verification Description Language (VDL), retrieval-augmented generation, and a coverage-feedback loop. It reported 1.46 times higher toggle coverage, 2.28 times higher line coverage, and a 24.23% improvement in functional coverage across 20 complex RTL designs. CoverAssert (TS40.10) used functional coverage feedback to guide LLM generation of SVAs.

Processor fuzzing gave another important example. SimFuzz (TS40.6) applied similarity-guided block-level mutation to RISC-V processors Rocket, BOOM, and XiangShan, finding 17 bugs, including 14 previously unknown issues and seven CVE-assigned bugs affecting decode and memory units.

This connects to GhostWrite (CVE-2024-44067), a RISC-V vector-extension implementation bug in T-Head XuanTie processors that allowed unprivileged code to write arbitrary physical memory. GhostWrite was not a side channel. It was a direct architectural flaw, and the mitigation required disabling the vector extension. This is a strong argument for structure-aware, security-directed processor verification.

AI-generated SVAs also appeared in several forms. PALM (TS07.6) investigated LLM assistance for valid SVAs in security verification, while CoverAssert (TS40.10) and AutoAssert (TS02.5) extended coverage-driven, LLM-assisted assertion generation with formal verification feedback. This seems to be the right near-term role for AI in formal verification: assistant and accelerator, not replacement for formal reasoning.

Agentic AI and structured specifications

The most visible emerging pattern in AI+EDA was the movement from single-shot prompting to multi-agent, tool-grounded, feedback-driven workflows. The focus session (FS07) “From Concept to Silicon: End-to-End Agentic AI for Smarter Chip Design” made this explicit across HLS, physical design, testing, and security verification.

The Nexus paper presented by PrimisAI (session SD01.1) framed the engineering problem clearly. EDA workflows need reliability and traceability, and weak coordination and unstructured communication are bottlenecks for multi-agent deployment. Nexus reported 100% accuracy on RTL generation tasks in VerilogEval-Human and nearly 30% average power savings on Verilog-to-routing (VTR) timing-optimization benchmarks.

AgenticTCAD (TS41.6) applied a natural-language-driven multi-agent system to TCAD device optimization, achieving IRDS-2024 specifications for a 2-nm nanosheet FET within 4.2 hours, compared with 7.1 days for human experts.

The key point is that agentic AI wraps the LLM in an engineering process. The flow is to decompose the task, call EDA tools, inspect reports, measure quality, repair errors, and iterate. That is much more credible for EDA than single-shot generation.

Two structured-language examples were also notable. The first was the Universal Specification Format (USF), a formal specification format (in session TS24.3) with unambiguous syntax and semantics able to generate formal properties and behavioral simulation models.

The second was Verification Description Language (VDL), introduced in ChatTest (TS22.7), which captures I/O pins, timing, functional coverage targets, stimulus sequences, checkpoints, and boundary conditions in YAML format. These are early signs that AI-assisted EDA may require better intermediate representations, not only better models.

European sovereignty and the next EDA wave

European semiconductor sovereignty was an undercurrent throughout DATE 2026, but it needs to be framed carefully. Semiconductor sovereignty is not about becoming completely self-sufficient, it is about reducing dangerous dependencies on other geographic regions. There are several separate questions, for example: sovereignty in processor design, sovereignty in EDA tools, and sovereignty in next-generation AI+EDA capability.

For processor design, the RISC-V activity, open chiplet ecosystems, and European design-enablement platforms such as the cloud-based makeChip point in a useful direction. However, first-time-right silicon still depends heavily on commercial EDA tools, qualified PDKs, verified sign-off flows, and high-quality verification IP. A realistic sovereignty strategy means sovereign design competence and secure access to the best tools, not an assumption that open-source-only flows can replace the commercial stack.

For EDA-tool sovereignty, open-source EDA is strategically valuable for education, research, reproducibility, open PDKs, and lowering barriers for small and medium-sized enterprises (SMEs) and universities. However, advanced-node commercial EDA represents decades of investment in algorithms, foundry relationships, sign-off maturity, and customer regression infrastructure.

The keynote by Luca Benini of the University of Bologna in Italy on democratizing silicon made the positive case for broader access, but open-source EDA is a supplemental and educational platform, not a near-term substitute for advanced-node sign-off.

The more compelling opportunity is next-generation AI+EDA. DATE 2026 showed that this area is still being defined. Agentic workflows, AI-assisted verification, coverage-driven test generation, formal and SVA support, open benchmarks, trustworthy AI, structured specification languages, and secure on-premise model deployment are all areas where research depth and engineering discipline matter.

Europe has strong universities, safety-critical application domains, active RISC-V and open-source hardware communities, and the policy framework of the EU Chips Act. That combination is well suited to shaping the next EDA wave.

The strongest form of European sovereignty is not isolation. It is capability: the ability to design, verify, secure, and understand the systems Europe depends on. DATE 2026 showed that the future of EDA will require new compute architectures, better verification methods, more automation, structured specifications, stronger security methods, and a clear understanding of where AI helps and where it introduces new risks. These are exactly the problems that a research-led, ecosystem-focused community should be able to address.

DATE 2026 was therefore not just an EDA conference about AI in chip design. It was a useful indication that the next phase of EDA will be defined by the interaction between AI, heterogeneous architectures, verification, security, and trust. The next step is to turn these research directions into reliable engineering flows.

Simon Davidmann is an EDA industry pioneer and serial technology entrepreneur with over 40 years of experience in simulation and verification. His career has been instrumental in shaping the foundational languages and methodologies used in modern chip design, particularly those now critical for AI/ML hardware. Davidmann was the co-creator of Superlog that became SystemVerilog. After selling Imperas to Synopsys in 2023 and being Synopsys VP for Processor Modeling & Simulation, he left Synopsys and is now an AI + EDA researcher at Southampton University, UK.

Editor’s Note

DATE 2026 was held on 20-22 April 2026 in Verona, Italy. The conference program is available at https://www.date-conference.com/programme. Specific session labels are noted in parentheses in the article.

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The post The next EDA wave: Lessons from DATE 2026 appeared first on EDN.

A subtle change to a standard circuit can enhance its usefulness—and even save a resistor.

If there were a prize for the most trivial Design Idea (DI) of the year, this one would likely be high on the shortlist (if not at the top). Most DIs involve adding components to circuits to improve them; this time we’re removing one. Circuits for line drivers, balanced or not, are ten a penny, but this variant has a surprising twist: surprising because it’s so simple and, when you look at it, obvious, though I can’t find it in any published schematic, even those from National Semiconductor’s golden days.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 presents it:

Figure 1 Resistors R1 and R2 help to set the gains of both the non-inverting and inverting stages, allowing for excellent matching of the anti-phased outputs with minimal components.

A1a is a non-inverting gain stage, utterly conventional except that its feedback network is referred to A1b’s virtual ground point. A1b is an inverting unity-gain stage, utterly conventional except that its input resistor is also A1a’s feedback network. A1a and A1b therefore work together to deliver perfectly matched anti-phase outputs (assuming perfectly matched components, of course). The gain can be set to anything above 1 (unity gain would revert the circuit to a simple buffer plus an inverting stage: nothing new).

At first glance, this circuit may look rather like part of a differential or instrumentation amplifier. But its function, as determined by the resistor ratios, is quite different. Those others have accurately-matched differential inputs; this is designed for balanced outputs.

Is that it?

Yup: ’fraid so, apart from some practical details. A CR network may be needed to remove DC from the input, and any remaining imbalance could be trimmed by bleeding some current into (or out of) the A1b in- input. Otherwise, the circuit is stable and well-behaved, and will happily drive a transformer directly, though series matching resistors should be added, perhaps with 300R in each output line if you want to be really picky about balance.

Trimming the frequency response is messy, and should be done before the signal gets this far. Any (HF-cutting) capacitor across R1 (call it C1) needs to be matched by (1 – 1 / Gain) × C1 across R3 if the responses in both output legs are to match.

The output drive differs from device to device. Using ±15 V rails and working into 600R, LM4562s delivered 26.3 V pk-pk and KA5532s gave 24.5 V, while TL072/082s disappointed at just 13.8 V. An MCP6022 (RRIO, unlike the others) with ±2.5 V supplies clipped at 4.7 V pk-pk into 600R.

And in the real world…

To paraphrase Bob Pease, “If a circuit’s never seen a soldering iron, it probably won’t work right” (although perhaps he’d make an exception for plug-in breadboards, at least at low frequencies). So, just to demonstrate that this doesn’t merely describe a simulation, Figure 2 shows it plugged in and “working right”:

Figure 2 This is how an LM4562 performs at 1 kHz with ±15 V rails and a 600R load. It is just clipping—cleanly and symmetrically—at a differential output level of 32.2 dBu.

As noted earlier, the circuit is well behaved as long as you avoid driving capacitive loads directly, as with all op-amp circuits (33–100R in series with an op-amp’s output pin is normally a good cure, limiting the peak current). Lacking any suitable audio transformers but wanting to check if such loading might cause problems, I hooked it up directly to the secondary winding of a small mains transformer, which seemed like a cruel enough (not to mention fun) test.

While the resulting >>300 V RMS output tolerated little loading, it could light a neon brightly (with its integral 220k series resistor) without affecting the distortion at the op-amps’ outputs. Although the HV output showed a nick in the waveform where the neon struck and went negative-resistance, this artifact wasn’t reflected back to the drive. Which is exactly what we’d expect, but should not take for granted.

For phase-splitting with gain (but no pain) and the ability to drive old-school 600Ω balanced lines, this circuit may be ideal. That said, there may be easier and cheaper ways of powering neons…

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

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• Power amplifiers that oscillate—deliberately. Part 1: A simple start and Part 2: A crafty conclusion

The post Well-balanced gain, driven without pain appeared first on EDN.

Power modules for data centers are incorporating AI inference for applications such as agentic AI, response generation with large language models (LLMs), and predictive analytics in finance and healthcare. The use of AI accelerators is mainly aimed at boosting energy efficiency in high-density boards.

Take the case of Infineon, which is incorporating d-Matrix’s Corsair inference accelerator in its OptiMOS TDM2254xx dual-phase power modules. According to Sid Sheth, founder and CEO of d-Matrix, Corsair was purpose-built for delivering the sub-2 ms token latency that interactive applications require.

The OptiMOS TDM2254xx dual-phase power module enables vertical power delivery while offering a density of 1.0 A/mm2. Source: Infineon

Infineon has been working closely with d-Matrix to optimize the Corsair inference accelerator for its power semiconductors. “Infineon has been collaborating with customers specializing in inference processors, such as d-Matrix, from the early days when the industry was mostly focused on training hardware,” said Raj Khattoi, VP and GM of consumer, computing and communication at Infineon.

Infineon, which offers a broad portfolio of power semiconductors, based on silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), has also been working closely with AI companies in both the training and inference markets. And these liaisons have aimed to improve energy efficiency at higher power density in hardware at data centers and other AI installations.

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The post AI inference accelerator bolsters efficiency in power modules appeared first on EDN.

Diminutive? Definitely. Flexible? Indubitably. Safety-cognizant? Thankfully…unless you activate “FORCE” mode, that is (hopefully intentionally).

A bit more than a year ago, within a blog post that talked about (potentially) resurrecting dead lead-acid batteries, I noted that I’d recently added additional members to my battery-charger stable. Historically, I’d relied on a legacy-design DieHard model, one of the two which, loudly humming and dubiously still working, I subsequently turned into a teardown target:

The others were all newer designs, solid-state (vs transformer-based) and both more flexible in their supported battery voltages and technologies and more feature-rich. Specifically, today I’ll be focusing on the NOCO Genius 1, a 1A trickle charge two examples of which I’d acquired on promo discount from Amazon’s Warehouse-now-Resale) site intending to tear one of ‘em down:

Walking while chewing gum

I’d teased the feature set a year-plus back, then focusing (given the overall writeup topic slant) on its battery-rejuvenating chops. Here’s the fuller feature-set list, requoted from the Amazon product page (from which, by the way, I’d acquired today’s dissection victim for only $20.12, ~1/3 off the current brand-new $29.95 price tag, which in and of itself also isn’t bad, or if you prefer, half off the $39.95 MSRP):

• MEET THE GENIUS 1 — Similar to our G750, just better. It’s 35% smaller and delivers over 35% more power. It’s the all-in-one charging solution – battery charger, battery maintainer, trickle charger, plus desulfator.
• DO MORE WITH GENIUS — Designed for 6-volt and 12-volt lead-acid (AGM, Gel, SLA, VRLA) and lithium-ion (LiFePO4) batteries, including flooded, maintenance-free, deep-cycle, marine and powersport batteries.
• ENJOY PRECISION CHARGING — An integrated thermal sensor dynamically adjusts the charge based on ambient temperature, preventing overcharging in hot weather and undercharging in cold, ensuring optimal battery performance.
• CHARGE DEAD BATTERIES — Charge batteries from as low as 1 volt, or use Force Mode to manually charge completely dead batteries down to zero volts. Perfect for recovering deeply discharged or neglected batteries.
• BEYOND MAINTENANCE — Keep your battery fully charged without worrying about overcharging. Our smart charger constantly monitors the battery, allowing you to leave it connected safely – indefinitely – for worry-free maintenance.
• RESTORE YOUR BATTERY — Precision pulse charging automatically detects and reverses battery sulfation and acid stratification, restoring your battery’s health for improved performance and extended lifespan.
• COMPATIBLE — Charges and maintains all types of vehicles, including cars, automobiles, motorcycles, mopeds, lawn mowers, ATVs, UTVs, tractors, trucks, SUVs, RVs, campers, trailers, boats, PWCs, jet skis, classic cars, and more.
• WHAT’S IN THE BOX — Includes a 1A charger, a direct wall plug-in, 110-inch DC cable with battery clamps, and integrated eyelet terminals, and 3-year warranty. Proudly designed in the USA.

It’s pretty tiny (that’s the aforementioned G750 behind it in the following photo, by the way); 3.62in (92mm) high, 2.32in (59mm) wide and 1.26in (32mm) deep, and weighing only 0.77lb (0.35kg):

And the manufacturer was even thoughtful enough to include a preparatory teardown diagram on the website product page:

(Simple) assembly required

Let’s see how close reality comes to matching that conceptual image, shall we? This charger arrived absent its packaging, so what you’ll see first (as usual accompanied by a 0.75″/19.1 mm diameter U.S. penny for size comparison purposes) is the other, ~$3 more, charger’s box:

Wonder what happened to the original “tab” for retail-display hanging purposes?

Opening up the box…

you’ll find user guide (also accessible here as a multi-language PDF, plus the product spec sheet) and promo literature, plus, in this particular case, the aforementioned formerly-MIA tab:

along with, of course, today’s two-part patient:

the base unit:

and the remainder of the cabling, including the battery terminal clamps:

Here’s the male-and-female connector pair that mates ‘em:

And what’s that lump partway down the “remainder of the cabling” span?

It’s a (user-replaceable, which is nice) fuse, as at least some of you may have already guessed. 2A is, IMHO at least, a reasonable choice considering the device’s 1A-max output specs:

Before putting the “remainder of the cabling” to the side, here’s a closeup of those “integrated eyelets” mentioned earlier in the bulletized feature list:

And this stock shot shows how to make ‘em usable:

A high degree of integration

Now for the base unit. Before diving inside, here are some real-life overview shots to augment the earlier stock ones:

You’ve probably already noticed the ultrasonic welds around the outside, holding the halves together. Regular readers may already recall that they’re a longstanding bane of mine. This time, since it was convenient to do so and I was under no delusions that the charger would be salvageable/reusable post-teardown anyway, I took a hacksaw to ‘em in conjunction with a vise:

Here’s what the inside of the back half looks like, revealing AC prong connections to the PCB:

And speaking of which, here’s our first look at the PCB itself, specifically the backside:

Nothing here is particularly surprising, nor is the broader fact that DC conversion circuitry dominates the landscape, given the physical proximity to the AC source. Most notable, probably, is the diminutive size of the two transformers, explained in part (but only in part) by this particular unit’s trickle-current characteristics. For the rest of the (hint: solid-state) story, we’ll need to see the other side of the PCB. No better time than the present:

Taking (which?) temperature

With the normally-restraining screws now removed:

and in the process of lifting the PCB out of the remaining chassis half:

I happened to notice, down by the DC cable exit point, two more wires alongside a NTC1 notation on the PCB:

I’m (fairly confidently) assuming that they reference a negative temperature coefficient (NTC) thermistor. My initial reaction, and one that in retrospect I admittedly clung to far too long, was that it somehow was used to ascertain if the battery itself was overheating, a situation which would compel the charger to “cut the juice”. Problem being, though, that there are only two wires (DC positive and negative) in the cable running from the main unit to the battery, so the thermistor would end up being nowhere near the battery itself (PDF).

In grasping at straws, I surmised that perhaps the battery temperature was being indirectly determined by the transferred temperature of the connected cabling, which admittedly seemed increasingly silly the more I thought about it. But then I re-read the device specs prior to sitting down to write and realized that what the thermistor was actually measuring was (probably) just the ambient environmental temperature. “An integrated thermal sensor dynamically adjusts the charge based on ambient temperature, preventing overcharging in hot weather and undercharging in cold, ensuring optimal battery performance.” Yeah, that’s it. Ahem.

Onward. Interesting PCB topside two-level sandwich, eh?

And speaking of which:

here’s the inside of the front half of the chassis:

And the PCB topside itself:

The largest IC, the one with the white dot on it and located at lower right on the top (of the two-PCB sandwich) mini-PCB, is the “brains” of the operation, an ABOV Semiconductor A96G148GR 8-bit 8051-class microcontroller with integrated flash memory. On the other (top) end, toward the center, is the multi-function toggle switch, which puts the charger in various operating modes, surrounded by a ring of LEDs, including two more toward the bottom. And to its far left is the multi-pin connector that mates the mini-PCB with its larger sibling below it.

I almost stopped at this point, clinging to the delusion that maybe I’d glue everything back together again in fully-functional form. But curiosity-while-writing eventually got the better of me (and anyway, that was a silly idea), so I rotated the assembly by 90° so the PCB markings could be read right-side-up and let ‘er rip:

Ok, now I’m done!

A (potentially fatal?) forcing function

In closing, let’s revisit that just-referenced multi-function toggle switch, specifically in the context of the “unless you activate “FORCE” mode (hopefully intentionally), that is” comment in this article’s subtitle. Quoting from the user guide:

Mode	Explanation
Force Mode Press & Hold (5 Seconds)	For charging batteries with a voltage lower than 1V. Press and Hold for five (5) seconds to enter Force Mode. The selected charge mode will then operate under Force Mode for five (5) minutes before returning to standard charging in the selected mode.

Here’s the ominous bit:

Force Mode. [Press & Hold for 5 seconds]
Force mode allow the charger to manually begin charging when the connected battery’s voltage is too low to be detected. If battery voltage is too low for the charger to detect, press and hold the mode button for 5 seconds to activate Force Mode, then select the appropriate mode. All available modes will flash. Once a charge mode is selected, the Charge Mode LED and Charge LED will alternate between each other, indicating Force Mode is active. After five (5) minutes the charger will return to the normal charge operation and low voltage detection will be reactivated.

CAUTION. USE THIS MODE WITH EXTREME CARE. FORCE MODE DISABLES SAFETY FEATURES AND LIVE POWER IS PRESENT AT THE CONNECTORS. ENSURE ALL CONNECTIONS ARE MADE PRIOR TO ENTERING FORCE MODE, AND DO NOT TOUCH CONNECTIONS TOGETHER. RISK OF SPARKS, FIRE, EXPLOSION, PROPERTY DAMAGE, INJURY, AND DEATH.

The entire quote, notably the all-caps portion, was 100% original, by the way, not “enhanced” in any way by editing from yours truly (explaining, among other things, the “creative” grammar in spots). Reminds you of Jason Hemphill’s “hack” that I highlighted back in mid-March, doesn’t it?

Death. I’ll just leave that for you to ponder as you wish. Memento Mori, my friends. And with that pleasant thought , I’ll wrap up for today and turn it over to you for your thoughts (feel free to skip posting the morbid ones, please) in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• Resurrecting a 6-amp battery charger

The post NOCO’s Genius 1: A trickle charger that tries harder appeared first on EDN.

When structures bend, stretch, or compress, engineers need a way to translate that invisible mechanical stress into measurable data. Strain gauges do exactly that—tiny sensors that convert deformation into electrical signals with remarkable precision.

From monitoring bridges and aircraft wings to ensuring the reliability of everyday electronics, strain gauges are the quiet workhorses that make stress visible, quantifiable, and actionable.

How resistance reveals stress

At the heart of every strain gauge lies a deceptively simple principle: when a conductor or semiconductor is stretched, its electrical resistance changes. Engineers harness this effect by arranging strain gauges in a Wheatstone bridge circuit, amplifying tiny resistance shifts into measurable voltage signals.

It’s a clever translation—microscopic deformations become clear electrical outputs. Narratively, this is where the magic happens: the silent stress within a bridge girder or aircraft fuselage suddenly speaks in numbers, allowing designers to predict failures, validate models, and ensure safety long before cracks appear.

Stress signals in the real world

A strain gauge is the sensing element itself, while a strain gauge sensor is the complete packaged device that integrates the gauge with wiring, housing, and often signal conditioning for practical measurement. That distinction becomes critical when sensors are deployed in demanding environments.

Consider aerospace wing testing: engineers attach arrays of strain gauges across critical points of an aircraft wing. As the wing flexes under simulated flight loads, each gauge’s resistance shifts, feeding signals into a monitoring system. The sensor assemblies ensure those delicate gauges survive vibration, temperature swings, and handling. This is where theory meets reality—tiny resistance changes become the data that validates aerodynamic models, ensures passenger safety, and drives innovation in lighter, stronger aircraft designs.

Civil infrastructure offers another compelling example. Bridges endure constant stress from traffic, wind, and temperature cycles. Embedded strain gauge sensors provide early warnings of fatigue, helping engineers schedule maintenance before cracks or failures occur. In this narrative, strain gauges are not just measuring stress, they are safeguarding lives and economies by keeping critical structures resilient and reliable.

A technical note: A strain gauge directly measures strain (physical deformation). From this measurement, we determine the internal stress—the intensity of the forces resisting that deformation—using the material’s known stiffness.

Strain gauge vs. load cell vs. FSR

Since this post is focused on strain gauges, here is a quick distinction. A strain gauge measures material deformation as a resistance change, forming the basis of precise force sensing. A load cell builds on this, packaging strain gauges into a calibrated transducer for accurate weight and force measurement in industry. By contrast, a force-sensing resistor (FSR) is a low-cost sensor whose resistance shifts with pressure—handy for relative force detection in consumer and robotic applications, but far less precise.

Figure 1 Strain gauges and force-sensing resistors convert mechanical input into changes in electrical resistance, yet their responses vary in linearity, sensitivity, and application scope. Source: Author

So, in essence, when designers and engineers need to measure force, two of the most widely used technologies are force sensing resistors and strain gauges. Both convert mechanical input into changes in electrical resistance, yet their principles, accuracy, and applications differ greatly.

A force sensing resistor is a thin, flexible, polymer-based sensor whose resistance decreases as pressure is applied to its surface. A strain gauge, on the other hand, is made of fine metallic foil or wire arranged in a grid and bonded to a stable substrate. Rather than detecting direct pressure, it measures strain—the deformation of the material it is attached to. As the material stretches or compresses, the strain gauge deforms as well, producing a slight change in resistance. This change is typically measured using a Wheatstone bridge circuit for precise results.

Similarly, load cells build upon strain gauge technology by integrating one or more gauges into a mechanical structure that translates applied force into measurable strain. This makes load cells highly accurate and reliable devices for quantifying weight and force in industrial, commercial, and scientific applications.

Figure 2 A compact button-type load cell, based on strain-gauge technology, delivers compression measurements in space-limited applications. Source: ATO

Wheatstone bridge configurations for precision strain measurement

In practical applications, strain measurements typically involve very small changes rather than large strain values. Detecting these minute variations requires precise measurement of small resistance changes. A Wheatstone bridge circuit (WBC) is widely used for this purpose, as it translates subtle resistance shifts into measurable voltage outputs.

A standard Wheatstone bridge consists of four equal resistors arranged in a square. An excitation voltage is applied across one diagonal, while the output voltage is measured across the other. In its balanced state, the bridge produces zero output voltage. For strain measurement, one or more resistors are replaced with active strain gauges, whose resistance varies in response to external forces acting on the structure.

To achieve higher sensitivity and improved accuracy, different Wheatstone bridge configurations are employed: quarter-bridge, half-bridge, and full-bridge. In a quarter-bridge, a single resistor is replaced with a strain gauge. A half-bridge uses two strain gauges, while a full bridge replaces all four resistors. These configurations not only enhance measurement precision but also help compensate for temperature effects, making them essential in modern strain gauge instrumentation.

Figure 3 Diagram illustrates a quarter Wheatstone bridge, where one resistor is replaced by the strain gauge. Source: Author

Selecting the right strain gauge

Selecting the right strain gauge requires balancing geometry, resistance, and environmental compatibility to achieve accurate measurements while controlling installation costs. Options range from simple linear gauges for uniaxial stress fields to rosette configurations—rectangular, delta, or tee—for analyzing complex or unknown stress directions, and bridge arrangements for enhanced sensitivity and thermal compensation.

The choice of grid orientation and gauge length must align with the material’s homogeneity and the stress distribution being measured. Equally important are electrical parameters such as the nominal resistance, which determines compatibility with the measurement circuitry, and self-temperature compensation, which offsets thermal effects to maintain accuracy and improve signal-to-noise ratios under fluctuating operating conditions.

Environmental and installation considerations in strain measurement

As stated before, strain gauges are inherently sensitive to temperature variations, and changes in temperature can alter their electrical resistance. If not properly compensated or controlled, this effect can introduce significant measurement errors.

Beyond temperature, external factors such as humidity, moisture, vibration, and electromagnetic interference can also degrade performance and accuracy. Appropriate protective measures—such as encapsulation, shielding, and environmental sealing—are therefore essential to ensure reliable operation.

Equally important is the bonding of the strain gauge to the surface of the substrate. A strong, uniform bond ensures that the gauge accurately follows the strain of the underlying material. Achieving this can be challenging when working with dissimilar materials or irregular surfaces. Poor bonding may result in signal instability or inaccurate readings, undermining the integrity of the measurement system.

Practical strain gauge systems: Bridges, amps, and test kits

In a Wheatstone bridge, the strain gauge serves as the variable resistor whose resistance shifts under mechanical deformation, producing a differential voltage proportional to strain. Because this resistance change is extremely small—often less than 0.1% of the gauge’s nominal value—the bridge must be energized with a stable excitation source and paired with an amplifier stage to extract the signal from noise.

For basic designs, a differential amplifier can provide initial signal conditioning, but for precision applications, an instrumentation amplifier (INA) is preferred due to its superior common-mode rejection and high input impedance.

Keep in mind that the bridge configuration depends on accuracy requirements: a quarter-bridge offers simplicity, a half-bridge adds temperature compensation, and a full-bridge delivers maximum sensitivity. The choice of amplifier ensures the bridge’s delicate balance is preserved while enabling reliable strain measurement.

Today’s compact strain gauge amplifiers make the entire measurement workflow far more straightforward by integrating multiple critical functions into a single, easy-to-use module. Not only do they provide clean signal gain and low-noise performance, but many also feature built-in excitation voltage sources, eliminating the need for external supplies.

They often include automatic bridge balancing to correct minor mismatches in resistance, ensuring the Wheatstone bridge remains stable and accurate. With high input impedance, filtering options, and sometimes digital outputs, these amplifiers reduce design complexity, accelerate setup, and deliver reliable strain data. For engineers, this means less time spent on circuit design and more confidence in capturing precise measurements across lab and field applications.

Figure 4 Compact strain gauge amplifier modules meet growing demand for industrial strain measurements, where miniature size and easy setup are essential. Source: Transmission Dynamics

Moreover, when it comes to strain gauge test kits, they offer a practical, all-in-one pathway for converting mechanical stress into precise electrical signals. These kits typically include gauges with standard resistances (120 Ω or 350 Ω), along with surface preparation tools, adhesives for secure bonding, and protective coatings to ensure durability in challenging environments.

Once integrated into a Wheatstone bridge, the kit enables detection of minute resistance changes defined by the gauge factor, directly linking strain to output voltage. Thus, strain gauge kits simplify what would otherwise be a complex measurement workflow, making them indispensable across fields ranging from structural health monitoring and aerospace stress testing to advanced biomechanics.

That wraps up today’s dive into strain gauges. From foil to semiconductors, the evolution continues—and now it’s your turn to engineer what comes next.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Strain gauges: Turning stress into signal appeared first on EDN.

Simple analog circuits manage multi-PSU powerup and shutdown sequences.

In projects containing digital and/or analog circuits, multiple power supplies are used, generally 5V DC for digital circuits and 15V DC for analog circuits. Some projects also use 24V or 48V DC as the third power supply. In many cases, these power supplies need to be switched on in sequence, commonly 5V DC first and 15V DC next, with a time delay in-between. Subsequently switching them off necessitates implementing this sequence in reverse, i.e., first in/last out (FILO) in total, with 15 VDC first and 5V DC next and again with a time delay in-between.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In MCU-based projects, this sequencing can be achieved through an appropriate software routine. For non-MCU projects, conversely, Figure 1 shows a simple analog circuit that accomplishes this function for two power supplies:

Figure 1 A simple analog circuit controls the powerup and shutdown sequencing of two power supplies. 

How does this circuit work? Fundamentally, it employs the charging and discharging of capacitor C1 to achieve both power supply sequencing and the interim time delay. SW1 is a two-pole ON/OFF switch. When it is pressed, 5V is applied first through one pole and then through the second pole. 0V applied to the base of Q5 creates an open circuit. Next, C1 gets charged through R8.

The voltage at C1 rises per the following formula:

 v= V(1-e-t/T)

Here V=5V and T=R8xC1. R9, R10 and R11 serve as voltage dividers to set the references for comparators U1B and U1A.

When the rising voltage v crosses through the first reference voltage set by R11, the U1B output goes HIGH, saturating Q1. This transition causes Q2 to conduct and connect to the 5V output.  Capacitor voltage v, further rising, next crosses through the second reference voltage set by R10+R11. Now the U1A output goes HIGH, saturating Q4. Q3 now also conducts, with 15V also made available at the output.

For switching off, although SW1 is now opened, 5V initially continues to be fed to the output through the ongoing conduction of Q2. The base of Q5 goes HIGH, causing it to saturate. C1 resultantly starts discharging through R12. The voltage v at C1 decreases as per the formula:

v=Ve-t/T

When this voltage goes below the reference voltage 2 set as the input to U1A, its output goes LOW. Q4 and Q3 now turn OFF. Hence, the 15V DC output is switched OFF first. As the capacitor voltage further decreases with the passing of time, it goes below the reference 1 set at the input of U1B. Its output now also goes LOW, turning Q1 and Q2 OFF. The 5V output, switched OFF last, implements the desired FILO sequence.

Notably, this design doesn’t employ a constantly power-consuming watchdog circuit. For different time delays, accordingly select R9, R10 and R11 to set the desired reference voltages. High current power supplies can be handled by using suitable MOS switches (Q2 and Q3).

You can expand this concept to cover any number of power supplies to be operated in a time-delay FILO sequence. For example, Figure 2 shows a derived analog circuit, this time supporting three power supplies:

Figure 2 An analog circuit derived from the previous one controls the powerup and shutdown sequencing of three power supplies, with the concept further as-needed expandable.

The video below demonstrates the operation of Figure 2’s circuit with three power supplies in a FILO sequence.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

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The post Single switch controls sequential operation of multiple power supplies appeared first on EDN.

The current robotics narrative is heavily weighted toward artificial intelligence (AI). The prevailing assumption is that more parameters, larger models, and better reinforcement learning pipelines will eventually grant machines human like dexterity. This belief has shaped research agendas, funding priorities, and public expectations.

However, for engineers designing hardware that must survive millions of high-velocity cycles at companies like Amazon Robotics, a different truth is apparent. In the lab, the focus is on the brain, but on the production floor, robots fail for mechanical reasons far more often than algorithmic ones.

In high duty cycle environments, the primary drivers of unplanned downtime are wear, compliance, thermal drift, misalignment, and mechanical fatigue. These are not failures of perception or planning. No amount of neural network tuning can compensate for a linkage that deflects under load or an end effector that cannot maintain repeatability. As the industry continues to chase AI-centric solutions, it risks overlooking the fundamental engineering disciplines that determine whether a robot succeeds in the physical world.

The robotics community is at a crossroads. The last decade has delivered extraordinary advances in machine learning, but the physical reliability of robotic systems has not kept pace. The result is a widening gap between what robots can demonstrate in controlled environments and what they can sustain in real production settings.

Closing this gap requires a shift in mindset. The next leap in robotics will not come from larger models or more training data. It will come from better mechanisms, better actuation, and better physical architectures.

The reliability gap

The industry has spent a decade optimizing the brain while neglecting the body. This imbalance has created what can be described as the reliability gap. As a technical judge for MassChallenge and for university capstone programs at Worcester Polytechnic Institute and Boston University, I have observed a recurring pattern.

Startups and student teams often present systems that segment objects perfectly in simulation, classify scenes with remarkable accuracy, and demonstrate impressive reinforcement learning policies. Yet when these systems are deployed in the physical world, they fail after only a few hours of operation.

The reason is straightforward. AI amplifies a robot’s capability, but the mechanism defines the physical boundary. If a kinematic chain introduces unpredictable hysteresis, software cannot compensate its way to a reliable solution. If a transmission loses stiffness under load, no amount of perception accuracy will restore positional integrity. If an end effector cannot generate stable contact forces, even the most advanced grasping model will fail.

The robotics industry must acknowledge a practical reality. Software and AI are essential, but they cannot overcome fundamental mechanical limitations. The most successful robotic systems in history have not been those with the most advanced algorithms, but those with the most deterministic mechanical behavior. Reliability is not an emergent property of software. It’s engineered into the physical system from the beginning.

Determinism and the voyager philosophy

True industrial progress requires a return to mechanical rigor, specifically a focus on what can be called deterministic mechatronics. This philosophy suggests that the most successful robotic systems are those engineered for passive stability, predictable behavior, and graceful failure. A useful analogy comes from deep space engineering.

Voyager 1, launched nearly half a century ago, remains operational in one of the harshest environments imaginable. NASA has occasionally uploaded new command sequences, performed resets, and adjusted subsystems to extend its life. These interventions succeed because the underlying mechanical and electrical systems were engineered for extreme reliability. The spacecraft’s longevity is not the result of software alone or hardware alone, but the synergy between robust physical design and intelligent control.

Industrial robotics should adopt this same mindset. The next leap in automation will come from kinematic architectures that reduce inertia, precision transmissions that maintain sub-millimeter accuracy under load, and actuation strategies that prioritize physical determinism. The goal is not to diminish the role of AI, but to ensure that AI is built on a stable mechanical foundation.

A deterministic mechanism reduces the burden on perception and control. It narrows the solution space. It transforms a difficult control problem into a manageable one. When the physical system behaves predictably, the software becomes simpler, more robust, and more efficient.

Case study: The apparel challenge

The manipulation of non-rigid materials, such as apparel, provides a clear example of this principle. Handling folded fabric is traditionally viewed as an AI problem. The common assumption is that complex pose estimation, dense depth reconstruction, and advanced vision models are required to manage the noise introduced by folds and wrinkles.

However, breakthroughs in this field, including those protected under U.S. Patents 11268223 and 11939714, demonstrate that the solution is primarily mechanical. By designing a compliant yet deterministic gripping architecture, the physics of the material can be used to the machine’s advantage.

When the kinematic chain is engineered to minimize shear forces, the physical interaction becomes predictable. When the mechanism constrains the degrees of freedom in a way that aligns with the material’s natural behavior, the need for complex perception is reduced.

In these systems, AI still plays a meaningful role. It identifies features, guides sequencing, and handles variability. But it succeeds because the underlying mechanism provides a stable substrate. The machine does the heavy lifting so the software can remain efficient. This balanced approach is what the industry needs. Instead of using software to compensate for mechanical unpredictability, the mechanism is engineered to reduce the burden on software.

This approach scales. It is robust. It is repeatable. And it is the foundation on which industrial grade automation must be built.

A new hierarchy of design

To unlock the next stage of automation, the engineering community must rebalance its priorities. The hierarchy of design must shift.

First, the industry must invest in mechanism research and development with the same intensity it brings to AI. For every dollar spent on perception, equal resources should be allocated to transmissions, linkages, and end effectors. Mechanisms are not a solved problem. They are the frontier that will determine the next decade of progress.

Second, the industry must build reliability-first architectures. Robots should be engineered with the longevity of aerospace systems, not the lifecycle of consumer electronics. This requires a shift in mindset. Reliability is not a feature. It’s a design philosophy.

Third, the industry must foster a new breed of roboticists. The next generation of engineers must be equally proficient in kinematics and PyTorch, equally comfortable with finite element analysis and neural network training and equally invested in mechanical determinism and algorithmic efficiency. The future belongs to engineers who can bridge the physical and digital domains.

Finally, the industry must resist the temptation to chase demos. The goal is not to produce systems that perform well in controlled environments, but systems that operate reliably in the real world. The measure of success is not a viral video, but a robot that performs millions of cycles without failure.

The next decade of robotics

Artificial intelligence is an extraordinary amplifier, but it’s not the foundation of robotics. Intelligence can only be as effective as the physical vessel through which it acts. The next decade of robotics will be defined by the engineers who recognize that mechanisms, transmissions, and physical architectures are not secondary considerations. They are the core of the system.

The future of robotics does not belong to the AI-first approach or the mechanism-first approach. It belongs to the integration of both into a single, reliable, and deterministic system. When the body and the brain evolve together, automation will finally achieve the scale, reliability, and capability that the industry has been pursuing for years.

This is the mechanism-centric future of robotics. And it’s long overdue.

Santosh Yadav is senior mechanical engineer and robotics researcher at ASME MBE Standards Committee.

Special Section: Smart Factory

• Rethinking machine vision in industrial automation
• Smart factory: The rise of PoE in industrial environments
• Precision lasers boost safety and efficiency in smart factories
• Tale of 3 sensors operating in smart factory environments
• From edge AI to physical AI in smart factories: A shift in how machines perceive and act

The post Robots: Why AI alone will not deliver the next leap in automation appeared first on EDN.

The evolution of automotive safety is moving from the exterior to the interior, opening a new frontier: in-cabin sensing. Its emergence marks a shift from passive vehicle shells to active systems capable of detecting and safeguarding occupants. However, implementing radar-based in-cabin sensing presents multifaceted engineering challenges, including privacy considerations, real-time data processing, and functional safety, all under strict regulatory umbrella.

Radar has become the preferred modality for in-cabin applications, offering privacy by design, effectiveness through interior materials, and immunity to lighting conditions. Crucially, it detects micro-motions such as breathing and heartbeat.

Why in-cabin sensing Is becoming mandatory

In-cabin sensing includes systems that monitor driver behavior, track occupant presence, detect vital signs, and recognize gestures within the vehicle. With the push for in-cabin sensing in response to global demand for higher safety standards, in-cabin sensing is moving from a “nice-to-have” to a “must-have” feature set.

Figure 1 In-cabin sensing is increasingly becoming a must-have feature in modern vehicles. Source: Cadence Design Systems

Tragic incidents involving children left in hot cars and drowsy driving have prompted regulators and safety organizations to act, making in-cabin sensing essential for top safety ratings.

Regulatory bodies are shifting focus from external crash prevention to interior safety measures. Programs like Euro NCAP’s Child Presence Detection (CPD), effective in 2025, and the U.S. Hot Cars Act highlight the importance of interior monitoring to prevent child fatalities and assess driver alertness. While traditional camera systems face privacy and lighting challenges, radar technology, especially 60 GHz frequency-modulated continuous wave (FMCW) radar, offers a superior, privacy-preserving solution for next-generation intelligent cockpits.

Why radar is emerging as a preferred modality

Radar technology offers a unique set of capabilities that make it the optimal choice for the complex environment of a vehicle cabin. Unlike cameras, which can be obstructed by poor lighting or raise privacy concerns, radar provides robust, non-intrusive sensing and offers many benefits.

Privacy by design

In an era where data privacy is paramount, radar offers a distinct advantage. It does not capture detailed visual images of faces or bodies. Instead, it detects presence and movement through point clouds. This allows the system to monitor occupants effectively without recording sensitive personal visual data, making it far more acceptable to privacy-conscious consumers.

Seeing the unseen (non-line-of-sight)

One of the most profound advantages of radar is its ability to penetrate materials. A camera cannot see a child covered by a blanket or sleeping in a rear-facing car seat obstructed by the driver’s seat. Radar, however, can detect the micro-movements of breathing or a heartbeat through clothing, blankets, and even seat materials (excluding steel). This non-line-of-sight (NLOS) capability is crucial for reliable CPD.

Environmental robustness

Radar is immune to lighting conditions. It functions just as effectively in pitch-black darkness as it does in blinding sunlight, ensuring continuous protection day or night. Furthermore, its performance remains robust despite temperature fluctuations, humidity, or vibrations—common factors in the automotive environment.

Why 60-GHz FMCW radar specifically?

As OEMs and Tier 1 manufacturers evaluate their platform choices, the FMCW-versus-ultra-wideband (UWB) debate often arises. While UWB has had success in consumer electronics and certain automotive access systems, FMCW radar aligns more naturally with the requirements of high-volume automotive in-cabin sensing deployments.

FMCW offers a lower cost structure, simpler integration path, and superior feature scalability. It supports multi-use sensing—from occupant monitoring and CPD to vital signs and gesture recognition—all within a unified signal-processing pipeline.

FMCW also avoids security challenges such as relay or “man-in-the-middle” vulnerabilities sometimes associated with UWB applications. Taken together, these factors make FMCW at 60 GHz the “sweet spot” for OEMs targeting a multi-model rollout between 2026 and 2030.

Challenges in engineering the intelligent cabin

Implementing radar-based in-cabin sensing is not without its challenges. It represents a multifaceted engineering hurdle that requires the convergence of precision sensors, high-speed signal processing, and functional safety compliance.

The processing challenge

Detecting the subtle rise and fall of a sleeping infant’s chest amidst the noise of a moving vehicle requires immense computational precision. The radar processing pipeline involves complex stages, including the Range FFT (Fast Fourier Transform), the Doppler FFT, and sophisticated clutter-removal algorithms.

Statistics show 99.9% accuracy in CPD using radar. To achieve this high accuracy, engineers must employ advanced digital signal processing (DSP) technologies. Solutions like the Tensilica Vision 110 DSP are designed specifically for these high-performance, low-power requirements.

Figure 2 Here is a radar processing pipeline for a child presence detection use case. Source: Cadence Design Systems

By offloading complex mathematical operations such as 8-bit and 16-bit MACs to a dedicated DSP, automotive designers can achieve the required frame rates (around 50 FPS) while adhering to strict power and thermal constraints.

Integrating AI and machine learning

The future of in-cabin sensing lies in the fusion of traditional signal processing with machine learning (ML). While traditional algorithms excel at determining distance and speed, ML is essential for classification. Is the object a bag of groceries or a child? Is the driver blinking due to fatigue or just natural movement? Object segmentation is performed by running AI models on a radar dataset.

Advanced radar architectures now support AI-driven classification, allowing the system to learn and adapt. This capability enables features like gesture recognition for touchless control of infotainment systems, adding a layer of comfort and convenience alongside safety.

Applications beyond safety: Comfort and autonomy

While safety mandates are the primary driver, the potential of radar-based in-cabin sensing extends well beyond user experience and autonomous operation.

Health and wellbeing

The sensitivity of 60-GHz radar enables vital sign monitoring. Systems can continuously track heart and breathing rates without physical contact.

Figure 3 This radar processing pipeline serves vital signs monitoring (HR/BR). Source: Cadence Design Systems

In the event of a medical emergency, the vehicle could detect the driver’s distress and autonomously pull over or alert emergency services.

Enhancing autonomy

As we progress toward L3 and L4 autonomy, the vehicle needs to know not just where it is, but also how its occupants are doing. In a handover scenario where the car needs the driver to take control, the in-cabin sensing system must verify that the driver is alert, present, and ready. Radar provides this verification reliably, acting as a core intelligence layer that builds trust in machine-driven environments.

Operational efficiency

For emerging mobility models like robotaxis, radar offers practical benefits. It can detect the number of passengers for billing purposes, ensure no objects are left behind, and even automatically manage trunk operation.

The silicon imperative: Efficient DSPs and AI at the edge

In-cabin radar workloads demand a unique blend of high-throughput DSP operations and compact neural-inference capabilities. Traditional MCUs lack the parallelism required for FFT-heavy pipelines, while dedicated NPUs often exceed cost and power envelopes for cabin modules. A new category of radar-optimized DSPs has emerged as the right balance—programmable, efficient, and capable of supporting both classical signal processing and radar-trained neural networks.

These processors must deliver high MAC throughput, robust SIMD capabilities, and efficient memory architecture while operating within tight thermal constraints. Their flexibility enables quick algorithmic iteration, which is essential in a domain where radar datasets continue to expand across body sizes, seating layouts, and vehicle architectures.

The road ahead

As vehicles advance toward autonomous operation, in-cabin sensing will become a core intelligence layer that predicts occupant needs, safeguards their well-being, and builds trust in machine-driven environments. The integration of radar into the vehicle cabin is redefining what it means to be safe on the road.

For automotive OEMs and Tier 1 suppliers, mastering scalable, radar-based sensing architecture is no longer optional, but is a determinant of future leadership. By leveraging powerful DSP platforms and embracing the unique capabilities of FMCW radar, engineers are not just meeting regulations; they are designing a safer, more intuitive driving experience.

The guardians are no longer just on the bumper; they are inside, ensuring that every journey ends as safely as it began.

Amit Kumar is director of Automotive Product Management and Marketing for Tensilica DSPs at Cadence. He has more than 20 years of design experience in the semiconductor and IP segments. Amit has held product marketing, application engineering, business development, and key strategic management roles with a specialization in automotive ADAS/AD and robotics applications.

Related Content

• Automotive: The latest on in-cabin sensing designs
• Partnering to Advance Automotive In-Cabin Sensing Tech
• In-Cabin Monitoring: Time-of-Flight and Radar Take the Wheel
• How In-Cabin Monitoring Solutions Contribute to Overall Vehicle Safety
• Advancements in radar technology and the evolution of in-cabin sensing

The post The guardians inside: How radar is redefining in-cabin sensing appeared first on EDN.

SmartClamp DrMOS power devices from AOS are designed for the demanding power requirements of AI servers and high-end GPUs. Each device is a synchronous buck power stage with two asymmetrically optimized high-side and low-side MOSFETs and an integrated driver. They provide precise 100-A positive and 50-A negative current limiting during high di/dt transients. The flagship AOZ53228QI extends protection to multiphase voltage regulators, helping prevent failures during frequent high peak-current events.

In AI applications, fast load transients can drive current beyond the limits of standard inductors and power stages. Conventional overcurrent protection schemes may introduce response delays that allow short current overshoot events, which can stress the high-side MOSFET, particularly under inductor saturation conditions.

The SmartClamp family mitigates this risk by implementing current limiting directly within the power stage rather than relying solely on the controller, improving response to load transients that occur in tens of nanoseconds. An internal ramp-based sensing method continuously monitors inductor current in real time, enabling cycle-by-cycle current clamping instead of reacting after fault conditions develop. Cycle-by-cycle control reduces the likelihood of inductor saturation and MOSFET overstress during AI-style burst loads.

SmartClamp devices, including the AOZ53228QI, AOZ53262QI, and AOZ53263QI, are available in production quantities with a 12-week lead time. The AOZ53228QI is priced at $1.40 each in lots of 1000 units.

Alpha & Omega Semiconductor 

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SiTime’s Elite 2 Super-TCXO family of oscillators delivers sub-nanosecond synchronization, increasing GPU utilization in AI clusters. By minimizing timing errors between GPUs, the devices boost throughput and performance per watt.

“Industry reports show GPU utilization in AI clusters can be as low as 20 to 40 percent—a large and largely hidden tax on AI infrastructure,” said Piyush Sevalia, chief business officer at SiTime. “AI workloads are distributed across GPUs in tightly orchestrated time slots. Even small timing errors force wait cycles to avoid data corruption, and in extreme cases can trigger GPU timeouts and system restarts. Poor synchronization directly caps GPU utilization.”

Emerging AI cluster requirements call for reducing timing errors to 10 ns, down from 1 µs today. The Elite 2 Super-TCXO achieves 1-ns synchronization accuracy—exceeding this target—with frequency slope as low as ±2 ppb/°C.

The series comprises four variants: SiT5234 and SiT5434, operating from 1 MHz to 60 MHz, and SiT5235 and SiT5435, operating from 60 MHz to 105 MHz. The SiT5234 and SiT5235 offer Allan Deviation (ADEV) of 1E-11, while the SiT5434 and SiT5435 achieve 6E-12. All oscillators are available in 3.2×2.5-mm plastic and 5.0×3.2-mm ceramic packages.

Elite 2 Super-TCXOs are sampling now, with commercial production expected in Q3 2026.

SiTime

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TVS diodes in the TPSMC, TPSMD, and TP5.0SMDJ series from Littelfuse provide standoff voltage ratings of up to 400 V in a single device. Compared to low- and mid-voltage TVS diodes that require multiple devices in series for adequate protection, this single-device approach reduces BOM costs and component count.

The TPSMC, TPSMD, and TP5.0SMDJ series deliver peak pulse power ratings of 1.5 kW, 3.0 kW, and 5.0 kW (10/1000 µs), respectively, with peak surge currents up to 300 A. Designed for automotive power electronics, the devices protect GaN/SiC MOSFETs and IGBTs in battery disconnect units, high-voltage HVAC systems, and PTC heaters from severe transients such as load dumps and other high-energy events.

These devices combine fast response times (typically <1 ps) for effective transient clamping with IEC-61000-4-2 ESD compliance up to 30 kV for robust system-level protection. AEC-Q101 qualification and PPAP capability support automotive reliability requirements, while the SMC (DO-214AB) surface-mount package minimizes PCB footprint and simplifies layout.

The TPSMC, TPSMD, and TP5.0SMDJ series are available in tape-and-reel format in quantities of 3000. Samples can be requested through authorized Littelfuse distributors worldwide.

Littelfuse

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R&S has extended its BBA300 family of broadband amplifiers with single-band models delivering 500 W and 1000 W P1dB RF output power. The BBA300-DE500 and BBA300-DE1000 cover 1 GHz to 6 GHz without band switching, improving efficiency in automated test environments. Optional BBA-PK1 software for the 500-W model enables bias point adjustment to optimize either linearity for complex signals or pulse fidelity, while providing a tradeoff between output power and mismatch tolerance.

Well-suited for automotive, aerospace, and defense applications, the solid-state amplifiers offer high availability and robust operation under mismatch conditions. They generate high field strengths for component and full-vehicle testing, as well as high-intensity radiated field (HIRF) testing. The amplifiers support a wide range of modulation types, from standard amplitude and pulse modulation to complex OFDM signals.

To achieve high power density, the compact modular amplifiers integrate into 30U racks preconfigured for direct horn antenna mounting. To reduce RF losses at high frequencies, the RF output is positioned centrally within the rack, minimizing cable length to the antenna and improving overall link budget.

Learn more about the BBA-300 family of broadband amplifiers here.

Rohde & Schwarz 

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The TS1800 platform root of trust controller and TS50x secure boot controller expand Microchip’s TrustShield portfolio of post-quantum cryptography (PQC)-ready devices. These ICs address emerging cybersecurity mandates, including the European Cyber Resilience Act (CRA) and Commercial National Security Algorithm Suite 2.0 (CNSA 2.0), across data center, compute, defense, and infrastructure systems.

Designed for external platform root of trust in multi-component systems, the TS1800 provides secure boot, secure firmware updates, attestation, and certificate handling using hardware-accelerated PQC. An Arm Cortex-M4F processor operating at up to 192 MHz provides up to 2× the processing power of previous generations to support the increased computational demands of PQC workloads. The controller also supports Open Compute Project (OCP)-compliant implementations, enabling firmware integrity validation and lifecycle management.

The TS50x series provides PQC-based secure boot for systems that do not require the full OCP-based platform root of trust feature set offered by the TS1800. With a simpler architecture, it focuses on signature verification using both PQC and classical cryptography for firmware stored in SPI flash. The controller holds the main chipset in reset until verification completes. This hybrid approach enables retrofitting existing ECC-based designs with PQC.

TS1800 and TS50x controllers and evaluation boards are available as part of Microchip’s early adopter program. 

TS1800/TS50x product page

Microchip Technology 

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This engineer no longer has a bulbous monitoring device attached to his chest. He’s transitioned to a svelte successor, in the same location but this time placed subcutaneously.

Thanks to all of you who wrote in expressing concern and well wishes subsequent to the publication of my previous two posts in this series, focusing on my recent cardiac issues. I’m happy to report that I successfully made it through the 30-day regimen with a function-tailored smartphone in my pocket and a monitor stuck to my chest . I’m also happy to report that my cardiologist’s analysis of the collected data revealed no serious ongoing concerns. That said, I’m not yet completely “off the hook”, therefore the topic of today’s follow-up writeup.

What the 30-day results did reveal were a few brief episodes of tachycardia, i.e., elevated heart rate and intensity sequences, albeit with a still-regular cadence:

As my cardiologist explained (and I now paraphrase), my heart seemed to be trying to go back into irregular rhythm but (thankfully) didn’t succeed. As such, he was of the opinion that I still should proactively have a cardiac ablation, but I’ve declined that option, at least for now.

During my mid-November episode, while the bulk of my arrythmia rhythm was classified as atrial flutter, which has a near-100% success rate even after only a single ablation procedure:

my heart also occasionally transitioned into atrial fibrillation (AFib), whose single-procedure success rate is lower, due in part to the larger number of impulse sites that typically need to be severed (subsequent repeat procedures bolster the chances of a successful eventual outcome):

Instead, what I proposed (and he eventually agreed to) was a more conservative approach, at least initially. I’d remain on rhythm-stabilizing beta blockers. And he’d embed a miniature leadless cardiac monitor, with three-year operating life, subcutaneously in my chest to enable ongoing logging of any further heart rate abnormalities. He’d then automatically receive a report from the service provider each month. If there was no further detected AFib or atrial flutter after the monitor’s integrated battery eventually died, I could declare an “all clear”, with the now-inert monitor potentially remaining in me for the rest of my life. And if any recurrence of irregular arrythmia did occur, we could revisit the potential ablation scenario.

Tiny but mighty

The system I’m now artificially augmented with—just call me Steve Austin—is from Medtronic. Specifically, it’s the first-generation Reveal LINQ, which has been in widespread use for more than a decade at this point. At its nexus is the model LNQ11 ICM (insertable cardiac monitor), now in residence in my chest, which required only a local anesthetic (lidocaine) and sub-1 cm incision for installation, along with a couple of internal dissolvable stitches and some glue to temporarily hold the incision flaps together for the first two weeks while it healed.

The ICM has dimensions of approx. 44.8 x 7.2 x 4 mm, translating to (at ~1.3 cubic cm) roughly 1/3 the volume of a AAA battery, and weighs around 2.5 grams. Here are some stock shots:

Wireless diversity

The ICM communicates with a standalone AC-powered patient monitor which receives transmissions from the ICM and passes them along to a “cloud” server over a cellular data link:

Here are the meaningful perspectives of the outer packaging I received post-ICM installation:

Opening up the box, there was (obviously) no longer an ICM inside; it had already been relocated to my skin’s underside, at the left pectoral region of my chest, to be precise:

The patient monitor is variously described as needing to be no further than either 2 or 3 meters away (depending on the literature piece being referenced) from the ICM-toting patient in order to ensure reliable data transfers:

The system manual (PDF) accessible (along with other useful info) via the patient portal provides detailed information on the divers spectrum swaths used for various ICM-to-patient monitor and patient monitor-to-cloud functions, along with their associated modulation schemes. The companion ICM manual (PDF) translates these technical specifications into “for the masses” cautions and broader recommendations for cardiac monitor operation in EMI-rich environments (motors, arc welders, radio transmitters, etc.) along with the information you should share beforehand with MRI scanner operators as well as airport and other security personnel (I carry a Medtronic-supplied info card in my wallet for situations such as these).

Speaking of spectrum swaths, the FCC certification ID for the ICM is LF5MEDSIMPLANT1; I encourage you to check out the FCC site for more interesting information on the device, including a set of teardown images. Even more interesting info can be accessed by punching other FCC IDs, found on product labels both above and below this point in the writeup, into the independently developed and maintained FCC certification website search engine.  And further to the spectrum swath topic, I’ll note that Medtronic has subsequently introduced the LINQ II ICM, similar in size (45.1 x 8 x 4.2 mm) and per my online research making several notable enhancements to the first-gen implementation:

• Like the 30-day cardiac monitor I described in my previous writeup, it communicates with the data receiver device over Bluetooth low energy (BLE), not the proprietary protocols leveraged with the first-generation ICM. As such, again as with the 30-day monitor I previously used, it can connect to a conventional smartphone versus requiring my dedicated bedside patient monitor device.
• Its BLE and smartphone intermediary foundations also enable it to be remotely reprogrammed by the cardiologist for settings fine-tuning purposes, versus necessitating an office visit for the patient.
• Estimated battery life is now 4.5 years.
• And the LINQ II is FDA-cleared for pediatric use with patients 2 years and older.

Selective storage and transmission

My previous cardiac monitoring device was bulky and required recharge every five days or so. How on earth, then, does this comparatively tiny ICM run for 3 years on a much smaller and non-rechargeable cell? Selectivity is one key differentiator; while the prior cardiac monitor was constantly logging heartbeat information, the ICM (automatically, at least; keep reading) only captures a data sequence when it senses there’s a potential arrhythmia event occurring, and cloud-based AI algorithms further weed out “false positives” before passing the information on to the cardiologist.

The ICM only houses enough onboard storage for 27 minutes’ worth of this auto-logged information. It’s what’s known as a “loop recorder”, overwriting old data with new, operating under the assumption that the old data has already been transferred to the patient monitor. Yes, this means that, as with my CPAP machine, I also need to travel with the patient monitor and its AC power adapter.

What happens if I’m symptomatic, suggestive of an in-process cardiac event; palpitations, dizziness, light-headedness, etc.? The answer to that question depends on whether my patient monitor is nearby. You may have already noticed in the earlier set of photos that the patient monitor appears to consist of two pieces, with the smaller portion sitting atop the larger base unit. Kudos on your insight: you’re right:

If the patient monitor is nearby when you find yourself in distress, you can detach the “reader” portion (which, perhaps obviously, contains an embedded rechargeable battery), place it on your chest directly above the implant area, and transfer the captured and “flagged” data for analysis by the cardiologist (who can also proactively reach out to you for an ad-hoc transmission of this same way, by the way, if he or she sees something awry in the auto-captured monthly report data).

And if you’re away from your patient monitor? That’s where the pocketable “patient assistant”, accompanied in the following photos by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes, comes into the picture:

Place it on your chest atop the ICM, punch the “record” button, LED light-confirm that the two devices are communicating and, later, that a successful sample has been captured, and the next time you’re nearby the patient monitor it’ll be priority-tagged and transmitted. The ICM contains additional storage sufficient for 30 minutes total (variously segmented) of patient-activated recordings, beyond the earlier-mentioned 27 minutes of auto-logged data.

I’ll pass along any other notable aspects of my “bionic augmentation” experience via this blog if/as I encounter them in the coming months (and years). For now, I welcome your thoughts in the comments on what I’ve shared so far!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Wearables for health analysis: A gratefulness-inducing personal experience
• Cardiac monitors: Inconspicuous, robust data collectors
• Adventures with a remote heart monitor
• Heart rate monitor using a programmable SoC

The post Cardiac flutter(ing): Long-term monitoring appeared first on EDN.

Ultra-wideband (UWB) has moved well beyond research labs. Driven by IEEE 802.15.4z standardization and integration into smartphones from Apple, Samsung, and Xiaomi, UWB now underpins industrial real-time locating systems (RTLS), consumer keyless entry, and asset management platforms across multiple verticals.

For most of this adoption, time-of-flight (ToF) ranging has been sufficient, delivering approximately 10 cm accuracy in line-of-sight environments by measuring signal round-trip time. But system architects are increasingly moving to angle-of-arrival (AoA) techniques, which resolve the angular direction of a tag without requiring additional anchor nodes. AoA unlocks more efficient infrastructure layouts and opens new use cases in worker safety, autonomous robotics, and automotive access.

The shift exposes a hardware bottleneck that no amount of signal processing can fully compensate for: antenna isolation. AoA positioning relies on comparing the phase of a UWB pulse arriving at two closely spaced antennas.

If those antennas are mutually coupled—that is, insufficiently isolated—their signals contaminate each other. The resulting phase corruption introduces systematic angular errors that propagate directly into positioning accuracy.

Three design challenges facing UWB AoA antenna engineers

1. The –25 dB isolation threshold

Qorvo’s Application Note APH511—the widely referenced industry guide for AoA antenna integration—sets two non-negotiable requirements. Inter-antenna isolation must reach at least –25 dB across the full operating band, and physical antenna separation should be approximately 0.45 times the signal wavelength (λ).

For UWB Channel 9 (centred at ~7.987 GHz), that spacing equates to roughly 16.87 mm. Even at this theoretically optimal separation, raw isolation without dedicated decoupling structures typically falls short. The shortfall allows mutual coupling to corrupt the phase difference of arrival (PDoA) measurement on which AoA computation depends—and angular errors compound with distance.

2. Broadband impedance matching and pulse fidelity

UWB systems transmit sub-nanosecond pulses spanning hundreds of megahertz of bandwidth. An antenna that appears well-matched at a spot frequency can still distort pulse shape if its phase response is non-linear across the band.

Published time-domain evaluations indicate that group delay variation beyond approximately 1 ns degrades ranging accuracy even when return loss (S11) looks clean. Engineers must validate not just impedance matching, but pulse fidelity and group delay flatness—metrics that add complexity to an already demanding design process.

3. Size constraints vs. isolation performance

Industrial IoT tags, wearables, access cards, and consumer devices impose tight dimensional budgets. Conventional approaches to achieving strong inter-antenna isolation rely on enlarged ground planes or external RF filtering networks; both of which are incompatible with compact form factors. The result has been a persistent trade-off: high isolation or small size, but rarely both.

Chip antenna purpose-built for AoA

LK1820201 is an SMD chip antenna engineered specifically to address these barriers. Key specifications are summarized below.

Source: Leankon

Proprietary decoupling architecture

The central innovation is a proprietary decoupling structure that achieves inter-antenna isolation better than –25 dB between two co-located UWB antennas. In practical validation, a dual-antenna AoA array using the LK1820201 and its decoupling element measures –26 dB of isolation across the complete UWB Channel 9 band, confirming that performance holds across the full 6.0–8.5 GHz operating envelope, not just at a single center frequency.

This directly meets—and in practice exceeds—the Qorvo APH511 threshold, providing a solid electrical foundation for phase-coherent AoA computation.

• Ultra-low 0.5 mm profile

At 0.5 mm in height, LK1820201 is among the lowest-profile UWB antennas available in SMD chip format. This enables integration into slim wearables, access badges, compact industrial tags, and consumer devices without compromising mechanical design. Standard SMD reflow mounting eliminates the need for bespoke assembly tooling, reducing manufacturing entry barriers.

• Radiation pattern and power efficiency

Counter-intuitively for positioning applications, a lower peak gain paired with high radiation efficiency is generally preferred over a high-gain directional pattern. High efficiency distributes signal energy across a wide spatial angle, improving coverage at anchor installations and reducing dead zones for tags moving through complex indoor environments.

The antenna’s efficient radiation characteristic also reduces the transmit power burden on the UWB chipset—extending battery life in tags and wearables that must operate over weeks or months between charges.

Application areas

Centimetre-accurate UWB AoA positioning, enabled by high-isolation antenna pairs, is opening deployments across several industries.

• Industrial RTLS and worker safety: In manufacturing plants, logistics hubs, and construction sites, AoA allows a single anchor to resolve not just distance but the angular direction of a tag. This reduces the anchor infrastructure required for full coverage, lowering deployment cost for geofencing, collision avoidance, and emergency mustering systems.
• Healthcare asset tracking: Hospitals require continuous visibility into the location of mobile medical equipment—from infusion pumps to crash carts. UWB delivers the accuracy to track assets to the correct bay or room, without the ambiguity of Bluetooth RSSI-based systems.
• Automotive keyless access: Digital car key implementations use PDoA and AoA to determine whether a smartphone is inside or outside a vehicle—a security-critical distinction that RSSI cannot reliably make. Multi-channel support and high isolation performance are prerequisites for meeting the phase measurement accuracy demands of these deployments.
• Autonomous mobile robots: UWB AoA enables infrastructure-light follow-me navigation on autonomous mobile robot (AMR) platforms. By resolving both range and angle to a worker’s tag from a single onboard antenna pair, a robot can track a target in real time without requiring a fixed anchor network.

Design enablement and engineering support

Selecting a datasheet-compliant antenna is only the starting point. PCB stack-up decisions, ground plane geometry, feed trace routing, and antenna placement relative to metallic enclosures all interact with measured RF performance. Leankon supports the LK1820201 chip antenna with a design enablement program that covers:

• PCB layout recommendations optimized for isolation performance
• Antenna performance simulation services for pre-layout validation
• Mechanical design assistance for antenna placement within enclosures
• Fast prototyping services to accelerate design verification cycles
• Pre-test support for FCC, CE, and regional certification processes

This end-to-end support model reduces the engineering risk of adopting a high-performance UWB antenna and shortens the path from concept to production-qualified hardware.

Why AoA now

UWB angle-of-arrival positioning is a technically compelling evolution from range-only systems, but its precision depends fundamentally on solving the antenna isolation problem. For years, that barrier has limited AoA adoption to designs with generous PCB real estate or expensive external RF filtering.

Chip antenna changes the equation. By achieving better than –25 dB isolation from a 0.5-mm SMD package, supporting all major UWB frequency allocations from a single component, and simplifying BOM complexity for global deployments, it removes the principal hardware barrier to AoA in compact, cost-sensitive devices.

For IoT hardware engineers, RTLS platform developers, and device makers targeting precise indoor positioning, this antenna represents a technically meaningful step toward aligning hardware capability with the precision that modern UWB applications demand.

Chris Zhong, engineering manager at Leankon, leads the global antenna R&D team, overseeing both RF and mechanical design. With over 15 years of antenna design expertise, he specializes in 4G LTE, Bluetooth, 5G and mm-Wave, UWB, NFC, LoRa, and Wi-Fi technologies.

Related Content

• Trends in UWB technology
• Inside UWB design: A tutorial
• UWB simplifies portable design
• Ultra-wideband antenna arrays–The basics
• Ultra-Wideband Radar in Healthcare: A New Era of Non-Contact Sensing and Monitoring

The post UWB: Why angle-of-arrival positioning hinges on antenna isolation appeared first on EDN.

Op amps tend to make analog design easy. Maybe sometimes too easy?

Don’t get me wrong.  I like operational amplifiers.  Some of my best friends are op amps.  They embrace such a wide range of varied capabilities, including low noise, high power, micropower, zero-drift, RRIO, high speed, etc., that they’re easy to love.  They tend to make analog design easy.  Maybe sometimes too easy?

Wow the engineering world with your unique design: Design Ideas Submission Guide

This design idea applies the ΔVbe temperature measurement principle to make any cheap 3¾ digit digital multimeter with a 300mV range into an accurate, linear, 0.1°C resolution digital thermometer.  As a (hopefully) entertaining exercise, this time it does it without incorporating any op amps.  Here’s how it works.

ΔVbe temperature measurement is described and applied in an app note written by the famed analog design guru Jim Williams. See page 7 (PDF). Williams explains that the ΔVbe/°C effect depends solely on the ratio of applied currents, independent of their absolute magnitudes, and has an amplitude of 198μV per °C per current decade.  198uV=1V/5050, so 198μV/°C per current decade works out to ΔVbe/°C = Log10(Current-ratio)/5050.

Therefore, for any chosen ΔVbe/°C, the required Current-ratio = 10^(5050 Vbe/°C). So if we want ΔVbe/°C = 1mV, the solution couldn’t be simpler.  We “only” need to set Current-ratio = 10^(5050 * 1mV) = 10^(5.050) = 316,228:1.

Yikes!

The challenge, of course, is to achieve such an extreme current ratio. If the high side current were 1mA, then the low side would have to be very (very!) low indeed…like 1mA/316,228 = 3.2nA low.  This would involve Gohm current-setting resistors and circuit impedances in the multi-Mohm range.  So it’s not so simple after all and in fact is very likely impractical—without op amps, that is.

But consider this.  If it’s impractical to get enough ΔVbe signal from a single junction, why not wire N junctions in series and let their signals add up?  For example, if N = 5, then to get the required 1mV/5 = 0.2mV, we only need Current-ratio = 10^(5050 * 200uV) = 10^(1.01) = 10.23.  That ratio is highly practical.  It’s exactly what Figure 1’s circuit does, in fact:

Figure 1 Switch U1a and current mirror Q2Q3 apply an excitation current ratio of 10.23:1 to the 5 sensor transistor series array.  This creates a 5 x 200uV/°C = 1mV/°C AC signal synchronously rectified by U1c.

Circuit details include the D1R6 dummy load that serves to balance the currents passed by the two sides of the U1a switch, thus equalizing Ron voltage losses.  Current mirror aficionados (I’m looking at you, Ashu) will probably wonder how the Q2Q3 mirror, consisting of unmatched transistors with no emitter degeneration, can possibly have an accurate gain ratio?  The answer, of course, is: it doesn’t.  But that’s okay. It doesn’t need one.

Remember that Jim Williams said that the ΔVbe/°C effect depends solely on the ratio of applied currents, independent of their absolute magnitudes.  So the mirror’s gain can vary as it pleases without significantly affecting temperature measurement accuracy. Multivibrator U1b provides ~7kHz timing for synchronous sensor excitation and rectification with a ~33% duty factor.  This takes advantage of the 10x lower sensor array impedance at the high-current side of the excitation square wave.

If a more usual temperature readout in Celsius rather than Kelvin is desired, just plug the minus lead of the DMM into Figure 2 instead of ground, to offset 273K to 0°C:

Figure 2 This precision voltage reference converts Kelvin to Celsius.

Speaking of variations that don’t spoil accuracy, the V+ supply, for example, can vary from 5 to 6 volts without affecting accuracy.  Output impedance is roughly 2k, so variation of output loading by a typical 10M DMM input won’t impact accuracy, either. Who needs op amps, anyway?  (Not a serious question!)

Thanks, Jim!

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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• A temperature-compensated, calibration-free anti-log amplifier

The post ΔVbe thermometer outputs 1mV/°C without calibration or op amps appeared first on EDN.

Misbehaving buffer pointers, whose effects threatened to create a fatal project setback, were identified via a clever software subdivision technique.

In the 1990s, I was working as a motion control engineer for the Giant Meter Wave Radio Telescope Project (GMRT). The radio telescope consists of 30 giant meter wave antennas, each a parabolic dish 45 meters in diameter. The motion control electronics (i.e., the control computer and power electronics) were located inside a control room within the supporting tower below each antenna. The servo computer received motion control coordinates from a master computer situated in a central building via an optical fiber link.

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After the first two prototype antennae were commissioned, the radio astronomers started using them for their observations. Whenever a celestial object is to be observed, the antenna has to move in opposition to the earth’s motion in order to remain focused on the object under observation. After a few weeks I received a phone call from the security guard manning one of the antennas. “The antenna was dancing madly,” the guard said. “I had to shut off the power supply! Please come down and investigate.” I reached the project site only to discover that the problem could not be reproduced.

This story repeated itself every few days, for both antennae in turn. The control system development team blamed the “dancing behavior” on erratic fluctuation with the rural electricity grid, suggesting that “if your grid bus voltage dances madly, the antenna will do the same.” However, I couldn’t “buy” this explanation. If it had been true, a repeated power on/off sequence could have reproduced the problem. But it didn’t.

The developers then handed me a 2,500 page printout of the source code, which was written in Turbo Pascal. Since I instead suspected a control software bug as the culprit, I was tasked with finding it. But how could anyone debug such a voluminous amount of software, written by multiple development team members, none of them myself? And what debugging tools could I use to track down an issue that occurs only once a few weeks? The situation appeared hopeless.

I decided to make use of the three LEDs located on the front panel of the servo computer, Each LED can have three states: on, off and blink. So we have cube of three combinations, 27 possible combinations in total. I divided the program into 27 different parts. A specific combination out of the 27 was therefore illuminated on the LEDs each time the associated code portion was being executed. I then asked the security guard to record the LED pattern being displayed every time the antenna was “dancing”, before he shut down power.

After only two or three iterations of the “dancing antenna event”, the culprit area of the program was identified, located within a two-page portion of the original 2,500-page source code printout. I was admittedly thrilled at the seeming magic of my debugging technique. The culprit program segment implemented a 128 byte circular communication buffer. When the master computer was issuing commands, the buffer would store them until the servo computer could execute them. Occasionally, however, the motion trajectory was so fast that the buffer would also rapidly begin to fill up.

In the worst-case scenario, the entire 128-byte buffer would become full. The buffer management routine maintained two pointers: a read pointer to the next command to be executed and a write pointer to the last location written. The pointers normally circularly wrapped around after reaching the 128th location. However, in this particular situation the read pointer was erroneously advancing to an invalid 129th location instead. No wonder it would then read a junk motion control command, resulting in the antenna “dancing” erratically!

I corrected the bug, to the delight of the other team members. The antennae had been running the risk of falling down during the “dancing”, leading to a fatal setback for our project. After more than three decades of development work, I have accumulated enough experience (and experiences) to come up with “life-saving” countermeasures for bugs such as these:

• Motion control software needs to carry out a “sanity check” before executing any motion command. Such a huge amount of inertia cannot be given a violent added acceleration beyond a reasonable threshold. Any command breaking this rule can be safely ignored, with an error subsequently flagged.
• A simple checksum for every command bit stream could have identified a “junk motion command” situation such as the one described here.

Our project received a prestigious IEEE Milestone Award a few years ago. Needless to say, if this difficult-to-find bug had not been identified and rectified, the project would not have even seen the light of the day, far from basking in the global good reputation it has achieved over the years among the international radio-astronomer research fraternity.

Vishwas Vaidya is a graduate of the Indian Institute of Technology in Delhi, India. Currently, he is self-employed as an engineering consultant and industry faculty member in the field of embedded systems for global automotive clients and high-repute academic institutions. Vishwas’ articles and research reports have appeared in many worldwide engineering publications.

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The post The curious case of the dancing antennae appeared first on EDN.

The concept of the “smart factory” has evolved significantly over the past decade. Early industrial AI deployments, often categorized as Industry 4.0, focused on centralized analytics. This typically involved collecting data from machines, transmitting it to the cloud, and generating insights for later action.

While useful for optimization and reporting, that model is no longer sufficient. What’s changing now is not just where AI runs, but how it operates—shifting from centralized analysis to systems that can perceive, decide, and act in real time within the physical environment.

Today’s factories demand intelligence that operates in real time, directly at the point of action. Whether detecting defects on a production line, coordinating robotic motion, or identifying safety hazards, AI is increasingly expected to function as an always-on, embedded capability within industrial systems.

This shift marks a broader transition in smart factories, from traditional edge AI toward more contextual awareness and autonomous operation: systems that not only analyze data, but perceive, decide, and act within the physical world. While the promise is substantial, realizing it introduces a new set of technical challenges that require purpose-built solutions.

Why edge AI Is moving closer to the machine in smart factories

Several converging forces are pushing AI workloads out of centralized infrastructure and toward the factory floor, where real-time interaction with physical systems is required.

Latency is among the most critical. In applications such as robotics, inspection, and safety monitoring, even small delays can result in defects, downtime, or safety risks. Round-trip communication to the cloud is often incompatible with these requirements. This is further compounded by the fact that many industrial environments operate with constrained, segmented, or variable network connectivity, making consistent low-latency cloud access difficult to guarantee.

Data volume is another key driver. Modern industrial systems generate vast streams of multimodal data—high-resolution video, audio signatures, vibration patterns, and increasingly, tactile inputs. Transmitting all of this data offsite is not only expensive but also unnecessary. In most cases, only a small fraction of events—such as anomalies, defects, or threshold violations—require action, making local inference far more efficient.

Figure 1 The transition from centralized AI to edge AI represents a fundamental shift in industrial computing. Source: Synaptics

Security and data sovereignty further make this trend important. Manufacturing processes and operational data are highly sensitive, and many organizations prefer to keep raw data within controlled environments.

The emergence of physical AI

On top of those factors, as AI moves closer to machines, its role is expanding. Instead of simply classifying or predicting, systems are beginning to interact with their environments in more dynamic ways.

This is the essence of physical AI in industrial systems, where they can:

• Interpret complex, multimodal sensory input in real time
• Adapt to changing physical conditions
• Execute actions with precise timing and coordination

Figure 2 The edge AI-enabled systems are now interacting with their environments in more dynamic ways. Source: Synaptics

Consider robotics as a leading example. Advances in tactile sensing now allow robotic systems to “feel” objects, adjusting grip force based on material properties. In one recent deployment developed with our partner Grinn, a robotic hand integrates distributed touch sensing with embedded machine learning, enabling nuanced manipulation of objects ranging from fragile materials to rigid components.

Such capabilities represent a shift from scripted automation to adaptive, context-aware behavior, bringing machines closer to human-like interaction with the physical world.

Key challenges in deploying edge and physical AI

Despite the momentum, implementing AI at the edge, and especially physical AI, presents several challenges.

1. Balancing performance and power

Industrial AI systems must operate continuously, often in constrained thermal and power environments. Unlike data centers, where peak performance is the primary metric, factory deployments prioritize sustained performance per watt.

Always-on workloads, for instance, predictive maintenance or safety monitoring, require efficient architectures that can run continuously without excessive energy consumption.

2. Managing workload diversity

Industrial AI is inherently multimodal. A single system may combine:

• Vision for inspection
• Audio for anomaly detection
• Vibration analysis for predictive maintenance
• Sensor fusion for robotics and control

These workloads have different computational characteristics, making it difficult to rely on a single type of processor. Increasingly, heterogeneous architectures that combine CPUs, GPUs, NPUs, and specialized sensors are required to efficiently handle diverse tasks.

3. Ensuring long-term reliability

Industrial systems often remain in operation for years or even decades. This creates unique requirements around:

• Silicon longevity and availability
• Stable software ecosystems
• Predictable behavior across revisions

Frequent hardware changes or software incompatibilities can disrupt operations and increase lifecycle costs.

4. Addressing model drift and lifecycle management

Unlike controlled lab environments, factories are dynamic. Lighting conditions change, materials vary, and equipment degrades over time. These factors can lead to model drift, where AI performance degrades after deployment.

Addressing this requires:

• Continuous monitoring and validation
• Local recalibration capabilities
• Secure, manageable update mechanisms

AI in industrial environments must be treated not as a static feature, but as a lifecycle-managed subsystem.

5. Integrating compute and connectivity

As systems become more distributed, the interaction between compute and connectivity becomes critical. Many manufacturers still rely on separate vendors for processing and wireless communication, leading to integration challenges and fragmented support models.

In physical AI systems, high-bandwidth, low-latency data movement between sensors, processors, and actuators is essential for safe and reliable operation.

The role of Wi-Fi 7 and next-generation connectivity

Connectivity is often a critical enabler of physical AI in smart factories, where real-time coordination between distributed systems depends on low-latency, high-reliability communication. As industrial systems scale in complexity and device density, traditional wireless technologies struggle to meet performance requirements.

Advancements in Wi-Fi and Bluetooth are addressing this, but wireless connectivity can no longer be viewed as a standalone, discrete capability. Without this level of connectivity, many physical AI use cases, particularly those requiring coordination across multiple systems, are not feasible.

There is a growing need, and clear benefits, in integrating processing and connectivity. This helps reduce system complexity, improve reliability, strengthen security, and simplify development for design teams.

Bringing together connectivity and processing changes how design decisions are made early in the product lifecycle. When core system functions work together, teams can simplify architecture choices from the outset and reduce the number of variables that typically slow progress.

Integrating connectivity and compute has benefits beyond the engineering and manufacturing phase. Over the lifetime of a product, integration helps reduce power consumption, lower device weight, and decrease overall system cost. At scale, even small reductions in size, mass, and power can translate into meaningful savings across production, shipping, and years of deployment.

Of course, wireless performance, range, and reliability are still critical in their own right. While existing Wi-Fi and Bluetooth standards have advanced the state of wireless connectivity, the emergence of Wi-Fi 7 introduces capabilities that enable more scalable and deterministic edge AI, supporting higher device densities and more predictable low-latency communication in smart factory environments.

• Multi-link operation (MLO) allows devices to transmit data simultaneously across multiple frequency bands. This provides redundancy and helps maintain consistent, low-latency communication even in environments with interference or congestion.
• Wider channel bandwidth (up to 320 MHz) supports high-throughput applications such as machine vision, where large volumes of image data must be transmitted quickly and reliably.
• Higher spectral efficiency (via 4K QAM) enables more devices to share the same wireless spectrum without degrading performance, an essential feature as industrial systems scale.

Toward a new system architecture

The convergence of edge AI, physical AI, and advanced connectivity is reshaping how industrial systems are designed, requiring more integrated and system-level approaches.

Some guiding principles to consider in developing such intelligent deployments are:

1. Start with system constraints

Rather than beginning with AI models, successful deployments start with system-level requirements:

• Latency and timing constraints
• Power and thermal limits
• Reliability and safety considerations

These factors should guide architecture decisions, including silicon selection and model design.

2. Embrace distributed intelligence

Instead of centralizing all processing, intelligence should be distributed across the system:

• Sensor-level processing for early data reduction
• Edge inference for real-time decisions
• Connection to cloud-based training and optimization for continuous improvement

This layered approach balances performance, efficiency, and scalability.

3. Design for multimodal integration

Physical AI systems rely on combining multiple sensing modalities. Architectures must support efficient data fusion and coordination across these inputs.

4. Treat AI as a lifecycle capability

Deployment is only the beginning. Ongoing monitoring, updates, and optimization are essential to maintaining performance over time.

The path forward

The smart factory is no longer defined solely by automation, but by intelligence embedded throughout the system, enabling decision-making that operates in real time, it adapts to its environment, and interacts with the physical world.

This transition from centralized AI to edge AI represents a fundamental shift in industrial computing. Performance and accuracy are still important, but what matters most is whether AI can operate reliably under real-world constraints: continuously, efficiently, securely, and in close coordination with physical processes.

Advances in heterogeneous computing, integrated connectivity, and open software ecosystems—as evidenced by AI-native platforms such as the Synaptics Astra Platform—are enabling this shift.

As these elements come together, the factory floor is becoming not just automated, but perceptive and adaptive, comprised of increasingly autonomous systems that do more than execute tasks; they understand context and respond accordingly.

Neeta Shenoy is VP of marketing at Synaptics.

Special Section: Smart Factory

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