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Intel, long known for its acquisition misadventures, has finally reached a reality check. Its new CEO, Lip-Bu Tan, has announced spinning off the company’s non-core businesses to focus on core operations: CPU design and contract chip manufacturing. “These parts of Intel are no longer central to its future,” he said during his keynote at the Intel Vision conference in Las Vegas, Nevada.

It’s important to note that Intel has already been on this path since the final days of former CEO Pat Gelsinger. The Santa Clara, California-based semiconductor firm has already spun off FPGA maker Altera. Even before Gelsinger took charge of the top job at Intel in February 2021, the company had sold its NAND memory business to SK hynix for $8.85 billion in 2020.

Tan didn’t indicate whether Intel will divest or sell its non-core businesses. Source: Intel

The company also turned Intel Capital into a standalone investment fund early this year before Tan took the CEO job. While Intel will remain an anchor investor, the fund will help the company to reduce costs and streamline operations.

So, what does this mean when Tan vows to shed the company’s non-core businesses? Apparently, Intel will pursue this endeavor more aggressively now to focus its CPUs on artificial intelligence (AI) and data center applications, along with what Tan calls a Software 2.0 strategy. But will Intel’s rush to shed non-core assets lower their market value? Or will Intel divest these units instead of seeking buyouts? Time will tell.

Intel’s non-core businesses

Now let’s discuss Intel’s non-core businesses. Start with Mobileye, a developer of automotive driver-assist systems, which was listed on Nasdaq in 2022. Though Intel has denied the plan to divest a majority stake in Mobileye in the past, it will now be one of the easiest targets for Intel to handle.

Intel’s networking division could also be up for grabs. However, many industry watchers consider Intel’s Network and Edge (NEX) group a core business of Intel. It focuses on edge computing, networking, and AI solutions while developing modified versions of consumer and data center CPUs for telecom companies and similar entities.

It’s worth noting that Altera and Mobileye are worth approximately $17 billion to 20 billion. Intel can generate a huge amount of cash from those two entities, which, in turn, will bring financial stability to this once-mighty semiconductor outfit now attempting to reclaim its past glory.

Still, the elephant in the room is not the non-core assets but whether Intel will remain whole or split up its CPU and contract manufacturing businesses. At the same time, however, Intel’s decision to shed non-core assets will bring much-needed stability during the turnaround that Tan envisions for this chip industry pioneer.

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• Intel’s Embarrassment of Riches: Advanced Packaging
• How will Intel’s purchase of Altera affect embedded space?

The post Will Intel’s rush to shed non-core assets benefit potential buyers? appeared first on EDN.

Today’s typical home is wired for at least 100-amp service, and many are wired for twice that number. This makes sense given the multiplicity of modern appliances and electronics in a home. The demand is obviously higher if you have an electric stove/range, or an electric vehicle using a basic in-house Level 1 charger.

The need for power—and more of it—became clear when a neighbor who was having a modest addition put on the house asked me for some advice. The situation was this: the contractor told him that for various reasons, their 100+ A service would be cut to 50 A for a month or two during the construction. The reasons for this cutback were not clear, but it had something to do with cable capacity.

The question I was asked was simple enough: could they—a couple plus two children approaching teen years—manage on just 50 A and, if not, what steps could the take to minimize disruption? (Actually, the word my neighbor used was “survive” rather than “manage” but I feel that’s overly dramatic.)

The semi-quantitative assessment

My answer was also simple, as I gave the prudent engineering response “it depends” followed by “I’ll think about it and get back to you.” Then I set out to develop a firmer answer by doing some semi-quantitative assessment.

My first impulse was to check the web and, sure enough, there were plenty of apps for assessing house power needs. However, these required a detailed inventory of the loads which was more than I was ready to do. Then I thought I would create an Excel spreadsheet but soon realized that sort of analysis could easily become more precise than the problem merited. After all, my neighbor wanted a simple answer:

1. It’s no problem,
2. it’s definitely a problem, or
3. it’s a manageable “maybe” problem.

Instead, I took out my “back of the envelope” pad and decided to do some rough assessments, Figure 1.

Figure 1 This “back of the envelope” pad serves as a visible reminder that rough and imprecise input numbers should get appropriate analysis and not impute undeserved precision to the results. Source: Bill Schweber

I didn’t actually use this custom-made pad, but instead I kept it in front of me as a constant reminder that I should stick to estimates that were rough enough that they could be added up “in my head” on that pad. The reason for this simplicity is there are a lot of fuzzy numbers in the assessment.

For example, without knowing the make and model of various higher-current appliances such as the electric stove/range, any number I did use would likely have a ±10 to ±20% error band. Further, while the individual errors might cancel each other out to some extent they could also accumulate, resulting in a fairly large error band. In other words, random errors can aggregate either way.

The danger when using a spreadsheet is that soon you fall into a mental false-accuracy trap, since its available precision of more digits soon leads to the sense that there is corresponding accuracy as well, which is clearly not the case here (yes, I could restrict the cells to a few digits, but that’s another thing to do). It’s been my experience that it is very easy make the leap from rough estimate to a firm “you can bet on it” number, even if there is no basis for doing so; I’ve seen that happen in preliminary design review meetings many times when the project manager asks for some numbers.

Complicating the assessment, some of the larger loads such as the stove/range or microwave oven are under the direct control of the house occupants, while others such as heating system, refrigerator, and separate freezer control their own on/off cycles.

Numbers guide but don’t prove

I asked some questions about what was in the house, made a list, and went online to get a sense of how much current each uses. These rough estimates are for current consumption from a 120 VAC line; for those with 230 VAC lines, the current numbers should be cut in half, so that 50-A maximum would be 25 A:

1) Big loads you can’t control (these intermittent, asynchronous loads cycle on and off with unknown duty cycle; they may add up all at once, or hardly at all)

• Refrigerator/freezer: 6 A (will be higher for a few seconds, as the compressor kicks in)
• Separate outside freezer: 3 to 5 A, depending on outside temperature (same note as above)
• Oil-fired heating system: 5 A, temperature-dependent (same note as above)
• Electric water heater: 5 to 8 A

Total: around 20 A

2) Small loads (some you can control, some not; not an issue unless you are close to maximum limit

• Large TV: 1 to 2 A
• smaller screens: 0.5 A
• Various chargers: 0.5 A or less
• House lights: 0.5 A each
• House network boxes: 1 A

Total: 5 to 10 A

3) Bigger loads that you can control

• Clothes washer: 4 to 6 A
• Clothes dryer: 15 to 20 A
• Air conditioning: 8 to 10 A (but not a factor as this is a winter situation)
• Kitchen range top: 5 to 10 A, depending on model and temperature setting
• Kitchen oven: 8 to 12 A, depending on model and temperature setting
• Toaster Oven: 8 A
• Dishwasher: 9 to 12 A
• Microwave oven: 8 A
• Hair dryer: 10 to 12 A

Total: it depends on what you are using and when, but it adds up very quickly!

Conclusion: The loads you can’t control add up to around 25 A (all of these won’t be on 100% of the time) plus small loads of 5 to 10 A bring the total to 30 to 35 A, so the family will have about 15 to 20 amps of headroom on the loads that can be controlled. That’s doable but also cutting it close; you could have a case when just one additional modest load causes a droop and a brown-out of the supply voltage. That, in turn, brings on other operational problems in both motorized and all-electronic products.

Electrical service to older homes

As a curiosity, I checked out some older houses (1930 vintage) in the area, many of which are still occupied by descendants of the original families. Some of the present occupants said when the houses were built, they were outfitted with 30-A service and used knob-and-tube wiring rather than metal conduit or Romex (NM, or non-metallic sheathed) cable, Figure 2. While they have upgraded to 100+ A overs the years, some still have the knob-and-tube in the attic (not even close to code-approved now).

Figure 2 Early wiring used knob and tube insulation (a) which was replaced by (b) metal conduit (still in wide use) and (c) PVC-coated non-metallic sheathed cable, usually referred to as Romex. Sources: Arc Angel Electric Co., Meteor Electrical, D&F Liquidators

What’s your sense of the home-AC service situation? Have you ever been on a temporary or permanent limited-power budget at home? Have you ever had the corresponding “average load” versus “peak load” power-supply rating dilemma, either for line AC or with the DC supply in a product?

Bill Schweber is an EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features.

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Reference

• Arc Angel Electric, “Understanding Knob and Tube Wiring: A Comprehensive Guide”

The post Can a household manage on just 50 amps? appeared first on EDN.

After quantum computing, quantum communication is now stealing the headlines. Numana, a Montreal, Québec-based non-profit technology accelerator, has engaged Nokia and Honeywell Aerospace Technologies in its Kirq Quantum Communication Testbed to advance quantum-safe communication networks. While Nokia will contribute its advanced cryptographic network technologies, Honeywell is to share quantum encryption techniques.

Read the full story at EDN’s sister publication, EE Times.

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The post Canadian tech accelerator engages Nokia in quantum telecom testbed appeared first on EDN.

As I briefly noted back in mid-November, I ended up replacing my initial failed-experiment lithium battery-based portable power unit, Energizer’s PowerSource Pro Battery Generator:

with two EcoFlow successors, the smaller RIVER 2:

and this writeup’s subject, the DELTA 2, which I bought in claimed factory-refurbished condition (albeit, like the RIVER 2, also seemingly actually brand new) from EcoFlow via eBay in mid-September on sale (20% off list price) for $479 with an included 2-year extended warranty:

Why both? Or said another way, how do they differ? As you can likely already tell from the stock photo of each, the DELTA 2 is the huskier of the two:

	Dimensions	Weight
RIVER 2	9.6 x 8.5 x 5.7 in	7.7 lbs
DELTA 2	15.7 x 8.3 x 11 in (400 x 211 x 281 mm)	27 lbs (12 kg)

That said, EcoFlow puts the DELTA 2’s larger volume to good use with 4x the storage capacity: 1,024 Wh versus 256 Wh with the RIVER 2. The expanded front, rear and sides’ cumulative real estate also affords the DELTA 2 a larger and broader allotment of output power ports:

• Six AC (four two-prong, two three-prong with ground): 120V, 50Hz/60Hz, 1800W (along with 2200W at sub-120V per X-Boost technology, as detailed in my RIVER 2 coverage, and 2700W surge), pure sine wave, not simulated
• Two USB-A DC: 5V, 2.4A, 12W max
• Two USB-A “Fast Charge” DC: 5V @ 2.4A / 9V @ 2A / 12V @ 1.5A, 18W max
• “Cigarette lighter” car DC: 12.6V, 10A, 126W max
• Two DC5521 DC: 12.6V, 3A, 38W max (DC5525 adapter cable also included in kit)
• And two USB-C DC: 5/9/12/15/20V 5A, 100W max (unlike with the RIVER 2, however, these can’t do double-duty as charging input ports)

Unlike the RIVER 2, the DELTA 2’s storage capacity can be further expanded to between 2 kWh and (beyond) 3 kWh by tethering it to a separate DELTA 2, DELTA MAX or DELTA 2 MAX extra battery via its integrated XT150 connector:

That same XT150 connection also enables in-vehicle fast charging at up to 800W using the Alternator Charger, which I also now own ($319.20 on sale) and plan to install in my van soon:

Unfortunately, the very cool (and similar) looking PowerStream residential power unit, which I’m guessing also communicates with the DELTA 2 over XT150, isn’t currently available in the United States due to regulatory restrictions on plug-in grid solutions.

But the XT150-compatible Smart Generator is:

It’s a bit of an enigma, at least to me, given the company’s seeming heavy emphasis on solar and other renewable energy recharging sources. But hey, when the sun’s not shining but your battery’s drained, I suppose this gas-powered generator will do in a pinch instead. And although the product page implies that it only works with higher-capacity DELTA Pro and Max units, this company-published video confirms that it’s mainstream DELTA 2-compatible, too:

Whereas the RIVER 2’s XT60i DC charging input, usable with both solar and “cigarette lighter” car sources via cable adapters, is 110W max (for solar, specifically, 100W for car), the one in the DELTA 2 is beefier, supporting (again, for solar) an 11-60V and up to 15A/500W max input. Last September, I also bought two refurbished 220W second-generation EcoFlow solar panels, on sale at the time for $299 each inclusive of a two-year extended warranty:

which I’ll be cable-extending and in-parallel combining:

Stand by for coverage of them, along with hands-on impressions of the entire setup, to come.

What about AC charging? Although, as previously mentioned, the DELTA 2 has 4x the storage capacity of its RIVER 2 sibling, the charging speeds are surprisingly similar. Whereas the RIVER 2 will charge from 0% to full in 60 minutes, EcoFlow claims that the DELTA 2 will get to 80% in 50 minutes and completely full in 80 minutes. Photos taken during the first-time charging of my unit show that the initial charging rate:

automatically slows down as the full-charge threshold nears (note the input power variance):

and is eventually reached:

Here are those same first two charging segments captured by the wireless-tethered mobile app:

which is capable of simultaneously communicating with both of my EcoFlow devices:

assuming they’re both powered on at the time:

And what of generational enhancements and broader differences? As with the RIVER-to-RIVER 2 sequence I discussed in my recent coverage, EcoFlow also evolved the DELTA 2’s core battery technology from its precursor’s NMC (lithium nickel manganese cobalt), which is only capable of a few hundred recharge cycles before its maximum storage capacity degrades to unusable levels in realistic usage scenarios, to a LiFePO4 (lithium iron phosphate), also known as LFP (lithium ferrophosphate), battery formulation. Whereas the first-generation DELTA was guaranteed for only 500 recharge cycles, with the DELTA 2 it’s 3,000 (in both cases to 80+% of the original battery pack capacity), along with offering a boosted 5-year warranty.

And last September, EcoFlow launched not only the RIVER 3 family but also its first two DELTA 3 devices. The first, the DELTA 3 Plus, is now shipping as I write these words at the end of 2024:

Improvements versus the DELTA 2 predecessor include:

faster switching from wall outlet-sourced to inverter-generated AC (higher power, too) for more robust UPS functional emulation, as with the RIVER 3, along with improved airflow (leading to claimed 30 dB noise levels in normal operation), newer-generation denser 40135 batteries (translating to smaller dimensions and lighter weight, along with a boosted recharge cycle count to 4,000), expansion support up to 5 kWh, and even faster AC charging (sub-1 hour to 100%).

That all said, the DELTA 3 Plus has the same 1-kWh capacity as the non-Plus DELTA 2. What then, of the baseline DELTA 3 also briefly mentioned in last September’s unveiling, and supposedly available in October? Detailed specs are not yet public, at least to the best of my knowledge, as I submit this writeup. Instead (or in addition?), EcoFlow has stealth-launched the DELTA 3 1500:

whose two-color-option styling is reminiscent of the DELTA 2 but with boosted 1.5 kWh capacity and other tweaks. Specs are also scant for this device, but the Reddit crowd was able to dig up a user manual. My guess? EcoFlow is struggling to source enough lithium batteries (brand new DELTA 2 supplemental batteries are also MIA right now, although refurbs occasionally appear on eBay, the company website, etc.) and is dynamically evolving its product line in response.

In closing, after re-reading this piece, I realize that I may have come off as a bit (or more than a bit) of an EcoFlow “fanboy”. To be abundantly clear…I paid for all this gear myself (with no post-publication kickbacks), and the company doesn’t even know I’m doing these writeups. I just think that the products and their underlying technologies are quite cool. Agree or disagree? Let me know your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post EcoFlow’s Delta 2: Abundant Stored Energy (and Charging Options) for You appeared first on EDN.

With the emergence of smaller models and techniques like distillation, will AI scaling stop, and we won’t need more compute power? Richard Ho, head of hardware at OpenAI, firmly believes that AI scaling will continue, and compute power will grow by orders of magnitude in the near future. During his keynote address at Synopsys Snug, he also talked about OpenAI’s in-house AI accelerator, issues related to AI clusters, and AI-empowered EDA tools.

Read the full story at EDN’s sister publication, EE Times.

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The post Will compute continue scaling in AI clusters? appeared first on EDN.

R&S has expanded its EPL series of test receivers to cover EMI measurements from 5 kHz to 7.125 GHz, offering flexible configuration options. Depending on the setup, these receivers can be used in development, certification preparation, and final testing to ensure compliance with EMI standards.

Alongside the previously launched EPL1000, which covers 5 kHz to 30 MHz, the new EPL1001 and EPL1007 operate up to 1 GHz and 7.125 GHz, respectively. Basic versions include EMI bandwidths (CISPR 16-1-1, DO-160, and MIL-STD-461) and detectors (CISPR 16-1-1), RF input protection, and automatic attenuation in 1-dB steps.

An optional preselection function improves the measurement of broadband signals and short pulses, while the preamplifier included in the preselection option enables the measurement of small signals. Adding the EPL1-B1611 option upgrades the receiver to full CISPR 16-1-1 compliance, enabling the certification of the equipment under test.

Time domain scan captures entire CISPR bands A or B in a single shot and measures above CISPR band B in 20-MHz steps, saving test time and improving emission detection. Additional options like real-time spectrogram, IF analysis, and a signal generator reduce the need for extra equipment, while battery or DC power operation enables testing in various environments.

The EPL1001 and EPL1007 EMI test receivers can be ordered in Q2 2025.

EPL series product page

Rohde & Schwarz 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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The Renesas DA14533 Bluetooth LE SoC offers power management features to reduce power consumption in automotive systems. AEC-Q100 Grade 2 qualified, it operates from -40°C to +105°C and is suitable for applications such as tire pressure monitoring, keyless entry, wireless sensors, and battery management systems.

Along with an Arm Cortex-M0+ MCU, the DA14533 combines a 2.4-GHz radio transceiver, memory, peripherals, and security functions in a 22-pin wettable-flank, fine-pitch QFN package that is just 3.5×3.5 mm. Its software stack is qualified to Bluetooth Core 5.3 and includes the latest security features, enabling developers to jumpstart their projects.

An integrated DC/DC buck controller adjusts the DA14533’s output voltage to match system requirements. Active power consumption is 3.1 mA during transmission and 2.5 mA during reception, dropping to 500 nA in hibernation mode. These features help extend the operational life of small-capacity battery-powered systems.

The DA14533 is available now, supported by the Bluetooth Low Energy SoC Development Kit Pro.

DA14533 product page

Renesas Electronics

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post BLE SoC meets automotive requirements appeared first on EDN.

ST’s EVLSERVO1, a turnkey reference platform for servo motor control, enables sensorless or sensored field-oriented control (FOC) with one, two, or three shunts. It drives three-phase brushless motors up to 2 kW with the provided heatsink or 3 kW with an external fan.

The reference design features the STSPIN32G4 three-phase motor controller with an embedded STM32G4 MCU, enabling advanced position and torque control algorithms, as well as six-step control modes. It pairs with a three-phase power stage optimized for nominal bus voltages from 24 V to 48 V. The power stage, stacked with the STSPIN32G4 to maximize power density, includes six pairs of paralleled MOSFETs with low RDS(ON) of 3.2 mΩ.

With a compact 50×80×60-mm form factor, the EVLSERVO1 enables designers to develop and prototype motor control applications such as industrial and home automation, home appliances, servo drives, e-bikes, and service robots. Additionally, ST offers the X-CUBE-MCSDK for easy configuration of motor control firmware parameters.

The EVLSERVO1 reference design is available now from the eSTore and ST distributors for $168.

EVLSERVO1 product page 

STMicroelectronics

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Reference design drives servo motors appeared first on EDN.

High-sensitivity InSb Hall elements from Diodes detect rotation speed and current across a broad range of applications, even in weak magnetic fields. The AHE300 sensor supports Hall output voltage (VH) classifications C through G, ranging from 168 mV to 370 mV. The AHE10x sensors support VH classifications C through H, with output voltages from 168 mV to 415 mV.

These Hall elements are well-suited for mobile phone and laptop opening detection, joystick control, and magnetic encoding. They are also used in current measurements with clamp-type overhead wire ammeters, as well as for position detection in brushless motors and wheel rotation speed monitoring.

Additionally, the devices enable contactless commutation, speed measurements, and angular position sensing in consumer appliances, office equipment, and industrial systems. The sensors’ low offset voltage (5 mV to 7 mV) ensures the high resolution required for accurate detection in these applications.

The AHE300 operates from -40°C to +110°C in a SIP-4 package and costs $0.18 each in 500-piece quantities. AHE10x devices cover a wider -40°C to +125°C range, making them suitable for harsh thermal environments. They come in SOT23-4 packages with various height options and cost $0.10 each in 3,000-piece quantities.

AHE300 product page

AHE10x product page

Diodes

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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The first in a new line of immersion temperature sensors, the B58101A0851A000 from TDK is designed specifically for EV powertrain cooling. Compact and lightweight (<11 g), this fully sealed NTC thermistor provides fast, precise temperature measurement in oil-cooled systems.

Oil cooling is emerging as the preferred method for EV drivetrain thermal management, offering superior performance over conventional water-glycol systems. By directly cooling motors and inverters, it enhances efficiency, extends component lifespan, and supports higher power densities—key for next-gen EVs.

The B58101A0851A000 sensor has a thermal time constant of <4 s (τ63%) in water and maintains accuracy within ±1 K from -40°C to ≤125°C. It operates up to +150°C and withstands system pressures up to 10 bar. With a nominal resistance of 5 kΩ at 25°C and a tolerance of ±1%, the device ensures reliable performance across a wide range of conditions.

Designed for durability, the immersion temperature sensor resists ZF EcoFluid E gear oil used in electric drive systems. Its resistance-temperature curve is customizable, and it adapts to various installation positions, cooling fluids, and mounting configurations.

The B58101A0851A000 sensor is available now from DigiKey and Mouser Electronics.

B58101A0851A000 product page

TDK

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Sensor aids EV thermal management appeared first on EDN.

In this look at transmission line theory, we will assume an RG-58 type of coaxial cable which has a characteristic impedance of 50 Ω. Where we let C stand for the capacitance per unit length, 30 pF per foot in this case, the characteristic impedance Zo = sqrt(L/C) where L is the inductance per unit length. This gives L = Zo²×C = 75 nH per foot.

We make a very simplistic MultiSim SPICE model of the transmission line being driven by a 50-Ω source impedance of the left in the Figure 1 with a load resistance whose value we are going to set to several different values, to 10,000 Ω, to 50 Ω, and then to 5 Ω while we examine the effects of each as a study of time domain reflectometry (TDR).

Figure 1 TDR result from a MultiSim SPICE model of a transmission line driven by a 50-Ω source impedance (R1) and where load resistance, R2, is set 10,000 Ω.

In Figure 1, using a square wave signal source, we see the signal takes 16.5 ns to make its way down the transmission line to arrive at R2. During that time, the signal input end at V1 and R1 presents an input impedance of 50 Ω, the cable’s characteristic impedance Zo.

Since the R2 value does not match Zo, energy transfer into R2 is incomplete and some of the arriving energy gets reflected back toward the left again. When that reflection reaches R1 in another 16.5 ns—a total transit time of 33 ns—the impedance presented to the V1 and R1 pair jumps up and we see the input voltage at the left end of the transmission line jump up too.

The propagation velocity and the velocity factor of the transmission line are calculable from the transit times are nearly two-thirds the speed of light in free space, just as in the published data for this cable.

In Figure 2, when we have R2 at 50 Ω, there is a match to Zo and no energy gets reflected back again. When we have R2 at only 5 Ω, we have a mismatch to Zo again and a reflection back toward the left, but the impedance at the left end drops instead of rising.

Figure 2 TDR Results for load R2 = 50 Ω, showing a match with no energy reflected back, and for R2 = 5 Ω showing a mismatch and energy reflected back.

Of course, this SPICE model is very crude in that each LC pair represents one foot of cable length. A more finely grained model with many more LC pairs per unit length would yield better waveform results than we’ve shown here.

For the sake of illustrating these principles though, I beg your forgiveness.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Time domain reflectometry  appeared first on EDN.

PCIe, the most successful interconnect technology for more than 25 years, is entering a new phase of complexity with the adoption of PCIe 6.0, which is now largely driving artificial intelligence (AI) workloads. Gary Hilson talks to senior managers at Broadcom and Astera Labs to understand issues related to PCIe 6.0 system design, interoperability and performance testing. These issues are critical in PCIe 6.0 deployment in advanced AI data centers.

Read the full story at EDN’s sister publication, EE Times.

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The post A closer look at PCIe 6.0 interoperability, performance testing appeared first on EDN.

LM317 fans will recognize Figure 1 as the traditional LM317 constant current source topology. It closely regulates Iout = Vadj/Rs by forcing the OUTPUT pin to be Vadj = 1.25 V positive relative to the ADJ pin. Thus, Iout = Vadj/Rs to a very good approximation. Master chip chef Bob Pease cooked it up to be so!

Figure 1 Classic LM317 constant current source,
Iout = Vadj/Rs + Iadj ≃ Vadj/Rs = 1.25/Rs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In usual practice, Iout >> Iadj, the latter being specified at 50 µA typical, 100 µA max. This simplifies the math by making the Iadj bias current safely ignorable without letting accuracy take a hit. It’s worked great for 50 years but it has an obvious downside. the way you program Iout is by changing Rs.

Figure 2 shows a new(er) topology with a different (more agile) method for making Iout programmable.

Figure 2 A novel LM317 topology enables control of amps of Iout with just milliamps of Ic,
Iout = (Vadj – (Ic – Iadj)Rc)/Rs – Ic + Iadj ≃ (Vadj – (Ic – Iadj)Rc)/Rs. 

Typically, Rc > 100Rs, making Figure 2 able to control up to 1.5 A of Iout with just milliamps of Ic. Of course, now it may no longer be good enough to just ignore Iadj. 

Figure 3 shows the idea fleshed out into a complete PWM controlled 15 V, 1 A, grounded-load current source that includes Iadj compensation. Here’s how it works.

Figure 3 The 1-A, 15-V, PWM-programmed grounded-load current source with a novel LM317 topology. The asterisked resistors are 1% or better and Rs = 1.25 Ω.

The 5-Vpp PWM input has a frequency (Fpwm) assumed to be 10 kHz or thereabouts. If it doesn’t, scale C1 appropriately with:

C1 = 22µF*10kHz/Fpwm

The resulting PWM switching of Q2 creates a variable resistance averaged by C1 to Rc(1 + 1/Df) where Df = the 0 to 1 PWM duty factor.  Thus a (0 to 2.5v)/2Rc = 3.11 mA Ic current = 2.5v/Rc(1 + 1/Df) flows into Z1’s summing point.

Z1 servos the V1 gate drive of Q1 to hold its source at an accurate 2.5-V reference for the PWM conversion and to level shift Ic to track U1’s ADJ pin. Also summed with Ic is Iadj bias compensation (2.5v/51k = 50µA) provided by R1.

The unsightly stack of six 1N4001’s is needed to provide bias for Q1 to work into. I freely admit that it’s not very pretty. Hopefully the novelty of Figure 2 makes up for it! 

Note that accuracy and linearity mostly depend only on the match of the Rc resistors and the precision of the Z1 and U1 internal references. It’s a happy coincidence that the 2:1 ratio of the TL431’s 2.5-V versus the LM317’s 1.25 V permits the convenient use of three identical Rc resistors.

If Rs = 1.25 Ω, then Iout(max) = 1 A and Iout versus Df is as plotted in Figure 4.

Figure 4 Iout versus Df where Df (x-axis) is the PWM duty factor and Iout (y-axis) is Vadj/1.25 = 1 A full-scale = 1 – 2/(1 + 1/Df).

 Df versus Iout is plotted in Figure 5.

Figure 5 Df versus Iout where Iout (x-axis) is 1 A full-scale and Df (y-axis) = 1/(2/(1 – Iout) – 1).

Note that U1 might be called upon to dissipate as much as:

• 20 W if Rs = 1.25 Ω and Iout(max) = 1 A
• 30 W if Rs = 0.83 Ω and Iout(max) = 1.5A

Moral of the story: don’t be skimpy on the heatsink! Also note that Rs should be rated for a wattage of at least 1.252/Rs.

Then there’s the consideration of power up/down transients. When the system is first switched on and C1 is sitting discharged, and the controller will have about 4 to 8 milliseconds to initialize the PWM logic to 1.0 before C1 can charge enough to allow U1 to come on and start sourcing current. Don’t forget this detail during software development! On power-down, Q3 kicks in when +5 V drops below ~2 V. This saturates Q1 and forces Iout to zero to protect the load as well as discharging C1 in preparation for the next power-up.

In closing, thanks go (again) to savvy reader Ashutosh for his suggestion that the Figure 2 topology might deserve a focused DI of its own, and (likewise again) to editor Aalyia for the fertile DI environment she has created that makes this kind of teamwork, well, workable!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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• LM317 smooths but doesn’t regulate
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• Power Zener using the LM317
• Use an LM317 as 0 to 3V adjustable regulator

The post PWM-programmed LM317 constant current source appeared first on EDN.

Semiconductor compute has grown drastically over the past 18 to 24 months amid the vast artificial intelligence (AI) infrastructure buildup. Nvidia and hyperscalers have made many announcements about migrating to GPUs with 200 Gbps per lane speeds. However, with computation moving to higher data rates, optical connectivity must also migrate to higher data rates.

But here comes the rub. While the rapid growth of AI workloads drives demand for increased bandwidth and interconnect density in AI clusters, optical interconnect power is a major factor limiting cluster scalability. Broadcom claims its new Sian3 and Sian2M PHY chips supporting 200 G/lane speeds offer greater levels of power efficiency and cost optimization for next-generation AI infrastructure.

Figure 1 Sian3 and Sian2M DSP PHYs enable module developers to rapidly address the growing demand for 200G optics in AI. Source: Broadcom

Optical connections can be short-reach or long-reach because sometimes AI clusters are in two different buildings. Natarajan Ramachandran, director of product line management for Broadcom’s Physical Layer Products Division, told EDN that Sian2M and Sian3 devices address these two scenarios, respectively.

Sian2M PHY chips

Ramachandran said that for shorter distances of less than 100 m, traditional optics, commonly termed multi-mode optics (MMF), is used. Here, vertical-cavity surface-emitting laser (VCSEL) technology has scaled very well so far. “However, in transition from 800 Gbps to 1.6 Tbps, VCSELs increasingly face physics limitations, making short-link bandwidths hugely constrained.”

Sian2M provides an optimized solution for 800G and 1.6T short-reach MMF links within AI clusters. It’s the first 200 G/lane DSP with integrated VCSEL drivers that enables low-power short-reach MMF links in AI clusters. “While industry watchers mostly believed that short link optics has reached a dead end, we are extending its life by at least one more generation,” Ramachandran said.

For longer distances of 2 Km to 3 Km operating across single-mode fiber (SMF) links, problems lie in power consumption. At 800 Gbps, power consumption was 15-16 W; but when you go to 1.6 Tbps, you don’t want to double the power usage. Enter Sian3 PHY chip.

Figure 2 Sian3 and Sian2M DSPs optimize power across single-mode fiber (SMF) and short-reach multi-mode fiber (MMF) links in 800G and 1.6T optical transceiver applications. Source: Broadcom

Sian3 PHY chips

At GTC 2025, held in San Jose, California, from 17 to 21 March, Nvidia’s chief Jensen Huang stressed the need for picojoule per bit to come down. That’s where Siam3 comes in, said Ramachandran. “We achieved 28 W with Sian2 while competition is roughly at 32 W,” he added. “With Siam3, a follow-on to Siam2, the transition from 5 nm to 3nm node results in 5-W savings, bringing power consumption down to 23 W.”

“So, we are getting close to what we’ve been consuming at 800 Gbps while moving to 1.6 Tbps speeds,” Ramachandran said. “And picojoule per bit is also showing a nice downward trend.” He also stated Broadcom’s aim to lower power consumption numbers, eventually reaching less than 20 W.

But is the cost also going down? Besides picojoule per bit, what about dollar per bit? Ramachandran said that with the transition from 5-nm to 3-nm process node, the die size also shrinks a lot, which significantly impacts the cost.

Broadcom is sampling Sian3 and Sian2M chips to early access customers and partners; Sian3 production is ramping up in the third quarter of 2025. Broadcom will demonstrate Sian chips and 200G VCSEL operating inside 1.6T optical modules at OFC in San Francisco, California, to be held on 1-3 April 2025.

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• Interfacing Fast Ethernet Transceivers with PHY ICs

The post Optical PHYs facilitate 200G/lane speeds for AI clusters appeared first on EDN.

Injection locking [1] can not only improve oscillator frequency stability and phase noise, but act as a selective frequency divider as well [2][3].

You can find sample setups of a simple two-transistor LC-based Peltz oscillator acting as a selective frequency divider in “Simple 5-component oscillator works below 0.8V” and “Investigating injection locking with DSO Bode function”.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The oscillator in the setup and shown in Figure 1 is just a pair of 2N3904s, a 10 µH inductor, a 2.6 nF capacitor, and a 1K bias resistor operating from -2 V. This produces a ~1 MHz oscillator output.

Figure 1 The Peltz oscillator found in the “Simple 5-component oscillator works below 0.8V” design idea (DI) consisting of only 5 components.

Signal injection is by means of a series 10 KΩ and 0.01 µF RC connected to the common emitters of the Q1 and Q2 2N3906 transistors. The subtle non-linearities within the oscillator allow selective frequency locking and division without additional active components. Figure 2 shows examples of frequency division by 2, 3, 5, and 10 respectively without any component values or circuit changes!

Figure 2 Examples of frequency division by 2, 3, 5, and 10 without any changes to the component values or circuit, this is due to the subtle non-linearities within the oscillator that allow selective frequency locking and division.

Injection locking also improves the oscillator phase noise even when acting as a divider. Figure 3 shows some results from the free running oscillator and when acting as a frequency-selective divider.

Figure 3 Spectrum analysis of the oscillator free running and when acting as a frequency-selective divider with an injection-locked division of 3 and 10. There is a marked improvement in phase noise when acting as a frequency-selective divider.

The test setup used a general-purpose AWG (SDG2042X) as the signal source, a DSO (SDS814X HD) and spectrum analyzer (SSA3021X Plus) for the displays. Of course this technique isn’t going to replace a proper digital divider, but might find use in a pinch when one needs frequency division, or improve a simple oscillators stability and phase noise.

Michael A Wyatt is a life member with IEEE and has continued to enjoy electronics ever since his childhood. Mike has a long career spanning Honeywell, Northrop Grumman, Insyte/ITT/Ex-elis/Harris, ViaSat and retiring (semi) with Wyatt Labs. During his career he accumulated 32 US Patents and in the past published a few EDN Articles including Best Idea of the Year in 1989.

 Related Content

• Simple 5-component oscillator works below 0.8V
• Investigating injection locking with DSO Bode function
• Ultra-low distortion oscillator, part 1: how not to do it.
• Ultra-low distortion oscillator, part 2: the real deal
• The Colpitts oscillator
• A two transistor sine wave oscillator
• Clapp versus Colpitts

References

1. Razavi, B. “A study of injection pulling and locking in oscillators.” Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., pp. 305–312, https://doi.org/10.1109/cicc.2003.1249409.
2. “EEVblog Electronics Community Forum.” SMD Test Fixture for the Tektronix 576 Curve Tracer – Page 1, eevblog.com/forum/projects/smd-test-fixture-for-the-tektronix-576-curve-tracer/.
3. “EEVblog Electronics Community Forum.” Injection Locked Peltz Oscillator with Bode Analysis – Page 1, www.eevblog.com/forum/projects/injection-locked-peltz-oscillator-with-bode-analysis/. Accessed 25 Mar. 2025.

 

The post Injection locking acts as a frequency divider and improves oscillator performance appeared first on EDN.

A few weeks ago, I told you about (among other things) the iPhone 16e, Apple’s latest “entry-level” smartphone and the pricier successor to the three-generation iPhone SE series:

I couldn’t resist noting that Google had responded to Apple’s news with a (temporary, as it turned out) price cut on its (then-)latest-generation entry-level smartphone, the Pixel 8a, to $399. That said, I’d already suspected (rumor-aided) that this likely wasn’t just a competitive counterpunch. Google was probably also doing some inventory-clearing in advance of a pending unveil of its own next-gen entry-level smartphone, presumably to be called the Pixel 9a.

The Pixel 9a reveal

I was right; this year Google didn’t even wait until the late May I/O conference to reveal it (that said, in retrospect the haste may not have been wise). Behold the Pixel 9a, which starts at $499:

and which (currently, at least) comes in four color options:

I chose the above image not only because it shows the color variants but because it also highlights one of the key differences between the Pixel 9a and its most recent three generational precursors. Look, for example, at the backside of the Pixel 8a:

Beginning with the Pixel 6 family, Google had switched to a backside style that grouped the camera (or multi-camera cluster), scene-illumination flash LED, microphone, and other related sensors into a horizontal raised bar, continuing that same style with “a” variants. With the Pixel 9a, conversely, Google seems to have returned to the (near-)flush approach exemplified by, for example, the Pixel 4a 5G handsets I owned prior to my current Pixel 7s:

I dunno why…mebbe the raised-bar approach made them more breakage-prone? Or mebbe they wanted it to look like an iPhone? Regardless, per Aalyia’s request , here’s a broader comparison table of the most recent two “a” generations, as well as the Pixel 9 introduced in-between them late last summer (to keep things simple, I left out the two Pixel 9 Pro variants):

	Pixel 8a	Pixel 9	Pixel 9a
Price	$499/$559	$799/$899	$499/$599
Storage	128 GB/256 GB	128 GB/256 GB	128 GB/256 GB
DRAM	8 GB (LPDDR5X)	12 GB (LPDDR5X)	8 GB (LPDDR5X)
Size	Height: 5.99 in (152.1 mm) Width: 2.86 in (72.7 mm) Depth: 0.35 in (8.9 mm)	Height: 6.02 in (152.8 mm) Width: 2.83 in (72 mm) Depth: 0.33 in (8.5 mm)	Height: 6.09 in (154.7 mm) Width: 2.89 in (73.3 mm) Depth: 0.35 in (8.9 mm)
Weight	6.63 oz (188g)	6.98 oz (198g)	6.56 oz (186g)
Screen	6.1-inch 20:9 aspect ratio 1080 x 2400 OLED at 430 PPI  60-120 Hz Up to 1400 nits (HDR) and up to 2000 nits (peak brightness)	6.3-inch 20:9 aspect ratio 1080 x 2424 OLED at 422 PPI 60-120Hz Up to 1800 nits (HDR) and up to 2700 nits (peak brightness)	6.3-inch 20:9 aspect ratio 1080 x 2424 pOLED at 422.2 PPI 60-120Hz Up to 1800 nits (HDR) and up to 2700 nits (peak brightness)
SoC	Google Tensor G3	Google Tensor G4	Google Tensor G4
CPU	Nona-core: 1× 2.91 GHz Cortex-X3 4× 2.37 GHz Cortex-A715 4× 1.7 GHz Cortex-A510	Octa-core: 1× 3.1 GHz Cortex-X4 3× 2.6 GHz Cortex-A720 4× 1.92 GHz Cortex-A520	Octa-core: 1× 3.1 GHz Cortex-X4 3× 2.6 GHz Cortex-A720 4× 1.92 GHz Cortex-A520
GPU	Mali-G715 MP7 890 MHz	Mali-G715 MP7 940 MHz	Mali-G715 MP7 940 MHz
NPU	3rd Gen Edge TPU	3rd Gen Edge TPU	3rd Gen Edge TPU
Cellular modem	Exynos 5300i	Exynos 5400c	Exynos 5300i
Front camera	13 MP camera ƒ/2.2 aperture 96.5° ultrawide field of view	10.5 MP Dual PD camera with autofocus ƒ/2.2 aperture 95° ultrawide field of view	13 MP camera ƒ/2.2 aperture 96.1° ultrawide field of view
Rear camera(s)	Dual rear camera system: optical zoom at 0.5x and 1x, digital zoom up to 8x 64 MP Quad PD wide camera ƒ/1.89 aperture 80° field of view 13 MP ultrawide camera ƒ/2.2 aperture 120° field of view	Dual rear camera system: optical zoom at 0.5x, 1x and 2x, digital zoom up to 8x 50 MP Octa PD wide camera ƒ/1.68 aperture 82° field of view 48 MP Quad PD ultrawide camera with autofocus ƒ/1.7 aperture 123° field of view	Dual rear camera system: optical zoom at 0.5x and 1x, digital zoom up to 8x 48 MP Quad PD Dual Pixel with closeup AF ƒ/1.7 aperture 82° field of view Optical + electronic image stabilization 13 MP ultrawide camera ƒ/2.2 aperture 120° field of view
Wireless charging	7.5W	15W	7.5W
Wired charging	18W USB-PD	27W USB-PD	23W USB-PD
Battery capacity	4492 mAh	4700 mAh	Typical 5100 mAh (minimum 5000 mAh)
Dust/water resistance	IP67	IP68	IP68

Pixel 9a observations

Several particularly interesting bits jump out at me:

• As I’d mentioned late last summer, Google had originally only planned for Gemini deep learning support to be enabled for the Pixel 8 Pro with 12 GBytes of RAM; the company subsequently developed a “Nano” variant of Gemini capable of being shoehorned into the 8 GBytes of RAM in other Pixel 8 versions. So, you might assume that the Pixel 9a, also with 8 GBytes of RAM, would also be Gemini-cognizant. And you’d be right…except this time, Google’s referring to the Gemini version as “Gemini Nano 1.0 XXS (extra extra small)”. Then again, the version available for Pixel smartphones with 12 GBytes or more of RAM is no longer just “Gemini Nano”, it’s “Gemini Nano XS (extra small)”. My guess as to what’s happening is just some rebranding of what already exists; as baseline Gemini becomes more feature-filled, the need to differentiate it from the version(s) running on phones and other resource-constrained devices therefore becomes more necessary.
• The selective mixing-and-matching within each device’s SoC is interesting. The Pixel 9a gets the Pixel 9’s CPU and other processing subsystems, but the cellular modem is a generational backstep, reverting to what was in the Pixel 8s (and 7s, for that matter). The modems and CPUs listed in this particular table are actually all fabricated on 4 nm Samsung processes, but I’m guessing that everything’s not integrated within a single die. Instead, the CPU and modem die are likely side-by-side (or alternatively sandwiched) within a common package, simplifying the mix-and-match process. Keep in mind, too, that whereas Google (generally speaking) is more forthright about its phones’ specs than is Apple, neither company publishes clock speeds. While my table shows the maximum documented speeds of various processing cores, it’s not guaranteed that they run at that speed in a particular system-implementation configuration.
• In many respects, the Pixel 9a is the latest in a long line of handsets derived from their earlier-announced, fuller-featured generational siblings. It swaps out the Pixel 9’s glass-and-aluminum frame back for plastic, for example, and its wireless charging support is conventional in power, therefore speeds, not “supercharged”. That said, there were some surprising deviations from usual form. The Pixel 9a is the only one of the three to explicitly list as features both optical and electronic image stabilization, for example, for its rear wide-angle camera. And its wired charging power-therefore-speed was nearly as fast as that of the Pixel 9, as well as being a significant improvement on the Pixel 8a.
• Further comparing the Pixel 9a to its direct forebear, the Pixel 8a, the aforementioned rear wide camera, for example, has also decreased in resolution by 25%, although both image sensors have equivalent 0.8µm pixel pitch (i.e., light-gathering capability). Plus, the new camera’s maximum aperture is larger, for improved low-light performance, further aided by the already-noted enhanced image stabilization support. The Pixel 9a offers slightly improved dust and moisture resistance than its Pixel 8a predecessor, too. That said, curiously, the 256GB version of the Pixel 9a costs $40 more than the 256GB Pixel 8a, $599 versus $559, although the 128GB versions of both handset generations are identically priced at $499.
• And check out that comparatively sizeable battery in the Pixel 9a versus either of the others! It’s particularly impressive given that the Pixel 9a is still lighter than the Pixel 8a. But what’s with the charge capacity variability; multiple battery suppliers, mebbe?

Pixel 9a vs iPhone 6e

Speaking of comparisons (and of Apple), how does the Pixel 9a stack up against the iPhone 16e? This analysis is simultaneously easier (from a hardware standpoint) and harder (from a usability perspective). Specs first; the Pixel 9a has (for example):

• A lower price tag ($499 vs $599, in both cases for versions with 256 GBytes of storage)
• A slightly larger display (6.3” diagonal versus 6.1”) with a 2x higher peak refresh rate (120 Hz versus 60 Hz), albeit at slightly lower resolution (1080 x 2,424 pixels/421ppi vs 1,170 x 2,532 pixels/460 ppi)
• Two rear cameras versus one, and
• A ~25% larger battery (5,100mAh versus 4,005mAh), along with
• Slightly more advanced Wi-Fi (6E vs 6) and Bluetooth (6 versus 5.3)

And now that Apple has indefinitely delayed the more personalized aspects of its Apple Intelligence capabilities, Google (with Gemini) has an advantage here as well, conceptually, at least. The thing is, though, AI doesn’t yet seem to be tangibly propelling smartphone sales. More generally, the fierce loyalty divide between Android and iOS users is akin to that between “blue” and “red” states. Take my household as an example; although originally a periodic “switcher”, I’ve settled on Android for a while now, although my tablets run iPadOS. Conversely, paraphrasing Charlton Heston, my wife would likely only give up her iPhone if you pried it from her cold, dead hands. And speaking of “indefinite delays”, Google (presumably driven by a decision made at the last pre-launch minute) is no longer saying exactly when the Pixel 9a will start shipping (only a nebulous “April”, and isn’t even yet accepting pre-orders for the handset, all due to an unspecified “component quality issue”.

Swollen battery

Maybe the problem’s with the battery? I jest (maybe), in transitioning (in closing) to the “distended” portion of this piece mentioned in the title. Long-time readers may remember that back in September 2020, I mentioned that in-parallel (fortuitously) with their replacement by Pixel 3as, my original Google Pixels were beginning to exhibit swollen-battery symptoms:

Well, look at what I noticed a couple of weeks ago on one of my Pixel 7s:

Lest you think that’s just an artifact of the case or the screen protector, here’s a “naked” view:

The left-side swell isn’t as pronounced:

which makes sense when, as iFixit’s teardown guide makes clear, you learn that the battery’s placement is right-side dominant:

This was my “work” phone, which was used less often (therefore spent more time just sitting trickle-charging) than its “personal” sibling. And although I had Adaptive Charging enabled, I hadn’t taken the extra step of limiting the peak charge point to 80% of total capacity.

Plus, the phone (purchased in June 2023) was beyond its one year of factory warranty support. That said, I’d fortunately also purchased Asurion’s 36-month extended warranty coverage at that same time. This writeup’s already in “extra innings”, so I’ll save the rest of the (good ending, mind you) story for another post at another time to come. Until then, please share your thoughts on what I’ve so-far discussed in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post Google’s Pixel Smartphone Line: Extended and…Distended? appeared first on EDN.

High-bandwidth memory (HBM) is again in the limelight. At GTC 2025, held in San Jose, California, from 17 to 21 March, SK hynix displayed its 12-high HBM3E devices for artificial intelligence (AI) servers. The Korean memory maker also showcased a model of its 12-high HBM4, currently under development, claiming that it’s now completing the preparatory works for large-scale production of the 12-high HBM4 in the second half of 2025.

Micron, another leading memory supplier, is signaling strong demand for its HBM chips in AI and high-performance computing (HPC) applications. Micron’s chief business officer, Sumit Sadana, told Reuters that all of Micron’s HBM chips are sold out for the calendar year 2025.

Figure 1 HBM is creating a new “near memory” space between cache and main memory. Source: IDTechEx

HBM—essentially a 3D structure of vertically stacked DRAM dies on top of a logic die—relies on advanced packaging technologies like through silicon vias (TSVs) while using a silicon interposer for interconnection with the processor. It’s proving highly suitable in parallel compute environments such as HPC and AI workloads.

That’s because it can handle multiple memory requests simultaneously from various cores in GPUs and AI accelerators to facilitate parallel workload processing. In fact, HBM has become the main venue for overcoming memory bottlenecks in data-intensive HPC and AI workloads. Otherwise, these memory bottlenecks lead to underutilization of AI processors.

What’s also pivotal about HBM devices is their continued development to improve AI accelerator performance. For instance, the current generation HBM3E devices use thermal compression with micro-bumps and underfills to stack DRAM dies. Next, HBM makers like Micron, Samsung and SK hynix are transitioning toward HBM4 devices, which employ advanced packaging technologies such as copper-copper hybrid bonding to increase input/outputs, lower power consumption, improve heat dissipation, and reduce electrode dimensions.

Market research firm IDTechEx’s report “Hardware for HPC, Data Centers, and AI 2025-2035: Technologies, Markets, Forecasts” assesses the key developments and trends in HBM devices serving AI and HPC workloads. It also projects that compared to 2024, the unit sales of HBM are forecast to increase 15-fold by 2035.

Figure 2 The booming AI and HPC hardware is forecast to increase HBM sales 15-fold by 2035. Source: IDTechEx

HBM was a prominent technology highlight in 2024 for its ability to overcome the memory wall for AI processors. With the emergence of HBM4 memory devices, that trend is likely to continue in 2025 and beyond.

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• HBM Flourishes, But HMC Lives
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• High-bandwidth memory (HBM) options for demanding compute

The post HBM memory and AI processors: Happy together appeared first on EDN.

Due to their versatility, ease of design, and low cost, flyback converters have become one of the most widely used topologies in power electronics. Its structure derives from one of the three basic topologies—specifically, buck-boost topology. However, unlike buck-boost converters, flyback topologies allow the voltage output to be electrically isolated from the input power supply. This feature is vital for industrial and consumer applications.

Among the different control methods used to stabilize power converters, the most widely used control method is peak current mode, which continuously senses the primary current to provide important protection for the power supply.

Additionally, to obtain a higher design performance, it’s common to regulate the converter with the output that has the highest load using a technique called cross-regulation.

This article aims to show engineers how to correctly design the control loop that stabilizes the flyback converter in order to provide optimal functionality. This process includes minimizing the stationary error, increasing/decreasing the bandwidth as required, and increasing the phase/gain margin as much as possible.

Closed-loop flyback converter block diagram

Before making the necessary calculations for the controller to stabilize the peak current control mode flyback, it’s important to understand the components of the entire closed-loop system: the converter averaged model and the control loop (Figure 1).

              Figure 1 Here is how the components look in the entire closed-loop system. Source: Monolithic Power Systems

The design engineer’s main interest is to study the behavior of the converter under load changes. Considering a fixed input voltage (VIN), the open-loop transfer function can be modeled under small perturbations produced in the duty cycle to study the power supply’s dynamic response.

The summarized open-loop system can be modeled with Equation 1:              (1)

Where G is the current-sense gain transformed to voltage and GC(s) and GCI(s) are the transfer functions of the flyback converter in terms of output voltage and magnetizing current response (respectively) under small perturbations in the duty cycle. GαTS is the modeling of the ramp compensation to avoid the double-pole oscillation at half of the switching frequency.

Flyback converter control design

There are many decisions and tradeoffs involved in designing the flyback converter’s control loop. The following sections of the article will explain the design process step by step. Figure 2 shows the design flow.

Figure 2 The design flow highlights control loop creation step by step. Source: Monolithic Power Systems

Control loop design process and calculations

Step 1: Design inputs

Once the converter’s main parameters have been designed according to the relevant specifications, it’s time to define the parameters as inputs for the control loop design. These parameters include the input and output voltages (VIN and VOUT, respectively), operation mode, switching frequency (fSW), duty cycle, magnetizing inductance (LM), turns ratio (NP:NS), shunt resistor (RSHUNT), and output capacitance (COUT). Table 1 shows a summary of the design inputs for the circuit discussed in this article.

Table 1 Here is a summary of design inputs required for creating control loop. Source: Monolithic Power Systems

To design a flyback converter compensator, it’s necessary to first obtain all main components that make the converter. Here, HF500-40 flyback regulator is used to demonstrate design of a compensator using optocoupler feedback. This device is a fixed-frequency, current-mode regulator with built-in slope compensation. Because the converter works in continuous conduction mode (CCM) at low line input, a double-pole oscillation at half of the switching frequency is produced; built-in slope compensation dampens this oscillation, making its effect almost null.

Step 2: Calculate parameters of the open-loop transfer function

It’s vital to calculate the parameters of the open-loop transfer function and calculate the values for all of the compensator’s parameters that can optimize the converter at the dynamic behavior level.

The open-loop transfer function of the peak current control flyback converter (also including the compensation ramp factor) can be estimated with Equation 2:

      (2)

Where D’ is defined by the percentage of time that the secondary diode (or synchronous FET) is active during a switching cycle.

The basic canonical model can be defined with Equation 3:              (3)

Note that the equivalent series resistance (ESR) effect on the output capacitors has been included in the transfer function, as it’s the most significant parasitic effect.

By using Equation 2 and Equation 3, it’s possible to calculate the vital parameters.

The resonant frequency (fO) can be calculated with Equation 4:

              (4)

After inputting the relevant values, fO can be calculated with Equation 5:              (5)

The right-half-plane zero (fRHP) can be estimated with Equation 6:              (6)

The q-factor (Q) can be calculated with Equation 7:              (7)

After inputting the relevant values, Q can be estimated with Equation 8:              (8)

The DC gain (K) can be calculated with Equation 9:              (9)

After inputting the relevant values, K can be estimated with Equation 10:              (10)

The high-frequency zero (fHF) can be calculated with Equation 11:

              (11)

It’s important to note that with current mode control, it’s common to obtain values well below 0.5 for Q. With this in mind, the result of the second-degree polynomial in the denominator of the transfer function ends up giving two real and negative poles. This is different from voltage-control mode or when there is a very large compensation ramp, which results in two complex conjugate poles.

The two real and negative poles can be estimated with Equation 12:              (12)

The new open-loop transfer function can be calculated with Equation 13:              (13)

The cutoff frequency (fC) can be estimated with Equation 14:              (14)

The following sections will explain how the frequency compensator design achieves power supply stability and excellent performance.

Step 3: Frequency compensator design

Once the open-loop transfer function is modeled, it’s necessary to design the frequency compensator such that it achieves the best performance possible. Because the frequency response of the above transfer function has two separate poles—one at a low frequency and one at a high frequency—a simple Type II compensator can be designed. This compensator does not need an additional zero, which is not the case in voltage-control mode because there is a double pole that produces a resonance.

To minimize the steady-state error, it’s necessary to design an inverted-zero (or a pole at the origin) because it produces higher gains at low frequencies. To ensure that the system’s stability is not impacted, the frequency must be at least 10 times lower than the first pole, calculated with Equation 15:

           (15)

Due to the ESR parasitic effect at high frequencies, it’s necessary to design a high-frequency pole to compensate for and remove this effect. The pole can be estimated with Equation 16:

(16)

On the other hand, it’s common to modify the cutoff frequency to achieve a higher or lower bandwidth and produce faster or slower dynamic responses, respectively. Once the cutoff frequency is selected (in this case, fC is increased up to 6.5 kHz, or 10% of fSW), the compensator’s middle-frequency gain can be calculated with Equation 17:           (17)

Once the compensator has been designed within the frequency range, calculate the values of the passive components.

Step 4: Design the compensator’s passive components

The most common Type II compensator used for stabilization in current control mode flyback converters with cross-regulation is made up of an optocoupler feedback (Figure 3).

Figure 3 Type-II compensator is made up with optocoupler feedback. Source: Monolithic Power Systems

The compensator transfer function based on optocoupler feedback can be estimated with Equation 18:          (18)

The middle-frequency gain is formed in two stages: the optocoupler gain and the adjustable voltage reference compensator gain, calculated with Equation 19:

(19)

It’s important to calculate the maximum resistance to correctly bias the optocoupler. This resistance can be estimated with Equation 20:     (20)

The parameters necessary to calculate RD can be found in the optocoupler and the adjustable voltage reference datasheets. Table 2 shows the typical values for these parameters from the optocoupler.

Table 2 Here are the main optocoupler parameters. Source: Monolithic Power Systems

Table 3 shows the typical values for these parameters from the adjustable voltage reference.

Table 3 The above data shows adjustable voltage reference parameters. Source: Monolithic Power Systems

Once the above parameters have been obtained, RD can be calculated with Equation 21:              (21)

Once the value of R3 is obtained (in this case, R3 is internal to the HF500-40 controller, with a minimum value of 12 kΩ), as well as the values for R1, R2, and RD (where RD = 2 kΩ), RF can be estimated with Equation 22:   (22)

Where GCOMP is the compensator’s middle frequency gain, calculated with Equation (17). GCOMP is used to adjust the power supply’s bandwidth.

Because the inverted zero and high-frequency pole were already calculated, CF and CFB can be calculated with Equation 23 and Equation 24, respectively.         (23)           (24)

Once the open-loop system and compensator have been designed, the loop gain transfer function can be estimated with Equation 25:           (25)

Equation 25 is based on Equation 13 and Equation 18.

It’s important to calculate the phase and gain margins to ensure the stability of power supply.

The phase margin can be calculated with Equation 26:          (26)

After inputting the relevant values, the phase margin can be calculated with Equation 27:          (27)

If the phase margin exceeds 50°, it’s an important parameter necessary to comply with certain standards.

At the same time, the gain margin can be approximated with Equation 28:            (28)

Equation 29 is derived from Equation 25 at the specified frequency:     (29)

In this scenario, the gain margin is below -10dB, which is another important parameter to consider, particularly regarding compliance with regulation specifications. If the result is close to 0dB, some iteration is necessary to decrease the value; otherwise, the performance is suboptimal. This iteration must start by decreasing the value of the cutoff frequency.

This complete transfer function provides stability to the power supply and the best performance made possible by:

• Minimizing steady-state error
• Minimizing ESR parasitic effect
• Increasing bandwidth of power supply up to 6.5 kHz

Final design

After calculating all the passive component values for the feedback loop compensator and determining the converter’s main parameters, the entire flyback can be designed using the flyback regulator. Figure 4 shows the circuit’s final design using all calculated parameters.

Figure 4 Here is how the final design circuit schematic looks like. Source: Monolithic Power Systems

Figure 5 shows the bode plot of the complete loop gain frequency response.

Figure 5 Bode plot is shown for the complete loop gain frequency response. Source: Monolithic Power Systems

Obtaining the flyback averaged model via small-signal analysis is a complex process to most accurate approximation of the converter’s transfer functions. In addition, the cross-regulation technique involves secondary-side regulation through optocoupler feedback and an adjustable voltage reference, which complicates calculations.

However, by following the four steps explained in this article, a good approximation can be obtained to improve the power supply’s performance, as the output with the heaviest load is directly regulated. This means that the output can react quickly to load changes.

Joan Mampel is application engineer at Monolithic Power Systems (MPS).

Related Content

• Power Tips: Compensating Isolated Power Supplies
• Details on compensating voltage mode buck regulators
• Power Tips #139: How to simplify AC/DC flyback design with a self-biased converter
• Modeling and Loop Compensation Design of Switching Mode Power Supplies, Part 1
• Modeling and Loop Compensation Design of Switching Mode Power Supplies, Part 2

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The XDP711-001 48-V digital hot-swap controller from Infineon offers programmable SOA current control for high-power AI servers. It provides I/O voltage monitoring with an accuracy of ≤0.4% and system input current monitoring with an accuracy of ≤0.75% across the full ADC range, enhancing fault detection and reporting.

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The XDP711-001 will be available for order in mid-2025. For more information on the XPD series of protection and monitoring ICs, click here.

Infineon Technologies 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Qualcomm unveiled the Snapdragon G series, a lineup of three chips for advanced handheld, dedicated gaming devices. The G3 Gen 3, G2 Gen 2, and G1 Gen 2 SoCs support various play styles and form factors, enabling gamers to play cloud, console, Android, or PC games.

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Starting this quarter, OEMs like AYANEO, ONEXSUGAR, and Retroid Pocket will release devices powered by the Snapdragon G series. For more details on all three platforms, click here.

Qualcomm Technologies

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