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Sensors—on the front lines of the technological revolution in factory automation—are embedding microprocessors, memory, and communication protocols within the ASIC to offer multiple functions in a single chip, facilitating a new generation of smart factory applications spanning from asset monitoring to industrial robots to manufacturing quality control.

Here is a sneak peek at three sensor designs that enable factory automation applications while ensuring productivity and safety in industrial environments. These sensor designs also incorporate a variety of interfaces to support a wide range of smart factory capabilities.

1. Depth sensor for automation and robotics

This real-time, indirect time-of-flight (iToF) sensor delivers high precision for long-distance measurements and 3D imaging of fast-moving objects. The Hyperlux ID family of depth sensors from onsemi can capture an entire scene and simultaneously process depth measurements in real time.

The sensor combines global shutter architecture with iToF technology to deliver precise, rapid depth sensing. The iToF technology enables it to measure depth by detecting the phase shift of the reflected light from one or multiple vertical-cavity surface-emitting lasers (VCSELs). And the global shutter technology aligns all sensor pixels with the VCSEL, significantly reducing ambient infrared noise from other lighting sources.

Figure 1 The iToF device further extends depth sensing under dynamic scene conditions while capturing fast-moving objects. Source: onsemi

The company claims that the device’s depth-sensing capability of up to 30 meters is 4 times that of standard iToF sensors. Moreover, the sensor can produce both monochrome (black-and-white) images and depth information simultaneously.

That’s vital in factory automation, where the ability to obtain highly accurate depth information quickly and efficiently is becoming critical to improve productivity and safety. So far, iToF sensors have been limited in their use due to minimal range, poor performance in harsh light, and inability to calculate depth on moving objects.

By providing precision measurements of moving objects and high-resolution images, the Hyperlux ID sensors can help reduce errors and downtime and optimize mission-critical processes in a smart factory. In factory automation and robotics, it facilitates object detection to improve navigation and collision avoidance, enhancing safety on factory floors.

Next, in manufacturing and quality control, this depth sensor can measure the volume and shape of objects, detect defects, and ensure that products meet quality standards. In logistics and material handling, the sensor can measure the positions, sizes, and content ratios of pallets and cargo to optimize storage and transportation processes.

2. The AI-enabled IMU

An inertial measurement unit (IMU) with two MEMS accelerometers and a gyroscope tunes this sensing device for activity tracking and high-g impact measurement in smart factory applications such as asset monitoring and event data recorders. The IMU also embeds AI processing—a machine learning core—to perform inference directly in the sensor, continuously registering movements and impacts.

STMicroelectronics’ LSM6DSV320X sensor module, available in a single package, comprises three MEMS sensors. One accelerometer, featuring a maximum range of ±16g, is optimized for robust resolution in activity tracking. The second accelerometer, measuring up to ±320g, quantifies severe shocks such as collisions or high-impact events. Then there is a gyroscope with a ±4000dps range.

Figure 2 The sensor module for industrial safety comprises two accelerometers and one gyroscope. Source: STMicroelectronics

The 3-mm x 2.5-mm sensor module enables smart factory applications—such as personal protection devices for workers in hazardous environments—to fully reconstruct events with high accuracy and assess the severity of factory-floor incidents. The inertial module with dual-sensing capability could also be used to accurately assess the health of factory equipment.

3. Sensor signal conditioner

This signal conditioning IC ensures high accuracy, sensitivity, and flexibility for sensor applications in industrial pressure transmitters, HVAC systems, weight scales, factory automation devices, and smart meters. The ZSSC3240 sensor IC’s flexible configuration makes it highly suitable for smart sensor-based devices for smart factory environments.

Figure 3 The signal conditioner provides higher flexibility for sensor adaptation in smart factory applications. Source: Renesas

Generally, micro-machined and silicon-based sensing elements produce mostly nonlinear, very small signals. And that calls for special technologies to convert the sensor signal into a linearized output.

Renesas’ ZSSC3240 signal conditioning IC facilitates both the design and production of sensor interfaces by providing programmable, highly accurate, wide-gain, and quantization functions, combined with powerful, high-order digital correction and linearization algorithms. So, with a flexible sensor front-end and a broad range of output interfaces, it allows design engineers to develop complete sensing platforms from a single signal conditioning chip.

Special Section: Smart Factory

• Rethinking machine vision in industrial automation
• Smart factory: The rise of PoE in industrial environments
• Precision lasers boost safety and efficiency in smart factories

The post Tale of 3 sensors operating in smart factory environments appeared first on EDN.

Power-supply inductors may be supplanted by piezoelectric energy-storage elements…maybe. And someday.

Today’s step-down DC/DC converters – often converting 48 V down to single-digit voltages — are highly refined topologies, offering efficiencies of 90 percent and higher. Designers can choose among many switched-mode power supply (SMPS) arrangements, each with various subtleties to maximize a desired attribute such as efficiency, transient response, line and load regulation, or output noise. One bill of materials (BOM) aspect that all of these designs share is consistent reliance on magnetics in the form of inductors, to store and release energy as needed during the various operating phases.

But it doesn’t have to be magnetics. A team at University of California at San Diego has developed what they call an “Always-Multi-Path Embedded Flying Capacitor Piezoelectric Resonator-based DC/DC Converter” (that’s a mouthful!) that adds hybrid, multi-path, output-power delivery features to reduce the internal charge-redistribution losses within a piezoelectric resonator.

Their integrated circuit modifies the optimal voltage conversion of the piezo network from 2:1 to 3:1, while adding a switched-capacitor output network and piezoelectric resonators (PRs) to enable continuous multi-path operation. The result is net optimal voltage conversion ratio of 9:1 for the converter. The chip, which is fabricated in a 180-nanometer high-voltage CMOS process, achieves a peak efficiency of 96.2% at a 48-to-4.8 V conversion ratio.

The “flying capacitor” concept itself is not a new development at all; they have been around since the “early days” of electronics. In a classic arrangement, a non-grounded, floating capacitor is first connected to an input source and charged, then it is disconnected for that input and switched to an output to discharge (Figure 1).

Figure 1 The flying capacitor scheme was originally used with electromechanical relays to isolate a signal or power source from the subsequent stage. (Image source: InsightCentral.net)

Also called a switched-capacitor arrangement, it was used for many years to galvanically isolate sensors with electromechanical relays for switching, while modern switching supplies use MOSFETs and other solid-state devices. The switching scheme has also been used in multistage step-up circuits which can deliver thousands of volts from a single-volt source (Reference 3).

What’s wrong with inductors, and why consider using piezoelectric resonators? Inductors are versatile and reliable, but converters using piezoelectric resonators — tiny devices that store and transfer energy using mechanical vibrations — could potentially be smaller, more energy dense, more efficient and easier to manufacture at scale (Figure 2). The UC-SD team claims that inductors have reached a limit in improvement with respect to size and storage density (I suspect inductor vendors would disagree with that assessment).

Figure 2 A piezoelectric resonator (white disk) used by the new chip to perform DC-DC step-down conversion. For comparison, an inductor that is typically used in traditional step-down converters is shown on the left. (Image source: University of California)

Unlike inductors, which store energy in magnetic fields, PRs store and transfer energy through mechanical deformation and piezoelectric effects. They offer several advantages over traditional magnetic devices, including reduced volume due to their thin planar form factors, superior volume-frequency scalability, the ability to be easily batch fabricated, and their potential for direct integration onto silicon chips in future work. The high coupling and quality factor (Q) of PRs makes them attractive when designing high-efficiency, high-performance power systems, especially in the context of next-generation power conversion technologies.

Not surprisingly, an off-the-shelf PR is not suitable for this application. Commercially available units are not optimized for power applications and cannot operate robustly at the high current demands of modern datacenters. Further, the maximum current-carrying capability of a PR is determined by its physical properties such as material, vibration mode, and geometrical design, as well as electrical excitation strategies. For these and other reasons, the team designed a custom PR unit (Figure 3).

Figure 3 The custom piezoelectric resonator (right) overcomes limitations of commercial ones; the resonator size (left) is shown compared to a penny. (Image source: University of California)

Final performance is characterized by many different parameters under different operating conditions, such as those in Figure 4:

Figure 4 Fabrication and measurement images in abundance augment your knowledge base: a) Silicon die photo of the proposed converter; b) Measured waveform of each side of the PR, its differential voltage (VCP), and output voltage under voltage conversion ratio (VCR) = 10 and VCR = 20; c) Efficiency curve versus load current with fixed VCR (=10); d) Efficiency curve versus VCR with fixed load current (=200mA); e) Output current versus operation frequency, where the frequency operates in the inductive region of the PR. (Image source: University of California)

The team does acknowledge some limitations. Because piezoelectric resonators physically vibrate, they cannot be soldered onto circuit boards using conventional approaches and will require different strategies to integrate them into electronic systems. Although the technology is still in its early stages, the researchers say it represents an important step toward overcoming the limitations of today’s power converters. Future work will focus on improving materials, circuit design and packaging

As project senior author Patrick Mercier, professor in the Department of Electrical and Computer Engineering at the UC San Diego Jacobs School of Engineering noted, “Piezoelectric-based converters aren’t quite ready to replace existing power converter technologies yet. But they offer a trajectory for improvement. We need to continue to improve on multiple areas — materials, circuits and packaging — to make this technology ready for data center applications.”

Will this new approach get some traction? I don’t know, nor does anyone. After all, when optimized magnetic-based converters already have efficiency in the 90-95% range along with other favorable attributes, the pain needed to get another point or fraction of a point of improvement may not be worth the gain. On the proverbial other hand, a reduction in size or cost, even at the same efficiency, may be worthwhile.

Their paper “A hybrid piezoelectric resonator-based DC-DC converter” was published in Nature Communications but is behind a paywall; however, the team has posted a preprint here.

References

1. Knowles, “What Are Flying Capacitors?”
2. Insight Central, “Flying Capacitor High Voltage Battery Monitor”
3. EE World Online,  “Generating really high voltages without a tesla coil”

Related Content

• Converter transformation shows how far we’ve come
• Piezo audio devices go micro, provide output in a big way
• Piezo-Based Energy Harvesting May Repel Tooth Decay

 

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Part 1 of this mini-series about PCIe 7.0 fundamentals explained ordering rules and the distinction between relaxed ordering and ID-based ordering. Part 2 elaborates why PCIe 7.0 bandwidth alone isn’t enough and how UIO addresses legacy ordering limitations in this version of high-speed serial interface specification.

As noted earlier, PCIe 7.0 doubles raw link bandwidth compared to PCIe 6.0, increasing full‑duplex throughput from 256 GB/s to 512 GB/s on an x16 link by raising the signaling rate to 128 GT/s in flit mode. However, raw bandwidth does not directly translate into sustained throughput in AI factories.

Large‑scale training and inference systems generate traffic patterns such as GPU collective operations, sharded parameter broadcasts, gradient reductions, and streaming access to disaggregated accelerator and memory resources. These patterns include many independent data streams that cross the PCIe fabric concurrently and continuously.

The legacy ordering model inherited from earlier PCIe generations, including strict ordering, relaxed ordering, and ID‑based ordering, was designed around a producer-consumer abstraction in which ordering conveys semantic meaning to software. Relaxed ordering and ID-based ordering loosen this model selectively.

Relaxed ordering allows certain transactions to bypass global ordering constraints, while still participating in fabric‑enforced ordering rules. ID-based ordering further scopes ordering guarantees to a requester or execution context, preserving program order within that scope. In both cases, the PCIe fabric requires tracking and enforcement of ordering relationships to ensure correctness.

However, fabric‑enforced ordering introduces head‑of‑the-line blocking, increases buffering pressure, and restricts the ability of switches and endpoints to exploit parallel paths. This is particularly the case for multi‑path and non‑tree topologies common in modern AI systems. These effects reduce effective link utilization even though physical bandwidth is available, making it difficult for highly parallel AI workloads to keep PCIe 7.0 links continuously busy.

Addressing legacy ordering limitations with UIO

The unordered I/O (UIO) engineering change notice (ECN) was introduced in the PCIe 6.1 specification and included in PCIe 7.0 to address the specific limitation noted above. UIO introduces a wire-level semantic that shifts producer-consumer ordering responsibility from the fabric to the endpoints. The UIO ECN declares that ordering may be irrelevant for certain traffic classes.

For AI factory workloads, where operations such as reductions, parameter streaming, and telemetry are independent or statistically aggregated and never consumed in program order, enforcing any form of ordering (even per‑ID ordering) adds overhead. UIO removes fabric‑enforced ordering, enabling true multi‑path parallelism and reducing buffering requirements.

This allows PCIe fabrics to sustain higher utilization for concurrent AI traffic. Since UIO enables independent transactions from different request originators to bypass one another safely, AI systems can optimize PCIe 7.0’s increased bandwidth to support rapidly growing model sizes and highly parallel GPU workloads.

UIO is especially effective at reducing read latency because multiple UIO read completions for a single UIO read request may be returned in any address order. This same flexibility applies to UIO write completions, with the additional capability that write completions for the same transaction ID may be coalesced. Since every UIO request has a corresponding completion, the request originator maintains the ordering of its own transactions. This allows the PCIe fabric to forward traffic along multiple paths without violating semantic correctness.

With its low latency, UIO transforms PCIe fabrics into high-throughput, highly parallel forwarding planes capable of accommodating modern AI workloads. Instead of relying on the fabric to manage per-flow sequencing, UIO shifts ordering control back to the source device that initiates the requests.

How UIO reduces latency and unlocks concurrency in AI applications

UIO’s command set and wire semantics reduce latency and boost performance for AI training and inference in several ways.

First, UIO mandates completions for all UIO requests. This gives GPU endpoints precise end-to-end flow control and prevents posted-write “fire and forget” bursts from clogging switch queues. It also cuts head-of-the-line blocking and shortens tail latency, speeding up requests by allowing different types of requests to bypass each other without applying any ordering rules within the PCIe fabric.

One of the classic head-of-the-line blocking examples in the baseline strict ordering rule is that current read requests are not permitted to bypass previous write requests. UIO eliminates this rule, allowing read and write requests to be processed in parallel and completed in any order, as shown in Figure 1.

Figure 1 UIO read and write requests are processed in parallel at the application layer. Source: Cadence Design Systems

In addition, UIO read requests reduce latency and buffering by allowing a completer to return read completions out of order. This enables data to be delivered as it becomes available, rather than delaying responses to preserve requests or address ordering. This improves overall efficiency by giving the device greater freedom to exploit internal data availability and minimizing completion queueing and reassembly overhead.

For example, Figure 2 and Figure 3 show the completion patterns for a single 512 MB MRD request for non-UIO (in-order) and UIO (out-of-order) cases, respectively.

Figure 2 Non-UIO completion responses must be in order for the same MRD request. Source: Cadence Design Systems

For non-UIO, Figure 2 illustrates that completions must arrive in order, starting at byte 0 and ending at byte 511. However, with UIO, the completion order can be random, as shown in Figure 3. The first two completions carry the last two chunks of MRD requests (256-383B and 384-511B) because they are already available in the local cache. After that, the application reads the remaining completion data from its local memory and sends the remaining two completions (0B-127B and 128B-255B).

Figure 3 UIO read and out-of-order completion responses are processed for the same request. Source: Cadence Design Systems

Second, because ordering is enforced at the source rather than at every intermediate hop, packets from unrelated GPU streams can be load-balanced across multiple parallel paths through the PCIe fabric without being serialized by switch-level producer-consumer rules. This increases effective throughput at a given link rate and stabilizes latency underload. In multi-path topologies, system architects often use a non-transparent bridge (NTB) to connect separate systems, enabling cross-system traffic within a larger fabric.

Third, UIO is available only in flit mode. Operating in fixed-size flits with UIO-specific VC3VC4 (via the streamlined virtual channel capability) isolates UIO traffic from legacy flows, minimizes delays, and improves switch buffer utilization.

Figure 4 The above diagram displays a multi-path application example. Source: Cadence Design Systems

Figure 4 shows two interconnected PCIe systems (System 0 and System 1), each with GPUs and local PCIe switches connected via multiple NTB links. The upper NTB link can operate with either UIO-enabled or non-UIO-enabled traffic, while the three diagonal and lower links operate with UIO-enabled NTB.

As a result, independent transactions can flow concurrently across switches SW0–SW3. This topology shows how UIO-based NTB paths improve GPU communication by enabling multipath routing, reducing latency, and increasing bandwidth in large-scale AI systems.

PCIe ordering: A traffic light analogy

A helpful way to think about PCIe ordering is traffic control in a city. Strict ordering is like running the entire city with a single traffic light, and every vehicle must wait its turn and proceed in sequence. While there is no ambiguity, congestion can quickly build up. Relaxed ordering allows certain vehicles to pass through intersections in specific emergency situations, provided it is safe to do so.

While this removes unnecessary traffic jams, it still assumes the traffic system is centrally managed. ID-based ordering further refines this model by assigning each neighborhood its own traffic lights. While cars within the same neighborhood must obey local ordering rules, traffic from different neighborhoods can flow independently. This improves parallelism without sacrificing local correctness.

UIO bypasses traffic light rules entirely. It is akin to routing traffic onto a freeway, where there are no intersections or signals at all, and vehicles move continuously as capacity allows. On a freeway, the infrastructure does not impose sequencing. Instead, the responsibility for safe merging and interpreting arrival order shifts to drivers.

Similarly, with UIO, the PCIe fabric no longer enforces producer‑consumer ordering or completion sequencing. The requester explicitly declares that ordering carries no semantic meaning, allowing the fabric and devices to deliver and complete transactions opportunistically. This maximizes parallelism while minimizing buffering and latency.

These four ordering schemes are a progression rather than a set of alternatives. Strict ordering prioritizes safety and simplicity, while relaxed ordering removes unnecessary global barriers. ID-based ordering preserves correctness within a context while enabling scale, and UIO explicitly abandons ordering when it has no value. This layered model allows PCIe to remain compatible with legacy software while scaling efficiently for modern accelerators, multi‑queue devices, and highly parallel workloads.

Turning PCIe bandwidth into system-level performance

Fully utilizing PCIe 7.0’s 128 GT/s link in today’s AI factories requires more than higher signaling rates. In an environment where thousands of GPUs, accelerators, and memory expanders operate as a single, distributed system, an ordering model that can scale with extreme parallelism is necessary.

Legacy relaxed ordering and ID-based ordering schemes retain implicit ordering constraints that limit their efficiency at PCIe 7.0 speeds, making them increasingly inadequate for AI factories operating at hyperscale.

UIO relaxes fabric‑enforced ordering and enables AI workloads to more effectively utilize multi‑path PCIe fabrics. By shifting ordering decisions to endpoints that already manage synchronization at the runtime and application levels, UIO reduces ordering-related head-of-the-line blocking issues.

Not only does this improve latency under bursty collective traffic, it also supports higher sustained link utilization across dense training and inference clusters. The result: Under AI workloads, PCIe 7.0 can be used more efficiently as a data plane, rather than simply serving as a peak‑bandwidth interconnect.

Vanessa Do is a senior product marketing manager for PCIe IP at Cadence with over 20 years of experience in PCIe design, system validation, and customer engagement. Her background spans PCIe protocol development, FPGA-based customer support, and leading cross‑functional teams to debug complex PCIe issues at the system level.

Editor’s Note

This is Part 2 of the article series about PCIe 7.0 fundamentals. Part 1 explained PCIe’s ordering rules and the distinction between relaxed ordering and ID-based ordering.

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Portable power units have both instantaneous-output and run-time limits, of course, but this situation seems a bit ridiculous. Or, then again, maybe not. But how to tell?

Last December, a few hours after the “kickoff” of our high wind-induced multi-day power outage “adventure”, I had the bright (if I do say so myself) idea to try hooking up our portable power stations (plus extended batteries in two of the three cases):

to the refrigerator-plus-freezer combo in the kitchen, along with both its combo fridge-plus-freezer companion and a standalone chest freezer out in the garage. The weather outside, therefore also the temperature in the garage, was chilly, so I wasn’t terribly worried about anything spoiling in either of those latter two units. Then again, I didn’t know how long the outage would last, and I had three supplemental power solutions at my disposal, so…

A preparatory test-drive admittedly would have been wise

I started (and ended; keep reading) with the cooling combo in the kitchen, my highest priority for perhaps-obvious comparative ambient temperature reasons. It’s a Samsung model RF217ACBP/XAA; here are a couple of stock photos to start:

I dragged from the downstairs furnace room the EcoFlow DELTA 2-plus-Smart Extra Battery “stack”, enabled the former’s AC inverter outputs, and plugged the combo fridge-plus-freezer in. I heard the compressor start up (accompanied by a DELTA 2 front panel display-reported AC output spike)…try to start up is a more accurate description, because after a second or so, the setup seemingly overloaded and gave up trying. Next up, the DELTA 3 Plus and its Smart Extra Battery sibling. Same underwhelming outcome.

The wind was blowing, the outside light was dimming, and my spouse was understandably getting stressed, so I didn’t waste any more time messing around; I promptly bailed on the idea and focused my attention elsewhere. Since I’d already expended the effort to get both “stacks” upstairs, they ended up alternatively finding use in powering table lamps, recharging various battery-powered devices—lanterns, laptops, tablets, smartphones—and the like.

No, I didn’t bother trying to haul upstairs my even heavier SLA battery-based Phase2 Energy unit. And fortunately, save for the spoil-prone contents of our kitchen refrigerator (but not its combo freezer), we didn’t need to toss any food. Still, I was both disappointed and (more than a) bit surprised, because I’d seen success reports from other folks who’d successfully powered food-storage equipment (albeit of unknown capacity and for unknown duration) using EcoFlow and other suppliers’ similar systems in similar circumstances as mine.

Published data also would have been helpful

Given my background experiences with other startup-surge hardware, I was pretty sure I knew how the failure had happened, but not specifically why. So, after the electricity started flowing again, I did some research. First off, I realized I hadn’t enabled either EcoFlow base unit’s X-Boost Mode feature, which might have gotten them over the compressor-start initial-surge “hump”. Please take a moment to “enjoy” the following promo video clips :

As I wrote last February, X-Boost “doubles the output AC power (at a reduced voltage tradeoff that not all powered devices are guaranteed to accept, albeit obviously counterbalanced by higher current)”. Could it have helped? Dunno; I’ll have to try it sometime when I get a chance.

But how much surge current, and at what minimum voltage, does the Samsung RF217ACBP/XAA demand on compressor startup? Ay, there’s the rub. You won’t find it in the user manual, or even the service manual, only steady-state power draw specs. The labels on the side:

and rear of the Samsung RF217ACBP/XAA:

weren’t directly helpful either, although they at least revealed the compressor model number (MK162D-L1U SJ1). But my online browsing using that specific search term was equally fruitless.

Cue the hand-waving

What do online resources say in general? Here’s Google AI Mode’s take on the topic:

A refrigerator typically experiences a startup surge current 3–4 times higher than its normal running amperage, lasting only a few seconds. While running at 1–4 amps, it can spike to 15–30 amps during compressor startup. This inrush current is essential to overcome inertia, usually requiring a dedicated 15–20 amp circuit.

I just checked and confirmed that my kitchen refrigerator breaker is 20A. Feel free to contrast that with the “3.9 Maximum Amperes” claim in the above sticker closeup shot. Sigh.

Ballpark figures are better than nothing, I suppose, albeit still (quite) non-ideal. Am I just overlooking something obvious, or being pedantic, or is the startup surge draw:

• useful information that
• Samsung (at least) isn’t publishing

therefore, compelling consumers to potentially overshoot, buying portable power systems beefier and more expensive than they may actually need (and, apparently, than I bad-pun-intended “currently” own)? Reader thoughts are as-always welcomed in the comments!

My father (the King of Duct Tape) would have been impressed

p.s…while researching this post’s topic online, I came across a mind-blowing (at least to me) somewhat-related Reddit thread that I couldn’t resist sharing: “Fridge kept tripping circuit breaker until I added an extension cord. Why?”. Here’s my stab at the TL;DR summary:

The OP (original poster) eventually determined, in conjunction with his repair tech, that the refrigerator’s defrost heater was failing. But in initially attempting to debug the issue, originally assuming that the outlet wiring might be failing, he used an extension cord (beefy, I hope) to plug the fridge into another outlet, which worked fine. Turns out, the extension cord was still largely coiled and sitting on top of the fridge; the resulting added circuit induction sufficiently opposed the high frequency noise injection coming from the failing defrost heater such that the arc fault circuit interrupting (ACFI) breaker stopped tripping…temporarily, at least.

The entire thread is well worth your perusal if you have sufficient spare time and interest!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Preemptive utilities shutdown oversight: Too much, too little, or just right?
• EcoFlow’s Delta 2: Abundant Stored Energy (and Charging Options) for You
• Portable power station battery capacity extension: Curious coordination
• EcoFlow’s DELTA 3 Plus and Smart Extra Battery: Product line impermanence curiosity
• An assortment of tech-hiccup tales

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ADI’s ADAA245x series of A2B 2.0 Automotive Audio Bus transceivers delivers 4× higher bus bandwidth (98.3 Mbps full-duplex) than A2B 1.0 devices. Now in production, the transceivers handle up to 119 upstream and downstream audio channels for advanced automotive audio systems, enabling high-definition audio transport across ECU networks.

The ADAA2457 supports Ethernet data tunneling via an Open Alliance SPI (OASPI) interface. All ADAA245x devices are compatible with existing A2B 1.0 cable and connector infrastructure and enable A2B 1.0 branching via device-specific I2S, I2C, and SPI interfaces. The ADAA2455 operates as a sub-node transceiver, while the ADAA2456 and ADAA2457 can be configured as main or sub-nodes.

According to ADI, the transceivers achieve up to 30% system cost reduction through increased functional integration and reduced external circuitry and component count. They also provide low, deterministic latency of 62 µs and are built for straightforward integration.

Learn more about A2B 2.0 and individual transceivers here.

Analog Devices

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Rohm’s ML7670/ML7671 wireless charging chipset provides NFC charging for compact wearables such as smart rings and fitness trackers. Operating in the 13.56-MHz band, NFC charging enables antenna miniaturization for ultra-compact devices. Following the 1-W ML7660/ML7661 chipset, the ML7670/ML7671 is optimized for even smaller wearable designs.

The chipset comprises the ML7670 receiver and ML7671 transmitter and supports wireless power transfer up to 250 mW. Peripheral components, including switching MOSFETs used to power the charging IC, are integrated. ROHM states that the 2.28×2.56×0.48-mm receiver IC reaches 45% power-transfer efficiency at 250 mW output, where it is optimized for compact wearable designs.

Rohm says the 45% power-transfer efficiency is enabled by tailored coil matching, rectifier circuitry, and reduced switching losses. Firmware for wireless power delivery is embedded in the IC, eliminating the need for a host MCU and reducing board space.

The NFC Forum WLC 2.0-compliant chipset is in mass production and is used in the Soxai Ring 2.

ML7670 product page 

ML7671 product page

Rohm Semiconductor

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Vishay has released 16 single and dual FRED Pt ultrafast rectifiers in low-profile DFN6546A packages with wettable flanks. The 200-V devices occupy a 6.5×4.6-mm footprint with a typical height of 0.88 mm. Rated from 6 A to 15 A, they offer a 10% lower profile and 50% higher current than comparable 200-V SMPC (TO-227A) devices.

The rectifiers are designed for high-frequency power conversion and protection in automotive, industrial, and consumer systems, including EV powertrains, ADAS, industrial automation, and telecom equipment. Automotive variants are AEC-Q101 qualified.

For these applications, the rectifiers feature low reverse leakage current and operate over a wide temperature range from −55 °C to +175 °C. A low forward voltage drop of 0.75 V, combined with fast reverse recovery time and low reverse recovery charge, reduces power losses and improves efficiency.

The DFN6546A package’s wettable flanks enable automatic optical inspection (AOI), eliminating the need for X-ray inspection and supporting automated assembly. The devices are MSL 1 qualified per J-STD-020, with a maximum peak reflow temperature of 260 °C.

Samples and production quantities of the single and dual FRED Pt ultrafast rectifiers are available now, with lead times of eight weeks.

Vishay Intertechnology 

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Microchip’s MD-990-0011-B M.2 plug-in timing module delivers precise synchronization for data center servers and 5G vRAN. Developed with Intel, it is compatible with Xeon 6 SoC–based server platforms. It leverages Intel’s vRAN architecture for low-latency time synchronization in distributed AI workloads and real-time applications.

Customized for Intel-based reference designs, the device supports automatic source selection and locking across GNSS, Synchronous Ethernet (SyncE), and PTP networks. Its integrated SyncE synthesizer includes two independent digital PLL channels: one for time and one for frequency. Additional components include an OCXO supporting 4 or 8 hours of 1.5-µs holdover, along with a temperature sensor, EEPROM, and a crystal oscillator to help maintain low jitter.

By integrating these components into a single plug-in module, the MD-990-0011-B simplifies server design and reduces complexity. Its modular approach also speeds installation and maintenance, helping minimize downtime.

The MD-990-0011-B is available in production quantities from Microchip and authorized distributors.

MD-990-0011-B product page 

Microchip Technology 

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The GD32F5HC series of 32-bit general-purpose MCUs from GigaDevice features a 200-MHz Arm Cortex-M33 core with DSP and FPU capabilities. Hardware-based security, ample on-chip memory, and integrated peripherals target both consumer and industrial designs.

On-chip memory includes 2 MB of flash, 320 KB of SRAM, and 32 KB of instruction cache. Multichannel DMA controllers handle complex algorithms, graphics frameworks, and high-speed data flows. QSPI and SPI interfaces enable external PSRAM and flash expansion at up to 45 MHz.

Peripherals include a 12-bit ADC with an integrated temperature sensor and an infrared interface for analog signal processing. Multiple 16-bit and 32-bit timers, along with a real-time clock, enable waveform generation, motor control, and synchronized multi-axis operation.

Security features combine Arm TrustZone with a 2-kbit eFuse for key storage and hardware cryptographic accelerators. Secure boot, storage, debugging, and firmware updates help maintain system integrity across the device lifecycle.

The MCUs operate from a 3.3-V supply and offer four power-saving modes: sleep, deep sleep, standby, and SRAM sleep. Devices are available in BGA64 and QFN56 packages with up to 54 GPIOs.

GD32F5HC product page

GigaDevice

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Combining an accurate temperature sensor with a standard digital multimeter can make an inexpensive, accurate, and useful thermometer.

A recent Design Idea, BJT is accurate sensor for absolute temperature in Kelvin and Rankine, was based on a 1991 application note (PDF) by a legendary guru, the forever remembered Jim Williams. In his article, Williams demonstrated that, when used as ΔVbe sensors, ordinary unselected transistors give temperature readings accurate to a fraction of a degree without calibration:

“…randomly selected 2N3904s and 2N2222s … showed less than 0.4°C spread over 25 devices from various manufacturers.”

Wow the engineering world with your unique design: Design Ideas Submission Guide

As shown in BJT is accurate…, the basic math of ΔVbe can be cooked down to a simple and easy to remember (hah!) linear-in-absolute-temperature relationship: ΔVbe/°C = Log10(Current-ratio)/5050.  Therefore, if we want any given ΔVbe/°C, the required is just Current-ratio = 10^(5050 ΔVbe/°C). 

For example, for ΔVbe/°C = 100uV, Current-ratio = 10^(5050 * 100uV) = 10^(0.5050) = 3.20.  This ratio is implemented in Figure 1’s simple circuit for a 100uV per Kelvin output.

Figure 1 An ordinary BJT Q1 makes an accurate 100uV per unit Kelvin absolute temperature sensor.

Okay. So. What’s it good for? One plausible application is, as frequent contributor Nick Cornford has shown in several ingenious designs:

• Newer, shinier DMM RTDs—part 1 and part 2
• Dropping a PRTD into a thermistor slot—impossible?
• DIY RTD for a DMM

that the combination of an accurate temperature sensor with a standard digital multimeter can make an inexpensive, accurate, and useful thermometer.

Nick’s favorite sensor is the super-versatile platinum RTD, but as Williams showed, a humble (and super cheap) 2N3904 (or similar) BJT might also fill the bill. That’s assuming that its package-limited −55 to +150°C temperature range is adequate. And that’s also assuming that it gets a little help from its friends, such as Figure 2’s zero-drift op amp that boosts the output span to a DMM-friendly 1mV per unit Celsius, Kelvin, Fahrenheit, and Rankine.

Figure 2 A zero drift, 5uV max offset A1 rescales 100uV/°K by 10x to 1mV/°C and by 18x to 1mV/°F.

Of course, Kelvin and Rankine absolute temperature measurements are absolutely less frequently useful than the common Celsius and Fahrenheit scales…which is where Figure 3 comes in:

Figure 3 Connect the DMM’s plus lead to the appropriate figure 2 output, and the minus lead to the correct precision 0° offset terminal, to re-zero 273K to 0°C and 460R to °0F.

V+ can be anywhere from 3 to 6 volts.  Current consumption at 3v is barely more than 1mA, dominated by the Z1 shunt reference, so two AAs will support 2000 hours (nearly three months) of continuous operation.  A single CR2032 lithium coin will hold up for 10 non-stop days.

Thanks, Nick and Jim!

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content 

• BJT is accurate sensor for absolute temperature in Kelvin and Rankine
• Newer, shinier DMM RTDs—part 1
• Newer, shinier DMM RTDs—part 2
• Dropping a PRTD into a thermistor slot—impossible?
• DIY RTD for a DMM

 

The post ΔVbe + DMM = Celsius, Kelvin, Fahrenheit, and Rankine thermometer appeared first on EDN.

Adding more compute is no longer enough to maximize AI training and inference performance in today’s AI factories. The real challenge is how efficiently data flows through AI systems, not raw processing power.

Training remains the foundation of AI development, and maximizing throughput across large clusters is critical as models internalize structure, learn statistical relationships, and establish a baseline for downstream workloads. Inference shifts the focus, demanding ultra-low latency and high-reliability token generation. Both of these phases are characterized by exponential scale.

Training trillion-parameter models and performing inference that requires enormous amounts of contextual information places significant pressure on the “plumbing” of modern computing platforms. In this environment, the efficiency, predictability, and speed of data movement across the CPUs, accelerators, memory, and I/Os that compose these AI systems have become the true bottleneck.

Eliminating data bottlenecks is now dependent on optimizing interconnect bandwidth. The interconnects themselves are crucial to system success, with PCI Express (PCIe), specifically PCIe 7.0, being a prime example.

PCIe’s role in multi-GPU scale-up systems

For more than a decade, PCIe has been the backbone of multi-GPU server systems due to its universal and extensible interconnect that ties all compute and I/O devices together inside a node, such as GPU-to-DPU/NIC, or GPU-to-switch. Even as newer, high-bandwidth GPU-to-GPU fabrics and proprietary accelerator meshes have emerged, systems continue to rely on PCIe for baseline connectivity, system bring-up, and data movement across system components.

Announced in June 2025, PCIe 7.0 doubles link bandwidth to 128 GT/s, delivering up to 512 GB/s of bi-directional throughput per x16 connection. While this increased bandwidth helps alleviate I/O bottlenecks for AI computing, fully utilizing PCIe 7.0 for inference workloads also requires minimizing latency across the fabric.

Multiple inference streams sharing the same PCIe path may cause head-of-the-line blocking due to unnecessary serialization. This results in delays in unrelated traffic, which impacts overall system efficiency.

To maintain low latency and fully utilize PCIe 7.0 bandwidth under parallel workloads, a more flexible ordering model is required.

Baseline PCIe ordering rules: Why serialization exists

First, it’s helpful to understand PCIe’s baseline ordering rules. Most systems using early PCIe generations—from 2.5 GT/s in PCIe 1.0 to 8 GT/s in PCIe 3.0—relied on simple point‑to‑point connections supporting a single application or device context. As a result, the PCIe protocol strictly enforced baseline ordering rules to ensure that the results of memory operations are presented in an order that matches software expectations.

Within a single traffic class, PCIe groups transaction-layer packets (TLPs) into posted, non-posted, and completion categories, each governed by defined ordering constraints. Posted requests are memory writes (MWR) and messages (MSG) that operate without needing a completion, while non‑posted requests include memory reads (MRD) and configuration transactions that must receive a completion. To simplify the discussion, the focus is on the main traffic. Only MRD requests, MWR requests, and read completions (CPL) are described in the ordering rules.

Table 1 Baseline ordering rules highlight the relationship between the current and previous requests. Source: Cadence Design Systems

Table 1 shows the relationship between the current requests in rows A, B, and C and the previous requests in columns 2, 3, and 4. The “Y/N” in the table is the abbreviation of “Yes/No” that implies the row’s request/completion “may pass” the column’s request/completion type.

To understand the A3 deadlock scenario detailed in Figure 1, assume the root complex (RC) issues an MRD request (1) followed by an MWR request (2) toward the endpoint (EP) device. A deadlock can occur when the RC exhausts the completion credits, and its completion buffer becomes full (3). The RC is unable to accept new completions (4) associated with the outstanding non-posted MRD (1).

Figure 1 In A3 deadlock, the RC completion queue (CQ) is full, preventing it from returning completion to release the MRD from blocking the MWR request. Cadence Design Systems

Because strict ordering prevents the newer MWR (2) from bypassing the unresolved MRD (1) until its completion (4) is received, the RC’s transmit request path is also blocked. This prevents the issuance of MWR (2) from propagating to the EP link (5). This head-of-the-line blocking creates circular dependency, which stalls internal request queue draining and completion acceptance. Unless the MWR is allowed to bypass the MRD, a deadlock results.

For the C3 deadlock scenario illustrated in Figure 2, assume both the RC and EP issue many non-posted read requests (1), which aggressively fill both the RX and TX request queues (RQ) (2) and prevent them from accepting any new MRD requests (3). Meanwhile, the completions (4) are returned for pending MRD requests (1) in the opposite direction, but they can’t be forwarded to fulfill the previous pending MRD request (1). This is because they arrived behind the new MRD request (3). If the completion is not allowed to bypass the previous MRD requests in the same direction, it will result in a deadlock.

Figure 2 A C3 deadlock occurs if both the RX and TX request queues are full, and the completion is not allowed to pass the previous MRD request. Source: Cadence Design Systems

For A2 (Row A, column 2), B2, and C2, MWR, MRD, and CPL requests cannot pass MWR requests to maintain correctness. These three scenarios are illustrated in Figure 3, Figure 4, and Figure 5, respectively.

Figure 3 In A2, current MWR requests cannot pass previous MWR requests. Source: Cadence Design Systems

Figure 4 In B2, current MRD requests cannot pass previous MWR requests. Source: Cadence Design Systems

Figure 5 In C2, current completion requests cannot pass previous MWR requests. Source: Cadence Design Systems

However, A3 and C3 illustrate that both MWR requests and completions can pass an earlier MRD request to avoid a deadlock. This is shown in Figure 6 and Figure 7.

Figure 6 In A3, MWR requests are allowed to bypass previous MRD requests to avoid a deadlock. Source: Cadence Design Systems

Figure 7 In C3, completions are allowed to bypass previous MRD requests to avoid a deadlock. Source: Cadence Design Systems

For B3, the current MRD request might be bypassed or blocked by the previous MRD request. For A4 and B4, the current MWR or MRD request is permitted to pass the previous completion or be blocked by the completion.

Figure 8 describes both the C4a and C4b scenarios. The yellow and green completions belong to the pending yellow (RD1) and green (RD0) MRD requests, respectively. If current completions belong to different MRD requests, they can pass each other as CPL10 passes CPL01 (C4a scenario). However, if they belong to the same MRD request as in the C4b scenario, they must follow the order and cannot pass previous completions (CPL00 followed by CPL01, and CPL10 followed by CPL11).

Figure 8 In C4, completions of the same MRD request can pass completions of the previous MRD, and completions of the same MRD request must follow in order. Source: Cadence Design Systems

Strict ordering: A safe but conservative baseline

PCIe’s default strict ordering rules ensure safe producer-consumer software behavior. Under strict ordering, the system observes transactions issued by a requester in program order. Posted writes must be completed before subsequent read completions of subsequent pending MRD requests.

However, this global ordering discipline is conservative. It causes unrelated transactions to wait for one another, even when there is no true data dependency. For instance, this can occur when different functions access data from different memory segments in the host or local memory. As PCIe link speeds increase, this approach becomes a scalability bottleneck because it causes head-of-the-line blocking of unrelated serialized traffic and underutilizes the available bandwidth.

Why relaxed ordering is needed

Relaxed ordering loosens these global constraints. When a transaction is marked as relaxed, it tells the PCIe fabric that this MRD or MWR request does not need to participate in the default system‑wide ordering guarantees. Relaxed ordering improves throughput and reduces latency by enabling certain transactions to be reordered. The key point is that relaxed ordering removes unnecessary ordering barriers between independent operations.

However, it still preserves most of the transactional correctness, such as ensuring the completion order of the same MRD requests. This is especially valuable for workloads such as prefetching, polling reads, or accelerator traffic, where software already explicitly manages synchronization. Relaxed ordering addresses the performance loss caused by overly strict global rules. However, it treats ordering as a binary choice, either fully ordered or globally relaxed.

Why ID‑based ordering is also necessary

Relaxed ordering alone is too coarse‑grained for modern devices. High‑performance endpoints, such as GPUs, NICs, and NVMe controllers, generate traffic from many independent sources, including queues, processes, virtual machines, or process address space IDs (PASIDs).

These sources often require ordering within themselves, but not between each other. With ID‑based ordering, PCIe maintains ordering among transactions that share the same requester ID or PASID, while permitting reordering across different IDs. In effect, it scopes ordering guarantees to a logical context rather than imposing them system‑wide.

This allows transactions of the same function or context to maintain the correct program semantics, while the fabric freely parallelizes traffic across independent functions or contexts. Without ID-based ordering, systems would be forced to choose between full serialization for safety or full relaxation with no per‑context guarantees.

Attribute-based ordering: Relaxed and ID-based ordering

Because the PCIe fabric already enforces ordering semantics for both relaxed ordering and ID‑based ordering, system software and device logic influence these behaviors by setting attributes in the TLP headers rather than redefining the rules themselves. Relaxed ordering and ID‑based ordering address different dimensions of the same problem, which is why both are required to meaningfully relax PCIe’s strict ordering rules.

Relaxed ordering removes unnecessary global ordering constraints between different classes of traffic, enabling better scheduling and reducing head-of-the-line blocking. In contrast, ID‑based ordering refines ordering to the level of a requester or context, preserving correctness where the associated software expects it while eliminating artificial dependencies elsewhere.

Together, they allow PCIe to scale with modern parallel workloads. While strict ordering provides a safe default, relaxed ordering removes global bottlenecks, and ID‑based ordering preserves local semantics without sacrificing concurrency. This combination allows PCIe to support today’s accelerators, virtualized I/Os, and high‑throughput devices without breaking the programming models that software relies on.

Table 2 Here is a highlight of the ordering rules for relaxed ordering and ID-based ordering. Source: Cadence Design Systems

Table 2 specifies the ordering rules for relaxed ordering and ID-based ordering. The “Y/N” in the table is the abbreviation for “yes/no”, indicating whether the row’s request/completion “may pass” the column’s request/completion type.

The key differences between the relaxed ordering and ID-based ordering rules detailed in Table 2 and the baseline rules shown earlier in Table 1 are A2, B2, and C2 vs. D2, E2, and F2, respectively. For baseline rules, current MWR, MRD, or completions are not allowed to pass previous MWR requests. However, relaxed ordering and ID-based ordering allow them to pass previous MWR requests if their request IDs—bus, device, function, and PASID—are different.

Vanessa Do is a senior product marketing manager for PCIe IP at Cadence with over 20 years of experience in PCIe design, system validation, and customer engagement. Her background spans PCIe protocol development, FPGA-based customer support, and leading cross‑functional teams to debug complex PCIe issues at the system level.

Editor’s Note

This is Part 1 of the article series about PCIe 7.0 fundamentals. Part 2 will explain why PCIe 7.0 bandwidth alone isn’t enough while highlighting the importance of addressing legacy ordering limitations with UIO.

The post PCIe 7.0 fundamentals: Baseline ordering rules appeared first on EDN.

Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

The post The system architect’s sketchbook: The tree knows appeared first on EDN.

The drive toward greater accuracy, efficiency, and automation in manufacturing environments and smart factories is accelerating at an unprecedented pace. This includes the deployment of advanced robotic systems, including autonomous mobile robots (AMRs) and collaborative robots working alongside humans, known as cobots.

The future of manufacturing depends on safe and seamless human-robot collaboration, requiring robots to dynamically adapt to the presence and movements of human workers. Maximizing the potential of these collaborative environments demands a critical capability: fast, accurate, and reliable 3D spatial sensing.

Traditional sensing methods often fall short in dynamic industrial settings that require reliable performance and high resolution. So, precision laser technologies, particularly time-of-flight (ToF) and frequency modulated continuous wave (FMCW) lidar, are emerging as key technologies, providing the detailed environmental sensing technology necessary for robots to navigate safely around personnel and to optimize workflows without compromising human safety.

Advanced lidar systems enable highly precise obstacle detection, distance measurement and real-time mapping, facilitating safer interaction between humans and robots. Design engineers are integrating the technology into automated factory systems to address the challenges of modern manufacturing while boosting accuracy, operational safety, and overall production efficiency.

How ToF lidar uses light to measure distance in smart factories

ToF lidar delivers highly accurate distance measurements by timing the round-trip travel of laser pulses, creating precise 3D point clouds of all objects in the surrounding environment—giving AMRs and cobots a detailed, real-time picture of their workspace. A ToF lidar system emits a pulse of invisible laser light onto an object and receives the reflected pulse back.

The system then calculates the distance between the transmitter/receiver and the object based on how long that round trip takes. Figure 1 shows a high-level diagram of a single-point optical ToF lidar system.

Figure 1 Distance measurement is shown between the object and the ToF lidar. Source: Texas Instruments

Cameras and ultrasonic sensors fall short in dynamic applications

Camera-based systems and ultrasonic sensing cannot match the speed and precision that ToF lidar delivers for distance measurement. While cameras excel at extracting texture and color information from their environment, they struggle with depth perception, especially in challenging lighting conditions.

Cameras often require illumination of the entire area of interest to function accurately, while ToF lidar systems, such as the module on top of the robot in Figure 2, supply their own illumination in the form of laser pulses. Most ToF lidar systems use laser light with a 905-nm wavelength invisible to humans and can sense objects over 100 m away while remaining eye-safe. Some scanning ToF lidar systems can provide 360-degree distance measurements, making them particularly useful in AMR applications where spatial awareness in all directions matters.

Figure 2 AMR is equipped with a ToF lidar module on top to supply illumination in the form of laser pulses. Source: Texas Instruments

Obtaining accurate 3D distance information from cameras requires complex and computationally expensive image processing algorithms that can introduce latency and potential inaccuracies. Camera-based systems also require good lighting conditions to operate properly.

Due to light dispersion, most camera-based systems deliver accurate distance measurements only for objects a few meters away and lose accuracy at greater distances unless design engineers use large, costly lenses.

Ultrasonic sensors offer a low-cost solution for proximity detection, but suffer from limited range, poor accuracy, and susceptibility to interference from noise and surface characteristics. Accuracy for distance measurement typically falls within a range of several centimeters, and environmental factors such as temperature, humidity, and the object surface texture heavily influence results. Additionally, a wide field of view makes it difficult to pinpoint the exact location of an obstacle, increasing the risk of false positives.

FMCW lidar adds velocity measurement for safer human-robot collaboration

FMCW lidar is quickly emerging as a superior sensing solution for smart factories, particularly in collaborative robotic applications.

Unlike ToF, which measures distance based on the time it takes a laser pulse to return, FMCW lidar transmits a continuous wave laser that varies in frequency. By analyzing the frequency difference between the transmitted and received signals, the system applies the Doppler principle to directly measure both distance and velocity with extremely high precision.

This velocity measurement provides critical advantage in environments where robots work alongside humans and other robots, enabling a proactive response to movement and significantly reducing collision and injury risks. FMCW lidar also achieves longer distance measurement range at the same laser power as ToF-based systems. Figure 3 shows a high-level diagram of an FMCW lidar system.

Figure 3 The high-level diagram shows how an FMCW lidar system works. Source: Texas Instruments

In high-throughput manufacturing environments utilizing conveyor belts, FMCW lidar offers significant advantages over traditional camera-based vision systems for object detection and tracking.

Camera-based systems rely on image processing and pattern recognition, which can be computationally intensive and sensitive to object orientation. Conversely, FMCW lidar directly measures distance and velocity regardless of these factors, enabling quicker and more reliable detection even with fast-moving objects.

FMCW lidar’s ability to create a dense 3D point cloud allows engineers to determine accurate size and shape without complex image analysis, significantly increasing overall manufacturing line throughput and system accuracy.

Driving what’s next in smart factory automation

The increasing demand for automation, efficiency, and safety in modern manufacturing is driving the rapid adoption of advanced sensing technologies such as ToF and FMCW lidar. Both technologies offer substantial advantages over camera-based vision systems and ultrasonic sensors in dynamic environments where human-robot collaboration takes priority.

ToF lidar provides accurate 3D spatial data for reliable obstacle detection and precise distance measurements. FMCW lidar further elevates performance through the direct measurement of both distance and velocity, crucial for proactive collision avoidance and enhanced safety.

Companies such as Texas Instruments provide essential semiconductor building blocks such as transimpedance amplifiers, laser drivers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and a comprehensive range of power products that are vital for designing and building high-performance ToF and FMCW lidar systems.

Ongoing innovation in laser technology and signal processing promises continued advancements in lidar capabilities, positioning it as a cornerstone technology in the evolution of smart factories and industrial automation.

Anthony Vaughan is marketing manager for high-speed amplifiers at Texas Instruments.

 

 

Special Section: Smart Factory

• Rethinking machine vision in industrial automation
• Smart factory: The rise of PoE in industrial environments

The post Precision lasers boost safety and efficiency in smart factories appeared first on EDN.

Leveraging a prior fixture design with different lab equipment once again enables highly reliable results.

High resolution bench digital multimeters (DMMs) are commonplace now in most work labs, even trickling down to home labs and one-person shops! These DMMs are great for all sorts of measurements, including those of low Z components when utilizing the popular 4-wire Kelvin-type probes and clips.

Wow the engineering world with your unique design: Design Ideas Submission Guide

However, attempting to measure low Z SMD components can be challenging even with the best probes and clips, thereby explaining why I developed a specialized custom fixture for bench-type LCR meters. This fixture has subsequently proven quite valuable when measuring various SMD inductors, capacitors and resistors. The thought of using a similar concept for high-resolution DMMs with four banana type inputs therefore naturally occurred to me. Specifically, since I’d already created custom PCBs with lever arm-toggling capabilities for holding SMDs in place, why not utilize the same PCB and lever arm concepts for DMM use?

DMMs require banana plugs as inputs; high-resolution DMM models have four total. As with the custom LCR meter fixture, my not wanting to have any potentially tangling cables would instead require a somewhat direct four-wire connection to the DMM utilizing banana plugs. Various bare banana plug options are available, such as the ones used in the Tektronix 577 adapter, along with commonplace ones found in audio applications. Since the audio types were handy, they’re what I used.

Mechanical support for the four banana plugs and the custom PCB was provided by a custom developed 3D-printed enclosure (Figures 1-3). The connections between the PCB and banana plugs were originally made by spade lugs (shown), but this approach proved difficult when tightening down the banana plugs. Instead, I later utilized direct-soldered wire connections.

Figure 1 Adapting a tried-and-true PCB design to a different kind of test and measurement equipment proved straightforward.

Figure 2 The design approach leverages commonplace audio banana plug.

Figure 3 The resultant fixture is compact and rugged.

Operation with low Z SMD components such as 2512 precision metal film resistors is possible with very good repeatability and stability, even on older DMMs such as the HP/AG34401A (Figures 4-6)!

Figure 4 The fixture delivers highly accurate, stable and repeatable measurement results.

Figure 5 This time, the fixture is being used in a full enclosed fashion.

Figure 6 The fixture works well even with legacy DMMs.

This custom fixture has been quite useful in my small home office/lab and didn’t cost me a week’s salary….actually, my week’s salary now won’t even buy me a coffee, since I’m now semi-retired, but you get the point! Hopefully, others will also find this fixture useful with their high-resolution bench DMMs.

Michael A Wyatt is a life member with the IEEE and has continued to enjoy electronics ever since his childhood. Mike has a long career spanning Honeywell, Northrop Grumman, Insyte/ITT/Ex-elis/Harris, ViaSat and retiring (semi) with Wyatt Labs. During his career he accumulated 32 US Patents and in the past published a few EDN articles including Best Idea of the Year in 1989.

Related Content

• Custom DIY LCR SMD fixture for low-Z components
• DIY custom Tektronix 576 & 577 curve tracer adapters
• DMM Plug-In Test Resistor with temperature sensing

 

The post Custom DIY DMM SMD fixture for low Z measurements appeared first on EDN.

Increasing power demands in data centers demand high-efficiency, high-density power-conversion solutions.

Figure 1 shows a block diagram of power distribution inside an IT tray. A 48V bus bar goes down the back of the rack to distribute power to the IT trays. Inside each tray is hot-swap or e-fuse circuitry to limit inrush current during tray plug-in and to protect the upstream rack during tray failures. Intermediate bus converters (IBCs) convert 48V to the second-stage voltage, usually 12V or 6V. Final-stage multiphase buck voltage regulators complete power delivery by converting the second-stage voltage to the loads, with the majority of power going to sub-1V, high-current processors. In this edition of Power Tips, I will focus on the 48V IBC, covering design considerations, comparing topologies, and discussing system trade-offs of various approaches.

Figure 1 48V IT tray power distribution. Source: Texas Instruments

The IBC power distribution network offers a wide range of power-conversion approaches inside an IT tray (Reference 1). As the system architect, you have three main design choices:

• A modular or discrete solution (also known as chip-down design).
• Regulated, unregulated (also known as fixed ratio) or semiregulated IBC operation.
• The second-stage bus voltage to maximize system performance.

When selecting a modular or chip-down design power converter, your main trade-off will be power density vs. board design flexibility. Power modules, as shown in Figure 2a, are highly optimized solutions built on high-layer-count printed circuit boards (PCBs) (usually more than 16), offering prequalification and the highest power density. The drawbacks of power modules are a lack of flexibility, with fixed footprints and set features, as well as a higher cost per watt.

Chip-down designs, as shown in Figure 2b, are highly flexible solutions that offer footprint and feature freedom, with a lower cost per watt in high-volume production. Their drawbacks include longer upfront time and greater cost investments to qualify the design.

(a) (b)

Figure 2 48V IBC design examples of modular (a) and chip-down design (b) approaches. Source: Texas Instruments

When considering the output regulation of the IBC, your choice depends on two main factors: the load being powered and the operating range of the IBC’s input bus voltage. When the IBC directly drives 12V loads such as cooling fans, hard drives and Peripheral Component Interconnect Express cards, only a fully regulated output voltage (Reference 1) will ensure component safety. In modern data centers, the tray voltage has a more stable, narrow range, typically 40V to 60V. This narrow input range gives you the option to use higher-efficiency and higher-power-density fixed-ratio or semiregulated IBCs. The regulated second-stage voltage regulators following the IBC stage can absorb fixed-ratio IBC output voltage fluctuations.

Your third design choice is the second-stage voltage delivered by the IBC. Equation 1 determines system efficiency (ηsystem):

ηsystem = ηIBC x ηPDN x ηVR

For a given power load, decreasing the second-stage bus voltage will lower the IBC efficiency (ηIBC), because it must deliver more current at a lower voltage to provide the same output power. Similarly, for the motherboard power distribution network (PDN), which distributes current from the first-stage IBC to the second-stage voltage regulator, the PDN efficiency (ηPDN) will also decrease because of increased I2 x R ohmic losses. The benefit of a lower second-stage bus voltage is apparent when using final-stage, high-frequency, high-current voltage regulators with significantly reduced voltage-related switching losses. This results in higher second-stage efficiency (ηVR) and a potentially smaller size of the second stage.

Unlike a buck converter-dominated second-stage voltage regulator, a first-stage IBC has a wide range of power delivery approaches and thus a wider variety of power-conversion topologies available. In most modern IT applications, isolation for safety purposes is not required, so your power topology options increase further when you can consider transformerless options. Figure 3 shows four popular options for IBC module and chip-down designs.

The full-bridge converter shown in Figure 3a is a simple buck converter-derived transformer-isolated topology. The full-bridge converter’s strengths are ease of regulation and the ability to easily scale the intended output voltage by adjusting the transformer turns ratio for your chosen second-stage bus voltage. One drawback of the full-bridge converter is that transformer design is key to its performance, requiring a high-layer-count PCB that limits the topology to module-based designs. Another drawback of the full-bridge converter is that the primary devices are hard-switched, limiting power density and efficiency.

The transformer-isolated inductor-inductor-capacitor (LLC) converter shown in Figure 3b looks very similar to the full-bridge converter but uses an additional capacitor and two inductors to eliminate switching-related losses in the primary devices, enabling high efficiency and high power density (Reference 2). The LLC converter has the same transformer-related strength (an easily scalable output voltage) and weakness (it’s limited to module-based designs) as the full-bridge converter. The LLC converter operates with the highest efficiency at the resonant frequency set by the additional passive components (CR and LR), with efficiency decreasing as you move away from the resonant frequency to regulate the output voltage. For this reason, the LLC converter’s most common application in IBCs is fixed-ratio designs, always operating at the resonant frequency, ensuring the highest efficiency.

Two other popular topologies, the hybrid switched-capacitor (HSC) converter (Reference 3) shown in Figure 3c and the basic buck converter shown in Figure 3d, both offer benefits for chip-down designs because of their lack of AC-dependent power transformers. The HSC converter has a natural step-down ratio of 4-to-1, making it a strong candidate for high-efficiency 48V to 12V IBCs. The addition of flying capacitors limits the power density and hinders this converter’s operation in boost mode, making it a good fit for semiregulation, as regulating only occurs in step-down buck converter mode.

Because the HSC converter has a natural step-down ratio of 4-to-1, scaling the output voltage down further to an 8-to-1 6VOUT design (for example) is more challenging than it would be for the full-bridge and LLC converter options because the HSC converter must rely instead on a longer freewheeling period, requiring a larger output filter inductor, decreasing power density and efficiency.

The buck converter is the most common topology in power electronics, used exclusively in the second-stage voltage regulator, so it is natural to want to apply this simple and well-known approach to the IBC stage as well. The challenge with using a buck converter in the higher-voltage IBC application is that the power devices experience the highest voltage and current stresses when compared to the other topologies, limiting efficiency and power density.

(a) (b) (c) (d)

Figure 3 Popular IBC topologies: full-bridge converter (a); LLC converter (b); HSC converter (c); and buck converter (d). Source: Texas Instruments

Table 1 compares the different topologies and trade-offs.

  Full-bridge converter LLC converter HSC converter Buck converter

Module or chip-down design	Module	Module	Both	Both
Regulation type	Regulated	Fixed ratio	Semiregulated	Regulated
Efficiency	Medium	High	High	Low
Power density	Medium	High	Medium	Low
Output-voltage scalability	High	High	Medium	Medium
Complexity	Medium	High	High	Low

Table 1 Comparing IBC topology characteristics.

 With the maturation of gallium nitride (GaN) power devices (Reference 4), which have much lower switching-related charges compared to traditional silicon metal-oxide semiconductor field-effect transistors (MOSFETs), simpler topologies like the buck converter topology become more attractive and viable options for higher-voltage applications like IBCs. See Table 2.

  100V Texas Instruments GaN semiconductor 100V silicon MOSFET Difference

VDS (V)	100	100
RDS(on) (mΩ)	1.1	1.7	35% lower
QG (nC)	27	106	75% lower
QOSS (nC)	98	205	52% lower
QGD (nC)	2.5	26	90% lower
FOM1 = QG x RDS(on)	29.7	180.2	83% lower
FOM2 = QOSS x RDS(on)	107.8	348.5	69% lower
FOM3 = QGD x RDS(on)	2.75	44.2	93% lower
Package (mm x mm = mm2)	4 x 6.5 = 26 FET with gate driver	5 x 6 = 30 Discrete FET	13% smaller

Table 2 Comparison of 100V GaN and silicon-based IBC semiconductor options.

The IBC power distribution network offers the widest range of power-conversion approaches of the systems inside an IT tray for good reason. As power requirements and architectures rapidly evolve, the best way to optimize performance for 48V IBCs changes. And as additional variables such as highly improved GaN semiconductors get thrown into the equation, it becomes even more important to understand design considerations, topology comparisons and trade-offs.

References

1. Hsu, C., L. Olariu, S. Zou, et al. “48V Onboard Power Solution Requirements.” Open Compute Project, Version 1.0.0, Nov. 15, 2024.
2. McDonald, Brent. “Overview of a planar transformer used in a 1kW high-density LLC power module.” Texas Instruments technical article, 2025.
3. Li, C., and J.A. Cobos. “A Switched Capacitor and Autotransformer Hybrid Converter With DC Current in the Windings,” in IEEE Transactions on Power Electronics 37 (2), February 2022, pp. 1870-1884.
4. Gallium nitride (GaN) power stages, Texas Instruments.

David Reusch is a systems engineer on the data center team at Texas Instruments, specializing in power electronics. David has more than 20 years of experience in power electronics, ranging from cutting-edge gallium nitride (GaN) technology to high-reliability space-grade DC-DC converters. He received his B.S., M.S. and Ph.D. in electrical engineering from Virginia Tech.

 

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In modern engineering, precision fluid control is vital across industries ranging from electronics manufacturing to medical device design. Peristaltic pumps, with their distinctive squeeze-and-release mechanism, deliver exceptional reliability, cleanliness, and accuracy in fluid transfer. By preventing direct contact between the pump and the fluid, they ensure contamination-free operation while reducing maintenance demands.

This post explores the fundamentals of peristaltic pumping and how electric-drive systems help engineers achieve the perfect flow in today’s most demanding applications.

Peristaltic pump vs. electric peristaltic pump

A peristaltic pump refers to the general pumping principle: fluid is moved through flexible tubing by a rotating squeeze-and-release motion. This design ensures accurate flow and prevents contamination since the fluid never touches the pump components.

An electric peristaltic pump, however, is a specific implementation powered by an electric motor. The motor provides consistent speed, programmable control, and higher precision, making it ideal for industrial automation, laboratory dosing, and electronics manufacturing processes. While the term “peristaltic pump” covers the entire category, “electric peristaltic pump” highlights the modern, motor-driven versions that engineers rely on for efficiency and repeatability.

Figure 1 A sample of today’s compact electric peristaltic pump—this battery-operable low-voltage DC motor version demonstrates modern design efficiency. Source: Author

Peristaltic pumps vs. dosing pumps

A dosing pump is a broader category of pumps designed to deliver exact volumes of fluid at controlled intervals. Peristaltic pumps can serve as dosing pumps when paired with electric drives and programmable controls, but other pump types—such as diaphragm or piston pumps—are also used for dosing applications.

In short, all electric peristaltic pumps can function as dosing pumps, but not all dosing pumps are peristaltic. Understanding this distinction helps engineers select the right solution depending on whether the priority is contamination-free transfer, chemical compatibility, or ultra-precise dosing.

As a quick aside, it’s worth noting the distinction between DC-motor-driven and stepper-motor-driven peristaltic pumps. DC motors provide continuous rotation with simple speed control, making them cost-effective and compact for general fluid transfer.

Stepper motors, on the other hand, deliver precise incremental motion, enabling highly accurate dosing and repeatability. The choice between the two depends on application requirements: DC motors excel in straightforward pumping tasks, while stepper motors are favored in laboratory and industrial settings where precision is paramount.

Figure 2 A stepper-motor peristaltic pump delivers responsive start-stop and reverse operation, offers a wide speed range, and ensures reliability, thus meeting the accurate and dependable flow control demanded by precision instruments. Source: Author

The inner workings of peristaltic pumps

At the heart of a peristaltic pump is a simple but ingenious principle: fluid is transported by compressing flexible tubing in a controlled sequence. As rollers mounted on a rotating rotor travel along the tubing, they push the fluid forward in discrete segments, creating a smooth, continuous flow. Because the fluid remains fully enclosed within the tubing, there is no risk of contamination or contact with mechanical components, making this design particularly valuable in sensitive applications such as pharmaceuticals.

The internal structure of a peristaltic pump reflects this principle with elegant simplicity. A rotor fitted with rollers or shoes provides the pressure needed to move the fluid, while the tubing’s elasticity ensures it returns to its original shape after each cycle. The pump housing supports and guides the mechanism, ensuring consistent operation.

This combination of mechanical precision and material resilience allows peristaltic pumps to deliver accurate dosing, reliable performance, and easy maintenance—qualities that make them indispensable in modern engineering systems.

Figure 3 Drawing simply depicts the mechanisms of single-roller and multi-roller peristaltic pumps. Source: Author

As a closely related note, industrial peristaltic pumps differ from those used in general and medical applications. Industrial designs often employ shoe mechanisms to achieve higher pressures and rugged performance, making them suitable for chemical transfer, mining, and other heavy-duty environments where durability is paramount.

By contrast, general-purpose and medical pumps typically rely on roller mechanisms, which minimize friction, reduce energy consumption, and extend tubing life—qualities essential for precision dosing, sterility, and reliable operation in laboratory and healthcare settings.

And when powered by an electric motor, the same mechanism gains programmable control, variable speed adjustment, and enhanced precision. Electric peristaltic pumps transform the fundamental design into a highly versatile dosing system, capable of delivering exact volumes with repeatability. This evolution from a simple mechanical concept to an automated solution makes them indispensable in neoteric engineering environments where accuracy, efficiency, and reliability are non-negotiable.

Pulsed flow: Quick pointers for makers and engineers

Now to a few compact cues and practical insights to keep your designs flowing with precision. First off take note that motor choice sets the tone for performance: DC drives are cost-effective for simple transfer tasks like irrigation or fluid circulation, while stepper motors deliver the precision required for accurate dosing.

Roller mechanisms are especially suitable for medical and laboratory applications, since they minimize friction, extend tubing life, and provide gentle, contamination-free fluid handling. They also make an excellent choice for hobbyist projects, offering simplicity, reliability, and low maintenance for makers experimenting with fluid transfer.

By contrast, shoe mechanisms are designed for rugged industrial environments where higher pressures are needed, though they accelerate tubing wear. Tubing selection is equally critical; silicone ensures biocompatibility, PVC covers general transfer needs, and specialized elastomers withstand aggressive chemicals.

Now recall that roller pumps themselves come in single-roller and multi-roller designs. Single-roller pumps are mechanically simpler, lower-cost, and easier to maintain, making them suitable for basic transfer or hobbyist projects where flow smoothness is less critical.

Multi-roller pumps, by contrast, provide smoother, more continuous flow with reduced pulsation, which is essential in medical and laboratory applications where dosing accuracy and patient safety matter. While multi-roller designs increase complexity and cost, they extend tubing life and deliver higher precision, making them the preferred choice in food and beverage industries as well.

Also, electric drives add programmable control and variable speed, enabling integration with MCUs or PLCs for automation, while compact low-voltage battery-operated designs balance efficiency with portability in point-of-care devices. Notably, to mitigate the risk of power outages, contemporary electric peristaltic pumps for medical applications are frequently equipped with hand cranks for manual fluid delivery.

In today’s market, DC drive versions are available with more than just a regular DC motor—many include extra leads for speed control inputs (often via pulse width modulation), tachometer outputs, and other control/feedback signals. These additions give designers greater flexibility in monitoring, closed-loop control, and seamless integration with modern embedded systems, making even basic DC drives far more versatile than before.

Figure 4 Datasheet snippet highlighting a brushless peristaltic pump that delivers multiple features, including speed and direction control. Source: Binaca Pumps

Maker tip: PPM-controlled “digital” peristaltic pumps simplify automation by emulating the behavior of standard RC servo motors. Because the motor driver is integrated directly into the pump, you can skip the complex external circuitry usually needed to manage speed or direction. This lets you control the pump directly from a microcontroller’s digital pin using standard libraries—saving you both space and setup time (here is a practical example).

Frankly, when it comes to real-world control challenges, few are as nuanced as those involving peristaltic pumps. The core difficulty stems from two inherent characteristics of their operation. First, these pumps often run at very low speeds, sometimes down to a complete standstill depending on the application. Second, the motor experiences highly variable loads as the rollers engage and disengage with the flexible tube.

For most of the rotation cycle, the rollers move smoothly along the tube with minimal changes in torque or fluid pressure. However, at the points of disengagement and re-engagement, the system encounters sharp pulses in both torque and pressure.

That is, the combination of low-speed operation (which challenges velocity controllers) and cyclic load fluctuations (which creates non-linear disturbances) is exactly what makes these pumps “fussy” to control. Addressing these dynamics requires specialized motion control strategies—but that is a topic for another discussion.

Closing note: Peristalsis in engineering form

I have more to share but let me close with the fundamentals at this time.

Peristaltic pumps are a class of positive displacement pumps inspired directly by biology. Just as peristalsis in the digestive tract moves food through rhythmic muscle contractions, these pumps transport fluids by progressively deforming flexible tubing with rollers or shoes. The motion sweeps fluid forward, but because the swept length is always less than the tubing circumference, each rotation introduces a brief pause, resulting in the characteristic pulsed flow.

Designs vary between fixed and variable occlusion systems: fixed occlusion maintains a constant compression force, while variable occlusion allows adjustment via springs to fine-tune performance. Accuracy is further influenced by the slip factor, a correction term that accounts for incomplete tubing recovery and backflow, which can cause measured dispense rates to differ from theoretical values.

In peristaltic pump engineering, slip refers specifically to tubing recovery and backflow losses, which differs from the slip factor used in turbomachinery but serves the same purpose of correcting theoretical versus actual flow.

In essence, peristaltic pumps mirror a biological process with engineering precision—balancing simplicity, safety, and adaptability across a broad range of applications. In healthcare, they provide sterile infusion for IV therapy, dialysis, and precise drug delivery. In laboratories, they handle chemical dosing, reagent transfer, and bioprocessing where purity is paramount. Industrially, they manage viscous fluids, corrosive chemicals, and food-grade materials without risk of cross-contamination.

In the food and beverage sector, they support hygienic transfer of juices, dairy, and brewing ingredients. For hobbyists, they simplify aquarium maintenance, hydroponics, and small-scale brewing. In agriculture, they excel at nutrient dosing in irrigation and supplement delivery in animal farming. Their gentle, pulsed flow and hygienic design make them a versatile solution wherever controlled, reliable fluid handling is required.

As you explore these designs in your own projects, consider how roller choice, hose selection, occlusion type, and modern drive features can shape performance, and share your insights to keep the conversation on precision fluid handling moving forward.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

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Obtain tighter stop band impedance variance via the techniques detailed in this tutorial.

Input impedances presented by lowpass and highpass filters in their respective stop bands are usually not controlled and can vary quite widely. Sometimes though, we’d like to have a little better control of them.

For example, tee-configuration low-pass filters and high-pass filters exhibit input impedances and frequency responses which are typified in the following sketches:

Figure 1 A typical tee-configuration low-pass filter delivers non-ideal results.

Figure 2 A typical tee-configuration high-pass filter also delivers non-ideal results.

For tee-configuration filters, the presented input impedance in the passband tends toward the load resistance value, but in the stopband, the presented input impedance rises without limit. That essentially uncontrolled and rising impedance can create stability problems for some kinds of driving devices delivering input signals to such filters.

There is at least a partial remedy for this impedance issue possible, as follows:

Figure 3 A tee-configuration filter pair provides at least a partial remedy.

Using both a low-pass and high-pass filter, with each feeding its respective load, the input impedance becomes controllable both in the passband and the stopband of whichever filter you decide is the intended signal path. Input impedance and frequency responses would take on the following forms:

Figure 4 Controlled impedance filtering can improve stability.

The corner frequency impedance null doesn’t go away, but the input impedance both above and below that corner frequency tends to the load resistance values, chosen here as fifty ohms, which may help make a driving amplifier more stable.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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As industrial environments rapidly evolve with the integration of operational technology (OT) and information technology (IT), the demand for seamless connectivity and reliable power delivery has never been higher. The proliferation of smart devices, such as sensors, controllers, cameras and robotic arms, has made data indispensable to modern factories and process industries.

To meet the increased demand, more industrial IoT (IIoT) device manufacturers are turning to Power over Ethernet (PoE) as a preferred solution, leveraging its unique ability to deliver both power and data over a single cable. This convergence is enabling smarter, more flexible and efficient industrial operations, while simplifying deployment and maintenance for end users.

Figure 1 Industrial environments are increasingly integrating operational and information technologies. Source: Microchip

What’s Power over Ethernet (PoE)?

Power over Ethernet (PoE) is a technology that allows electrical power and data to be transmitted simultaneously over standard Ethernet cabling. It was first introduced by PowerDsine in 1998; the company was later acquired by Microchip Technology. The Institute of Electrical and Electronic Engineers (IEEE) introduced the first IEEE 802.3af standard in 2003.

PoE was initially developed to power devices like IP phones and wireless access points without the need for separate power supplies. Since then, PoE standards have evolved to include IEEE 802.3 af/at/bt supporting higher power levels and a broader range of devices, making it a cornerstone technology for modern networking encompassing industrial automation and IIoT deployments.

Why IIoT manufacturers are turning to PoE

For IIoT device manufacturers, PoE offers a host of compelling benefits. PoE simplifies deployment by combining power and data in a single cable, eliminating the need for separate electrical wiring and reducing installation complexity and cost. It enables flexible placement of devices, allowing installation in remote, hard-to-reach, or hazardous locations where traditional power sources may be unavailable or cost-prohibitive.

PoE also supports unified network architecture, streamlining network design and making it easier to scale and adapt to changing operational needs. Reliability and compliance are enhanced, as standards-based PoE delivers safe, low-voltage DC power, supporting regulatory compliance and minimizing electrical hazards.

Additionally, offering PoE-powered devices can provide manufacturers with a competitive advantage in a crowded market by delivering a more convenient, integrated solution to customers.

Overcoming PoE deployment challenges in industrial settings

Despite its advantages, deploying PoE in industrial environments is not without challenges. One of the primary obstacles is the limited availability of PoE-enabled network infrastructure. Many existing industrial networks lack PoE switches, and even when available, these switches may not provide sufficient power on every port to support all connected devices.

The cost and complexity of upgrading network infrastructure can be prohibitive, especially in legacy facilities. Other challenges include limited access to power, as not all areas of a factory or plant have easy access to network cabling or power outlets, making device placement difficult. The high cost of power delivery can also be a concern, as retrofitting facilities to support PoE can be expensive and disruptive.

Compatibility concerns must be addressed to ensure that PoE-powered devices work seamlessly with existing network equipment, avoiding downtime and support issues. Finally, scalability is a challenge, as the number of connected devices grows, so does the demand for reliable, scalable power solutions.

Introducing PoE midspans: Supplementing network power

To address the challenge of limited PoE-enabled infrastructure, many industrial facilities are turning to PoE midspans, also known as injectors, to supplement network power where it does not exist. A PoE injector is a device that sits between an Ethernet port that is not supplying PoE and the powered device, injecting power into the Ethernet cable so that both data and power are delivered to the endpoint.

This approach allows manufacturers and customers to deploy PoE-powered IIoT devices without the need to replace existing switches or overhaul network architecture, making it a cost-effective and scalable solution for expanding PoE coverage in industrial environments.

Figure 2 PoE midspans inject power into the Ethernet cable. Source: Microchip

PoE industrial injectors vs. standard indoor injectors

While standard indoor PoE injectors are suitable for office or commercial settings, industrial environments demand more robust solutions. PoE industrial injectors are specifically designed to withstand the harsh conditions often found in factories, processing plants, and outdoor installations.

These injectors feature ruggedized construction, enabling reliable operation in environments with extreme temperatures, humidity, dust, and vibration. They support an extended temperature range, ensuring consistent performance in both hot and cold conditions.

Enhanced safety and compliance are also critical, as industrial injectors meet stringent safety and regulatory standards, providing low-voltage, standards-compliant DC power that minimizes electrical hazards. Industrial PoE injectors support higher power levels—such as IEEE 802.3bt up to 90 W—to accommodate demanding devices and are designed with robust surge protection, which is essential in industrial environments where electrical surges from machinery or harsh conditions are more common.

Flexible mounting options, such as DIN rail, wall, or rack installations, accommodate diverse deployment scenarios. Reliability and longevity are ensured through components and enclosures designed for continuous operation, providing long-term durability and minimal maintenance. These features are essential for maintaining uptime, safety, and performance in industrial settings, where environmental challenges and operational demands are far greater than in typical office environments.

Figure 3 Here is a visual comparison between standard indoor midspan (above) and industrial midspan (below). Source: Microchip

What to look for in a PoE solution provider

For IIoT device manufacturers and customers deploying PoE-powered devices, selecting the right PoE solution provider is critical. Proven compatibility is essential; the provider’s injectors should be tested and validated for seamless operation with a wide range of industrial devices, reducing the risk of downtime and support issues.

Flexible power options are important, with support for various power levels and device types to meet diverse application needs. Reliability and compliance should be prioritized, ensuring solutions meet industry standards for safety and performance, supporting regulatory requirements and minimizing risk.

Ease of installation is also key, with plug-and-play solutions that leverage existing Ethernet cabling to simplify deployment and reduce installation time. Rugged design is necessary for industrial-grade injectors, offering robust construction and extended temperature ranges for reliable operation in challenging environments.

Finally, strong technical support and post-sale service from the provider can help resolve compatibility issues and ensure long-term satisfaction. By prioritizing these features, manufacturers and customers can ensure successful, scalable, and reliable PoE deployments in industrial environments, unlocking the full potential of smart IIoT devices.

Alan Jay Zwiren is senior marketing manager of Microchip Technology’s Networking and Connectivity Business Unit.

Special Section: Smart Factory

• Rethinking machine vision in industrial automation

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Cirrus Logic has launched the CS82L4x series of analog front-end (AFE) chips for CIS and CCD sensors in scanners and industrial imaging platforms. Based on a redesigned SAR ADC architecture, the devices are said to offer faster scan times and enhanced efficiency, while an integrated RGB LED driver reduces design complexity.

The CS82L41, CS82L44, and CS82L46 provide one, four, and six channels, respectively, with a conversion rate of 24 Msamples/s per channel. With 16-bit resolution, the AFE ICs convert LED reflections from scanned objects into accurate digital representations. Per-channel signal conditioning includes reset level clamping, correlated double sampling, and programmable polarity, gain, and offset adjustment.

Operating from a 3.3-V supply, the CS82L4x series provides a scalable platform for multi-lens and multichannel scanning architectures across a range of imaging systems. The CS82L41 features an SPI control interface with CMOS output. The CS82L44 and CS82L46 offer SPI or I²C control interfaces, CMOS or LVDS outputs, and integrated sensor timing generation. All devices operate over a temperature range of −40°C to +85°C and come in QFN packages.

Samples are available now from Cirrus.

CS82L41 product page

CS82L44 product page

CS82L46 product page

Cirrus Logic 

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