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The 800 V automotive systems enable higher performance electric vehicles capable of driving ranges longer than 400 miles on a single charge and charging times as fast as 20 minutes. 800 V batteries rarely operate at exactly 800 V and can go as high as 900 V with converter input requirements up to 1000 V.

There are a number of power design challenges for 1000-V-type applications, including field-effect transistors (FET) selection and the need to have a strong enough gate drive for >1,000 V silicon FETs which generally have larger gate capacitances than silicon carbide (SiC) FETs. SiC FETs have the advantage of lower total gate charge than silicon FETs with similar parameters; however, SiC often comes with increased cost.

You’ll find silicon FETs used in designs such as the Texas Instruments (TI) 350 V to 1,000 V DC Input, 56 W Flyback Isolated Power Supply Reference Design, which cascodes two 950 V FETs in a 54 W primary-side regulated (PSR) flyback. In lower-power general-purpose bias supplies (<10 W), it is possible to use a single 1,200 V silicon FET in TI’s Triple Output 10W PSR Flyback Reference Design which is the focus of this power tip.

This reference design can be a bias supply for the isolated gate drivers of traction inverters. It includes a wide input (60 V to 1000 V) PSR flyback with three isolated 33 V outputs, 100 mA loads, and uses TI’s UCC28730-Q1 as the controller. Figure 1 shows the UCC28730-Q1 datasheet with a 20-mA minimum drive current.

Figure 1 Gate-drive capability of the UCC28730-Q1 with a 20-mA minimum drive current. Source: Texas Instruments

The challenge is that the 1,200 V silicon FET will have a very large input capacitance (Ciss) of around 1,400 pF at 100 V VDS, which is 4 times more than a similarly rated SiC FET.

With a relatively weak gate drive from the UCC28730-Q1, Equation 1 estimates the primary FET turn-on time to be approximately 840 ns.

Figure 2 shows that as FET gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD) increases, it consumes the on-time of the primary FET required to regulate the output voltage of the converter.

Figure 2 FET turn on and off curves, as FET CGS and CGD increase, it consumes the on-time of the primary FET required to regulate the output voltage of the converter. Source: Texas Instruments

Figure 3 shows the undesirable effect of this by looking at the gate voltage of the UCC28730-Q1 driving the primary FET directly. In this example, it takes approximately 800 ns to completely turn on the FET and 1.5 µs for the gate to reach its nominal voltage. As you go to 400 V, the controller is still trying to charge CGD when the controller decides to turn off the FET. It is much worse at 1,000 V where the CGS is still being charged before turning off. This shows that as the input voltage increases, the controller cannot output a complete on-pulse and therefore the converter cannot power up to nominal output voltage.

Figure 3 Gate voltage of UCC28730-Q1 directly driving the primary FET with increasing input voltage. Source: Texas Instruments

To solve this, you can use a simple buffer circuit using two low-cost bipolar junction transistors as shown in Figure 4.

Figure 4 Simple N-Channel P-Channel N Channel-, P-Channel N-Channel P-Channel (NPN-PNP) emitter follower gate-drive circuit. Source: Texas Instruments

Figure 5 shows the gate current waveform of the primary FET and demonstrates the buffer circuit capable of gate drive currents greater than 500 mA.

Figure 5 Gate drive buffer current waveform of PMP23431, demonstrating that the buffer circuit is capable of gate drive current greater than 500 mA. Source: Texas Instruments

As shown in Equation 2, this reduces the charge time to 33 ns and is 25 times faster compared to just using the gate drive of the controller.

A PSR flyback architecture typically requires a minimum load current to stay within regulation. This helps increase the on-time and the converter can now power up to its minimum load requirements at 1000 V as shown in Figure 6. The converter’s overall performance is in the PMP23431 test report and Figure 7 shows the switching waveform with constant pulses on the primary FET. At 1,000 V with the minimum load requirement, the on-time is approximately 1 µs. Without this buffer circuit, the converter would not power up to 1,000 V input.

Figure 6 Converter startup with minimum load requirement with a 1000-V input. Source: Texas Instruments

Figure 7 Primary FET switching waveform of PMP23431 at 1000 V input. Source: Texas Instruments

In high voltage applications up to 1,000 V, the duty cycle can be quite small—in the hundreds of nanoseconds. A high-voltage silicon FET can be the limiting factor to achieving a well-regulated output due to its high gate capacitances. This power tip introduced PMP23431 and a simple buffer circuit to quickly charge the gate capacitances to support the lower on-times of these high voltage systems.

Darwin Fernandez is a systems manager in the Automotive Power Design Services team at Texas Instruments. He has been at TI for 14 years and has previously supported several power product lines as an applications engineer designing buck, flyback, and active clamp forward converters. He has a BSEE and MSEE from California Polytechnic State University, San Luis Obispo.

 

Related Content

• Power Tips #128: Designing a high voltage DC-link capacitor active precharge circuit
• Power Tips #76: Flyback converter design considerations
• Power Tips #98: Designing a DCM flyback converter
• Why use a BJT in a flyback converter?
• Power Tips #91: How to improve flyback efficiency with a nondissipative clamp
• Power Tips #77: Designing a CCM flyback converter
• Power Tips #17: Snubbing the flyback converter

Additional Resources

1. Read the application note, “Practical Considerations in High-Performance MOSFET, IGPT and MCT Gate-Drive Circuits.”
2. Check out the application report, “Fundamentals of MOSFET and IGBT Gate Driver Circuits.”
3. Download the PMP41009 reference design.

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We’re in the fourth industrial revolution, commonly referred to as Industry 4.0, where advanced technologies are reshaping the landscape of manufacturing and business. The idea of machines communicating with each other, robots milling around, and factories practically running themselves no longer seems like a sci-fi concept.

In the fourth industrial revolution, digital and physical worlds are converging to improve the industrial and commercial (I&C) industries. The Internet of Things (IoT) is a critical player in this revolution, disrupting every facet of the global economy and laying the foundation for a comprehensive overhaul of production, management, and governance systems.

With an estimated annual economic impact ranging from $1.6 trillion to $4.9 trillion by 2025 for factories and retail settings, the rising potential of IoT is becoming increasingly evident as advancements in connectivity open new doors for innovative use cases across the I&C industries.

Despite the rapid advancements in wireless network technologies, companies have been held back from achieving their maximum efficiency and productivity gains due to several operational challenges. Many businesses in industrial and commercial settings face substantial downtime, delayed production, high operating costs, low energy efficiency, and inefficient processes.

So, how can we leverage Industry 4.0’s digital transformation to increase productivity, reduce downtime, lower costs, and drive future growth? The answer may lie in harnessing the power of the I&C IoT.

What’s industrial and commercial IoT?

The Industrial Internet of Things (IIoT) involves the integration of smart technologies and sensors in the industrial sector, enabling the collection and analysis of data to optimize processes, improve worker safety, enhance energy efficiency, improve productivity, and predict potential issues. The IIoT is indispensable for navigating global competition, striking a balance between capturing new business and ensuring sustainable operations.

Commercial IoT encompasses the application of interconnected devices and technologies in the commercial business domain, where the integration of digital solutions aims to enhance retail efficiency, reduce labor costs, and create a seamless omnichannel experience. These advancements in smart retail technology are helping transform traditional business models and increase overall profitability for companies across the globe.

Figure 1 IoT technology will contribute to the growth of commercial industries. Source: Silicon Labs

While such devices may sound out of reach, many exist and are used today for a growing number of I&C applications. In the commercial industry, facility managers seeking to upgrade their estate cost-effectively often use commercial lighting devices like the INGY smart lighting control system that incorporates sensors into luminaires to enable a variety of smart building services without needing an additional infrastructure investment.

Retailers are also adopting electronic shelf label (ESL) devices like the RAINUS InforTab that manage store-wide price automation and reduce operating costs by eliminating hours of tedious human resources. Additionally, asset tracking devices like the Zliide Intelligent Tag can provide fashion retailers with extremely precise location information on how their merchandise moves, helping improve the user experience.

Of course, the commercial industry is not the only application for asset-tracking devices. Machine manufacturers and contractors can also use asset tracking devices like the Trackunit Kin tag that helps connect the entire construction fleet through one simple platform, reducing downtime and costs associated with asset management.

Manufacturers also use smart factory automation devices like CoreTigo’s IO-Link that provide cable-grade, fast, and scalable connectivity for millions of sensors, actuators, and devices at any site worldwide to enable real-time control and monitoring across the entire operational technology.

Likewise, plant and facility managers seeking a comprehensive view of their operations can use predictive maintenance devices such as the Waites plug-and-play online monitoring system to provide a range of sensors and gateways for monitoring and analyzing data, which streamlines device setup and installation.

Benefits of industrial and commercial IoT devices

The growing use of I&C IoT devices could help businesses in the commercial industry make well-informed, real-time decisions, have better access control, and develop more intelligent, efficient, and secure IoT applications. For example, before advanced I&C IoT technology, someone at a retail store had to go out and change the tags on the store shelves if the pricing changed.

Now, with electronic shelf labels, retailers can provide real-time updates. Additionally, by using connected devices and sensors to collect data about a wide variety of business systems, companies can automate processes and improve supply chain management efficiency.

For example, a large retail chain operating hundreds of stores across the country could integrate smart shelf sensors, connected delivery trucks, and a warehouse management system to monitor goods moving through the supply chain in real time. Insights from this data would enable retailers to reduce stockouts, optimize deliveries, and improve warehouse efficiency.

Businesses are also improving control by adopting commercial lighting solutions and wireless access points. With these solutions, businesses can enable indoor location services to track assets and consumer behavior and speed up click-and-collect through shop navigation.

I&C devices also have the potential to positively impact the industrial segment by helping businesses optimize operation efficiency, routing, and scheduling. Prior to predictive maintenance devices, manufacturers had to halt their production line for hours or days if a pump failed and they weren’t planning for it. The repercussions were substantial since every hour of unplanned machine downtime costs manufacturers up to $260,000 in lost production.

Figure 2 IIoT is expected to play a critical role in reshaping the industrial automation. Source: Silicon Labs

Now, with predictive maintenance systems, manufacturers can identify early-stage failures. Moreover, recent advancements in edge computing have unlocked new capabilities for industrial IoT devices, enabling efficient communication and data management.

Machine learning (ML) integration into edge devices transforms data analysis, providing real-time insights for predictive maintenance, anomaly detection, and automated decision-making. This shift is particularly relevant in smart metering, where wireless connectivity allows for comprehensive monitoring, reducing the need for human intervention.

Challenges for industrial and commercial IoT devices

I&C IoT devices have progressed significantly due to the widespread adoption of wireless network technologies, the integration of edge computing, the implementation of predictive maintenance systems, and the expansion of remote monitoring and control capabilities.

Despite all the benefits that I&C IoT devices could bring to consumers, these technologies are not being utilized to their fullest potential in I&C settings today. This is because four significant challenges stand in the way of mass implementation:

1. Interoperability and reliability

The fragmented landscape of proprietary IoT ecosystems is a significant hurdle for industrial and commercial industry adoption, and solution providers are addressing this challenge by developing multi-protocol hardware and software solutions.

Multi-protocol capabilities are especially important for I&C IoT devices, as reliable connectivity ensures seamless data flow and process optimization in factories, guarantees reliable connectivity across vast retail spaces, and contributes to consistent sales and operational efficiency. Due to the long product lifecycle, it is also critical for the devices to be compatible with legacy protocols and have the capability to upgrade to future standards as needed.

2. Security and privacy

Security and privacy concerns have been major roadblocks in the growth of industrial and commercial IoT, with potential breaches jeopardizing not only data but also entire networks and brand reputations. Thankfully, solution providers are stepping in to equip developers with powerful tools. Secure wireless mesh technologies offer robust defenses against attacks, while data encryption at the chip level paves the way for a future of trusted devices.

This foundation of trust, built by prioritizing cybersecurity from the start and choosing reliable suppliers, is crucial for unlocking the full potential of the next generation of IoT. By proactively shaping their environment and incorporating risk-management strategies, companies can confidently unlock the vast opportunities that lie ahead in the connected world.

3. Scalability of networks

Creating large-scale networks with 100,000+ devices is a critical requirement for several industrial and commercial applications such as ESL, street lighting, and smart meters. In addition, these networks may be indoors with significant RF interference or span over a large distance in difficult environments. This requires significant investments in testing large networks to ensure the robustness and reliability of operations in different environments.

4. User and developer experience

Bridging the gap between ambition and reality in industrial and commercial IoT rests on two crucial pillars: improving the user experience and the developer experience. If we’re going to scale and deploy this market at the level that we know needs to happen, we need solutions that simplify deployment and management for users while empowering developers to build and scale applications with greater speed and efficiency.

Initiatives like Matter and Amazon Sidewalk are paving the way for easier wireless connectivity and edge computing, but further strides are needed. Solution providers can play a vital role by offering pre-built code and edge-based inference capabilities, accelerating development cycles, and propelling the industry toward its true potential.

Looking ahead

As the industrial and commercial IoT landscape evolves, we are primed for a dynamic and interconnected future. The industrial and commercial IoT industry is poised for continued growth and innovation, with advancements in wireless connectivity, edge computing, AI, and ML driving further advances in industrial automation, supply chain optimization, predictive maintenance systems, and the expansion of remote monitoring and control capabilities.

The semiconductor industry has been quietly helping the world advance with solutions that will help set up the standards of tomorrow and enable an entire ecosystem to become interoperable.

Ross Sabolcik is senior VP and GM of industrial and commercial IoT products at Silicon Labs.

Related Content

• AI Will Empower Industry 4.0 — When It Arrives
• Designer’s Guide to Industrial IoT Sensor Systems
• Smart and Secure Embedded Solutions for IoT Design
• As Industry 4.0 Rises, DevOps Helps Expedite Workflows
• Jumping into Industry 4.0 with Predictive Maintenance Solutions

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Tape measures are right up there with uncooperative-coiling (and -uncoiling) extension cords and garden hoses on the list of “things guaranteed to raise my blood pressure”. They don’t work reliably (thanks to gravity) beyond my arm span unless there’s something flat underneath them for the entire distance they’re measuring. Metal ones don’t do well with curved surfaces, while fabric ones are even more gravity-vulnerable. Speaking of which, the only way to keep a fabric one neatly spooled when not in use is with a rubber band, which will inevitably slip off and leave a mess in whatever drawer you’re storing it in. And when metal ones auto-spool post-use, they inevitably slap, scratch, or otherwise maim your hand (or some other body part) enroute.

All of which explains why, when I saw Dremel’s HSLM-01 3-in-1 Digital Measurement Tool on sale at Woot! for $19.99 late last October, I jumped for joy and jumped on the deal. I ended up buying three of ‘em: one for my brother-in-law as a Christmas present, another for me, and the third one for teardown for all of you:

The labeling in this additional stock photo might be helpful in explaining what you just saw:

Here’s a more meaningful-info example of the base unit’s display in action:

The default laser configuration is claimed to work reliably for more than five dozen feet, with +/- 1/8-inch accuracy:

while the Wheel Adapter enables measuring curved surfaces:

and the Tape Adapter (yes, I didn’t completely escape tape, but at least it’s optional and still makes sense in some situations) is more accurate for assessing round-trip circumference (and yes, they spelled “circumference” wrong):

I mean…look how happy this guy is with his!

Apologies: I dilly-dally and digress. Let’s get to tearing down, shall we? Here’s our victim, beginning with the obligatory outer box shots:

And here’s what the inside stuff looks like:

Here’s part of the literature suite, along with the included two AAA batteries which I’ll put to good use elsewhere:

Technology licensed from Arm and STMicroelectronics? Now that’s intriguing! Hold that thought.

Here’s the remainder of the paper:

And here’s the laser measurer and its two-accessory posse:

This snapshot of the top of the device, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

is as good a time as any to conceptually explain how these devices work. Wikipedia more generally refers to them as laser rangefinders:

A laser rangefinder, also known as a laser telemeter, is a rangefinder that uses a laser beam to determine the distance to an object. The most common form of laser rangefinder operates on the time of flight principle by sending a laser pulse in a narrow beam towards the object and measuring the time taken by the pulse to be reflected off the target and returned to the sender. Due to the high speed of light, this technique is not appropriate for high precision sub-millimeter measurements, where triangulation and other techniques are often used. It is a type of scannerless lidar.

The basic principle employed, as noted in the previous paragraph, is known as “time of flight” (ToF), one of the three most common approaches (along with stereopsis, which is employed by the human visual system, and structured light, used by the original Microsoft Kinect) to discerning depth in computer vision and other applications. In the previous photo, the laser illumination emitter (Class 2 and <1mW) is at the right, with the image sensor receptor at left. Yes, I’m guessing that this explains the earlier STMicroelectronics licensing reveal. And the three metal contacts mate with matching pins you’ll soon see on the no-laser-necessary adapters.

The bottom is admittedly less exciting:

As are the textured and rubberized (for firm user grip) left and right sides (the two-hole structure at the bottom of the left side is presumably for a not-included “leash”):

I intentionally shot the front a bit off-center to eliminate reflections-of-self from bouncing off the glossy display and case finish:

The duller-finish backside presented no such reflectance concerns:

I have no idea what that white rectangular thing was inside the battery compartment, and I wasn’t brave enough to cut it open for a more thorough inspection (an RFID tracking tag, maybe, readers?):

This closeup of the back label does double-duty as a pictorial explanation of my initial disassembly step:

Screws underneath, just as I suspected!

You know what comes next…

Liftoff!

We can already see an overview of the laser transmitter function block (complete with a heatsink) at upper right and the receptor counterpart at upper left. Turns out, in fact, that the entire inner assembly lifts right out with no further unscrew, unglue, etc. effort at this point:

From an orientation standpoint, you’re now looking at the inside of the front portion of the outer case. Note the metal extensions of the three earlier noted topside metal contacts, which likely press against matching (flex? likely) contacts on the PCB itself. Again, hold that thought.

Now we can flip over and see the (even more bare) other side of the PCB for the first time:

This is a perspective you’ve already seen, this time absent the case, however:

Three more views from different angles:

And as you may have already guessed, the display isn’t attached to the PCB other than via the flex cable you see, so it’s easy to flip 180°:

Speaking of flipping, let’s turn the entire PCB back over to its back side, now unencumbered by the case that previously held it in place:

Again, some more views from different angles:

See those two screws? Removing them didn’t by itself get us any further along from a disassembly standpoint:

But unscrewing the two other ones up top did the trick:

Flipping the PCB back over and inserting a “wedge” (small flat head screwdriver) between the PCB and ToF subassembly popped the latter off straightaway:

Here’s the now-exposed underside of the ToF module:

and the seen-before frontside and end, this time absent the PCB:

Newly exposed, previously underneath the ToF module, is the system processor, a STMicrolectronics (surprise!…not, if you recall the earlier licensing literature…) STM32F051R8T7 based on an Arm Cortex-M0:

And also newly revealed is the laser at left which feeds the same-side ToF module optics, along with the image sensor at right which is fed by the optics in the other half of the module (keep in mind that in this orientation, the PCB is upside-down from its normal-operation configuration):

I almost stopped at this point. But those three metal contacts at the top rim of the base unit intrigued me:

There must be matching electrical circuitry in the adapters, right? I figured I might as well satisfy my curiosity and see. In no particular order, I started with my longstanding measurement-media nemesis, the Tape Adapter, first. Front view:

Top view:

Bottom view, revealing the previously foreshadowed pins:

Left and right sides, the latter giving our first glimpse at the end-of-tape tip:

And two more tip perspectives from the back:

Peeling off the label worked last time, so why not try again, right?

Revealed were two plastic tabs, which I unwisely-in-retrospect immediately forgot about (stay tuned). Because, after all, that seam along the top looked mighty enticing, right?

It admittedly was an effective move:

Here’s the inside of the top lid. That groove you see in the middle mates up with the end of the “spring” side of the spool, which you’ll see shortly:

And here’s the inside of the bottom bulk of the outer case. See what looks like an IC at the bottom of that circular hole in the center? Hmmm…

Now for the spool normally in-between those two. Here’s a top view first. That coiled metal spring normally fits completely inside the plastic piece, with its end fitting into the previously seen groove inside the top lid:

The bottom side. Hey, at least the tape isn’t flesh-mangling metal:

A side view, oriented as when it’s installed in the adapter and in use:

And by the way, about the spindle that fits into that round hole…it’s metallic. Again, hold that thought (and remember my earlier comment about using a rubber band to keep a fabric tape measure neat and tidy?):

Here’s the part where I elaborate on my earlier “forgot about the plastic tabs” comment. At first things were going fine:

But at this point I was stuck; I couldn’t muscle the inner assembly out any more. So, I jammed the earlier seen flat head screwdriver in one side and wedged it the rest of the way out:

Unfortunately, mangling one of the ICs on the PCB in the process:

Had I just popped both plastic tabs free, I would have been home free. Live and learn (once again hold that thought). Fortunately, I could still discern the package markings. The larger chip is also from STMicroelectronics (no surprise again!), another Arm Cortex-M0 based microcontroller, this time the STM32F030F4. And while at first, reflective of my earlier close-proximity magnetic-tip comment, I thought that the other IC (which we saw before at the bottom of that round hole) might be a Hall effect sensor, I was close-but-not-quite: it’s a NXP Semiconductors KMZ60 magnetoresistive angle sensor with integrated amplifier normally intended for angular control applications and brushless DC motors. In this case, the user’s muscle is the motor! Interesting, eh?

Now for the other, the Wheel Adapter. Front:

Top:

Bottom (pins again! And note that the mysterious white strip seen earlier was pressed into service as a prop-up device below the angled-top adapter):

Left and right sides:

And label-clad back:

I’m predictable, aren’t I?

Note to self: do NOT forget the two now-exposed plastic tabs this time:

That went much smoother this time:

But there are TWO mini-PCBs this time, one down by the contact pins and another up by the wheel, connected by a three-wire harness:

Unfortunately, in the process of removing the case piece, I somehow snapped off the connector mating this particular mini-PCB to the harness:

Let’s go back to the larger lower mini-PCB for a moment.  I won’t pretend to feign surprise once again, as the redundancy is likely getting tiring to the readers, but the main sliver of silicon here is yet another STMicroelectronics STM32F030F4 microcontroller:

The mini-PCB on the other end of the harness pops right out:

Kinda looks like a motor (in actuality, an Alps Alpine sensor), doesn’t it, but this time fed by the human-powered wheel versus a tape spool?

So, a conceptually similar approach to what we saw before with the other adapter, albeit with some implementation variation. I’ll close with a few shots of the now-separate male and female connector pair that I mangled earlier:

And now, passing through 2,000 words and fearful of the mangling that Aalyia might subject me to if I ramble on further, I’ll close, as-usual with an invitation for your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• Measuring powerful laser output takes a forceful approach
• Rotational (or linear) measurement using an optical mouse sensor
• Modeling and simulation of magnetoresistive sensor systems (Part 1 of 2)
• MEMS ultrasonic time-of-flight innovation: sensors advance user experiences
• 3D vision gives robots guidance

The post Looking inside a laser measurer appeared first on EDN.

In the rapidly evolving semiconductor industry, keeping pace with Moore’s Law presents opportunities and challenges, particularly in system-on-chip (SoC) designs. Notably, the number of transistors in microprocessors soared to an unprecedented trillion.

Therefore, as modern applications demand increasing complexity and functionality, improving transistor usage efficiency without sacrificing energy efficiency has become a key goal. Thus, the network-on-chip (NoC) concept has been introduced, a solution designed to address the limitations of traditional bus-based systems by enabling efficient, scalable, and flexible on-chip data transmission.

Designing an NoC involves defining requirements, selecting an architecture, choosing a routing algorithm, planning the physical layout, and conducting verification to ensure performance and reliability. As the final checkpoint before a NoC can be deemed ready for deployment, a deadlock/livelock-free system can be built, increasing confidence in design verification.

In this article, we will dive deeper into a comprehensive methodology for formally verifying an NoC, showcasing the approaches and techniques that ensure our NoC designs are robust, efficient, and ready to meet the challenges of modern computing environments.

Emergence of network-on-chip

NoCs have revolutionized data communications within SoCs by organizing chip components into networks that facilitate the simultaneous transmission of data through multiple paths.

The network consists of various elements, including routers, links, and network interfaces, which facilitate communication between processing elements (PEs) such as CPU cores, memory blocks, and other specialized IP cores. Communication occurs through packet-switched data transmission where data is divided into packets and routed through the network to its destination.

One overview of the complexity of SoC design emphasizes the integration of multiple IP blocks and highlights the need for automated NoC solutions across different SoC categories, from basic to advanced. It advocates using NoCs in SoC designs to effectively achieve optimal data transfer and performance.

At the heart of NoC architecture are several key components:

1. Links: Bundles of wires that transmit signals.
2. Switches/routers: Devices routing packets from input to output channels based on a routing algorithm.
3. Channels: Logical connections facilitating communication between routers or switches.
4. Nodes: Routers or switches within the network.
5. Messages and packets: Units of transfer within the network, with messages being divided into multiple packets for transmission.
6. Flits: Flow control units within the network, dividing packets for efficient routing.

Architectural design and flow control

NoC topology plays a crucial role in optimizing data flow, with Mesh, Ring, Torus, and Butterfly topologies offering various advantages (Figure 1). Flow control mechanisms, such as circuit switching and wormhole flow control, ensure efficient data transmission and minimize congestion and latency.

Figure 1 The topology of an NoC plays an important role in optimizing data flow, as shown with Mesh and Ring (top left and right) and Torus and Butterfly (bottom left and right). Source: Axiomise

Role of routing algorithms in NoC efficiency

As we delve into the complexity of NoC design, one integral aspect that deserves attention is the routing algorithm, the brains behind the NoC that determines how packets move through the complex network from source to destination. They must be efficient, scalable, and versatile enough to adapt to different communication needs and network conditions.

Some of the common routing algorithms for network-on-chip include:

1. XY routing algorithm: This is a deterministic routing algorithm usually used in grid-structured NoCs. It first routes to the destination columns along the X-axis and then to the destination rows along the Y-axis. It has the advantages of simplicity and predictability, but it may not be the shortest path and does not accommodate link failures.
2. Parity routing algorithm: This algorithm aims to reduce network congestion and increase fault tolerance of the network. It avoids congestion by choosing different paths (based on the parity of the source and destination) in different situations.
3. Adaptive routing algorithms: These algorithms dynamically change routing decisions based on the current state of the network (for example, link congestion). They are more flexible than XY routing algorithms and can optimize paths based on network conditions, but they are more complex to implement.
4. Shortest path routing algorithms: These algorithms find the shortest path from the source node to the destination node. They are less commonly used in NoC design because calculating the path in real-time can be costly, but they can also be used for path pre-computation or heuristic adjustment.

Advantages of NoCs

1. Scalability: As chip designs become more complex and incorporate more components, NoCs provide a scalable solution to manage interconnects efficiently. They facilitate the addition of new components without significantly impacting the existing communication infrastructure.
2. Parallelism: NoCs enable parallel data transfers, which can significantly increase the throughput of the system. Multiple data packets can traverse the network simultaneously along different paths, reducing data congestion and improving performance.
3. Power consumption: By providing shorter and more direct paths for data transfer, NoCs can reduce the chip’s overall power consumption. Efficient routing and switching mechanisms further contribute to power savings.
4. Improved performance: The ability to manage data traffic efficiently and minimize bottlenecks through routing algorithms enhances the overall performance of the SoC. NoCs can adapt to the varying bandwidth requirements of different IP blocks, providing optimized data transfer rates.
5. Quality of service (QoS): NoCs can support QoS features, ensuring that critical data transfers are given priority over less urgent communications. This is crucial for applications requiring high reliability and real-time processing.
6. Flexibility and customization: The flexibility and customization of the NoC architecture is largely due to its ability to employ a variety of routing algorithms based on specific design requirements and application scenarios.
7. Choice of routing algorithm: Routing algorithms in an NoC determine the network path of a packet from its source to its destination. The choice of routing algorithm can significantly impact the performance, efficiency, and fault recovery of the network.

NoC verification challenges

Designing an NoC and ensuring it works per specification is a formidable challenge. Power, performance, and area (PPA) optimizations—along with functional safety, security, and deadlock and livelock detection—add a significant chunk of extra verification work to functional verification, which is mostly centred on routing, data transport, data integrity, protocol verification, arbitration, and starvation checking.

Deadlocks and livelocks can cause a chip respin. For modern-day AI/ML chips, it can cost $25 million in some cases. Constrained random simulation techniques are not adequate for NoC verification. Moreover, simulation or emulation cannot provide any guarantees of correctness. So, formal methods rooted in proof-centric program reasoning are the only way of ensuring bug absence.

Formal verification to the rescue

Industrial-grade formal verification (FV) relies on using formal property verification (FPV) to perform program reasoning, whereby a requirement expressed using the formal syntax of System Verilog Assertions (SVA) is checked against the design model via an intelligent state-space search algorithm to conclude whether the intended requirement holds on all reachable states of the design.

The program reasoning effort terminates with either a proof or a disproof, generating counter-example waveforms. No stimulus is generated by human engineers, and the formal verification technology automatically generates almost an infinite set of stimuli only limited by the size of inputs. This aspect of verifying designs via proof without any human-driven stimulus and with almost an infinite set of stimuli is at the heart of formal verification.

It gives us the ability to pick corner-case issues in the design as well as pick nasty deadlocks and livelocks lurking in the design. Deep interactions in state space are examined quickly, revealing control-intensive issues in the design due to concurrent arbitration and routing traffic in the NoC.

With NoCs featuring numerous interconnected components operating in tandem, simulating the entire range of possible states and behaviors using constrained-random simulation becomes computationally burdensome and impractical. It is due to the intense effort needed for driving stimuli into the NoC that is needed to unravel the state-space interaction, which is not easily possible. This limitation undermines the reliability and precision of simulation outcomes.

Compelling advantages of NoC architectures tout the benefits of integrating FV into the design and verification process using easy-to-understand finite state machine notations and using protocol checkers developed for FV in chip and system integration testing increases confidence and aids error detection and isolation.

The effectiveness of this approach and the challenges of verifying complex systems with large state spaces are emphasized when compared to traditional system simulation successes.

An NoC formal verification methodology

In the complex process of chip design verification, achieving simplicity and efficiency amid complexity is the key. This journey is guided through syntactic and semantic simplification and innovative abstraction techniques.

In addition to these basic strategies, using invariants and an internal assumption assurance process further accelerates proof times, leveraging microarchitectural insights to bridge the gap between testbench and design under test (DUT). This complex verification dance is refined through case splitting and scenario reduction, breaking down complex interactions into manageable checks to ensure comprehensive coverage without overwhelming the verification process.

Symmetry reduction and structural decomposition address verification challenges arising from the complex behavior of large designs. These methods, along with inference-rule reduction and initial-value abstraction (IVA), provide a path that effectively covers every possible scenario, ensuring that even the most daunting designs can be confidently verified.

Rate flow and hopping techniques provide innovative solutions to manage the flow of messages and the complexity introduced by deep sequential states. Finally, black-box and cut-pointing techniques are employed to simplify the verification environment further, eliminating internal logic not directly subject to scrutiny and focusing verification efforts where they are most needed.

Through these sophisticated techniques, the goal of a thorough and efficient verification process becomes a tangible reality, demonstrating the state-of-the-art of modern chip design and verification methods.

Safeguarding NoCs against deadlocks

When setting up NoCs, it’s important for channels to be independent, but it’s not easy to ensure of this. Dependencies between channels can lead to troublesome deadlocks, where the entire system halts even if just one component fails.

Formal verification also contributes to fault tolerance, crucial in NoCs where numerous components communicate. When a component fails, it’s important to understand how close the system is to a permanent deadlock.

Formal verification exhaustively explores all possible system states, offering the best means to ensure fault tolerance. With the right approach, weaknesses of an NoC can be identified and addressed. Catching them early on can save the expensive respin.

Optimizing routing rules to suit the needs is common and critical for performance, but it can be tricky and hard to thoroughly test in simulation. Hundreds of new test cases may emerge just by introducing one new routing rule.

So, modelling all the optimizations in formal verification is crucial. If done properly, it can catch corner case bugs quickly or prove that optimizations behave as expected, preventing unexpected issues.

In the next section, we describe at a high level how some bugs can be caught with formal verification.

Formal verification case studies

Message dependence caused deadlock

A bug originated from a flaw in the flow control mechanism where both request and response packets shared the same FIFO. In this scenario, when multiple source ports initiate requests, the flow control method leads to a deadlock. For instance, when source port 0 sends a request reqs0, consisting of header flit h0req, body b0req, and tail t0req, it gets moved successfully.

Subsequently, the response resps0 made of (h1resp, b1resp, t1resp) intended also for source port 0 arrive, it causes no issue. However, when a subsequent request reqs2 from source port 2 with header flit h2req, body b2req, and tail t2req entered the FIFO, only its header and body move forward, but the tail is blocked from being sampled in the FIFO as the response’s header h2resp has blocked the tail t2req because they arrive in the same clock cycle.

Consequently, source port 2 was left waiting for the tail t2, and found itself blocked by the response header, resulting in a deadlock. Meanwhile, source port 1, also waiting for a response, would never get one, further exacerbating the deadlock situation. This deadlock scenario paralyzed the entire NoC grid, highlighting the critical flaw in the flow control mechanism.

Figure 2 Dependence between request and response causes deadlock. Source: Axiomise

Routing error caused deadlock

In the context of the previously mentioned flow control method, each source port awaits a response after sending a request. However, a deadlock arises due to a flaw in the routing function. When a request is mistakenly routed to an incorrect target port, triggering the assertion of the “wrong_dest” signal, the packet is discarded. Consequently, the source port remains in a state of deadlock, unable to proceed with further requests while awaiting a response that will never arrive.

Figure 3 A deadlock in the flow is caused by a routing error and is unable to proceed. Source: Axiomise

Redundant logic revealing PPA issues

Certain design choices in the routing algorithm, such as prohibiting-specific turns, lead to situations where several FIFOs never have push asserted, and some arbiters handle less than two requestors.

This has been identified during the verification process, revealing that these components—and consequently, millions of gates—are going unused in the design but still occupy chip area and, when clocked, would burn power while not contributing to any performance. Eliminating these superfluous gates significantly reduced manufacturing costs and improved design efficiency.

The case for formal verification in NoC

An NoC-based fabric is essential for any modern high-performance computing or AI/ML machine. NoCs enhance performance by efficient routing to avoid congestion. While NoCs are designed to be efficient at data transmission via routing, they often encounter deadlocks and livelocks in addition to the usual functional correctness challenges between source and destination nodes.

With a range of topologies possible for routing, directing simulation sequences to cover all possible source/destination pairs is almost impossible for dynamic simulation. Detecting deadlocks, starvation and livelocks is nearly impossible for any simulation or even emulation-based verification.

Formal methods drive an almost infinite amount of stimulus to cover all necessary pairs encountered in any topology. With the power of exhaustive proofs, we can establish conclusively that there isn’t a deadlock or a livelock or starvation with formal.

Editor’s Note: Axiomise published a whitepaper in 2022, summarizing a range of practically efficient formal verification techniques used for verifying high-performance NoCs.

Zifei Huang is a formal verification engineer at Axiomise, focusing on NoC and RISC-V architectures.

Adeel Liaquat is an engineering manager at Axiomise, specializing in formal verification methodologies.

Ashish Darbari is founder and CEO of Axiomise, a company offering training, consulting, services, and verification IP to various semiconductor firms.

Related Content

• Introduction to Formal Verification
• What is the future for Network-on-Chip?
• Interconnect (NoC) verification in SoC design
• How formal verification saves time in digital IP design
• Specifications: The hidden bargain for formal verification

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A generally accepted fact about relays and solenoids is that after they’re driven into the actuated state, only half as much coil voltage and therefore only one fourth as much coil power, are required to reliably sustain it. Consequently, any solenoid or relay driver that continuously applies the full initial actuation voltage to merely sustain is wastefully squandering four times as much power as the job requires.

The simplest and cheapest (partial) solution to this problem is shown in Figure 1.

 Figure 1 Basic driver circuit where C1 actuates, current-halving R1 sustains, then C1 discharges through R1 during Toff.

Wow the engineering world with your unique design: Design Ideas Submission Guide

But as is often true of “simple and cheap,” Figure 1’s solution suffers from some costs and complications.

1. While R1 successfully cuts sustaining current by half, it dissipates just as much power as the coil as it does so. Consequently, total sustaining power is ½ rather than ¼ of actuating power, so only half of the theoretical power savings are actually realized.
2. When the driver is turned off, a long recovery delay must be imposed prior to the next actuation pulse to allow C1 enough time to discharge through R1. Otherwise, the next actuation pulse will have inadequate amplitude and may fail. This effect is aggravated by the fact that, during actuation, C1 charges through the parallel combination of R1 and Rm, but during Toff it discharges through R1 alone. This makes recovery take twice as long as actuation.

Figure 2 presents a better performing, albeit less simple and cheap, solution that’s the subject of this Design Idea.

Figure 2 Q1 and Q2 cooperate with C to double VL for actuation, Q2 and D2 sustain, then Q3 rapidly discharges C through R to quickly recover for the next cycle.

Actuation begins with a positive pulse at the input, turning Q1 on which drives the bottom end of the coil to -VL and turns on Q2 which pulls the top end of the coil to +VL. Thus, 2VL appears across the coil, insuring reliable actuation. As C charging completes, Schottky diode D2 takes over conduction from Q1. This cuts the sustaining voltage to ½ the actuation value, and therefore drops sustaining power to ¼.

At the end of the cycle when the incoming signal returns to V0, Q3 turns on, initiating a rapid discharge of C through D2 and R. In fact, recovery can easily be arranged to complete in less time than the relay or solenoid needs to drop out. Then no explicit inter-cycle delay is necessary and recovery time is therefore effectively zero!

Moral: You get what you pay for!

But what happens if even doubling the VL logic rail still doesn’t make enough voltage to drive the coil and a higher supply rail is needed? 

Figure 3 addresses that issue with some trickery described in an earlier Design Idea: Driving CMOS totem poles with logic signals, AC coupling, and grounded gates.

 

Figure 3 Level shifting Q4, R1, and R2 are added to accommodate ++V > VL.

 Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Driving CMOS totem poles with logic signals, AC coupling, and grounded gates
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• Solenoid-protection circuit limits duty cycle
• Simple solenoid driver is adaptable and efficient

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At a time when scalable high-bandwidth and low-latency connectivity is becoming critical for artificial intelligence (AI) clusters, the new 400G PCIe Gen 5.0 Ethernet adapter chips aim to resolve connectivity bottlenecks in AI data centers.

Broadcom claims its 400G PCIe Gen 5.0 chips are the first Ethernet adapters built with 5-nm process technology. “We recognize the significance of fostering a power-efficient and highly connected data center for AI ecosystem,” said Jas Tremblay, VP and GM of the Data Center Solutions Group at Broadcom.

The 400G PCIe Gen 5.0 Ethernet adapters deliver higher rack density by driving passive copper cables up to five meters. Moreover, these Ethernet adapters employ low-latency congestion control technology and innovative telemetry features while equipped with a third-generation RDMA over Converged Ethernet (RoCE) pipeline.

These Ethernet adapters are built on Broadcom’s sixth-generation hardened network interface card (NIC) architecture. Their software is designed to be vendor agnostic; it supports a broad ecosystem of CPUs, GPUs, PCIe and Ethernet switches using open PCIe and Ethernet standards.

Ethernet adapter chips must resolve connectivity bottlenecks as cluster sizes grow rapidly in AI data centers. Source: Broadcom

According to Patrick Moorhead, chief analyst at Moor Insights and Strategy, as the industry races to deliver generative AI at scale, the immense volumes of data that must be processed to train large language models (LLMs) require even larger server clusters. He added that Ethernet presents a compelling case as the networking technology of choice for next-generation AI workloads.

AI-centric applications are reshaping the data center networking landscape, and Broadcom’s new 400G PCIe Gen 5.0 Ethernet adapters highlight the crucial importance of devices operating in the high-bandwidth, high-stress network environment that characterizes AI infrastructure.

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The MXO 5C series of low-profile oscilloscopes from R&S provides a bandwidth of up to 2 GHz and either four or eight channels. Although they lack displays, the rack-mount scopes deliver the same performance as the MXO 5 series, while occupying only a quarter of the vertical height (3.5 inches or 8.9 cm).

Built with two in-house ASICs for fast response, the MXO 5C delivers an acquisition capture rate of up to 4.5 million waveforms per second. It also features a 12-bit ADC with a high-definition mode that increases vertical resolution to 18 bits. A small front-panel E-ink display shows key information, such as IP address, firmware version, and connectivity status.

Four-channel models offer bandwidths of 350 MHz, 500 MHz, 1 GHz, and 2 GHz. Eight-channel models provide the same bandwidths, with the addition of 100 MHz and 200 MHz options. Standard acquisition memory of 500 Mpoints per channel can be optionally upgraded to 1 Gpoint per channel.

Although tailored for rack-mount applications, the MXO 5C oscilloscopes can also be used on a bench by connecting an external display via their HDMI or DisplayPort interfaces. Other connectivity interfaces include two USB 3.0 and one 1-Gbit LAN.

The MXO 5C series oscilloscopes are now available from R&S and select distribution channel partners.

MXO 5C series product page

Rohde & Schwarz 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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A single-chip inverse cable equalizer, the QPC7330 from Qorvo allows CATV operators to upgrade their hybrid fiber coax (HFC) networks to DOCSIS 4.0. The QPC7330 streamlines field installation by eliminating the need for plug-ins or complicated circuitry to implement the input cable simulation function. Programmed through an I2C interface, the device seamlessly integrates into the automated setup routine.

The function of the QPC7330 75-Ω inverse cable equalizer is to flatten out an input signal with too much uptilt in a line extender or system amplifier. It features 25 states to simulate the loss of different lengths of coaxial cable, offering tilt adjustments from 1 dB to 24 dB (measured from 108 MHz to 1794 MHz). The device integrates all equalizer functions, including a low-loss bypass mode, into a 10×14-mm laminate over-mold module.

The QPC7330 inverse cable equalizer is sampling now, with production quantities available in August 2024.

QPC7330 product page

Qorvo

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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ST’s A6983 step-down synchronous DC/DC converters provide space savings in light-load, low-noise, and isolated automotive applications. The series offers flexible design choices, including six non-isolated step-down converters in low-power and low-noise configurations, plus one isolated buck converter. With compensation circuitry on-chip, these devices help minimize both size and design complexity.

Non-isolated A6983 converters supply a load current up to 3 A and achieve 88% typical efficiency at full load. Low-power variants minimize drain on the vehicle battery in applications that remain active when parked. Low-noise types operate with constant switching frequency and reduce output ripple across the load range. These devices offer a choice of 3.3-V, 5.0-V, and adjustable output voltage.

The A6983I is a 10-W isolated buck converter with primary-side regulation that eliminates the need for an optocoupler. It allows accurate adjustment of the primary output voltage, while the transformer turns ratio determines the secondary voltage.

All of the AEC-Q100 qualified converters have a quiescent operating current of 25 µA and a power-saving mode that draws less than 2 µA. Input voltage ranges from 3.5 V to 38 V, with load-dump tolerance up to 40 V.

The converters come in 3×3-mm QFN16 packages. Prices start at $1.75 and $1.81 for the A6983 and A6983I, respectively, in lots of 1000 units. Free samples are available from the ST eStore.

A6983 product page

A6983I product page

STMicroelectronics

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The Melexis MLX90427 magnetic position sensor is intended for applications requiring high automotive functional safety levels, such as steer-by-wire systems. It provides stray field immunity and EMC robustness, as well as SPI output. Additionally, the device transitions seamlessly between four operating modes, including rotary, joystick, rotary with stray field immunity, and raw data.

At the heart of the MLX90427 is a Triaxis Hall magnetic sensing element that is sensitive to three components of flux density (BX, BY, and BZ) applied to the IC. This allows the sensor to detect movement of any magnet in its vicinity. The part also integrates an ADC, DSP, and output stage driver for SPI signal output.

In addition to AEC-Q100 Grade 0 qualification, the MLX90427 is SEooC ASIL C ready in accordance with ISO 26262 and can be integrated into automotive safety-related systems up to ASIL D. To simplify system integration, the sensor is compatible with 3.3-V and 5-V designs and operates over a temperature range of -40°C to +160°C. Self-diagnostics are built in to ensure swift fault reporting.

The MLX90427 position sensor comes in an 8-pin SOIC package. A fully redundant dual-die variant in a 16-pin TSSOP is due to launch in Q4 2024.

MLX90427 product page

Melexis

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Murata’s L Cancel Transformer (LCT) neutralizes the equivalent series inductance (ESL) of a capacitor to optimize its noise-reducing capabilities. Leveraging nonmagnetic ceramic multilayer technology, the LCT improves power supply noise suppression, while cutting component count.

The LCT component suppresses harmonic noise in power lines within a frequency range of a few MHz to 1 GHz. It achieves this by using negative mutual inductance to lower a capacitor’s ESL, thereby increasing the capacitor’s noise-reduction effectiveness. Murata states that the LCT also significantly reduces the number capacitors required in a power supply noise-reduction circuit design.

Operating at temperatures up to 125°C, the LCT ensures stable negative inductance and low DC resistance of 55 mΩ maximum. Rated current is 3 A maximum. The part is suitable for a wide range of consumer, industrial, and healthcare products. Dimensions of the surface-mount device are just 2.0×1.25×0.95 mm.

The L Cancel Transformer, part number LXLC21HN0N9C0L, is entering production. Samples are available now.

LCT product page

Murata

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Open radio access network (O-RAN) technology is driving the mobile communication industry toward an open, virtualized, and disaggregated architecture. O-RAN breaks traditional hardware-centric RANs into building blocks—radios, hardware, and virtualized functions—enabling mobile network operators to create their RANs using a multivendor, interoperable, and autonomous supply ecosystem. Using open and standardized interfaces, O-RAN enables network vendors to focus on specific building blocks rather than creating an entire RAN. Similarly, operators can mix and match components from multiple vendors. While O-RAN delivers many improvements, energy efficiency is a top priority.

Energy efficiency in RAN

Global efforts toward a carbon-neutral future and consumer demand for greener products have increased the urgency to focus on energy efficiency. Sustainability is a critical priority for the information and communications technology (ICT) industry, which is committed to making 6G and 5G a green reality.

Three key performance indicators define objectives and characterize improvements for a RAN energy optimization effort:

• Energy consumption (EC) represents the energy used to power the infrastructure. The European Telecommunications Standards Institute (ETSI) ES 202 706-1 defines EC as the integral of power consumption.
• Energy savings (ES) represents the reduction of energy consumed with minimal impact on the quality of service (QoS).
• Energy efficiency (EE) refers, in a general sense, to a measure of how an appliance or system uses energy. EE is the ratio between useful output or service over the required energy input.

These three factors are essential to consider. EE improvement strategies aim to apply several mechanisms when there is no need for all the available performance, thereby minimizing the impact on QoS and the user experience. Engineers need a balanced approach depending on QoS goals. They must make insightful measurements to understand power consumption rates for different load conditions and metrics.

Energy efficiency in O-RAN

The ETSI ES 203 228 test specification considers the gNodeB as a whole. However, the O-RAN Alliance® recognizes the urgency of addressing EE and EC in a disaggregated RAN. For example, the initial version of the O-RAN fronthaul interface specification included signaling mechanisms to notify the radio unit about periods of non-usage of radio symbols. These signaling mechanisms enabled the radio to halt transmission and conserve power. The fronthaul interface now provides the capability to inform the network about energy-saving capabilities in each radio, such as carrier deactivation, enabling automated activation and deactivation of energy-saving mechanisms. The O-RAN Alliance is also developing energy-saving test cases to ensure conformance and enhance vendor interoperability.

As shown in Figure 1, energy consumption spans the entire network, including the grid, RAN, core, and transport, depending on many parameters: from RF channels to topology. Therefore, energy consumption requires a comprehensive approach involving multiple parts of an operator’s organization to capture all components. Test engineers must consider and tweak numerous parameters and variables to identify optimal configurations. The main question remains: How can test engineers reduce energy consumption and costs without impacting QoS?

Figure 1 O-RAN architecture with user equipment (UE) and core network. Source: Keysight

 Reducing energy consumption and cost without impacting QoS  1. Reducing energy consumption

There are numerous techniques to reduce EC at a network level, each requiring varying levels of effort for implementation. Migrating technology from legacy platforms onto the most recent and energy-efficient platforms can immediately reduce network energy consumption. Such a migration requires an upfront investment in new equipment and resources to perform the upgrade, but it is a relatively low engineering effort. If investing in equipment upgrades is not possible, analyzing existing deployments, eliminating redundancies, and identifying overprovisioned devices helps improve energy consumption.

While it requires a mix of engineering and equipment investments, network topology optimization can also help reduce EC by determining the ideal minimum subset of equipment necessary to cover different topologies without sacrificing the QoS.

2. Optimizing energy efficiency

To maximize energy efficiency, engineers must continuously adapt user demand to the supply of network resources. They need to dynamically allocate the correct number of computing services and radio resources to match demand and aggregate user demand to ensure the entire use of each resource. For example, engineers can avoid using two servers at 50% load each. By applying the methodology at various levels, from the system to the device/chipset levels, engineers can optimize EE.

System-level intelligence is another way to maximize EE by performing dynamic resource allocation decisions at the system level. Engineers would activate or turn off nodes on wireless networks and perform load balancing to redirect users to active nodes. Similarly, they can allocate resources to the device hardware and chipset level.

Semiconductors and chipsets are the first elements of the energy chain. Hence, they are the main contributors to energy consumption and efficiency. New chipset generations provide advanced resource optimization capabilities, such as turning on or off discrete digital resources on the chip. Engineers can accomplish this mechanism by changing analog parameters (clock speed and bandwidth) to adjust the desired performance level and reduce power consumption since the energy is a function of electrical transitions in each gate.

At the radio level, engineers can perform additional optimization with innovative scheduling capabilities in the O-RAN distributed unit when traffic is low. They can regroup physical resource blocks (PRBs) from multiple symbols into a reduced number and augment the transmission blanking time.

Optimizing EE requires using chipset-level power-saving capabilities to the fullest extent possible. Only then can engineers determine the hosting of the power decision entity to prevent conflicts.

3. Standardization

The emergence of standardized O-RAN drives the need to define standards that enable intelligent control and energy optimization of multivendor-based networks. Ultimately, the Alliance’s work will result in new O-RAN specifications and technical reports sections. The Alliance’s ongoing work includes defining procedures, methodology, use cases, and test case definitions for cell/carrier switch on/off, RF channel selection, advanced sleep modes, and cloud resource management.

4. Embedded and chipset-based energy optimization

Intelligent control loops significantly contribute to energy optimization at the system level. But these loops are also appropriate at the chipset level as they contribute to local power optimization within a device.

Chipset sleep mode mechanisms consist of deactivating or slowing down function within a specified period. Different sleep levels enable multiple levels of energy saving.

However, each sleep mode comes at a cost: the deeper the sleep and energy-saving, the more time the chipset remains in the sleep mode and the wake-up transitions. These transitions are not energy-efficient and may offset gains from the sleep phase. Therefore, defining sleep strategies optimizes the trade-off between transitions and sleep phases.

How to Measure and evaluate the energy efficiency of O-RAN components

Figure 2 shows an O-RAN architecture which consists of the following components:

• O-RAN radio unit (O-RU) for processing the lower part of the physical layer
• O-RAN distributed unit (O-DU) for baseband processing, scheduling, radio link control, medium access control, and the upper part of the physical layer
• O-RAN central unit (O-CU) for the packet data convergence protocol layer
• O-RAN intelligent controller to gather information from the network and perform the necessary optimization tasks

Figure 2 An overview of O-RAN architecture with the O-RU for processing the lower part of the PHY layer, O-DU for processing the upper part of the PHY layer, O-CU for the packet data convergence protocol layer, and an O-RAN intelligent controller to perform optimization. Source: Keysight

Energy plane testing requires a cross-domain measurement system and cross-correlation of the data to gain meaningful insights into the energy performance of the RAN components. The testing combines power measurement with protocol and RF domains. As O-RAN and the 3rd Generation Partnership Project (3GPP) are fast-evolving standards, equipment manufacturers must ensure product compliance with the latest versions. Automation of the test cases and report generation are the keys to ensuring compatibility with the latest standards of regression testing.

Measure the energy efficiency of an O-RU

RAN energy consumption and efficiency improvement requires minimizing power usage while maximizing performance. For RU testing, the ETSI ES 202 706 standard, which describes the test methodology to measure power consumption in a gNodeB, can be adapted to make similar measurements in an O-RU under different load conditions, representing a typical day in the life of a RU—the load changes during the test in low, medium, high, and complete steps (Figure 3). So, by measuring the O-RU at different loads, we can calculate the total energy consumed.

Figure 3 Decoded constellation, signal spectrum, allocated PRBs, EVM per modulation type and decoded bits. Source: Keysight

To measure the energy efficiency of an O-RU, test engineers need an O-DU emulator, a DC power supply, and an RF power sensor (Figure 4). The O-DU emulator generates different static traffic levels from low, medium, busy, to full load traffic as defined by the ETSI ES 202 706-1 standard. A DC power supply provides power to the O-RU and measures the accumulated power consumption over time. The RF power sensor measures the output power at the antenna connector port. The ratio of output RF power to input DC power represents the energy efficiency measurement.

Figure 4 O-RU test set-up with an O-DU emulator, power sensor, as well as a power supply and analyzer. Source: Keysight

Measure the energy efficiency of O-CU/O-DU

Ensuring accurate and standardized EE of O-DU and O-CU in an O-RAN involves assessing various factors related to power consumption, resource utilization, and overall network performance. As EE is the ratio of delivered bits and consumed energy, test engineers need access to the user equipment (UE) throughput data to ensure that lower EC is not at the cost of lower quality of service. The fronthaul and backhaul interface require emulation to measure the EE of an O-DU and O-CU. In addition, test engineers must be able to simulate the traffic profiles of different pieces of UE.

The fronthaul requires an O-RU emulator to provide the interface to the O-DU. A UE emulator simulates the traffic flow to the O-RU emulator the UEs request. The backhaul requires a core emulator or a live core network. An AC or DC power supply capable of recording the output power measures the combined energy consumption of O-DU / O-CU. The ETSI specification does not refer to the disaggregated base station architecture, so the points of power measurement can vary depending on the implementation. The test software generates an energy efficiency report by simulating different UE traffic profiles with varying path loss, file size, and throughput.

Evaluate the performance of gNodeB

To test gNodeB, test engineers can use a set of automated test cases and analytics tools based on ETSI standards. The test setup should include a UE emulator, a core network emulator, and a power analyzer. The UE emulator emulates stateful UE traffic and measurements, while the core network emulator terminates the calls from the UE emulator for stateful O-DU/O-CU testing. Both emulators require dimensioning to load testing scenarios, and a power analyzer measures the server’s power consumption.

Energy efficient wireless networks

While the wireless communication industry increasingly prioritizes sustainability and net zero strategies, achieving energy efficiency has become as important as performance, reliability, and security. As wireless networks evolve into multivendor disaggregated systems, collaboration among chipsets, equipment, and test vendors is necessary to optimize power consumption without compromising performance.

Moving forward, test and measurement companies should focus on delivering cutting-edge technology and tools that accelerate the transition to green and sustainable wireless communications, realizing the network performance and capital expenditure (CapEx) advantages of O-RAN. To achieve that, understanding the energy performance of RAN components is key. As highlighted in this article, there are methodologies providing standardized and accurate assessments of energy efficiency in RAN components, essential for optimizing network performance while minimizing energy consumption in the increasingly dynamic and complex telecommunications landscape.

Chaimaa Aarab is a use case marketer focused on the wireless industry (5G, 6G, Wi-Fi 7, O-RAN) at Keysight Technologies. Her background is in electronics engineering with previous experience as a technical support engineer and market industry manager. 

 

 

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• 5G NR base stations bring new conformance testing challenges

The post Navigating energy efficiency in O-RAN architectures appeared first on EDN.

Junction field-effect transistors (JFETs) usually require some reverse bias voltage to be applied to a gate terminal.

In HF and UHF applications, this bias is often provided using the voltage across the source resistor Rs (Figure 1).

Figure 1: JFETs typically require some reverse bias across the gate terminal and in HF/UHF applications, this is often provided using the voltage across resistor Rs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Barring the evident lack of efficiency, such approach has other shortcomings as well:

• The drain current has statistical dispersion, so to get a target value of the current some circuit adjustment is required.
• The drain current may depend on temperature or power fluctuations.
• To achieve an acceptable low source impedance, several capacitors Cs have to be used.
• To maintain the same headroom a higher power voltage is required.
• The lack of direct contact with the ground plane means worse cooling of the transistor, which is crucial for power applications.

The circuit in Figure 2 is free of all these. It consists of a control loop which produces control voltage of negative polarity for n-channel JFET amplifier.

Figure 2: A control loop that produces control voltage of negative polarity for n-channel JFET amplifier in HF and UHF applications.

The circuit uses two infrared LEDs IR333C (diameter = 5 mm) in a self-made photocoupler. Two such LEDs placed face-to-face in an appropriate PVC tube about 12 mm long, that’s all. One such device produces 0.81 V @ Iled < 4 mA, which is quite sufficient for the HEMT FHX35LG, for example.

Of course, if you need higher voltage, several such devices can be simply cascaded.

The main amplification in the loop is performed by the JFET itself. Its value is about gm * R1, where gm is a transconductance of Q1.

The transistor pair Q2 and Q3 compares the voltage drops on the resistors R1 and R2 making them equal. Hence, by changing the ratio R2:R3 you can set the working point you need:

Id = Vdd * R2 / ((R2 + R3) * R1)

As we can see, the drain current (Id) still depends on power voltage (Vdd). To avoid this dependence, we can replace resistor R2 with a Zener diode, then:

Id = Vz / R1

 —Peter Demchenko studied math at the University of Vilnius and has worked in software development.

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The post Bias for HF JFET appeared first on EDN.

During electrical design process, certain design choices need to be made. One example is USB C type connector-based design with a straddle-mount connector. In such scenario, the overall PCB thickness is constrained while using a straddle-mount connector whose thickness governs the overall thickness. For historical reasons, the standard PCB thickness is 0.063” (1.57 mm).

Before the advent of PCBs, transistor-based electronics were often assembled using a method called breadboarding, which involved using wood as a substrate. However, wood was fragile, leading to delicate assemblies. To address this, bakelite sheets, commonly used on workbench surfaces, became the standard substrate for electronic assemblies, with a thickness of 1/16 inch, marking the beginning of PCBs at this thickness.

Figure 1 A PCB cross section is shown with a straddle-mount type connector. Source: Wurth Elektronik

Take the example of Wurth Elektronik’s USB 3.1 plug, a straddle-mount connector with part number 632712000011. The part datasheet recommends a PCB thickness of 0.8 mm/0.031” for an optimal use. This board thickness is common among various board fabrication houses. The 0.031” board is relatively easy to fabricate as many fab houses do a 6-layer PCB with 1 Oz copper on each layer.

However, designing and working with thin PCBs presents several challenges. One of the primary concerns is their mechanical fragility. Thin PCBs are more flexible and prone to bending or warping, making them difficult to handle during assembly and more susceptible to damage during handling. The handling includes pick and place assembly process, holes drilling, in-circuit testing (ICT) as well as functional probes during the functional testing.

The second level of handling is by the end user, for example dropping the device containing the PCB assembly (PCBA). Additionally, thin PCBs often requires specialized manufacturing processes and materials, leading to increased production costs. Component placement becomes more critical as well, as traces may need to be positioned closer together, increasing the risk of short circuits and signal interference.

Furthermore, thin PCBs face challenges in heat dissipation due to their reduced thermal mass. Addressing these challenges demands careful consideration during the design, manufacturing, and assembly stages to ensure the reliability and performance of the final product.

These issues are especially critical when a designer mounts a ball grid array (BGA) component on a 0.031” thickness board. Most of major fabrication houses recommend a minimum thickness of 0.062” when BGAs are mounted on the board.

How to test durability

The mechanical durability of PCB assemblies is generally assessed using a drop test. Drop test requirements for a PCBA typically include specifying the drop height, drop surface, number of drops, orientation during the drop, acceptance criteria, and testing standards. The drop height is the distance from which the PCBA will be dropped, typically ranging from 30 to 48 inches, depending on the application and industry standards.

The drop surface, such as concrete or wood, is also defined. Manufacturers determine the number of drops the PCBA must withstand, usually between 3 to 6 drops. The orientation of the PCBA during the drop, whether face down, face up, or on an edge or corner, is also specified. Acceptance criteria, such as functionality after the drop and any visible damage, are clearly defined.

Testing standards like IPC-TM-650 or specific customer requirements guide the testing process. For a medical device, the drop test requirements are governed by section 15.3.4.1 of IEC 60601-1 Third Edition 2005-12. By establishing these requirements, manufacturers ensure that their PCBAs and products are robust enough to withstand real-world use and maintain functionality even after being subjected to drops and impacts.

The soldering joint might not be captured during a drop test until a functional failure is observed. The BGA can fail due to poor assembly-related issues like the thermal stresses during soldering or poor soldering joint quality. A thin board weakens due to excessive mechanical shock and vibration assembly.

These defects can be captured during a drop test as the BGA part may not withstand the stresses encountered during a drop test, as shown in the figures below. The BGA failures can be inspected using X-ray, optical inspection, or electrical testing. A detailed analysis may be performed using cross section analysis using scanning electron microscopy (SEM).

Figure 2 The BGA solder joint shows a line crack. Source: Keyence

Figure 3 The above image displays a cross section of a healthy BGA. Source: Keyence

Figure 4 Here is a view of some of the BGA failure modes. Source: Semlabs

How to fix BGA failure on thin PCBs

Pad cratering is the fracturing of laminate under Cu pads of surface mount components, which often occurs during mechanical events. The initial crack can propagate, causing electrically open circuits by affecting adjacent Cu conducting lines. It’s more common in lead-free assemblies due to different laminate materials. Mitigation involves reducing stress on the laminate or using stronger, more pad cratering-resistant materials.

The issue can be fixed by mechanically stretching the PCB or changing the laminate material. It can be done with any of the following steps.

• Thinner boards are more prone to warping and may require additional fixturing (stiffeners or work board holders) to process on the manufacturing line if the requirements below are not met. A PCB stiffener is not an integral part of the circuit board; rather, it’s an external structure that offers mechanical support to the board.

Figure 5 An aluminum bar is shown as a mechanical PCB stiffener. Source: Compufab

• Corner adhesive/epoxy on the BGA corners or use BGA underfill. For example, an adhesive that can be used for this purpose is Zymet UA-3307-B Edgebond, Korapox 558 or Eccobond 286. The epoxy along the BGA corners or as an underfill strengthens the PCB, thereby preventing PCB flexion and hence the failure.
• Strict limitations on board flexure during circuit board assembly operations. For instance, supporting the PCB during handling operation like via hole drilling, pick and place, ICT, or functional testing with flying probes.
• Matching the recommended soldering profile of the BGA. The issue can be made worse if the BGA manufacture’s recommended soldering profile is not followed, resulting in cold solder joints. There should be enough thermocouples on the PCB panel to monitor the PCB temperature.
• Ensure that the BGA pad size is as per manufactures recommendation.

Managing thin PCB challenges

A thin PCB (0.031”) can weaken the PCB assembly, thereby making it susceptible to mechanical and thermal forces. And the challenges are unique when mounting a BGA to the thin PCB.

However, the design challenges and risks can be managed by carefully controlling the PCB handling processes and then strengthening the thin PCB with design solutions discussed in this article.

Editor’s Note: The views expressed in the article are author’s personal opinion.

Jagbir Singh is a staff electrical engineer for robotics at Smith & Nephew.

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The post Thin PCBs: Challenges with BGA packages appeared first on EDN.

Starting last year, as I mentioned at writeup publication time, EDN asked me to do yearly coverage of Google’s (or is that Alphabet’s? whatevah) I/O developer conference, as I’d already long been doing for Apple’s WWDC developer-tailored equivalent event, and on top of my ongoing throughout-the-year coverage of notable Google product announcements:

• Smartphones and smartwatches and their Android O/S foundations
• Various form factor computing platforms and their Chrome OS origins
• New and evolved processor architectures for all of these plus “cloud” servers
• etc…

And, as I also covered extensively a year ago, AI ended up being the predominant focus of Google I/O’s 2023 edition. Here’s part of the upfront summary of last year’s premier event coverage (which in part explains the rationalization for the yearly coverage going forward):

Deep learning and other AI operations…unsurprisingly were a regularly repeated topic at Wednesday morning’s keynote and, more generally, throughout the multi-day event. Google has long internally developed various AI technologies and products based on them—the company invented the transformer (the “T” in “GPT”) deep learning model technique now commonly used in natural language processing, for example—but productizing those research projects gained further “code red” urgency when Microsoft, in investment partnership with OpenAI, added AI-based enhancements to its Bing search service, which competes with Google’s core business. AI promises, as I’ve written before, to revolutionize how applications and the functions they’re based on are developed, implemented and updated. So, Google’s ongoing work in this area should be of interest even if your company isn’t one of Google’s partners or customers.

And unsurprisingly, given Google’s oft-stated, at the time, substantial and longstanding planned investment in various AI technologies and products and services based on them, AI was again the predominant focus at this year’s event, which took place earlier today as I write these words, on Tuesday, May 14:

But I’m getting ahead of myself…

The Pixel 8a

Look back at Google’s Pixel smartphone family history and you’ll see a fairly consistent cadence:

• One or several new premium model(s) launched in the fall of a given year, followed by (beginning with the Pixel 3 generation, to be precise)
• one (or, with the Pixel 4, two) mainstream “a” variant(s) a few calendar quarters later

The “a” variants are generally quite similar to their high-end precursors, albeit with feature set subtractions and other tweaks reflective of their lower price points (along with Google’s ongoing desire to still turn a profit, therefore the lower associated bill of materials costs). And for the last several years, they’ve been unveiled at Google I/O, beginning with the Pixel 6a, the mainstream variant of the initial Pixel 6 generation based on Google-developed SoCs, which launched at the 2022 event edition. The company had canceled Google I/O in 2020 due to the looming pandemic, and 2021 was 100% virtual and was also (bad-pun-intended) plagued by ongoing supply chain issues, so mebbe they’d originally planned this cadence earlier? Dunno.

The new Pixel 8a continues this trend, at least from feature set foundation and optimization standpoints (thicker display bezels, less fancy-pants rear camera subsystem, etc.). And by the way, please put in proper perspective reviewers who say things like “why would I buy a Pixel 8a when I can get a Pixel 8 for around the same price?” They’re not only comparing apples to oranges; they’re also comparing old versus new fruit (this is not an allusion to Apple; that’s in the next paragraph). The Pixel 8 and 8 Pro launched seven months ago, and details on the Pixel 9 family successors are already beginning to leak. What you’re seeing are retailers promo-pricing Pixel 8s to clear out inventory, making room for Pixel 9 successors to come soon. And what these reviewers are doing is comparing them against brand-new list-price Pixel 8as. In a few months, order will once again be restored to the universe. That all said, to be clear, if you need a new phone now, the Pixel 8 is a compelling option.

But here’s the thing…this year, the Pixel 8a was unveiled a week prior to Google I/O, and even more notably, right on top of Apple’s most recent “Let Loose” product launch party. Why? I haven’t yet seen a straight answer from Google, so here are some guesses:

• It was an in-general attempt by Google to draw attention away from (or at least mute the enthusiasm for) Apple and its comparatively expensive (albeit non-phone) widgets
• Specifically, someone at Google had gotten a (mistaken) tip that Apple might roll out one (or a few) iPhone(s) at the event and decided to proactively queue up a counterpunch
• Google had so much else to announce at I/O this year that they, not wanting the Pixel 8a to get lost in all the noise, decided to unveil it ahead of time instead.
• They saw all the Pixel 8a leaks and figured “oh, what the heck, let’s just let ‘er rip”.

The Pixel Tablet (redux)

But that wasn’t the only thing that Google announced last week, on top of Apple’s news. And in this particular case the operative term is relaunched, and the presumed reasoning is, if anything, even more baffling. Go back to my year-back coverage, and you’ll see that Google launched the Tensor G2-based Pixel Tablet at $499 (128GB, 255GB for $100 more), complete with a stand that transforms it into an Amazon Echo Show-competing (and Nest Hub-succeeding) smart display:

Well, here’s the thing…Google relaunched the very same thing last week, at a lower price point ($399), but absent the stand in this particular variant instance (the stand-inclusive product option is still available at $499). It also doesn’t seem that you can subsequently buy the stand, more accurately described as a dock (since it also acts as a charger and embeds speakers that reportedly notably boost sound quality), separately. That all, said, the stand-inclusive Pixel Tablet is coincidentally (or not) on sale at Woot! for $379.99 as I type these words, so…

And what explains this relaunch? Well:

• Apple also unveiled tablets that same day last week, at much higher prices, so there’s the (more direct in this case, versus the Pixel 8a) competitive one-upmanship angle, and
• Maybe Google hopes there’s sustainable veracity to the reports that Android tablet shipments (goosed by lucrative trade-in discounts) are increasing at iPads’ detriment?

Please share your thoughts on Google’s last-week pre- and re-announcements in the comments.

OpenAI

Turnabout is fair play, it seems. Last Friday, rumors began circulating that OpenAI, the developer of the best-known GPT (generative pre-trained transformer) LLM (large language model), among others, was going to announce something on Monday, one day ahead of Google I/O. And given the supposed announcement’s chronological proximity to Google I/O, those rumors further hypothesized that perhaps OpenAI was specifically going to announce its own GPT-powered search engine as an alternative to Google’s famous (and lucrative) offering. OpenAI ended up in-advance denying the latter rumor twist, at least for the moment, but what did get announced was still (proactively, it turned out) Google-competitive, and with an interesting twist of its own.

To explain, I’ll reiterate another excerpt from my year-ago Google I/O 2023 coverage:

The way I look at AI is by splitting up the entire process into four main steps:

1. Input
2. Analysis and identification
3. Appropriate-response discernment, and
4. Output

Now a quote from the LLM-focused section of my 2023 year-end retrospective writeup:

LLMS’ speedy widespread acceptance, both as a generative AI input (and sometimes also output) mechanism and more generally as an AI-and-other interface scheme, isn’t a surprise…their popularity was a matter of when, not if. Natural language interaction is at the longstanding core of how we communicate with each other after all, and would therefore inherently be a preferable way to interact with computers and other systems (which Star Trek futuristically showcased more than a half-century ago). To wit, nearly a decade ago I was already pointing out that I was finding myself increasingly (and predominantly, in fact) talking to computers, phones, tablets, watches and other “smart” widgets in lieu of traditional tapping on screens and keyboards, and the like. That the intelligence that interprets and responds to my verbally uttered questions and comments is now deep learning trained and subsequent inferred versus traditionally algorithmic in nature is, simplistically speaking, just an (extremely effective in its end result, mind you) implementation nuance.

Here’s the thing: OpenAI’s GPT is inherently a text-trained therefore text-inferring deep learning model (steps 2 and 3 in my earlier quote), reflected in the name of the “ChatGPT” AI agent service based on it (later OpenAI GPT versions also support still image data). To speak to an LLM (step 1) as I described in the previous paragraph, for example, you need to front-end leverage another OpenAI model and associated service called Whisper. And for generative AI-based video from text (step 4) there’s another OpenAI model and service, back-end this time, called Sora.

Now for that “interesting twist” from OpenAI that I mentioned at the beginning of this section. In late April, a mysterious and powerful chatbot named “gpt2-chatbot” appeared on a LLM comparative evaluation forum, only to disappear shortly thereafter…and reappear again a week after that. Its name led some to deduce that it was a research project from OpenAI (further fueled by a cryptic social media post from CEO Sam Altman) —perhaps a potential successor to latest-generation GPT-4 Turbo—which had intentionally-or-not leaked into the public domain.

Turns out, we learned on Monday, it was a test-drive preview of now-public GPT-4o (“o” for “omni”), And not only does GPT-4o outperform OpenAI precursors as well as competitors, based on Chatbot Arena leaderboard results, it’s also increasingly multimodal, meaning that it’s been trained on and therefore comprehends additional input (as well as generating additional output) data types. In this case, it encompasses not only text and still images but also audio and vision (specifically, video). The results are very intriguing. For completeness, I should note that OpenAI also announced chatbot agent application variants for both MacOS and Windows on Monday, following up on the already-available Android and iOS/iPadOS versions.

Google Gemini

All of which leads us (finally) to today’s news, complete with the aforementioned 121 claimed utterances of “AI” (no, I don’t know how many times they said “Gemini”):

@verge Pretty sure Google is focusing on AI at this year’s I/O. #google #googleio #ai #tech #technews #techtok ♬ original sound – The Verge

Gemini is Google’s latest LLM, previewed a year ago, formally unveiled in late 2023 and notably enhanced this time around. Like OpenAI with GPT, Google’s deep learning efforts started out text-only with models such as LaMDA and PaLM; more recent Gemini has conversely been multimodal from the get-go. And pretty much everything Google talked about during today’s keynote (and will cover more comprehensively all week) is Gemini in origin, whether as-is or:

• Memory footprint and computational “muscle” fine-tuned for resource-constrained embedded systems, smartphones and such (Gemini Nano, for example), and/or
• Training dataset-tailored for application-specific use cases

including the Gemma open model variants.

In the interest of wordcount (pushing 2,000 as I type this), I’m not going to go through each of the Gemini-based services and other technologies and products announced today (and teased ahead of time, in Project Astro’s case) in detail; those sufficiently motivated can watch the earlier-embedded video (upfront warning: 2 hours), archived liveblogs and/or summaries (linked to more detailed pieces) for all the details. As usual, the demos were compelling, although it wasn’t entirely clear in some cases whether they were live or (as Google caught grief for a few months ago) prerecorded and edited. More generally, the degree of success in translating scripted and otherwise controlled-environment demo results into real-life robustness (absent hallucinations, please) is yet to be determined. Here are a few other tech tidbits:

• Google predictably (they do this every year) unveiled its sixth-generation TPU (Tensor Processing Unit) architecture, code-named Trillium, with a claimed 4.7x performance boost in compute performance per chip versus today’s 5th-generation precursor. Design enhancements to achieve this result include expanded (count? function? both? not clear) matrix multiply units, faster clock speeds, doubled memory bandwidth and the third-generation SparseCore, a “specialized accelerator for processing ultra-large embeddings common in advanced ranking and recommendation workloads,” with claimed benefits both in training throughput and subsequent inference latency.
• The company snuck a glimpse of some AR glasses (lab experiment? future-product prototype? not clear) into a demo. Google Glass 2, Revenge of the Glassholes, anyone?
• And I couldn’t help but notice that the company ran two full-page (and identical-content, to boot) ads for YouTube in today’s Wall Street Journal even though the service was barely mentioned in the keynote itself. Printing error? Google I/O-unrelated v-TikTok competitive advertising? Again, not clear.

And with that, my Google I/O coverage is finit for another year. Over to all of you for your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post The 2024 Google I/O: It’s (pretty much) all about AI progress, if you didn’t already guess appeared first on EDN.

A little more than a year after he took the reins of Intel’s ambitious bid for semiconductor contract manufacturing, Stuart Pann is retiring while handing over the charge to Kevin O’Buckley. The transition took place on Monday, 13 May, and it once more raised questions about the future viability of Intel’s third-party foundry business.

Pann, a 35-year company veteran, joined Intel during the heydays of the PC revolution in 1981. He returned to the Santa-Clara, California-based semiconductor firm in 2021 to lead the chip manufacturing division, Intel Foundry Services (IFS). He replaced Intel Foundry’s first chief, Randhir Thakur, who later became CEO and managing director of Tata Electronics, the electronics manufacturing arm of Indian conglomerate Tata Group.

Figure 1 Pann, currently in a support role for a smooth transition, will retire at the end of this month. Source: Intel

Now O’Buckley replaces Pann, and it’s a déjà vu of Thakur-to-Pann handover a year ago. For instance, during the first quarter of 2024, Intel Foundry reported revenue of $4.4 billion, which was down by $462 million compared to the first quarter of 2023. That’s mainly attributed to lower revenues from back-end services and product samples.

Pann—who left the company only a few months after Intel Foundry marked the official launch of the manufacturing business as an independent entity to compete with the likes of TSMC and Samsung—set up Intel’s IDM 2.0 Acceleration Office (IAO) to guide the implementation of an internal foundry model. IAO closely works with Intel’s business units to support the company’s internal foundry model.

Intel Foundry, which aims to move beyond traditional foundry offerings and establish itself as the world’s first open-system foundry, faces huge technical and commercial challenges. That includes combining wafer fabrication, advanced process and packaging technology, chiplet standards, software, and assembly and test capabilities in a unified semiconductor ecosystem.

O’Buckley inherits these challenges. He comes from Marvell, where he led the company’s custom chips business as senior VP for the Custom, Compute and Storage Group. O’Buckley came to Marvell in 2019 via its acquisition of Avera Semiconductor, a 1,000-person chip design company that traces its roots to IBM, which offloaded it to GlobalFoundries before it was sold to Marvell. O’Buckley led Avera’s divestiture from GlobalFoundries.

Figure 2 Like his predecessor, O’Buckley will report directly to CEO Pat Gelsinger. Source: Intel

Intel CEO Pat Gelsinger, who has bet Intel’s revival bid on setting up an independent fab business, acknowledges that Intel Foundry is still some distance away from profitability due to the large up-front investment needed to ramp it up. However, time isn’t on Gelsinger’s side, meaning a swift turnaround plan is in order for O’Buckley.

O’Buckley is an outsider, a plus at Intel, where employees are known to have stayed long years; his expertise in the custom chips business will also be an asset at Intel Foundry. Next, during his stint at IBM, he spearheaded the company’s development of 22- and 14-nm FinFET technologies. As Gelsinger puts it, he has a unique blend of expertise in both foundry and fabless companies.

Now comes the tough part, execution.

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The post Change of guard at Intel Foundry, again appeared first on EDN.

If we want to take samples of some analog waveform, as in doing analog to digital conversions at some particular conversion rate, there is an absolute lower limit to the rate of doing conversions versus the highest frequency component of the analog signal. That limit must not be violated if the sampling process is to yield valid results. We do not want to encounter the phenomenon called “aliasing”.

The term “aliasing” as we use it here has nothing to do with spy thrillers or crime novels. Aliasing is an unwanted effect that can arise when some analog waveform is being sampled for its instantaneous values at regular time intervals that are longer than half the reciprocal of a sampling frequency. If we were to sample some waveform once every microsecond, the sampling interval is half of that one microsecond for which we would have a sampling frequency limit of 2 MHz or faster.

Aliasing will occur if the sampled waveform has frequency component(s) that are greater in frequency than 50% of the sampling frequency. To turn that statement around, aliasing will occur if the sampling frequency is too low. Aliasing will occur at any sampling rate that is lower than twice the highest frequency component of the waveform being sampled.

The next question is: Why?

The late comedian Professor Irwin Corey once posed a similar question: “Why is the sky blue?” His answer was something like “This is a question which must be taken in two parts. The first part is ‘Why?’ ‘Why’ is a question Man has asked since the beginning of time. Why? I don’t know. The second part is ‘Is the sky blue?’ The answer is ‘Yes!'”

Fortunately, we can do a little better than that as follows.

The sampling process can be thought of as multiplying the waveform being sampled by a very narrow duty cycle pulse waveform of zero value for most of the time and of unity value for the very narrow sampling time interval. That sampling waveform will be rich in harmonics. There will be a spectral line at the sampling frequency itself plus spectral lines at each of the sampling frequency’s harmonics as well. Each spectral line will have sidebands as shown in Figure 1 which will extend from those sampling frequency spectral lines up and down the frequency spectrum in keeping with the sampled waveform’s bandwidth.

Figure 1 Sampling versus aliasing where spectral line will have sidebands that will extend from those sampling frequency spectral lines up and down the frequency spectrum in keeping with the sampled waveform’s bandwidth.

The sampling waveform is amplitude modulated by the sampled waveform and so I’ve chosen to call that sampled waveform’s highest frequency component, Fmod. Each bandwidth is 2 * Fmod.

If the sampling frequency is high enough as with Fs1, the illustrated sidebands do not overlap. There is a respectable guard band between them, and no aliasing occurs.

If the sampling frequency starts getting lower as with Fs2, the sidebands start getting closer together and there is a less comfortable, if I may use that word, guard band.

If the sampling frequency gets too low as with Fs3 which is less than twice Fmod, the sidebands overlap, and we have aliasing. Sampling integrity is lost. The sampled waveform cannot be reconstructed from the undersampled output of this now unsatisfactory system.

Consider this an homage to Claude Shannon (April 30, 1916 – February 24, 2001) and his sampling theory.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Sampling and aliasing appeared first on EDN.

Self-heated transistors used as thermal air flow sensors are a particular (obsessive?) interest of mine, and over the years I must have designed dozens of variations on this theme. Figure 1 illustrates one such topology seen here before. It connects two transistors in a Darlington pair with Q2 serving as an unheated ambient thermometer and Q1 as the self-heated airflow sensor. Reference amplifier A1 and current sense resistor R3 regulate a constant 67 mA = heating current = 333 mW @ 5 V heating power.

Figure 1 Typical self-heated transistor thermal airflow sensor.

Wow the engineering world with your unique design: Design Ideas Submission Guide

This heat input raises Q1’s temperature above ambient by 64oC at 0 fpm air speed, cooling to 24oC at 1000 fpm as shown in Figure 2.

 Figure 2 Thermal sensor temperature versus air speed.

As shown in Figure 2, the relationship between the airspeed and cooling of the self-heated transistor sensor is highly nonlinear. This is an inherent characteristic of such sensors and causes the sensor temperature versus air speed signal to be equally nonlinear. Consequently, even relatively small power supply instabilities, that translate % for % into instability in sensor temperature rise, can create surprisingly large airspeed measurement errors.

Clearly, anything less than perfect power supply stability can make this a problem.

But Figure 3 offers a surprisingly simple and inexpensive fix consisting of just two added resistors: R7 and R8.

Figure 3 Added R7 and R8 establish an instability-cancelling relationship between heating voltage V and heating current I.

The added Rs sum feedback from current sensing R3 with heating voltage source V. Summation happens in a ratio such that a percentage increase in V produces an equal and opposite percentage decrease in current I, and vice versa. The result is shown graphically in Figure 4.

Note the null (inflection) point at 5 V where heating is perfectly independent of voltage.

Figure 4: Sensor temperature versus supply voltage where: Blue = heating voltage V and (uncorrected) power; Red = heating current I; and Black = I*V = heating power / temperature.

Here’s the same thing in simple nullification math:

 I = (0.2 – V*R8/R7)/R3 = (0.2 – 0.02V)/R3
H = I*V = (0.2V – 0.02V2)/R3
dH/dV = (0.2 – 0.04V)/R3 = (0.2 – 0.2)/R3 = 0 @ V = 5 volts
dH = -0.01% @ V = 5 volts ±1%

Note the 200:1 stability improvement that attenuates a ±1% variation in V down to only -0.01% variation in heating power and therefore temperature.

Problem solved. Cheaply!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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The post Cancel thermal airflow sensor PSRR with just two resistors appeared first on EDN.

As Rohm Semiconductor deepens its ties with Toshiba Electronic Devices & Storage, industry watchers wonder if Rohm is getting closer to acquiring Toshiba’s power chips business. It all began late last year when the two companies announced a joint investment of $2.7 billion to collaborate on manufacturing power electronics devices.

But what made this news more noteworthy was that the announcement followed Rohm’s becoming part of a private equity group that was planning to take Toshiba private. However, when the two companies joined hands to boost the volume production of power devices, they stated that they had been considering this collaboration for some time and that it wasn’t a starting point in Rohm acquiring Toshiba’s power semiconductors business.

There is a third player in this $2.7 billion investment plan: the Japanese government, which adds another dimension to this hookup between Rohm and Toshiba Electronic Devices & Storage. Japan, aiming to strengthen the resilience of its semiconductor supply chains, recognises the strategic importance of power electronics and wants to double the power chip production in the country.

Moreover, Japan sees the local power chip industry as too fragmented, which makes it hard for them to compete with companies like Infineon. So, the Japanese government will subsidize one-third of this $2.7 billion investment in power semiconductor production on part of Rohm and Toshiba.

A closer look at this dimension also adds merits to the possibility of Rohm subsequently acquiring Toshiba’s power semiconductors business. It’s worth mentioning that Rohm was the first company to mass produce silicon carbide (SiC) MOSFETs, and it’s been continuously investing in this wideband gap (WBG) technology since then.

Figure 1 The Miyazaki Plant No. 2, based on assets acquired from Solar Frontier in July 2023, is dedicated to manufacturing SiC power devices. Source: Rohm

In the $2.7 billion joint investment plan announced late last year, Rohm will invest ¥289.2 billion in its new plant in Kunitomi, Miyazaki Prefecture, to produce SiC power chips. Toshiba will invest ¥99.1 billion in its newly built 300-mm fab in Nomi, Ishikawa Prefecture, to produce silicon-based power chips.

After delisting late last year, Toshiba faces an uncertain future. However, it still possesses highly valuable assets, and its power electronics business is one of them. There has also been chatter about splitting Toshiba into three units.

Figure 2 Vehicle electrification and automation of industrial equipment have led to strong demand for power devices like MOSFETs and IGBTs at 300-mm fab in Nomi. Source: Toshiba

When you see this potential divesture in the wake Japan’s desire to have a power electronics company that can compete with the likes of Infineon, Rohm taking over Toshiba’s power semiconductors business seems like a no-brainer. Among Japan’s current power chip firms, Rohm is known to have a stable power electronics business.

And the company is keen to affirm its management vision: “We focus on power and analog solutions and solve social problems by contributing to our customers’ needs for energy savings and miniaturization of their products.” Given this backdrop, Rohm taking over Toshiba Electronic Devices & Storage is probably a matter of time.

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The emerging technology of Wi-Fi sensing promises significant benefits for a variety of embedded and edge systems. Using only the radio signals already generated by Wi-Fi interfaces under normal operation, Wi-Fi sensing can theoretically enable an embedded device to detect the presence of humans, estimate their motion, approximate their location, and even sense gestures and subtle movements, such as breathing and heartbeats.

Smart home, entertainment, security, and safety systems can all benefit from this ability. For example, a small sensor in a car could detect the presence of back-seat passengers—soon to be a requirement in new passenger vehicles. It can even detect a child breathing under a blanket as it does not require line of sight. Or an inexpensive wireless monitor in a home could detect in a room or through walls when a person falls—a lifesaver in home-care situations.

Figure 1 Wi-Fi Sensing can be performed on any Wi-Fi-enabled device with the right balance of power consumption and processing performance. Source: Synaptics

Until recently, such sensing could only be done with a passive RF receiver relying on the processing capability of a nearby Wi-Fi access point. Now, it can be done on every Wi-Fi-enabled end device. This article explores how designers can get from theory to shipped product.

How it works

The elegance of Wi-Fi sensing is that it uses what’s already there: the RF signals that Wi-Fi devices use to communicate. In principle, a Wi-Fi receiving device could detect changes in those RF signals as it receives them and, from the changes, infer the presence, motion, and location of a human in the area around the receiver.

Early attempts to do this used the Wi-Fi interface’s receive signal strength indicator (RSSI), a number produced by the interface periodically to indicate the average received signal strength. In much the same way that a passive infrared motion detector interprets a change in IR intensity as motion near its sensor, these Wi-Fi sensors interpret a change in RSSI value as the appearance or motion of an object near the receiver.

For instance, a person could block the signal by stepping between the receiver and the access point’s transmitter, or a passing person could alter the multipath mix arriving at the receiver.

RSSI is unstable in the real world, even when no one is nearby. It can be challenging to separate the influences of noise, transmitter gain changes, and many other sources from the actual appearance of a person.

This has led researchers to move to a richer, more frequently updated, and more stable data stream. With the advent of multiple antennas and many subcarrier frequencies, transmitters and receivers need far more information than just RSSI to optimize antenna use and subcarrier allocation. Their solution is to take advantage of channel state information (CSI) in the 802.11n standard. This should be available from any compliant receiver, though the accuracy may vary.

Figure 2 Wi-Fi system-on-chips (SoCs) can analyze CSI for subtle changes in the channel through which the signal is propagating to detect presence, motion, and gestures. Source: Synaptics

CSI is reported by the receiver every time a subcarrier is activated. It is essentially a matrix of complex numbers, each element conveying magnitude and phase for one combination of transmit and receive antennas. A three-transmit-antenna, two-receive-antenna channel would be a 3 x 2 array. The receiver generates a new matrix for each subcarrier activation. So, in total, the receiver maintains a matrix for each active subcarrier.

The CSI captures far more information than the RSSI, including attenuation and phase shift for each path and frequency. In principle, all this data contains a wealth of information about the environment around the transmitter and receiver. In practice, technical papers have reported accurate inference of human test subjects’ presence, location, motion, and gestures by analyzing changes in the CSI.

Capturing presence data

Any compliant Wi-Fi interface should produce the CSI data stream. That part is easy. However, it is the job of the sensor system to process the data and make inferences from it. This process is generally divided into three stages, following the conventions developed for video image processing: data preparation, feature extraction, and classification.

The first challenge is data preparation. While the CSI is far more stable than the RSSI, it’s still noisy, mainly due to interference from nearby transmitters. The trick is to remove the noise without smoothing away the sometimes-subtle changes in magnitude or phase that the next stage will depend upon to extract features. But how to do this depends on the extraction algorithms and, ultimately, the classification algorithms and what is being sensed.

Some preparation algorithms may simply lump the CSI data into time bins, toss out outliers, and look for changes in amplitude. Others may attempt to extract and amplify elusive changes in phase relationships across the subcarriers. So, data preparation can be anything from a simple time-series filter to a demanding statistical algorithm.

Analysis and inference

The next stage in the pipeline will analyze the cleansed data streams to extract features. This process is analogous—up to a point—to feature extraction in vision processing. In practice, it is quite different. Vision processing may, for instance, use simple numerical calculations on pixels to identify edges and surfaces in an image and then infer that a surface surrounded by edges is an object.

But Wi-Fi sensors are not working with images. They are getting streams of magnitude and phase data that are not related in any obvious way to the shapes of objects in the room. Wi-Fi sensors must extract features that are not images of objects but are instead anomalies in the data streams that are both persistent and correlated enough to indicate a significant change in the environment.

As a result, the extraction algorithms will not simply manipulate pixels but will instead perform complex statistical analysis. The output of the extraction stage will be a simplified representation of the CSI data, showing only anomalies that the algorithms determine to be significant features of the data.

The final stage in the pipeline is classification. This is where the Wi-Fi sensor attempts to interpret the anomaly reported by the extraction stage. Interpretation may be a simple binary decision: is there a person in the room now? Is the person standing or sitting? Are they falling?

Or it may be a more quantitative evaluation: where is the person? What is their velocity vector? Or it may be an almost qualitative judgment: is the person making a recognizable gesture? Are they breathing?

The nature of the decision will determine the classification algorithm. Usually, there is no obvious, predictable connection between a person standing in the room and the resulting shift in CSI data. So, developers must collect actual CSI data from test cases and then construct statistical models or reference templates, often called fingerprints. The classifier can then use these models or templates to best match the feature from the extractor and the known situations.

Another approach is machine learning (ML). Developers can feed extracted features and correct classifications of those features into a support vector machine or a deep-learning network, training the model to classify the abstract patterns of features correctly. Recent papers have suggested that this may be the most powerful way forward for classification, with reported accuracies from 90 to 100% on some classification problems.

Wi-Fi sensing implementation

Implementing the front-end of an embedded Wi-Fi sensing device is straightforward. All that’s required is an 802.11n-compliant interface to provide accurate CSI data. The back-end is more challenging as it requires a trade-off between power consumption and capability.

For the data preparation stage, simple filtering may be within the range of a small CPU core. After all, a small matrix arrives only when a subcarrier is activated. But more sophisticated, statistical algorithms will call for a low-power DSP core. The statistical techniques for feature extraction are also likely to need the power and efficiency of the DSP.

Classification is another matter. All reported approaches are easily implemented in the cloud, but that is of little help for an isolated embedded sensor or even an edge device that must limit its upstream bandwidth to conserve energy.

Looking at the trajectory of algorithms, from fingerprint matching to hidden Markov models to support vector machines and deep-learning networks, the trend suggests that future systems will increasingly depend on low-power deep-learning inference accelerator cores. Thus, the Wi-Fi sensing system-on-chip (SoC) may well include a CPU, a DSP, and an inference accelerator.

However, as this architecture becomes more apparent, we see an irony. Wi-Fi sensing’s advantage over other sensing techniques is its elegant conceptual simplicity. But something else becomes clear as we unveil the true complexity of turning the twinkling shifts in CSI into accurate inferences.

Bringing a successful Wi-Fi sensing device to market will require a close partnership with an SoC developer with the right low-power IP, design experience, and intimate knowledge of the algorithms—present and emerging. Choosing a development partner may be one of the most important of the many decisions developers must make.

Ananda Roy is senior product line manager for wireless connectivity at Synaptics.

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