EDN Network

AI processing, inference specifically, remains mostly a cloud-centric function, but not for long. Whether it shifts to client devices in tandem or completely, who will win?

Way back in December 2022, in the introduction to a teardown of an autonomous object-tracking accessory for a smartphone’s integrated camera, I more broadly positioned the trade-off between cloud- and edge-based AI processing, with the latter exemplified by the widget.

One common way to reduce the device BOM is to offload as much of the total required processing, memory and other required resources to other connected devices. A “cloud” server is one common approach, but it has notable downsides that also beg for consideration from the device supplier and purchaser alike, such as:

• Sending raw data up to the “cloud” for processing, with the server subsequently sending results back to the device, can involve substantial roundtrip latency. There’s a reason why self-driving vehicles do all their processing locally, for example!
• Sending data up to the “cloud” can also engender privacy concerns, depending on exactly what that data is (consider a “baby cam”, for example) and how well (or not) the data is encrypted and otherwise protected from unintended access by others.
• Taking latency to the extreme, if the “cloud” connection goes down, the device can turn into a paperweight, and
• You’re trading a one-time fixed BOM cost for ongoing variable “cloud” costs, encompassing both server usage fees (think AWS, for example) and connectivity bandwidth expenses. Both of those costs also scale with both the number of customers and the per-customer amount of use (both of each device and cumulatively for all devices owned by each customer).

Those points all remain valid nearly four years later, IMHO at least, although an added cloud-based set of downsides now also begs for inclusion in the list. Back then, the AI data center (also called a hyperscaler) build-out phenomenon was still in its comparative infancy, with much of the compute capability then coming online intended for cryptocurrency mining (which ironically has subsequently been redirected to deep learning processing). Nowadays, conversely, the data center phenomenon is in fuller stride, with understandable backlash from the broad populace.

• Speculative investment deals, often “circular” in nature (a hardware supplier invests in a data center developer, for example, with the latter promising to use the former’s chips and software in exchange), result in frequent stock market volatility and broader growing “bubble market” concern.
• Governmental jurisdictions provide lucrative tax breaks and other incentives to data center developers, even though any tangible increase in employment for the local populace will be time-restricted to only the subsequent duration of construction.
• Data center energy demands are substantially incremental, necessitating in-parallel built-outs of additional power plant facilities whose costs are assumed by all.
• The incremental energy predominantly comes from hydrocarbon-based power sources such as coal and natural gas, with substantive pollution and noise impacts.
• Water demands for cooling purposes are equally sizeable, redirecting and draining aquifer reserves no matter whether the sources are fresh, recycled, or a mix of these.
• And the facilities are massive in size, gobbling up available open space as well as fields formerly used for various agricultural purposes.

Edge demands

And here’s what I wrote about the edge processing alternative back in late 2022.

Another popular BOM-slimming approach involves leveraging a wired or (more commonly) wireless tethered local device with abundant processing, storage, imaging, and other resources, such as a smartphone or tablet. This technique has the convenient advantage of employing a device already in the consumer’s possession, which he or she has already paid for, and for which any remaining “cloud” processing bandwidth involved in implementing the complete solution he or she will also bankroll. The latency is also notably less than with the pure “cloud” approach, privacy worries are lessened if not fully alleviated, and although the smartphone’s connection to the “cloud” may periodically go down, the connection between it and the device generally remains intact.

All still valid, too, IMHO. And add to the list the facts that the alluded-to enhanced privacy not only applies in a general sense but also specific to keeping personal data out of the “cloud” provider’s training data set, and that the cessation of ongoing-cost outflows involves not only hardware but also monthly expenses for AI service subscriptions (if you’re a consumer) or tokens (for developers). However, the only downside I mentioned back then was the following.

The notable requirement for the manufacturer here is that whatever device-offloading application is running on the tethered mobile device must comprehend all common mobile operating systems (predominantly Android and iOS, along with the related iPadOS for tablets, nowadays) and the various devices that run on them, and it must also evolve as both operating systems and hardware evolve. Otherwise, the application will sooner-or-later stop meaningfully working, as will the device it’s tethered to.

Admittedly, in my defense, the device I was showcasing in that teardown heavily depended on a smartphone-based app, so it made at least some sense to focus on that nuance. But although I noted that the app leveraged the smartphone’s built-in image capture and processing resources, thereby obviating the need for costly redundancy in the accessory, I overlooked the not-insignificant and growing burden of that processing, along with the associated necessity for adequate memory—both nonvolatile for storage and volatile for code execution and temporary data—and how those memory capacity and speed needs might expand in the future.

Now we know. Not only are the not-unlimited supplies of SSDs (along with HDDs, interestingly, trading off raw performance and energy consumption for raw capacity and cost-per-bit) and DRAM being redirected to data centers, the required capacities of each in PCs, smartphones and the like for today’s edge AI processing functions are increasing in lockstep. Take, for example, the Gemini AI models embedded in latest-generation Chrome browser installs, which take up at least 4 GBytes of storage space. Or the Apple Intelligence included with iOS 27, now required vs. optional with the version 26 O/S predecessor, and using up to 14 GBytes of capacity. The similarly required-by-default AI model suite included with MacOS 27? 12-30 GBytes in size, although open source can come to the rescue in this case.

While a company called PrismML, which specializes in quantizing and otherwise compressing deep learning models for use in resource-constrained systems, was able to shrink Alibaba’s Qwen3.8 27B open-source model by between 9-10x while still matching 98% of Qwen’s aggregate benchmark scores, the resultant model was still 5.9 GBytes. Perplexity’s Portable Computer for local on-computer model storage and processing? 20 GBytes. And of course, storage needs in both cloud and edge scenarios will further increase in the future.

Hybrid intermediaries

One of many ironies here is that a not-insignificant percentage of the processing resources in data centers find use, at least on a part-time basis, not for inference but for training—initial training, periodic retraining to counteract performance decay, iterative training to encompass new and expanded datasets, and transfer learning to adapt frontier models for specific tasks. OpenAI recently reported, for example, that the training run for its latest-generation “Astra” GPT-6 fully consumed more than 100,000 GPUs. These particular operations are compute-intensive and highly parallelizable, which explains why GPU-derived architectures have come to the fore in this particular application.

For inference, conversely, only the prefill portion of the total task is parallelizable, therefore GPU-amenable (albeit not necessarily GPU-optimal). The subsequent decode portion of the total inference pipeline is conversely memory-intensive, from both capacity and bandwidth standpoints, the latter rationalizing the ascendance of advanced HBM approaches.

That all said, any claim that inference is instead going to transition fully to the edge in all cases is, once again IMHO, a pipe dream. Autonomous vehicles and other specific scenarios? Sure. But there are plenty of other applications where latency and privacy (which can alternatively be handled via encryption, anyway) aren’t an issue but the need for access to sizeable trained models is, and servers rule in such cases, as I noted in late-2024 follow-up coverage.

Hybrid approaches, in which a base level of inference occurs locally with cloud resources tapped as-needed for beefier-function requirements, will be increasingly common going forward. Alternatively, other local-ish (or, if you prefer, local networked cloud) scenarios are also beginning to emerge. Take, for example, NVIDIA’s Personal AI Router (PAIR), which enables spreading the overall inference (including agents) processing task across multiple LAN-connected computers (including non-NVIDIA-based Macs). Or instead consider storing the models on a LAN-shared NAS for common access, although RAM limitations will likely preclude full inference processing there.

Revenge of the commodity (and the proprietary)

The obvious beneficiaries of these trends include memory and broader mass storage suppliers. I admittedly find it ironic that after countless commodity boom-and-bust cycles, several of which I personally lived through from the supplier side, the semiconductor memory industry may have finally found a path to a predictable and otherwise sustainable business model.

The other potential winners are inference chip and IP core suppliers. As mentioned earlier, whereas GPU-based architectures will likely continue to reign into the future from a training standpoint (if for no other reason than proprietary software tools prevalence), an ever-increasing percentage of total growth in the AI processing space will instead be in inference, where toolset lock-ins are more fungible and other parallel-processing, not to mention more memory-centric architectures may indeed end up more optimal for the necessary tasks.

What are your thoughts on the trends I’ve identified, their root causes and beneficiaries, and their short- and long-term outcomes? Let me and your fellow readers know in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• iJoy’s chase face- and object-tracking widget: A robot or tripod it isn’t
• Made by Google 2026: This limited silicon-supply situation really sucks
• The Microsoft-reminiscent iPhone Duo: How much customer holding-and-folding is necessary to keep Apple from folding on the experiment?
• Training and inference: Two faces of AI compute
• HBM memory and AI processors: Happy together

 

The post Cloud to edge AI: If and when, to what degree, and how and why appeared first on EDN.

Particularly in consideration of current (and over-time increasing) semiconductor constraints, this has been a surprisingly busy (albeit pricey) October from a systems-release standpoint.

Nearly two months ago, as is typical for the season, Apple announced new smartphones, watches and earbuds. Several weeks before that, the company had somewhat-typically-for-fall unveiled two new processors and systems containing them. But wait, there’s more. Just two weeks back, and atypically, Apple had rolled out more hardware, this time for the smart home. And this week? Three straight days of even more hardware. Very atypical.

I’ll get to Apple’s most recent news shortly. But it wasn’t the only tech heavyweight to unveil new mobile computing devices—a mix of laptops and tablets—this month.

Microsoft and Nvidia go “Ultra”

Last November, within my yearly “Holiday Shopping Guide for Engineers” (this year’s edition which I’m now reminded I need to begin writing shortly), I suggested (among other things) you consider purchasing, for others and/or yourself, Nvidia’s DGX Spark mini AI workstation.

(it’s the gold-colored device to the right of the laptop, not the laptop itself. Hold that thought).

As background info for today’s discussion, I noted the following back then.

Its application processor, originally referred to as the N1X, is now renamed the GB10. Co-developed by NVIDIA (who contributed the Grace Blackwell GPU subsystem) and MediaTek (who supplied the multi-core CPU cluster and reportedly also handled full SoC integration duties), it was originally intended for—and may eventually still show up in—Arm-based Windows PCs. But repeated development hurdles have (reportedly) delayed the actualization of both SoC and system shipment aspirations, and lingering functional bugs preclude Windows compatibility (therefore explaining the DGX Spark’s Linux O/S foundation).

Those bugs have apparently finally been squashed—or at least sufficiently worked around—because Nvidia and lead mobile systems partner Microsoft publicly released the Surface Laptop Ultra on October 7. The history lesson here is interesting (IMHO, at least) and instructive.

Microsoft has been steadily working on Windows-on-Arm, spanning operating systems, applications suites and hardware to run them on, since June 2012 with the Windows Surface RT, which was powered by the multi-core Arm Cortex-A9-based Nvidia Tegra 3 SoC.

 

From then until now, everything else Arm-related, including my latest Surface Pro 11 “Plus” acquisition (along with several generations of developer-tailored desktop hardware), ran Qualcomm-developed silicon, even if the SoCs were Microsoft-stamped. But Nvidia’s back, baby. And it’ll only cost you $2,599 (baseline, as much as $5,899.99 top-end) to own one. With delivery “later this year” (which, I’m compelled to note, has only two more months left in it as I type this). Gulp.

Two versions of the Nvidia RTX Spark N1X (apparently, in a clarification of the earlier rename mention, both GB10 and N1X are valid monikers, for different system form factors) exist, both with the same NPU core inside:

• 5120-core GPU and 18-core CPU, and
• 6144-core GPU and 20-core CPU

System memory ranges from 24 GB to 128 GBytes in capacity, LPDDR5x DDR unified in all configurations. SSD options start at 512 GBytes (PCIe Gen 4), with 1 and 2 TByte PCIe Gen 5 configurations also offered. And by the way, an RTX Spark-based developer platform, $5,999.99 and up, is also available for pre-order (perhaps a replacement for the canceled Qualcomm one?).

Amazon loves generic Android (again)

Next stop: tablets. I’ve said it before, I’ll say it again today, and I’m unfortunately sure I’ll be saying it more in the future, given where semiconductor building block prices and tariffs are going: when your bill-of-materials costs increase, the best way to “hide” them is to bail on entry-level models and conversely double-down on already-profit-margin-padded high-end product variants. Enter Amazon’s no-longer-Fire, now Alexa-branded, latest-generation tablets.

Plastic cases are gone (except for the kiddie-tailored ones), replaced by thin unibody aluminum chassis, wrapped around higher-quality LCDs, multi-speaker arrays and other integrated goodies. Gone too is access to the Amazon Appstore (which won’t be a surprise to anyone who read my last-October Amazon coverage); Amazon’s back to leveraging the Google Play Store.

More generally, the new tablets run “vanilla” Android instead of the “forked” Fire OS precursor. They come in 8”, 11” and 12” “Pro” flavors, each with multiple storage capacity tiers (along with two DRAM capacity options for the 8” version, interestingly), with prices starting at $299 and ranging up to $679.99, not including cases or the high-end model’s optional pen and keyboard accessories.

Speaking of October Amazon coverage, by the way, the company chose today, at the tail-end of competitor Apple’s three-day announcement cadence, to roll out this year’s collection of Echo speakers (one even complete with a camera? SMH), smart displays and such. I won’t be covering them in this particular piece, so to tide you over until I have time to discuss them, I’ll hand you over to Engadget (or any of the other usual suspects, for that matter) for coverage purposes.

Touch me. Finally.

And speaking of unwise chronological congruity, what did Apple roll out this week? Monday brought a new generation of the iPad mini (the prior generation of which, which I own, was dubbed “cute” by my wife just the other day), no longer with a trailing-edge SoC versus its larger siblings (now with the A20 Pro), and with a slightly larger display (8.5” in diameter this time) that, even more impactfully, switches from LCD to OLED. The front camera is conveniently relocated to the landscape edge, too. And yes, all this goodness is accompanied by price increases. The entry-level 128 GByte Wi-Fi-only variant of my 2024 model was originally $499 but got bumped by Apple up to $599 in June of this year, while this year’s edition is $699 and up. Yup.

 

Yesterday? Thanks for asking. The 14” (but not 16”, interestingly…the same thing happened last year, so I’m guessing the larger one’s “Pro” and “Max” only from here on out) entry-level version of the MacBook Pro now runs the M6 SoC, versus last year’s M5, while the 24” iMac makes a two-gen (and associated two-year between-updates) jump from the M4 to the M6.

Yep, that’s basically it; form factors, etc. remain unchanged. Yawn. Even the MacBook Pro stock image shown above, from Apple’s press release, was boring. And if I was a betting man, I’d lay my odds on the earlier-leaked theory that the next SoC iterations of the higher-end “Pro” and “Max” MacBook Pro variants will await the M7 Apple Silicon generation.

Apple instead “kept its powder dry” for today’s unveiling of its first touchscreen-augmented (and broader PROLED XDR-based) computers, MacBook Pro laptops in both 14” and 16” display and both M5 Pro and Max SoC options.

Now that’s a snazzy stock image…err…video, right? Unsurprisingly, there’s a whole lot of underlying software evolution of both MacOS and key apps such as the Safari browser (beta-examination insights into the latter which were discovered two weeks back) as enablers of the enhanced hardware. And equally unsurprisingly, those hardware enhancements come with an associated price tag increase. Depending on size and configuration, you could pay anywhere from $2,899 to…hold your hat…$14,549 for the privilege of a display that responds to your touch.

You may now pick yourselves up from the floor and climb back in your seats. Although I’m sure Apple’s done no shortage of advance market research, including conversations with potential customers under NDA, I’m admittedly somewhat skeptical about the prospects for long-term high volume success here. I say this although I have absolutely no doubt in the first-generation fiscal-and-other enthusiasm of technology early adopters, and even though I acknowledge (in a nod to my earlier Microsoft Surface case study comments) that Apple’s a late adopter here as compared to Windows-powered touchscreen counterparts (along with its own iPad, for that matter).

Speaking of case studies, let’s take me as an example. Including my current x86-based Surface Pro 7+ (and spare, along with two Pro 8+ successors in the queue) and earlier mentioned Arm-based Pro 11 models, I’ve to date purchased nine (six to-date actively used) touchscreen Windows laptops, if my recollection is correct. But I’ve barely used their touchscreens at all, far from for any meaningful period of time.

Partly, speaking of fiscal blessings, it’s because I’ve in-parallel owned multiple generations of iPads. And to that point, I’m most enthused about the concept when it’s applied to hybrid systems like the Surface Pro that can operate as both a tablet and a laptop, depending on if a physical keyboard is connected at the time. But that’s not the form factor of these new MacBook Pros. And I’d wager that anyone who’ll buy one is capable of buying an iPad (or few), too.

Thoughts, readers? Let me know in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Apple’s processor cadence: A pending stutter-step for improved long-term edge inference?
• The Microsoft-reminiscent iPhone Duo: How much customer holding-and-folding is necessary to keep Apple from folding on the experiment?
• Apple heads Home: Distributed identity validation, and how much does Matter matter?
• Amazon and Google: Can you AI-upgrade the smart home while being frugal?
• The Microsoft Surface Pro 5 succession: Selections, motivations, and initial impressions

The post Amazon, Apple and Microsoft: New mobile computing platforms take off appeared first on EDN.

TetraMem has completed tapeout of the MLX300, a 12-nm analog in-memory computing (A-IMC) SoC based on multi-level RRAM technology. The chip was developed using Synopsys EDA software delivered through Synopsys Cloud FlexEDA, extending multi-level RRAM-based AI chip development to advanced FinFET nodes.

The MLX300 tapeout follows TetraMem’s MLX200/MLX200M multi-level RRAM A-IMC SoCs, which completed full-mask tapeout in 2026 on a commercial 22-nm process.

TetraMem’s architecture enables scalable AI accelerator development while improving performance per watt and reducing data movement. The MLX300 uses this architecture in a single-chip accelerator for audio, vision, and smaller language models. It supports up to 64 million INT4 parameters on-chip without external DRAM for model-weight storage. TetraMem says the SoC targets energy efficiency exceeding 50 TOPS/W.

TetraMem

The post Analog in-memory computing advances to 12 nm appeared first on EDN.

ST has launched an automotive sensor platform that combines multi-axis accelerometers and angular-rate sensors in a single package. The platform is designed to extend active and passive safety systems and driver-assistance features across vehicle categories, from premium to mass-market. Applications include crash protection, rollover detection, airbag deployment, vehicle stability control, and radar beam stabilization.

The sensors feature internal diagnostics and support SafeSPI, a serial peripheral interface for automotive safety. ST’s first four offerings following its integration of NXP’s sensors division are:

• NCS1012BAEP: z-axis (yaw) angular-rate sensor and xy low-g accelerometer
• NCS1012CAEP: x-axis (roll) angular-rate sensor and yz low-g accelerometer
• NCS1012EAEP: x-axis (roll) angular-rate sensor and xy medium-g accelerometer
• NCS10135AEP: z-axis (yaw) angular-rate sensor and xyz low-g accelerometer

Angular-rate sensors offer full-scale ranges of ±125 dps, ±250 dps, or ±350 dps, with integrated low-pass filtering (12.5–400-Hz cutoff options) and operation from −40°C to +105°C. Low-g accelerometers cover ±1.50 g to ±34 g, while medium-g versions cover ±15.5 g to ±150 g and feature an independent signal chain to minimize noise. Both acceleration sensor types feature low offset and drift over the automotive temperature range and integrated low-pass filtering.

The combo sensors are now in production in 24-pin QFN packages with wettable flanks.

STMicroelectronics

The post Motion sensor combo ICs target vehicle dynamics appeared first on EDN.

A programmable Hall switch from Melexis, the MLX92342, simplifies remote position detection in automotive systems such as seatbelt buckles. The 2-wire, PCB-less sensor IC provides a valid output and generates a diagnostic safety signal in less than 100 µs. This signal indicates a fault condition, allowing the ECU to distinguish a sensor malfunction from a valid buckle-state reading.

With integrated on-chip diagnostics, the MLX92342 is certified as an ISO 26262 ASIL B SEooC and qualified to AEC-Q100. ESD protection is rated at 8-kV HBM, 15-kV system-level contact discharge, and 25-kV system-level indirect discharge. The device supports magnetic latch, unipolar switch, and omnipolar switch configurations, with a magnetic operating range of 0.5 mT to 200 mT. 

Beyond seatbelt buckle detection, the MLX92342 can be used in window lifters, brake fluid level sensors, active air skirts, locks, valves, and actuators. It is a suitable option for applications using mechanical microswitches, reed switches, or less advanced magnetic switches, adding programmability, diagnostics, and contactless operation.

The MLX92342 is available now. A locked, pre-programmed version, the MLX92341, is also available.

MLX92342 product page 

Melexis

The post Hall switch adds diagnostics for automotive safety appeared first on EDN.

Innodisk offers the GMSL2 camera starter kit, which bundles four 3-Mpixel cameras, a MIPI CSI-2-to-GMSL2 capture card, and accessories. The kit provides a ready-to-use platform for developing and validating multi-camera systems for edge AI vision applications.

GMSL2 is a high-speed serial link for real-time video transmission, supporting forward-channel data rates of up to 6 Gbps. The starter kit includes camera source code for the NVIDIA Jetson Orin Nano Super Developer Kit, the platform used to run the system. The pre-integrated hardware and software reduce the need for component sourcing, complex system-level integration, driver debugging, and tuning.

In addition to the four fixed-focus GMSL2 camera modules and capture card, the kit comes with four 1-meter GMSL2 FAKRA cables, a power adapter, and power cords.  Target edge AI applications include blind spot detection and ADAS for heavy-duty vehicles, as well as object recognition and environmental perception for humanoid robots and autonomous mobile robots.

After initial validation with the starter kit, Innodisk offers customization services ranging from hardware fine-tuning to application deployment in edge environments.

GMSL2 camera starter kit (EKIT-B14-001)

Innodisk

The post Camera kit simplifies multi-camera AI development appeared first on EDN.

The Renesas RX74M and RX74N 32-bit MCUs are the first in the RX family to use a 22-nm process and incorporate embedded MRAM. Based on a 600-MHz RXv3e core, both of these industrial devices achieve more than twice the performance of their 240-MHz predecessors, the RX72M and RX72N.

Each MCU features 1 MB of code MRAM, 256 KB of zero-wait-state TCM (tightly coupled memory) RAM, and 1.5 MB of SRAM for real-time processing. Unlike embedded flash, MRAM can be written without a prior erase operation, allowing faster code and data updates and reducing programming time.

The RX74M is designed for industrial automation equipment, including AC drives, industrial robots, and PLCs. The RX74N targets smart meters, power conditioners, and HVAC systems. Both integrate Gigabit Ethernet and CAN FD, while the RX74M adds a TSN-capable Ethernet switch and an EtherCAT slave controller for industrial networking.

The RX74M and RX74N are available now, along with corresponding evaluation boards.

RX74M product page 

RX74N product page 

Renesas Electronics 

The post Industrial MCUs pair 600-MHz cores with MRAM appeared first on EDN.

Designing compact and efficient power factor correction (PFC) stages for low-power to mid-power applications often requires operating in critical conduction mode (CrM) or discontinuous conduction mode (DCM). These modes offer improved efficiency and simplified control at light loads, but require careful design to ensure correct valley detection and mode transitions across the entire input range and load range.

CrM/DCM boost PFC topology is a highly recommended solution for applications up to 200 W. This topology remains a compelling choice for the 200 W to 400 W range, particularly when cost effectiveness and light-load performance are primary design constraints. However, it’s important to select the most suitable mode depending on the power level and system constraints.

Figure 1 The PFC boost stage operates in CrM under worst-case conditions and falls back to DCM at lighter loads. Source: Monolithic Power Systems

This article presents a step-by-step methodology for designing a boost PFC stage that operates in CrM under worst-case conditions and falls back to discontinuous conduction mode at lighter loads, as shown in Figure 1.

The inductor is selected to achieve critical conduction at the minimum input voltage (VIN) and a full load, ensuring proper zero-current switching. Key aspects such as variable frequency behavior, inductance, and peak current calculation are addressed in this article through a formula-driven approach.

Step 1: Define the operating parameters

An effective power design should include a clear set of specifications and consider the worst-case scenario. The operating parameters for a universal input PFC converter are the minimum AC RMS input voltage and maximum output power (POUT_MAX).

Table 1 shows the power converter specifications for a practical example, which will be applied to the following calculations in this article.

Table 1 These power converter specifications are applied to calculations in this article. Source: Monolithic Power Systems

Based on Table 1, the minimum switching frequency (fSW) is at the peak of the low AC line and at POUT_MAX. Figure 2 shows that the inductor current dependent on time (iL (t)) follows the AC input voltage and its average value (IL_AVG) in CrM.

Figure 2 The inductor current dependent on time follows the AC input voltage and its average value in CrM. Source: Monolithic Power Systems

The worst-case conditions can be determined using the power converter specifications from Table 1.

The maximum input power (PIN_MAX) can be calculated with Equation (1):

If POUT_MAX is 150 W and η is 0.94 under the worst-case conditions, then PIN_MAX is 159.57 W.

The minimum peak AC voltage (VIN_PK_MIN) can be calculated with Equation (2):

If VAC_MIN is 85 V, then VIN_PK_MIN is 120.21 V.

Step 2: Calculate the inductance

The single most important component in this design is the boost inductor (L). Figure 3 shows an example of a power inductor for the PFC boost stage.

Figure 3 Here is an example of a power inductor for the PFC boost stage. Source: Monolithic Power Systems

The boost inductance determines the energy storage per cycle and mode. The converter must be in CrM at the minimum AC input voltage under full loads. This ensures that the inductor has sufficient energy storage capability for all other operating conditions.

The required inductance (L) for CrM can be calculated with Equation (3):

Where VIN_PK_MIN is the peak input voltage at the minimum AC input voltage, VOUT is the DC output voltage, PIN_MAX is the input power at full load, and fSW_MIN is the target minimum switching frequency.

The inductance based on Equation (3) and the power converter specifications provided in Table 1 is 450 µH, as shown below.

At the highest current demand (low line peak at full loads), a 450-µH inductor ensures that the current returns to 0 A by the end of a 70-kHz cycle. For any other current demand levels, the cycle completes faster, causing the part to operate in discontinuous conduction mode.

Step 3: Calculate the maximum component stress

With a fixed inductance, the absolute maximum peak current tolerated by the MOSFET and diode at the peak of the low AC line voltage can be calculated. In CrM, the inductor current waveform is a triangle starting from 0 A, where the peak current (ISW_PK) is exactly twice the average input current. The average current at the peak of the sinusoid (IIN_PK_AVG) can be calculated with Equation (4):

The absolute peak switch current (ISW_PK_MAX) can be calculated with Equation (5):

The calculation for the practical example is shown below.

This means that the MOSFET (Q1) and boost diode (D1) must be rated to handle a repetitive peak current of at least 5.31 A. The RMS current rating is lower, but this peak value determines the component’s survivability.

Step 4: Analyze variable frequency operation

A defining characteristic of a CrM/DCM PFC is its variable switching frequency (fSW), which changes dynamically throughout each half-cycle of the AC line and is the lowest at the peak of the AC voltage (where the most power is processed) and highest near the zero-crossings.

The instantaneous fsw (t) can be calculated with Equation (6):

Where vin (t) is the instantaneous input voltage, and p (t) is the instantaneous input power.

vin (t) can be calculated with Equation (7):

p (t) can be calculated with Equation (8):

Figure 4 shows fSW across a half-line cycle, which has a characteristic U shape.

Figure 4 Switching frequency (fSW) across a half-line cycle has a characteristic U shape. Source: Monolithic Power Systems

The designed minimum 70 kHz switching frequency (fSW_MIN) is lowest at the peak of the sinusoid, while the frequency rises dramatically near the zero-crossing. The controller IC must have a maximum frequency clamp to prevent excessively high-frequency operation, which would lead to high switching losses. A typical clamp is about 250 kHz.

Step 5: Understanding the control loop and zero-current detection (ZCD)

Compared to a fixed-frequency CCM design, a CrM/DCM PFC uses on-time control and zero-current detection (ZCD). The voltage loop sets the on-time command to regulate the output voltage (VOUT), while the ZCD signal and the controller’s internal timing logic determine when the next switching cycle can begin. As a result, fSW depends on the on time (tON), the inductor demagnetization time, and any additional delay introduced by the controller.

On-time control

The main control loop adjusts the MOSFET’s tON. A longer tON results in a higher peak current and more power delivered to the output. The controller’s error amplifier (EA) compares VOUT to a reference voltage and sets the required tON to keep VOUT in regulation. The tON behavior across the AC line cycle depends on the control method implemented between constant-on-time (COT) control and variable-on-time (VOT) control.

• Constant-on-time (COT): In this standard approach, the controller maintains a fixed tON throughout a single mains half-cycle. The peak current (IPK) can be calculated with Equation (9).

The current naturally follows the sinusoidal shape of VIN, providing inherent power factor correction. The voltage loop updates this constant value slowly across several cycles to regulate the output load.

• Variable-on-time (VOT): To further minimize total harmonic distortion (THD), advanced controllers may modulate tON within the half-cycle. For example, intentionally extending tON near the VIN zero-crossings can compensate for dead zones and crossover distortion, resulting in a purer sinusoidal input current.

Zero-current detection (ZCD)

Rather than use a fixed-frequency clock to start a new cycle, the controller waits for a signal from the ZCD circuit, indicating that the inductor current (IL) has dropped to 0 A. An auxiliary winding is added to the boost inductor. When IL decays and reaches 0 A, the voltage on the main winding collapses, inducing a voltage swing in the auxiliary winding. This voltage swing is detected by the ZCD pin on the PFC controller, which immediately initiates the next MOSFET turn-on event.

Final design

By calculating the required boost inductance and current on the semiconductor devices, a PFC boost converter design can be completed using the MP44020, a multi-mode CrM/DCM PFC controller. Table 2 shows the key design results for a 150-W application.

Table 2 Design results are shown for a 150-W application. Source: Monolithic Power Systems

The MP44020 CrM/DCM controller provides simple and high-performance active PFC using minimal external components. To enhance system performance across all load conditions, fSW is reduced at light loads via dead time (DT) extension technology, which improves efficiency and helps achieve very low standby power consumption. MP44020 also achieves lower THD by implementing VOT control, a significant advantage over conventional COT methods.

Protections include over-voltage protection (OVP), over-current limit (OCL), brown-in (BI) and brown-out (BO), VCC voltage (VCC), under-voltage lockout (UVLO), and over-temperature protection (OTP).

Due to MP44020’s high integration, the PFC stage requires only a few external components to function effectively. Figure 5 shows the PFC boost converter schematic using the MP44020 CrM/DCM controller.

Figure 5 The PFC boost converter using the MP44020 requires only a few external components to function effectively. Source: Monolithic Power Systems

Adhere to CrM design principles

Implementing an active PFC boost converter is a critical first stage for modern AC/DC power supplies. This ensures compliance with harmonic current standards and maximizes power quality. In particular, CrM topology offers a cost-effective solution for applications up to 400 W.

By adhering to the design principles for CrM, such as selecting the appropriate boost inductor and managing the variable fSW, engineers can design efficient and reliable PFC circuits. Moreover, a modern controller significantly simplifies this task. Its variable-on-time (VOT) control scheme ensures low THD in addition to integrated protections and efficiency-boosting features for light-load conditions that achieve a robust and high-performance design.

Rafael Collado is a design engineering supervisor at Monolithic Power Systems (MPS).

Related Content

• Power Factor Correction (PFC) Modules
• Back to Basics: Power Factor Correction
• How to design a high-boost-ratio boost converter
• Advantages of interleaved boost converters for PFC
• Feasibility and Accuracy Analysis of Input Power Estimation for Boost PFC Converters with Additional Sensors

The post An equation-driven guide to designing a CrM/DCM boost PFC appeared first on EDN.

A simple circuit adds a relevant status-reporting bit to the device’s existing already-sizeable capabilities suite.

As described in its datasheet (PDF), the DRV103 is a (mostly) complete, robust, versatile, and efficient solution for solenoid and other power driver applications. However, there’s one trick missing from its sleeve. It lacks the ability to detect and report open-load faults in which the driven load has come adrift or is missing its connection to the power source, or the coil winding has come open or has otherwise lost continuity.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The 103 falls out of its shrink wrap with built-in over-current and over-temperature detection and protection already in place. The logic-level OK-status flag output goes to zero when an energize command is issued and such an error occurs. So, this variety of mishap and mayhem is already adequately covered. No need for rework there.

But obviously, if the driver attempts to energize the load when the load’s connections are broken, nothing useful will happen. And, in an unmodified 103, neither before nor after the failed attempt will any diagnostic error indication be sent to the controller, which will therefore happily but erroneously assume its orders are continuing to be obeyed. This might not be so good, particularly if the application is critical. And at the end of the day, aren’t they all?

Figure 1 shows a (reasonably) simple modification to address this shortcoming.

Figure 1 The absence of V+ at OUT when Input = 0 causes “wired-or” Status OK bit to be pulled low by Q2, indicating the open-load error condition. A connected GPI pin should be configured for passive pullup.

Here’s how it works.

When Input is pulled low by the controller, typically a µC general-purpose (GP) output bit, Q3 turns off, releasing Q1’s collector. Since Input being low also turns the DRV104 internal transistors off, the driver’s OUT pin will now float high or low depending on whether (or not) an intact connection to V+ is established through a properly connected load. This will turn Q1 on (or off), and Q2’s base along with it.

If a good V+ connection exists, Q1 will now turn on, turning Q2 off, releasing Status OK and causing a connected GP input bit to go true, sharing the good news with the controller.

Otherwise not.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• 8 to 48 volt PWM relay/solenoid driver finds fault, pinches power
• Booster circuit enables reliable solenoid operation
• The overcurrent limiting transistor fails before anything else!
• Three discretes suffice to interface PWM to switching regulators
• Automotive low side output switch architecture suitable for 8 to 48 volt buses and beyond

The post Adding open-load fault detection to the DRV103 PWM driver appeared first on EDN.

Any engineer with hands-on experience is familiar with cables which are shielded with a woven, all-metal braid, seen in Figure 1. Braided shielding has been used for decades. It is widely available, has modest cost, and it works—at least up to a point.

Figure 1 This schematic of a cable using conventional braided shielding illustrates the RF barrier it provides; the illustration shows multiple basic-wire conductors, but the same concept is used with coaxial cables and twisted-pair cabling. Source: Stecker Express

The braid serves two complementary EMI functions in most cases. It attenuates emissions of electromagnetic energy from the cable, and, at the same time, it prevents interfering energy from reaching the cable. It’s used for cables carrying DC all the way to gigahertz signals. Shielding is used with coaxial cable, twisted pairs, multiconductor cable assemblies, and more.

Engineers have a love/hate relationship with cables that use a tightly woven conductive braid for shielding. On one side, it’s an essential passive component for maintaining signal integrity, and how can you put a price on that, especially when there seems to be no viable alternative. On the other side, it adds bulk, weight, cost, and routing challenges to the end-product.

Shielded cable also has termination challenges. Every hands-on engineer can tell “horror stories” of trying to cleanly terminate the shield to the connector, especially if it’s being done by hand without the right tools or jigs. Those tiny cut shards of braid that “fall” when trimming it can easily short the cable, and nearby circuit board, and cause general troubleshooting havoc.

The shielded-cable dilemma increases in today’s world of complex cabling in small spaces, with design emphasis on cable size, weight, and performance. Cables with conventional braided shields—almost always made of copper, but sometimes other metals such as aluminum are used—are relatively heavy and bulky.

Furthermore, the relative proportion of their overall weight and bulk increases compared to core cable size as the core that is being shielded shrinks down. That creates a dilemma for designers as gigahertz cables go down to millimeter-levels diameter, and the weight and bulk of the shielding soon become a significant design issue.

There’s even another insidious concern: performance. As frequencies reach in the multi-gigahertz range, the shielding performance of the braid decreases. The tiny voids in the woven braid become “open windows” to the short-wavelength RF energy. These shielded cables also restrict movement, can be difficult to handle and install, and their “shape memory” makes routing and rerouting more difficult.

Tighter weaves improve the situation somewhat, but at a cost in materials, flex, weight, and other factors.

Some cables use a solid foil as a first-layer shield, which is then covered with a braided shield. This improves RF shielding to nearly 100%, but further increases cost and weight and adds to termination complexity.

What can be done?

New shielding technologies and approaches are needed as cable applications shift. A vendor-authored article I saw highlighted the ARACON shielding system from Micro-Coax, a division of Amphenol. It’s based on a very different approach to creating the RF cage around the signal-carrying conductors.

Instead of woven metal braid, it uses lightweight, ultrathin, and extremely strong DuPont Kevlar fibers to create a textile-like material that then is coated with either nickel or silver (for solderability). It forms a composite shielding braid that is up to 80% lighter than copper, while still providing strong EMI/RFI protection, lightning protection, and mechanical robustness.

The conducting coating adheres to the fabric-like fibers to form a “wrapper” against electromagnetic energy. The result is a thin braid-equivalent that slips onto the cable core like a thin, open-ended, super-flexible sock. It can be used with coaxial cable, twisted pair, and even wire bundles, shown in Figure 2.

Figure 2 The ARACON shielding system uses a thin but super-tough fabric sock that slips over the conductor or wire bundle to be shielded. Source: Micro-Coax

To get a sense of the bulk differences, the density of aramid fibers is only 1.44 grams per cubic centimeter (g/cc), compared to copper at 8.9 g/cc. Even with the addition of the metal coatings, the density of fibers ranges from 3 g/cc to 5 g/cc. At the same time, the tensile strength of the aramid core, at 350 kilopounds per square inch (Ksi) is 3 to 10 times higher than that of traditional or high-strength copper cores (35 Ksi to 95 Ksi).

Its other attributes are flexibility and longevity. It has been tested to withstand over 50,000 flex cycles over a 180-degree arc; installs easily, as it cuts like fabric with standard tools; and it offers corrosion resistance (important in many real-world settings). Termination techniques are similar to those for wire-braided shields.

It meets or exceeds the many stringent mil/aero and space-related electrical, mechanical, and outgassing performance standards for shielding (it’s a long list), but with far less bulk and weight. Micro-Coax says it can be braided and fabricated by wire/cable vendors using standard metal-wire equipment and it supports crimping or banding, as well as soldering (if it’s silver plated).

The high surface-to-volume ratio of ARACON fibers contributes to effective RF EMI shielding, exceeding the performance of conventional shielding, as seen in Figure 3.

Figure 3 Despite its reduced bulk and weight, the Aracon approach offers approximately 20 dB greater attenuation compared to conventional copper braid (here, industry standard AA59569). Source: Micro-Coax

There’s a lot that is attractive about this shielding approach, which is not just a lab development but has been in use for over 10 years. It has been proven “in the field” in aircraft, space vehicles, and more.

While I couldn’t get comparative pricing—and direct one-to-one comparisons are difficult—I suspect it’s more costly than conventional metal-braided shielding. But I can see where the extra cost is justified in applications where lower weight and bulk, along with performance and flexibility, are more critical priorities than cost.

It feels weird to say “we’ve been a team all these years, but things have changed” to braided shielding. Still, sometimes we must acknowledge reality and move on in a somewhat different direction to meet new design demands and constraints. Perhaps that’s what will happen with the availability of this alternative to braided shielding.

Have you ever found the realities of standard braided shielding to be inadequate for your project, or that it imposed too many burdens? Did you look for alternative cable-shielding solutions? Was your search successful?

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

Related Content

• Sophisticated Cables: Not Just for RF
• Litz Wire & Other Component Cleverness
• Cable self-heating: The other side of IR drop
• Cable Assemblies: Ignore Them and Be Sorry
• Read this and give electric insulation a second thought
• Transmission line design: Why not 75 ohms instead of 50 ohms?

The post A viable alternative to braided shielded cable appeared first on EDN.

Inductor-inductor-capacitor (LLC) applications that don’t require a closed control loop can benefit from simple and low-cost implementations.

High-power applications that require isolation and prioritize high efficiency often use inductor-inductor-capacitor (LLC) converters in either a half- or full-bridge configuration implemented on the primary side, depending on the voltages and power levels. Synchronous rectification is often mandatory to achieve good efficiency, especially with low output voltages.

When looking for closed-loop LLC controllers, there are various options on the market, which offer features for protection and a precise ±3% regulated output. For open-loop applications that can tolerate an unregulated output of ±10%, many closed-loop controller features aren’t necessary, and it often takes some effort to disable certain functions to get an open-loop design working.

LLC controller features

The feature set for an open-loop LLC controller can be divided into mandatory and optional features. Mandatory features include soft start, enable input, over-current protection (OCP) with cycle-by-cycle current limiting (hiccup mode or latch-off), and driving the primary-side power stage. Optional features may include power-good output, over- and under-voltage lockout, and driving the synchronous rectifiers.

The Texas Instruments programmable logic device (TPLD) family can implement these features to achieve a cost-effective solution for open-loop applications. Figure 1 is a block diagram of the TPLD2001-Q1. This device includes various logic blocks, internal oscillators with a clock frequency up to 25MHz, a state machine, and analog comparators, making it a good match for the features that an open-loop LLC controller requires.

Figure 1 This block diagram shows the building blocks available in the TPLD2001-Q1. Source: Texas Instruments

Open-loop LLC implementation

Generating control signals for the power stages is a simple task. For low switching frequencies, designers can use the internal pulse-width modulation (PWM) generators, but higher frequencies require a logic-based approach. One possible implementation is a classical ring buffer built from configurable one-shot blocks, which generate two inverted signals for the primary side and add dead time. Figure 2 shows an implementation that generates the two control signals for the primary side as well as two control signals for driving the synchronous rectifiers on the secondary side, with adjustable dead bands between primary and secondary.

Figure 2 This example implementation generates four output signals with an adjustable dead band, all within a single TPLD2001-Q1. Source: Texas Instruments

In this way, there is no need for a specialized synchronous rectifier controller. To enable synchronous rectification, a comparator channel can measure the primary-side current to enable synchronous rectification as soon as the converter input current rises above a decision threshold.

Figure 3 shows a design example using synchronous rectification without a specialized controller. The use of LMG2104-Q1 integrated half bridges simplifies the TPLD implementation, since these devices take care of the required dead time for the primary side by themselves.

Figure 3 This overview of an example design uses TI’s TPLD2001-Q1 as a controller. Source: Texas Instruments

It is possible to achieve OCP using the internal comparators, which disable switching if the primary-side current gets too large. The amount of available logic gates enables an implementation that does cycle-by-cycle current limiting by skipping cycles if the primary-side current reaches a set limit (Figure 4). After a certain period of time, the control logic then enters hiccup mode or latch-off, which either one-shots or one of the TPLD’s counters can easily implement. Also, during soft start, the disabled synchronous rectification ensures that no unwanted current flows from the output back to the input of the converter.

Figure 4 This example current-limit implementation also fits within the TPLD2001-Q1. Source: Texas Instruments

An enable input completes the connectivity requirements and resets the device so that it goes through soft start when enabled. For devices with several analog inputs, it is easy to add under-voltage lockout and over-temperature protection features.

Of course, there are some limitations to these programmable logic devices, although many are easy to overcome. When using the internal PWM generators, the maximum frequency is limited to <100 kHz because of the fixed-period counter value.

Because the open-loop LLC topology requires no duty cycle or frequency variation, you can build your own control signal generator using the available logic cells within the TPLD2001-Q1 to achieve your desired output frequency. A 25 MHz clock frequency is high enough to generate suitable dead times and output signal frequencies up to about 500 kHz. Higher frequencies are possible; however, the dead time becomes an increasing percentage of the total switching cycle, thereby lowering efficiency.

When using synchronous rectifier controllers and integrated power stages – which take care of the dead time by themselves – this efficiency penalty is no longer an issue. Figure 5 shows the switching waveform of the design example, using a TPLD for controlling the primary side and synchronous rectification.

Figure 5 This graph from the design example shows the switch node and current waveform. Source: Texas Instruments

If you don’t need more than two analog inputs, a smaller device such as the TPLD1202-Q1 is an option. But since that device has only one comparator, the inputs are multiplexed and therefore too slow for OCP. The discrete analog comparators available within the TPLD2001-Q1 are fast enough to implement OCP and can be used for other features like the previously described simple synchronous rectification control. If OCP is the only analog feature that you require, the smaller TPLD1202-Q1 device variant may be a good fit for more cost-sensitive applications.

Conclusion

The TPLD family offers enough flexibility to implement relatively complex control mechanisms for power converters. LLC applications that don’t require a closed control loop can benefit from a simple and low-cost implementation. Although this power tip is based on a working solution, depending on the overall requirements (for example, bidirectional operation or higher switching frequencies), some device limitations could demand a different approach. Here, the TI MSPM0 microcontroller could become a valid option.

As part of the Power Design Services team, Björn Görner has eight years of experience designing custom power solutions and reference designs, with the main focus on automotive applications. He is a regular presenter for Power Supply Design Seminars, which Texas Instruments offers biannually to educate and support anyone interested in power conversion.

 

Related Content

• Power Tips #155: How to choose the best topology for isolated energy storage systems
• How to design a digital-controlled PFC, Part 4

The post Power Tips #158: Using a programmable logic device as an LLC controller appeared first on EDN.

To the untrained ear, it’s a mesmerizing rhythm; to an engineer, it’s a masterclass in continuous wave (CW) ultrasound. Capturing a fetal heartbeat means navigating a complex landscape of acoustic impedance, shifting frequencies, and maternal anatomy.

There’s a moment in pregnancy that feels almost magical—the first time you hear the rhythmic thump of your baby’s heartbeat. Traditionally, this experience belonged to the OB-GYN’s office, where trained professionals used specialized equipment to reassure expectant parents. But in recent years, that sound has traveled beyond the clinic walls, finding its way into living rooms through a small, handheld device: the fetal doppler.

At first glance, it seems like a miracle of accessibility—technology that lets families connect with their unborn child anytime they wish. Yet, as with most medical tools, the story is more nuanced. A fetal doppler is not a toy; it’s a diagnostic instrument repurposed for consumer use. Understanding what it is, how it works, and the realistic pros and cons of at-home listening is essential.

In this post, we’ll explore the science, the emotional appeal, and the safety guidelines that should shape responsible use.

Fetal doppler basics: Sound over sight

At its core, a fetal doppler is a handheld ultrasound device designed to pick up the sound of a baby’s heartbeat. It relies on the Doppler Effect—a principle you’ve likely experienced when a siren changes pitch as it speeds past. The device sends high‑frequency sound waves into the abdomen; when those waves bounce off moving structures like a tiny, pumping heart, they return at a slightly different frequency. The doppler translates those shifts into the familiar “whoosh‑whoosh” sound of a heartbeat.

To make this possible, users apply ultrasound gel to the probe before placing it on the skin. The gel isn’t just for comfort—it eliminates air pockets between the device and the body, allowing sound waves to travel smoothly. Without it, the signal would scatter and fade.

It’s important to note that a fetal doppler is not the same as a full ultrasound scan. While dopplers capture sound, clinical ultrasounds create detailed images of the fetus and surrounding structures. In other words, the doppler lets you listen, but it doesn’t let you see. This distinction underscores both the accessibility and the limitations of at‑home devices.

Figure 1 A pocket fetal doppler with a 3-MHz probe captures low-amplitude Doppler-shifted signals from the fetal heart. Source: KernMed

At‑home vs. medical‑grade dopplers

Not all dopplers are created equal. The handheld device you can order online for around $40 is a far cry from the equipment used in a doctor’s office or by a midwife. Medical‑grade dopplers are built with higher sensitivity, meaning they can detect faint signals from a tiny fetal heart earlier and more reliably.

They also feature advanced noise‑filtering circuits that reduce interference from maternal blood flow or background movement. Just as importantly, these professional devices are regularly calibrated to ensure accuracy, a step that consumer units rarely undergo.

By contrast, at‑home dopplers are simplified, mass‑market versions. They may pick up a heartbeat, but they’re more prone to false positives (like mistaking maternal pulse for fetal heart sounds) or false negatives if the probe isn’t positioned correctly. While they offer emotional reassurance, they lack the precision and reliability of clinical tools. Understanding this gap is key to using them responsibly.

When can you hear the heartbeat and how to use it safely

For most families, the first audible heartbeat comes between weeks 12–16, when at‑home dopplers begin to consistently pick up the sound. Earlier detection—around weeks 8–12—is possible in a doctor’s office with medical‑grade equipment, but it’s often unreliable at home.

Even within the “sweet spot,” factors like an anterior placenta, the baby’s position, or simply being at the early edge of gestation can make the heartbeat harder to find. Knowing this helps prevent unnecessary panic if silence greets the probe.

Safe use starts with preparation: a full bladder (which helps lift the uterus), lying flat, and applying plenty of gel to eliminate air gaps. Begin the search low, near the pubic bone, and rock the probe slowly rather than sliding it quickly. When successful, you’ll hear the baby’s heart racing like a galloping horse or rapid train—usually 110–160 beats per minute.

By contrast, maternal sounds include the slower thump of the mother’s pulse or the swooshing rhythm of placental blood flow. Recognizing these differences is key to avoiding confusion and using the device responsibly.

Pros and cons plus expert guidelines

At‑home dopplers can feel like a lifeline, offering families a way to connect with their baby between appointments. The pros are easy to see: they provide instant connection, letting partners and siblings share in the experience, and they can ease anxiety for parents who’ve faced pregnancy loss.

But the cons are just as real. A heartbeat doesn’t guarantee that everything is fine, and relying on that sound alone can delay urgent medical care if fetal movement decreases. On the flip side, not finding the heartbeat—often due to baby’s position, placenta placement, or simple user error—can trigger unnecessary panic.

Medical experts urge caution. The FDA recommends that fetal dopplers be used only by or under the supervision of healthcare professionals. While ultrasound waves themselves are generally safe, prolonged or improper use can theoretically cause slight tissue heating. The greater risk lies in misinterpretation: families may either be falsely reassured or unduly alarmed. In short, these devices can be meaningful tools for bonding, but they should never replace professional guidance.

The physics of doppler ultrasound

Now let’s step beyond the emotional resonance and into the engineering core of how fetal dopplers actually work.

At the foundation is the Doppler Effect—the same principle that makes a passing siren change pitch. A fetal doppler’s transducer emits continuous, high‑frequency ultrasound waves in the 2–3 MHz range. When these waves encounter moving targets—like red blood cells coursing through the fetal heart or umbilical cord—the reflected frequency shifts slightly. The device captures this frequency delta and translates it into sound, producing the rapid “whoosh‑whoosh” heartbeat that parents recognize.

While most handheld fetal dopplers operate between 2 MHz and 3 MHz, the choice of frequency carries practical trade‑offs. A 2-MHz probe penetrates deeper, making it more effective for women with higher BMI or later gestational stages. A 3-MHz probe offers crisper resolution at shallower depths, often preferred in early pregnancy when the fetal heart is closer to the abdominal surface. Engineers balance these parameters to optimize sensitivity without sacrificing safety, illustrating how MHz selection is more than a specification—it’s a design decision rooted in anatomy and physics.

Most handheld dopplers rely on CW ultrasound. One crystal transmits continuously while another receives, creating a steady stream of reflections that can be converted into audio. In contrast, diagnostic imaging systems use pulsed wave (PW) ultrasound, which alternates between sending and receiving. PW enables depth resolution and visual mapping (seen in B‑mode scans), while CW is limited to audio feedback without imaging.

Figure 2 Compact fetal doppler monitors fetal heart rates during routine examinations for obstetricians, midwives, and expectant mothers. Source: pregnancy & baby.ie

Finally, the role of acoustic impedance is critical. Air is a poor conductor of high‑frequency sound, scattering waves before they reach tissue. That’s why ultrasound gel is indispensable: it eliminates air pockets, minimizes impedance mismatches, and ensures efficient coupling between probe and skin. Without gel, the doppler’s signal would degrade, making detection unreliable.

In essence, fetal dopplers are elegant demonstrations of applied physics—transforming MHz‑range ultrasound reflections into audible signatures of life, while highlighting the trade‑offs between sound and image that engineers must balance.

Gestational timeline and anatomical confounders

The physics of doppler ultrasound only tells half the story. The other half lies in how pregnancy anatomy changes over time, shaping when and how a fetal heartbeat can be detected.

In the first trimester (8–11 weeks), the uterus remains tucked deep within the true bony pelvis. This positioning makes acoustic detection extremely difficult, even with medical‑grade equipment. Around weeks 12–14, the uterus ascends into the abdominal cavity. Once it rises above the pelvic brim, the fetal heart becomes more accessible to a transducer probe, marking the point when at‑home dopplers begin to consistently pick up sound.

Here, probe frequency plays a role. A 3-MHz probe is often favored in early pregnancy, when the fetal heart lies closer to the abdominal surface, offering sharper resolution. By contrast, a 2-MHz probe penetrates deeper, making it more effective later in gestation or in cases where maternal tissue density is higher. This frequency choice interacts directly with anatomy, underscoring how engineering design must adapt to biological variation.

Even within this window, anatomical confounders can complicate detection. An anterior placenta—positioned at the front of the uterine wall—acts like an acoustic muffler, dampening returning signals. Maternal tissue density or higher BMI increases the distance ultrasound waves must travel, attenuating their strength. And a retroverted uterus, tilted backward rather than forward, alters the probe’s angle of approach, requiring more patience and precision.

Understanding these variables is crucial. They explain why a heartbeat may not be immediately audible, and they help reduce unnecessary panic when silence meets the probe. For engineers, these confounders highlight the importance of sensitivity, calibration, and acoustic design in consumer doppler devices.

Acoustic differentiation: The audio signatures

One of the greatest challenges in at‑home doppler use is not the physics of ultrasound, but the interpretation of what you hear. Misidentifying maternal blood flow as the baby’s heartbeat—or vice versa—can lead to false reassurance or unnecessary panic. Engineers and clinicians alike emphasize the importance of recognizing distinct audio signatures.

Fetal cardiac activity typically ranges between 110–160 beats per minute (BPM). The sound is rapid, crisp, and rhythmic, often likened to a galloping horse or a distant locomotive. Its pace and clarity distinguish it from slower maternal rhythms.

By contrast, the placental souffle is the sound of maternal blood rushing through uterine arteries. It matches the mother’s pulse rate—usually 60–100 BPM—and presents as a soft, low‑pitched, synchronous “swishing” or “swooshing.” This can easily be mistaken for fetal activity if the listener isn’t trained to note the slower cadence.

A third signature comes from umbilical cord flow. Blood traveling through the umbilical arteries matches the fetal heart rate but produces a sharper, mechanical “whistling” or “whooshing” rather than a distinct cardiac thump. It’s rhythmic and fast, but its tonal quality differs from the gallop of the heart itself.

For engineers, these distinctions highlight the need for filtering algorithms and signal processing that can help separate overlapping sounds. For families, they underscore why professional guidance matters: the heartbeat is more than just a sound—it’s a signal embedded in a complex acoustic environment.

Regulatory frameworks and the ALARA principle

Beyond physics and anatomy, fetal dopplers exist within a regulatory framework designed to protect users. The FDA has long emphasized that these devices should be used only by or under the supervision of healthcare professionals. Their concern is less about the ultrasound waves themselves—which are generally safe at diagnostic levels—and more about the risks of misinterpretation and delayed medical care.

For engineers, the guiding ethic is the ALARA principle: As Low As Reasonably Achievable. This concept, borrowed from radiation safety, applies equally to ultrasound. It means designing devices and usage protocols that minimize exposure while still achieving reliable detection. In practice, ALARA drives decisions about output power, duty cycles, and probe design. It also informs recommendations for short listening sessions rather than prolonged scanning.

By embedding ALARA into design philosophy, manufacturers balance accessibility with responsibility. The principle reminds us that even safe technologies demand respect: every extra milliwatt of acoustic energy, every unnecessary minute of scanning, is exposure that can—and should—be reduced. For clinicians, ALARA is a usage guideline; for engineers, it’s a design imperative. Together, they ensure that fetal dopplers remain tools of connection and reassurance without compromising safety.

Engineering the handheld doppler

From regulatory guardrails to circuit realities, the handheld doppler’s design chain shows how safety principles translate into hardware decisions.

Behind the familiar “whoosh-whoosh” lies a carefully tuned hardware chain. Designing a handheld fetal doppler means building an analog front end (AFE) optimized for continuous-wave architectures in the 2–3 MHz band. A 3-MHz probe enhances sensitivity for shallow signals in early gestation, while 2 MHz penetrates deeper for higher-BMI patients.

Figure 3 A waterproof 3-MHz fetal probe supports early pregnancy monitoring. Source: Newman Medical

Most handheld probes use a dual-element piezoelectric transducer to isolate the signal paths. On the transmit side, high-frequency driver circuits actuate the dedicated transmit crystal with high efficiency. On the receiver side, a dedicated low-noise amplifier (LNA) connected to the receive crystal pairs with an in-phase/quadrature (I/Q) demodulator to extract microvolt-level return voltages from abdominal tissue.

Once reflections are demodulated into the baseband audio spectrum (< 3 kHz), a low-power microcontroller or DSP running real-time autocorrelation filters out maternal vascular artifacts to calculate fetal heart rate. Safety remains the hard boundary: strict isolation barriers and capped driver thermal limits ensure acoustic intensity stays below 20 mW/cm² to align with ALARA principles.

Wrap‑up: Fundamentals in action

Fetal dopplers are more than sentimental gadgets. They are living demonstrations of applied physics, anatomy, and acoustic engineering. From MHz‑range ultrasound reflections to uterine ascent and placental positioning, every heartbeat heard at home is shaped by a complex interplay of science and structure.

The audio signatures—galloping fetal rhythms, placental swooshes, and umbilical whistles—remind us that listening is not the same as diagnosing. And the regulatory guardrails, anchored in the ALARA principle, ensure that connection never comes at the cost of safety.

For engineers, this is a case study in design trade‑offs: CW simplicity versus PW precision, consumer accessibility versus clinical calibration. For families, it’s a reminder that reassurance must always be paired with professional guidance.

Well, whether you are a parent marveling at the sound of life or an engineer refining the next generation of devices, carry forward the fundamentals. Respect the physics, honour the anatomy, and design—or use—technology with safety at its core. That is how prenatal listening becomes not just a moment of wonder, but a responsible practice rooted in science.

Every heartbeat heard is physics in practice—a reminder that fundamentals aren’t just theory, they’re life itself.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Electronics For Medical Devices
• Developing GUIs for medical equipment
• Addressing Challenges of Medical Electronics
• Streamlining the design of portable medical electronics
• Adopting An SOC-based Approach to Designing Handheld Medical Devices

The post Fetal dopplers: Physics, anatomy, and audio signatures of prenatal listening appeared first on EDN.

What good is a non-networked water sensor? Still pretty good, as long as its existence, and specifically its embedded battery’s inevitable impermanence, are things you remember.

Back in March, I detailed the initial setup and ongoing usage impressions for a wireless sensing setup for my sorta-“smart” home, comprising TP-Link’s Tapo H100 smart hub.

Tapo T315 hygrometer (also available in a display-less option).

And Tapo T300 water (and other fluids) leak sensor.

The latter replaced a Gentronics model BWD-HWA leak sensor that had long sat at the base of our downstairs water heater, accompanied in the following photos by a 0.75′′/19.1 mm diameter U.S. penny for size comparison purposes.

As to why I made the hardware swap, here’s an excerpt from that initial March coverage, specifically discussing the original non-networked sensor.

Note, however, this bit in the operating instructions:

Replacing the battery: Replace the battery if the alarm has operated for an extended period of time, or if the battery expiration date is approaching. You may want to mark the battery expiration date on a piece of tape and attach it to the alarm when you install the battery.

Let’s be real. I know myself well enough to realize that once I set it, I’m going to forget it. I was admittedly surprised to learn, after replacing it (more accurately, moving it; it now sits below the whole-house water filter enclosure in a different room) that unlike my carbon monoxide detectors at their end-of-life dates, it didn’t at least chirp when its battery was getting low. That said, we’d only hear the sound if we were there at the time, and assuming it was loud enough to capture our attention. And further to that point, more generally, if we were away when a leak started, we’d be blissfully ignorant of what was going on…at least at first, until we returned home, that is.

As mentioned above, I originally just moved the original device elsewhere, replacing it at the water heater with the Tapo T300. That said, I eventually replaced the original in its new location with a Tapo T300, too, since the whole-house water filter is in a storage area with a normally closed, sound-muting door, and since the Tapo T300 successor is inexpensive (sub-$20).

The leak detector that time forgot

Earlier this year, we got the upstairs hardwood floor resurfaced, and in preparation I rolled forward the kitchen refrigerator. Imagine my surprise to find another Gentronics BWD-HWA “Watchdog” Water Alarm behind it! The plumber had done a flurry of initial work when we moved into the residence, also including hooking up the water line to the new refrigerator for icemaker-feeding purposes, and apparently (and wisely) put a leak sensor there, too. While I could claim that I’d not been aware of its presence until now, more likely is that he’d told me about it and I’d promptly then forgotten not only about the need to periodically change its batteries but more broadly about its very existence.

Unsurprisingly, as exemplified by the barely audible “bark” (normally, quoting from the product page on the company website, a “piercing, 110 dB alarm”) when I used a moistened finger to span the “Watchdog’s” under-side electrical contacts, its 9V cell was nearly dead.

I promptly ordered a third Tapo T300 to succeed it. And since I now had two legacy leak sensors on my hands, I of course then decided to take one of them apart. Here’s where the now-drained battery used to be, behind a slide-away cover.

And here was a slick-feature surprise, at least to me. The panel containing the electrical contacts was removable, leading to its potential relocation up to 6 feet away from the base unit.

Had I seen the product web page in advance of the teardown, I might have realized this earlier (in my slight defense, I don’t remember getting any instructions; then again, I don’t remember getting the device itself, either, so…).

That said, I’m not sure what the manufacturer means on that same web page by this phrase (bolded emphasis is mine).

The alarm includes 6 feet of wire, which can be extended up to 100 feet, allowing the sensor to be used in hard-to-reach places.

Span extension mention = dissection invitation?

I don’t see any way to detach the wire harness from the contacts ends for length-augmentation purposes. Surely, they don’t recommend taking the base unit apart, do they?

Just in case they do, though, I’m taking it as an implied disassembly solicitation (or at least sanction). The three back panel screws you may have noticed in an earlier photo are first to go.

With them out of the picture, the back panel comes right off.

Let’s focus on the “meat” of the hardware.

The three clips that hold the PCB in place detach straightaway.

Flip the PCB over, and its frontside comes into clear view.

Maybe I’m just being dense, but I still don’t see how to extend the wire harness beyond its 6’ default span in a consumer masses-friendly fashion.

I’m sure you’ve already noticed the alarm buzzer dominating the landscape. Aside from that, a discrete transistor (see the above image) and a smattering of passives, the only other notable thing to “write home about” is this IC, a Texas Instruments CD4069UB hex inverter.

And that’s as far as I’m going to go today. Even though these legacy leak sensors aren’t particularly “smart”, they’re still perfectly usable. As such, they’re destined for donation, to serve someone else far into the future. I’ll close with my usual invitation for reader observations in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• The Tapo Hub: TP-Link joins the low-bandwidth, long-range RF club
• Smart hygrometers: Still largely useful even without integrated visual monitors
• TP-Link’s Tapo H100: Smart sensing unencumbered
• TP-Link’s Tapo T300 sensor detects water and other liquid-leak dangers
• Disarming a carbon monoxide detector

The post Disassembling a low-tech liquid-leak detector appeared first on EDN.

There are several ways to boost a relatively low voltage by a factor of two or three, or even hundreds—but there are also many risks.

Part 1 of this high-voltage article series discussed configurations that boost the voltage, but they can only go so far. Instead, what are called voltage “multipliers” can push voltages to much-higher values. The design and considerations change dramatically when the output voltage starts going about 100 V and then into the >1000 V range.

Fortunately, many of these higher-voltage systems need only modest current (100 mA or less) which simplifies the problem somewhat. Applications for these truly high voltages include X-ray machines, physics experiments, beam steering, electric-field shaping, lightning simulation, electrostatic tests, and many more – it’s more common than many people realize.

The obvious question is why can’t you just use a transformer with suitable turns ratio to multiple the input voltage by 10× or 1000×, or whatever is needed? In theory, you could. But as the turns ratio and secondary voltage increases, there are issues of additional inefficiency due to transformer losses (perhaps acceptable), and high-voltage breakdown of the wire insulation, among others. This does not mean it can’t be done, but it can be a difficult approach due to practical considerations.

The transformer approach been used commercially in many applications with a configuration called a flyback converter (Reference 1), such as for the cathode-ray tube (CRT) of the mass-market TVs that dominated the video world for over 50 years until the LED/LCD flat panels took over) The flyback design uses a special transformer which is a wound as a combination of a transformer, plus an inductor to store energy.

However, there are various topologies which use passive components to multiply an input voltage. In general, they rely on a combination of diodes and capacitors in a series of stages to leverage the voltage of the previous stage. These voltage multipliers are specialized rectifier circuits which develop an output voltage which is (in theory) an integer times the AC peak input, for example, ×2, ×3, or ×4 times the AC peak input value. They are usually configured as a stack of half or full-wave rectifiers.

For example, the circuit of Figure 1 shows a three-stage multiplier. The action is as follows: each cycle of the AC input charges the various capacitors, and each capacitor is eventually charged by successive AC cycles to the peak value of the input sine wave. Thus, for a 120 VAC rms line voltage, the peak is 170 V. By doing this across the multiple capacitors – each charging independently – and then allowing these capacitors to be stacked in series, the output voltage is the sum of the individual capacitor voltages.

Figure 1 In the basic voltage-multiplier configuration, a ladder of capacitor-diodes arranged as rectifiers is used with the capacitor charging from the AC line and then adding their voltages in series at the output. (Image source: Spellman High Voltage Electronics Corporation)

There is no tangible or visible switching in this arrangement, yet it goes from charging to stacking of stored voltage in a standard rectifier arrangement. The diodes act as passive switches and prevent discharge of the capacitors when the input voltage starts to drop. They allow current flow to the capacitors, but not flow from the capacitors back to the input source. And if you need a negative high voltage from a multiplier, that’s only easy thing about high-voltage multipliers: simply reverse the polarities of all the multiplier diodes and capacitors to produce a negative version.

These multiplier configurations seem easy enough to implement but they are not. First, the diodes and capacitors must have a minimum reverse-breakdown voltage rating of at least twice the peak voltage across them. Even if you are starting with a 120 VAC line (170 V peak), you’d need components rated for at least 1700 V if you are building a 10× multiple (plus a factor of ×2 or more for safety margin, of course).

There are also other issues in a high-voltage designs such as these. First, they can deliver very little current at that high voltage: once you begin to draw current for the for the load, the stored charge and thus the voltage drops. In many cases, this is too restrictive, since many higher-voltage applications need only small amount of current, for example, to create an electric field.

Also, the physics of the high-voltage world has many points at which “strange” things happen; increasing the voltage is not a linear situation. Think of it as analogous to water crossing the temperatures where freezing or boiling occurs. For example, high voltage circuits will have corona discharges from sharp points. These are both hazardous in themselves, and they also cause pitting of metal contacts and can punch through insulators.

Even “small things” such solder joints are an issue for corona. You might assume a standard, well-made solder joint would be OK, but it will act as a starting point for corona discharge. Therefore, “ball soldering” is frequently used instead in the high-voltage implementation using large, spherical solder connections (Figure 2). The large-diameter, smooth spherical shape of the solder connection helps to control the local E-field, thus suppressing the generation of corona.

Figure 2 In the high-voltage word, every aspect of the physical construction is critical: a standard solder joint will encourage corona discharge, so the joints must be made as balls without corners. (Image source: Maker Forums)

If you are tempted to build your own high-voltage circuit, think about it very carefully. It’s probably not a good idea, because there is so much more to it than just the schematic diagram and the bill of materials (BOM), and that BOM itself has truly unique parts.

It is a truly dangerous world where just “being careful” is not enough, and even the slightest mistake or oversight has deadly consequences. Physical spacing, component ratings, insulation properties, pinhole imperfections, and material breakdown are just some of the many issues. Circuit protection is also unique: specialty fuses and other overvoltage/overcurrent devices are essential.

Not surprisingly, that doesn’t stop people from doing so, as seen in the posting which shows someone building a multiplier going into the tens of kilovolts (Reference 5).  Don’t try this at home (or even in the lab) unless you have someone with you is experienced in high-voltage construction (and can call for help – although it usually too late at that point!). Finally, there are the complicated regulatory issues if you intend to produce and sell the product.

There are many examples of high-voltage multipliers used in attention-getting projects. For example, a team at MIT recently built and tested an aircraft with a wingspan of a few meters but with no moving parts (Figure 3, details are in References 6 and 7). Instead, it uses the flow of negative ions attracted by high-voltage, positive electrostatic field across the wing rear edge.

Figure 3 High voltages are key to some very unusual applications, such as this MIT aircraft, which is propelled by a stream of ions across the wing; the ions are attracted to the 20-kV “fence” at the trailing edge of the wing. (Image source: MIT)

This non-tethered, free-flying aircraft has an on-board battery (nominally at 200 V DC) for its 600-W power supply (Figure 4, designed by the Power Electronics Research Group in the MIT Research Laboratory of Electronics). It uses a switching regulator followed by a 1:15 step-up transformer, and then a six-stage, full-wave “Cockcroft-Walton” voltage multiplier to deliver 20 kV DC (see References 8 through 10).

Figure 4 Within the MIT aircraft is a DC/DC power subsystem which converts 200 V DC from on-board batteries into an AC waveform, then transforms it to 20 kV DC using the Cockcroft-Walton multiplier topology. (Image source: MIT)

Cockroft-Walton multipliers play a very large role in advanced physics experiments, often used as initial “injectors” for various particle accelerators. The 750-kV unit of Figure 5 was commissioned in 1975 at CERN and was recently retired. Larger units can now reach up to the single-digit megavolt range.

Figure 5 This Cockroft-Walton generator at CERN produces up to 750 kV; it’s definitely not a “desktop” unit, as it is about 12 feet (~3 ½ meters) tall. (Image source: CERN)

The world of high-voltage boosters and multipliers is a strange yet important one. Some of these architectures result in modestly higher voltages, and some reach into kilovolt range. As voltages go beyond about 60 V, issues of safety become a concern. As they go into the hundreds and thousands of volts, additional issues of material characteristics and electrical phenomena show that design and construction for these levels is a very different world.

References:

1. Wikipedia, “Flyback converter”
2. Spellman High Voltage Electronics Corporation, “High-Voltage Reference Manual”
3. All About Circuits, “Voltage Multipliers (Doublers, Triplers, Quadruplers, and More)”
4. Instructables, “High Voltage Multiplier”
5. MIT, “MIT engineers fly first-ever plane with no moving parts”
6. MIT Electric Aircraft Initiative, “MIT engineers fly first-ever plane with no moving parts in propulsion system”
7. Georgia State University Hyperphysics, “Cockroft-Walton Accelerators”
8. Wikipedia, “Cockcroft–Walton generator”
9. Wenzel Associates, TechLib, “Cockcroft-Walton voltage multipliers”
10. CERN, “The 750kV Cockcroft-Walton generator and Faraday cage”

—Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors and signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing, and he also developed significant mechanical-engineering insight while designing control electronics for large materials-testing systems.

Related Content

• High-Voltage Design: Living Long and Still Prospering
• Pulsed high-power systems are redefining weapons
• Learning to like high-voltage op-amp ICs
• Rich voltage, poor voltage: My incandescent tale

The post Creating higher voltages, part 2: Voltage multipliers appeared first on EDN.

Interim steps to the end destination are often a wise policy, economically if for no other reason. And, it turns out, non-bleeding-edge gear can be made wiser in the process, too.

As recently mentioned, I shortly plan to begin migrating my LAN from 1 to 2.5 GbE (and 10 GbE in some spans). That said, to be clear, I don’t plan to do so in one fell swoop. And frankly, I may never complete the transition.

Most of my LAN clients connect to either the main router or mesh points over wireless, and it doesn’t make sense to update any switch hardware tethered to them until they’re upgraded beyond the Wi-Fi 5-plus-1 GbE backhaul technology threshold. And even if a LAN client hooks into the LAN fully in a wired fashion, most of them are 1 GbE-only.

There are exceptions, of course; my Apple Mac Studio in the office is 10 GbE-supportive, and I’ve upgraded the highest-end of my three QNAP NASs in the furnace room below it for 10 GbE cognizance, too. And then there are the multiple MoCA 2.x adapters, one in the furnace room, that I may reintroduce in the future. Perhaps obviously, therefore, the multi-port switches in both locations will get upgraded first; if the Cat 5e span between them turns out not to be 10 GbE-reliable, I’ve got 50 feet of optical cable and two SFP+ modules ready to replace it.

For the switch in the furnace room, sitting right next to the router and cable modem, and therefore acting as the LAN nexus, the mix of legacy and more modern, higher speed clients proved to be manageable in combination with an open-box (truly so, it turned out; never unpacked, far from used) Zyxel device, the XGS1010-12, that I bought for $49.99 on eBay.

As you can see from the photo, it baseline-integrates eight 1 GbE ports, the same quantity and speed as with the switch I’m currently using, a TRENDnet TEG-S81g. But there are also two 2.5 GbE ports, along with two 10G SFP+ cages. Not only will the XGS1010-12 expand my total port allotment at that location, its RJ-45 and SFP+ additions will deliver higher speeds, too. And, it turns out, another pleasant surprise also awaited me post-purchase.

Switch types

Both my existing switch and the Zyxel XGS1010-12 are unmanaged, meaning (to quote Wikipedia) that they have no configuration interface or options. They are plug and play. They are typically the least expensive switches, and therefore often used in a small office/home office environment. Although likely running firmware, it’s usually non-upgradeable, and no settings or broader graphical user interface (GUI) exist for the user to access, either. Therein the lack of a MAC address on my XGS1010-12’s underside.

Managed switches, on the other end of the spectrum, are (as the name implies) user-configurable and -updateable. Why would you want such a thing? One example is virtual LAN (VLAN) support, the ability to isolate various clients (and clusters of them) so that they can’t access other client groups and, in some cases, the WAN either. One well-known example here is the “guest network” feature bundled with many modern routers, which provides visitors with the ability to use the Internet without allowing them to “see” devices on the main LAN.

You might also want to, for example, be able to isolate “smart home” IoT devices from the rest of the LAN so that, should one of them get hacked, the infection can’t then spread elsewhere. Managed switches also enable you, for example, to prioritize traffic flowing through a particular port (for VoIP applications, say), to hard-wire various ports’ bandwidth and duplex settings, to implement MAC filtering and other network access rules, to aggregate multiple ports for the same connection (to a multi-port NAS, for example), and to more broadly monitor real-time network traffic conditions, along with other features.

And between these two extremes is the “smart” switch, implementing a subset of the fully managed switch’s capabilities, across a subset of the total available ports, but in a more user-friendly fashion. Take, for example, the front panel multi-position configuration switch offered with this low-priced Tenda device.

The lion in sheep’s clothing

All of which leads to the XGS1010-12’s managed “big brother”, the XGS1210-12. Notice the familial name similarity? They could, in fact, be twins, judged by their visual commonality (aside, of course, from the respective product names on the front panels, and the MAC address stamped on the XGS1210-12 underside).

It turns out, in fact, that the hardware allotment is identical between the two, aside from one other front panel deviation; the XGS1210-12 extends a PCB-mounted reset button to the exterior for easy user access. They otherwise differ (I’m speaking specifically of my XGS1010-12 with hardware version A1; hold that thought) only in the software running inside. Have you guessed yet where this tale is headed?

After purchasing the XGS1010-12 unmanaged switch, and while waiting for the eBay to ship it to me, I did a Google search on the product code to see what else I could find out about it. Near the top of the results page, I excitedly learned, was a Reddit post (along with subsequent follow-up posts from the original poster, and broader r/homelab community discussion) describing how to hack the XGS1010-12 and upload the XGS1210-12 firmware to it, converting it to the managed-switch version in the process.

“But Brian,” you might be thinking right about now, “I thought you said that unmanaged switches don’t have user-accessible GUIs?” I did, actually, but I never said anything about a command-line user interface (CLI), did I? What Redditor zeda1ert realized was that in-between two of the side passive airflow vents was a standard UART console header.

The Reddit post has detailed instructions; you’ll see in the ensuing conversation that three years later I chimed in with a bunch of questions. Fortuitously, zeda1ert was still monitoring the post and graciously helped me. The following few paragraphs summarize the process.

Connect a USB-UART adapter (I own both this 3.3V one and this 5V one and can use either, because the switch’s 3.3-V UART circuitry is self-powered, so only the adapter’s Tx, Rx and GND need to be hooked up, although the latter’s cable is conveniently longer) to the switch and your computer, start up a CLI terminal session (I used MacOS’s built-in command-line “screen” utility), and issue a timing-critical ESC to terminate the switch’s boot sequence before it finishes.

Now configure a MAC address for the switch, along with static IP addresses for both the computer and switch (different, but on the same subnet), then fire up a TFTP server session on the computer (MacOS has a built-in one, but it’s also command line-based and fairly cryptic, so I instead went with SoftPerfect’s excellent freeware GUI utility, which I’ll include in the next best-of list). Use it to download and install the most recent v1 XGS1210-12 firmware to the switch. Then reboot, and the switch is now managed.

And speaking of “re”(boot), the missing hardware “re”set button isn’t a problem in practice, as you can alternatively accomplish the same reset outcome through either the switch’s CLI or GUI.

Hardware fortuity

I’d earlier explicitly noted that mine was an A1 hardware version unit. The distinction was initially important, and remains so for “stock” firmware, although broadly no longer (stay tuned). Partway through its ongoing product life, Zyxel redesigned the XGS1010-12, switching from Realtek’s RTL8226 2.5 GbE PHYs to the newer RTL8221B with reduced power consumption, therefore also lower heat dissipation.

Unfortunately, this caused an incompatibility with the legacy firmware for the XGS1210-12, which wasn’t similarly hardware-updated. Installing XGS1210-12 firmware on a version B1 XGS1010-12 resulted in nonfunctional multi-gig ports.

A further nuance involves the various A1 revisions, A, B, and C. Originally, it was not possible to install any newer v2 XGS1210-12 firmware (patch 0 link, patch 1 link with OpenSSL vulnerability fix) on a version A1, revision C XGS1010-12 unit such as mine.

Scroll down in the Reddit thread, though, and you’ll see that another contributor later figured out how, via resistor relocation, to spoof the board identifier, enabling successful v2 firmware update. But I haven’t bothered doing so, because I have a more robust alternative next step planned for eventual implementation.

Open source once again saves the day

Three years back, when the original Reddit thread post was published, OpenWrt development for the XGS1010-12 was immature and insufficiently staffed, with the resulting available build functionally incomplete. A lot has changed since then, notably including the inclusion of support for version B1 units’ RTL8221B PHYs (in spite of Realtek’s longstanding and ongoing open-source reticence) beginning in mid-2026.

Right now, the v1 “stock” XGS1210-12 conversion does everything I need, and since the switch isn’t exposed to the Internet, I’m not worried about its ongoing “Heartbleed” OpenSSL compromise. But at some point, I’ll probably take the plunge and further migrate to OpenWrt instead. If and when I do so, I’ll report the result here in the form of another blog post. And until then, I as-always welcome your thoughts in the comment on what I’ve discussed in this post!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• The multi-gig migration: Motivations and implementations
• NAS upgrades: proprietary lockouts and surmounts
• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• SFP: Add-in module delivers diminutive performance, flexibility
• Heartbleed: the wakeup call the open-source community needed?

The post Hacking a network switch for management enhancements appeared first on EDN.

Defense-grade Agilex FPGAs and SoC FPGAs from Altera operate reliably in harsh environments across a temperature range of -55°C to +125°C. Leaded-ball and ruggedized packaging options are designed to withstand temperature cycling, vibration, and shock in mission-critical aerospace and defense applications.

The defense-grade devices will span Altera’s entire Agilex portfolio, from cost-optimized Agilex 3 FPGAs to mid-range Agilex 5 and high-performance Agilex 7 and Agilex 9 Direct RF-Series FPGAs. The portfolio addresses varying requirements for performance, power efficiency, and integration in applications ranging from embedded processing to high-bandwidth communications, sensing, and electronic warfare. A common architecture lets designers adapt their systems as mission requirements evolve.

Altera’s HyperFlex architecture uses Hyper-Retiming and Hyper-Pipelining to balance pipeline delays and shorten critical logic and routing paths. These techniques enable higher clock frequencies and greater processing throughput.

Fabrication in the United States provides a domestic source of wafer production, supporting supply-chain resilience for aerospace and defense programs with long service-life requirements.

Initial shipments of defense-grade Agilex FPGAs are scheduled for Q1 2027. Contact an Altera sales representative for additional information.

Altera

The post Altera extends Agilex FPGAs to defense systems appeared first on EDN.

The Synaptics Astra SR200 series of xMCUs runs multimodal AI workloads without the memory and compute limitations of conventional MCUs. Devices combine heterogeneous, AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of Mbytes. This allows larger AI models and richer multimodal workloads to run entirely on-device.

Powered by Synaptics’ Torq AI engine with Google Research’s transformer-capable Coral NPU, the xMCUs deliver up to 400 GOPS of AI inference. They also feature Arm Cortex-M85 and Cortex-M52 cores, integrated vision and audio capabilities, and hardware-rooted security. A tiered architecture pairs up to 8 Mbytes of SRAM with extensible, high-bandwidth, high-capacity custom DRAM. Synaptics says this architecture runs workloads at one-third the power of typical system DRAM.

The Astra SR200 series comprises three pin-compatible product lines sharing a common hardware foundation and SDK. The SR210 reaches 200 GOPS for always-on voice and sensing; the SR230 adds vision, display, and optional audio at 300 GOPS; and the SR250 provides 400 GOPS with dual vision and display paths for demanding edge applications.

Locate a distributor or sales office here.

Astra SR200 product page 

Synaptics

The post MCUs accelerate multimodal edge AI appeared first on EDN.

Microchip’s POL-05-20S-T GaN point-of-load converter delivers up to 20 A of continuous current to power FPGAs, MCUs, and other processing-intensive digital loads in space. The radiation-tolerant device uses GaN power HEMTs to achieve high efficiency and power density in a compact, lightweight form factor, helping engineers meet the size, power, and energy constraints of onboard processing systems.

A synchronous buck topology with current-mode control provides fast transient response and stable operation. The 4.75-V to 13.2-V input range and adjustable 0.7-V to 5-V output accommodate multiple power rails and system architectures.

The POL-05-20S-T’s electrical parameters are specified before and after irradiation up to 50 krad(Si), and its single-event effects (SEE) have been characterized up to a linear energy transfer (LET) of 43 MeV·cm²/mg. The converter operates at full load over a temperature range of −55°C to +100°C.

Housed in a 1.51×1.51×0.45-in. surface-mount package, the POL-05-20S-T is now available in production quantities.

POL-05-20S-T product page 

Microchip Technology 

The post Rad-tolerant GaN converter powers space electronics appeared first on EDN.

BrainChip’s Sequora processor IP core runs generative AI and large language models (LLMs) directly on battery-powered edge devices, such as earbuds and sensor nodes. It pairs with the company’s Akida neural processor IP to handle complementary AI workloads.

Akida processes streaming sensor data, including vibration, audio, radar, raw RF IQ data, and biological signals. Sequora runs generative and sequential AI tasks, from on-device LLM inference to voice-to-voice interaction and AI agents. It is optimized for state-space models (SSMs), which maintain a fixed-size state to represent input history, keeping memory requirements constant regardless of sequence length. This architecture suits generative AI workloads on resource-constrained edge devices.

Sequora uses a unified multiply-accumulate (MAC) array for both signal processing and neural-network computation, eliminating the need for a separate DSP preprocessing stage. Its instruction-set architecture (ISA) also allows new algorithms to be deployed through software updates.

Sequora is available now as licensable semiconductor IP, delivered as process-portable, fully synthesizable RTL. The package includes verification IP, synthesis scripts, and an SDK with a compiler, C++ runtime library, and model zoo.

Sequora product page 

Brainchip Holdings   

The post Processor IP brings generative AI to edge devices appeared first on EDN.

AMD Helion is a rack-scale reference design for agentic AI infrastructure, combining open-source hardware and software. The design accommodates CPU-only configurations for hyperscale deployments and CPU/GPU configurations for enterprises. Based on Open Compute Project (OCP) specifications, the Helion 21-in. rack architecture lets customers balance CPU and GPU performance, core density, and power consumption to meet their application requirements.

A CPU-only rack can be powered by AMD EPYC processors supporting up to 32,768 Zen 6 x86 CPU cores. The all-in-one rack integrates AMD EPYC CPU nodes, up to 16 AMD Instinct MI350 GPU nodes, and general-purpose compute. A token router directs inference requests to frontier models in the cloud or open-source models running locally in the rack.

AMD plans to contribute the Helion specification to OCP for community development and adoption. Rack configurations are under development with ecosystem partners, with availability planned for November 2026.

Helion product page

AMD

The post AMD defines rack-scale infrastructure for agentic AI appeared first on EDN.