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Despite advances in healthcare technology, blood pressure measurement has largely remained unchanged for decades. Across hospitals, clinics, and homes, cuff-based devices continue to be the primary method for monitoring cardiovascular health.

While this method is clinically accepted, it provides only occasional measurements, needs user involvement, and does not facilitate continuous monitoring. Consequently, important information on conditions such as nocturnal hypertension, sudden spikes, stress-related changes, and long-term cardiovascular trends often goes unnoticed.

This limitation is becoming critical as healthcare shifts toward prevention, remote monitoring, and continuous health insights. The idea of measuring blood pressure passively and continuously with wearable technology has emerged as an exciting area in digital health.

However, monitoring blood pressure without a cuff is more complicated than just switching the inflatable cuff for a wearable sensor. This presents a difficult challenge in biomedical engineering that requires merging sensor technology, understanding physiological signals, using smart algorithms, designing hardware, and conducting clinical tests.

Why cuffless BP monitoring matters

Continuous visibility of blood pressure could change how healthcare is delivered. For patients with high blood pressure, single readings often do not reflect the true variations in cardiovascular activity throughout the day. Moreover, cuffless monitoring may also be especially useful for screening people who do not know they have high blood pressure. So, a passive monitoring system could enable earlier interventions, better therapy adjustments, and improved chronic condition management.

Cuffless devices are generally more comfortable than traditional cuffs because they avoid inflation and noise, which can reduce the burden of repeated checks. In remote patient care, non-intrusive blood pressure tracking could enhance care at home while reducing reliance on periodic manual checks, though validated cuff-based monitors are still recommended for accurate hypertension management.

Consumer wearables have already made continuous heart rate and oxygen saturation monitoring common. However, blood pressure remains one of the most clinically valuable yet technically challenging physiological parameters to measure continuously and accurately. Successfully overcoming this challenge would mark a significant advancement in enabling truly intelligent and continuous cardiovascular monitoring.

The engineering challenge behind the vision

Unlike heart rate, blood pressure cannot be measured directly with a single optical or electrical sensor in a wearable device. Instead, cuffless estimation depends on interpreting indirect physiological signals that relate to blood vessel behaviour.

Calibration adds another layer of difficulty. Many cuffless methods need initial reference measurements from traditional cuff-based devices. However, physiological traits can change over time due to aging, hydration, medication, illness, and activity levels, making it hard to maintain long-term accuracy. A system that works for one person may not apply well to a larger population.

This is why cuffless blood pressure monitoring remains one of the most challenging areas in wearable healthcare.

A practical engineering path to cuffless BP device innovation

One of the common difficulties faced in medical technology innovation is attempting to solve product-scale problems before fully understanding the underlying technical uncertainties. Cuffless blood pressure monitoring requires a more structured engineering approach that prioritizes validation of core physiological assumptions before committing to long-term architectural decisions.

A practical path begins with understanding whether available physiological signals can reliably support meaningful blood pressure estimation. This requires careful exploration of signal accessibility, synchronization accuracy, feature extraction quality, calibration methodologies, and algorithm performance under realistic operating conditions.

At this stage, the emphasis is not on building a commercial product, but on establishing technical confidence in the signal-to-estimation pathway. Early studies also need to plan for the large content of physiological data being generated, transmitted, and securely stored, since cuffless devices can create substantial amounts of health data.

Raw physiological data must be collected, processed, and analyzed to identify stable correlations between measurable biosignals and blood pressure behaviour. Algorithmic approaches whether deterministic or AI-assisted must be evaluated against reliable reference measurements to understand their practical limitations.

Critical engineering questions emerge early. Can the selected biosignals consistently support accurate estimation? Which signal combinations remain robust under motion, physiological drift, and environmental variation? How much calibration dependency exists and can performance generalize across broader user populations?

Resolving these questions early helps shape sound architectural decisions, reduce avoidable development risk, and create a stronger foundation for eventual product realization.

Why custom hardware becomes necessary

While existing wearable platforms help speed up feasibility studies, they also have significant technical limitations. Consumer-grade wearables are usually designed for wellness applications, not precise physiological measurement.

Access to raw synchronized data may be limited. Control over sampling rates, signal quality, analog front-end behaviour, and timestamp accuracy can be insufficient. These limitations become crucial when estimating blood pressure relies on subtle timing, such as pulse transit time, where accuracy is key.

As technical feasibility becomes more defined, the next step is to move to a custom hardware platform.

Custom hardware enables optimization on multiple levels. Sensor choice can be tailored specifically for blood pressure estimation, and the device features it depends on, rather than general wellness monitoring. The design of the analog front-end can be adjusted for better signal quality, reduced noise, and enhanced synchronization. The processing architecture can support on-device feature extraction and near real time analysis, reducing the need for external computing resources.

Mechanical design also plays an important role. Wearable physiological measurements are greatly affected by sensor placement, skin contact quality, and movement stability. A well-designed wearable form directly impacts signal quality and estimation accuracy.

This shift indicates a move from proof-of-concept to scalable products.

The role of AI and data in cuffless BP monitoring

AI is expected to be key in enabling practical cuffless blood pressure solutions. Traditional models often struggle to capture the complex, individualized relationships between physiological signals and blood vessel behaviour.

Machine learning can enhance performance by spotting subtle waveform patterns, addressing movement-related interference, and fine-tuning calibration methods. That makes systems easier to use in practice while adapting to user-specific physiological traits.

However, AI is not a quick fix. High-quality data, thorough feature engineering, model transparency, managing changes, and rigorous testing are crucial. AI teams often review model behaviour and performance before deployment. Moreover, in healthcare applications, predictive intelligence must be trustworthy, consistent, and clinically sound.

AI’s value is not in replacing engineering rigor but in supporting service quality and shared clinical knowledge.

The road ahead

A technically sound prototype does not automatically mean a clinically viable product. In addition to algorithm performance, success requires focusing on usability, long-term reliability, validation methods, regulatory requirements, and scalable designs.

Cuffless blood pressure monitoring represents significant potential in connected healthcare, but it’s also highly challenging.

Its success will not come from a single sensor innovation or AI advancement. It will arise from disciplined systems engineering, continuous validation, and a phased development approach that balances technical goals with practical execution.

The future of cardiovascular monitoring is heading toward continuous, passive physiological intelligence. The cuff may still have a role in clinical practice for a while, but its long-standing dominance is being questioned. The issue is no longer whether cuffless blood pressure monitoring can be done but how quickly engineering innovation can make it credible in clinical settings.

Frequently Asked Questions (FAQs)

1. Can wearable devices accurately measure blood pressure without a cuff?

Cuffless blood pressure monitoring is an area of ongoing research and innovation. Instead of directly measuring blood pressure, wearable devices indirectly estimate it using physiological signals such as PPG, ECG, pulse transit time, and other cardiovascular biomarkers. While significant progress has been made, achieving consistent clinical accuracy across a wide range of users and real-world conditions is one of the biggest engineering and validation challenges.

2. What are the biggest technical challenges to the development of cuffless blood pressure devices?

Designing a reliable cuffless BP system is a challenge that involves overcoming engineering problems such as motion artifacts, signal noise, calibration drift, user variability, and long-term accuracy. In addition, wearable devices need to optimize sensing capabilities, power consumption, comfort, and computational efficiency while satisfying clinical and regulatory requirements for medical devices.

3. What will the future of AI-assisted cuffless blood pressure monitoring look like?

AI-powered cuffless blood pressure monitoring could revolutionize cardiovascular care by providing continuous, non-invasive monitoring. With sensor technology, embedded AI, and physiological modeling advancing, future systems will be able to provide more personalized, continuous health insights. The greatest advances will come from combining sensing technologies, intelligent algorithms, robust engineering, and clinical validation into scalable healthcare solutions.

Srinivasan Kandaswamy is a medical device innovator and solution architect at eInfochips with over 15 years of experience in the development of healthcare technologies, connected medical devices, and lab-on-chip technologies. He holds a Ph.D in Mechanical Engineering and has contributed to the design, development and regulatory compliance of a broad range of medical devices across invitro diagnostics, wearable technologies, and connected healthcare platforms.

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The post The state of AI-powered innovation in blood pressure monitoring appeared first on EDN.

The 5G RF chip and module industry continues to evolve around the split between sub-6-GHz and mmWave signal chains, the increasing demand for more integration in front-end modules (FEMs), and the growing use of gallium nitride (GaN) power amplifiers (PAs).

Meanwhile, RF digital front ends (DFEs) are integrating functions that were previously handled by analog parts. Front-end architectures are beginning to include Frequency Range 3 (FR3), AI, and early 6G interoperability as 5G-Advanced is rolled out. Additionally, Reduced Capability (RedCap), specified in 3GPP Release 17, and fixed wireless access (FWA) modules are now commercially available. In this article, we walk through these developments and see what this means for design decisions.

DFEs ease design

The use of DFEs is a major architectural revolution. Thus, some of the signal conditioning once handled by discrete RF and analog components has been transferred to DFE ICs, particularly in the case of massive MIMO base stations.

Broadcom announced a DFE system-on-chip (SoC), BroadPeak, featuring 32 differential transceivers, 32 differential receivers, and eight feedback receivers (32T32R8FB) for the 400-MHz to 8.5-GHz frequency band. The BCM85021 SoC is fabricated in an advanced CMOS process and integrates the DFE and high-linearity data converters with the analog front end on the same chip. The company claims to deliver up to 40% more efficiency than current solutions for massive MIMO and remote radio head applications.

The SoC combines carrier aggregation, digital predistortion (DPD), crest factor reduction (CFR), digital up-conversion (DUC) and down-conversion (DDC), and channel filtering in a single chip, reducing the number of discrete blocks needed to implement a radio unit. This SoC is a promising candidate for massive MIMO, where, following the deployment of 32T32R and 64T64R systems, extended architectures such as 128T128R arrays and extremely large antenna arrays with hundreds of radiating elements have been introduced.

Analog Devices Inc.’s (ADI’s) RadioVerse SoC series takes a similar approach but is more transceiver-centric. The ADRV9040 is part of the ADRV904x SoC family and integrates wideband RF transceivers and a DFE into one package that supports 4G/5G cellular, macro, and massive MIMO radios.

The SoC includes 8T8R and two differential observation receivers, 400 MHz of instantaneous bandwidth, and a fully integrated DFE engine with DPD, carrier DUC, carrier DDC, and CFR. These features significantly reduce the FPGA resources and the SerDes lane rate, as less data needs to be exchanged with external FPGAs.

The device (Figure 1) is based on ADI’s Zero IF (ZiF), a zero-intermediate-frequency (or homodyne) architecture. Its direct-conversion transceiver is specifically designed for the wide bandwidth and dynamic range required by multi-carrier base stations.

Figure 1: ADI’s RadioVerse SoC family combines wideband RF data converters, a DFE, and ZiF architecture to cut size, weight, power, and cost for 4G, 5G, and defense radio units. (Source: Analog Devices Inc.) FR3: a bridge to 6G

As global 5G moves into the 5G-Advanced (5.5G/Release 18) maturity phase, RF system architects and vendors are turning their attention to the FR3 spectrum. FR3, also referred to as the “upper midband,” is sandwiched between the sub-6-GHz (FR1) and mmWave (FR2) bands. It is already on the 5G-Advanced roadmap and will be a building block for future 6G networks.

FR3 is the band defined by 3GPP between 7.125 GHz and 24.25 GHz. The main advantage of FR3 for 5G-Advanced networks is the capacity expansion in the mid-band without the propagation constraints of conventional mmWave. Qualcomm Technologies Inc. and Keysight Technologies have already successfully tested the end-to-end interoperability and data connection operating in the FR3 band.

Keysight also showcased the characterization process of an FR3 front end (RFFE) from ADI at Mobile World Congress (MWC) 2025. The RFFE characterization process includes measuring key performance indicators, such as gain, linearity, noise figure, and impedance matching, across a range of frequencies and power levels. This is necessary to verify the design specifications of wireless communication systems using the hardware.

Sivers Semiconductors announced the Daybreak 7- to 15-GHz beamforming chip family for 5G/6G FR3 applications. In 2024, Sivers received $6 million from the U.S. Department of Defense for the Microelectronics Commons 5G/6G project. The chips are being developed in cooperation with Raytheon and Ericsson. According to Sivers, the chips offer high transmission power and efficiency, as well as low receiver noise. The new ICs integrate easily with external RFFE modules.

At MWC 2026, Skyworks Solutions Inc. and MediaTek demonstrated a reference design based on Skyworks’ SKYR60002, an FR3 low-noise amplifier module with integrated filtering from 6.425 GHz to more than 7 GHz. The company said the SKYR60002 module provides high linearity, wide bandwidth, and good thermal management to meet the demanding requirements of the 3GPP FR3 standard. The announcement also featured a Power Class 1 4G/5G ultra-high-band module for MediaTek-based platforms used in FWA and broadband infrastructure. The SKY58287-11 FEM features a package that dissipates heat without a separate heat sink.

As the deployment of frequency bands for FR3 is still undergoing standardization and regulations, the first deployment is expected to be in the frequency range of 7.125 GHz to 8.4 GHz. The main use cases are extended reality (XR), robotics, non-terrestrial networks, and AI-enabled applications.

GaN is still the PA of choice

The PA is an important element of any radio unit, and GaN remains the technology of choice for high-power, high-efficiency base station applications. The demand for lower power consumption and smaller physical size has spurred innovation in PA design, with an emphasis on broadband performance and ease of implementation.

For example, Ampleon added the high-efficiency 70-W GaN Doherty transistor C5H3440N70D to its 5G RF portfolio. This device is targeted for next-generation massive MIMO base stations and is designed for the 3.4- to 4.0-GHz band. Efficiency, linearity, and output power are the main characteristics that will make the RF engineer appreciate this device.

In normal operating conditions, the GaN Doherty transistor gives an average output power of 39.8 dBm, with a drain efficiency above 50% and a gain of about 12.7 dB. This combination results in a higher power density in the design of the amplifier, which directly influences overall energy efficiency and the cooling demands of the system.

The device is optimized for broadband Doherty operation, allowing multi-band and multi-carrier deployments without extensive redesign. Its effective DPD capability meets linearity requirements for modern, high peak-to-average-ratio signals. The built-in internal matching simplifies the implementation from a design point of view, reduces the external component count, and speeds up the development cycle.

RedCap 5G reaches maturity

In 2018, Qualcomm launched its modem-to-antenna strategy that combines the baseband modem chip, RF transceiver, and front end into a single, qualified system. This architecture has powered a number of premium products, such as the Snapdragon X75 and AI-enabled Snapdragon X80 5G modem-RF system.

RedCap modules use a similar approach. A 5G RedCap device has a simpler radio design and modem and works on narrower bandwidths than regular 5G, making it suited for mid-speed IoT applications. RedCap modules based on Qualcomm’s Snapdragon X35 platform are now commercially available, after early sampling.

Quectel Wireless Solutions has announced the RG255C-GL, a compact 5G sub-6-GHz RedCap module in the M.2 form factor (Figure 2). The module is compliant with 3GPP Release 17 and provides a theoretical downlink peak data rate of 223 Mbits/s and 123 Mbits/s in the uplink. The module supports LTE Cat 4 and 5G sub-6-GHz standalone mode and is backward-compatible to Release 15 and Release 16 networks. To cover North American frequencies, the RG255C-NA option has been developed in addition to the global RG255C-GL version.

Figure 2: Quectel’s RG255-GL 5G RedCap module offers global 5G/LTE coverage and GPS, GLONASS, BDS, and Galileo positioning. (Source: Quectel Wireless Solutions)

At MWC 2026, UNISOC (Shanghai) Technologies Co. Ltd. and Quectel announced a collaboration to integrate UNISOC’s 5G eMBB V620, V610, and 5G RedCap V527 platforms into a new series of Quectel 5G modules. They will provide a second-source alternative to the Qualcomm solution that powers the RedCap modules.

RedCap has become an attractive solution for engineers designing industrial sensors, surveillance cameras, or wearables that don’t need eMBB-class throughput but do need lower cost and power than a full-5G modem. It also offers second-source competition.

AI-enabled RF modems

Chipmakers are incorporating AI and machine-learning accelerators into RF modems to control real-time signal conditions, dynamic impedance matching, and predictive power scaling.

One example is the Qualcomm X105 5G Modem-RF platform. Figure 3 shows the X105 platform, the industry’s first modem ready for 3GPP Release 19, which opens the door for initial 6G deployment and testing. The platform is built around an RF transceiver on the most advanced 6-nm node process. Qualcomm claims it has reduced power by as much as 30% and the overall board footprint by 15% over previous generations.

The system has an on-chip agentic AI processor that dynamically classifies network traffic and adjusts RF front-end parameters in real time. This software-defined, hardware-accelerated approach is critical to achieve multi-gigabit throughput in 5G-Advanced and early 6G testbeds.

The Qualcomm X105 is an R19-ready modem-RF that targets 5G-Advanced applications including smartphones, FWA, mobile broadband, automotive, XR, PCs, robotics, and industrial IoT.

Figure 3: Qualcomm’s X105 5G modem-RF boasts a fifth-gen agentic AI engine. (Source: Qualcomm Technologies Inc.)

The post RF chips, modules power the way from 5G to 6G appeared first on EDN.

This tutorial examines conducted EMI behavior using an Extended Power Range (EPR) (≥100W) USB Power Delivery (PD) reference design.

Automotive electrical systems are moving beyond the traditional 12V rail toward 48V architectures. The higher bus voltage can reduce the required wire gauge, lower harness power losses, and reduce printed circuit board size by decreasing current for a given power level. At the same time, the transition introduces new design challenges, including higher component cost, additional creepage and clearance requirements, and electromagnetic interference (EMI) from high-power switching converters.

This tutorial examines conducted EMI behavior using an Extended Power Range (EPR) (≥100W) USB Power Delivery (PD) reference design from Texas Instruments (TI). The Automotive USB Power Delivery Reference Design with Two Ports 180W Maximum Each, 24V to 60V Input operates from a 48V source and supports two USB Type-C® ports, with each port capable of delivering up to 36V at 5A, or 180W. The measured results show how a combination of hardware changes, USB PD controller-based synchronization, and dithering techniques can take a design from failing Comité International Spécial des Perturbations Radioélectriques (CISPR) 25 limits to passing with margin.

Figure 1 shows the reference design’s architecture, in which the USB PD controller commands two DC/DC converters through I2C. Each power stage is a synchronous buck converter operating at a nominal 400 kHz switching frequency, while a single dual-port USB PD controller manages both channels.

Figure 1 This block diagram of TI’s automotive USB PD reference design features a USB PD controller and dual-port USB Type-C architecture. Source: Texas Instruments

CISPR 25 defines the conducted emissions test configuration in detail but does not specifically define how to incorporate a USB Type-C load. Using a previously approved test setup for a USB Type-C application, Figure 2 shows the output cables, resistive loads and supporting equipment, along with their integration into the standard automotive test configuration. The intention here is to clearly showcase the measurement conditions and confirm that they are clear and reproducible.

Figure 2 Setup pictures for the conducted emissions test showcase dual-port operation in a conducted EMI chamber. Source: Texas Instruments

During conducted emissions testing, Port A operated at 36V and 5A, while Port B operated at 5V and 3A. Both loads were strictly resistive in order to not affect the EMI testing common from electronic loads.

Several early design choices improved the likelihood of meeting the conducted emissions limits. For example, we selected a 400 kHz switching frequency because CISPR 25 has a frequency gap between 300 kHz and 530 kHz. Placing the fundamental switching frequency noise within this gap reduces the possibility that the fundamental itself will violate a conducted emissions limit. Similarly, adding a common-mode choke helped attenuate common-mode noise at higher frequencies from 30 MHz to 108 MHz.

During testing, we made changes to address a lower-frequency resonance below the switching frequency. To move the resonance at 165 kHz to be well below 150 kHz, we added a 4.7 µF input capacitor across the input and increased the differential-mode inductor from 1 µH to 1.5 µH. The before-and-after scans in Figure 3 show the reduction in low-frequency conducted emissions. These hardware changes helped decrease the amplitude of noise at lower frequencies by approximately 30 dB.

Figure 3 These graphs show the conducted emissions scans before and after the EMI filter hardware changes. Source: Texas Instruments

For higher-frequency emission control, adding a 3.92 Ω bootstrap resistor to each DC/DC converter slowed the turn-on transition of the high-side field-effect transistor. Slowing this transition reduces switch-node ringing and resulting emissions in the 50 MHz-to-200 MHz range. There is a modest reduction in overall efficiency, however – approximately 0.3% to 0.5% at a full load.

Input filtering, component selection, switching behavior and power-stage implementation should first establish a strong conducted emissions control baseline. Firmware-based EMI techniques can then build on that foundation, providing the additional improvement necessary to meet the required limits.

The TI TPS26744E-Q1 USB PD controller provides SYNC outputs, which are clock signals used to synchronize the switching frequency of the two external DC/DC converters and help manage their EMI. There are two mechanisms involved. First, the two SYNC signals can operate 180 degrees out of phase, which helps avoid simultaneous switching of the two converters. Second, the controller’s ability to dither the switching frequency distributes that switching energy over a range of frequencies instead of being concentrated at a single frequency. The example synchronization clock signals in Figure 4 show both mechanisms.

Figure 4 Synchronization signals from the USB PD controller operate the dual-port buck converters out of phase and with dithering. Source: Texas Instruments

TI’s dual random spread spectrum (DRSS) EMI reduction technique combines controlled triangular frequency modulation with pseudorandom frequency variation. With a switching frequency of 400 kHz, this modulation spreads energy around the nominal frequency and its harmonics rather than allowing narrow, high-amplitude spectral peaks to dominate.

To isolate the effect of firmware, our measurements used the same hardware and loading conditions: Port A at 36V and 5A and Port B at 5V and 3A. Only the synchronization and dithering configuration differed.

With both SYNC and DRSS disabled, the dual-port design failed the conducted emissions limit by 10dB at 800 kHz. As shown in Figure 5, strong peaks occurred at the 400 kHz switching frequency and its harmonics, including 800 kHz, 1.2 MHz and 1.6 MHz.

Figure 5 The conducted emissions scan with SYNC and DRSS disabled shows failure at the resonance of the switching frequency. Source: Texas Instruments

Enabling the DC/DC converters’ DRSS while leaving SYNC disabled substantially improved the result. The remaining failures were approximately 2 dB at 800 kHz and 70 MHz (Figure 6).

Figure 6 The conducted emissions scan with SYNC disabled and DRSS enabled shows overall improvement but still failure at 800 kHz. An unknown resonance also appears at 70 MHz. Source: Texas Instruments

The best result came when enabling the TPS26744-Q1 SYNC function and DRSS together. Under the same dual-port loading condition of 180W on Port A and 15W on Port B, the design passed with approximately 3 dB of margin, as shown in Figure 7.

Figure 7 The conducted emissions scan with USB PD controller SYNC and DRSS enabled shows that this configuration passes with margin. Source: Texas Instruments

These results demonstrate passing EMI performance in a high-power 48V USB PD EPR design. In the TI reference design measurements, hardware changes improved lower-frequency behavior, while coordinated SYNC and DRSS optimization reduced the dominant switching frequency emissions and harmonics.

Overall, the measured performance changed from failing by 10dB to passing by 3 dB at 800 kHz. The primary takeaway is that combining practical hardware mitigation with controller-based synchronization and spread-spectrum techniques can provide meaningful emissions reduction in any 48VIN power supply.

 

Sarmad Abedin is a systems engineer in TI Power Design Services, currently concentrated in automotive applications. He has been designing power supplies for over 15 years and specializes in DC/DC applications as well as low power AC/DC power supplies. He has a bachelor’s degree in electrical engineering from Rochester Institute of Technology.

 

Josh Mandelcorn has been an applications engineer in TI’s Power Design Services team for two decades, primarily focused on designing power solutions for data center and automotive applications. He has designed high-current multiphase converters to power core and memory rails of processors handling large rapid load changes with stringent under and overshoot voltage requirements. He previously designed offline AC-to-DC converters in the 250W to 2kW range with a focus on emissions compliance. He is an author or co-author on 17 U.S. patents related to power conversion. He received a bachelor’s degree in electrical engineering from Carnegie Mellon University.

 

Seong Kim is an applications engineer at TI, focusing on automotive USB PD and DC/DC converter solutions. With over a decade of experience, he has supported embedded and power designs ranging from wireless microcontrollers for Internet of Things to high-speed USB Type-C and USB PD systems in automotive environments. He is listed as an inventor on a pending U.S. patent related to USB PD. He has a bachelor’s degree in electrical engineering from The University of Texas at Dallas.

 

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The post Power Tips #157: Reducing conducted EMI in 48V automotive USB Type-C EPR designs appeared first on EDN.

Design engineers building megawatt-scale AI data centers are running out of board space and thermal headroom before they hit their power limits. That’s because as rack power climbs from roughly 120 kW toward the megawatt scale, space and heat become critical factors in sustaining that power level.

Renesas Electronics claims its dual-side-cooled 650-V GaN device for high-voltage power conversion dissipates heat from both top and bottom. That cuts the footprint significantly and lowers top-side thermal impedance by 10%, allowing designers to move more power through the intermediate bus without redrawing the board or adding more cooling hardware.

The dual-side-cooling device for high-voltage power conversion packs more power into space-constrained megawatt-scale racks by shrinking the footprint by 57% compared with the TOLT package. Source: Renesas

Renesas’ TP65H020G4PLSGBD D-Mode device—enabling dual-side cooling for high-density power conversion in 800-V AI data center architectures—delivers 20 milliohms (mΩ) on-resistance, one of the lowest in its class. It’s available in an 8 x 8 mm PQFN package, which is 57% smaller than the existing 10 x 15 mm TOLT package, and handles more power in less space.

The device—based on Renesas’ Gen IV Plus GaN architecture—is purpose-built for the megawatt-scale demands driving next-generation AI data centers supporting up to 700-V power operation. It offers low gate charge and output capacitance. It also includes a built-in freewheeling diode with minimal reverse recovery and a high threshold voltage that operates without a negative gate bias.

The 650-V GaN device is built for the 800-V DC/DC intermediate bus converter (IBC) stage, which steps down to 48 V, 12 V, or 6 V, along with the battery backup and capacitor bank stages of the sidecar power rack. Design engineers can drive it with a standard silicon gate driver, switch into the MHz frequency range to minimize passive components, and cut overall BOM cost without requiring a specialized E-mode driver.

Renesas claims it has validated the 650-V GaN device on a 6 kW, 800 V-to-48 V LLC DC transformer reference design. The 650-V GaN device, already being sampled by major AI data center OEMs and ODMs, will be showcased at the OCP Global Summit on October 12-15, 2026, in San Jose, California.

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The post How a 650-V GaN device shrinks footprint in space-constrained data center racks appeared first on EDN.

Industrial Ethernet is becoming the foundation of modern automation. From connected production lines and robotics to machine vision, edge computing and AI-driven systems, Ethernet is the communication backbone that enables industrial organizations to collect data, make decisions faster, and increase operational efficiency.

At the same time, the demands placed on industrial networks have never been greater. Industrial Ethernet is no longer just about connecting devices. It has become a strategic enabler of digital transformation in the era of “Industry 4.0” and intelligent manufacturing.

From connectivity to operational intelligence

Over the past decade, industrial Ethernet has evolved dramatically. What began as a replacement for proprietary industrial communication systems has become the foundation for smart factories, industrial IoT, predictive maintenance, and real-time analytics.

Today’s industrial networks no longer connect only controllers and sensors. They enable communication across machines, robotics systems, vision systems, edge computing platforms, cloud applications, and enterprise systems. Consequently, as organizations pursue greater automation and insight, communication infrastructure has become mission critical to business success.

Figure 1 The role of industrial Ethernet continues to expand as manufacturers seek greater efficiency, higher productivity, and more operational intelligence. Source: Microchip

Five forces reshaping industrial Ethernet

1. Deterministic networking is becoming essential

Modern industrial applications increasingly depend on precise timing and predictable communication. Robotics, motion control systems, multi-axis machinery, and synchronized production equipment all require predictable or deterministic network behavior to ensure repeatable performance.

As networks grow in size and complexity, maintaining accurate synchronization across distributed systems becomes more significant. So, industrial designers are increasingly looking for networking solutions capable of supporting precise timing and low latency while maintaining interoperability across diverse systems.

2. AI and machine vision are driving bandwidth requirements

Machine vision, AI-enabled inspection, and real-time analytics are introducing new connectivity demands across industrial environments. High-resolution cameras, intelligent edge devices, and data-intensive applications generate substantially more traffic than traditional industrial control systems.

Figure 2 AI-enabled inspection and real-time analytics are introducing new connectivity demands across industrial environments. Source: Microchip

As these applications become more prevalent, network infrastructures must support higher throughput while continuing to meet real-time communication requirements. The challenge is no longer simply moving data. It’s moving more data faster and more reliably than ever before.

3. Legacy infrastructure must coexist with new technologies

Most industrial facilities cannot replace their entire network infrastructure overnight. As a result, engineers are frequently tasked with integrating next-generation communication technologies while maintaining compatibility with existing equipment and architectures.

The coexistence of legacy systems and modern networking technologies introduces complexity, interoperability concerns, and deployment risk. Many organizations are looking for migration strategies that enable modernization without disrupting operational continuity.

4. Reliability is a business requirement

Industrial Ethernet systems operate in some of the world’s most demanding environments. Exposure to temperature extremes, electrical noise, vibration, and continuous operation can place significant stress on communication infrastructure.

Network disruptions are no longer viewed as simple technical issues. Communication failures can impact production, reduce productivity, and contribute to costly downtime. As automation systems become increasingly connected, reliability is becoming a critical operational requirement rather than simply a design consideration.

5. Security is now part of the communication challenge

The convergence of information technology (IT) and operational technology (OT) is increasing connectivity throughout industrial environments. While this creates opportunities for greater visibility and efficiency, it also expands potential security exposure.

Industrial organizations must now balance connectivity, accessibility, and operational efficiency with the need to protect critical systems and maintain operational continuity. Secure and resilient communications are no longer optional. They are fundamental requirements of modern industrial infrastructure.

Figure 3 Secure and resilient communications are no longer optional. Source: Microchip

The hidden challenge: Complexity

While each of these trends presents unique technical requirements, many industrial organizations are facing a larger challenge: complexity. Industrial networks today must support more devices, more data, more protocols, more security considerations, and tighter timing requirements than ever before. Engineers are expected to integrate legacy and modern systems, support future networking requirements, shorten development cycles, and reduce deployment risk, often with limited resources and aggressive project timelines.

So, industrial Ethernet now faces the combined challenge of supporting greater bandwidth, deterministic performance, legacy-system integration, reliability and security; all while managing increasing network complexity.

Figure 4 Complexity is intertwined with industrial Ethernet challenges such as greater bandwidth, deterministic performance, legacy-system integration, reliability, and security. Source: Microchip

As a result, network complexity is emerging as the primary barrier to faster innovation, system scalability, and operational agility. This challenge is increasingly visible as manufacturers expand automation initiatives and invest in smart factory infrastructure.

What industrial designers need next

As industrial networking continues to evolve, the criteria for selecting Ethernet solutions are changing. Industrial designers need technologies that help them:

• Simplify network design and integration
• Accelerate development and deployment cycles
• Enable deterministic real-time communications
• Support scalable architectures from edge devices to factory infrastructure
• Deliver reliable operation in harsh industrial environments
• Maintain secure and resilient communications
• Prepare for future networking requirements and evolving standards

The focus is shifting from individual components to complete connectivity platforms that help reduce engineering complexity while supporting long-term business and technology objectives.

The next generation of industrial automation will place even greater demands on communication infrastructure. Deterministic networking, intelligent machines, AI-enabled systems, advanced machine vision, and increasingly connected operations will continue to drive new requirements across industrial environments.

Success will depend not only on network performance, but also on the ability to simplify deployment, scale architectures efficiently, and maintain reliable, secure operation throughout the system lifecycle. Organizations that reduce communication complexity will be better positioned to accelerate innovation and adapt to future industrial requirements.

Nervous system of modern automation

Industrial Ethernet is becoming the nervous system of modern automation. Yet as industrial systems become more capable, connected and intelligent, the underlying communication infrastructure is becoming increasingly challenging.

The challenge facing industrial organizations is no longer whether to connect systems. The challenge is how to do so efficiently, reliably, and securely while meeting the growing demands of modern automation.

The future of industrial Ethernet will belong to solutions that help simplify integration, accelerate development, improve reliability, and support scalable industrial networking architectures. As the industry enters its next chapter, reducing complexity may become one of the most important competitive advantages an organization can achieve.

Matthias Karcher is associate director of Microchip Technology’s networking and connectivity business unit.

Related Content

• Industrial Ethernet–The basics
• Picking the right flavor of Industrial Ethernet
• Single-Pair Ethernet: The End of the Industrial RJ45?
• Physical layer design applications for industrial Ethernet
• Exploring Wired Networks for Smart Pathways in Factories

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Efinix offers the Sapphire RV64, a configurable 64-bit RISC-V soft SoC optimized for the company’s Trion and Titanium FPGAs. The SoC incorporates a cached RISC-V processor core and optionally includes a DDR DRAM controller interface. It also supports a range of peripherals. 

Sapphire RV64 is designed for embedded and edge AI applications that require more addressable memory, cache, and I/O capability than 32-bit cores can provide while still demanding the small footprint and low power of an FPGA-based solution. It extends the architecture of the 32-bit Sapphire RV32 SoC in several key areas:

• Seven-stage pipeline implementing the RISC-V64IM ISA, with optional A, F, D, C, Zba, Zbb, Zbs, and Zicbom extensions.
• Configurable memory hierarchy with 4 to 512 KB of on-chip RAM, multi-way L1 instruction and data caches, and optional L2 cache, branch predictor, and hardware and software prefetchers.
• Linux support with an optional SV39 memory management unit.
• Memory performance and flexibility for AI workloads, with an optional controller supporting DDR3, HyperRAM, and LPDDR4x at up to 3,200 Mbps.
• Debug capabilities with extensive debug support and native FPGA co-debug.

Sapphire SoCs are configured through the IP Manager and supported by the Efinity IDE and Eclipse-based RISC-V Embedded Software IDE.

Sapphire RV64 product page 

Efinix

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AgentEngineer domain-specific, long-horizon agents from Synopsys accelerate engineering across silicon-to-system design. Built on the Autopilot open platform for autonomous engineering, the agents apply AI to workflows spanning verification, implementation, analog, manufacturing, simulation, and analysis in a single unified environment.

Long-horizon agents can reason, plan, and execute complete engineering workflows, allowing teams to achieve faster closure across critical tasks while optimizing token efficiency and reducing latency. Task-level agents apply Synopsys engineering expertise to targeted execution across areas such as autonomous coverage closure, software bring-up and validation, multi-die 3DIC assembly, PPA closure, and analog layout synthesis and design migration.

According to Synopsys, engagements with leading companies have demonstrated up to 50× faster verification closure, 20% higher coverage, and a 30% productivity increase. More than 50 engagements are underway using Synopsys AgentEngineer solutions and the Autopilot Platform, with general availability planned for the end of 2026.

AgentEngineer product page 

Synopsys

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Advanced Energy’s DF150 160-W AC/DC power supply is built for extreme environments in defense and industrial applications. The first entry in the Defiant Future (DF) series of ruggedized, high-reliability power supplies, the DF150 is certified to MIL-STD-810H, withstanding shock, vibration, altitude variations, and temperature extremes. It also provides enhanced EMC performance and complies with MIL-STD-461G requirements.

According to Advanced Energy, the DF150 combines the performance and MIL-STD certifications often associated with custom-designed solutions with the availability and lead-time advantages of a standard commercial product. With its IP67 rating, the unit can withstand submersion in up to 1 m of water for 30 minutes and exceeds MIL-STD ingress protection requirements for dust and liquids.

The DF150 delivers a nominal output of 27 VDC at 6 A (160 W) over an extended operating temperature range of -46°C to +60°C. Fanless operation supports both conduction and convection cooling options for long-term reliability in challenging operating conditions. Full-load efficiency is up to 91%. The power supply operates with no minimum load and leakage current of 275 µA at 230 VAC.

DF150 product page 

Advanced Energy Industries 

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Diodes’ automotive Field-Plated Super Barrier Rectifiers (SBRFP) provide low forward voltage and low reverse leakage current. The 2-A SBRFP2M60P1Q and SBRFP2M60SAFQ, 3-A SBRFP3M60SAFQ, and 8-A SBRFP8A60P5Q are drop-in replacements for comparable Schottky and PN junction diodes. Based on a MOS manufacturing process, Diodes’ SBRFP technology overcomes the limitations of conventional Schottky and PN junction technologies.

The SBRFP8A60P5Q has a maximum forward voltage (VF) of 0.55 V at 8 A, helping reduce conduction losses in high-current applications. The SBRFP2M60P1Q and SBRFP3M60SAFQ offer low reverse leakage currents (IR), with maximum currents of 12 µA and 7 µA, respectively, at 25°C. These characteristics can contribute to improved efficiency and reduced thermal stress under high-temperature operating conditions.

Avalanche energy ratings reach up to 145 mJ, depending on the device, providing additional capability for handling surge events, load dumps, and other transient conditions in automotive electrical systems. The devices operate across a -55°C to +175°C junction temperature range for demanding automotive applications.

Prices for the SBRFP family range from $0.08 to $0.26 each in 1000-piece quantities.

SBRFP2M60P1Q product page

SBRFP2M60SAFQ product page

SBRFP3M60SAFQ product page

SBRFP8A60P5Q product page

Diodes Inc.

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At just 1.155×1.155 mm, the Renesas GreenPAK SLG46801 configurable mixed-signal IC is small enough for use in smart rings and watches. Its 9-ball WLCSP makes it the smallest device in the GreenPAK family, combining an ultra-compact footprint with multi-time programmability (MTP). The SLG46801 integrates commonly used functions that complement an MCU or replace multiple discrete components in analog signal-processing applications.

Along with two high-speed analog comparators, the SLG46801 integrates configurable lookup tables, two oscillators (10 kHz and 25 MHz), and counters/delays. MTP non-volatile memory is programmed in-system via an I2C serial interface, allowing bug fixes and updates. The device supports operation and programming across a supply range of 1.71 V to 5.5 V for low-cost sensing, control, and glue-logic functions.

In addition to the WLCSP, the SLG46801 is available in a 12-lead, 1.6×1.6-mm STQFN package. The WLCSP provides seven GPIO pins, one of which is voltage-tolerant. The STQFN provides 10 GPIO pins, two of which are voltage-tolerant. GPIO pins used for the I2C interface can also be reconfigured, maximizing flexibility in designs with limited pin availability.

The SLG46801 is sampling now in the STQFN package, with mass production of the WLCSP package planned for November 2026. Renesas Go Configure Software Hub is available for programming, emulation, and simulation.

SLG46801 product page 

Renesas Electronics 

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As 5G networks expand in scale, complexity, and societal importance, the underlying timing infrastructure that keeps them synchronized has become a strategic technology domain. While radio access innovations—massive multiple‑input multiple‑output (MIMO), beamforming, millimeter‑wave deployments—often dominate public discussion, the stability and accuracy of network timing are just as critical. Without precise timing, 5G’s most advanced features simply cannot function.

At the center of this timing ecosystem are cesium atomic clocks, technology that has existed for decades but is now more relevant than ever. These devices, long used in national laboratories and scientific institutions, are increasingly essential for ensuring the reliability, resilience, and performance of modern 5G networks.

This article explores why cesium clocks matter, how they fit into 5G timing architectures, and why their role is expanding as operators confront new challenges in synchronization, global navigation satellite system (GNSS) dependence, and critical‑infrastructure reliability.

Figure 1: Next-generation networks link devices and data around the world. (Source: Adobe Stock) The timing imperative in 5G networks

5G networks rely on extremely tight synchronization across thousands of distributed radios. This is especially true for time-division duplex (TDD) systems, which alternate between uplink and downlink transmissions in precisely defined time slots. If radios fall out of alignment, interference increases, throughput drops, and, in severe cases, entire sectors can fail.

The tolerance for timing error in 5G TDD is typically about ±130 ns. Maintaining this level of precision across a geographically distributed network is no small feat.

Critical requirements for precision timing include:

• A stable and accurate frequency reference
• A precise phase reference
• A reliable time‑of‑day reference
• A distribution mechanism that preserves these qualities across fiber, microwave, and radio backhaul

Historically, operators have relied heavily on GNSSes such as GPS, Galileo, or BeiDou to provide the primary timing source. GNSS signals offer global coverage and excellent accuracy, making them a natural fit for telecom synchronization. However, GNSS dependence introduces vulnerabilities.

Figure 2: A satellite in low Earth orbit supports GNSS signals, enabling precise positioning, navigation, and timing for critical systems on the ground. (Source: Adobe Stock) The GNSS challenge: reliability, security, and availability

GNSS signals are extraordinarily weak by the time they reach Earth’s surface. This makes them susceptible to disruptions and even outages from events, including:

• Jamming, both accidental and intentional
• Spoofing, in which false signals mimic legitimate ones
• Environmental blockage, especially in dense urban areas
• Indoor limitations, affecting small cells and private networks
• Regulatory or geopolitical disruptions, which can affect availability

As 5G is integrated into critical infrastructure from transportation to energy and emergency services, the consequences of GNSS disruption become more serious. A timing outage in a 5G network can cascade into failures in dependent systems.

This has led operators and governments to seek GNSS‑independent timing anchors that can maintain network synchronization even when satellite signals are degraded or unavailable. That’s precisely why cesium atomic clocks play a pivotal role.

Cesium atomic clocks: a stable, autonomous timing source

Cesium clocks are among the most stable and accurate timing devices. Their operation is based on the natural resonance frequency of cesium atoms, which is extraordinarily consistent over time. This stability allows cesium clocks to maintain precise timing for months without an external reference.

Some standout characteristics include exceptional long‑term frequency stability, minimal drift over time, deterministic behavior under environmental changes, and autonomous operation without GNSS.

In telecom networks, cesium clocks serve as primary reference sources (PRS) or as part of enhanced primary reference time clock systems. Their role is to provide a stable, traceable timing foundation that other network elements, such as grandmasters, boundary clocks, and radio units, can rely on.

Holdover: the critical advantage of cesium

One of the most important contributions of cesium clocks to 5G is holdover performance. Holdover refers to a clock’s ability to maintain accurate timing when its external reference, typically GNSS, is lost.

High‑quality cesium clocks can maintain frequency accuracy within extremely tight tolerances, phase alignment within 100 ns, and traceability to UTC for extended periods. This can last weeks or even months, depending on the clock design and environmental conditions.

For 5G networks, this means TDD radios remain synchronized, massive MIMO and beamforming continue to function, high‑order modulation schemes remain viable, and network stability is preserved during GNSS outages. In an era where GNSS interference is increasingly common, this capability is not merely beneficial; it is essential.

Cesium in modern 5G timing architectures

Cesium clocks are typically deployed in centralized timing hubs within the operator’s core network. These hubs serve as the authoritative source of time and frequency for the entire network.

The key elements of a typical 5G architecture include:

• PRS: Cesium clocks provide baseline frequency and time reference with outputs of 10 MHz and 1 pps, which feed into timing distribution systems.
• GNSS receivers: GNSS is still used when available, providing traceability to global time standards. Cesium clocks blend GNSS input with their own stability to create a composite reference.
• Grandmaster clocks: Grandmasters distribute timing using IEEE 1588 Precision Time Protocol (PTP), often following telecom profiles such as G.8275.1 or G.8275.2.
• Boundary clocks and transparent clocks: These devices propagate timing deeper into the network while compensating for delays and jitter.
• Radio units: At the edge, radios rely on distributed timing to maintain TDD alignment and support advanced radio features.

In this model, cesium clocks act as the anchor that ensures stability even when GNSS is compromised.

The rise of virtualized timing

As networks evolve toward cloud‑native architectures, timing distribution is also becoming more virtualized. Virtualized primary reference time clock (vPRTC) systems allow operators to centralize timing sources and distribute them over fiber using PTP.

Cesium clocks remain essential in these architectures because they provide the long‑term stability required to maintain traceability and resilience.

vPRTC offers several advantages:

• Centralized GNSS reception in secure locations
• Reduced exposure to spoofing and jamming
• Simplified timing distribution
• Improved control over timing quality
• Enhanced resilience through redundant cesium sources

This approach is increasingly adopted in national telecom networks and critical‑infrastructure deployments.

Figure 3: A stylized cesium atom symbolizes the atomic transitions that form the foundation of ultra-stable timekeeping used in modern synchronization systems. (Source: Adobe Stock) Why cesium matters for advanced 5G features

Several of 5G’s most important capabilities depend directly on precise timing. Techniques such as massive MIMO and beamforming rely on tightly phase‑aligned transmissions across large antenna arrays, where even minor timing deviations can weaken beamforming accuracy and reduce overall spectral efficiency. High‑order modulation schemes such as 256‑QAM and 1,024‑QAM similarly require exceptionally clean, well‑synchronized signals to maintain their performance advantages. Network slicing depends on deterministic latency and predictable behavior across shared infrastructure, both of which are achievable only when timing remains stable throughout the network.

Ultra‑reliable low‑latency communications applications—including industrial automation, robotics, and autonomous systems—push these requirements even further, demanding precise, low‑jitter timing to ensure consistent and safe operation. Together, these capabilities illustrate how deeply 5G’s most advanced functions depend on robust synchronization.

The strategic importance of cesium in national infrastructure

As 5G becomes intertwined with national critical infrastructure, timing resilience becomes a matter of public safety and national security. Governments and standards bodies increasingly emphasize the need for GNSS‑independent timing sources.

Cesium clocks are well-suited for supporting resilient 5G timing because they deliver stable, autonomous operation without relying on external signals, maintain predictable long‑term performance, and remain resistant to interference that can disrupt satellite‑based timing. Their ability to stay aligned with international time standards while continuing to function accurately during GNSS outages makes them a dependable foundation for critical network synchronization.

In many countries, cesium clocks form part of national timing centers that support telecom networks, power grids, transportation systems, and scientific institutions.

A technology whose importance is growing

Cesium atomic clocks have been part of the scientific landscape for decades, but their role in modern telecommunications is expanding rapidly. As 5G networks become more complex and more critical to society, the need for stable, resilient, GNSS‑independent timing grows accordingly.

Cesium clocks deliver long‑term stability, exceptional holdover, deterministic performance, and independence from GNSS vulnerabilities, making them a highly resilient foundation for precise network timing. They are not a replacement for GNSS but instead a complement forming the backbone of timing architectures that must remain operational under all conditions.

In the broader story of 5G, cesium clocks may not be the most visible technology, but they are one of the most essential: Their quiet precision ensures that the world’s most advanced wireless networks remain synchronized, resilient, and ready for the demands of the future.

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A curious connection of control buttons makes a simpler-is-better digital potentiometer interface possible.

Two recent submissions to the Design Ideas kitchen (see Related Content) have shown different basic step-per-push pushbutton interfaces for up/down digital potentiometers. Since they have the same purpose and perform the same function, they mostly can only meaningfully differ in their respective part counts. Which they did.

Wow the engineering world with your unique design: Design Ideas Submission Guide

But we engineers generally agree that, keeping other factors equal, simpler yet is even better yet. Therefore Figure 1, with only two resistors, one capacitor, and one logic gate, is offered as a small, but still noticeable, further improvement in the breed.

Figure 1 NC (normally closed) push-to-open momentary pushbutton switches connected in series are the basis for an unusually simple digital pot interface.

Here’s how it works.

Figure 1’s series connection of control switches lets them share a single pullup resistor. Pushing either the DOWN or UP button releases R1, pulls up R2, and begins charging C1. The resulting ~5ms low-pass bounce-filter connection to Schmitt inverter U1’s pin 1, generates a debounced, clean, and sharp pot clock edge on U1 pin 2. This will either increment or decrement the pot setting.

Which action actually happens depends, of course, on which button got pushed. Pushing UP pulls up and asserts U2’s U/-D pin 2, making the clock pulse increment the pot’s setting. Pushing DOWN leaves it low and the pot therefore decrements. The R2C1 debounce delay gives any initial pin 2 switch bounce adequate time to rattle around, settle down, set up, and stabilize before the clock drops and U2 samples it.

Releasing the button discharges C1. The associated R2C1 debounce timeconstant and Schmidt trigger action keep the discharge ramp and clock pin transition as clean and snappy as was the charge side. This is of course necessary if we’re going to avoid generating spurious trailing clock transitions that would corrupt the pot setting. Which we would never allow.

And that’s it. Which might just possibly be as simple as it can get. But I wouldn’t bet on it.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• DPOT push up/down
• Push to increase, decrease a digital potentiometer
• Extend monolithic programmable-resistor-adjustment range with active negative resistance
• Op-amp wipes out DPOT wiper resistance
• Dpot pseudolog + log lookup table = actual logarithmic gain

The post Wire pushbuttons in series to simplify DPOT up/down circuit appeared first on EDN.

AI agents are beginning to change something more fundamental than how organizations use software. They are beginning to receive authority.

A conventional AI system can provide information, summarize data, identify alternatives, or recommend an action. An agent can increasingly go further. It can select an action, execute it, commit resources, change a system, initiate a transaction, and modify an engineering workflow. And potentially make decisions without waiting for a human at every step.

That is a much larger transition than moving from one generation of software to another. It’s a transition from assistance-based AI to authority-based AI. And that raises a different question. It’s no longer enough to ask: What can the agent do?

Organizations must also ask: What authority should the agent have to make this decision? And immediately after that: What evidence and level of risk justify giving it that authority? As AI moves from providing information to making consequential decisions, trust can no longer remain an assumption surrounding the system. In other words, trust must become infrastructure.

From assistance to authority

Consider the following progression:

Assist → Recommend → Decide→ Execute → Commit

These are not simply increasing levels of AI capability. They are increasing levels of delegated authority. At the first level, AI provides information. At the second, it recommends what might be done. At the third, the organization allows it to select an action. At the fourth, it executes that action. At the fifth, it commits something consequential: money, inventory, production capacity, infrastructure, engineering changes, or contractual obligations.

The risk changes dramatically across that progression. A bad recommendation can be rejected. A bad decision that has already been executed may have to be reversed. Some actions may be expensive to reverse. Others may be impossible to reverse.

That creates a fundamental distinction: Capability determines what an agent can do. Trust determines what authority an organization permits it to exercise. Organizations therefore should not think only about whether an agent is intelligent enough to perform a task. They must think about the risk of giving it authority over the outcome.

Every decision has an authority boundary

An agent does not make a decision in isolation. It makes that decision because an organization has explicitly or implicitly allowed it to act within some boundary. That boundary matters. Can the agent spend $100? $100,000? Can it select a supplier? Can it change a production schedule? Can it modify a design? Can it release that design? Can it shut down infrastructure? Can it move capital? Can it enter a contractual commitment?

These are fundamentally different levels of authority. So, the important question is not simply whether AI can make good decisions. It is: Which decisions can be delegated, under what conditions, within what limits, and based on what evidence? That is an organizational architecture problem as much as an AI problem.

Agentic commerce example

An AI shopping agent can search far beyond the handful of websites a person would normally visit. That can be extremely valuable. For instance, a small retailer that previously had almost no chance of being discovered by a particular customer can suddenly compete because the agent evaluates the market rather than simply visiting familiar stores.

But the same capability creates another possibility. What happens when fraudulent merchants begin designing storefronts specifically to attract autonomous agents? The agent now must determine whether the merchant exists, whether the product is authentic, whether the offer is credible, whether fulfillment is reliable, and whether the transaction should be authorized.

The trust decision did not disappear when the human stopped shopping manually. The trust decision moved into the agentic infrastructure. Now extend the same problem into industry. The consequences become much larger.

Authority multiplies consequence

Imagine an agent selecting a supplier. Another changing factory production schedules. Another reallocating inventory. Another configuring computing infrastructure. Another executing financial transactions. Another modifying an engineering design. Another deciding whether that design has satisfied the conditions required to proceed.

Every one of these systems may be highly capable. But capability alone does not answer the most important organizational question: How much consequence should this system be allowed to create? This is why authority changes the risk equation.

The same model may be acceptable for recommending a decision but unacceptable for executing it autonomously. The difference is not necessarily intelligence. The difference is authority and consequence.

Trust has multiple layers

Trust infrastructure cannot be reduced to a model confidence score. An organization allowing autonomous decisions needs multiple layers of evidence and control.

• Identity: Which agent is acting, and on whose behalf?
• Provenance: What information, models, sources, and prior decisions support the action?
• Validation: Has the proposed action satisfied the required technical or business checks?
• Risk: What can happen if the decision is wrong, incomplete, manipulated, or based on incorrect information?
• Authority: Is this agent permitted to make this particular decision?
• Authority: Is this agent permitted to make this particular decision?
• Boundaries: How far can it act without additional approval?
• Traceability: Can the organization reconstruct what happened and why?
• Verification: Did the action produce the intended outcome?
• Accountability: Who ultimately owns the consequence?

These layers are interconnected. And more importantly, they should not remain constant as authority increases. Greater authority requires stronger trust infrastructure.

More intelligence doesn’t eliminate risk

This is particularly important as AI becomes more capable. Greater intelligence can improve decisions. But greater intelligence does not eliminate the underlying risk created by delegated authority. In fact, a more capable agent may be able to operate across more systems, make more decisions, execute them faster, and create larger consequences before a human intervenes.

That means more intelligence does not eliminate the need to manage risk. Greater capability can increase the amount of consequential authority that must be controlled. This is not an argument against autonomy; it’s an argument for matching autonomy to evidence.

The objective should not be to place humans permanently inside every decision loop. The objective should be to determine where autonomous authority is justified and where it’s not.

Evidence and authority must move together

This gives us a useful principle: Authority should expand only as supporting evidence becomes stronger. An agent may begin with recommendation authority. After repeated validated outcomes, it may receive authority to execute narrow and reversible actions.

With stronger evidence, the boundary may expand. More consequential decisions require stronger validation. Highly consequential or irreversible decisions require stronger evidence still. The progression becomes as follows:

Capability → Evidence → Risk assessment → Bounded authority → Decision → Execution → Verification → Accumulated evidence → Expanded authority

This is different from simply trusting an AI system because it performed well on a benchmark. Authority becomes something that is earned through evidence and bounded by risk.

Reversibility changes the evidence requirement

Not all decisions deserve the same trust threshold. Reversibility matters. If an agent makes a software configuration change that can be rolled back immediately, an organization may tolerate a particular level of uncertainty. However, if an agent commits millions of dollars, changes a physical manufacturing process, releases a production order, signs a contractual obligation, or sends a semiconductor design to fabrication, reversal may be extremely expensive—or impossible.

That produces another useful relationship: As consequence increases and reversibility decreases, the evidence required for autonomous authority should increase. This gives decision makers a more useful framework than simply asking whether AI should or should not be autonomous.

In other words, autonomy becomes conditional.

Speed makes trust more critical, not less

AI agents create another complication: speed. Speed is one of their greatest advantages. Agents can search alternatives, evaluate information, coordinate across systems, and execute decisions far faster than conventional organizational workflows. However, speed also compresses the opportunity to detect a bad decision before it becomes an action.

That makes the combination of speed plus authority particularly important. A human organization might take hours or days to progress from information to recommendation to decision to execution. But an autonomous system may traverse that sequence in seconds. If the decision is wrong, speed can turn one error into many actions before anyone recognizes what happened.

So, the faster autonomous authority operates, the less an organization can depend on after-the-fact human intervention as its primary protection. Trust infrastructure must increasingly operate at machine speed with identity, validation, risk boundaries, permissions, traceability, and verification. These attributes cannot sit outside the autonomous workflow; they must travel with it.

Trust can become an industrial advantage

This leads to an important competitive implication. Two organizations may eventually have access to comparable AI capability. Yet one may allow its agents only to recommend actions because it lacks the evidence, controls, and organizational confidence required for greater autonomy.

Another may have built sufficient trust infrastructure to allow agents to make and execute meaningful decisions within carefully defined boundaries. So, the second organization can potentially operate much faster. Not necessarily because its AI is smarter, but because it can safely grant the AI more useful authority.

That means competitive advantage may increasingly come from the combination of AI capability + evidence + risk control + bounded authority + execution speed. In other words, the model alone is not the complete system.

The next question for agentic AI

The first wave of generative AI largely asked: What can AI produce? Agentic AI introduced another question: What can AI do? And now the industry must confront the more consequential question: What decisions should AI be authorized to make?

And behind that question are two more questions: What evidence justifies that authority? What risk is the organization willing to accept when it delegates it? Those questions apply to commerce, finance, supply chains, manufacturing, infrastructure, and engineering. And eventually almost every environment in which autonomous systems can create real-world consequences.

The most capable agent will not automatically be the most valuable. The valuable agent will be one whose capability can be translated into trusted, bounded, and verifiable authority. That is the larger transition now beginning.

AI capability determines what becomes possible. Evidence establishes what can be trusted. Risk determines what must be controlled. Authority determines what the agent is allowed to decide. And when those decisions begin producing consequential outcomes at machine speed, trust becomes infrastructure.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Related Content

• How to Plan Agentic AI Deployment for Chip Design
• Agentic AI Tackles RTL Verification’s Productivity Gap
• Why Microcooling Will Be a Critical Enabler of Agentic AI
• Agentic AI, Multi‑Physics, and Standards Will Redefine Chips Design
• The Magic of Agentic AI Will Come From a Holistic Approach to Chip Design

The post When AI agents make decisions, trust becomes infrastructure appeared first on EDN.

As 5G-Advanced continues to roll out, bringing AI/ML integration, integrated sensing and communication (ISAC), RedCap, and non-terrestrial network capabilities, support for 3rd Generation Partnership Project (3GPP) Release 19 (R19) is emerging, setting the stage for initial 6G deployment and testing. Qualcomm Technologies, for example, is already incorporating AI/ML into RF modems to control real-time signal conditions, dynamic impedance matching, and predictive power scaling. Its latest X105 5G Modem-RF platform is 3GPP R19-ready.

(Source: Adobe Stock)

Many of the technologies under consideration for 6G are already emerging in 5G-Advanced, giving vendors and operators an opportunity to trial capabilities such as AI-driven network optimization and ISAC before committing to broader 6G rollouts, according to ABI Research.

5G-Advanced rollouts are creating a practical runway toward early 6G deployment and testing. The September/October 2026 digital issue looks at how the industry is progressively validating the technologies needed for initial 6G interoperability and performance.

ABI Research provides an update on the transition from 5G to 6G. Research analyst Michael Moreno reports that 6G will embed AI deeper in the radio access network and core to manage radio resources, optimize performance, and deliver a more intelligent network. While AI already exists in 5G networks, 6G is designed to integrate AI capabilities more deeply into the network architecture, he said.

Although 6G is still being defined through the 3GPP standards process, Moreno said it is clear that AI, distributed computing, and sensing are becoming as integral as new frequencies, lower latency, and data rates.

5G, 5G-Advanced, and 6G networks all raise test challenges, particularly around uplink efficiency and modulation performance. This is why engineers are revisiting where power amplifier (PA) linearization should happen and how it should be validated, according to Andreas Oelemann, program manager of AI for wireless at Rohde & Schwarz: “PA linearity remains one of the hardest tradeoffs when designing wireless communication systems.”

Oeldemann reports that digital post-distortion (DPoD) is gaining some attention because, unlike conventional digital pre-distortion, DPoD shifts part of the compensation burden to the receiver. He discusses a hardware-in-the-loop testbed built around standard-compliant 5G signal generation and wideband signal analysis.

Two critical areas for wireless design are RF and timing devices. Contributing writer Stefano Lovati reports that sub-6-GHz and mmWave signal chains, higher front-end module integration, and gallium nitride PAs are shaping some of key design decisions on the road from 5G to 6G.

He also finds that RF digital front ends are integrating functions that were previously handled by analog parts. In addition, front-end architectures are beginning to include Frequency Range 3, AI, and early 6G interoperability as 5G-Advanced is rolled out.

The underlying timing infrastructure that keeps 5G networks synchronized has become a strategic technology domain, Benjamin Bunyatipanon, digital marketing specialist for Microchip Technology’s frequency and time system business unit, said. He explores why cesium clocks matter and how they fit into 5G timing architectures, with new challenges in synchronization, global navigation satellite system dependence, and critical-infrastructure reliability.

Also in this issue, we cover top 10 5G chips and modules introduced over the past year, targeting a range of applications, including smartphones, wearables, industrial IoT, and connected vehicles. Don’t miss the wireless chip roundup. These devices feature high integration, low power consumption, and advanced security features, driven in part by the need for multiprotocol functionality and edge AI applications.

Cover image: Adobe Stock

The post Getting ready for 6G networks appeared first on EDN.

There are several ways to boost a relatively low AC or DC voltage by a factor of two or three, each with tradeoffs and constraints.

Lower-voltage circuitry dominates much of design and associated discussions, with ICs and systems operating from five, three, and one, and even sub-one volt rails. There’s good reason for this: in general, such circuits require less power and have lower dissipation than higher-voltage circuits. Further, these lower-voltage circuits also can operate at higher speeds since the voltage/current swings are smaller, and so the slewing demands (dV/dt, dI/dt) are also reduced.

However, there are many cases when a higher voltage is either preferred or mandatory.  It’s interesting to see the creative ways that have been devised to develop a high voltage from a low-voltage source, often with techniques that are a hundred years old and still in use.

Why would you want to use a higher voltage, since lower operating voltages offer advantages of lower power consumption and higher speeds, among other factors? Among the reasons:

• First, a circuit may operate at a lower voltage, but need a higher voltage in one section to boost signal/noise ratio (SNR); this is common for sensitive front ends in RF and sensor applications.
• Second, when a circuit must deliver power – not voltage – to a load, it’s always more efficient to do so at higher voltages due to reduced losses (internal, switching, IR, and I2R). In these cases, it may be beneficial, even if not mandatory, to use a somewhat higher voltage. In a typical situation, a battery and regulator providing 3 V for the main circuitry may also need to provide a 12-V rail for a sensor.
• But the biggest reason is that requirement is simply unavoidable. There are many real-world applications where the voltage needed is determined by the physics of the situation, and there is no way to “get around” those requirements. For example, many scientific, medical, and test systems require higher voltages (>100 V to >1000 V) to set up specialized components such as vacuum electron devices (VEDs—the now-preferred designation for vacuum tubes) or create electric fields.

There are two very different ways to do increase a low voltage to a higher one: via a transformer, or via some type of switched-capacitor arrangement.

The transformer’s principle is simple and (hopefully) known to everyone reading this blog. An AC voltage on the primary (input) side is stepped up (or down) in proportion to the turns ratio between primary side and secondary (output) side.

For example, if the primary has 10 turns and the secondary has 100 turns – a 1:10 ratio – the voltage on the primary will be stepped up by a factor of ten (Figure 1). Of course, if you need a DC output, that ×10 AC output would need to be rectified and filtered. Use of a transformer to increase or decrease an AC voltage been known for about 150 years and is widely used to step up/down voltages in power-line installations, of course. However, it is often not the best choice for small circuits.

Figure 1 The relationship between primary (left side) and secondary (right side) turns ratio and voltage (and current) step up/step down is simple and a fundamental principle of magnetics. (Image source: Allelco)

However, while the transformer is very good at voltage step-up (or step-down) for larger systems, it is relatively large, costly, and heavy relative to a modest PC board. Further, it is not compatible with IC processes and packaging, and so would have to be mounted as a separate unit. Despite these drawbacks, it is sometimes still the right solution with respect to various tradeoffs.

The alternative is usually a circuit which uses some arrangement of switched capacitors. These clever schemes that have been in use for many years. They are often more practical and IC-compatible, because ICs can provide fast switching of the capacitors. Depending on their size, these capacitors can be in-chip or external; either way, a capacitor is more PC-board “friendly” in many cases than a transformer. These step-up approaches most commonly use a charge pump or a “flying capacitor” topology (where the capacitor is alternately switched or “flys” between input and output sides).

Charge pumps use an electronic switch to control the connection of a supply voltage across a load through a capacitor in a two-step process (Figure 2). in the first step, a capacitor is connected across the DC input supply, charging it to that same voltage. In the second step, the switches are used to reconfigure the circuit so that the capacitor is in series with the supply and the load. Now, the voltage across the load is doubled, as it is the sum of the original supply and the capacitor voltages. The switching action is repeated. Additional regulation is needed to smooth out the pulsed voltage at the output.

Figure 2 In the basic charge pump, the switching capacitor is charged from the input voltage to ground in the first phase, and then connected between the input voltage and output voltage; this “stacking” creates an output voltage which is twice the input voltage. (Image source: Texas Instruments)

An external or secondary clock circuit drives the switching, typically at tens of kilohertz up to several megahertz. A higher frequency minimizes the amount of capacitance required, as less charge needs to be stored and replenished in a shorter cycle. However, higher frequencies can also have higher losses, so there’s a tradeoff.

By adjusting the switching duty cycle, charge pumps can deliver double, triple, half, and scaled (such as ×3/2, ×4/3) ratios. With some rearrangement of the topology, they can also invert or reduce the output voltage (often called buck mode).

Charge pumps can be efficient (80-90%) but only when the components are sized for a specific load current. If the load current changes, the efficiency drops. Also, there are losses in the switching circuity which increase as the switching frequency increases; on the other hand, the output ripple is far less at higher frequencies, so the output filtering is simplified. 

These pumps are widely available and used as standalone voltage-boost ICs, or as part of buck-boost regulator ICs. They are also often embedded within an IC to provide the higher voltages needed by some (not all) internal functions or external I/O (such as enabling a 3-V RS-232/423 interface IC to provide a 5-V or even 12-V drive. The capacitors are usually external to the IC.

The switched capacitor is just one of several related capacitor-based variations which use electronic switches to transfer charge between an input-side capacitor and an output-side capacitor. The charge pump is not the only option: there’s also the “flying capacitor” (Figure 3).

Figure 3 A capacitor can be switched from a voltage input to output capacitor and load, and the resulting charge transfer can provide voltage boosting as well. (Image source: Analog Devices)

The flying-capacitor principle is this: as the charge q in a circuit is unchanged (let’s assume that there is no load, for now) then the input-side charge q = C1 × V1. Then, if this charge is switched to another capacitor on the output side, q flows to that capacitor but is unchanged, and thus the voltage on the second capacitor changes, as q now equals C2 × V2. If the output-side capacitor is smaller than the input-side one, the output-side voltage will be higher than the input-side voltage.

This almost sounds like something for nothing, but it is not. As charge is “drained” from the output side by the load, the capacitor’s voltage will decrease. To correct this, the input-to-output action must be repeated at a high-enough rate to replenish the lost charge.

Incidentally, the flying-capacitor scheme was used many years ago to provide galvanic isolation between a sensor and a circuit. The sensor for be on the “input” side, while the circuit would be on the output side. The voltage across the sensor would be captured and then transferred to the system circuitry without any ohmic path between the two sides. This scheme has largely been made obsolete by modern isolation schemes using transformer, capacitive, optical, and even RF coupling.

In theory, the transformer or switched-capacitor schemes can be used for transforming, say, 10 or 100 V to thousands of volts. However,  in practice, they cannot be used without major adjustments, as the high-voltage world has some unique issues.

However, as voltages go beyond about 60 V, issues of safety and regulatory mandates become a concern. As these voltages reach into the hundreds and thousands of volts, there are additional unavoidable and non-intuitive issues of material characteristics and electrical phenomena that show that design and construction for these voltage levels is a very different world.

Part 2 of this blog will look at how clever schemes based primarily on diodes and capacitors are used to develop those much-higher voltages using voltage multipliers.

References:

• Flyback converter, Wikipedia
• Cockcroft-Walton voltage multipliers, Wenzel Associates (via TechLib)
• Charge Pumps: The Forgotten Converter, Texas Instruments
• Switched Capacitor Voltage Converters, Analog Devices

—Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors and signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing, and he also developed significant mechanical-engineering insight while designing control electronics for large materials-testing systems.

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• Rich voltage, poor voltage: My incandescent tale

The post Creating higher voltages, part 1: Voltage boosters appeared first on EDN.

Modern RTL verification flows generate more evidence than engineers can always review with equal priority. Simulation, assertions, coverage, and formal analysis each expose different classes of behavior, but a large design can produce hundreds or thousands of properties.

This article describes an AI-assisted workflow that uses machine learning to prioritize those properties while leaving proof and counterexample generation to the formal engine. The approach is intended to complement, not replace, established SystemVerilog, Universal Verification Methodology (UVM), simulation, and formal verification practices.

The problem: too many properties, too little verification time

Verification teams face a practical allocation problem. A complex subsystem may include control-state logic, FIFO interfaces, arbitration, multiple clock domains, configuration registers, error handling, and protocol checks. Each area can generate assertions, and each assertion can have a different verification cost and value. Some properties prove quickly. Others expose difficult corner cases or consume substantial solver resources.

Simulation remains essential because it exercises realistic scenarios, software interactions, coverage goals, and system-level behavior. Formal verification offers a different capability: it can prove or disprove a specified property over the modeled state space under explicit assumptions. Formal methods therefore complement simulation rather than simply compete with it.

The remaining question is operational: when a verification environment contains a large property set, which properties should receive attention first? Engineers normally answer this using design knowledge, coverage, previous failures, proof history, and experience. As designs grow, an automated way to organize that evidence becomes attractive.

AI as a prioritization layer

Machine learning has become an active research area in electronic design automation, including hardware design and verification. For formal verification, the most useful role may be narrower than asking AI to determine whether a design is correct. AI can instead act as a prioritization layer in front of the formal engine.

The model can assign a priority to each property using features such as RTL hierarchy, number of referenced signals, control and data dependencies, state-machine complexity, clock relationships, previous proof duration, coverage gaps, prior failures, and related assertions. The output is a recommendation about verification order, not a proof result.

A five-stage workflow

The workflow can be organized in five stages: RTL and property analysis, feature extraction, AI-based property ranking, formal execution, and feedback.

Figure 1 Here is a broad view of the five-stage AI-assisted formal verification workflow. Source: Author

1. RTL and property analysis: Collect the RTL, assertions, hierarchy, interfaces, assumptions, and available verification metadata.
2. Feature extraction: Convert verification information into features that describe structural complexity, dependencies, coverage, history, and proof behavior.
3. AI-based ranking: Use one or more machine-learning models to estimate which properties may provide useful verification information earlier.
4. Formal execution: Run selected properties in the formal engine, which produces the authoritative proof result or counterexample.
5. Feedback: Feed proof results, counterexamples, and verification history back into the prioritization process.

Why use more than one model?

A single machine-learning model may not capture every relationship in a verification dataset. A hybrid system can compare recommendations from multiple models and look for agreement. If several models independently place a property near the top of the queue, the system can treat that agreement as a scheduling signal.

This does not make the prediction a formal result. The distinction is important. Machine learning estimates where verification effort may be useful; formal verification establishes whether the selected property holds under the specified assumptions.

Figure 2 In this illustrative AI-assisted property prioritization, scores are conceptual and are not measured results from a specific project. Source: Author

Counterexamples can become verification feedback

A formal counterexample contains more information than a pass/fail label. It can expose a state transition, control path, boundary condition, protocol sequence, or assumption associated with failure. A verification workflow can use those observations to identify related properties that deserve attention.

For example, consider a hypothetical subsystem with a FIFO, arbitration logic, and two clock domains. Suppose a clock-domain property receives high priority because it involves multiple clocks, has limited simulation coverage, and is related to previous failures. If formal analysis produces a counterexample, the system can increase the priority of other properties that share the affected control or clock-domain path.

This is a feedback mechanism, not autonomous verification. The engineer still determines whether the property is correctly formulated, whether assumptions are valid, and whether the resulting evidence is sufficient.

Working with UVM and simulation

The AI layer does not require a new verification environment. Existing SystemVerilog and UVM infrastructure already produces useful information, including test results, functional coverage, assertion status, regression history, and debug information.

Figure 3 UVM and simulation data have been integrated with AI analysis, formal verification, and engineer review. Source: Author

Simulation can provide scenario coverage and failure information. UVM can provide structured testbench and regression data. The AI layer can organize these signals and recommend formal priorities. The formal engine can then produce proofs or counterexamples. This division lets each part of the flow retain its established role.

• Review low-confidence or strongly disagreeing model recommendations manually.
• Keep AI priority, formal status, and signoff status as separate fields.
• Record the features and model version that produced each recommendation.
• Make sure that critical properties are protected by explicit rules.

In a continuous-integration environment, the loop can run after an RTL change: identify affected properties, update their features, generate priorities, execute selected formal jobs, collect results, and store the new evidence. The next run can then use that history. The result is a practical feedback loop that fits around existing verification infrastructure instead of requiring a separate verification methodology.

The scheduler should also enforce engineering rules outside the model. A property marked as mandatory for signoff should remain in the verification plan even if the model assigns it a low priority. Likewise, the system can reserve resources for regression baselines while using AI to order the remaining work. This makes the AI layer a scheduling aid rather than an uncontrolled gatekeeper.

For example, a property record might contain the number of referenced signals, hierarchy depth, number of state elements involved, clock-domain count, previous proof time, previous failure frequency, coverage status, and whether the property belongs to a critical interface or reset sequence. These features are useful because engineers can inspect them and relate them to the underlying design rather than relying on an opaque score.

The approach can be introduced without replacing the existing verification tool chain. A lightweight orchestration script can collect RTL and assertion metadata, regression results, coverage summaries, formal proof history, and counterexample information. The collected information can be normalized into one record per property. Each record can then be passed to a trained model or a small ensemble of models that returns a priority recommendation.

Turning the concept into an engineering workflow

Below is an illustrative property prioritization example.

Table 1 In this illustrative prioritization example, the entries demonstrate the method and are not experimental measurements. Source: Author

The main benefit is not that AI makes formal verification mathematically stronger. The benefit is that it can help organize verification work. A team can use prioritization to focus compute time on properties associated with complex control, weak coverage, previous failures, or other signals that indicate potential value.

The same idea can help with regression management. If a new RTL revision changes a particular control path, the system can identify related properties and move them upward in the queue. If a property repeatedly consumes large amounts of solver time without producing useful evidence, engineers can inspect its formulation and decide whether to refine it, decompose it, or change its assumptions.

What AI should not decide

AI-based prioritization introduces a new failure mode if engineers treat a low score as permission to ignore a critical property. The system should therefore preserve explicit criticality rules. Safety-critical, security-sensitive, interface, reset, and other signoff properties may require execution regardless of their predicted rank.

The workflow should also remain explainable. Engineers should be able to see which features influenced a ranking and distinguish between a property that was not selected, a property that timed out, and a property that was formally proven. These states carry very different meanings.

From verification execution to verification management

As IC designs become larger, verification teams need more than additional tests. They need ways to organize the evidence produced by tests, assertions, coverage, formal analysis, and debug. AI can provide one layer of that organization.

The practical model is therefore a division of responsibility. Simulation explores scenarios. UVM structures the verification environment. AI analyzes evidence and recommends priorities. Formal verification supplies rigorous proofs and counterexamples. Engineers interpret the results and make signoff decisions.

AI-assisted formal verification is most useful when it remains an assistant to established verification methods. Using machine learning to prioritize properties can help teams direct limited compute and engineering resources toward potentially informative checks, while formal verification remains the authority for proof and counterexample generation.

The approach does not require replacing SystemVerilog, UVM, simulation, or existing formal tools. It adds a layer that connects the evidence those systems already produce. With appropriate safeguards, that layer can turn verification history and counterexamples into feedback for the next analysis cycle.

Praveen Kumar Vagala is a semiconductor design verification professional and independent researcher with extensive experience in the semiconductor industry.

Related Content

• Introduction to Formal Verification
• Is Formal Verification Artificial Intelligence?
• Formal verification: where to use it and why
• Specifications: The hidden bargain for formal verification
• Formal Verification Moves Firmly into the Design Environment

The post Rethinking RTL flows with AI-driven hybrid formal verification appeared first on EDN.

Take a baseline device, remove a subsequently added protocol and replace it with a function, and…you end up with a bigger-than-expected revision?

As I alluded to in a blog post a week-and-a-half back, I’m nearing the finish line of my teardown series on TP-Link smart plugs. As I mentioned last month, my basic aspiration with this project is to ascertain to what degree (if any) differences in the company’s various smart plug products’ feature sets, broadly between the Kasa and Tapo product lines as well as between products within a given line, are due to hardware variability versus (or in addition to) software-implemented inconsistency.

As such, today’s entry ended up being a deviation from the to-date norm, therefore a pleasant surprise. But I don’t want to ruin it for all of you via a premature reveal, so I’ll keep my cyber-lip zipped for the moment. Here’s the so-far published dissection list:

• TP-Link’s Kasa HS103: A smart plug with solid network connectivity
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again
• TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive
• TP-Link’s Tapo P105: A Kasa EP10 clone, or evolutionarily derived?
• TP-Link’s Tapo P125: A smart plug with an Apple HomeKit vibe

Revisiting another last-month comment, again note that hardware changes can be driven not only by evolving feature set requirements but also by phaseout and replacement of building block components inside these devices. To wit, hold that thought.

Unpacking the patient(s)

Today’s dissection victim is TP-Link’s Tapo P115, a two-pack of which set me back $13.77 during a Thanksgiving 2025 Amazon Resale (formerly Warehouse) used-goods promotion.

Like last month’s Tapo P125, it shares a common form factor with the baseline Tapo P105 I took apart in early June.

But as the above “stock” photo highlights, whereas the Tapo P125 had built on the Tapo P105 foundation with added Apple Homekit support, today’s Tapo P115 instead focuses its enhancement energy on energy monitoring and logging specifically. As such, it’s conceptually akin to the prior-gen Kasa EP25, again with energy monitoring, that went “under the knife” back in March.

What, if any, hardware commonality exists between the Kasa EP25 and Tapo P115? As well as, for that matter, between the Tapo P105 and Tapo P115? Let’s find out, as usual starting with some outer box shots, again accompanied by a 0.75′′/19.1 mm diameter U.S. penny for size comparison purposes.

The Amazon Resale-origination identifying sticker added to the bottom panel left unobscured the hardware version, v1.6. TP-Link’s support page indicates that this is the latest-and-greatest revision, with a v1.26 predecessor. Why do I care about such seeming minutia? I’ll remind you of my early-March coverage of the Kasa EP10, wherein I detailed (for the first time, but definitely not the last) version-based functional shortcomings both in an absolute sense and in “smart home”-striving combination with same-name devices containing different-version hardware.

Picking patient

As was the case last month, opening the packaging and perusing the contents revealed evidence of prior-customer access and device removal, leading me to select that same device for analysis (the one on the left, if not already obvious).

Last month’s noted cuteness continues unabated, of course.

And now, finally free from its cardboard captivity, here’s our patient.

Once again, as is the case with the box containing it, the device’s bottom side is the most informative perspective, revealing factoids including the always-helpful FCC ID (2BCGWP110).

Diving inside

Here’s a vendor-supplied conceptual cutaway to whet your appetite for what’s next (regular readers of my teardowns already know how much I love coming across and sharing these).

How closely (or not) does this marketing creation (or abomination?) match what our eyes see when they peruse the actual insides? Let’s find out.

The inside of the back half of the enclosure is, as usual, bland and boring (unless you’re a plastics specialist, I suppose).

The other half, on the other hand…that’s more like it (including an under-penny further peek) for an electrical engineer like you and me.

Much of it is reminiscent of what we’ve seen before. Here’s the top-side view.

Once again, the relay is a Churod A16-V-105DA2F, although in comparison to its Tapo P125 cousin, it’s 90° rotated and downward shifted location-wise on the PCB this time.

Bottom side view next.

Now to the right.

And the left…wait, what’s this?

Silicon and broader software swaps

The Shanghai Belling BL0937 single-phase energy monitoring IC at right is the same as the one previously seen in the Kasa EP25. Below it is yet another five-lead SOT-packaged IC, presumably housing a dual-transistor combo and seen multiple times before, this time labeled as follows:

JWM3J
5G5hG

And in the middle is, once again, a switch alongside an LED. But check out the processor at left! In every other TP-Link smart plug I’ve taken apart so far, it has come from Realtek Semiconductor and is based on an Arm architecture. This time, in contrast, it’s the RISC-V-based Espressif Systems ESP8684.

The very first page of the datasheet clears up another discrepancy I’d noted; seemingly no discrete flash memory device anywhere on the mini-PCB this time. Instead, the documentation tipped me off that there’s “Optional 2 MB or 4 MB flash in the chip’s package”.

All of which leaves me with no shortage of questions, which do not include the contents of the as-usual difficult-to-access PCB underside (as usual, it’s quite bare, as far as I can tell, and FCC certification photos can fill any nagging knowledge gaps for the curious among you out there).

These questions include (but are not limited) to the following:

• Previously, in transitioning from the conventional Tapo HS103 to the energy-monitoring Tapo EP25, TP-Link migrated from a single- to dual-core Realtek Arm-based chip. To what degree, if any, was a similar performance-boost need behind this more significant shift?
• Were, as I alluded to at the beginning, product shortages or more definitive device phaseouts factors in this particular more significant change of supplier and architecture?
• And to what degree, if any, was a desire to shift to a royalty-free, fully open-source processor architecture behind this design decision, keeping in mind the substantial software porting effort that would be required for TP-Link to actualize its aspiration?

I daresay I’m not likely to get any answers from TP-Link if I inquire, so I doubt I’ll even bother. Or from either Espressif Systems or Realtek, for that matter. But I’m guessing at least a one of you out there has a tangible clue as to what’s going on. Tips, either passed on to me anonymously over email or publicly in the comments, are greatly appreciated!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Tapo or Kasa: Which TP-Link ecosystem best suits ya?
• TP-Link’s Tapo P125: A smart plug with an Apple HomeKit vibe
• TP-Link’s Tapo P105: A Kasa EP10 clone, or evolutionarily derived?
• TP-Link’s Kasa HS103: A smart plug with solid network connectivity
• TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive

The post TP-Link’s Tapo P115: Smart plug subtracts Apple, adds energy tracking appeared first on EDN.

Thermal imaging sits at the intersection of science and engineering, where invisible heat patterns are transformed into visible insights. By harnessing the physics of infrared radiation, converting it into electrical signals, and mapping those signals into pixel-based images, engineers unlock a powerful tool for diagnostics, safety, and innovation.

What makes this field exciting is not just the science—it’s the empowerment it offers: the ability to see beyond the visible spectrum, anticipate problems before they surface, and design solutions that protect, heal, and inspire. When pixels, power, and physics converge, they don’t just reveal heat, they reveal possibilities.

Nature’s blueprint for thermal vision

Nature has long demonstrated the power of thermal perception. Pit vipers detect prey through specialized infrared-sensing organs, beetles locate forest fires by sensing thermal radiation, and certain fish use heat gradients to navigate their environments.

These biological systems remind us that thermal vision is not an artificial invention but an evolutionary advantage. By studying and emulating these natural mechanisms, engineers extend human capability, transforming biology lessons into technology that safeguards industries, advances medicine, and expands the boundaries of exploration.

Figure 1 The image visualizes how a pit viper detects prey using its specialized infrared-sensing pit organ, converting heat signatures into directional cues for precise targeting. Source: Author

The physics beyond “heat vision”

To a maker, a thermal imager isn’t magic; it’s a sensor array tuned for long-wave infrared (LWIR) light. The trick lies in the atmospheric window: while Earth’s atmosphere absorbs most infrared radiation, there’s a transparent band between 8 µm and 14 µm where IR passes through cleanly. Thermal imagers exploit this window, giving us a view of heat patterns without interference from the air.

Deeper physics comes from Planck’s Law. Every object emits radiation based on its temperature, and the peak wavelength shifts as that temperature changes. For room-temperature objects, the peak falls right inside the LWIR band—exactly where thermal imagers are most sensitive. That’s why these devices can reveal the invisible glow of everyday objects, translating physics into practical “heat vision”.

Figure 2 Uncooled LWIR OEM thermal camera module with continuous zoom lens delivers a high-performance imaging solution. Source: Teledyne FLIR OEM

Sensor: The microbolometer

At the core of a thermal imager lies the microbolometer. Unlike the CMOS sensor in a visible-light camera, which counts photons through a photovoltaic effect, a microbolometer is built as a grid of tiny resistors. Each resistor changes its electrical resistance when warmed by incoming infrared radiation. By measuring these resistance shifts across the array, the device constructs a thermal image—turning invisible heat into a visible map of temperature differences.

VOx and a-Si represent two different material approaches to building the resistive pixels. Vanadium Oxide (VOx) has become the industry’s benchmark for high-end sensors because it offers higher sensitivity to small temperature changes and better thermal stability over time. Amorphous Silicon (a-Si), while less sensitive, is cheaper to manufacture and often used in cost-conscious designs where performance trade-offs are acceptable.

Another key factor is the thermal time constant—the rate at which each pixel heats up and cools down. Because the sensing elements must physically absorb and release heat, their response is slower than the instantaneous photon counting of a digital camera.

This is why thermal imagers often feel “laggy”: the image refresh is limited by the physics of thermal inertia, not just by electronics. Engineers designing with microbolometers must balance sensitivity, stability, and time constant to match the intended application.

Figure 3 The PICO384S infrared detector utilizes a 384 x 288 pixel microbolometer array to capture high-contrast thermal imagery in zero-light environments for surveillance, industrial monitoring, and predictive maintenance. Source: Lynred USA

The emissivity trap: Radiometer, not thermometer

The “emissivity trap” is the most important gap-learning concept for new users. A thermal camera is not a thermometer; it’s a radiometer, measuring emitted infrared radiation rather than direct temperature.

Emissivity is a material property—ranging from 0 to 1—that describes how efficiently a surface emits IR energy. High-emissivity surfaces like electrical tape (≈ 0.95) give reliable readings, while low-emissivity metals like polished aluminum (≈ 0.05) reflect more than they emit.

The problem: If a maker points a thermal imager at a shiny copper busbar, the sensor may capture a reflection of its own body heat instead of the copper’s true temperature. Without accounting for emissivity, readings can be misleading—sometimes dangerously so. Understanding this distinction is what separates casual “heat vision” from serious engineering measurement.

Key engineering specifications

When engineers compare thermal camera datasheets, three specifications define performance. Noise equivalent temperature difference (NETD) expresses sensitivity—the effective signal‑to‑noise ratio of heat. A camera with an NETD of 50 mK can resolve temperature differences as fine as 0.05 °C, making subtle gradients visible.

Instantaneous field of view (IFOV) sets spatial resolution, describing how much area each pixel covers at a given distance. It’s not just pixel count but pixel footprint that determines whether small features can be distinguished.

Finally, non‑uniformity correction (NUC) explains the audible “click” many users notice: a mechanical shutter briefly closes so the sensor can recalibrate against a uniform reference, correcting pixel drift and maintaining image consistency. Together, these specifications shape how accurately and reliably a thermal imager translates invisible radiation into usable engineering data.

The maker angle: Integrating thermal into projects

For makers, the real challenge is not just capturing thermal data but integrating it into projects through communication protocols and processing pipelines. The FLIR Lepton module offers higher resolution and uses a Video over SPI (VoSPI) interface layered on SPI/I²C, making it powerful but slightly more complex to handle.

In contrast, the Melexis MLX90640 provides lower resolution but communicates directly over I²C, which is simpler to implement on hobbyist microcontrollers—ideal for cost‑sensitive builds.

Figure 4 The radiometric-capable LWIR camera Lepton 3.5 integrates into mobile devices as an IR sensor or thermal imager, capturing calibrated temperature data in every pixel. Source: Teledyne FLIR OEM

It’s worth noting about the FLIR Lepton 3.x series at this point that its two primary variants—the Lepton 3.0 and Lepton 3.5—focus their differences entirely on internal capabilities, remaining completely identical on the outside. Both micro-camera modules share the exact same 160×120 resolution and compact physical form factor, meaning the true differentiator is the Lepton 3.5’s advanced radiometry.

While the 3.0 acts purely as a thermal imager to visualize relative heat differences up to 120°C, the 3.5 delivers fully calibrated, pixel-by-pixel temperature readings alongside a significantly expanded dynamic range capable of measuring scenes up to 450°C.

Beyond the sensor choice, makers should pay attention to the communication protocols that move thermal frames from sensor to processor. The FLIR Lepton relies on VoSPI, a packetized stream layered on the SPI bus that demands careful timing and buffer management but rewards with higher‑resolution data throughput.

By contrast, the Melexis MLX90640 uses a straightforward I²C register map, where each pixel’s 14‑bit value can be read directly with simple address calls. For hobbyist platforms, I²C feels friendlier—easy to implement on Arduino or ESP32—while VoSPI requires tighter firmware discipline but scales better for real‑time imaging. Choosing between them is less about raw capability and more about how much protocol complexity a maker is willing to embrace.

Once the sensor delivers raw frames, the next step is data processing. Thermal imagers typically output 14‑bit values per pixel, representing temperature intensity. Makers must map these values into a visual palette—common choices include Ironbow, Rainbow, or grayscale—using libraries like OpenCV or lightweight embedded frameworks.

Even microcontrollers such as the ESP32 or Teensy can handle this task, converting raw thermal data into colorized images or live heat maps. This workflow bridges physics and electronics, turning invisible infrared into accessible, project‑ready visuals.

Engineering wins in the real world

Thermal imagers are more than “heat vision”—they are tools of discovery, precision, and problem‑solving. In real‑world debugging, they deliver engineering wins that save time, prevent failures, and inspire innovation. On a PCB, a thermal camera can expose a hidden latch‑up state or a poorly decoupled regulator by revealing the telltale heat bloom.

In mechanical systems, it can uncover stress points, such as friction heating in a misaligned 3D printer lead screw. Even in fluid dynamics, thermal imaging makes the invisible visible, showing the heat dissipation patterns of a custom liquid‑cooling block.

For the electronics fraternity, the challenge is clear: don’t just admire thermal images—use them. Treat every glowing hotspot as a clue, every gradient as a story, and every frame as a chance to engineer smarter, safer, and more resilient systems.

The call to action is to embrace thermal imaging not as a novelty, but as a core debugging instrument. Push beyond “heat vision” and let physics guide your next breakthrough.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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As 5G and 5G-Advanced push uplink efficiency and modulation performance, engineers are revisiting where power amplifier (PA) linearization should happen and how it should be validated. Hardware-in-the-loop testing of AI-based digital post-distortion (DPoD) is now linking today’s 5G measurements with possible 6G receiver architectures.

PA linearity remains one of the hardest tradeoffs when designing wireless communication systems. A user device can operate its PA in the linear region with power backoff to preserve signal quality, but that reduces efficiency and drains battery life. Or it can drive the PA closer to saturation, improving power efficiency while introducing in-band distortion and out-of-band spectral regrowth. In 5G, and increasingly in 5G-Advanced, that compromise is becoming more visible as uplink performance demands rise.

This is one reason why DPoD is attracting attention. Unlike conventional digital pre-distortion, which linearizes the PA at the transmitter, DPoD shifts part of the compensation burden to the receiver. In the cellular uplink, that means the base station attempts to recover a signal that may have been transmitted by a more efficient, more nonlinear user device. The idea is especially relevant for battery-powered equipment at the cell edge, where uplink power efficiency matters most.

Although DPoD is often discussed in the context of 6G, its practical evaluation starts with 5G testing. The key questions are measurable today: How much uplink distortion can a receiver tolerate? Can AI-based receivers recover signals beyond what conventional algorithms can handle? And what test setup is needed to compare the two under realistic conditions?

Why the uplink remains difficult

The peak-to-average power ratio of OFDM signals in the 5G uplink leads to nonlinear distortions when operating the PA of the user equipment (UE) close to saturation. As modulation orders increase, the margin for impairment shrinks further. Higher-order constellations improve spectral efficiency, but they are also more vulnerable to error-vector-magnitude degradation caused by PA compression and phase distortion.

Traditionally, this problem has been managed at the UE with transmitter linearization, calibration, and careful PA operation. But that approach carries costs in complexity, power consumption, and thermal overhead. For smartphones, wearables, and IoT devices, those penalties are not trivial.

That is why receiver-side compensation is being revisited, particularly as 5G-Advanced sharpens focus on uplink performance and 6G research considers more aggressive spectral-efficiency targets.

DPoD does not remove the need for spectral compliance, and it does not make PA nonlinearity harmless. What it does offer is a different system partitioning: Some of the burden of recovering a distorted uplink is shifted from the device to the network receiver.

Why AI-based DPoD matters

Classical post-distortion methods rely on predefined models of nonlinear behavior. Those methods can work well in controlled cases, but real uplink signals are shaped by multiple effects at once: PA nonlinearity, multipath fading, noise, synchronization error, and implementation nonidealities. That makes a purely model-based approach increasingly difficult, especially when thinking beyond current 5G deployments toward 5G-Advanced and 6G.

Figure 1: Nokia and Rohde & Schwarz tested a 6G radio receiver that uses AI to boost uplink distance, enhancing coverage for future 6G networks. (Source: Rohde & Schwarz)

AI-based receivers are attractive because they can learn from representative data rather than relying on a fixed analytical model. One example is Nokia Bell Labs’ HybridDeepRx, a neural-network-based receiver designed for OFDM waveforms affected by channel impairments and transmitter nonlinearity (Figure 2). In the setup discussed here, HybridDeepRx effectively replaces part of the conventional base-station receiver chain.

Figure 2: The HybridDeepRx AI receiver (Source: Nokia Bell Labs)

Its role is not simply to “denoise” the signal. The model jointly addresses channel-related effects and nonlinear distortion, then performs demapping to generate soft information for decoding. A key feature of the architecture is that it alternates between frequency-domain and time-domain processing.

Frequency-domain stages help address channel effects in a way familiar to conventional OFDM receivers, while time-domain stages are well-suited to mitigating PA-induced distortion. This hybrid structure makes it a useful candidate for testing whether AI-based DPoD can outperform conventional uplink receiver processing when the transmitter is deliberately operated in a more nonlinear region.

Hardware-in-the-loop testbed

To evaluate that question credibly, Nokia Bell Labs and Rohde & Schwarz (R&S) used a hardware-in-the-loop testbed built around standard-compliant 5G signal generation and wideband signal analysis. The objective was to compare conventional receiver processing with AI-based reception under controlled but realistic uplink impairment conditions.

Figure 3 shows the overall setup. An R&S SMW200A vector signal generator creates the 5G uplink waveform and applies a PA model, followed by wireless channel emulation. This is important because it allows a controlled introduction of nonlinear PA distortion without changing physical hardware from test to test. Researchers can vary amplifier operating point and distortion level repeatably, which is essential for comparing conventional and AI-based receiver behavior.

Figure 3: Hardware-in-the-loop AI receiver testbed using the R&S SMW200A vector signal generator, FSWX signal and spectrum analyzer, and VSE vector signal explorer to compare conventional 5G uplink reception with Nokia Bell Labs’ HybridDeepRx (Source: Rohde & Schwarz)

On the receive side, an FSWX signal and spectrum analyzer captures the impaired uplink waveform. The FSWX provides the bandwidth and dynamic range needed for this kind of work. The captured signal is then processed in the R&S VSE vector signal explorer software, which serves as the central analysis environment.

VSE plays several roles in the setup: It performs the standard demodulation steps needed for signal analysis; supports KPI extraction such as BLER, BER, throughput and ACLR; and, crucially, can load user-defined AI models in ONNX format. In this case, Nokia Bell Labs’ HybridDeepRx receiver is imported into the measurement flow and executed using GPU-accelerated inference. That creates a direct bridge between AI model development and RF test instrumentation: The same captured waveform can be processed through a conventional algorithm chain or the neural-network-based receiver.

This is where HybridDeepRx becomes central to the measurement concept. Rather than evaluating an abstract AI model offline, the setup places the model directly inside a realistic signal-analysis flow. That allows the comparison of receiver approaches using the same waveform, same impairment conditions, and same measured KPIs such as block error rate and throughput. For engineers, this is much more convincing than a purely simulated benchmark.

The value of the testbed is not limited to proving that an AI receiver can run in the loop. It also helps clarify how much distortion can be tolerated before conventional processing breaks down and whether an AI-based receiver extends that operating region.

Because the R&S SMW200A can impose both wireless-channel effects and controlled PA nonlinearity, the setup can explore a range of realistic uplink cases, from mildly impaired links to strongly compressed transmission. This makes it possible to study a key architectural question for future systems: If the receiver becomes more intelligent, can the UE be allowed to transmit less linearly and therefore more efficiently?

That question matters because receiver-side compensation may improve bit recovery, but it does not remove the physical consequences of PA compression. The value of a hardware-in-the-loop setup is that it keeps the evaluation grounded in measurable signal behavior and system-level KPIs rather than algorithm claims alone.

From 5G measurement to 6G architecture

This makes AI-based DPoD a good example of how 5G testing is feeding future wireless architecture. The waveforms, KPIs, and measurement discipline are rooted in today’s 5G and 5G-Advanced work. But the system question being explored points toward 6G: whether some of the uplink linearization burden can move from power-limited devices to compute-rich infrastructure.

That possibility is attractive because the uplink is where device constraints are least forgiving. If future base stations can recover more heavily distorted signals, UEs may be able to operate with simpler or more efficient transmitters in difficult link conditions. For cell-edge users, that could translate into better power efficiency without an equivalent penalty in coverage or throughput.

The concept is still emerging, and many challenges remain, including generalization across devices, channels, and deployment conditions. But the combination of a realistic 5G waveform source, controlled PA and channel emulation, wideband signal capture, and in-tool AI inference provides a practical way to study the idea now.

AI-based post-distortion is not just a theoretical 6G topic; it is already a 5G test problem. And as this work shows, progress depends on hardware-backed comparison between established receiver methods and AI-based alternatives, using tools that let both live in the same measurement flow.

About the author

Andreas Oeldemann is program manager of AI for wireless at Rohde & Schwarz, headquartered in Munich. As part of the corporate R&D team, his work focuses on how novel T&M solutions will enable the validation and deployment of physical- and MAC-layer AI/ML methods of 5G-Advanced and 6G communication systems. In this role, he investigates future customer requirements for testing AI/ML implementations in the air interface, develops early proof-of-concept T&M solutions, and drives collaborations with industry partners and academic institutions to advance 6G R&D. He holds an M.Sc. in electrical engineering from the Technical University of Munich.

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Traditionally, every generation of cellular technology has been mostly about moving data faster. However, 6G is shaping up to be a different kind of upgrade. The industry’s focus is shifting from how fast a network can move data to what new services and experiences it can deliver, with artificial intelligence enabling this shift.

6G is being designed to embed AI deeper into the radio access network (RAN) and core, enabling the network to predict demand peaks before congestion sets in and manage radio resources in real time. That same intelligence could also help the network make use of its own infrastructure and wireless signals to provide data and gather information about the physical environment.

AI already exists in 5G networks, but 6G is designed to integrate these capabilities more deeply into the network architecture. 6G is still being defined through the 3rd Generation Partnership Project (3GPP) standards process, and many of these technologies are in the trial stage. Still, the direction is becoming clear as AI, distributed computing, and sensing are becoming as integral as new frequencies, lower latency, and data rates.

6G standardization & 3GPP

3GPP started to study 6G in Release 19, which was completed in December 2025. Release 20 evaluates foundational items for 6G, including studies of AI, sensing, and new architecture of the 6G network, and it is expected to be completed by 2027. Release 21 is now open for contributions and will be the first normative 6G specifications, pending finalization of its scope and timeline, and is expected to build on top of Release 20 studies and be completed by 2030.

Commercial 6G systems are still expected around 2030, although pre-commercial deployments and field trials will appear earlier. Many of the technologies being considered for 6G are already being introduced through 5G-Advanced, giving vendors and operators a chance to test capabilities such as AI-driven network optimization and integrated sensing and communication (ISAC) before committing to larger 6G deployments.

At the same time, 6G development is not limited to consumer networks. Governments and defense departments are also exploring potential use cases, particularly where communications, computing, sensing, and real-time decision-making need to work together. The U.S. Department of Defense is exploring 6G technologies and prototypes for military applications, adding another potential source of demand for early 6G systems.

The U.S. government’s Mission 6G 28 initiative is another example of this push toward early testing. The initiative is encouraging industry-led demonstrations of technologies, including AI-driven networking and integrated sensing, ahead of the 2028 Los Angeles Olympic Games. These demonstrations use pre-standard technology, providing an early look at which concepts can move from research into real-world environments.

Vendors are also developing tools to support these early trials, giving operators and research and development teams a way to test new capabilities before the standards are finalized.

3GPP’s timeline for Release 21 (Source: 3rd Generation Partnership Project)

The standards process provides the industry with key milestones to watch. Release 20 is expected to conclude in 2027, followed by the development of the normative 6G specification in Release 21 and the final protocol freeze in March 2029. After that, the focus shifts to operators and equipment manufacturers to turn those specifications into reliable systems.

AI-RAN

One of the clearest examples of AI moving into the network is in the RAN, which includes the base stations and antennas that connect devices to the cellular network. Traditionally, RAN equipment has been built around proprietary hardware and custom silicon designed for telco-specific functions with long upgrade cycles. AI is starting to challenge that model, but the industry is not taking one single approach.

Ericsson is taking a more evolutionary approach. The company is embedding AI capabilities into the RAN infrastructure that operators already have, with the goal of improving performance without a costly, large-scale hardware replacement. Early trial results point to real gains in efficiency and throughput, particularly around scheduling and radio resource management.

Nokia and Nvidia are pushing something more transformative. Their AI-RAN uses graphics processing unit (GPU)-based computing alongside traditional telco workloads, turning the RAN into a more flexible compute platform.

Nvidia backed this vision with a $1 billion investment in Nokia, and the two companies already have live trials running with T-Mobile. Putting more GPUs into the RAN brings additional computing capacity but also higher power consumption, cooling requirements, and infrastructure costs. Operators will ultimately have to decide whether the revenue from running AI workloads at the edge is enough to justify those costs.

If operators mostly want better network performance, adding AI to existing RAN infrastructure may be enough. However, the case for GPU-based AI-RAN becomes stronger if operators see an opportunity to turn that additional compute into a new business around distributed AI workloads.

The 6G core

AI is also starting to reshape the network core, the part of the network responsible for routing traffic, managing connections, and allocating resources. In May 2026, 3GPP advanced two competing approaches for integrating AI into the 6G core, with both now being studied in parallel.

The first, Solution Variant #18.1, puts AI directly into the core through new, agent-based network functions. These functions could interpret an intent from a user or application and orchestrate existing network functions to carry it out.

The second, Solution Variant #18.3, keeps AI separate from the core. A dedicated AI domain would interact with existing network functions through a translator function, allowing AI to optimize and orchestrate the network without fundamentally changing the core itself.

Two approaches for integrating AI into the 6G core (Source: ABI Research)

Variant #18.1 is being pushed primarily by Chinese vendors and operators, including Huawei, ZTE, and the major Chinese carriers, while Variant #18.3 has support from Western vendors and operators including Nokia, Ericsson, AT&T, T-Mobile, Qualcomm, and Google. SK Telecom is notably involved in both, reflecting the fact that the industry has not settled on a single path.

For now, 3GPP is keeping both options open. Where AI ends up sitting in the core will shape network architecture and vendor influence for years.

Integrated sensing and communication

As AI makes the network more capable of making decisions and managing itself, sensing can give it more information about the physical environment around it. ISAC uses its existing wireless signals for both communication and sensing, allowing cellular infrastructure to detect and track objects without dedicated sensing equipment.

Recent trials are starting to show what it could look like in practice. For example, in July 2026, AT&T and Ericsson used existing 5G infrastructure outside the AT&T Stadium in Texas to detect, locate, and track multiple drones flying between 300 and 400 feet. The system used existing massive multiple-input/multiple-output radios, signal processing, and AI-enabled sensing rather than a separate radar system.

The demonstration is a useful proof point, but it is not yet a replacement for dedicated radar. It’s more likely a near-term role as an additional layer of sensing, particularly in places where cellular infrastructure is already widely deployed. Drone detection, perimeter security, industrial sites, ports, and logistics facilities are the likely first use cases.

The bigger test will be whether ISAC can move beyond controlled trials and demonstrate performance across different environments, weather conditions, distances, and object types. If ISAC can handle those conditions, it could give AI-driven networks another important input, allowing them to make decisions based on what is happening in the physical environment and inside the network.

What to watch

The next few years will show whether 6G can deliver on the larger idea that it is less about a faster connection and more about the network becoming an intelligence platform. The clearest checkpoints are on the standards calendar: Release 20 studies conclude in 2027, the architecture is due to be finalized in 2028, and the first normative 6G specs freeze in March 2029. This will determine the technical standards, but what operators do in practice comes down to whether AI, distributed computing, and sensing can create enough value to justify the cost and complexity of putting them deeper into the network.

This is what truly differentiates 6G from previous generations. The network is becoming part of the computing infrastructure and can process AI workloads closer to the source, make decisions about how network resources are used, and gather information about the physical environment. That moves 6G beyond the traditional role of connecting devices and toward a more intelligent network.

This is a follow-up to ABI Research’s 5G & 6G: Adoption, Technologies and Use Cases.

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