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When applying an input signal to an operational amplifier (op amp) that is far beyond its bandwidth, you would expect that the op amp would reject or attenuate the input signal. For example, if you’re applying a 600-MHz input signal to an op amp with a 10-MHz bandwidth, you would expect the 600-MHz signal to have significant attenuation. Both SPICE and general amplifier theory will predict this expected output.

Unfortunately, the high-frequency noise will not be rejected, and will actually cause a shift in the op amp’s input offset voltage (VOS). In addition to the shift in offset, some of the high-frequency noise will simply pass through the op amp.

Some op amps are better at rejecting this high-frequency signal than others: The ability of an op amp to reject radio-frequency signals is called the electromagnetic interference rejection ratio (EMIRR). See the application report, “EMI Rejection Ratio of Operational Amplifiers” with OPA333 and OPA333-Q1 op amps as a design example.

Amplifiers with good EMIRR often have a simple internal filter on the input pins of the op amp. Amplifiers with this feature are called EMI-hardened. The input filter is a simple RC filter where the amplifier inputs have small resistors and capacitors placed both in common mode and differentially across the inputs (Figure 1). The input resistors generate noise, and the differential capacitor can degrade amplifier stability, so there are limits to how effective this filter can be.

Figure 1 Here is how EMI-hardened op-amp works using input filtering. Source: Texas Instruments

To improve the EMI rejection, many engineers choose to add an external filter capacitor across the input pins of the op amp. This can be an effective solution, but the op amp generally needs additional components to maintain stability. Stability in this context is the ability of an op amp to properly amplify a signal without oscillating.

Op amps can become unstable when connecting a capacitive load to the output pin or when capacitance connects to the inverting node. For the EMI filter, the concern is the capacitance on the inverting node because the filter capacitor is connected between the inverting and noninverting nodes.

It’s possible to use a transient small-signal step on the input or a transient load step on the output of an op amp to test stability. The amount of overshoot to the step directly relates to the circuit phase margin, which is a measurement of stability. A circuit is considered to be stable with an overshoot of less than 23%, which corresponds to a phase margin of greater than 45 degrees.

For a circuit with a filter on the input pins, test the stability with an output load step rather than an input step. An input step does not work for this circuit because the edges on the input step will be filtered by differential capacitance.

Figure 2 shows the transient response stability test for the uncompensated amplifier to a ±1 mA load step. The circuit in this example is a difference amplifier with a 1-nF filter capacitance between the inputs. For the load-step stability test, the initial output transient spike is the step size, and the following spike is the overshoot.

Figure 2 A transient output load stability test shows instability. Source: Texas Instruments

The percentage overshoot for Figure 2 is 68.2% (see Equation 1):

The Analog Engineer’s Calculator can convert the percentage overshoot to a phase margin of 13.8 degrees (Figure 3). The circuit is unstable, since a phase margin of greater than 45 degrees is required for stability.

Figure 3 Analog Engineer’s Calculator is used to convert overshoot to phase margin. Source: Texas Instruments

Understanding why the input capacitor causes instability requires some background in stability theory. Figure 4 shows the standard open-loop test circuit applied to the same circuit that underwent the transient stability test.

Figure 4 Here is a view of open-loop test circuit for op-amp stability. Source: Texas Instruments

The open loop is the most accurate way to test stability; it provides curves for open-loop gain (AOL), loop gain (AOL×β), 1/β, and phase margin (Figure 5). Stability is tested at the point where 1/β intersects AOL. The phase margin is the phase shift where AOL intersects 1/β.

Figure 5 Open-loop stability results show instability. Source: Texas Instruments

The phase margin for the open-loop circuit is 17.5 degrees, whereas the phase margin from the transient step test was 13.8 degrees. Technically the two numbers should match exactly, but there are some differences because the transient test assumes that the system is a second-order system. Nevertheless, the results are reasonably close, and both results indicate instability.

The open-loop test has an additional benefit in that it provides insight into what is causing the stability problem and how to stabilize the circuit. One way to understand the source of the stability issue is to use the rate-of-closure (ROC) rules. The ROC looks at the difference in slopes where the AOL and 1/β curve intersect.

If the difference in slopes is greater than 40 dB/decade, then the circuit is unstable. In Figure 5, the slope of AOL is –20 dB/decade, and the slope of 1/β is +20dB/decade. The difference between these two slopes is 40 dB/decade, so the circuit is unstable (Equation 2):

To correct the stability issue, you need to adjust the ROC to 20 dB/decade. The problem in this example is that 1/β has a zero at approximately 87.5 kHz, which causes the gain to increase by 20 dB/decade (Equation 3):

Adding a pole at the same frequency cancels this zero. The zero frequency is set by CIN and 2 × RG, and CF and RF set the pole frequency. To set the pole frequency the same as the zero frequency, choose CF so that RF × CF = RIN × CIN. In this example, setting CF = 100 pF will cancel the zero (Equation 4):

Setting CF = 200 pF yields the open-loop response shown in Figure 6. Note that the 1/β curve is completely flat because the pole and zero cancel each other (Equation 5 and Equation 6). Since the ROC is now 20 dB/decade and the phase margin is 81 degrees, the circuit is stable.

Figure 6 Stable open-loop response is shown with CF = 100 pF. Source: Texas Instruments

The compensated transient response, shown in Figure 7, also shows minimal overshoot and no ringing, indicating good stability.

Figure 7 Stable transient response is shown with CF = 200 pF. Source: Texas Instruments

Setting the pole and zero in 1/β equal provides good stability and also improves noise, since the noise-gain peaking is minimized. It’s possible to stabilize the circuit and increase the bandwidth using a smaller value of CF, however. Equation 7 gives the minimum value of CF that will stabilize the circuit, and Equation 8 applies the example values.

Figure 8 shows the open-loop and transient response for the minimum CF value (CF_MIN = 47pF). The phase margin is lower for the minimum value of CF compared to the case where the pole and zero cancel, but the circuit is still very stable (phase margin = 62 degrees).

Figure 8 Open-loop and transient response is shown for minimum CF compensation. Source: Texas Instruments

Figure 9 compares the bandwidth and noise for the two compensation options.

Figure 9 Here is a comparison between bandwidth and noise for two different CF compensations. Source: Texas Instruments

Stabilize the circuit

When using a capacitive filter across the input pins of an op amp, it’s important to use feedback capacitors to stabilize the circuit. The theory presented in this article is useful for understanding the root cause, but not necessary to compensate the circuit. Ultimately, you can stabilize the circuit by choosing the feedback capacitors according to Equation 3.

The feedback capacitor can also be helpful in reducing noise and stabilizing circuits with capacitive load. In general, it’s a good idea to include a placeholder for the feedback capacitors in most op-amp circuits because it can often be helpful in resolving stability and noise issues.

Art Kay is application engineer at Texas Instruments.

 

 

 

Related Content

• The perils of input capacitance
• Active filters: Design tips and tricks
• Tips and Techniques for Capacitor Testing
• Designing RC active filters with standard-component values
• Testing op amp tools for their active filter design accuracy and dynamic range

The post Op-amp input filtering can cause instability without proper compensation appeared first on EDN.

Inconsistency is a fundamental bane of troubleshooting. So it goes at work…and also at home.

At some point(s) in your engineering career, have you ever had the “pleasure” of inheriting the ongoing development and maintenance for a poorly-at-best documented project whose original leader was no longer available for advisement? Me too; I’ve dealt with handoff aftereffects for more than a dozen years so far with no definitive end in sight, albeit with increasing clarity as time passes. But in the case study described today, my project is personal, not professional.

When my then-fiancée (now-wife) and I bought the home we now live in, the previous owner had recently passed away and the original builders/owners were also no longer available for consultation (the husband is also deceased, I believe; I don’t have any contact-or-other info about his wife). So, aside from a pile of user manuals, receipts and other paperwork, I was pretty much on my own in sorting out the plumbing, mechanical, electrical, and other aspects of the residence.

An incomplete history

Judging from reputation per conversations with neighbors, not to mention the thick speaker wiring still installed in various rooms’ walls and baseboards, along with a nice set of B&W outdoor speakers, the prior owner was an enthusiastic audiophile. And judging from the sizeable living room plasma television, not to mention the projection system downstairs, also a videophile (as well as, I suspect, a “techie”).

So, it was no surprise to be told by the realtor that the home was already pre-wired for Comcast (a.k.a. Xfinity, the company’s brand for consumer products and services) broadband and television. That said, the only residence-specific detail I was aware of, and mentioned by the realtor only in passing, was that the prior owner “had another line of service installed” at some point. Hold that though.

When I moved in, I transferred my existing Comcast service from my previous Colorado residence, a process that to the best of my recollection was quick and painless. Coax cable runs on top of (plus shallowly under) the ground, as well as being attached to exterior walls at three of the four sides of the home, along with shielded, outdoor-rated Ethernet cable (all of which I’ve mentioned before).

The technician showed me which coax feed I should plug my cable modem into. And with that, for the next decade-plus and beyond relocating that strand’s interior end to my furnace room, which became the home’s networking nexus, and upgrading my service tier during the COVID-19 pandemic, ignorance was bliss.

I’ve played around a bit with MoCA in attempting to wired-extend the LAN to two guest bedrooms downstairs, versus running new Ethernet feeds or just relying on Wi-Fi. Beyond that, I kept the various wall-mounted coax connectors scattered around the house capped with terminators, since I was instead leveraging Windows Media Center over Ethernet to distribute TV service from a networked CableCard triple-tuner device and a Windows 7-based PC to various Xbox 360-based clients.

A missed-map mishap

Eventually, I expanded from a single-router setup to a multi-node mesh network, still using wired Ethernet for the backbone. All this time, the mysterious plastic box labeled “Comcast” in one corner of the property nagged at me.

As did the realtor’s cryptic “prior owner had another line of service installed” insight. But in the spirit of “if it works, don’t touch it,” I held my curiosity at bay…until last October, when necessity first forced my hand. In preparation for the nearby emergency access road construction that began shortly thereafter, the community’s water and sanitation service upgraded my neighborhood’s hydrants, so they could alternatively act as conveniently-located refill sites for water trucks. Unfortunately, in the process of replacing the hydrant across the street from me, they inadvertently also cut the thick coax feed(s) that Comcast-serviced my residence as well as that of my next-door neighbor.

After alerting Comcast to the fact that I was having a problem that was theirs, not mine, to solve (I can’t count the number of times I’ve heard the words “when’s the last time you replaced your cable modem” in the last near-year), they sent out a diagnostics tech, who confirmed the cut.

The community’s water and sanitation service washed their hands of the issue, since it turns out Comcast had seemingly neglected to add the wiring to publicly accessible maps post-initial installation. And it took another couple of days to get a different Comcast technician out to spend nearly a day digging up the wiring, re-splicing it back together, and re-burying it.

Broadband and television service came back up immediately…but only for about 24 hours; then they went down again, this time only for a couple of hours (that day, at least). I’d never experienced Comcast flakiness before, so it wasn’t much of stretch to associate not only a correlation but a more definitive causation between what I was now experiencing and the day-prior repair attempt.

I’d already realized that a simple cable splice, versus a comprehensive full-run replacement, would result in at least a modicum of SNR loss. I deduced the incremental signal degradation had “pushed” our apparently already-marginal service “over a cliff”, at least periodically.

What symptoms did I notice whenever I was having Comcast service issues, aside from the fact that LAN devices would lose Internet connectivity and sometimes the router itself would also go down (since the Google Nest system is cloud-managed)? The second LED from the top of my Netgear CM1100 cable modem, referencing downstream connectivity, would perpetually blink, with those below it non-illuminated.

And speaking of the cable modem, sometimes even when I was online, the third LED down, referencing upstream connectivity, would still blink (versus its usual steady-illuminated state). That all said, unless broadband connectivity went down for an extended period, and sometimes even if it did, television service often still remained “up”.

Convincing Comcast of the validity of my ongoing issues—not to mention the company’s ongoing responsibility for solving them—was a different matter. The first tech that came out had given me his business card with an invitation to reach out if I continued having issues. Every time I texted him—I did strive to practice at least some restraint—he’d remote-check my modem and CableCard status and report back no issues logged on his end, including no T2, T3 or T4 timeouts.

There was also seasonal variability to the unreliability (assumed associations: ambient temperature and moisture). As autumn turned to winter, the outages thankfully became less frequent, at least for a while (again, hold that thought). So, I eventually gave up trying to get someone back out on Comcast’s dime and switched over to cellular hotspots whenever broadband started flaking out.

Learnings and lingering mysteries from this portion of the story:

• The Comcast “tap” that services me and my next-door neighbor, it turns out, is at the very end of the line that runs through our neighborhood. Service-drop alerts sent to Comcast when customers’ cable modems, set-top boxes, and the like go offline only automatically result in a “truck roll” when a critical mass of customers are simultaneously affected. I don’t remember the exact number, but I think the tech said a half-dozen or thereabouts. Otherwise, Comcast logs the situation as a potential issue (similar to what happens if a customer reports an outage over the phone or in-app) but by default assumes a power outage or other unrelated-to-Comcast problem is the root cause of the service glitch. This is why I had to work so hard on my end to get the repair going in the first place.

• You might have noticed in the earlier photos I took last fall that there are two thick coax feeds that had gotten severed. Particularly given that ours was the last line “tap”, I was baffled as to why there wasn’t just one cut cable. Descriptions sometimes refer to such lines as “loops” or “rings”, which initially explanation-contented me. But I more recently came up with what I think is a more likely answer. Again, hold that thought.

Another year, another cut cable

Fast-forward to June of this year. We were still getting occasional outages, but only a couple of times a month, most of them lasting only a few minutes each, and typically happening in the mid- to late-afternoons (again, with an assumed ambient temperature association). But one day, broadband was up-and-down (lather, rinse and repeat) for several hours straight. I decided to take a break from work and go for a hike around the neighborhood, wherein I came across a bunch of Comcast trucks.

Apparently, an Xcel Energy boring machine digging a pathway under the road in preparation for running electrical cabling had once again sliced through a Comcast feed, this one servicing an entire street’s worth of customers next to ours. And although we didn’t solidly lose service where I lived, the technician I spoke with indicated that as part of the repair, they were re-tuning all the area’s line RF amplifiers, thereby explaining why our service was also up-and-down for so long that afternoon. Here’s what a few of the neighborhood RF amps look like:

Including this one near the cut location, which for some reason, ended up with its top still off (or is this a broader area-servicing fiber coax transceiver node, readers? Let me know in the comments!

And then there’s this unidentified (again, readers?) hunk of equipment right next to it, also surrounded by Comcast “flags”, in this case with its cover still intact albeit ajar.

Unfortunately, this re-tuning apparently further suppressed the ongoing SNR at my residence, because beginning the very next day I started experiencing more frequent outages again, this time roughly every other day. I eventually rang up Comcast again and scheduled a technician call for the next day. That evening, when service came back, Comcast called me back and tried its best to convince me to cancel my appointment, but I strongly declined the offer.

I’ll continue the story in part 2 of this series, scheduled for publication next week. Until then, I as-always welcome your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Dear Comcast, we haven’t yet tangled our last
• Keeping technology user-friendly and simple: the latest failure example
• Will a location change improve my MoCA?
• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• A quest for faster upstream bandwidth
• Debugging a “buggy” networked CableCARD receiver

The post Debugging intermittent Comcast, part 1: Scenario-setting appeared first on EDN.

Quectel’s 4G SH602FA and 5G SE505FE smart modules feature built-in Android 16 to accelerate industrial and commercial IoT development. The modules enable developers to build connected products such as handheld terminals and inspection devices with rich user interfaces and enhanced multimedia performance.

The 4G SH602FA is powered by a MediaTek MT8786 chipset with a 64-bit octa-core processor comprising two Arm Cortex-A75 cores and six Cortex-A55 cores. An Arm Mali-G52 MC2 GPU supports graphics-intensive embedded applications without requiring an external host processor. The smart module integrates LTE Cat 4, Wi-Fi 802.11ac, Bluetooth 5.1, and GNSS, along with camera and touch-panel interfaces. 

Offering Android 16-powered 5G connectivity, the SE505FE leverages a MediaTek MT8863T chipset with a 64-bit octa-core processor comprising two Arm Cortex-A76 cores and six Cortex-A55 cores, along with an Arm Mali-G57 GPU. The module supports 5G sub-6-GHz and LTE Cat 4, together with Wi-Fi 6, Bluetooth 5.2, and GNSS.

A timeline for module availability was not provided at the time of this announcement.

SH602FA product page 

SE505FE product page 

Quectel Wireless Solutions 

The post Smart modules bring Android 16 to IoT designs appeared first on EDN.

A Class-D mono audio amplifier, the PAM2011Q from Diodes delivers up to 3 W of output power for automotive applications. Designed for instrument clusters, dashboard and backup cameras, driver notification chimes and warnings, and emergency call (eCall/T-box) systems, the filter-free amplifier provides 1.8-mA quiescent current and up to 94% efficiency.

The PAM2011Q comes in a compact, thermally enhanced package and requires minimal external components, simplifying design and reducing system cost. It operates from a 2.8-V to 6.0-V supply and delivers 2.53 W at 1% THD and 3.15 W at 10% THD from a 5-V supply into a 4-Ω load. Audio specifications include THD+N below 0.03% and 21-µV integrated output noise (A-weighted) at 6-dB gain.

The amplifier is AEC-Q100 qualified and operates over a junction temperature range of -40°C to +125°C. Integrated de-pop circuitry provides silent startup and shutdown while eliminating unwanted noise. Overvoltage and overtemperature protection with auto-recovery are also integrated to enhance system reliability.

The PAM2011Q is available now from Mouser Electronics.

PAM2011Q product page

Diodes Inc.

The post Class-D amplifier enhances automotive audio performance appeared first on EDN.

The Vertex 6.0 channel emulation platform from VIAVI supports carrier frequencies up to 23.6 GHz and 400 MHz of instantaneous bandwidth. The company says it is the industry’s first channel emulator for 6G and Wi-Fi 7/8 testing, meeting newly defined 6G waveform requirements and exceeding Wi-Fi 7/8 bandwidth requirements. The enhanced platform features field-replaceable RF modules that can be installed in an existing 6U Vertex chassis.

Building on the 5G FR1/FR2 capabilities of the previous generation, Vertex 6.0 recreates real-world wireless conditions in the lab for complex cellular, Wi-Fi, military, and aerospace RF applications. Combined with the VIAVI FR3 MIMO converter and raytracing, the platform serves as a digital twin for RF propagation, enabling use cases such as FR3, Wi-Fi 7, AI-RAN, and ISAC.

Each chassis accommodates 36 RF ports, 256 digital links, and up to 1.6 GHz of bandwidth. For cellular technologies, the platform handles FR3 bands with up to 1 GHz of bandwidth. For Wi-Fi 7/8, it offers native support for 320 MHz and 4096 QAM in 2×2 to 8×8 configurations. The channel emulator supports land-to-land, land-to-air, and air-to-air transmissions, including anechoic and reverberation OTA chambers, NTN (LEO, MEO, and GEO), mesh, drone, and ISAC networks.

Vertex 6.0 product page

VIAVI Solutions  

The post Channel emulator adds 6G, Wi-Fi 7/8 testing appeared first on EDN.

Kinetic Technologies’ KTS1642Q AEC-Q100-qualified load switch protects automotive loads from abnormal power-supply or load conditions. When used with the appropriate external TVS diodes, the device supports ISO 7637-2 transient requirements while helping designers address the electrical stress conditions of ISO 16750-2.

Operating from 4 V to 40 V, the KTS1642Q integrates two N-channel MOSFETs with 41-mΩ on-resistance and delivers 6 A of continuous output current. It provides reverse-battery protection to -28 V, fixed 20.3-V overvoltage protection with a typical 360-ns response time, overtemperature protection with auto-retry, battery detection, and a fault flag output. Input ESD protection meets IEC 61000-4-2 Level 4, with ±2-kV HBM ESD protection on other pins per AEC-Q100-002.

The load switch operates over a temperature range of -40°C to +125°C and is supplied in a 4×4-mm TDFN. The KTS1642AQGDV-TR features an active-high enable, while the KTS1642QGDV-TR features an active-low enable. Both versions are available now.

KTS1642Q product page 

Kinetic Technologies 

The post Load switch guards automotive power rails appeared first on EDN.

Standard MCUs in Toshiba’s TXZ+ Series M4V Group enhance security and data management in IoT devices and industrial control equipment, ranging from smart home appliances to factory automation systems. The devices feature a multilayered security architecture that combines access control, memory protection, and execution control functions, helping protect systems against unauthorized access and program tampering.

Based on an 80-MHz Arm Cortex-M4 core with an FPU, the M4V MCUs’ on-chip memory includes 128 KB of code flash, 64 KB of data flash, and 32 KB of RAM with parity support. Both flash memories support up to 100,000 rewrite cycles, and dual mode enables one flash area to be rewritten while instructions are executed from the other. The data flash can retain rewritable data such as configuration and log data, enabling data management tailored to the operating conditions of the equipment.

The MCUs operate with a supply voltage of 2.7 V to 5.5 V, making them suitable for consumer and industrial equipment with 5-V power supplies. An integrated 10-MHz oscillator provides ±1% frequency accuracy over the full operating temperature range of -40°C to +105°C, eliminating the need for an external oscillator.

Toshiba has started shipping engineering samples of the TXZ+ Series M4V Group MCUs. The M4V Group includes four package options to accommodate different PCB sizes and assembly requirements.

TXZ+ M4V Group product page 

Toshiba Electronic Devices & Storage

The post MCUs strengthen security in IoT and control systems appeared first on EDN.

This basic beat oscillator makes continuous wave keyed code and single sideband suppressed carrier signals audible.

A recent Design Idea from contributor Gavin Watkins shows an inexpensive add-on beat frequency oscillator (BFO) for inexpensive and vintage short-wave radio receivers.  It makes reception of highly efficient amplitude modulation transmission formats like CW (continuous wave keyed code) and SSBSC (single sideband suppressed carrier) possible on basic, inexpensive radios that otherwise couldn’t.  It’s very cute and thrifty.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Today’s Design Idea (Figure 1) does a similar job, but takes less space while needing only about half as many components.  Also, the parts it does require are easier to source.

Figure 1 This 455 kHz intermediate frequency beat frequency oscillator is tuned by R1.  The amplitude of the injected IF signal is adjusted by R3.  It works happily with a wide range of supply voltages and so needs no regulator.

Here’s how it works.

Both single-sideband suppressed carrier (SSBSC) and (the somewhat misleadingly named) keyed continuous wave (CW) radio transmissions share the lack of a steady carrier wave reference.  Eliminating the carrier and redundant sideband is good because it increases transmission efficiency in both bandwidth and transmitter power utilization.  But it adds complexity to the receiver because then it must provide the missing reference frequency to produce an audible and intelligible signal. 

Some basic, mainly older, receivers can’t do that.  What to do for them?  We can simply tack on a BFO. An add-on BFO works by injecting a low-level signal into the receiver’s IF chain that:

1. Is manually adjustable to be the correct amplitude that allows the receiver’s existing automatic gain control (AGC) loop to respond to and follow the incoming RF signal normally.
2. Is tuneable to accurately match and sum with the IF frequency so that, when mixed with the IF signal by the receiver’s final detector, it can recreate the SSB suppressed carrier and modulation audio.

The oscillation frequency is given by the following equation:

Fo = 1/(ln(2)(R3 + R4)(C1 + Cs) + Td)
where
Cs = stray capacitance = ~15pF
Td = internal 555 delay (See Related Content link #2) = ~212ns

With the component values shown, it’s tunable over 455 kHz +/-20%.

The oscillator output is taken from pin 7 rather than 3 to maximize isolation and minimize coupling between the IF chain and BFO oscillation frequency.  This is important for audio quality. 

The output amplitude is adjusted by R3 over a range of 0 to (V+)/2.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Add-on beat frequency oscillator (BFO) for shortwave radio
• Improve 555 frequency linearity
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• Gated 555 astable hits the ground running
• Can a free running LMC555 VCO discharge its timing cap to zero?

The post Single sideband radio meets LMC555 beat frequency oscillator appeared first on EDN.

The future of advanced packaging is not one universal package. It’s a technology platform capable of placing the right interconnect, material, die, memory stack, optical engine, and thermal structure at the right system boundary.

For many years, the design sequence appeared straightforward:

Design the chip → select the package → connect it to the board

That sequence is becoming less accurate. AI accelerators, high-bandwidth memory (HBM), chiplets, optical I/O, advanced cooling, and high-current power delivery are now so tightly coupled that the package can no longer be selected after the system architecture is largely complete.

The package increasingly determines:

• How the system can be partitioned
• How many chiplets can be integrated
• Where silicon-class interconnect density is required
• Where broader and lower-cost routing is sufficient
• How HBM is placed and connected
• Where electrical path should transition to optic
• How power reaches the compute elements
• How heat leaves the package
• How assembly can be manufactured, tested, repaired, and qualified

The package is no longer merely supporting the system. It’s defining what system can be built.

From package choice to packaging platform

Traditional packaging discussions often compare individual technologies:

• Should the design use a silicon interposer?
• Would a local silicon bridge be sufficient?
• Should fan-out redistribution replace part of the substrate?
• Should the system use 2.5D or 3D integration?
• Should optics remain at the front panel, move near the package, or become co-packaged?

These remain important questions, but they are no longer independent choices. A modern AI system may require several of these technologies at the same time.

A broad interposer may connect compute chiplets and HBM. Here, localized bridges may provide silicon-class density only at selected die boundaries. And fan-out redistribution may extend routing across a larger area. Next, vertical stacking may integrate cache, memory, control, or specialized processing. Then there are optical engines that may sit near the package edge.

A thermal structure may also need to remove highly non-uniform heat from several dies with different power densities. Finally, the system may also require test access, known-good-die strategies, repair paths, redundancy, and manufacturing flows that span several suppliers. This is why advanced packaging is moving from isolated process choices toward integrated technology platforms.

A platform does not force every product into one structure. It provides a coordinated set of technologies from which the system architect can select the right realization method for each boundary.

Vertical integration’s two meanings

The phrase vertical integration is often interpreted physically. But that is the first meaning.

Physical vertical integration

Dies, memory stacks, interconnect layers, optical engines, power-delivery structures, and thermal components are placed beside or above one another. This includes technologies such as:

• 2.5D integration
• 3D die stacking
• Package-on-package structures
• Through-silicon or through-glass vias
• Vertically-integrated power delivery
• Stacked memory and logic

Physical stacking is important because it can shorten interconnects, increase bandwidth density, reduce footprint, and place functions closer together. But there is a second meaning that may be even more important.

Technology platform integration

Different packaging technologies become coordinated elements within one ecosystem. A platform may combine:

• Broad-area fan-out routing
• Localized silicon bridges
• Full silicon interposers
• Vertical stacking
• System-in-package integration
• Co-packaged optics
• Assembly and bonding processes
• Package-level test
• Thermal and mechanical structures
• Manufacturing and reliability flows

In this model, vertical integration does not mean that every component must be stacked. It means the complete realization capability is integrated across design, materials, process, assembly, test, and system requirements. That is the deeper transition.

In other words, the future is not one package replacing all others. It’s a platform selecting the right precision, material, and integration method at each boundary.

Different boundaries need different precision

One of the most important architectural questions is: How much of the package truly requires silicon-class interconnect density?

A full silicon interposer can provide extremely dense routing and short connections across a broad area. But that precision comes with cost, area, yield, manufacturing, and mechanical consequences. Not every connection requires the same pitch or routing density.

Some die-to-die boundaries may require very fine-pitch interconnect. Other regions may only need moderate-density redistribution. Still others may be adequately served by an organic substrate or board-level connection.

A platform approach allows the package to become hierarchical: Silicon-class density where necessary.

• Fan-out or redistribution where broader routing is needed
• Substrate-level routing where lower density is sufficient

This avoids using the most expensive and complex technology everywhere. The objective is not maximum integration at every location; the objective is appropriate integration at every boundary.

Fan-out more than a package format

Fan-out packaging is often discussed as a package category. But within a larger platform, fan-out can perform several architectural roles. It can:

• Provide broad redistribution beyond the original die footprint
• Support heterogeneous die integration
• Reduce dependence on a large silicon interposer
• Connect local high-density regions to broader package routing
• Create a transition between chiplet-scale and substrate-scale interconnect
• Support system-in-package or package-on-package structures

Fan-out chip-on-substrate approaches can combine redistribution-layer density with the mechanical and routing capabilities of a larger package substrate. A fan-out bridge architecture can place localized silicon-class interconnect only where adjacent dies require it.

This allows precision to be concentrated rather than distributed uniformly across the complete package. That is not simply a manufacturing variation; it’s an architectural choice about where density should reside.

Bridges and interposers are complementary

Silicon bridges and full interposers are sometimes presented as competing technologies. They are better understood as different tools.

A broad interposer can provide:

• Dense routing across a large region
• Extensive die-to-die connectivity
• Controlled electrical paths
• Close integration between compute and HBM
• Broad placement flexibility

A local bridge can provide:

• Very high density at selected chiplet boundaries
• Reduced silicon area
• More localized precision
• Potentially lower cost for systems that do not require a full interposer
• A path to combine high-density and conventional routing within one package

The correct decision depends on:

• Die placemen
• Required pitch
• Routing density
• Signal reach
• Power delivery
• Thermal expansion
• Warpage
• Assembly tolerance
• Yield
• Test
• Cost

A packaging platform should therefore not declare one technology universally superior. It should allow the architecture to place each technology where it creates the greatest system value.

HBM makes package a compute boundary

HBM has already transformed the package. The connection between the accelerator and HBM is no longer a peripheral interface; it’s part of the compute architecture.

HBM placement determines:

• Achievable bandwidth
• Energy per bit
• Interposer or bridge requirements
• Package area
• Routing density
• Power delivery
• Thermal interaction
• Mechanical balance
• Yield and assembly complexity

As the number of HBM stacks grows, the package becomes larger and more difficult to manufacture. So, the system must manage:

• Interposer scale
• Reticle boundaries
• Die placement accuracy
• Warpage
• Underfill
• Bump reliability
• Heat-spreader geometry
• Non-uniform thermal loading
• Package-level test

The package is therefore not merely connecting compute to memory. It’s determining the physical shape of the compute system.

CPO an element of the platform

Co-packaged optics (CPO) is often treated as a separate technology story. But CPO cannot scale independently from advanced packaging. Moving the optical engine closer to a switch ASIC or accelerator may reduce electrical reach, SerDes power, and front-panel density pressure.

It also introduces new package-level responsibilities:

• EIC-to-PIC connectivity
• Optical attach
• Fiber routing
• Laser placement
• Wavelength control
• Thermal drift
• Calibration
• Optical test
• Compound yield
• Repairability
• Serviceability

A future AI package may combine:

• Compute dies
• HBM
• A full or partial interposer
• Localized bridges
• Fan-out redistribution
• Electrical I/O chiplets
• Optical engines
• External laser interfaces
• Power delivery structures
• Integrated cooling

CPO is therefore not simply another component added beside the ASIC. It changes the electrical, thermal, mechanical, manufacturing, test, and serviceability boundaries of the complete package. However, the package must create the environment in which optical performance can ensure repeatable system performance.

Optics moves inward only when the package platform can absorb the consequences of moving it inward. This is why CPO belongs inside the larger packaging-platform discussion.

Thermal architecture chosen with the package

As more functions move into the package, thermal design can no longer be treated as an external cooling problem. Different dies produce different heat fluxes. HBM, compute chiplets, I/O dies, optical engines, voltage-regulation structures, and control electronics may all have different temperature limits.

The package architecture determines:

• Which devices share a heat spreader
• Where thermal-interface materials are placed
• How bond-line thickness is controlled
• Whether a lid, cold plate, vapor chamber, or direct-liquid structure is required
• How mechanical pressure is distributed
• How thermal expansion affects interconnect reliability
• Whether optical alignment drifts with temperature

A package platform must therefore support more than electrical connectivity. It must coordinate the thermal path with the die placement, interconnect architecture, assembly process, and reliability requirements.

The best electrical placement may not be the best thermal placement; the best thermal placement may complicate fiber routing or package test. This is why package architecture is a system trade-off, not an isolated layout decision.

Power delivery also a package decision

AI systems require large current with rapidly changing load demand. As package power rises, the distance between voltage regulation, decoupling, power planes, and compute dies becomes increasingly important.

So, the package may need:

• Improved vertical power delivery
• Backside or near-die power structures
• Integrated voltage regulation
• Lower-inductance current paths
• More distributed decoupling
• Coordinated signal and return-current design

Power delivery interacts with:

• Chiplet placement
• HBM placement
• Interposer routing
• Thermal density
• Mechanical structure
• Package height
• Available routing layers

Manufacturing and test platforms

A package can be electrically attractive and still be difficult to manufacture. A platform approach must connect architecture choices to process capability. Questions include:

• Can the required die-placement tolerance be achieved?
• Can the redistribution layers be fabricated at the required scale and yield?
• Can the bridge or interposer be assembled without unacceptable warpage?
• Can underfill penetrate the available stand-off?
• Can thermal stack be controlled within bond-line limits?
• Can optical interface survive assembly and thermal cycling?
• Can each die be tested before integration?
• Can the completed assembly be tested after integration?
• Can failed modules be repaired or replaced?
• Can failed modules be repaired or replaced?

The package architecture is not complete when the drawing is complete. It’s complete when the process can repeatedly produce the intended geometry and performance. Manufacturing does not merely build the package; it creates the physical structure through which the system must operate.

Next, as the number of integrated dies increases, test complexity grows rapidly. A platform must account for:

• Known-good-die requirements
• Pre-bond test
• Post-bond test
• Interposer and bridge continuity
• Memory test
• Optical loopback
• Thermal calibration
• Power-delivery validation
• Fault isolation
• Repair or redundancy strategies

The challenge is especially severe when dies from different suppliers are integrated into one product. A failure in one small component can affect the yield of the entire assembly. This creates a compound-yield problem.

The value of a platform is therefore not simply that it offers several package technologies. It should also provide coordinated design rules, assembly flows, test access, metrology, failure analysis, and reliability evidence across those technologies.

System architecture now begins with workload

The new design sequence should begin with the workload and move downward into physical realization. Here, the deterministic chain encompasses:

• Workload requirements
• System partitioning
• Compute and memory placement
• Electrical and optical boundaries
• Package architecture
• Power and thermal architecture
• Manufacturing and test strategy
• Verified system performance

This reverses the older assumption that the package is selected near the end. The package platform must be taken into consideration from the beginning because it defines which partitioning options are physically and economically possible. A system architect cannot decide where compute, memory, optics, and power should reside without understanding the package technologies available to connect and sustain them.

Platform is not product

There is one important caution. A large portfolio of packaging technologies does not automatically produce a successful AI system. The platform provides options, but the product must still select and coordinate them correctly.

Adding more technologies can also increase:

• Process interactions
• Supplier dependencies
• Yield risk
• Test complexity
• Thermal coupling
• Mechanical stress
• Qualification burden
• Cost

The winning package will not be the one that includes the greatest number of advanced technologies. It will be the one that uses each technology only where its benefit exceeds its integration burden.

A local bridge may be better than a full interposer in one system. A full interposer may be essential in another. Near-packaged optical (NPO) may provide the right optical boundary for one product and CPO may be justified for another.

Vertical stacking may reduce latency but worsen thermal density. Fan-out may reduce cost but impose different warpage and process constraints. Therefore, the architecture must be selected based on system evidence, not technology enthusiasm.

Advanced packaging is no longer a menu of isolated process choices. It’s becoming the architecture through which compute, memory, electrical interconnect, optics, power delivery, cooling, manufacturing, and test are assembled into one realizable system.

The future is not one universal package. It’s an integrated technology platform capable of placing:

• Silicon-class density where it’s necessary
• Broader redistribution where it’s sufficient
• Vertical stacking where proximity creates value
• Optics where electrical reach becomes limiting
• Cooling where heat is generated
• Test access where failure must be isolated

The package is no longer selected after the system is defined. It increasingly determines which system architecture can be realized, manufactured, qualified, and scaled. The winning platform will not be the one that stacks the most technologies. It will be the one that places each technology where its system benefit exceeds its realization burden.

The chip defines capability. The package platform defines the system.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

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The post AI silicon: Package becoming system architecture appeared first on EDN.

This proposed design eliminates traditional additional requirements for AGC, AC coupling, and post amplification circuitry.

This Design Idea presents a simple op-amp-based sine wave oscillator that directly generates a low-impedance bipolar output of approximately 20 Vpp at frequencies above 100 kHz. The circuit was developed to directly drive an AD633 in an on–off keying (OOK) digital transmission system.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Many sinewave oscillators reported in the literature provide a unipolar output and require additional circuitry for automatic gain control (AGC), AC coupling, and post amplification to achieve the desired amplitude. The proposed circuit eliminates these requirements by directly generating a high-amplitude bipolar sinewave.

The circuit (Figure 1) consists of an LC tank connected in a feedback loop with an op-amp configured as an inverting amplifier with a gain set by the R3/R2 ratio. At the resonance frequency, fosc = 1/(2π√(L·Cs)), where Cs = C1 || C2, the LC network introduces 180° phase shift, while the inverting amplifier provides an additional 180°, resulting in a total loop phase shift of 360°, thus satisfying the Barkhausen phase condition.

Figure 1 This simple LC oscillator uses an op-amp and the intrinsic losses of the resonant tank to generate a stable low-distortion 20 Vpp sine wave without AGC.

The topology can be viewed as a simplified Colpitts oscillator in which the op-amp both sustains oscillation and compensates for the losses of the resonant network. A key practical advantage is that the oscillation amplitude is set by the op-amp closed-loop gain, primarily through the feedback resistor R3, allowing straightforward amplitude control without additional circuitry.

The prototype was implemented using the LT1357, a high-speed op-amp featuring high slew rate and wide gain-bandwidth product. In general, a wideband op-amp with sufficient slew rate and gain-bandwidth product is required, particularly as the oscillation frequency increases.

Resistor R1 is not critical in value and primarily serves to isolate the op-amp output from the LC tank, preventing degradation of the phase margin due to the reactive load. At resonance, assuming an ideal inductor, R1 is effectively in series with R2 and forms a voltage divider. Its value should therefore be kept small relative to R2 to limit attenuation of the LC network, but not so small as to excessively load the op-amp, resulting in a practical design trade-off.

At startup, the loop gain is greater than unity, allowing oscillation to build up from noise. As the amplitude increases, current in the LC tank also increases, leading to higher losses due to winding resistance and ferrite core dissipation. These losses introduce additional attenuation in the resonant network, progressively reducing the loop gain until it reaches unity.

At equilibrium, the energy provided by the op-amp exactly compensates for the tank losses, and the oscillation amplitude stabilizes. The op-amp remains in its linear region, and the resulting waveform is very close to an ideal sine wave, as confirmed by oscilloscope capture (Figure 2).

Figure 2 The waveform generated by the circuit is very close to an ideal sine wave.

The oscillation frequency remains essentially constant as the amplitude varies, indicating that inductance variation due to core nonlinearity is negligible. The circuit was built and tested experimentally (Figure 3).

Figure 3 The circuit was breadboarded, versus simply simulated, to more definitively validate its functionality.

The measured frequency is approximately 120 kHz, compared to a nominal value of about 124 kHz, with the difference mainly attributable to component tolerances, particularly in the ceramic capacitors and the inductor .

The value of R3 depends on the characteristics and quality factor of the inductor. In the prototype, the inductor was hand-wound on a ferrite toroid to obtain approximately 100 µH. When reproducing the circuit, R3 may require empirical adjustment depending on the specific inductor used.

This oscillator provides a simple and effective solution for generating low-distortion sine waves at medium–high frequencies, offering easy amplitude control via op-amp gain while eliminating the need for dedicated amplitude control circuitry and directly delivering a low-impedance bipolar output.

—Luca Bruno has a Master’s Degree in Electronic Engineering from Politecnico of Milano. He taught electronics and telecommunications for many years at ITI Hensemberger and has published numerous Design Ideas in EDN on analog and electronic circuit design.

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The post Op-amp LC oscillator uses tank losses for amplitude stabilization appeared first on EDN.

As a long-time analog-component and circuit “practitioner,” I view the schematic diagram as the starting point for almost any discussion of a design. It shows the signa flow, the primary ICs, other necessary but often underappreciated passive and active devices, the connectors, power source and distribution tree, and much more.

I sat down with the late circuit genius and prolific EDN contributor Jim Williams many years ago. See “This 30-ppm scale proves that analog designs aren’t dead yet” for just one of the many circuits he devised and explained in his articles published at EDN. As I sat down with him, he literally sketched out and talked through a clever yet conscientious design in real time; it was a master class in circuit explanation and exposition.

But lately I’ve been wondering to what extent we still need these schematics. In the era before large-scale analog ICs, a schematic was not only a diagram of what connected to what, but also a debug and troubleshooting guide. You could follow the signal flow from stage to stage, and separate the stages if needed, to see if a stage’s output corresponded correctly to its input.

A classic six-transistor AM-radio schematic makes this very clear (Figure 1).

Figure 1 This classic six-transistor AM radio has no processor, and its schematic diagram shows a linear signal flow from left to right, with RF stage/local oscillator, IF amplifiers, audio-stage driver, and audio power amplifier. Source: All American Five Radio

Things have changed; that’s for sure. Many electronic circuits now consist of a central processor, often with integrated analog I/O, plus perhaps a specialized network or other processor IC, along with connections to I/O including switches, displays, indicators, and similar. In other words, what we really need is an interconnection wiring diagram rather than a stylized schematic.

Consider a representative analog measurement function for an optical module for heart rate and blood oxygen (SpO2) measurement. Early units used a handful of individual devices, starting with the LED and its driver, going across to the phototransistor and its preamp, and then the rest of the signal chain that captured, conditioned, and digitized the output to show the relevant reading.

Now, the needed functions are largely integrated into a single IC such as the Analog Devices MAXM86161A, which includes the LED drivers, photodetector amplifier, analog and analog/digital functions, optical cancellation circuity, and I2C interface (Figure 2). All that’s missing is the user display, LED and photodetector, a soft on/off switch, and battery, plus a few capacitors and pullup resistors.

Figure 2 The MAXM86161A IC provides electro-optics for heart rate and blood oxygen monitoring, incorporating electrical and optical-friendly features. Source: Analog Devices

So, a product schematic diagram consists primarily of connections to that IC (Figure 3).

Figure 3 A highly integrated, tightly focused IC such as the MAXM86161A does not need many I/O connections. Source: Analog Devices

For this modest medical device, a hybrid block diagram/partial schematic is actually more informative, as it shows smaller-scale ICs with an independent processor (Figure 4).

Figure 4 A blend of conventional schematic diagram and high-level block diagram provides insight into system functionality and overall circuit action. Source: Microchip Technology

In many cases, the wiring diagram rather than the formal schematic is often of more use. When my microwave oven died, I opened the front panel out of curiosity and found both of those diagrams tucked inside (an unexpected but pleasant surprise). The below schematic (top) doesn’t really show what the wiring diagram clearly does (bottom). The innards are really a “mystery” control module with lots of connectors for keypad, display, safety interlock switches (lots of those), thermal overload switches and, of course, the magnetron tube that makes it all possible.

 

Figure 5 You can be the judge of which is more useful: the schematic diagram (top) or the wiring diagram (bottom) of this consumer microwave oven. Source: GE Appliances

Making it right

A good schematic tells the story of a design and shows how the different functional blocks relate to each other. For a not-so-good example, consider the one of Figure 6, also a heart rate and SpO2 monitor. It may have all the facts, but it certainly doesn’t tell the story at all.

Figure 6 This schematic of a heart rate and SpO2 monitor may be correct, but it’s hard to say; even if it is, it’s not very useful. Source: ResearchGate

It seems unnecessary to restate the obvious, but the guidelines for a good analog-centric schematic are simple. I have seen schematics from students which miss these points:

• Have signal flow from left-to-right to the extent possible.
• Use meaningful net names such as GND, SPI_CLK, SENSOR_OUT; designation such as Net_25 mean little. Even the circuit’s creator won’t remember these a few months later.
• Group components by function, such as power, processor, sensors, and interfaces. My personal peeve is when all the bypass and bulk capacitors—and there can be dozens—are clustered in one corner of the schematic connected between the power rail and ground, without any indication of which IC a particular capacitor is supporting. That may be electrically correct, but it’s terrible in terms of the story, and useless for the inevitable debug and troubleshooting process.

But wait…there’s a counter to the story

On one side, the increasing use of large-scale analog-centric ICs with 40, 50, or more contacts is changing the function of the schematic diagram. Does this mean that conventional schematics are going the way of the six-transistor radio?

That was my fear, but then I realized I was only looking at the situation through one end of the telescope, so to speak. If today and the future are all about highly integrated, multifunction analog-centric ICs, why do vendors collectively release hundreds of single-function analog ICs every year (and that’s doesn’t include the countless power discrete devices, controllers, and management devices)?

Three examples show the reality. There’s the Analog Devices ADG2712 quad SPST switch (top), the Texas Instruments LVx886 zero-drift, low-noise op amp with multiplexer-friendly inputs (middle), or the STMicroelectronics TSC1801 current-sense amplifier (bottom) shown in Figure 7.

Figure 7 Despite the trend towards much highly integrated analog ICs, vendors still introduce many small, single-function ones such as this quad SPST switch, specialized low-drift op amp, and current-sense amplifier. Source: Analog Devices, Texas Instruments, and STMicroelectronics

Each one of these implements a basic function that is essential yet would be difficult, if not impossible, to implement with the needed performance in a larger multifunction IC. In most cases, doing so would require excessive compromise in one or more parameters such as leakage, bias current, on resistance, drift, and stability. It’s a long list. By offering single-function analog ICs, the compromises related to process, design, packaging, and cost are minimized or at least easier to manage.

Of course, once you have a circuit with these components, you’re going to need a real, story-telling, signal-flow schematic. So maybe I am too worried.

What are your thoughts about the future of schematic diagrams? Will it fade away, morph somewhat, become an entirely new technical entity? Or will it remain pretty much as-is?

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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The post Do we still need schematic diagrams for analog circuits? appeared first on EDN.

Bluetooth and Wi-Fi combine to untether smartphone-to-car connections…this time with a Google, versus Apple, angle.

Last month, I took apart a third-party adapter that aspires to augment Apple’s CarPlay interface with wireless connectivity between iPhone and vehicle.

This time, I’ll be disassembling the other adapter I’d mentioned at the end of late January’s initial conceptual coverage, in this case intended to wirelessly bridge between a car and an Android-based handset using Google’s Android Auto protocol.

But once again, the originally planned hardware target of my dissection attention isn’t what you’ll actually be seeing today. Initially, I’d planned on taking apart the v1 AAWireless unit, which I’d bought several years back in its original Indiegogo crowdfunding form.

But then I remembered that AAWireless had notably iterated the hardware (and associated software) design in-between that initial version and what ended up going into full production where it was sold and stocked not only by the manufacturer but also retailers like Amazon. AAWireless has already moved on to its second-generation product, in fact.

Supplier switcheroo, part 2

I didn’t want to further limit the project’s relevance by focusing on the rarer premier version of the first-generation offering (which put the company on the map, mind you, but still…). Instead, today you’ll be seeing the insides of this adapter (model BY969C).

It came from a company named “Vnilrgle” (believe it or not, and despite the user manual variously alternatively mentioning “TERUNSOIU”, or maybe that’s “TERUNSOIL”, as the supplier) and cost me a whopping $9.99 plus tax (with free shipping) from Woot in late February (versus listing for $48.87 on Amazon as I write this). Here are more stock shots to whet your appetite.

As you may have already noticed from one of them, this adapter model was of particular interest to me because of its low price, its quality construction (belying the $10 I paid for it), and its integration of NFC functionality, which aspires to simplify the initial setup process.

I’ll start out with shrinkwrap-inclusive front and back shots, as-usual accompanied by a 0.75′′ (19.1 mm) diameter U.S. penny for size comparison purposes, and revealing additional labeling.

The shrinkwrap-clinging stickers are absent from the now-clear-plastic-less backside photo that follows.

Time to open ‘er up.

Some literature bits (here’s an online version of the user manual).

And an optional-use double-sided sticker for, as I also said last month, adhering the wireless adapter to the vehicle interior.

As with its Apple CarPlay-supportive predecessor, this one includes a USB-A-to-USB-C adapter.

And here is today’s patient standalone, viewed from top.

Bottom.

Cable-entry point.

And cable connector-end perspectives.

Sh-sh-sh-shattered

(Obligatory admittedly-obscure-to-at-least-some section header reference)

Now to get inside. You’ve likely already noticed the gap between the silver-color circumference of the device body and the clear flat regions, both of which I’d assumed were made of plastic (for NFC reception reasons). My attempts to insert a spudger were unsuccessful, however.

So, I stuck the device in my vise (see what I did there?) in preparation for an attempted hacksaw-cut of one side. Oops.

I guess that’s glass, not plastic. And I won’t be using this device post-teardown. Onward.

Now for the other side, with tap-assistance from a ball peen hammer.

See those four screws? Not anymore, you don’t.

And with them removed, we have achieved liftoff.

An “Ultra” foundation for the fortunate

Let’s look first at the PCB underside (based on a device orientation assumption that places the product logo on the NFC antenna “top” side, with the marking minutia on the “bottom” side).

At left in the three-area-dominant IC row is the system processor. I mentioned last month, generally speaking about the wireless Android Auto and/or CarPlay product category, that “these are commonly Arm-based”. Judging from the markings on top of this one, there’s no doubt as to whose CPU core(s) is/are inside.

I’d even go so far to guess Cortex-A7 in generation. But who makes it? A search on “BU2025021” brought up bupkis. And the only reference I found to an “A7 Ultra” was associated with this Vanzen dual Android Auto-plus-CarPlay wireless adapter.

Although…”Cotex”?

Anyhow, to its right is the presumed serial-interface (therefore eight-lead package) firmware storage NOR flash memory, from GigaDevice and marked as follows.

AP2133
5F1GQ5UEY1H
UG5131

“1G” is suggestive of a 1 Gbit capacity, but I can’t find a direct reference to the IC anywhere online; reader assistance is welcomed! GigaDevice also makes Arm-based SoCs, by the way, so the company also acting as the source for the “A7 Ultra” wouldn’t be a complete surprise to me.

If you’re wondering (assuming my guess is correct) why 128 Mbytes of storage is necessary to implement a seemingly elementary device like this, my answer is two-fold albeit related.

• It doesn’t just handle Android Audio protocol and USB-to-wireless bridge functions
• And that capacity isn’t solely devoted to code

Turns out there’s also a web server (and pages) running inside the device, used for firmware-update and broader technical support-outreach functions, as this user manual page documents.

In fairness, circling back for a moment, the CarPlay adapter I took apart last month offers similar capabilities. I finally dug up an online version of the user manual for it; here’s the relevant page.

What’s the frequency, Kenneth?

(Another obligatory admittedly-obscure-to-at-least-some section header reference)

Finally, at far right is the wireless communications subsystem, based on the AIC8800DC40 controller from AICSemi, a company previously unknown to me, and surrounded by embedded Wi-Fi and Bluetooth antennae. Once again referencing last month’s writeup, I’d written the following.

Two wireless broadcast links are necessary: 2.4 GHz Bluetooth for initial setup, and Wi-Fi for ongoing streaming. The latter is usually based on the 5 GHz band for higher transfer bandwidth, since range isn’t a concern in a diminutive vehicle interior.

But in that teardown, I’d only found one antenna, suggestive of Bluetooth-plus-Wi-Fi shared usage, therefore 2.4 GHz-only system functionality. And this time, a datasheet I found online for the AIC8800DC40 suggests that it has 2.4 GHz-only Wi-Fi capabilities, even though the device documentation makes the following claims.

Wi-Fi Bluetooth module frequency:
Bluetooth 2.4 GHz, Wi-Fi 2.4-5.8 GHz

So… In search of clarity, I went looking for an FCC ID, which I hoped would lead me to definitive certification documentation. Believe it or not, nowhere related to last month’s patient—packaging, literature, or device itself—had I been able to find an FCC ID reference, or even a product name that might indirectly point me to my desired certification-data prize. Here’s what Google AI Assistant rightly said in response to my search query on “WOLIOS carplay adapter FCC ID”.

The WOLIOS wireless CarPlay adapter does not have an official, dedicated FCC ID registration tied directly to the “WOLIOS” brand name. Budget-friendly online resellers like WOLIOS often rebrand generic white-label factory units (such as common smart dongles) that may display general CE/FCC compliance claims or use an unverified label rather than maintaining an authentic, searchable filing in the FCC ID Database.

Alrighty, then. This time I at last had a valid model code, BY969C. With it, I tracked down the FCC ID (2A5XO-BY969D), which as it turned out covered a variety of products with different model numbers, physical appearances and both Android Auto and CarPlay support, suggestive of common hardware differentiated via firmware. And yes, both 2.4 and 5.8 GHz beacon support.

Speaking of antennae, and in closing, let’s now flip the PCB over to its topside and more closely check out that NFC subsystem.

Sequentially detaching the antenna from the PCB, both from connector and adhesive perspectives, and then peeling off its accoutrements, results in the following image sequence.

Note the LED that shines through the NFC antenna center “hole” and out the top of the device.

And now to dispense with the foam (at least most of it) between the double-sided sticker and antenna itself.

A Google search on the “BY969-LS-V01-NFC-HXW” product code stamped on top of the NFC antenna was of no help whatsoever. Alas. Unless, that is, I’m mistaken and it’s actually a Textured Johnny Collar Sweater Polo from Original Penguin by Munsingwear, sold by (but sold out at, as I type this) J. Crew Factory stores.

With that final bit of silliness out of the way, I’ll wrap up for today. Sound off in the comments with your thoughts on Rolling Stones or R.E.M. songs, men’s sweaters or anything else discussed in this piece!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Adapter makes Google’s wireless Android Auto a reality appeared first on EDN.

Every engineer’s confidence in measurement rests on more than the instrument—it depends on the interface that ties instruments together into a working system. Standards like GPIB, USB, LXI, PXI, and VXI are not just acronyms; they are the lifelines that enable communication, synchronization, and scalability across labs and production floors.

Understanding these interfaces equips engineers to unlock the full potential of their tools, ensuring precision today while building readiness for tomorrow’s challenges. This fundamentals guide maps the evolution and role of these connections, showing how mastery of interfaces translates directly into mastery of measurement.

Interfaces as the backbone of measurement

Instrument interfaces are the quiet enablers of every test setup, defining how equipment communicates, synchronizes, and scales. From the legacy reliability of GPIB to the plug-and-play familiarity of USB, and from the networked flexibility of LXI to the modular power of PXI and VXI, these standards form the connective tissue of modern measurement.

Mastering them isn’t just about knowing acronyms; it’s about gaining the confidence to build systems that are precise, adaptable, and future-ready. By understanding the fundamentals of these interfaces, engineers equip themselves to unlock the full potential of their instruments and drive measurement forward with clarity and control.

Legacy heavyweights: GPIB and serial

Before “plug and play” became the industry standard, test and measurement benches relied on a rugged era of “plug and screw-in” connectivity, dominated by GPIB (IEEE-488) and serial interfaces. GPIB is instantly recognizable by its massive, 24-pin Centronics-style connector and notoriously stiff, heavily shielded cabling.

Despite its bulk, GPIB offered a unique, ingenious hardware feature: stackability. Because the cables featured a male connector on one side and a female on the other, engineers could literally stack five or six connectors directly on top of a single instrument port to daisy-chain devices together, keeping complex automated test systems organized.

Figure 1 The GPIB interface in the B2901B source/measurement unit (SMU) incorporates the device into automated test systems, enabling seamless communication with legacy controllers and peripheral hardware. Source: Keysight

Parallel to GPIB, traditional RS-232 and RS-485 serial communication typically relied on robust DB9 or DB25 D-Sub connectors to lock down data links. While these legacy ports were a staple of early automated test setups, modern instrument backplanes have largely phased out the bulky D-Sub form factor.

Today, you are much more likely to find an RJ-45 or USB-B port that “emulates” serial communication. Transitioning to these modern setups often requires specific adapter cables—such as the ubiquitous “Cisco blue cable”—bridging the gap between classic serial protocols and modern benchtop connectivity.

The modern bench: USB and Ethernet

If you have bought a piece of test equipment in the last 15 years, there is a 90% chance your back panel is dominated by USB and Ethernet connectivity. Unlike the fragile Type-A ports found on modern consumer electronics, most instruments standardize on the chunkier USB Type-B port (the classic “printer cable” connection).

It’s a deliberate choice by instrument designers; the Type-B architecture is physically much more robust, providing the mechanical stability needed to survive the constant plugging, unplugging, and cable-tugging common in a busy lab environment. However, navigating instrument USB ports requires a bit of spatial awareness.

While the Type-B port on the back is meant for raw PC control, many instruments feature a standard USB-A port right on the front panel. It’s crucial to remember that this is a “Host” port. It is there to let the instrument control peripheral devices—like saving screenshots to a thumb drive or hooking up a mouse for easier UI navigation—and cannot be used to interface the equipment directly with a computer.

That mechanical status quo is finally shifting, however, with the slow but steady arrival of USB-C on the test bench. While engineers initially feared its tiny footprint would be too fragile for heavy lab use, its massive data bandwidth and high power-delivery capabilities are proving too good to ignore.

Modern compact USB oscilloscopes and smart, battery-powered field instruments are increasingly adopting USB-C, allowing them to simultaneously stream high-speed sample data to a PC and pull operational power over a single, reversible cable.

LXI/Ethernet (RJ-45)

If USB is the king of close-range bench automation, Ethernet is the undisputed champion for remote testing, distributed systems, and distributed lab networks. Utilizing the standard 8P8C (RJ-45) jack, modern Ethernet-enabled instruments generally conform to the LAN eXtensions for Instruments (LXI) standard, transforming a simple local network into a highly synchronized, long-distance test environment.

But Ethernet brings an even bigger hardware advantage to the bench: galvanic isolation. Unlike USB connections, which share a common DC ground between the instrument and your PC, Ethernet architecture is inherently transformer-coupled. This creates a physical, magnetic barrier for electrical DC currents.

If you are working with high-power systems or floating measurements where your instrument’s chassis sits at a different electrical potential than your PC, Ethernet eliminates the risk of “ground loops.” It ensures that a sudden voltage spike or ground fault will not travel down the communication line and catastrophically blow up your PC’s motherboard.

Figure 2 Arrow points to the LXI port on the RIGOL DS1202Z-E rear panel. Source: Rigol

The unsung hero of automation: Digital I/O interface

While analog channels get all the glory for capturing waves and signals, the digital input/output (digital I/O) interface is the quiet workhorse that turns standalone Test & Measurement (T&M) instruments into fully automated systems. Think of it as the instrument’s binary nervous system. It uses simple high/low voltage signals (typically TTL or CMOS levels) to communicate with the outside world.

Through digital inputs, an instrument can listen for external triggers—like a sensor detecting that a device under test (DUT) is properly in place, or a companion machine signaling is ready. Conversely, digital outputs allow the instrument to command its environment, such as triggering an external laser, switching a relay, or flashing a red warning light if a test fails.

For engineering students and hobbyists transitioning from manual bench testing to automated production lines, mastering digital I/O is the crucial first step toward building smart, synchronized, and hands-free test environments.

Figure 3 The digital I/O interface is on the rear panel of the Keithley 2602B SMU. Source: dataTec

High-speed backbone: PXI, PXIe, and VXI

When benchtop space is at a premium and a handful of standalone instruments can no longer keep up with massive channel counts or ultra-high throughput demands, the “instrument” undergoes a physical evolution. While VXI served as the rugged, VMEbus-based grandfather of this movement in the late 1980s, modern high-density testing has largely migrated to PXI and PXI Express (PXIe).

In these automated test equipment (ATE) environments, traditional boxes give way to modular instrumentation systems like PCI eXtensions for Instrumentation (PXI) and PXI Express (PXIe). In these systems, instruments lose their front panels, screens, and individual power supplies, transforming into compact, modular cards that slide into a shared industrial rack.

These card-edge modules do not work alone; they require a dedicated chassis to provide the necessary power, cooling, and communication pathways, alongside a dedicated controller card that serves as the system’s “brain.” What truly separates PXI/PXIe from consumer-grade PC chassis, however, is its high-density “hard metric” backplane connector packed with hundreds of pins.

This backplane doesn’t just route high-speed PCIe data lanes; it features hardwired, dedicated hardware lines for precision triggering and 10 MHz/100 MHz reference clocks. By baking synchronization directly into the physical backplane copper, engineers can synchronize multiple instrument cards—such as digitizers and RF signal generators—with absolute precision, dropping timing skew down to the picosecond level.

Specialty and high-frequency sync

When you are pushing the boundaries of high-speed measurement, a fast data interface like USB or Ethernet simply isn’t enough; the inherent software latencies are far too unpredictable. For true phase alignment and precise event matching, you need physical, hardware-level timing synchronization. This is where dedicated coaxial connections on the back panel come into play, stripping away communication protocols in favor of raw, speed-of-light electrical pulses.

The most common tool for this job is the ubiquitous BNC (Trigger In/Out) connector—the classic, 50-Ω “push and twist” interface found on almost every piece of serious bench gear. These ports carry simple TTL voltage steps to command multiple instruments to start capturing data at the exact same microsecond, eliminating any jitter caused by PC software.

Right alongside the trigger ports, you will almost always find the 10-MHz reference In/Out BNC ports. These are used to completely override an instrument’s internal crystal oscillator. By daisy-chaining these reference lines, you can “lock” the internal timebases of every instrument on your bench to a single master clock—whether that is a high-end oscilloscope or an ultra-stable external rubidium or GPS disciplined clock—ensuring your entire test system drifts as one.

Here is a side note on why 10 MHz. Ten megahertz (10 MHz) became the universal reference frequency because it strikes the right balance between practicality and precision. It’s low enough to distribute cleanly over coaxial cables without distortion, yet high enough to be multiplied or divided into the ranges needed for synthesizers and RF systems.

Its adoption was reinforced by national time services, rubidium and cesium atomic clocks, and GPS-disciplined oscillators, all of which commonly output 10 MHz. As a result, nearly every serious instrument supports it, making 10 MHz the common language for locking multiple devices to a single master clock.

Engineering trade-off: Speed, distance, and ruggedness

Ultimately, choosing the right hardware interface is an exercise in balancing speed, distance, and ruggedness against the specific needs of your test setup. If you are building a permanent, high-throughput automated rack that requires absolute clock synchronization, scaling up to PXIe or building out an LXI-compliant Ethernet network is the gold standard.

Conversely, if you are just pulling a quick measurement at your desk or running a temporary validation test, the simplicity of USB remains king. There is no single “best” interface—only the right tool for the specific measurement topology at hand.

Navigating the “hidden” hardware premium

As you map out your test system, it’s worth keeping an eye on the budget for the often-overlooked physical layer accessories. While it’s easy to assume that hooking up an older, high-end GPIB-equipped spectrum analyzer to a modern PC is just a matter of a simple cable change, the “hidden” hardware costs can catch you off guard.

Because GPIB is a complex parallel bus, standard GPIB-to-USB controller adapters from reputable T&M vendors require dedicated, specialized chipsets inside the cable housing. Consequently, these controller cables can easily run anywhere from $500 to over $1,000 each.

Figure 4. NI GPIB-USB-HS interface translates legacy GPIB signals into a USB-compatible format to enable remote instrument control and data logging. Source: National Instruments

Don’t let these price tags discourage you from utilizing legacy gear, though. These rugged adapters are highly reliable, built to last for decades, and frequently retain their value on the secondary market. Alternatively, if you are working on a tighter budget, there are excellent open-source or lower-cost third-party controller alternatives available, ensuring you can still breathe modern life into classic, high-performance bench instruments without breaking the bank.

From bench to bus: Your turn to build

At the end of the day, every piece of iconic technology—from the Mars rovers to the smartphone in your pocket—started as a cluster of instruments connected to a test bench. Whether you are a seasoned automation engineer managing a massive PXIe chassis rack, or a curious maker setting up your very first USB oscilloscope at a home workbench, the interfaces you choose are the quiet enablers that bring your designs to life.

Don’t let the complex acronyms or the price tags of high-end adapters intimidate you; the fundamentals of data, grounding, and synchronization remain exactly the same. So, here is our challenge to you: look at the back panel of your gear, grab a cable, and push your bench a little further this week.

If you are a novice, try writing a basic script to pull a single voltage reading over USB. If you are a veteran, see if you can optimize your automated test cycle times by swapping a legacy serial link for LXI Ethernet. Every great piece of hardware engineering is built on the back of rigorous measurement. Go wire up your bench, automate your data, and show us what you are building.

What does your current test setup look like? Are you still rocking legacy GPIB gear via adapters, or have you fully migrated to an Ethernet-driven LXI bench? Drop a comment below and share your worst ground-loop horror stories or your slickest automated test setups!

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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• Why you should use LXI instruments in your next T&M system
• The USB takeover: Why modern T&M is moving to your pocket

The post Measurement basics: A field guide to instrument interfaces appeared first on EDN.

Oscilloscopes utilize both hardware and software tools to enhance the resolution of time measurements. Happily, most of the processing is transparent.

The primary display from an oscilloscope is amplitude versus time. Most of the focus when using oscilloscopes is on the vertical axis, including amplitude resolution, analog bandwidth, and vertical accuracy. The time axis does not seem to get equal billing. That’s because oscilloscope time bases are very good.

Timebase accuracy

The oscilloscope’s timebase generates the sampling clock, which samples the input signal at uniform time intervals at the sampling rate. The sampling rate and the length of the acquisition memory determine the horizontal scale factor. The timebase clock of an oscilloscope has a frequency accuracy generally specified in parts per million (ppm) or parts per billion (ppb).

For example, an instrument with a timebase specified as accurate to within ± 0.1 ppm (100 ppb). This means that any time interval, T, being measured is accurate to within ± 0.1/106 of the value of T. If the measured interval is one second, the uncertainty of the measurement is ±1×10-7 seconds or ±0.1 microseconds (ms).

Clock oscillators are subject to frequency drift over time. This timing uncertainty is cumulative and increases as the oscillator operates over longer periods. That drift, called aging, is usually specified as an additive uncertainty in frequency, expressed in parts per million per year (ppm/yr). A typical clock timebase accuracy specification might be ±0.1 ppm + 0.05 ppm/year. The time is measured from the instrument’s last calibration.

If the oscilloscope’s internal timebase is not as accurate as desired or if the oscilloscope’s operation must be synchronized with other instruments, many oscilloscopes include an external clock reference input. The external reference is usually generated from a very stable signal source at either 10 or 100 Megahertz (MHz), which is used to synchronize the internal timebase to the reference input to improve its accuracy.

Improving time resolution

The time resolution of a digitizing instrument, based only on the sampling clock frequency, would be the reciprocal of the sampling rate. An oscilloscope that samples at 40 gigasamples per second (GS/s) would have a time resolution of 25 picoseconds.

Oscilloscopes enhance hardware time resolution by using a specialized frequency counter called a time-to-digital converter (TDC). In real-time acquisition mode, the time-to-digital converter measures the time between the trigger event and the next sample.

In general, the trigger event and the sample clock are not synchronous. The time delay between these two events is uniformly distributed over the sampling period. The uniform distribution means that any time delay between zero and the sampling period is equally possible. The time delay for each acquisition is called the horizontal offset and is a characteristic of the acquired waveform. Figure 1 shows a horizontal offset measurement.

Figure 1 A typical measurement of the horizontal offset of an acquisition measuring time between the trigger point and the next sample point.

The figure shows an acquired waveform. The bright dots on the waveform indicate the real samples.

Horizontal relative cursors provide a visual measurement of the time between the trigger point and the next following sample and display the Δx value of 12.5 ps in the cursor readout field in the lower right corner. The TDC output provides an exact digital readout internally.

The time resolution of the TDC is much finer than the sample rate. In this specific example, it is five ps. The horizontal offset is used to align waveform samples for display and measurements. It is also used to combine multiple acquisitions of a periodic waveform into a random interleaved sampling acquisition.

Random interleaved sampling

Random interleaved sampling (RIS) is an acquisition mode that enhances the instrument’s time resolution when measuring multiple periodic waveforms with a stable trigger point. The oscilloscope acquires multiple waveforms, each with the same shape (Figure 2).

Figure 2 The horizontal offset, time delay between the trigger and the next sample, is uniformly distributed over the sampling period; multiple acquisitions show this variation.

Each acquired waveform has a horizontal offset uniformly distributed over the sampling period. Multiple acquired waveforms will each have a different horizontal offset. Examining the time difference between the trigger point and the first sample that follows in the figure illustrates this variation. Overlaying the twelve waveforms shows how they synthesize a waveform with an effectively higher sample rate (Figure 3).

Figure 3 Creating a composite waveform from multiple acquisition results in a higher effective sample rate.

The oscilloscope measures the horizontal offset of each waveform and categorizes them to select those whose values are multiples of the desired effective sampling rate. These selected waveforms are combined to form the RIS waveform (Figure 4).

Figure 4 This graph compares a real-time and RIS waveform.

The lower waveform in the figure is the real-time acquisition. Cursors mark a 25 ps sampling period of the real-time waveform.  The upper trace is the RIS acquisition. Note that there are five effective sample periods between the cursors; the effective sample rate is five times the 40 GS/s sample rate, or 200 GS/s. Remember that the RIS acquisition mode requires multiple repetitive acquisitions with the identical waveform using a stable trigger point.

Sequence mode

Sequence mode is another acquisition mode that uses the TDC. This mode is used to minimize the dead time between adjacent acquisitions. It is also applied to reduce the time between acquisitions. Sequence mode breaks the acquisition memory into a user-defined number of segments. Each segment holds a single acquisition. Since the oscilloscope does not need to display the trace between segments, the dead time between acquisitions is minimized.

The downside of this mode is that the time between segments is indeterminate as the instrument waits for the next acquisition trigger. To counter this, the oscilloscope marks the location, in time, of each segment in two ways.

First, it labels the start of each segment using the oscilloscope’s real-time clock to label each trigger time. The real-time clock has a resolution of one second, which is not practical for fast acquisitions. It also uses the TDC to measure the time delay of each trigger from the first trigger in the acquisition (Figure 5).

Figure 5 A sequence mode acquisition of five ultrasound pulsed bursts showing the sequence mode time stamps.

The figure shows a sequence-mode acquisition of five ultrasonic pulse bursts, each in its own segment. The sequence mode time stamps appear under the graphic display, including the absolute time from the oscilloscope’s real-time clock in the column labeled time. Additionally, it lists the time from the start of the first segment and the time between segments. These TDC-measured times are displayed with a resolution of one nanosecond.

The time stamps indicate the timing of the trigger events. It basically places each segment at a specific time. If each trigger event is an anomaly, then the time stamps provide the frequency of the anomalies, a bit of diagnostic information that often proves useful.

Interpolation

If the TDC is the hardware tool for precise time measurements, then interpolation is the software tool. Interpolation is a mathematical technique for increasing the effective sample rate of an acquired signal. Interpolation calculates intermediate sample values between the real-time samples. Interpolation is usually applied to the displayed data, but in many cases, it is incorporated into application-specific measurements.

Interpolation is also available as a math function and can be used to increase the time resolution of acquired waveforms. The oscilloscope used in this article offers sin x/x, linear, or cubic interpolation with sampling rate improvement from two to fifty calculated points per real-time sample.  Interpolation increases instrument processing time proportional to the number of interpolated samples.

On the positive side, interpolation can be applied to single-shot acquisitions. On the downside, interpolation requires that the data meet the Nyquist criteria and have a sample rate greater than twice the signal’s bandwidth. Failure to satisfy Nyquist can result in significant errors. From a data integrity perspective, it is essential to note that RIS data comprises all real samples, whereas interpolated data is a combination of real and calculated sample values.

Jitter measurements

Jitter is a short-term variation in the timing of a digital signal from its nominal value. Any timing parameter can be the subject of jitter analysis, and the main timing parameters considered are variations in width, period, and time-interval error (Figure 6).

Figure 6 This graphic gives examples of timing uncertainty in width, period, and time interval error jitter, including jitter measurements along with the histogram of time interval error.

Width or period jitter can be measured using the width and period measurement parameters, respectively. The jitter is evident in the statistical readouts for minimum (min), maximum (max), and standard deviation (sdev). The difference between the maximum and minimum is the range or peak-to-peak jitter. The standard deviation is the root-mean-square (RMS) jitter.

Time interval error (TIE) measures the difference between each actual waveform edge and the ideal location of that edge. The ideal edge locations are computed from the waveform’s mean frequency.  TIE can be thought of as the instantaneous phase of the signal.

 The time parameters period, width, and TIE are measured by determining the time between edges. For a period, it is the time between adjacent edges with the same slope. For the width measurement, it is the time between adjacent edges with different slopes. TIE measures the time between an acquired edge and an ideal edge. The measurement uses interpolation to achieve the highest possible time resolution (Figure 7).

Figure 7 A dual interpolator finds use in obtaining a more precise measurement time resolution.

The figure shows an edge defined by three real-time samples taken with a 10 GS/s sampling rate. The interpolator uses a cubic interpolation to fit several interpolated samples between each real-time sample. Then, the two samples that bracket the measurement threshold are used to perform linear interpolation to determine the time at which the measurement threshold is crossed. The resulting measurements in this example have a resolution better than 1 picosecond.

Jitter has both random and deterministic components.  Random jitter is associated with stochastic processes, such as noise, and is unbounded, meaning it increases with increasing observation time. Deterministic jitter is bounded, and its amplitude is limited with increasing observation time. The random components of jitter are studied using statistical tools, such as histograms.

Figure 6 shows the histogram of the TIE parameter. There are parameters intended to interpret histograms themselves. The histogram mean (hmean), mode (hmode), standard deviation (hsdev), and range (hrange) are examples of histogram-specific parameters.

Conclusion

Oscilloscopes utilize both hardware and software tools to enhance the resolution of time measurements. Improved time resolution is used both in displaying the data and in measurements. Happily, most of the processing is transparent and requires little user interaction to achieve good results.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

Related Content

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• Basic oscilloscope operation
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• Oscilloscope special acquisition modes
• How to perform histogram analysis on your oscilloscope
• Basic jitter measurements using an oscilloscope
• Closing the gaps in your digital oscilloscope waveforms

The post Secrets of oscilloscope time measurements appeared first on EDN.

Odorless. Colorless. Tasteless. But certainly not harmless. Radon, in both air and ground water, is a health risk whose prevalence should be regularly assessed and, if necessary, dealt with.

Beginning last fall and continuing through early summer, my community built an emergency access road that links up with a state highway below us and provides an alternate escape path in case of fire or other calamity, a particularly appealing option for those (like me) whose homes are at the far end of the community.

Road construction involved, among other things, the use of dynamite to blast pathways through rocky hillsides. And shortly after road completion, I learned that a residence a few minutes’ walk away from us had tested positive for high radon levels and was in the process of installing a mitigation setup.

Were the two events—earth disturbance due to road construction and radon release—related? I don’t know, and I’m not forward enough to ask the neighbors, but it’s possible. Regardless, even though our home had successfully passed a radon test done as part of the pre-purchase inspection more than a decade ago, I was motivated to learn more about radon and then re-test the premises for myself to see if the situation had subsequently evolved in an adverse direction.

Uranium and radium decay

As usual, I began my education with a visit to Wikipedi’s radon entry.

Radon is a chemical element; it has symbol Rn and atomic number 86. It is a radioactive noble gas and is colorless and odorless. Of the three naturally occurring radon isotopes, only 222Rn has a sufficiently long half-life (3.825 days) for it to be released from the soil and rock where it is generated. Radon isotopes are the immediate decay products of radium isotopes.

Here’s more.

A common source of environmental radon is uranium-containing minerals in the ground. Radon can also occur in ground water, such as spring waters and hot springs. Radon trapped in permafrost may be released by climate-change-induced thawing of permafrosts, and radon may also be released into groundwater and the atmosphere following seismic events leading to earthquakes, which has led to its investigation in the field of earthquake prediction.

Seismic events leading to earthquakes…and possibly also dynamite blasts? Here’s where the prose turned worrisome.

Epidemiological studies have shown a clear association between breathing high concentrations of radon and incidence of lung cancer. Radon is a contaminant that affects indoor air quality worldwide. Because radon is denser than air it accumulates in basements and crawlspaces under dwellings. According to the United States Environmental Protection Agency (EPA), radon is the second most frequent cause of lung cancer, after cigarette smoking, causing 21,000 lung cancer deaths per year in the United States. About 2,900 of these deaths occur among people who have never smoked. While radon is the second most frequent cause of lung cancer, it is the number one cause among non-smokers, according to EPA policy-oriented estimates.

And finally, there’s this from the related Wikipedia entry for radon mitigation.

There is no proven link between radon in water and gastrointestinal cancers; however, extremely high radon concentrations in water can be aerosolized by faucets and shower heads and contribute to high indoor radon levels in the air.

Yikes!

Radeon prevalence varies across the United States and, more broadly, the world at large. It turns out that Denver, Colorado and surrounding regions have among the highest U.S. concentrations, as the following two related graphics show. The first documents the predicted fraction of U.S. homes having concentrations of radon exceeding the EPA’s recommended action level of 4 pCi/L. Note the orange region smack dab in the middle of Colorado, right where my residence is located.

And then there’s this one, which formats the data slightly differently, but ends up with the same essential outcome.

The most concise and clarifying data I came across related to my specific situation comes from an informative page (and a highly recommended read, even if you’re not a neighbor of mine) on the Jefferson County website.

Approximately 50% of homes in Jefferson County test above the EPA action level for radon every year.

It’s followed by this.

Radon is found throughout the U.S. and is particularly prevalent in Colorado. The U.S. Environmental Protection Agency (EPA) has ranked Colorado as a Zone 1 area, meaning the average house will exceed the EPA’s action level for indoor radon.

Once again: yikes! I guess that’s why I see mitigation setups (more on them later) like this one all over the community.

Testing scenarios and equipment options

The Jefferson County webpage on radon also includes these non-scientist explanation statements that I thought were enlightening.

Radon is an invisible, odorless, tasteless, cancer-causing gas that comes from the natural radioactive breakdown of uranium and radium in soil, rock and water. Radon enters buildings through cracks, holes and pipes in the foundation. All buildings contain some radon, but homes are the most concerning since that is where families spend most of their time.

There’s also this.

Radon is produced as a decay product from uranium and radium. This naturally occurring radioactive gas is found in most soil, rock, and groundwater. Since radon is a gas, the inert element can easily travel through cracks and pores without being chemically bound or attached to other elements. Voids and porous materials are found under every building, allowing radon easy entry.

Perhaps obviously, once again quoting from the Jefferson County website, “the test kit should be placed in the lowest occupied level (typically a basement) and in the normal breathing zone (about 2-6 ft. from the floor) and 3 ft. from windows, doors, vents, or anything that allows airflow.”

Preferably, in fact, windows, doors (especially screened) and other outside-air ventilation sources should be shut as much as possible through the entire multi-day testing cycle to minimize gas dilution and maximize negative pressure (aka, “stack effect”) flow into the home, thereby simulating the worst-case radon accumulation that would normally occur in winter and other closed-off times (that said, air conditioning systems are another common catalyst for high radon gas leakage into buildings).

Free radon test kits are available to me from both Jefferson County and the Colorado Department of Public Health and Environment and can also be bought from local hardware and home improvement stores and online retailers. Keep in mind, however, that the kit still needs to be sent in for post-test analysis, with results subsequently sent back to the submitter, all steps incurring delays.

Yet another gizmo-acquisition opportunity

Instead, especially since I’m a techie who can’t resist new toys, I decided to buy my own radon detector hardware. The Airthings Corentium Home 2 (stock photos and promo video follow) normally costs around $180, but I found one promotion-priced on the Resale (formerly Warehouse) area of Amazon’s website for $121.46.

Versus its first-generation predecessor, it supplements the integrated display with Bluetooth LE and SmartLink (Airthings’ proprietary wireless protocol) connectivity to a separate device.

And battery life extends from 1.5-2 years (3 AAA alkaline batteries) with the original Correntium to 2-3 years (two AA alkaline batteries).

Here’s my own unit, starting with outer packaging shots.

Now open, with the contents accompanied by a 0.75′′ (19.1 mm) diameter U.S. penny for size comparison purposes.

Inside, of course, is the Corentium Home 2, along with some literature (also found online here) and a silica gel packet.

Here’s the open backside; batteries are included, with only a thin slip of plastic needing to be removed to complete the connection. Activate them as the power source and start testing.

Mating and initial setup of the device with my smartphone—which subsequently receives periodic notifications from it—was uneventful.

And, after a preparatory 24-hour delay over which the device collected and averaged (but did not yet share with me) its initial data set, preliminary results were encouraging.

I kept the measurements going for nearly three weeks before capturing another screenshot set, and the good news thankfully kept coming.

The application (Android in my case, but iOS also available) displays trend graphs, too, useful to see how radon levels, along with also-measured humidity and temperature, varied over time.

Mitigation methodology

All well and good, though I plan to continue conducting going-forward measurements, since radon gas levels vary over time due to a variety of factors. But what if my results had been more concerning? Step one is to seal off as much as possible any soil-sourced radon gas leakage coming into the house through slab and foundation cracks; more substantial slab voids resulting from floor drains and sump pumps are also potential culprits, albeit harder-to-eliminate ones.

Next, strive to minimize negative pressure (stack effect) situations, where the inside-house air pressure is lower than that of the outside, generating a partial vacuum condition that pulls air in from below the residence in attempting to equalize the differential. Frequent, vigorous use of HVAC systems is a potential root cause of pressure imbalances, along with attic fans, bathroom and kitchen-cooking-appliance exhausts, and the like. Keeping windows and screen doors open whenever weather and broader seasonal temperatures afford this option, as earlier mentioned, is helpful albeit only as temporary workarounds.

The most significant mitigation measure, and one that per my earlier shared photo I see frequently around my community, involves the installation of an active soil depressurization system. A PVC pipe originating below the home’s foundation, commonly in combination with a continuously running inline fan, draws radon gas out and up to the roof where it’s safely exhausted, completely bypassing the residence interior (and its inhabitants) in the process.

A tutorial video I found online showcases an in-home mitigation system installation.

I found it interesting for two main reasons, among others:

• The system’s location: I’d previously only been familiar with exterior-visible setups such as the one in the earlier-shown photo. I now wonder how many more homes in my community have implemented radon mitigation, internally (and therefore invisible to me from the outside) in these latter cases.
• And the initial, albeit unsuccessful, attempt to rely solely on a passive system, later supplemented by an active fan to create sufficient incremental suction.

I’ll wrap up here and turn it over to you for narration of your radon-related experiences and broader thoughts in the comments. Thanks as always in advance for them!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Radon: Level detection, risk determination, and as-needed mitigation appeared first on EDN.

The Controller Area Network (CAN) extended data-field length (XL) specification—which has been standardized for years—now has the first commercially available CAN XL transceiver. Texas Instruments has unveiled the TCAN6062 CAN XL transceiver, which supports payloads of up to 2,048 bytes per frame and data rates up to 20 Mbps.

The CAN XL transceiver ensures that priority messages are delivered first and on time, facilitating performance critical to humanoid robots, industrial robots, and human-machine interface (HMI) systems. This allows system designers to leverage CAN XL to exchange data rapidly and reliably in applications ranging from industrial robotics to automotive safety.

Figure 1 The CAN XL technology is promising to open the door to a new era of applications. Source: Texas Instruments

The new CAN XL transceiver is also backward compatible with CAN flexible data rate (FD) and CAN signal improvement capability (SIC) operations. This ensures a seamless migration and enables design teams to evolve existing designs incrementally without requiring a full redesign.

Next, while CAN XL is better and cheaper than CAN FD, it can also tunnel Ethernet. So, the CAN XL transceiver allows engineers to consolidate communication layers and use Ethernet in mixed-network architectures with Transmission Control Protocol/Internet Protocol (TCP/IP) tunneling. That facilitates efficient transfers of diagnostics, sensor data, control traffic, and over-the-air (OTA) updates on a single network.

Figure 2 The TCAN6062 CAN XL transceiver helps reduce ringing by up to 80% in complex networks, simplifying validation in high-node architectures. Source: Texas Instruments

CAN has been the backbone of industrial communications for decades. However, industrial systems are now generating and demanding more data than ever before. That’s because applications require fast, deterministic communication to synchronize motion control, sensor feedback, and diagnostic data. That, in turn, leads to new networking requirements, and as a result, engineers often accept system-level trade-offs to compensate for bandwidth constraints.

Dwight Byrd, GM of Interface Products at TI, claims that the TCAN6062 CAN XL transceiver bridges that gap. “It offers engineers a path to higher-bandwidth networks while maintaining the proven reliability CAN is known for.”

“As industrial systems become more intelligent and interconnected, what we ask of our networks continues to evolve,” Byrd added. “Engineers need more data, higher speeds, and greater flexibility, all without compromising performance or reliability.

TI’s networking technology managers are confident that CAN XL will open the door to a new era of applications, enabling systems to deliver higher performance at a reasonable cost. And here, TI has the first-mover advantage.

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The post TI a first mover in CAN XL transceivers appeared first on EDN.

AI-driven demand underpins logic foundry and memory fab capacity constraints, leading to cost increases. Add tariffs to the mix, and Google and its competitors (not to mention end users) pay the price.

Last year’s Made By Google fall product launch event happened midday on August 20, moderated by Jimmy Fallon. Although I found value in the devices, software and services Google unveiled there, the un-traditional Tonight Show-styled format wasn’t particularly to my liking, a negative opinion shared by a notable number of others whose coverage I subsequently perused.

This year’s event, earlier today (August 12) as I write this, was once again celebrity-moderated, this time by Trevor Noah. But this time it took place in the evening, with the announcements notably preceding it; a flurry of blog posts had already hit Google’s website at 8 am MT, where I am. Feel free to draw your own conclusions as to the judged effectiveness (or, perhaps more accurate, lack thereof) of last year’s event And begging the question of why Google bothered doing this year’s event at all, save I suppose for the chance to see “live” demos, “softball” interviews and other such questionable-value content.

That said, the products themselves once again were notable, both in an absolute sense and relative to their prior-generation predecessors.

Befitting my engineering-dominated readership, I’ll as usual start out my coverage with the application processor, the Tensor G6, the intelligence nexus of the Pixel 11 smartphone series.

Power/performance balance (and profit) optimization

When I published last year’s event coverage, little was known at the time about the latest-generation Tensor G5 SoC save for its 3 nm TSMC fabrication source (a notable departure from Google’s longstanding foundry partnership with Samsung) and its eight-core CPU cluster mix: “one “prime” core, five mid-level ones, and two efficiency ones.” Beyond that, all Google was saying at the time was that, versus its Tensor G4 predecessor, it delivered the following updates.

• An up to 60% more powerful TPU
• A 34% faster on average CPU, and
• New security hardware

One year later, thanks to intensive developer engagement with the platform, we know much more about the Tensor G5 than we did before.

• CPU (8 total cores): 1x Arm Cortex-X4 at 3.78 GHz, 5x Arm Cortex-A725 at 3.05 GHz, 2x Arm Cortex-A520 at 2.25 GHz
• GPU: Imagination Technologies PowerVR (DXT-48-1536)

And now on “Day Zero” of the Tensor G6 era, what’s Google saying about it? Predictably, not much beyond another year’s worth of nebulous hand waving in comparison to the Tensor G5:

Tensor G6 features an upgraded CPU for 25% faster web browsing and 15% quicker app launches. Packing 50% more TPU compute and paired with the latest Gemini Nano model, Google Tensor G6 processes on-device AI tasks up to 3.5 times faster while using up to 3.5 times less energy.

But thanks to a leak sourced from embargoed media hands-on time with the Pixel 11 family, the following additional (and more specific) Tensor G6 specs, referencing Arm’s C-series cores, are also presumably accurate.

The Tensor G6 sports a seven-core configuration, with one prime “C1 Ultra” core clocked at 4.1GHz, four performance “C1 Pro” cores clocked at 3.4GHz, and two efficiency “C1 Pro” cores clocked at 2.65GHz. The GPU appears to be a PowerVR C-series variant with six compute units clocked at 1.3GHz.

One other silicon-related nuance also bears mention. Although, as previously mentioned, Google switched from Samsung to TSMC as its foundry source for the Tensor G5 last year, it stuck with Samsung’s Exynos cellular subsystem. This year, reportedly (although I haven’t yet seen definitive confirmation), this too has changed; Google’s supposedly now leveraging MediaTek M90 5G cellular IP.

Smartphone evolutionary modesty

Aside from the new colorways, you’d understandably likely be hard-pressed to discern a visual difference between Google’s latest handsets—the baseline Pixel 11, high-end Pixel 11 Pro and Pro XL, and book-style Pixel 11 Fold—and their 10th generation predecessors. Backs are once again all-glass. Displays are a bit brighter, and more scratch-resistant in the “Pro” variants. Camera bars are a bit more svelte (along with overall Fold thinness), and for “Pro” versions, embed a multicolor notification LED assembly surrounding the flash and branded “HiLight”. Particularly clever readers may have already noted the enhanced scratch-resistance association, since the notifications can only be seen when the phone is screen-down on a flat surface.

That all said, to the overall “supply constraints” theme of this writeup, I’ll point out that the Pixel 11 storage options now start at 256 GBytes; the entry-level 128 GByte variant of the Pixel 10 that I recently acquired isn’t offered this time around. In Google’s defense, Apple did the same thing a year ago with the iPhone 17 versus its iPhone 16 precursor, although in that earlier case the 2x capacity multiplier came for the same intro price as the 128 GByte prior-gen device.

This time the 256 GByte Pixel 11 price thankfully at least matches that of the year-ago 256 GByte Pixel 10, versus with an accompanying price increase as other smartphone suppliers are doing nowadays. Further to Google’s defense, note that a year ago any bill-of-materials cost increases were predominantly due to tariff impacts. Now, in contrast, supply constraints are additionally being felt to fuller effect. It’ll be curious to see how Apple handles both memory and TSMC foundry cost increases at its likely next-month announcement event; for one thing, the company will reportedly delay the launch of its baseline iPhone 18 until sometime next year.

In closing, at least for this section, one more memory-related twist bears mention. A year ago, I wrote, “Google also didn’t “hide” tariff costs by cutting RAM capacities (which would counterbalance its burgeoning AI ambitions, anyway)”. Well, this year they did. The lowest (256 GByte) storage capacity variants of the Pixel 11 Pro and Pro XL also have less RAM—12 GBytes vs 16 GBytes—than both their higher-capacity this-year siblings and same-capacity Pixel 10 predecessors, in the latter case with no accompanying generational price break. Admittedly, Google’s working hard on optimizing memory requirements for its on-device models, but still…

Watches and trackers

Last year’s Pixel Watch 4 was a notable update to its predecessor(s), as I wrote about at the time (although I’m still fiscally quite content with a recent update from my long-in-the-tooth first-generation wearable to “only” the Pixel Watch 3, more discussion of which I’ll save for another post another day). This year’s Pixel Watch 5 advancements are also more modest, notably including slight (~12%) CPU performance and battery capacity upticks along with an on-device AI-intended RAM upgrade from 2 GBytes to 3 GBytes, the latter leading to—you guessed it—an associated $50 price tag increment.

I’m not entirely sure why Google included a set of earbuds in its launch suite promo photo shown earlier this piece, as aside from a new Pixel Buds 2 (two years old) colorway option and pending firmware-delivered feature updates to both them and the Pixel Buds 2a (introduced a year ago), nothing’s new. Conversely, the most brand-new device released this week was the Pixel Tag, unsurprisingly supportive of Google’s Find My Device network and conceptually similar to (and a competitor of) Apple’s also-UWB-enhanced second-generation AirTag.

Hopefully, this wireless-connectivity enhancement suggests that we’ll be seeing broader support for UWB in both Google’s and other Android licensees’ handsets in the future. My biggest surprise here is that, unlike Motorola and other tracker manufacturers, Google didn’t also adopt an AirTag-clone form factor that would enable it to slot into the already sizeable and still steadily expanding AirTag ecosystem of luggage tags, stealth security setups and the like.

That’s what I’ve got for you today, folks. As always, please sound off with your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• Google I/O 2026: Agentic AI gets serious
• Google’s Pixel 10: Upgrading smartphones again

The post Made by Google 2026: This limited silicon-supply situation really sucks appeared first on EDN.

NoMIS Power has developed a 6.5-kV large-die SiC MOSFET that has demonstrated over 8 kV of blocking voltage, 90-mΩ on-resistance, and 55-A drain current. Based on the planar SiC technology used in its 3.3-kV devices, the 6.5-kV MOSFET extends the technology into the high-voltage class and provides a foundation for the company’s planned 10-kV MOSFETs and 20-kV SiC IGBTs.

NoMIS is sampling the 6.5-kV SiC MOSFET to U.S.-based customers, with standard-production devices scheduled for Q4 2026. The company plans to expand the 6.5-kV portfolio with additional on-resistance variants, small-die MOSFETs, hybrid junction-barrier Schottky FETs (JBSFETs), and standalone diodes for applications including HVDC power transmission, solid-state transformers, pulsed-power systems, rail traction, and megawatt-scale EV charging

The 6.5-kV devices build on the company’s 3.3-kV SiC MOSFET family, which is already in production, while 10-kV and higher-voltage MOSFETs, diodes, JBSFETs, and SiC IGBTs are in development.

For more information, visit the NoMIS Power Semiconductors and Modules webpage.

NoMIS Power

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NEO.AI is a memory platform from NEO Semiconductor that overcomes SRAM and DRAM scaling limitations in AI memory systems. As part of the platform launch, NEO Semiconductor is introducing its X-SRAM technology for on-chip memory in GPUs and AI processors and reporting its latest progress on 3D X-DRAM, a high-capacity memory technology for HBM.

By replacing conventional six-transistor SRAM with a two-transistor architecture, X-SRAM enables up to 5 times higher memory density to support 1–2 GB of on-chip memory, according to NEO. The technology maintains SRAM-class performance and is compatible with advanced nanosheet CMOS processes. It also provides a path toward future monolithic 3D X-SRAM implementations.

Built on 3D NAND manufacturing processes, 3D X-DRAM delivers up to 10 times higher memory capacity than conventional DRAM, according to NEO. Successful proof-of-concept validation demonstrates its potential as a scalable and manufacturable solution for next-generation HBM.

For more information, visit the NEO X-SRAM webpage.

NEO Semiconductor 

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The KTS1630 5-A eFuse from Kinetic Technologies protects sensitive electronics against overcurrent, short circuits, and thermal faults. It is designed for consumer and industrial systems operating from 5-V and 12-V power rails, helping improve system safety and reliability. By detecting overcurrent conditions typically within 100 ns, the device can isolate faults before they can damage downstream circuitry.

An integrated MOSFET with a typical on-resistance of 31 mΩ from VIN to VOUT helps reduce conduction losses while supporting operation across a 4.5-V to 18-V input range, with a 20-V absolute maximum rating at VIN. The KTS1630’s adjustable 1-A to 5-A current limit allows designers to set the protection threshold for specific loads rather than relying on a fixed current-limit threshold. The eFuse also includes a dedicated control output for an external reverse-blocking MOSFET that prevents reverse current when the input supply is removed or the output voltage exceeds VIN.

A programmable output slew rate controls inrush current during startup, helping prevent input-supply droop, connector stress, and unintended system resets when large capacitive loads are connected.

Supplied in 10-pin, 3×3-mm VDFN packages, the eFuse is available in both auto-retry and latched-off versions.

KTS1630 product page 

Kinetic Technologies  

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