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Parsing PWM (DAC) performance: Part 3—PWM Analog Filters

Птн, 03/01/2024 - 18:27

Editor’s Note: This is a four-part series of DIs proposing improvements in the performance of a “traditional” PWM—one whose output is a duty cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to produce a DAC. The first part suggests mitigations and eliminations of common PWM error types. The second discloses circuits driven from various Vsupply voltages to power rail-rail op amps and enable their output swings to include ground and Vsupply. This third part pursues the optimization of post-PWM analog filters.

 Part 1 can be found here.

 Part 2 can be found here.

Recently, there has been a spate of design ideas (DIs) published (see Related Content) which deals with microprocessor-generated pulse width modulators driving low-pass filters to produce DACs. Approaches have been introduced which address ripple attenuation, settling time minimization, limitations in accuracy, and enable outputs to reach and include ground and supply rails. This is the third in a series of DIs proposing improvements in overall PWM-based DAC performance. Each of the series’ recommendations are implementable independently of the others. This DI addresses low pass analog filters.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The PWM output

Spectrally, the PWM output consists of a desirable DC (average) portion and the remainder—undesirable AC signals. With a period of T, these signals consist of energy at frequencies n/T, where n = 1, 2, 3, etc., that is, harmonics of 1/T. If the PWM switches between 0 and 1, for every harmonic n there exists a duty cycle corresponding to a peak signal level of (2/π)/n. This shows the futility of an attenuation scheme which focuses on a notch or band reject type of filter—there will always be a significant amount of energy that is not attenuated by such. The highest amplitude harmonic is the first, n = 1. At the very least, this harmonic must be attenuated to an acceptable level, α. Any low pass filter that accomplishes this will apply even more attenuation to the remaining harmonics which are already lower in level than the first. In summary, the search for the best filter will focus on what are called all-pole low pass filters, which is another way of saying low pass filters which lack notch and band-reject features.

The skinny on low pass all-pole filters

Analog filters can be defined as a ratio of two polynomials in the complex (real plus imaginary) variable s:

Where I ≤ K. The terms zi and pi are referred to respectively as the zeroes and the poles of the filter. K is the order (first, second, etc.) of the filter as well as the number of its poles. All-pole filters of unity gain at DC can be specified simply as:

Filter types include Butterworth, Bessel, Chebyshev, and others. These make different trade-offs between the aggressiveness of attenuation with increasing stop-band frequency and the rapidity of settling in response to a time domain impulse, step, or other disturbance. Improving one of these generally denigrates the other. Tables of poles for various orders and types of these filters can be found in the reference [1]. Values given are for filters which at approximately 1 radian per second (2π Hz) exhibit 3 dB of attenuation with respect to the level at DC. This point is considered to be the transition between the low frequency pass and high frequency stop bands. Multiplying all poles by a frequency scaling factor (FSF) will cause the filter to attenuate 3 dB at 2π·FSF Hz. The frequency response of a filter can be calculated by substituting j·2π·f for s in H(s) and taking the magnitude of the sum of the real and imaginary parts. Here, j = √-1 and f is the frequency in Hz.

The time domain response of a filter to a change in PWM duty cycle reveals how quickly it will settle to the new duty cycle average. For a filter of unity gain at DC, this involves subtracting from 1 the inverse Laplace transform of H(s)/s. A discussion of Laplace transforms, their inverses, and practical uses is beyond the scope of this DI. These inverse transforms can, however, be readily determined by using a web-based tool [2].

Requirements of an optimal filter

A filter must attenuate the maximum value over all duty cycles (2/π) of the PWM first harmonic by a factor of α. A b-bit PWM has a resolution of Full-Scale·2-b. So, for the first harmonic peak to be no greater than ½ LSB, α should be set to (π/2)·2-(b+1). Asking for more attenuation would slow the filter response to a step change in duty cycle. From the time domain perspective, the time ts should be minimized for the filter to settle to +/- α · Full Scale in response to a duty cycle change from Full Scale to zero.

Towards an optimal filter

Consider a 12-bit PWM clocked from a 20 MHz source. The frequency of its first harmonic is F0 = 4883 Hz, and its α is 1.917·10-4. 3rd, 5th, and 7th order filters of types Bessel, Linear Phase .05° and .5° Equiripple error, Gaussian 6 dB and 12 dB, Butterworth, and .01 dB Chebyshev are considered. These are roughly in order of increasingly aggressive attenuation with frequency coupled with increasing settling times. Appropriate FSFs are needed to multiply the poles (listed in reference [1]) of each filter to achieve attenuation α at F0 Hz. Excel’s Solver [3] was used to find these factors. The scaled values were divided by 2π to convert them to Hertz and applied to LTspice’s [4] 2ndOrderLowpass filter objects in its Special Functions folder to assemble complete filters. The graph in Figure 1 shows the frequency responses of 24 scaled filters. These include 3rd, 5th, and 7th order versions of the filter types listed above. These filters were named after the mathematicians who developed the math describing them (I have for some reason failed to find any information about Mr. or Ms. Equiripple). Additionally, there are the same three orders of one more filter type that was developed by the author and will be described later. Although the author makes no claims of being a mathematician, for want of an alternative, these have been named Paul filters. (An appalling choice, I’m sure you’ll agree.)

Figure 1 The frequency response of 24 scaled filters including include 3rd, 5th, and 7th order versions of the 7 filter types listed above (Bessel, Linear Phase, Equiripple, Gaussian, Butterworth, Chebyshev and the Paul filter developed by the author) where the value of α is depicted by the horizontal red line.

In Figure 1, the value of α is depicted by the horizontal line. It and all the filter responses intersect at a frequency of F0 (the PWM’s first harmonic) satisfying the frequency response attenuation requirement. Figure 2 is the Bessel filter portion of the LTspice file which generates the above graph. The irregular pentagons are LTspice’s 2ndOrderLowPass objects. The resistors and capacitors implement first order sections. H = 1 is the filter’s gain at DC.

Figure 2 The Bessel filter portion of the LTspice file which generates the response in Figure 1, U1-U6 are LTspice’s 2ndOrderLowPass objects, resistors and capacitors implement first order sections, and H = 1 is the filter’s gain at DC.

By changing the “.ac dec 100 100 10000” command in the file to “.tran 0 .01 0”, replacing the “SINE (0 1) AC 1” voltage source with a pulsed source “PULSE(1 0 0 1u 1u .0099 .01)” and running the simulation, the response of these filters to a duty cycle step from 1 V to 0 V is obtained as shown in Figure 3.

Figure 3 Replacing the AC voltage source with a pulsed source to change the duty cycle step of the filter response from 1 V to 0 V.

Oh, what a lovely mess! The vertical scale is the common log of the absolute value of the response—absolute value because the response oscillates around zero, and log because of the large dynamic range between 1 and α, the latter of which is again shown as a horizontal line.

Which filter’s absolute response settles (reaches and remains less than α) in the shortest period of time? To find the answer to that question, use is made of LTspice’s “Export data as text” feature under the “File” option made available by right-clicking inside the plot. This data is then imported into Excel. Each filter’s data is parsed backwards in time starting from 10 ms. The first instants when the responses exceed α are recorded. These are the times that the filters require to settle to α. (As can be seen, there were some that require more than 10 ms to do so.) For each filter order, it was determined which type had the shortest settling time. Table 1 shows the settling times to ½ LSB for 8-bit through 16-bit PWMs of 3rd, 5th, and 7th orders of filters of various types.

Table 1 Settling times to ½ LSB for 8-bit through 16-bit PWMs of 3rd, 5th, and 7th orders for various types of filters. The fastest settling times are shown in bold red while those that failed to settle within 10 ms are grey and listed as “> 10 ms”.

The entries in each table row with the fastest settling time is shown in bold red. Those which failed to settle within 10 ms are listed as > 10 ms and are greyed-out. In general, the 7th orders settled faster than the 5th orders, which were noticeably faster than the 3rd’s. Also, those with the lower Q sections settled faster than the higher Q alternatives (again, see the tables in reference [1]). The Chebyshev filters with ripples greater than .01 dB (not depicted) for instance, had higher Q’s than all the ones listed above and had hopelessly long settling times.

As a group, the Paul filters settled the fastest, but that does not preclude the selection of another filter in an instance when it settles faster. Still, it’s worth discussing how the Pauls were developed. Starting with the 3rd, 5th, and 7th order frequency-scaled Bessel poles, the Excel Solver evaluated the inverse Laplace transforms of the filters’ functions H(s). It was instructed to vary the pole values while minimizing the maximum value of the filter response after a given time ts. This was made subject to the constraint that the amplitude response of |H(2πj·F0)| be α, where F0 = 20MHz / 212 and α = (π/2)·2-(12+1). If the maximum response exceeded α for a given ts, ts was increased. Otherwise ts was reduced. Several runs of Solver led to the final set of filter poles. It is interesting that even though the optimization was run for a 12-bit PWM only, settling times at other bit lengths between 8 and 16 is still rather good and in most cases superior to those of the other well-known filters. The Paul filter poles and Qs are listed in Table 2.

Table 2 The poles and Qs for 3rd, 5th, and 7th order Paul filter.

Table 3 includes FSFs for the poles of the well-known filters. The unscaled poles are given in the tables of reference [1]. The scaled poles are characteristic of filters which also attenuate a frequency of F0 by a factor of α.

Table 3 The FSFs for the poles of the well-known filters in the tables of reference [1] for the values of α and F0.

 Implementing a filter

A starting point for the implementation of a filter whose poles are taken from a reference table is to apply to those poles an appropriate FSF.  These factors are given for well-known filters in Table 3 for an attenuation, α, at a frequency of F0 Hz. In Table 2, the Paul filter poles have already been scaled as such. For any of these filters, to change the α from a frequency F0 to F1 Hz, the poles should be multiplied by an FSF of F1/F0.

In settling quickly to the small value of α, some of the biggest errors in filter performance are due to component tolerances. To limit these errors, resistors should be metal film, 1% at worst with 0.1% preferred.  Capacitors should be NPO or C0G for temperature and DC voltage stability, 2% at worst and 1% preferred. Smaller value resistors result in a quieter design and lead to smaller offset voltages due to op amp input bias and offset currents. However, these also require larger-valued, bigger, and more expensive capacitors. Keep these restrictions in mind when proceeding with the following steps.

For a first order section with pole ω:

  1. Start by guessing values of R and C such that RC = 1/ω.
  2. Choose a standard value NPO or COG capacitor close to that value of C.
  3. Calculate R’ = 1/(ω·C) where C is that standard value capacitor.
  4. Choose for R the next smaller standard value of R’ and make up the difference with another smaller resistor in series. Although this will not compensate for the components’ 1% and 2% tolerances, it will yield a result which is optimal on average.
  5. Connect one terminal of R to the PWM output and the other to the capacitor C (ground its other side) and to the input of a unity gain op amp. If gain is required in the aggregate filter, it is this op amp which should supply it rather than one which implements a second order section; unlike second order sections, gain in this op amp has no effect on the R-C section’s AC characteristics because there is no feedback to the passive components. The output of this op amp should drive the cascade of remaining second order sections (Figure 4).

Figure 4 Recommended configuration where one terminal of R is connected to the PWM output, and the other is connected to the capacitor C (ground its other side) and to the input of a unity gain op amp.

For second order sections with pole ω and quality factor Q, error sources are again component values. Errors can be exacerbated by the choice of a filter topology. A second order Sallen Key [5] section with the least sensitivity employs an op amp configured for unity gain as shown in Figure 5.

Figure 5 A second order Sallen Key section with the least sensitivity employs an op amp configured for unity gain.

To select component values:

  1. Start by choosing values of R and C such that RC = 1/ω.
  2. Choose standard values of C1 and C2 similar to C such that C1 / C2 is as large as possible, but no larger than 4Q2. Creating a table of all possible capacitor ratios is helpful in selecting the optimal ratio.
  3. Calculate D = (1 – 4Q2·C2/C1)0.5 and W = 2·Q·C2·ω
  4. For R1a, select a standard resistor value slightly less than (1 + D)/W and add R1b in series to make up the difference.
  5. For R2a, select a standard resistor value slightly less than (1 – D)/W and add R2b in series to make up the difference.
  6. If there are more than one second order section, the sections should be connected in order of decreasing values of Q to minimize noise.

A PWM filter example

Consider a 5th order Paul filter with an attenuation of α at a frequency F1 = F0/2. Each of the ω values in the Paul filter table would be multiplied by an FSF of F1/F0 = ½, but the Q’s would be unchanged. The following schematic shown in Figure 6 satisfies these constraints.

Figure 6 A 5th order Paul filter scaled to operate at F0/2 Hertz.

 Designing PWM analog filters

A set of tables listing settling times to within ½ LSB of 8 through 16-bit PWMs of period 204.8 µs (1/4883 = 1/F0 Hz) has been generated for 3rd, 5th, and 7th order versions of eight different filter types. These filters attenuate the peak value of steady state PWM-induced ripple to ½ LSB. From these listings, the filter with the fastest settling time is readily selected. These filters can be adapted to a new PWM period by multiplying their poles by a scaling factor equal the ratio of the old to new periods. New settling times are obtained by dividing the ones in the tables by that same ratio.

Pole scaling factors for the operation of well-known filters at F0 are supplied in a separate table. The poles of these filters are available in reference [1] and should be multiplied by the relevant factor to accomplish this. A new “Paul” filter (already scaled for F0 operation) has been developed which in most cases has faster settling times than the well-known ones while providing the necessary PWM ripple attenuation. As with the others, it too can be scaled for operation at different frequencies.

It should be noted that component tolerances will lead to filters with attenuations and settling times which differ somewhat from the calculations presented. Still, it makes sense to employ filters with the smallest calculated settling time values.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content


  1. http://www.analog.com/media/en/training-seminars/design-handbooks/basic-linear-design/chapter8.pdf%20 (specifically Figures 8.26 through 8.36. This reference does a great job of describing the differences between the filter response types and filter realization in general.)
  2. https://www.wolframalpha.com/input?i=inverse+Laplace+transform+p*b%5E2%2F%28%28s%5E2%2Bb%5E2%29*%28s%2Bp%29%29
  3. https://support.microsoft.com/en-us/office/define-and-solve-a-problem-by-using-solver-5d1a388f-079d-43ac-a7eb-f63e45925040
  4. https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
  5. https://www.ti.com/lit/an/sloa024b/sloa024b.pdf
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Integrated motor drivers save PCB space

Чтв, 02/29/2024 - 20:48

Along with a dsPIC33 digital signal controller (DSC), motor drivers from Microchip pack a three-phase MOSFET gate driver and optional LIN or CAN FD transceiver. These integrated devices reduce the component count, PCB size, and complexity of embedded motor control systems in space-constrained applications.

Real-time processing is enabled by the dsPIC33 DSC, which operates between 70 MHz and 100 MHz. It provides up to 256 kbytes of ECC flash memory, 12-bit ADCs, and a 32-bit optical/incremental encoder interface. The DSC also supports field-oriented control (FOC) and other advanced motor control algorithms.

The integrated motor drivers operate from a single power supply up to 29 V with transient tolerance up to 40 V. An internal 3.3-V low-dropout voltage regulator powers the dsPIC33 DSC, eliminating the need for an external LDO. Qualified to AEC-Q100 Grade 0 requirements, the devices operate from -40°C to +150°C.

The dsPIC33-based motor drivers are supported by an ecosystem of software and hardware development tools. These include the dsPIC33CK motor control starter kit and MCLV-48V-300W development board. The motorBench development suite is a free GUI-based tool for FOC. Also available are various reference designs, including an automotive cooling fan and drone propeller controller.

dsPIC33 driver product page

Microchip Technology 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Switchers tout single-stage multi-output operation

Чтв, 02/29/2024 - 20:48

InnoMux-2 is a family of GaN-based flyback switcher ICs from Power Integrations that offers multiple independently regulated outputs. The switchers consolidate AC/DC and downstream DC/DC conversion stages into a single chip, providing up to three independently regulated outputs or two voltage outputs and a constant current output.

The elimination of separate DC/DC stages not only reduces component count and PCB footprint, but also increases efficiency by as much as 10% compared to conventional two-stage architectures. Efficiency is aided by integrated 750-V GaN transistors, zero-voltage switching, and synchronous rectification.

InnoMux-2 ICs deliver up to 90 W of output power with regulation of better than ±3% across input line, load, and temperature. Total power system efficiency (AC to regulated low-voltage DC) is above 90%. The InnoMux-2 controller also manages light-load power delivery, eliminating the need for preload resistors and reducing no-load consumption to less than 30 mW.

Prices for the InnoMux-2 IMX2174F devices start at $1.11 each in lots of 50,000 units. The parts come in thermally efficient InSOP 24 and InSOP 28 packages.

InnoMux-2 product page

Power Integrations

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Current sensor helps shrink EV onboard chargers

Чтв, 02/29/2024 - 20:47

Asahi Kasei’s CZ39 series of coreless current sensors allows OEMs to design smaller and lighter onboard chargers for electric vehicles. With its fast response time, low heat generation, and noise immunity, the CZ39 enables current measurements in high-speed SiC- and GaN-based power systems.

The current sensor employs a sensitive compound Hall element that enables a response time of 100 ns, fast enough to keep up with the high switching speed of SiC and GaN devices. Its unique package maintains a primary conductor resistance of just 0.3 mΩ.

Even under continuous 40-A current flow at an ambient temperature of +125°C, heat generation is minimal. This reduces the need for bulky thermal management measures. The structure of the package provides sufficient creepage and clearance distances for use in applications above 650 V. CZ39 devices also offer enhanced noise immunity, ensuring continuous and accurate current detection in noisy automotive environments.

Asahi Kasei has begun mass production of the CZ39 series of coreless current sensors. For more information about the CZ39 series, click here.

Asahi Kasei Microdevices

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Wireless modules expand development options

Чтв, 02/29/2024 - 20:47

Quectel has launched four new Wi-Fi and Bluetooth modules to provide designers with a greater array of options in terms of size, cost, and power efficiency. Joining the company’s portfolio of IoT modules are the FCU741R Wi-Fi 4 module and the FCS950R Wi-Fi 5/Bluetooth 4.2 combo module. The HCM010S Bluetooth LE 5.4 module and the HCM111Z Bluetooth LE 5.3 module also extend the IoT lineup.

The FCU741R Wi-Fi 4 module for wireless LAN connections operates at 2.4-GHz and 5-GHz frequencies to deliver a maximum data rate of 150 Mbps. It offers a USB 2.0 interface and operates over a temperature range of -20°C to +70°C.

The FCS950R Wi-Fi 5 and Bluetooth 4.2 module supports IEEE 802.11a/b/g/n/ac and achieves a maximum data rate of 433.3 Mbps in 802.11ac mode. It also furnishes an SDIO 3.0 interface and is just 12.0×12.0×2.35 mm.

Outfitted with an Arm Cortex-M33 processor, the HCM010S module supports both Bluetooth LE 5.4 and Bluetooth mesh networking. Built-in memory comprises 64 kbytes of SRAM and 768 kbytes of flash. Transmit power up to +20 dBm enables a longer transmission range.

Also based on an Arm Cortex-M33 processor, the HCM111Z Bluetooth LE 5.3 module offers a maximum data rate of 2 Mbps. It includes 48 kbytes of SRAM and 512 kbytes of flash memory, as well 13 general-purpose I/Os and a built-in codec for microphone pickup and audio playback.

Quectel Wireless Solutions 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Transceivers enable contactless USB2 connectivity

Чтв, 02/29/2024 - 20:47

Two 60-GHz V-band transceivers, the ST60A3H0 and ST60A3H1 from ST, offer short-range cable-free connectivity at up to 480 Mbps. Operating in half-duplex mode, these compact devices enable embedded USB2 (eUSB2), I2C, SPI, UART, and GPIO RF tunneling.

The ST60A3H0 and ST60A3H1 can be used in personal electronics like digital cameras, wearables, portable hard drives, and small gaming terminals. They also afford data transfer in industrial applications, such as rotating machinery. As cost-effective cable replacements, the transceivers allow designers to create products with slim, aperture-free cases.

Self-discovery with instant mating eliminates pairing, while low power consumption preserves battery runtime. The parts consume 130 mW in eUSB Rx/Tx mode and 90 mW in UART, GPIO, and I2C modes. Shutdown mode reduces power consumption to just 23 µW.

Housed in VFBGA packages, the ST60A3H0 connects to an external antenna, while the ST60A3H1 has an integrated antenna. Samples of the transceivers are available now and cost $5. Detailed technical data, evaluation kits, and production pricing are subject to a non-disclosure agreement.

ST60A3H0 product page

ST60A3H1 product page


Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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APEC 2024, Day 3: Daily Briefing Video

Чтв, 02/29/2024 - 18:45

EDN editor-in-chief Majeed Ahmad and Power Electronics News editor-in-chief Maurizio Di Paolo Emilio discuss the highlights on day 3 of APEC 2024. One major topic included the move to a greener infrastructure for automotive manufacturing and more efficient automotive subsystems such as power trains. Wide bandgap (WBG) semiconductors such as SiC and GaN will be critical in realizing higher efficiencies for these systems moving forward. 

Majeed touched upon the rising popularity of GaN devices for applications outside its previous space of consumer electronics (e.g., USB chargers, AC adapters, etc.) and high frequency (RF) devices to other use cases such as data center power supplies and EV systems. Many players have, in recent years, made the claim that GaN can go beyond 650 V however, the jury is still out on its viability especially in large volumes. GaN power devices must contend with finding a suitable substrate to enhance factors such as power density, voltage capabilities, thermal performance, larger wafer sizes, long-term reliability, etc. Substrates for GaN vary from GaN-on-Si, GaN-on-SiC, to more specialty GaN-on-GaN, GaN-on-sapphire, and GaN on ceramics such as QST as accomplished by Vanguard International Semiconductor (VIS) in Taiwan. 

SiC technology has been steadily maturing where cost and wafer availability issues are appearing to ease up. Many exhibitors displayed wafers up to 8″and test and measurement (T&M) systems for wafer testing. Innovations in simulation tools such as QSPICE continue to keep up the pace with advances in SiC technologies, offering engineers a free platform rapidly to evaluate designs. Finally, Maurizio covers the non-WBG technologies revealed including a hydrogen fuel cell power system by Kohler Energy. 

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Photosensitivity: Seizures from displays

Чтв, 02/29/2024 - 17:53

A couple of years ago, I described having witnessed someone undergo an epileptic seizure at the company where I was employed at the time. I tried to keep cool and collected while writing about that incident, but the truth be told, it was jarring. Please read the story here.

I was idly browsing on my “smart” phone the other day when I came across an item about a then upcoming Star Wars movie where clever computer people had recreated the character Princess Leia as she would have been portrayed by the late Carrie Fisher. I was taken aback by an admonishing note on the link, but I grasped its justification as I watched the clip itself (Figure 1).

Figure 1 Film clip of the upcoming Star Wars movie with the warning “Contains flashing images”

Before one gets to watch the clip showing off the video technology that has been brought to bear, there is a warning about “flashing images”. When the film clip runs, the rapid flash-flash-flash for which Star Wars films are noted actually had a somewhat disorienting effect on yours truly and I do NOT have any epileptic history.

The point of all this is that those of us whose work products involve display(s) of any kind need to be cognizant of the possible dangers that a flashing display might present to some users of the product(s).

Some of us will recall that this was one of the plot devices in the movie The Andromeda Strain back in 1969 in which a woman is driven by a flashing image into an epileptic attack.

From more than half a century ago right up to this very moment, this concern is for real and quite frankly, I am glad to see it having been addressed as shown in Figure 1.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

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APEC 2024, Day 2: Daily Briefing Video

Чтв, 02/29/2024 - 17:35

During Day 2 of APEC 2024, Power Electronics News editor-in-chief Maurizio Di Paolo Emilio and EDN editor-in-chief Majeed Ahmad underscored the significance of silicon and silicon carbide technologies alongside passive components, gallium nitride advancements, and the promising outlook of fusion energy. ADI introduced a gate driver tailored for GaN FETs, while Infineon and Qorvo exhibited diverse, SiC-based solutions. SemiQ also made substantial investments in SiC, unveiling 1,200-V MOSFETs.

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APEC 2024, Day 1: Daily Briefing Video

Срд, 02/28/2024 - 15:15

Welcome to the first day of the 2024 APEC conference, where global leaders converge to discuss pivotal topics shaping our technological landscape. Today, we delve into the field of semiconductor technology, exploring the transformative potential of wide-bandgap semiconductors and the dichotomy between wide-bandgap and not-wide-bandgap semiconductors. In this video, we analyze some points during the plenary session on Day 1.

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Lenovo’s Smart Clock 2 Charging Dock: Multiple lights and magnetic “locks”

Срд, 02/28/2024 - 14:56

Two months ago, EDN published my teardown of Lenovo’s Smart Clock 2:

I’d mentioned in it that my dissection victim, acquired at steep discount from the original MSRP, included the “optional charging dock for both it, a wireless-charging (with MagSafe support, to boot) smartphone or other device, and a USB-tethered device (the USB charging port moved from the back of the speaker itself to the dock in this second-generation design)”:

An upfront correction before proceeding; I realize in retrospect upon re-read that my imprecise wording might have left you with the impression that the dock not only charged wireless- and USB-connected devices but also powered the Smart Clock 2 itself. Indeed, there’s an array of contacts on the underside of the Smart Clock 2:

which, as you’ll soon see, mate up to an array of spring-loaded pogo pins on the dock. However, as you may have already ascertained, given that that the Smart Clock 2 comes with a wall wart:

which mates with a barrel plug connector on the back of the device:

the power flow actually goes from the Smart Clock 2 to the charging dock and from there to its USB and wireless charging facilities for other devices’ use. One other note on the latter point, by the way…since the wall wart’s DC output is only 18W (12 V x 1.5 A) and since some of that power needs to be devoted to fueling the Smart Clock 2 itself along with whatever might be connected to the dock over USB, that explains (among other reasons) why Lenovo labels the wireless charging pad as “MagSafe-compatible”, not fully “Made for MagSafe”. Indeed, dive into the products’ tech spec minutia and you’ll find the following regarding the dock’s wireless charger:

  • 5 W
  • 7.5 W
  • 10 W
  • Fast-charging

Frankly, I was surprised to see that the peak wireless charging power goes that high; I’m guessing it’s only valid if the USB charging port isn’t in simultaneous use at the time.

In that earlier writeup, I also noted that “I bought mine brand new direct from Lenovo at the end of 2022 for only $29.99, complete with the docking station (which I’ll save for another teardown to come).” That time is now if you haven’t already figured it out ;-).

Our previous allusion to the charging dock, aside from the verbiage and pictures on the outside of the combined packaging:

was intentionally titillating: a brief glimpse of a white box:

underneath the more decorative box for the Smart Clock 2 itself (which was presumably intended to be optionally placed directly on retailer shelves for standalone sale):

Here’s a fuller view of the aforementioned box o’the bottom, as-usual accompanied by a United States penny (0.75 inches/19.05 mm in diameter) for size-comparison purposes:

Riveting presentation, eh? I’ll save you six closeups of various plain white box panels, instead substituting a sole closeup of the product sticker in the previous overview shot:

Yes, the label includes the FCC ID (O57SEA61UW). And yes, if you’re impatient to see what the charging dock looks like inside you could bypass my scintillating prose and jump right to the FCC’s internal photos. But where’s the fun in that? Are you trying to hurt my feelings? 😉

Ahem. Onward:

Here’s our first glimpse of our victim; its bottom side, to be precise:

The charging dock has dimensions of 0.93″ x 8.65″ x 3.26″ (23.66 mm x 219.65 mm x 82.77 mm). I couldn’t find a weight spec anywhere and didn’t think to weigh it myself until after it was already in pieces. Underneath it is nothing but more cardboard along with a literature sliver:

Here’s the dock again, still in its protective translucent sleeve:

First glimpse of the topside:

Finally freed from its plastic captivity:

The two oval inserts fit into matching insets on the underside of the Smart Clock 2, with the one handling power transfer obvious from the aforementioned pins-to-contacts cluster:

Let’s next look around back to get a different perspective on those pins:

Along with, refocusing slightly, that USB charging port:

Finally, flipping the dock back over (the front and sides are bland unless you’re into pictures of off-white plastic):

Let’s take a closer look at those markings and the sticker alongside them:

You probably also saw the two rubberized “feet”. If you’ve perused any of my teardowns before, you know that what’s often underneath them (screw heads, etc.) are prime candidates to get inside, therefore garnering my immediate attention. Habitual behavior rears its head again:


Keen-eyed readers may have already noticed that both feet left plastic film behind:

which thankfully was no match for my trusty Philips screwdriver:

That said, I’m honestly not sure how much purpose the screws served, since after I sufficiently loosened them, I was left with two enclosure halves that still stubbornly clung together. Some additional attention along the sides from my spudger followed by a screwdriver (flat head this time), along with some patience, finally convinced them to separate, however:

In the process of wrestling the bottom panel away, I’d inadvertently also dislodged a previously unknown-to-me top-side insert, which I focused my attention on next:

And after removing four screws holding the metal plate in place (underneath of which, I suspect you’ve probably already guessed, is the wireless charging coil), I was able to lift it away:

See, there’s the coil (other examples of which we’ve seen before in teardowns past)!

Revealing, in the left-behind top half of the chassis, the “MagSafe-compatible” magnets:

Next step: separate the PCB from the insert. The first four screws to be removed were obvious to my eyes, but the PCB still wouldn’t budge…until I looked again more closely and saw #5 (not the first time I’ve overlooked a screw in a disassembly rush, and likely not the last, either):

Free at last!

Speaking of magnets, here’s another (bigger) one:

Revisiting my earlier Smart Clock 2 teardown, I realized I hadn’t mentioned a metal plate on the inside of its underside, focusing instead on the mini-PCB (such an electrical engineer, aren’t I?):

This magnet, perhaps obviously, proximity-clings to the plate, thereby helping keep the Smart Clock 2 connected to the dock below it.

Finally, the closeups of the “guts” that you’ve been waiting for. Note first the black-color ground strap wire connecting the metal plate to the PCB:

Flip it over and you can see the two thick wires connecting the PCB to the coil, along with two much thinner wires that run between the PCB and the temperature sensor at the coil’s center:

Now for the PCB itself. Here’s the side you’ve already seen plenty of, which points downward when the system is assembled:

Near the center, and toward the top, is a chip marked MT581 (along with a vertical line seemingly drawn by hand with a Sharpie?) from Maxic Technology, described as a “highly integrated, high-performance System on Chip (SoC) for magnetic induction based wireless power transmitter solutions”. It’s the function equivalent of various ICs from STMicroelectronics that I’ve encountered in past wireless charger teardowns. Below and to its right is the CH552T, a USB microcontroller manufactured by Nanjing Qinheng Microelectronics. Unsurprisingly, it’s nearby the dock’s USB charging port. And in the upper right quadrant, to the right of the MT581, is a cluster of four small chips with identical markings:


whose function eludes my Google research (ideas, readers?). Flip the PCB over:

and the dominant feature that’ll likely catch your eye is a rectangular-ish outline near the periphery comprised of 18 small white pieces of what looks like plastic. At first, I thought they might find use in attaching the PCB to the underside of the insert, but more thoughtful analysis quickly dashed that theory. Turning the PCB sideways revealed their true purpose:

They’re LEDs, implementing the charging dock’s “nightlight” function. Duh on me!

That’s all I’ve got for today, folks, although I’ll as-usual hold onto the pieces o’hardware for a while, for potential assistance in answering any questions you might have on stuff I haven’t already covered. More generally, as always sound off with your thoughts in the comments!

Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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Voltage inverter uses gate’s output pins as inputs and its ground pin as output

Втр, 02/27/2024 - 16:33

When analog circuits mix with digital, the former are sometimes dissatisfied with the latter’s usual single supply rail. This creates a need for additional, often negative polarity, voltage sources that are commonly provided by capacitive charge pumps.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The simplest type is the diode pump, consisting of just two diodes and two capacitors. But it has the inherent disadvantages of needing a separately sourced square wave to drive it and of producing an output voltage magnitude that’s at least two diode drops less than the supply rail. 

Active charge pump switches (typically CMOS FETs) are required to avoid that.

Many CMOS charge pump chips are available off the shelf. Examples include the multi-sourced ICL7660 and the Maxim MAX1673 pumps that serve well in applications where the current load isn’t too heavy. But they aren’t always particularly cheap (the 1673 for example is > $5 in singles) and besides, sometimes the designer just feels the call to roll their own. Illustrated here is an example of the peculiar outcomes that can happen when that temptation isn’t resisted.

The saga begins with Figure 1, showing a (vastly simplified) sketch of a CMOS logic inverter.

Figure 1 Simplified schema of typical basic CMOS gate I/O circuitry showing clamping diodes and complementary FET switch pair.

Notice first the input and output clamping diodes. These are included mainly to protect the chip from ESD damage, but a diode is a diode and can therefore perform other useful functions, too. Similarly, the P-channel FET pair was intended to connect the V+ rail to the output pin when outputting a logic ONE, and the N-channel for connection to V- to pin for a ZERO. But CMOS FETs will willingly conduct current in either direction when ON. Thus, current running from pin to rail works just as well as from rail to pin. 

Figure 2 shows how these basic CMOS facts relate to charge pumping and voltage inversion.

Figure 2 Simplified topology of logic gates comprising voltage inverter, showing driver device (U1), switch device (U2), and coupling (Cc), pump (Cp), and filter (Cf) capacitors.

 Imagine two inverters interconnected as shown in Figure 2 with a square wave control signal coupled directly to U1’s input and through DC blocking cap Cc to U2’s with U2’s input clamps providing DC restoration.

Consider the ZERO state half cycle of the square wave. Both U1 and U2 P-channel FETs will turn on, connecting the U1 end of Cp to V+ and the U2 end to ground. This will charge Cp with its U1 terminal at V+ and its U2 end at ground. Note the reversed polarity of current flow into U2’s output pin due to Cp driving the pin positive and from there to ground through U2’s P FET and positive rail pin.

Then consider what happens when the control signal reverses to the ONE state.

Now the P FETs will turn OFF while the N FETs turn ON. This forces the charge previously accepted by Cc to be dumped to ground through U1 and its complement drawn from U2’s V- pin, thus completing a charge-pumping cycle that delivers a quantum of negative charge:

Q- = -(CpV+ + Cf V–)

to be deposited on Cf. Note that reversed current flow through U2 occurs again. This cycle will repeat with the next reversal of the control signal, and so on, etc., etc.

During startup, until sufficient voltage accumulates on Cf for normal operation of internal gate circuitry and FET gate drive, U2 clamp diodes serve to rectify the Cp drive signal and charge Cf.

That’s the theory. Translation of Figure 2 into practice as a complete voltage inverter is shown in Figure 3. It’s really not as complicated as it looks.

Figure 3 Complete voltage inverter: 100 kHz pump clock (set by R1C1), Schmidt trigger and driver (U1), and commutator (U2).

 A 100 kHz pump clock is output on pin 2 of 74AC14 Schmidt trigger U1. This signal is routed to the five remaining gates of U1 and the six gates of U2 (via coupling cap C2). Negative charge transfer occurs through C3 into U2 and accumulates on filter cap C5.

Even though the Schmidt hysteresis feature isn’t really needed for U2, the same type is used for both chips to improve efficiency-promoting synchronicity of charge-pump switching.

Some performance specs (V+ = 5V):

  • Impedance of V- output: 8.5 Ω
  • Maximum continuous load: 50 mA
  • Efficiency at 50 mA load: 92%
  • Efficiency at 25 mA load: 95%
  • Unloaded power consumption: 440 µW
  • Startup time < 1 millisecond

But finally, is there a cost advantage to rolling your own? Well, in singles, the 1673 is $5, the 7660 about $2, but two 74AC14s can be had for only a buck. The cost of passive components is similar, but this DI circuit has more solder joints and occupies more board area. So, the bottom line…??

But at least using outputs as inputs and ground as an output was fun.

And an afterthought: For higher voltage operation, simply drop in CD4106B metal-gate chips for the 74AC14s, then with no other changes, V+ and V- can be as high as 20V.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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Computer upgrades: Motivations, hiccups, outcomes, and learnings

Пн, 02/26/2024 - 16:30

I habitually, admittedly, hold onto computers far longer than I should, in the spirit of “if it ain’t broke, don’t fix it” (not to mention “a penny saved is a penny earned”). What I repeatedly forget, in the midst of this ongoing grasping, is that while the computer I’m clinging to might originally have been speedy, sizeable and otherwise “enough” for my needs, the passage of time inevitably diminishes its capabilities. Some of this decline is the result of the inevitable “cruft” it accumulates as I install and then upgrade and/or uninstall applications and their foundation operating systems, as well as the data files I create using them (such as the Word file I’m typing into now). I also fiscally-conveniently overlook, for example, that newer operating system and application revisions make ever-increasing demands on the computer hardware.

Usually, what compels me to finally make the “leap of faith” to something new is some variant of utter desperation: either the existing hardware has been (or will soon be) dropped from the software support list or a software update has introduced a bug that the developer has decided not to fix. Today’s two case studies reflect both of these scenarios, and although the paths to the replacement systems were bumpy, the outcomes were worth the effort (not to mention everything I learned along the way). So much, in fact, that I’ve got another upgrade queued for the upcoming Christmas holiday next-week (as I write these words in mid-December 2023). Wonder how long I’ll wait to update next time?

The 2020 (Intel-based) Apple 13” Apple Retina MacBook Pro (RMBP)

This one had actually been sitting on my shelf for more a year, awaiting its turn in my active-computer rotation, ever since I saw it on sale brand new and open-box discounted at Small Dog Electronics’ website for $1,279.99. When I found out that this particular unit also came with AppleCare+ extended warranty coverage good through mid-May 2025, therefore representing a nearly $1,000 discount from the new-from-Apple total price tag, I pulled the purchase trigger.

It represents the very last iteration of Intel-based laptops from Apple, introduced in May 2020. Why x86, versus Apple Silicon-based? I went for it due in part to its ability to run not only MacOS but also Windows, either virtualized or natively, although I also have a 13” M1 MacBook Air (also open-box, also from Small Dog Electronics, and with similar RAM and SSD capacities: keep reading) in queued inventory for whenever Apple decides to drop x86 support completely.

This high-end RMBP variant, based on a 2.3 GHz quad-core Intel Core i7 “Ice Lake” CPU, includes four Thunderbolt 3 ports, two on either side, versus the two left-side-only configurations of lower-end models. It also integrates 16 GBytes of RAM and a 512 GByte SSD. Unlike its 2016-2019 “butterfly” keyboard precursors, it returns to the reliable legacy “scissors” keyboard (this actually was key—bad pun intended—for me) that Apple amusingly rebranded as the “Magic Keyboard”. Above the keyboard are the Touch ID authentication sensor alongside the nifty (at least to me), now-deprecated Touch Bar. And thankfully, Bluetooth audio support in MacOS 12 “Monterey” for Zoom and other online meeting and webinar apps now works again.

Normally, I’d restore a Time Machine backup, originating from the old machine, to the new one to get me going with the initial setup. But at the time, I was more than 1,000 miles away from my NAS, at my relatives’ house for the Thanksgiving holidays. Migration Assistant was a conceptual alternative, although from what I’ve heard it’s sometimes more trouble than it’s worth. Instead, particularly with my earlier “cruft” comment in mind, I decided to just start from scratch with software reinstalls. That said, I still leveraged a portable drive along with my relatives’ Wi-Fi to copy relevant data files from the old to new machine.

The process was slow and tedious, but the outcome was a solid success. I can still hear the new system’s fan fire up sometimes (a friend with an Apple Silicon system mocks me mercilessly for this) but the new machine’s notably faster than its predecessor. Firefox, for example, thankfully is much snapper than it was before. And speaking of Mozilla applications, I was able to migrate both my Firefox and Thunderbird profiles over intact and glitch-free; the most I ended up having to do was to manually disable and re-enable my browser extensions to get them working again, along with renaming my device name in the new computer’s browser settings for account sync purposes. Oh, and since the new system’s not port-diversity-adorned like its precursor, I also had to assemble a baggie of USB-C “dongles” for USB-A, HDMI, SD cards, wired Ethernet…sigh.

The Microsoft Surface Pro 7+ (SP7+) for business

This next one shouldn’t be surprising to regular readers, as I telegraphed my intentions back in early November. The question you may have, however, is why did I tackle the succession now? For the earlier-discussed MacBook Pro, the transition timing is more understandable, as its early-2015 predecessor will fall off Apple’s O/S-supported hardware list in less than a year. Its performance slowdowns were becoming too noticeable to ignore. And the Bluetooth audio issues I started having after its most recent major O/S upgrade were the icing on the cake.

The Surface Pro 5 (SP5), on the other hand, runs Windows 10, for which Microsoft has promised full support until at least mid-October 2025, longer if you pay up. Its overheating-induced clock throttling was annoying but didn’t occur that often. And although its RAM and SSD capacity limitations were constraining, I could still work around them. Part of the answer, frankly, ties back to how smoothly the RMBP replacement had gone; it tempted me to tackle the SP7+ upgrade sooner than I otherwise would. And another part of the answer is that I wanted to be able to donate both legacy systems to charity while they were still supported and more generally could still be useful to someone else with less demanding use cases. Specifically, I hoped to wrap up both upgrades in time to get the precursor computers to EChO for pass-along in time for them to get wrapped up by their recipients as Christmas presents for others.

Once again, I did “clean” installs of my suite of applications to the SP7+. This strategy, versus an attempted “clone” of the old system’s mass storage contents, was even more necessary in this case because the two computers ran different operating systems (Windows 10 Pro vs Windows 11 Pro). And again, the process was slow but ultimately successful. That said, the overall transition was more complicated this time, due to what I tackled before the installs even started. As I’d mentioned back in November, one of the particularly appealing attributes of the SP7+ (and SP8, for that matter) versus the SP5 is that their SSDs (like that in my Surface Pro X) are user-accessible and -replaceable. What I did first, therefore, after updating Windows 11 and the driver suite to most current versions, was to clone the existing drive image in the new system to a larger-capacity replacement, initially installed in an external enclosure.

Here’s the 256 GByte m.2 2230 SSD that the system came with, complete with its surrounding heatsink, post-clone and removal:

And here’s the 1 TByte replacement, Samsung’s PM991a (PCIe 3.0-based, to allay any excess-energy consumption concerns):

before cloning the disk image to it and installing it (absent a heatsink or thermal tape, but it still seemingly works fine) in place of its precursor:

As you can probably tell from the sticker on one side, it wasn’t new-as-advertised. But it had been only lightly used (and the bulk of that was from me, doing multiple full- and quick-format cycles on it for both initial testing and failed-clone-recoveries) so I kept it:

First step, the clone. I’d thought this might be complicated a bit by the fact that since the system was running the Pro version of Windows 11, (potentially performance-sapping) BitLocker drive encryption was enabled by default. Fortunately, however, my cloning utility of choice (Macrium Reflect Free, which I’ve long recommended) was able to handle the clone as-is just fine, even on a booted O/S with an active partition, although it warned me afterwards that the image on the SSD containing the clone would be unencrypted. Fast forwarding to the future for a moment, I made sure to archive a copy of the existing SSD’s encryption key before doing the swap, in case I ever needed to use it again. The new SSD came up auto-re-encrypted by Windows on first boot, I didn’t need to re-activate the O/S, and I archived its BitLocker key, too, for good measure.

The other—hardware—aspect of the clone was more problematic. Here’s the enclosure that I used to temporarily house the new SSD, Orico’s TCM2-C3, which I bought back in February 2020 and have been using trouble-free for a variety of external-tether purposes ever since:

This time was different. I initially tried tethering the new SSD-inclusive enclosure to the SP7+ via the USB-C to USB-C cable that came with the enclosure, but shortly after each cloning operation attempt started, I’d get an obscure “Error Code 121 – The semaphore timeout period has expired” abort message from Macrium Reflect. Attempts to reformat the SSD before trying the clone again were also inconsistent, sometimes succeeding, other times not due to spontaneous disconnects. Eventually, I got everything to work by instead using the slower but more reliable USB-A to USB-C cable that also came with the enclosure. Is my USB-C to USB-C cable going bad? Or is something amiss with the USB-C transceiver in the system or the enclosure? Dunno.

Once I booted up the computer with the new SSD inside, I ran into two other issues. The first was that the initial O/S partition, which had been hidden on the original SSD, was now visible and had been assigned the C: drive letter. A dive into Windows’ Disk Management utility got this glitch sorted out.

The other quirk, which I’d encountered before, was that the new SSD still self-reported as 256 GBytes in size, the same capacity as its predecessor. Disk Management showed me the sizeable unused partition on the new SSD, which I’d normally be able to expand the main O/S partition into. In this particular case it wasn’t able to do so, though, because the two partitions were non-contiguous; in-between them was 650 Mbyte hidden Windows Recovery partition. I could have just deleted that one, although it would have complicated any subsequent if-needed recovery attempt. Instead, I used another slick (and gratis) utility, MiniTool’s Partition Wizard, to relocate the recovery partition to the “end”, thereby enabling successful O/S partition expansion:

And as hoped-for, the SP7+ is fully compatible with my full suite of existing SP5 accessories:

What’s next?

Requoting what I said upfront in this piece:

I’ve got another upgrade queued for the upcoming Christmas holiday.

It’s my “late 2014” Mac mini, which I’d transitioned to fairly recently, in mid-2021, for similar obsolescence reasons.

Like the early 2015 13” RMPB, it’s not scheduled to exit O/S support until mid-to-late 2024, but it’s becoming even more performance-archaic (due in part to its HDD-centric Fusion Drive configuration). Its replacement will be a 2018 Mac mini, also x86-based, whose specific configuration is “interesting” (I got a great deal on it, explaining why I went with it): a high-end 3.2 GHz Intel Core i7 CPU, coupled with 32 GBytes of RAM but only a 128 GByte SSD (which I plan to augment via external storage). Stand by for more details to come in a future post. And until then, I’m standing by for your thoughts on this piece in the comments!

Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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An MCU test chip embeds 10.8 Mbit STT-MRAM memory

Птн, 02/23/2024 - 14:51

A prototype MCU test chip with a 10.8 Mbit magnetoresistive random-access memory (MRAM) memory cell array—fabricated on a 22-nm embedded MRAM process—claims to accomplish a random read access frequency of over 200 MHz and a write throughput of 10.4 MB/s at a maximum junction temperature of 125°C.

Renesas, which developed circuit technologies for this embedded spin-transfer torque MRAM (STT-MRAM) test chip, presented details about it on February 20 at the International Solid-State Circuits Conference 2024 (ISSCC 2024) held on 18-22 February in San Francisco. The Japanese chipmaker has designed this embedded MRAM macro to bolster read access and write throughput for high-performance MCUs.

Figure 1 The MCU test chip incorporates a 10.8-Mbit embedded MRAM memory cell array. Source: Renesas

Microcontrollers in endpoint devices are expected to deliver higher performance than ever, especially in Internet of Things (IoT) and artificial intelligence (AI) applications. Here, the CPU clock frequencies of high-performance MCUs are in the hundreds of MHz, and to achieve greater performance, read speeds of embedded non-volatile memory need to be increased to minimize the gap between them and CPU clock frequencies.

However, MRAM has a smaller read margin than the flash memory used in conventional MCUs, which makes high-speed read operation more difficult. At the same time, MRAM is faster than flash memory for write performance because it requires no erase operation before performing write operations. That’s why shortening write times is desirable not only for everyday use but also for cost reduction of writing test patterns in test processes and writing control codes by end-product manufacturers.

Renesas has developed circuit technologies for an embedded STT-MRAM test chip with fast read and write operations to address this design conundrum.

Faster read and write

First, take MRAM reading, which is generally performed by a differential amplifier or sense amplifier to determine which of the memory cell current or reference current is larger. But because the difference in memory cell currents between the 0 and 1 states—read window—is smaller for MRAM than for flash memory, the reference current must be precisely positioned in the center of the read window for faster reading.

So, Renesas introduces two mechanisms to achieve faster read speed. First, it aligns the reference current in the center of the window according to the actual current distribution of the memory cells for each chip measured during the test process. Second, it reduces the offset of the sense amplifier.

Another challenge that Renesas engineers have overcome relates to conventional configurations, where large parasitic capacitance in the circuits is used to control the voltage of the bitline, so it doesn’t rise too high during read operations. While it slows the reading process, Renesas has introduced a Cascode connection scheme to reduce parasitic capacitance and speed up reading. That allows design engineers to realize the random read operation at more than 200 MHz frequencies.

Next, for write operation, it’s worth mentioning that Renesas announced in December 2021 that it has improved write throughput by applying write voltage simultaneously to all bits in a write unit using a relatively low write voltage generated from the external voltage (I/O power) of the MCU through a step-down circuit. Then, it used a higher write voltage only for the remaining few bits that could not be written.

Figure 2 In late 2021, Renesas announced an increase in the write speed of an STT-MRAM test chip manufactured on a 16-nm node.

Now, while power supply conditions used in test processes and by end-product manufacturers are stable, Renesas has relaxed the lower voltage limit of the external voltage. As a result, by setting the higher step-down voltage from the external voltage to be applied to all bits in the first phase, write throughput can be improved 1.8-fold. A faster write speed will contribute to more efficient code writing in endpoint devices.

Test chip evaluation

The prototype MCU test chip combines the above two enhancements to offer a 10.8 Mbit MRAM memory cell array fabricated using a 22-nm embedded process. The evaluation of the prototype chip validated that it achieved a random read access frequency of over 200 MHz and a write throughput of 10.4 MB/s.

The MCU test chip also contains 0.3 Mbit of one-time programmable (OTP) memory that uses MRAM cell breakdown to prevent falsification of data. That makes it capable of storing security information. However, writing to OTP requires a higher voltage than writing to MRAM, which makes it more difficult to perform writing in the field, where power supply voltages are often less stable. Here, Renesas suppressed parasitic resistance within the memory cell array, which in turn, makes writing in the field possible.

Renesas has vowed to further increase the capacity, speed, and power efficiency of MRAM.

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BLDC motor driver prolongs battery life

Чтв, 02/22/2024 - 20:58

A three-phase BLDC motor driver, the AOZ32063MQV from AOS, offers an input voltage range of 5 V to 60 V and 100% duty cycle operation. The IC enables efficient motor operation, while its low standby power helps extend the battery life of cordless power tools and e-bikes.

The AOZ32063MQV drives three half-bridges consisting of six N-channel power MOSFETs for three-phase applications. It has a high-side sink current of 1A and a maximum source current of 0.8 A. A power-saving sleep mode lowers current consumption to just 1 µA.

Along with an integrated bootstrap diode, the driver provides adjustable dead-time control and a fault indication output. Onboard protection functions include input undervoltage, short-circuit, overcurrent, and thermal shutdown. The device operates over a temperature range of -40°C to +125°C.

Housed in a 4×4-mm QFN-28L package, the AOZ32063MQV costs $1.55 in lots of 1000 units. It is available in production quantities, with a lead time of 24 weeks.

AOZ32063MQV product page

Alpha & Omega Semiconductor 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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100-V MLCC is among the industry’s smallest

Чтв, 02/22/2024 - 20:58

Murata expands its GJM022 series of high-Q multilayer ceramic capacitors (MLCCs) with a 100-V device that is just 0.4×0.2 mm (L×W). The MLCC is intended for high-frequency module applications, such as those used in cellular communication infrastructure.

Exhibiting high-Q, low-loss performance, the miniature capacitor enables electronic engineers to overcome packaging limitations, while maintaining optimal performance. A high-temperature guarantee also gives designers greater positioning freedom. The MLCC helps ensure reliable long-term operation, even in close proximity to power semiconductors that radiate heat.

The GJM022 can be used for a wide variety of applications, including impedance matching and DC cutting within RF modules for base stations. In such implementations, the capacitor’s high-Q value and low equivalent series resistance (ESR) contribute to improving power amplifier efficiency and lowering power consumption.

Engineering samples of the GJM022 100-V chip capacitor are available in limited production. The product will move to full stocked production in the next several weeks. A datasheet for the device was not available at the time of this announcement. For information on the GJM series of high-Q MLCCs, click the product page link below.

GJM series product page  


Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Development kit pairs RISC-V and FPGA

Чтв, 02/22/2024 - 20:58

The PolarFire SoC Discovery Kit from Microchip makes RISC-V and FPGA design accessible to a wider range of embedded engineers. This low-cost development platform allows students, beginners, and seasoned engineers alike to leverage RISC-V and FPGA technologies for creating their designs.

The Discovery Kit is built around the PolarFire MPFS095T SoC FPGA, which embeds a quad-core RISC-V processor that supports Linux and real-time applications. It also packs 95,000 FPGA logic elements. A large L2 memory subsystem can be configured for performance or deterministic operation and supports an asymmetric multiprocessing mode.

An embedded FP5 programmer is included for FPGA fabric programming, debugging, and firmware development. The development board also provides a MikroBUS expansion header for Click boards and a 40-pin Raspberry Pi connector, as well as a MIPI video connector. Expansion boards are controlled using protocols like I2C and SPI. 

The PolarFire SoC Discovery Kit costs $132 for the general public and $99 when purchased through Microchip’s Academic Program. Production kit shipments are expected to commence mid-April 2024.

PolarFire Soc Discovery Kit product page

Microchip Technology

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SP4T switches offer high isolation up to 8.5 GHz

Чтв, 02/22/2024 - 20:57

pSemi announced production readiness of two UltraCMOS SP4T RF switches that operate from 10 MHz to 8.5 GHz with high channel isolation. According to the manufacturer, the PE42445 and PE42446 switches integrate seamlessly into 4G and 5G base stations and massive MIMO architectures. They can provide digital pre-distortion feedback loops and transmitter monitoring signal paths to prevent interference and maintain signal integrity.


Both the PE42445 and PE42446 offer >60 dB isolation at 4 GHz and operate over an extended temperature range of -40°C to +125°C. Additionally, the devices provide low insertion loss across the band, high linearity of 65 dBm IIP3, and a fast switching time of 200 ns.  The SP4T switches are manufactured on the company’s UltraCMOS process, a variation of silicon-on insulator technology.

The PE42445 comes in a 3×3-mm, 20-lead LGA package, while the PE42446 is housed in a 4×4-mm, 24-lead LGA package. Sales inquiries can be submitted using the product page links below.

PE42445 product page

PE42446 product page 


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MRAM macro speeds read/write operations

Чтв, 02/22/2024 - 20:57

Renesas presented an embedded MRAM macro in an MCU test chip at ISSCC 2024 that delivers a random-read access frequency of over 200 MHz. The test chip also exhibited a write throughput of 10.4-Mbytes/s.

The company developed two high-speed circuit technologies to achieve faster read and write operations in spin-transfer torque magnetoresistive RAM (STT-MRAM). A prototype MCU test chip, fabricated using a 22-nm process, combined the two technologies with a 10.8-Mbit MRAM memory cell array. Evaluation of the prototype chip confirmed the high-speed results at a maximum junction temperature of 125°C.

Advancements in read technology have enabled Renesas to achieve what it claims is the world’s fastest random read access time of 4.2 ns. Even taking into consideration the setup time of the interface circuit that receives the MRAM output data, the company was able to realize random read operation at frequencies in excess of 200 MHz. Further, improved write technology can improve MRAM write throughput 1.8-fold.

For greater detail, read the complete press release here.

Renesas Electronics 

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Logic Probe has a wide voltage range

Чтв, 02/22/2024 - 16:53

The logic probe is powered from the device under test (DUT)—it may be any binary logic, which can be powered in the range +2 V to +6 V. This may be a microcontroller or 74/54 series logic chips, including HC/HCT chips.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The probe determines 3 conditions: 

  • Logical 0
  • Logical 1
  • Undefined (this may be a Z-condition, or bad contact).

It also features a counter, which is very handy when you want to count impulses, to estimate the value of frequency or to test an interface. (This part is shown as a sketch.)

The probe in Figure 1 consists of two Schmitt triggers, the upper trigger on the figure determines the logical 0, and the lower trigger determines the logical 1.

Figure 1 The logic probe with two Schmitt triggers where the upper determines logical 0 and the lower determines logical 1.

Two different colors were selected: 

  • Blue for logical 0
  • Red for logical 1

Since the blue LED demands more than 2 V, a slightly modified “joule-thief” circuit on Q2 is used to increase the voltage. The transformer has 2 windings with an inductance ranging from 80 to 200 µH, if the windings are not equal, the greater one should be connected to the collector. (The author used a tiny transformer from an old ferrite memory, but any coil with an added winding over it can do.)

If you choose a green or red LED instead of blue, the “joule-thief” circuit can be eliminated, and the LED connected between the upper terminal of R5 and “+A”.

Due to the wide supply voltage range, the current through the LEDs can increase 100% or more. Since the LEDs are quite bright, some control of brightness is desirable. It’s performed by the circuit’s U3, Q3, and two diodes, which can decrease the LEDs supply by 1.4 V.

Note, the 74HC14 can be used instead of the 74HC132 almost everywhere in the circuit.

Peter Demchenko studied math at the University of Vilnius and has worked in software development.

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