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Based on BrainChip’s Akida neuromorphic engine, the AKD1500 edge AI coprocessor is now available in a compact M.2 2230 (22×30 mm) form factor. The card features a B+M key edge connector for use with Raspberry Pi 5 and compatible host systems, enabling fanless, plug-and-play AI acceleration without redesigning existing power or cooling systems.

Operating from a 3.3-V supply, the AKD1500 M.2 card connects through a two-lane PCIe Gen2 host interface. The coprocessor integrates 32 neural processing units (NPUs) and delivers up to 800 effective GOPS (INT4) for edge AI inference. It also includes 1 MB of dual-port on-chip memory and consumes a typical 250 mW at 400 MHz.

The event-based digital architecture delivers ultra-low-power acceleration for standard neural network models and supports on-device learning, enabling applications to adapt without a cloud connection or full model retraining. Models are developed and optimized using BrainChip’s MetaTF software flow with TensorFlow/Keras and PyTorch front ends before deployment to the card.

The AKD1500 M.2 card with a B+M key connector is priced at $129 and is available for purchase directly from BrainChip.

AKD1500 M.2 product page 

BrainChip Holdings 

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Advantech is launching a portfolio of servers based on AMD EPYC 9006 SP8 processors to support next-generation AI infrastructure. Servers, such as the SKY-924E5F, provide the scalability and reliability required for AI, high-performance computing (HPC), networking, and mission-critical industrial workloads.

EPYC 9006 series server CPUs feature up to 128 Zen 6 or Zen 6c cores, 256 threads, and 2-nm process technology, delivering up to a 20% average performance improvement over the previous generation and up to a 20% performance-per-watt improvement. These processors enable more virtual machines, higher throughput, and improved system efficiency. With up to 128 PCIe Gen6 lanes per CPU, CXL 3.1 memory expansion, and support for DDR5-8000MHz and MRDIMM-12800MHz, the EPYC-powered servers provide balanced compute, memory, and I/O performance.

The edge servers support GPU-accelerated AI workloads and AFA-ready high-density E1.S/E3.S NVMe SSD storage. The lineup includes the following models:

• SKY-642E5, 4U MGX GPU server for large-scale AI acceleration
• SKY-722E5, 2U DC-MHS server with DC-SCM capability for modular data center and edge AI deployments
• SKY-712E5, 1U DC-MHS server with HHHL and FH-3/4L expansion card compatibility for high-density enterprise edge and cloud workloads
• SKY-822E5, 2U short-depth DC-SCM modular server accommodating 2–3 dual-slot GPU cards for space-constrained edge data centers
• SKY-924E5F, 2U 4-node front-access server for distributed edge computing
• ASMB-982 and ASMB-832, server boards for flexible, expandable system designs

A timeline for server availability was not provided at the time of this announcement. Learn more about the Advantech + AMD EPYC 9006 platform here.

Advantech

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Optimized for physical AI, AMD’s Ryzen AI Embedded X100 series processors combine CPU, GPU, and NPU resources on a single embedded SoC. With up to 16 AMD Zen 5 CPU cores, an integrated GPU, power-efficient NPU, and unified memory, the processors handle perception, reasoning, and real-time control workloads in robotics, industrial automation, aerospace and defense, and other embedded systems.

AMD says the series delivers up to 2.1× higher multithreaded CPU performance, 1.7× higher graphics performance, and 3.5× higher AI token generation with 1.4× faster time-to-first-token than Intel Core Ultra Series 3 processors. The company also says the processors provide up to 3× higher peak FP32 performance than the NVIDIA Jetson T5000 and an average 1.7× faster beamforming for cardiac ultrasound than the NVIDIA RTX 4000 Ada.

The Ryzen AI Embedded X100 series supports an open software stack with Linux, the AMD ROCm GPU software stack, the Xen Hypervisor, and AI frameworks including PyTorch, ONNX, and TensorFlow. AMD also provides tools to migrate CUDA codebases to ROCm.

Production availability of the Ryzen AI Embedded X100 series is expected in Q4 2026. Learn more about the processors on the product page or in AMD’s technical blog.

Advanced Micro Devices 

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Advanced Energy’s AIH03ZPFC power factor correction (PFC) converter delivers 1100 W of output power in a half-brick form factor. The board-mount module achieves up to 97.3% peak efficiency and a power density of 380 W/in³. According to the company, this represents a 2.3% improvement in efficiency and a 44% increase in power density over its previous-generation PFC devices.

The AIH03ZPFC integrates features that enhance functionality in a small half-brick design, including internal inrush limiting, digital PMBus control and monitoring, and auxiliary power support for external housekeeping functions. These capabilities make the converter well suited for industrial, medical, defense, and telecommunications systems with demanding size and efficiency requirements.

The AIH03ZPFC provides a 390-VDC output with 1% load regulation, maintains a unity power factor across an 85-VAC to 264-VAC input range, and requires no power derating under low-line conditions.

Baseplate contact cooling supports operation from -20°C to +100°C, with startup at temperatures as low as -40°C. The encapsulated half-brick package measures 2.4 × 2.3 in. (61 × 58.4 mm) and has an installed height of 0.52 in. (13.3 mm).

AIH03ZPFC product page

Advanced Energy Industries

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Cadence says its AuraStack AI Super Agent is the industry’s first agentic AI platform for PCB and advanced packaging design. Running on the company’s Allegro AI Studio and accelerated by NVIDIA Blackwell GPUs and NVIDIA CUDA-X libraries, the platform coordinates domain-specific AI agents across planning, implementation, and tightly integrated multiphysics analysis. AuraStack joins Cadence’s ChipStack, InnoStack, and ViraStack AI Super Agents, extending the company’s agentic AI portfolio across IC design, advanced packaging, and PCB design.

Built on the same architecture as Cadence’s ChipStack AI Super Agent, AuraStack combines agentic AI with simulation and optimization tools to automate design exploration, implementation, and signoff. An AI-driven multiphysics foundation concurrently models electrical, thermal, and mechanical behavior to support earlier design optimization.

According to Cadence, AuraStack can accelerate time to market by up to 2× and increase productivity by up to 15× while identifying system issues earlier in the design process to help reduce costly respins. It also enables system-level co-optimization with advanced packaging technologies, including CoWoS, to improve product performance and manufacturability.

Cadence plans to make the AuraStack AI Super Agent available in 2026.

AuraStack product page 

Cadence

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As the automotive industry shifts toward software-defined vehicles (SDVs), with features and updates delivered via software, vehicle electrical/electronic (E/E) architectures are evolving. These architectures are moving away from traditional flat and domain-based designs, in which separate control units for each function were the norm, to zonal architectures that group vehicle functions based on various criteria, such as physical location, application group, and other functional criteria in zone electronic control units (ECUs).

In a zonal architecture, each zone of a vehicle, such as front, rear, or cabin, has a high-performance controller managing local devices and communicating with other controllers over high-speed networks. This approach is faster to update, easier to scale, less complex, and even cheaper, but it also presents new technical challenges for automakers to overcome. The good news is that innovative microcontroller (MCU) solutions can help tackle those challenges.

Key challenges in the shift to zonal architectures

Zonal architectures offer clear benefits of reducing wiring complexity and consolidating compute resources.

However, each zone controller in an SDV must handle a wide range of tasks, from low-level real-time control of sensors and actuators (such as sensing braking pressure, steering angle, or controlling window-lift motors) to high-level data processing tasks (including controlling advanced safety systems or vehicle dynamics or running local AI models to process sensor data). This means the ECUs in a zonal design require compute capabilities that can handle both time-sensitive and compute-intensive workloads concurrently.

Maintaining freedom from interference among functions is a key challenge. Zonal designs consolidate diverse functions, from safety-critical functions such as braking to non-critical functions such as body control on a single ECU with shared compute and communication resources. Without proper safeguards, a fault in one function could disrupt others.

To prevent this, robust isolation mechanisms such as hardware-enforced separation are needed. Ideally, these features should be embedded in the hardware design rather than software implementation to minimize the impact on performance, behavior, or safety.

In-vehicle networks also need rethinking. Modern SDVs generate massive amounts of data from sensors and devices, including cameras, LiDAR, and radar, to support advanced driver-assistance and autonomous-driving features. The vehicle network must ensure that this data is delivered in a predictable and time-sensitive manner.

Traditional in-vehicle networks such as CAN, LIN, and FlexRay struggle to meet these demands at the scale of the modern SDV. Moreover, Ethernet is increasingly used in vehicles for its advantages in performance, reliability, and connectivity options, and at the same time, many legacy devices in the vehicle still use CAN or LIN.

To ensure network performance and avoid communication bottlenecks, next-gen vehicle controllers should include native support for Ethernet and CAN networking on-chip. A well-architected MCU will also enable sufficient control and acceleration features to reduce latency and ensure predictable message delivery, ultimately resulting in deterministic communications at the vehicle level.

Next-generation automotive MCUs need to adopt improved, low-latency architectures and design philosophies to overcome key challenges in the shift to zonal architectures. (Source: NXP Semiconductors) Making updates secure, easy, and fast

A hallmark of SDVs is the ability and the need to receive secure over-the-air (OTA) updates throughout the vehicle’s life. This contrasts with traditional vehicle designs with dozens of ECUs for which updates are complex, time-consuming, and often performed only in service environments.

For an SDV built on a zonal E/E architecture, software updates can be pushed to a selected number of controllers that can be responsible for the software of an entire region of the vehicle, such as the front zone or the rear chassis zone. To support these frequent updates with minimal downtime, embedded nonvolatile memory (eNVM) needs to be upgraded as well to a more versatile option with much faster write speeds and higher endurance.

How modern MCUs lay the foundation for next-gen SDVs

Next-generation automotive MCUs need to adopt improved, low-latency architectures and design philosophies to overcome these challenges. Rather than relying on a homogeneous architecture, the implementation of heterogeneous cores optimized by functions is required.

The NXP S32K5 MCU, for example, integrates different kinds of CPU cores complemented by various accelerators for dedicated functions such as AI/ML, signal processing, and network acceleration, enabling designers to assign the right function to the right core. Furthermore, a dedicated low-power engine is available for simple tasks, such as periodic wakeups and sensor monitoring, which can help optimize battery life in electric vehicles.

The integration of multiple functions of mixed criticality warrants robust mechanisms to ensure freedom from interference. The S32K5 lives up to this challenge by implementing features such as XRDC, an in-house NXP IP for isolation and resource allocation in hardware from pin to core.

Moreover, dedicated network accelerators need to be implemented for CAN2CAN (communication between CAN networks) and CAN2ETH (communication between CAN and Ethernet networks) acceleration to ensure deterministic and low-latency architectures.

In addition, integrating an Ethernet switch with fast data-routing capabilities ensures that the latest-generation Ethernet vehicle architectures can achieve latency requirements with minimal CPU load.

With an embedded MRAM as the eNVM, the S32K5 offers write speeds that are 15× faster than conventional eFlash. Write without erase and endurance of 1M write cycles of MRAM helps optimize costs, simplify software development, and minimize downtime for the frequent OTA updates expected in an SDV architecture.

Building the foundation for next-gen SDVs

Zonal architectures are emerging as a necessity for next-gen vehicles because they align with the needs of SDVs. They concentrate compute, reduce complexity, and enable new, software-driven experiences. With the latest generation of MCUs as the building blocks, automakers now have more tools to develop zonal vehicle architectures to deliver the high performance, reliability, and flexibility required by next-gen vehicles.

The post Accelerating the shift to next-gen SDVs with zonal MCUs appeared first on EDN.

Self-heated Darlingtion transistor pair linearly senses airflow using just two wires for both power in and signal out.

Suppose we take a common TO-92 transistor and heat it to a constant temperature differential above ambient.  The power input required to keep it there will be determined by its thermal impedance ZT relative to the surrounding air. This suggests it might be handy for air flow measurement.  Maybe even moreso if it needed only a simple two-wire connection for both (phantom) power supply from, and signal delivery to, the supporting electronics.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Please see the Related content listings below for a more detailed treatment of the subject.  Figure 1 graphs the resulting power vs air speed relationship.  Unfortunately, it’s badly bent.

Figure 1 This graph logs power dissipated vs air speed of a TO92 held at a constant 31oC above ambient. Pw = 31/ZT.

Figure 2 shows a practical thermostat circuit to achieve and maintain the delta-T while outputting a signal predictably related to Pw.  It utilizes a Darlington sensor transistor pair (Q1 and Q2) to compensate for ambient temperature and convert the resulting nonlinear Pw curve into a linearized airflow readout.  Its current mode, phantom-power output is compatible and convenient for the long cable runs often seen in airflow measurement applications.

Figure 2 This circuit implements a phantom-powered Darlington anemometer with a 40-140 mA current mode output.  Adjust R10 to calibrate 40 mA (zero fpm), and R11 to calibrate 140 mA (250 fpm). The adjustments interact so some iteration may be necessary.  Sorry ‘bout that.

Q1 serves as the self-heated sensor with Q2 providing ambient temperature compensation.  Opamp A2 runs a feedback loop that forces a constant Vbe differential between Q1 and Q2.  This establishes a constant 31oC temperature differential between Q1 and ambient.  It does this (with the help of Darlington current gain) by forcing Q1’s current draw (I) through R3 to drive Q1’s power dissipation (Pw) to follow the Figure 1 curve of heat-vs-air flow.

Okay so far.  But how does compensation for Figure 1’s nonlinearity happen?   Well, happily the function of Q1’s Pw vs collector current I isn’t linear either.  In fact Pw = 5vI – I2R3.  That quadratic I2 term is the key.  It creates the lovely linearizing curve shown in Figure 3.

Figure 3 This graph logs Q1 power dissipation vs  collector current.  Pw = 5vI – I2R3.

The 2nd-order curvature of fig. 3 irons out (most of) the bend in Figure 1 and results in a linear 33 to 125 mA current draw over the 0 to 250 fpm flow rate range. Although the match isn’t perfect, when converted to the 40 to 140 mA by opamp A1 and output transistor Q4, the realized output is a calibrated readout of air speed that differs from ideal by less than +/- 5% from 0 to 250 fpm, as shown in Figure 4.

Figure 4 This graph logs anemometer output vs airspeed. FPM = 2.5(Iout – 40mA).

Note that most (~90%) of the output current is actually drawn by inverted regulator U1 as it maintains a constant 5v across the (thirsty) thermal transistors.  All that’s left for A2 and Q4 is to conduct several mA of shim current to establish and maintain calibration, which barely gets Q4 warm.  U1, however, can be called on to dissipate about three quarters of a watt and thus should be bundled in a TO220 or similar package.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Self-heated Darlington transistor pair comprises new air flow sensor
• Linearized portable anemometer with thermostated Darlington pair
• Nonlinearities of Darlington airflow sensor and VFC compensate each other
• Improve thermal airflow sensor PSRR with just two resistors
• A groovy apparatus for calibrating miniature high sensitivity anemometers

The post Phantom-powered solid-state linear airflow sensor appeared first on EDN.

When people talk about AI hardware, the conversation usually begins with the AI accelerator. That is understandable. GPUs, custom AI accelerators, CPUs, and high-performance compute dies are the most visible symbols of the AI era. They are also where much of the leading-edge semiconductor investment is focused.

Advanced logic nodes, extreme transistor density, high-performance standard-cell libraries, and sophisticated design methodologies are all essential to scaling AI compute. But an AI accelerator alone does not create AI infrastructure.

A modern AI system is not one chip, one fab, one node, or one technology family. It’s a physical system built from many semiconductor ecosystems converging through packaging, substrates, interconnect, power delivery, cooling, reliability engineering, and manufacturing scale. And that distinction matters.

The AI era is not only pushing logic scaling. It’s forcing the semiconductor industry to rethink how different fab outputs—logic, memory, analog, power, compound semiconductor devices, photonics, MEMS, and mature-node control silicon—come together as one physical infrastructure platform. In other words: AI infrastructure is becoming a multi-fab physical realization stack.

This is the missing link in many AI hardware discussions.

The visible part: Leading-edge logic

The most visible part of AI hardware is the leading-edge logic die. This includes GPUs, CPUs, AI accelerators, network processors, and custom compute engines. These devices depend on advanced process technology, dense routing, high-performance transistors, complex power grids, and increasingly sophisticated design automation.

But the logic die is only the center of computation; it’s not the full system. The accelerator may execute the matrix operations, tensor workloads, inference engines, training loops, and dataflow schedules, but its usefulness depends on everything around it.

• How fast data can reach it
• How close memory can be placed
• How efficiently power can be delivered
• How heat can be removed
• How signals can escape the package
• How optical or electrical I/O can scale
• How the package can be manufactured and yielded
• How the system can be tested, qualified, and deployed

This is why AI hardware is no longer just a logic-node conversation. The accelerator is the most visible object, but the infrastructure stack, outlined below, is the real product.

1. Memory fabs: HBM becomes part of the compute architecture

AI compute is deeply memory constrained. The value of an accelerator depends not only on peak compute performance, but on how effectively it can access data. This is why memory fabs are central to AI infrastructure.

DRAM, NAND, and especially high-bandwidth memory (HBM) are no longer secondary components in the system. HBM has become part of the AI compute architecture itself. The location, bandwidth, thermal behavior, power profile, and package integration of memory directly affect system-level performance. This changes the role of packaging.

Advanced packaging platforms such as CoWoS, interposers, bridges, and other high-density integration methods are not merely ways to place chips together. They are mechanisms for bringing logic and memory into a physical relationship that conventional board-level integration cannot support.

The memory fab produces the memory device, but the AI system requires memory to be integrated into a bandwidth-dense, thermally stable, mechanically reliable, and yieldable package. That is physical realization.

2. Analog and mixed-signal fabs: The hidden interface layer

AI hardware may appear digital from the outside, but every real system depends on analog and mixed-signal functions. Interfaces, clocking, sensors, converters, retimers, voltage regulators, power management ICs, monitoring circuits, and control loops often come from process technologies very different from leading-edge logic.

These functions are not always glamorous, but they are essential. They help manage signal integrity, power sequencing, telemetry, control, protection, timing, and communication between the digital compute die and the rest of the system. This is one reason mature-node and specialty-node capacity remains important.

Not every device in an AI system belongs on the most advanced logic node. Many functions are better implemented on older, more stable, more cost-effective, or more specialized processes. AI infrastructure therefore depends on both leading-edge and non-leading-edge semiconductor manufacturing. The system is advanced because the pieces work together, not because every piece is manufactured on the smallest node.

3. Power semiconductor fabs: Energy delivery becomes a scaling limiter

AI systems are power-hungry. As accelerators, memory stacks, switch chips, and rack-level systems scale, power delivery becomes one of the central limits. This pulls power semiconductor fabs directly into the AI infrastructure discussion.

Power conversion, voltage regulation, current delivery, board-level power architecture, rack-level distribution, and data-center energy efficiency are now deeply connected to semiconductor scaling. Technologies such as silicon power devices, GaN, SiC, advanced voltage regulators, and power management ICs all become part of the AI hardware stack.

The challenge is not simply generating more compute. The challenge is delivering usable power to the compute fabric with acceptable loss, noise, heat, and reliability. This is where chiplet and package architecture become tightly coupled to power architecture.

The industry can no longer treat power delivery as a board-level afterthought. For high-current AI systems, power is a physical design problem across die, package, substrate, board, rack, and facility. A compute die may come from a leading-edge logic fab, but the system cannot scale unless the power ecosystem scales with it.

4. Compound semiconductor fabs: Efficiency, RF, and high-performance physical interfaces

Compound semiconductor technologies such as GaN, SiC, GaAs, and related material systems are also part of the broader AI infrastructure stack. They are important for high-efficiency power conversion, RF systems, high-frequency communication, and specialized physical interfaces. While they may not sit inside the main AI accelerator, they support the physical infrastructure around advanced compute.

This matters because AI systems are becoming more energy- and communication-limited. As data centers scale, the efficiency of power conversion, the quality of high-speed links, and the ability to move signals across packages, boards, racks, and facilities become increasingly important. Compound semiconductor devices can play a role in those parts of the system.

Again, this reinforces the broader point: AI infrastructure is not a single-fab product. It’s a convergence of many semiconductor technologies.

5. Photonics fabs: Data movement becomes optical

AI scaling is also stressing electrical interconnect. As systems grow from single accelerators to multi-chip modules, boards, racks, clusters, and data centers, data movement becomes a dominant challenge. Electrical I/O remains essential, but optical communication is becoming increasingly important for bandwidth, distance, energy efficiency, and system architecture.

This brings photonics fabs into the AI infrastructure stack. Silicon photonics, lasers, modulators, detectors, waveguides, optical transceivers, and eventually co-packaged optics (CPO) all represent a different manufacturing and integration ecosystem from conventional logic.

But photonic devices alone do not solve the problem. They must be connected to ICs, packaged with optical interfaces, aligned to fiber or waveguides, stabilized against temperature and mechanical stress, tested at the package level, and qualified for product deployment.

This is why CPO is not only a photonics problem; it’s a packaging, thermal, mechanical, electrical, optical, manufacturing, and reliability problem. A photonics fab can create the optical device. But AI infrastructure requires the optical path to become a stable product-scale system.

6. Mature-node fabs: The infrastructure control layer

Mature-node fabs are often underestimated in AI discussions. But AI infrastructure depends heavily on mature-node silicon for control, sensing, power management, monitoring, security, timing, industrial interfaces, and system management. Many of these functions do not require leading-edge process nodes. On the contrary, they may benefit from mature, robust, and well-characterized process manufacturing technologies.

The AI system may be marketed around the accelerator, but it operates through a large population of supporting devices. Controllers, power management ICs, sensors, retimers, interface chips, baseboard management devices, and other infrastructure ICs help keep the system functional, observable, and controllable.

Without this layer, the accelerator is only a powerful device without a complete operating environment. This is another reason the AI era should not be understood only through leading-edge logic capacity.

Advanced packaging as the convergence platform

If many fab ecosystems create the pieces, advanced packaging becomes one of the main places where those pieces converge. This is why CoWoS, CoWoP, chiplets, CPO, interposers, bridges, substrates, wafer-scale integration, and advanced package-to-board transitions are so important.

They are not just packaging formats; they are also physical convergence platforms. They bring together logic, memory, photonics, power delivery, substrates, interconnect, thermal paths, and mechanical constraints into one manufacturable system.

But that convergence is difficult because each technology arrives with different physical requirements:

• Logic needs dense routing and power delivery
• HBM needs high-bandwidth proximity and thermal control
• Photonics needs optical alignment and temperature stability
• Power devices need current handling and efficiency
• Analog interfaces need noise control and signal integrity
• Substrates need dimensional stability, low loss, and manufacturability
• Cooling systems need physical access to heat sources
• Test flows need visibility into the assembled system
• Reliability flows need confidence across materials and interfaces

This is why advanced packaging is not only “putting chips together.” It’s the physical realization layer of AI infrastructure.

Why “one fab” thinking is no longer enough

Traditional semiconductor conversations often separate the world into categories: logic, memory, analog, power, photonics, packaging, board, system. That separation is useful for organization. But it can hide the real scaling challenge: how AI infrastructure forces these domains to interact.

The logic die affects memory placement. Memory placement affects package size and thermal behavior. Thermal behavior affects power delivery. Power delivery affects substrate design. Substrate design affects signal integrity and manufacturability. Optical I/O affects package architecture. Package architecture affects test access, reliability, and yield.

The outcome is a coupled physical system. A limitation in one layer can become a bottleneck for the entire infrastructure platform. This is why the industry needs to think beyond individual fab outputs and toward a connected realization stack.

From device performance to physical realization

Device performance is still important. Material properties are still important. Transistor density is still important. But they are not sufficient by themselves. A material with excellent properties must still be processed, patterned, bonded, inspected, assembled, tested, and qualified.

A photonic device with strong lab performance must still survive package stress, temperature drift, fiber attach, calibration, and product reliability. A power device with high efficiency must still fit into a board, rack, or package-level power architecture. A high-density substrate must still meet warpage, routing, via, reliability, yield, and cost targets.

An AI accelerator with impressive compute density must still receive data, power, cooling, and system-level integration. This is the central shift: The next era of AI hardware will not be defined only by the best device. It will be defined by the best realized system.

The multi-fab physical realization stack

A more complete way to view AI infrastructure is as a multi-fab stack:

• Logic fabs create the compute engines
• Memory fabs create the bandwidth and capacity layer
• Analog and mixed-signal fabs create interfaces, control, and conversion
• Power semiconductor fabs support efficient energy delivery
• Compound semiconductor fabs enable high-efficiency power and high-frequency functions
• Photonics fabs enable optical data movement
• Mature-node fabs provide control, monitoring, and infrastructure silicon
• Packaging and OSAT flows bring heterogeneous devices into one manufacturable platform
• Substrate and materials ecosystems provide the physical foundation
• Thermal and cooling systems keep the infrastructure operational
• Test, reliability, and yield flows determine whether the system can scale

This is the AI physical realization stack. It’s broader than the accelerator, it’s broader than the package, and it’s broader than the fab.

AI infrastructure is a convergence problem

AI infrastructure is often described through the language of compute performance. But the real system is much larger. It’s a convergence problem across fabs, materials, packages, substrates, optics, power, cooling, manufacturing, test, reliability, and yield.

Leading-edge logic remains essential, but it’s only one layer. The AI accelerator becomes valuable when it’s connected to memory, powered efficiently, cooled effectively, packaged reliably, linked optically or electrically, controlled by supporting silicon, and manufactured at scale.

That’s why the next phase of AI hardware should be understood as a multi-fab physical realization stack.

• Different fabs
• Different materials
• Different devices
• Different process technologies
• One AI infrastructure system

The companies and ecosystems that win will not be those that optimize one layer in isolation. They will be those that connect many semiconductor technologies into reliable, manufacturable, and scalable infrastructure.

And for that, material properties are important, device performance is important, and packaging density is important. But physical realization is what makes them valuable.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Related Content

• True Wafer-Level Packaging
• Wafer Level Chip Size Package (WLCSP) Guidelines
• Intel’s Embarrassment of Riches: Advanced Packaging
• Nvidia, TSMC, and advanced packaging realignment in 2025
• Intel flash move could put wafer-level packages on the map

The post AI infrastructure is a multi-fab physical realization stack appeared first on EDN.

The global semiconductor industry is transitioning to the post-quantum cryptography (PQC) era. PQC is changing how digital systems defend against potential mathematical attacks. PQC algorithms are designed to protect against hackers who try to recover secret keys by breaking the underlying mathematics. However, physical hardware attacks can bypass mathematically secure algorithms, even if a PQC algorithm is perfectly implemented.

As organizations migrate to PQC, replacing the cryptographic assets being protected—PQC private keys, root keys, firmware signing keys—becomes costly and complex in deployed devices like automotive electronic control units (ECUs) and industrial or defense systems. When a chip processes post-quantum algorithms, it handles significantly larger key sizes and more complex mathematical operations than legacy cryptography.

This extended processing time and high computational intensity widen the vulnerability window, leaving the silicon exposed to physical tampering such as side-channel attacks (SCAs) and fault injection attacks (FIAs).

Mathematically upgrading to PQC only stops a hacker sitting at a quantum computer miles away. It does not stop a hacker from attempting physical attacks. This is where analog anti-tamper security IP comes into play. Analog sensors provide the first layer of defense to secure the silicon itself by detecting tampering techniques used in physical attacks, such as clock, voltage and temperature attacks, as well as electromagnetic and laser fault injection attacks.

Clock, voltage, and temperature attacks

A clock attack occurs when a hacker alters the incoming clock’s frequency or timing on a chip to cause glitches in an effort to interrupt normal operations and extract sensitive information. A clock attack monitor can be implemented to track the frequency and timing of the clock signal. If there is any unusual activity, an alert would be raised and preventive action taken.

A voltage glitch attack takes place when a hacker tries to tamper with the incoming power supply. Generating voltage drops or spikes can cause errors that impact encryption algorithms and bypass security procedures. A voltage glitch detector identifies when there is an unexpected change in voltage and sets off an alarm to reset or shutdown the system to protect against data loss.

A temperature or thermal attack involves a hacker quickly heating or cooling a device to generate timing or supply errors without having access to the clock signal or power supply. A temperature sensor can check for sudden temperature variations and then apply countermeasures if required.

Electromagnetic and laser fault injection attacks

An electromagnetic fault injection (EMFI) attack is when the hacker tampers with a device using an electromagnetic pulse, so no electrical contact or physical connection to the chip’s pins is required. An EMFI sensor can be integrated into the silicon to detect even small changes in the internal magnetic field on the device and respond swiftly to stop an attack from causing damage.

A laser fault injection (LFI) attack occurs when a laser beam is used by a hacker to induce errors to breach security and corrupt data. An LFI sensor is placed on a chip to monitor specific transient characteristics of a malicious laser pulse. If there are any indications of an attack, then the sensor can ensure that secret keys are erased or the device may be forced into lockdown mode.

PQC’s physical side

As PQC becomes more widely adopted, the frequency and complexity of physical hardware attacks are expected to rise. Whilst the latest cryptographic algorithms may resist quantum computers, hackers will continue to exploit physical vulnerabilities because without robust protection these are often easier than breaking the underlying mathematics.

This looks set to drive demand for analog anti-tamper IP that can detect clock, voltage, temperature, EMFI and LFI attacks, trigger responses such as key zeroization or secure reset if required, complement digital root of trust (RoT) solutions, and strengthen compliance with hardware security requirements in sectors such as automotive, industrial, financial and government.

Analog IP solutions offer a continuous line of defense, including clock, voltage, temperature and EMFI sensors, which complement digital RoT systems. As physical attack routes evolve, adding optical and LFI detection to the physical security envelope will become the benchmark for securing next-generation system-on-chips (SoCs).

While PQC addresses the security of cryptographic algorithms, analog anti-tamper IP protects the physical implementation of those algorithms. As organizations invest in PQC, safeguarding the hardware root of trust and stopping physical attacks becomes an even more critical part of a comprehensive security strategy.

Chris Morrison is VP of product marketing at Agile Analog.

Related Content

• Looming Quantum Threat as PQC Market Expands
• Post-quantum cryptography (PQC) knocks on MCU doors
• Post-Quantum Cryptography Incorporated into SoCs via eFPGA
• The need for post-quantum cryptography in the quantum decade
• Test and Measurement Strategies for QKD, PQC and Hybrid Systems

The post Why analog anti-tamper security IP is crucial in the PQC era appeared first on EDN.

Expensive shortwave radios include beat frequency oscillators, so why not also add one to an inexpensive radio version?

Broadcast shortwave (SW) radio use may be declining, but there are still lots of interesting signals to listen to between 1.6 and 30 MHz, such as amateur radio (Reference 1), pirate radio stations (Reference 2), aeronautical weather reports (Reference 3) and long-distance aircraft communications (Reference 4). Unfortunately most of these use Single Side Band (SSB) as opposed to the Amplitude Modulation (AM) used by broadcasters, which cannot be received on cheap domestic SW radios.

Wow the engineering world with your unique design: Design Ideas Submission Guide

AM consists of a radio frequency (RF) carrier wave (in red) which is partially modulated by the information – speech or music – (green), as shown in Figure 1a. The time domain signal in Figure 1a can alternatively be viewed in the frequency domain as in Figure 1b, where the carrier is surrounded by two smaller sidebands containing the information. A diode detector can demodulate this signal. In the time domain, the approach can be regarded as rectification with a low pass filter. In the frequency domain, the non-linear action of the diode mixes the carrier with the sidebands, therefore down-converting it back to an audio signal.

Figure 1 This sequence of images shows AM in the time  (a) and frequency domains (b), along with SSB in the frequency domain (c).

SSB lacks this carrier, with only one sideband as shown in Figure 1c. To demodulate SSB, an external carrier signal must be added; the resulting signal can then be demodulated with a diode detector like AM. This additional carrier is sometimes referred to as a Carrier Insertion Oscillator (CIO) or Beat Frequency Oscillator (BFO). Expensive SW radios include a BFO, so why not try and add one to a cheap one?

SSB demodulation

Many SW radios for SSB published in hobbyist magazines apply a high amplitude BFO signal to the input of the diode detector alongside the intermediate frequency (IF) signal, as shown in Figure 2a. The high BFO amplitude tends to overload any Automatic Gain Control (AGC) loop. Hence, in this type of receiver the AGC loop is disabled and the radio’s dynamic range is alternatively managed by manual RF and/or IF gain control.

Figure 2 These block diagrams show shortwave radios with BFO (a) and low-level BFO injection (b).

Adding a BFO to an existing radio in the way shown in Figure 2a would involve substantial modification to the radio to disable the AGC loop and integrate a manual RF gain control, if not already present. A second disadvantage with this technique is that because the IF signal has a large amplitude at the input of the detector, it can leak into the BFO and modulate it, therefore introducing distortion to the point of making the signal unintelligible.

The Eddystone EB35 radio from the late 1960s (Reference 5) overcame the leakage issue by injecting a low-amplitude BFO signal into the input of the IF amplifier chain. It does however still disable the AGC and instead rely on manual RF gain control.

Proposed here is a method of injecting the BFO at low amplitude into the input of the IF amplifier chain and controlling its level so as to best match the received signal when the existing AGC loop is operational, as shown in Figure 2b. The BFO with level control can be built into an external box with minimum modification, hence is easy to incorporate and then later remove from a valuable vintage radio receiver.

External BFO

The schematic of the BFO is shown in Figure 3. The oscillator is a Hartley type where a tap on transformer T1 provides the feedback. This is generally at 25% of the winding. T1 is a recycled IF transformer from an old transistor radio. Most low-cost radios like those shown in Figure 2 use an IF frequency between 455 and 470 kHz.

Figure 3 In this BFO schematic, VR1 is the pitch and VR2 is the level.

TR1 is a BC548 transistor, which although not known for its high frequency performance has sufficient gain at 455 kHz. The IF transformer includes a capacitor to set its operating frequency. To operate effectively as a BFO, the frequency needs are varied over a small range of a few kHz. This is achieved with a varactor diode D1, which here is half of a 1 A bridge rectifier (Reference 6) and controlled by VR1.

Level control is provided by VR2. The level of the carrier is reduced further by selecting a low values for C5 of 5pF. The values of C2 and C3 are not very critical, but past experience has shown that their optimum values are:

where fR is the operating frequency in MHz and C2 = C3 in pF. This is based on the optimum capacitor values for a Colpitts oscillator (Reference 7). The BFO is designed to run off 5V, so a voltage regulator (Reg1) is included. A 78L05 could be used, but in this application the radio used—a Realistic Patrolman SW60—had a 6 V supply, so a low-drop out K5050 regulator was used instead.

A photograph of the BFO built in a small plastic box and stuck to the back of the SW60 is shown in Figure 4. An additional hole is drilled in the box so that the core of T1 can be tuned. Although the SW60 is based on NPN transistors, it is a positive ground design, so the screen of the coaxial cable is connected to the input of Reg1 and the purple wire is ground. Another version was built for use with a WWII-era PCR radio where the cables passed through an unused headphone jack socket—requiring no modification to the case.

Figure 4 In this photograph of the BFO attached to the SW60, the top control is BFO level and off, the bottom is BFO pitch, and T1 is the metal can on the right.

Operation

When first used, the radio should be tuned between stations so only background white noise in heard. The BFO level control should be set to maximum. Doing this may cause a change in the sound of the noise. It is likely that the BFO will be operating outside of the IF bandwidth and will need to be tuning in.

Set the pitch control to approximately midpoint and with a trimmer tool, adjust the core of T1. As the BFO is tuned across the IF bandwidth, the general tone of the noise will drop and then increase on the other side. Generally, it should be adjusted so that the tone is at its lowest. Turning the pitch control should now cause the tone of the noise to rise on either side. At this point the level control can be backed off as it is probably driving the AGC loop. The optimum level control point is when the background noise is at maximum volume.

Tuning the radio to somewhere in the 7-7.3 MHz range in the late afternoon and evening should pull in stations in the 40-meter amateur band. If the signal sounds distorted, trying increasing the BFO level and the fidelity should improve. Adjusting the pitch control will of course affect the pitch of the received signal. When these two controls are correctly adjusted, the received signal fidelity is very good.

References

1. Amateur Radio bands: https://en.wikipedia.org/wiki/Amateur_radio_frequency_allocations
2. Shortwave Pirate Radio Stations: https://www.hfunderground.com/wiki/List_of_Pirate_Radio_Frequencies
3. VOLMET frequencies: https://dxinfocentre.com/volmet.htm
4. Aeronautical HF Radio: https://swling.com/blog/2015/09/aeronautical-hf-radio-map/
5. Eddystone EC10 Receiver: https://eddystoneusergroup.org.uk/Manuals/Eddystone%20EC10%20Manual.pdf
6. Rectifier diodes as varicaps (varactors): https://www.hanssummers.com/varicap/varicapdiode.html
7. NE602 Application note: https://www.scribd.com/document/46152488/Single-Chip-Frequency-Converter

Gavin Watkins is the founder of GapRF, a producer of online EDA tools focusing on the RF supply chain. When not doing that, he is happiest noodling around in his lab, working on audio electronics and RF projects, and restoring vintage equipment.

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The post Add-on beat frequency oscillator (BFO) for shortwave radio appeared first on EDN.

AI infrastructure is moving from server-scale acceleration to multi-rack supernodes that must behave like a single, highly available computer. Distributed optical circuit switching offers a practical way to extend scale-up fabrics with lower latency, lower power, flexible topology control, and limited disruption to existing data center architecture.

AI data centers are entering a phase where the hardest problem is not simply building a faster accelerator. It’s keeping thousands of accelerators fed, synchronized, and available as one machine. Training frontier models, serving long-context inference, and running agentic workloads all create a similar demand: more devices must communicate over longer distances without allowing the network to dominate cost, latency, power, or reliability.

That changes the definition of scale-up. It’s no longer only the set of links inside a server or rack. Increasingly, scale-up must span multiple racks while preserving the low-latency behavior programmers expect from a tightly coupled system.

Nvidia has framed the issue in similar terms, noting that as AI factories reach “extreme scale,” networking infrastructure “must be reinvented to keep pace.” The company’s recent silicon photonics announcements focus on exactly the metrics now becoming critical in AI infrastructure: power efficiency, signal integrity, resilience, and deployment speed.

That emphasis reflects a broader industry shift. The bottleneck is no longer just whether a link can move bits from one endpoint to another. It’s whether the entire fabric can support large, tightly synchronized accelerator domains while reducing power, limiting failure points, and remaining practical to deploy and service.

Copper has been the default for scale-up because it’s familiar, low latency, and economical at short reach, but physics is becoming less forgiving as per-lane data rates rise. Longer copper paths increase insertion loss and signal-integrity burden; thicker wires help the signal but work against density, airflow, and manufacturability.

Rack-scale cable trays become difficult to assemble and service, and a failure may require replacing large mechanical units rather than a small module. Retimers, equalization, and more complex board design can extend the life of copper, but they do not remove the underlying reach-density-power tradeoff.

Traditional pluggable optics solve part of this problem. They move data farther with less distance penalty than copper and are widely deployed in scale-out networks. But a scale-up fabric is different from a scale-out Ethernet fabric. Scale-up traffic often has stricter latency, synchronization, and collective-communication requirements, and in emerging architectures may carry memory-semantic traffic rather than ordinary packetized network traffic.

In that environment, the raw specifications of an optical link alone are not sufficient. The fabric also needs deterministic paths, fast reconfiguration, high serviceability, and smaller, more containable failure domains.

Figure 1 Next-generation scale-up and scale-out solutions extend the limits of traditional electrical interconnect and pluggable optical modules. Source: Lightelligence

Co-packaged optics (CPO) is an important long-term solution, but it’s not a simple drop-in replacement for today’s data center designs. Bringing optical engines into or near the package changes the thermal, packaging, manufacturing, serviceability, and qualification model. Recent industry discussions around CPO focus heavily on these operational issues: how to manufacture high-yield optical assemblies, make optical interfaces field-serviceable, and manage light sources and redundancy at scale.

Nvidia’s recent Spectrum-X Ethernet Photonics announcements also show where early CPO commercialization is gaining traction: scale-out and scale-across AI-factory networking. Scale-up CPO will follow, but it asks a different question: how do we preserve the behavior of a tightly coupled compute domain while changing the physical medium underneath it?

This is where distributed optical circuit switching, or dOCS, becomes important. Rather than concentrating the switching function in precious rack space, a dOCS architecture distributes compact silicon-photonic switching elements close to servers, GPU trays, or XPU clusters. This improves compute density by eliminating the switch chassis.

The goal is to keep data in the optical domain from port to port through the switch path, reducing unnecessary optical-electrical-optical conversions and avoiding the power and cost burden of very large centralized electrical switch ASICs. In practical terms, dOCS treats the scale-up network less like a fixed cable plant and more like a configurable optical fabric.

Figure 2 A distributed optical circuit switch (dOCS) integrates the optical interconnect and switching functions into one compact module. Source: Lightelligence

The distinction matters. A centralized switch can become expensive, power-intensive, and operationally painful as scale-up domains grow. It can also create a large failure domain. A distributed optical switch breaks the switching function into smaller modules, shrinking the blast radius of any one failure and enabling more granular service.

In one described implementation, the dOCS module integrates optical interconnect and optical circuit-switching functions in a compact module built around silicon photonics, controller, driver, and receiver circuitry. The architecture is intended to support millisecond-level failover, including substitution of a hot-standby GPU when a device fails.

For AI workloads, the value of that reconfigurability is not only resilience, it’s also topology control. Different phases of training and inference stress the fabric differently.

Dense all-reduce operations, mixture-of-experts routing, retrieval, key value (KV)-cache movement, and pipeline-parallel execution do not all benefit from the same topology. A circuit-switched optical layer can expose topologies such as ring, mesh, or dragonfly and allow the cluster manager to adjust the fabric according to specific workload-parallelism requirements.

Recent dOCS-based supernode work has described real-time topology reconfiguration and elastic expansion beyond 500 GPUs in a single logical domain. The broader architectural point is more important than the exact number: the network should become a schedulable resource, not a static constraint.

This also helps explain why dOCS is especially relevant to certain architectures. A supernode is not just a cluster with a marketing label. It is a tightly interconnected group of GPUs or other accelerators that attempts to behave like one large compute unit. In that context, effective model FLOPs utilization depends on how much time accelerators spend computing rather than waiting.

Optical scale-up links can extend reach across racks, while circuit switching can create predictable paths for high-volume collective traffic. The result is not simply more bandwidth on a datasheet; it’s a path to higher sustained utilization.

The same argument applies to memory. AI systems are increasingly constrained by memory capacity, memory bandwidth, and the location of memory relative to compute. High-bandwidth memory (HBM) on the accelerator remains essential, but it’s finite and expensive. Long-context inference and agentic workloads amplify the pressure by generating large KV caches and preserving more state across interactions.

CXL is important because it provides cache-coherent connectivity for processors, memory expansion, and accelerators, enabling resource sharing with lower software complexity. But coherent memory fabrics still need physical reach. Optical PCIe/CXL links and reconfigurable optical switching can help move memory from a stranded local resource toward a pooled resource available across boards, servers, and racks.

The practical advantage of dOCS is that it creates an intermediate deployment path. Data center operators do not need to redesign every server, change every protocol, or wait for full CPO maturity before gaining optical reach and switching flexibility in the scale-up domain. A dOCS-based fabric can be designed to remain protocol agnostic at the physical layer, supporting multiple higher-level fabrics while changing the transmission medium and switching mechanism underneath.

That matters because AI data centers are heterogeneous. They include GPUs, CPUs, XPUs, switches, storage, memory expansion devices, and management controllers sourced from multiple vendors and refreshed on different schedules.

Figure 3 As shown in this example, the dOCS architecture offers a practical advantage by creating an intermediate deployment path. Source: Lightelligence

A sensible roadmap is therefore not copper versus CPO, or pluggables versus CPO. It’s a staged migration. Linear pluggable optics can address immediate reach and power issues with limited architectural change. Distributed optical circuit switching can add fabric-level reconfiguration, availability, and scale-up reach.

Near-packaged optics can shorten electrical traces and improve density. CPO optics can eventually move optical I/O directly beside GPUs or switch ASICs for the highest bandwidth density and lowest electrical loss. Each step moves optics closer to the compute, but each step should also preserve serviceability and operational practicality.

The AI infrastructure industry is learning a familiar lesson from earlier computing transitions: the winning technology is rarely the one with the most elegant device physics alone. It’s the one that fits into systems, software, manufacturing, and operations at the right time.

The dOCS architecture fits that requirement because it attacks a real bottleneck now. It extends scale-up beyond the practical limits of copper, avoids inefficiencies of repeated electrical conversion, supports flexible accelerator-fabric topologies, and improves system uptime by localizing failures and rapidly rerouting traffic or switching to standby resources when hardware fails.

The future data center will almost certainly use several optical technologies at once: pluggable optics, linear drive optics, near-packaged optics, CPO, optical I/O chiplets, CXL-enabled memory fabrics, and optical circuit switches. The case for dOCS is that it gives operators a rapid-deploy scale-up option while the rest of the optical roadmap matures.

For AI infrastructure, that may be the most important kind of innovation: not a clean-sheet replacement for the data center, but a way to make the next supernode larger, more efficient, more available, and easier to deploy than the last one.

Maurice (Mo) Steinman is senior VP and U.S. GM at Lightelligence. He has enjoyed a 40-year career in the semiconductor industry, working for such companies as Digital, Compaq, HP, Intel and AMD, where he held the title of Senior Fellow before joining Lightelligence. Steinman has expertise in SoC architecture, SoC interconnect, memory subsystems, and energy management.

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• Overcoming interconnect obstacles with co-packaged optics (CPO)

The post Rapid scale-up in data center: The case for distributed optical circuit switching appeared first on EDN.

The automotive industry has undergone a major transformation, shifting from traditional hardware-centric vehicles to software-defined vehicles (SDVs). Unlike conventional cars, SDVs continuously evolve through over-the-air (OTA) updates, unlocking new features, optimizing performance, and enhancing safety over time.

While this shift continues to enable greater connectivity, automation, and personalization, it also expands the cybersecurity threat landscape. As SDVs integrate with cloud systems, mobile apps, and AI-driven features, they become more vulnerable to cyberattacks. Ensuring robust security frameworks is critical to unlocking the full potential of SDVs while safeguarding user safety and data privacy.

What makes SDVs unique?

At the heart of SDVs is a shift in computing architecture. Traditional vehicles relied on multiple fixed-function electronic control units, but as software complexity grows, automakers are shifting toward zonal architectures. By dividing vehicles into manageable zones powered by system-on-chips, manufacturers can streamline software updates, optimize performance, and future-proof vehicle systems against obsolescence.

However, this software-driven transformation also creates security challenges. The sheer scale of SDV software is unprecedented: Traditional vehicles already contain about 100 million lines of code, and as fully autonomous Level 5 driving emerges, this number is expected to surpass 1 billion lines. The growing attack surface demands a proactive cybersecurity strategy to prevent vulnerabilities from being exploited.

Automakers need to implement a multilayered defense strategy that encompasses multiple security measures across the entire ecosystem to build a secure SDV ecosystem. (Source: Adobe Stock) The expanding cybersecurity threat landscape

Unlike their predecessors, SDVs are no longer isolated machines. Instead, they function as interconnected platforms, continuously exchanging data with cloud networks, IoT devices, and other vehicles. While this level of interconnectivity unlocks powerful capabilities, it also increases exposure to cyberthreats.

Without strong encryption and data protection measures, cloud-connected vehicles risk having sensitive driver information compromised. AI-powered personal assistants and autonomous-driving systems must be designed with robust privacy safeguards to prevent unauthorized tracking or manipulation.

Compounding the risk is the lack of standardized security frameworks across the industry. While standardization efforts are advancing, every automaker develops proprietary software and interfaces, leading to inconsistencies in security implementations. These inconsistencies create opportunities for cybercriminals to exploit fragmented security protocols. A single vulnerability in one system could serve as an entry point for attackers to gain access to critical vehicle functions, jeopardizing both data privacy and operational safety.

Supply chain risks also contribute to the security dilemma. Modern vehicles rely on third-party software and hardware providers, each of which may introduce vulnerabilities that adversaries can exploit.

Furthermore, SDVs must support a mix of legacy and cutting-edge systems, making it difficult to implement uniform security measures across all components. The absence of an industry-wide security standard exacerbates these risks, as automakers struggle to balance innovation with the need for strong protections.

This growing digital ecosystem extends beyond the vehicle itself. Automakers now maintain ongoing digital relationships with drivers through software-based subscriptions and AI-powered enhancements, often leveraging mobile apps for remote vehicle control. While these applications provide convenience, allowing users to start their cars, unlock doors, or adjust vehicle settings from anywhere, they also introduce critical security vulnerabilities.

If mobile apps are not properly secured with strong authentication and robust software protections, cybercriminals could exploit weaknesses to hijack these functions, potentially gaining control over vehicles or tracking driver locations in real time.

Mobile apps also store personally identifiable information, such as driver profiles, payment details, and vehicle usage data, making them attractive targets for cybercriminals. This further increases the need for stronger authentication protocols, end-to-end encryption, and strict compliance with privacy regulations such as GDPR and CCPA.

Real-world incidents have already demonstrated the dangers of inadequate security. Just last year, researchers uncovered vulnerabilities in Subaru’s Starlink system that allowed remote attackers to unlock and start millions of vehicles, track their locations, and access extensive driving histories. While Subaru quickly patched the flaw, the incident highlighted the urgent need for automakers to adopt more comprehensive cybersecurity frameworks.

Building a secure SDV ecosystem

Securing SDVs goes beyond simply implementing technical solutions. It requires fostering a robust security culture within organizations, using certified solutions, and relying on independent third-party assessments to ensure compliance with ever-evolving industry standards. A fragmented approach to security can leave dangerous gaps that attackers are quick to exploit.

Security must be integrated from the ground up, beginning at the chip and silicon IP level to prevent hardware-based exploits. Adopting a bottom-up security architecture ensures that every layer, whether it be firmware, software, network communications, or cloud services, remains protected against potential cyberthreats.

To build a truly secure SDV ecosystem, automakers must implement a multilayered defense strategy that encompasses multiple security measures across the entire ecosystem. This strategy starts with hardware-based security, which prevents tampering at the chip level, ensuring that foundational components remain secure. From there, AI-driven threat detection becomes essential, as it enables vehicles to continuously monitor and respond to emerging cyberthreats in real time.

Equally crucial is the establishment of a secure cloud infrastructure. This includes implementing encrypted data storage, strict access controls, and continuous monitoring to safeguard against cloud-targeted attacks. Additionally, OTA updates must be encrypted to ensure that software changes are secure and tamper-proof, thus protecting against potential supply chain attacks.

Finally, securing access to the vehicle itself is paramount. Strong authentication and identity management systems must be in place to ensure that only authorized individuals can interact with critical functions, such as unlocking doors or tracking the vehicle’s location.

Creating a secure SDV ecosystem is a collaborative effort among engineers, security teams, and end users. Automakers must cultivate a security-first culture, ensuring that cybersecurity awareness is ingrained at every level of development. Teams must be trained to anticipate, detect, and respond to threats proactively and effectively.

The road ahead

SDVs represent a paradigm shift in the automotive industry, offering continuous improvements but also introducing security challenges. As AI, automation, and cloud connectivity become integral to modern mobility, cybersecurity will remain a priority for automakers.

Looking ahead, advancements such as quantum computing and the need for quantum-resistant cryptography will further reshape the cybersecurity landscape. To stay ahead of these developments, automakers must proactively strengthen security frameworks, embedding protection at every layer from silicon to software. By taking a proactive approach to cybersecurity, the industry can unlock the full potential of SDVs while ensuring safety, reliability, and trust in the vehicles of the future.

The post The security imperative for software-defined vehicles appeared first on EDN.

Two capsules. Two consequent pickup-pattern options. Three pickup-setting options. What’s not to like (aside, maybe, from the cosmetics)?

In November 2022, EDN published my introductory treatise on standalone microphones. At the time, I mentioned that two examples of the USB-interface Blue (now Logitech) Snowball microphone were (and had for some time been…since late 2007, my email archive informs me!) in my possession, one of them destined for teardown.

I subsequently also acquired two Snowball iCE mics, one of which I took apart, wrote about and EDN published back in May. The Snowball iCE, released a decade (2015) after its original Snowball sibling (2005), is a lower-cost (and -priced) single-capsule condenser variant of the original design, therefore supporting only a cardioid pickup pattern.

I’ve finally gotten around to actualizing the several-year-back initial aspiration to disassemble the original Snowball, with the fruits of my labors detailed today. As usual, I’ll start out with a set of outer box shots, in each case (along with other photos to follow) accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes.

Brace yourselves: here come the most existing ones of the lot (not).

Build quality upgrades

With that riveting visual intro out of the way, let’s see what’s within. Accessories include a USB-A to USB-B cable, akin to those commonly used with printers, this time microphone-destined.

And a three-legged stand, conceptually similar to—albeit this time more sturdily constructed than—the one included with its more economical Snowball iCE cohort.

Of course, there’s also our stand-disconnected dissection victim. Front.

Left side.

Back: visible is the USB-B male connector, handling both power (input) and digital audio data (output), and the three-position switch alluded to in the subhead. The switch settings reference the following functional options and other implementation nuances:

1. Position 1
   •    Setting: Cardioid (capsule)
   •    Applications: speech, vocals, and podcasting
   •    Picks up sound from the front, ideal for podcasting, game streaming, or recording vocals and instruments
2. Position 2
   •    Setting: Cardioid (capsule) with -10dB pad
   •    Applications: live music and loud sound sources
   •    Reduces mic sensitivity, so loud instruments or vocalists come in crystal clear and distortion free
3. Position 3
   •    Setting: Omnidirectional (capsule)
   •    Applications: conferences, interviews, and environmental recordings
   •    Picks up sound all around the mic, perfect for conference calls or recording a group of musicians

Onward. Right side.

Top, showcasing the pointed-forward power LED.

And bottom, with the vertical-swivel (45° tilt up and down) screw-hole connection to the earlier-seen stand.

Capsule counting

Now to get inside the mic itself. The procedure is exactly the same as for the Snowball iCE, which I’ve already textually and photographically documented in exhaustive detail back in May. So, I’ll back-reference you for the specifics versus doing a repeat performance. The only variance is that the shiny silver ring around the circumference is metal (with an adhesive backing) this time, versus just a sticker (another cost-reduction move that Blue-then-Logitech apparently made with the Snowball iCE).

Remove the black foam sheet from the front half.

And as before, you’ll see the connection to the power LED.

Now for the much more interesting (at least to me) back half.

Completely remove the four screws that originally held the two halves together:

And the guts detach from the back-half housing straightaway.

There’s a hefty metal plate in-between the multi-capsule assembly and the PCB.

See those three screw heads? You know what comes next.

Back in May, I mentioned a competitor-sourced controversy regarding just how many condenser pickup capsules the Snowball contained. But in revisiting the referenced October 2023 prior-coverage source, I realized that I hadn’t yet provided the associated visual evidence. The competitor was another USB-interface dual-pattern mic I’d disassembled, JLab’s Talk GO. And here’s the belated comparative graphic, presumably JLab-sourced, although published at the product page of a retail channel partner, Woot (where I’d bought mine).

I don’t know about you, but this sure looks like two condenser capsules inside the Snowball to me. Agree?

Now for the PCB, beginning with the comparatively boring front side that normally nestles up against the metal plate (but doesn’t actually touch it, which would short out those solder points, thanks to thin white plastic spacers that keep them apart).

Here’s the more intriguing, or at minimum, more populated backside:

You’ll see in a minute where the two grey multi-wire harnesses at top and left end up. You’ve already seen where the yellow-and-white one also at the top goes (the front/top power LED), as well as the two red-and-black ones (the two condenser pickup capsules). But what about the ICs in the middle? I thought you’d never ask.

The Snowball iCE’s dominant audio ADC-plus-USB interface device was C-Media Electronics’ CM6327A. This time it’s Micronas’ UAC 3556B, first publicly discussed more than a quarter century ago (!!!) and curiously positioned as “enabling Voice over Internet Protocol (VoIP) functionality, integrating an additional audio channel directly into existing USB keyboard architectures” (???).

It includes a two-channel ADC, although per the datasheet (PDF), only one of the two channels can optionally act as either an (electret) microphone or line input, with the other only supporting line levels. Presumably, the UAC 3556B also implements back panel switch position #2’s input attenuation function. The IC’s integrated DAC is seemingly unused.

Speaking of the back panel switch, and in closing, there’s this last shot.

Showing, as previously promised and after more black foam removal, where those two grey multi-wire harnesses end up at their other ends. And with that, I’ll wrap up for today. Share your thoughts in the comments, please!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Microphones: An abundance of options for capturing tones
• The Blue (now Logitech) Snowball iCE: This mic sounds nice
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The post Blue’s original Snowball: A multi-capsule sonic catch-all appeared first on EDN.

Engineers are redefining energy by looking not at massive grids but at the overlooked flows around us. Rain gutter generators that channel storm runoff, tap-mounted turbines spinning with household water, and balcony-scale wind turbines catching urban breezes prove that power can be harvested wherever motion exists.

These micro power generators embody the spirit of engineering empowerment, transforming ordinary infrastructure into sustainable energy assets. By designing systems that thrive on the smallest currents, engineers are not just solving technical challenges; they are enabling a future where autonomy, resilience, and sustainability are built into the everyday fabric of life.

Harnessing gravity: Micro hydro power

You don’t need a colossal dam to tap into hydroelectricity—gravity and flowing water are enough. Whenever water moves downward, whether from a rooftop gutter or a household faucet, it carries kinetic energy that can be captured and converted into usable current.

Micro hydro systems thrive on small vertical drops, known as “head,” which create surprising pressure even in everyday settings. A rain gutter turbine, often built around a miniature Pelton wheel, can be placed at the base of a downspout so that rainfall from a two-story home delivers enough head to charge an outdoor battery bank, turning stormwater into renewable energy storage.

Faucet hydros, on the other hand, are pocket-sized turbines that screw directly onto sinks or showerheads, producing between 5-V and 12-V DC—the perfect range for powering smart water temperature displays, LED bathroom lighting, or other low-voltage gadgets. Together, these simple setups prove that even the smallest streams of water can be harnessed to generate clean electricity, making hydro power accessible at the scale of everyday living.

Figure 1 Micro-hydroelectric power generators convert kinetic energy from small water streams into sustainable electrical power. Source: Author

Catching the breeze: Urban wind

Just as falling water can be harnessed for energy, moving air offers another everyday source of clean electricity. Standard windmills are massive, but compact vertical axis wind turbines (VAWTs) are reshaping the landscape for residential use. Unlike the towering three-blade giants on hillsides, these turbines resemble kinetic sculptures, blending into urban settings while quietly generating power.

Their design makes them safer for birds, more tolerant of turbulent wind bouncing off fences or house walls, and ideal for small spaces where airflow is unpredictable. With the ability to charge 12-V batteries, they provide reliable energy for garden sheds, security cameras, or other low-voltage systems, proving that even the breezes swirling through neighborhoods can be transformed into practical power.

Figure 2 Mini wind turbines harvest kinetic energy from turbulent urban breezes to provide localized renewable power. Source: Author

Harvesting the invisible: RF and Wi-Fi

If water and wind can be turned into electricity, why not the invisible waves that surround us every day? It may sound like science fiction, but it’s pure physics: electromagnetic energy from routers, cell towers, and radio stations constantly fills the air. RF energy harvesters capture this ambient power using a specialized antenna called a rectenna, which converts radio frequency signals into direct current. The output is small—usually measured in microwatts (𝜇𝑊)—but it’s enough to sustain ultra-low-power devices.

Imagine a moisture sensor in your garden that never needs a battery because it feeds on the Wi-Fi signal leaking from your window, or a network of “batteryless” sensors quietly monitoring conditions without ever needing replacement. By tapping into the invisible spectrum, RF harvesting extends the idea of micro power generation into the realm of everyday signals, proving that even the unseen can be harnessed for sustainable living.

Figure 3. The AEM30940 PMIC manages energy extraction from piezoelectric, micro-turbine, or high-frequency RF sources. It simultaneously charges a storage element while providing two independently regulated output voltages to power system components. Source: e-peas

Power from difference: Thermal energy

Just as water and wind can be harnessed for electricity, temperature itself can drive power generation through the Seebeck Effect. When one side of a material is hot and the other is cold, electrons begin to move, creating a voltage difference that can be captured as usable current.

This principle is already at work in stove-top generators found in many off-grid cabins, where a thermoelectric fan sits with its base on a hot wood stove and its top cooled by surrounding air. The temperature gradient produces enough electricity to spin the fan, circulating warmth throughout the room without external wiring.

On a smaller scale, wearable thermoelectric generators (TEGs) are emerging as a way to harvest body heat, powering fitness trackers and other low-power devices directly from the warmth of your skin. By turning everyday temperature differences into electricity, thermal energy harvesting extends the reach of micro power generation into both rustic cabins and modern wearables, proving that even the contrast between hot and cold can be transformed into sustainable current.

Figure 4 Stove-top thermoelectric generators convert waste heat into usable electricity. Source: TEG

Sunbeams to volts: The “magic” of micro-solar

At its heart, solar is the only micro-generator that feels like literal magic: it has zero moving parts, no loud turbines, and it runs on nothing but daylight. The fundamental “trick” is simply catching photons to knock electrons loose, creating a silent flow of power. Today, this technology is defined by “energy independence in a box,” where ultra-portable power stations—utilizing long-lasting LiFePO4 batteries and AI-driven energy management—allow anyone to build a personal power grid in minutes.

We’ve come a long way from the flimsy calculators of the 90s. From high-efficiency bifacial panels that harvest light from both sides to the emergence of perovskite-silicon tandem cells that pack 25% more power into the same small footprint, solar micro-generators provide a fuel-free alternative to traditional engines.

Whether it’s a balcony-mounted micro-inverter system or a foldable camping mat, solar is no longer just a “green” alternative; it’s the most reliable, scalable tool for decentralized power in our modern world. It’s basically like having a tiny, silent utility company that you can carry in your backpack.

Figure 5 N-type TOPCon dual-glass bifacial solar panels maximize energy harvesting by capturing incident sunlight on the front surface while simultaneously absorbing reflected light from the rear. Source: Author

Power of a pulse: Stepping into piezo power

While solar catches light, piezoelectric generators catch movement. The fundamental principle is almost toy-like in its simplicity: certain materials, like specialized ceramics or crystals, generate an electric spark when you squeeze or deform them.

In the world of micro-generation, this means turning everyday “wasted” energy—like the thud of a footstep, the vibration of a passing train, or even the pulse of a finger on a keyboard—into usable volts. Today’s technology has miniaturized this into “energy harvesting skin” and thin-film polymers that can be embedded into everything from smart sneakers to bridge supports.

Unlike solar, which needs the sun, or wind, which needs a breeze, piezo power only needs action. It’s the ultimate “hidden” generator, silently sipping energy from the vibrations of the world around us. While a single “squeeze” might only power a tiny sensor or a wireless signal, scaling this tech into “smart floors” or wearable fabrics is turning the human body and our infrastructure into a living, breathing power plant. It’s the fundamentals of physics turned into a literal “walk in the park” for renewable energy.

Figure 6 Cantilever piezoelectric harvesters convert mechanical strain from bending and vibrations into usable electrical energy. Source: Smart Material

Designing lean systems for ultra-low power

For engineers and makers, the frontier of micro power isn’t just about capturing energy; it’s about designing lean, ultra-low-power systems that thrive on the tiniest trickles of current. By leveraging efficient voltage regulators, sleep-mode microcontrollers, and energy-aware communication protocols, you can stretch microwatts into meaningful work.

Smart design tricks—like duty-cycling sensors, harvesting capacitors for short bursts, and matching generator output to the load—transform fragile prototypes into reliable systems. Today’s ecosystem of modular rectennas, plug-and-play thermoelectric modules, and ultra-low-power ICs makes experimentation easier than ever, giving designers the tools to tailor micro power generators for domains ranging from smart homes to wearables.

Power your world with micro generators

Today’s maker landscape is rich with possibilities: micro hydro turbines, mini vertical-axis wind kits, piezo energy harvesters, and even RF harvesting modules are widely available online, often bundled as DIY systems that simplify setup for hobbyists. Many components—Pelton wheels, turbine housings, and airflow vanes—can be 3D-printed from open-source designs, making customization affordable and accessible.

Dedicated ICs such as ultra-low-power boost converters, energy harvesting PMICs, and rectifier-regulator modules are designed to stabilize and store trickle currents, while plug-and-play thermoelectric generators extend experimentation into thermal domains. With kits, printable parts, and specialized electronics at hand, building micro power generators across water, wind, signal, heat, light, and vibration/impact sources has become a practical weekend project rather than a distant engineering challenge.

The possibilities are here and the tools are ready—so why wait? Shock your imagination, spark your designs, and start building micro power generators that turn everyday forces into lasting energy solutions.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Micro power generators: Turning everyday flows into energy appeared first on EDN.

The market for commercial autonomous vehicles (AVs) is poised for explosive growth over the coming decade, and 4D imaging radar has a key part to play. 4D radar, which offers a 4D view combining distance, velocity, position, and vertical resolution, will help AV companies deploy autonomous fleets in real-world environments faster while also building the potential to scale such deployments rapidly.

The autonomous truck market alone is set to rocket from $50.8 billion this year to $158.7 billion in 2035, at a compound annual growth rate of 13.5%, according to a research report by MarketsandMarkets. With technology the key driver of growth, according to the researcher, the adoption of advanced sensors such as 4D radar, alongside high-performance computing platforms and AI-based software, is vital to this expansion.

However, one of the key challenges facing the sector is that 4D radar solutions have, until now, tended to operate as closed systems, meaning that access to the raw data is limited. Newer systems, such as bitsensing’s AIR4D imaging radar, will help enable developers and AV companies to continuously refine vehicles’ perception models and validate their performance.

In turn, this will accelerate the path from testing new systems to safe and large-scale deployment in real-world fleets. This will drastically speed up the commercialization of AVs worldwide.

In contrast to sensors such as LiDAR and camera sensors, radar offers key advantages that will be vital to driving real-world use in the commercial vehicle sector. It is safe, cost-effective, and proven, and it is already widely incorporated into advanced driver-assistance systems (ADAS) to offer the velocity accuracy needed for ADAS functions such as automatic emergency braking. This is a well-known technology and already evolving into more advanced 4D systems, suited for commercial vehicles.

Radar systems work in all weather conditions (cameras, for example, struggle in fog and low-light conditions as well as over longer ranges). The latest radar systems work comfortably at ranges of more than 200 meters and have low power consumption. The technology can easily be integrated into vehicle systems, with manufacturers already building systems designed specifically for the commercial AV market.

4D radar delivers high-resolution, real-time environmental mapping and integrates with cameras to deliver a comprehensive perception system. (Source: Adobe Stock) The 4D advantage

The reason 4D radar is so important for the rapid commercialization of AV technology is that it enables the rapid classification of different kinds of road users (for instance, pedestrians, buses, and cars). This will play an important role in enabling trucks, buses, and robotaxis to move safely through city streets, whether in Level 2 or 3 autonomy (where driving is conditionally automated) and moving toward Level 4 autonomy (where driving is highly automated, with vehicles capable of driving fully autonomously in real-world settings without the assistance of a human driver).

The reason 4D radar is so powerful is that it instantly senses distance, velocity, and position, along with vertical resolution. This means that anything “seen” by the vehicle has not only movement but also shape and altitude. This allows vehicle systems to sense how quickly an object is moving and rapidly categorize it as a certain class of vehicle, such as a motorbike or truck, or a pedestrian.

The rapid adoption of 4D radar will be a key growth driver in commercial AVs. Today, some robotaxis already ship with more than 20 advanced 4D sensors, and this will become a key trend across the market for commercial vehicles. Analysis by ResearchAndMarkets found that 169 million radar sensors shipped globally in 2024, translating into 0.8 long-range radars per vehicle and rising to one per vehicle by 2030.

The adoption of regional regulatory mandates (such as the EU’s Vehicle General Safety Regulations) is also helping to accelerate the growth of commercial AVs. The latest radar sensors offer both horizontal and vertical resolution, enhancing obstacle-detection and collision-avoidance capabilities. This means they can cope with any road conditions and any weather conditions, complying with the new regulations.

Built for commercial vehicles

To really drive the commercial AV market forward, it’s also vital that sensors are purposely designed for full autonomy, rather than being repurposed from devices for the consumer market. Today, many 4D radars were developed for use in ADAS, rather than being built from the ground up for full driverless functionality.

To truly deliver the information that AVs need, these systems should be optimized to deliver 4D sensor data directly to the AI models in these vehicles. They should also be optimized for power and heat efficiency. These features will be vital for real-world operation.

Going forward, a camera-plus-radar architecture will also be crucial to offering a viable path to curbing per-vehicle sensor costs. This will help to drive faster AV deployment on roads around the world. These are some of the design factors that we have also considered with our own work, including with the AIR4D imaging radar.

The AIR4D imaging radar is purpose-built for AVs, which is critical for full autonomy. (Source: bitsensing Inc.) Increasing accuracy

The latest radar sensors build on the strengths of the technology to offer higher performance than rival sensors, such as LiDAR and cameras, with long-range detection up to 300 meters and the ability to operate in near-total darkness. This allows commercial vehicles to maintain awareness even on poorly lit roads in the middle of the night.

The ability to measure direct velocity per object is also helping to enable faster and more accurate decision-making, with the latest radar sensors able to measure the speed and direction of vehicles, cyclists, and pedestrians in real time. This means that radar alone can provide full spatial accuracy. With previous generations of 3D radars, other sensors were relied on to create a “full” image of the objects moving in the surrounding environment.

Today, AVs equipped with 4D radar can build a high-resolution, real-time spatial picture of their environment across all four dimensions. This is what safe autonomous driving demands. With 4D radars penetrating even snow and rain and able to integrate with cameras, radar is the foundation of a comprehensive perception system, which will be the building block of autonomous driving.

Toward safer bus fleets

There are many factors that make radar sensors appealing in a commercial context, especially the “weather-proof” nature of the technology. Commercial fleets, such as the use case of buses in Korea, are already adopting radar-based technology through initial pilot schemes, with further plans to expand fully to intercity bus routes.

Critically, these ADASes have modularity at their heart, with features that can be easily added to existing vehicles. These functions, such as forward-collision warning, enable buses to precisely detect vehicles and pedestrians, even in the most demanding environments or roads.

A 4D future

The dawn of the commercial AV era is upon us today, and to drive forward into this future, it’s clear that 4D imaging radar has a vital role to play. Not only will 4D radar help to overcome the limitations of previous sensors, such as LiDAR and cameras, but it also transcends the limitations of previous radar systems, with the latest sensors purpose-built for seamless integration into the fleets of tomorrow.

The post Why 4D imaging radar is critical to AV commercialization appeared first on EDN.

Have you heard of the golden ratio? Well, what about the gold-colored guitar fret ratio?

I’ve been listening lately to classical guitar musicians on YouTube. Such skill and artistry is utterly astonishing. After a while, though, I got curious about how the guitars were made and how they achieved their frequency outputs. I noticed something. I took a screen shot of a guitar’s strings and fretboard and, by counting pixels, I measured the dimensions seen in Figure 1:

Figure 1 Guitar fret positioning is definitely not random, acoustically speaking.

I then looked at the ratios of a string’s fret-to-base length (my choice of term) to that of the next shorter one (Figure 2):

Figure 2 Length ratios: the ratio of each fret position taken in pixels divided by that of the next fret closer to the base is the ratio of the frequencies of each note of the string. That ratio is nominally 2^(1/12) =1.05946… which is approximated in each and every case. The average of the calculations as shown here comes to 1.058422 which is only 0.1% in nominal error.

I discovered that in spite of my crudeness in using the pixels, the ratios come out very close to the twelfth root of two. That ratio is the ratio of adjacent note frequencies of a tempered musical scale. If the full length of a string is taken as “Do” in its particular key, the fret positions yield the twelve-tone-scale arrangement of notes seen in Figure 3. In hindsight, I guess I should have intuitively known this but I didn’t. I do now.

Figure 3 Tempered scale: taking the full length of each string as the note “Do” as in Do-Re-Mi-Fa-Sol-La-Ti-Do scaling, we see how each fret position corresponds to one of the twelve notes (including sharps and flats) of the Western culture’s twelve-tone scale.

It should be noted that singer Jimmie Rodgers once admitted that he couldn’t really play the guitar as he performed, so he tuned the six strings of his guitar to be in open string harmony. Then when he was performing, he would keep one finger, his thumb, across all six strings at the same time across the fretboard. Since all six strings followed the above length versus note pattern, the six strings were always in harmony. He was using a single, movable chord.

Watch how his left hand does that in the following YouTube videos and enjoy the music.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Earplugs ready? Let’s make some noise!
• A pitch-linear VCO, part 1: Getting it going
• A pitch-linear VCO, part 2: taking it further

The post Guitar Frets appeared first on EDN.

Part 2 of this series covered the user-space tooling stack—cxl, ndctl, daxctl, numactl, lspci, and setpci—and walked the boot path from power-on through DRAM training, DVSEC and HDM reporting, decode programming, CDAT delivery, ACPI table handoff, and OS driver binding. It framed each stage as a validation gate so you can tell whether a failure is rooted in link training, capacity reporting, firmware tables, or policy—not only in application behavior.

Part 3 turns that framework into hands-on practice. You will learn how CXL memory may surface as system RAM or Device DAX, when to use daxctl and boot parameters such as efi=nosoftreserve, how to confirm expander memory as a distinct NUMA node, how to decode key lspci fields for link health and CXL.mem enablement, and how to drive targeted traffic with numactl and standard stress tools. So, you can separate transport defects from NUMA misconfiguration before closing bring-up or sign-off on CXL Type 3 device validation.

Integration modes: System RAM and Device DAX

CXL Type 3 host-managed memory may integrate in more than one way. The platform and kernel can expose it as conventional system RAM, or as persistent-memory-class capacity that surfaces as Device DAX character devices (for example /dev/dax0.0). The daxctl utility and libdaxctl can reconfigure those DAX instances; for example, switching a region to system-RAM mode so the same physical capacity behaves like normal DRAM instead of a raw DAX mapping, subject to firmware and driver support.

To reconfigure a device that appears as /dev/daxX.Y to system RAM:

sudo daxctl reconfigure-device –mode=system-ram daxX.Y

Firmware can mark some memory ranges in the system map as EFI “soft reserved.” Think of that map as the machine’s inventory of RAM, soft-reserved means, “this range exists, but do not treat it as ordinary free RAM yet.”

That pattern is common when capacity comes from persistent memory (PMEM) or CXL Type 3 expanders, because the platform often wants the OS to decide later whether that capacity should behave like normal DRAM or be exposed as a Device DAX mapping (a special character device such as/dev/dax0.0). By default, Linux honors those soft reservations, which leaves the memory set aside instead of freely handing it to applications as regular RAM.

The boot parameter efi=nosoftreserve changes that policy. It tells the kernel: do not keep soft-reserved areas reserved so the OS can bring that capacity online in the mode operators want (typically system RAM) when the firmware’s soft-reserve marking does not match the deployment goal.

Use efi=nosoftreserve only when your platform vendor or bring-up guidance says it’s appropriate. Applied without that context, it can change how capacity appears (RAM vs DAX), affect NUMA topology, and complicate debugging when firmware and OS expectations disagree.

Verifying NUMA topology

Use numactl to confirm the expander enumerates as its own NUMA node:

numactl -H

Figure 1 Sample numactl -H output on a two-socket system with 2 CXL devices, where each CPU is a NUMA node with native DRAM. Node 0 and node 1 show socket-local DRAM and the CXL devices appear as node 2 and node 3 with 128 GB of memory (each) and no local CPUs. This memory-only NUMA node pattern is common for Type 3 expanders and is the baseline for placement-aware testing. Source: Author

Initial sanity checks with lspci

lspci shows whether the CXL endpoint is present and reports vendor/device ID, class codes, PCIe link width and speed, and related DVSEC register status. It’s a fast first check before chasing firmware decode, driver bind, or memory-onlining issues.

lspci | grep -i cxl

lspci -s <BDF> -vvvv

Decoding key lspci fields

Device link width and speed

LnkCap and LnkSta should match expectations (for example speed 32GT/s, width x16). Unexpected degradation signals an unstable link and issues at the electrical layer. This must be resolved before proceeding further.

Figure 2 lspci output showing the negotiated PCIe link speed and width for a CXL Type 3 endpoint. Source: Author

CXL capabilities and status

CXL DVSEC blocks use Vendor ID 0x1E98 and a DVSEC ID identifying the structure type. A healthy device advertises both CXL.io and CXL.mem under CXLCap/CXLCtl. If CXL.mem is disabled (CXLCtl Mem-), possible causes include DRAM enumeration failure or the host failing to assign address space. HDMCount 0 is a red flag. When memory enumeration fails, verify DIMM compatibility and mounting, and use vendor SDKs to probe internal controller registers via out-of-band access where available.

Figure 3 CXL DVSEC capability and control fields showing CXL.io and CXL.mem enablement, HDM decoder configuration, and active memory ranges. Source: Author

Address range and Active bit

Device firmware can be set up to include the entire HDM in one range or split it into two. The range fields reflect the size and which range is active. Range fields should translate to the full HDM size with Valid+ and Active+ set. Otherwise, it indicates that DDR negotiation or mapping failed. For initial bring-up, set the decoder and mailbox timeout values to their maximum supported settings to avoid premature failures during DDR negotiation.

Driver and kernel modules

Kernel driver in use should be cxl_pci. To verify kernel version, kernel 6.3 and above are recommended. During link stability testing, unlink drivers as required by your test procedure.

The cxl CLI tool for CXL memory expander bring-up

The cxl command-line utility is the user-space front-end to libcxl, shipped with the ndctl project on most Linux distributions. It walks the kernel CXL sysfs hierarchy, which includes buses, ports, endpoints, memdevs, decoders, and regions and prints structured as JSON output.

It complements lspci, which shows transport and DVSEC state at the PCI layer, and daxctl or numactl, which show how onlined memory capacity is exposed to applications. Reach for cxl after dmesg if the firmware, CXL driver, and user-visible memory policy do not agree.

What cxl exposes

At a high level, cxl list reports the objects the Linux CXL core registers under /sys/bus/cxl/devices/; root buses, switch and root ports, endpoints tied to PCI functions, memory devices (mem0, mem1, …), host-managed device memory decoders, and regions that may span one or more expanders. For single-LD Type 3 cards, the first sanity check is usually whether a memdev appears with a non-zero ram_size, a host BDF, and decoders or regions in a committed decode_state after platform firmware has programmed HDM and asserted mem_enable.

Essential commands during bring-up and sanity testing

Initial discovery

Run these early in bring-up to confirm the kernel bound cxl_pci and registered at least one memdev:

cxl list -M

cxl list -M -u

Look for memdev entries with ram_size, serial, host (PCI BDF), and numa_node when memory is onlined. An empty list or zero-sized memdev often means the device is present on the bus but not yet consumable—trace back to HDM validity, decode programming, or driver bind before chasing application issues.

Topology and decoder verification

After link-up and driver bind, verify the decode path from root port through endpoint decoders:

cxl list -vvu

cxl list -D -d endpoint -u

cxl list -P -p switch,endpoint -m memX -u

Use -vvu for buses, ports, decoders, regions, and target mapping in one view. Filter by memX or by PCI BDF (cxl list -M -m 0000:bb:dd.f) when multiple expanders or a switch is present. Decoder listings should show plausible Host Physical Address (HPA) windows and a committed state before you treat CXL-attached DRAM as usable system memory.

Region and exposure mode checks

When the platform surfaces expander memory through a CXL region and DAX subsystem, confirm how capacity is configured before running daxctl or numactl tests:

cxl list -R -RXu

cxl list -r regionN -RXu

The daxregion section reports chardev names (for example dax0.0), mode (devdax versus system-ram), and memblock onlining progress. This tells you whether the next step is daxctl reconfigure-device, memory hotplug onlining, or NUMA verification with numactl -H.

Enable, disable, and health

Type 3 expanders usually auto-enable by default. These commands matter after manual disable, hot-reset recovery, or scripted regression gates:

cxl enable-memdev mem0

cxl disable-memdev mem0

cxl list -m mem0 -H -u

enable-memdev revalidates HDM decoders and CXL.mem enablement along the port hierarchy. The -H health listing exposes maintenance, media, and error counters when the device supports mailbox health reporting—useful during long stress runs alongside dmesg and RAS logs.

Suggested bring-up command sequence

A practical first-pass sanity script on a booting system:

lspci | grep -i cxl

lspci -s <BDF> -vvvv

cxl list -M -u

cxl list -vvu

cxl list -R -RXu

cxl list -m mem0 -H -u

numactl -H

Together, these commands separate device not seen (lspci) with details of DVSEC that can be parsed for information of interest, device seen but not registered (no memdev in cxl list), decode not committed (decoders/regions), and memory online but misconfigured (numactl shows wrong node or missing capacity). That layering matches the validation mindset used throughout the “Bring-up and testing of systems with CXL Type 3 memory expanders” series.

Keeping kernel pages off CXL memory

CXL expander memory should be treated as a migratable capacity tier, not as interchangeable DRAM. Slab caches, page tables, and other non-migratable kernel structures must stay on local socket memory because they cannot be demoted or migrated and would suffer higher latency and reliability risk on CXL.

Online CXL capacity in ZONE_MOVABLE

The primary remedy is to defer CXL expander capacity only into ZONE_MOVABLE on a discrete, CPU-less NUMA node. After confirming the device with cxl list and daxctl list, reconfigure it as system RAM with the default movable policy as we saw previously.

sudo daxctl reconfigure-device –mode=system-ram daxX.Y

daxctl onlines new blocks as movable by default; avoid –no-movable. Only move blocks assigned to CXL memory to ZONE_MOVABLE. This must be done carefully; determine the NUMA node assigned to a CXL device, use the sysfs interface, /sys/devices/system/node/node2/memory*, to determine which blocks are assigned to the CXL memory and only apply the ZONE_MOVABLE attribute to those blocks by looping over the respective CXL nodes. It’s important to note that CXL memory range onlined in ZONE_MOVABLE is not eligible for 1-GB Gigantic Page allocation.

Page temperature and tiered memory placement on CXL systems

Hot, warm, and cold pages

In CXL-enabled tiered memory systems, pages are commonly classified by access frequency over a sliding time window rather than by a fixed label. Hot pages are touched often enough to affect performance while cold pages are allocated but remain idle for minutes or longer.

Production studies report that a large share of allocated memory, often well over half, can be cold in short windows. Warm pages sit between those extremes: accessed occasionally or likely to be re-accessed soon, so they tolerate slower tiers better than hot data, but still benefit from promotion if they heat up.

TPP further notes that page type matters. Anonymous heap and stack pages tend to run hotter than file-backed cache and tmpfs, and temperature can flip quickly as pages are allocated and freed, so static placement fails.

Why page placement is critical

CXL expander memory is reachable with byte-addressable semantics but at higher latency and often lower effective bandwidth than socket-local DRAM. If the OS treats all NUMA nodes as equivalent, hot working sets can land on CXL, new allocations compete with cold data for fast DRAM, and capacity-bound workloads that should tolerate tiering still lose double-digit performance.

TPP reports up to roughly 18% performance improvement over default NUMA balancing on CXL-tiered platforms, and production analyses show sharp latency-sensitivity once the hot footprint exceeds what local DRAM can hold.

For CXL Type 3 bring-up, correctness may pass with memory online, but performance sign-off requires verifying not only that CXL capacity exists, but that hot, warm, and cold pages are landing on the intended tiers under the policies that the user fleet actually runs.

Default Linux policies

Default policies start simple: allocate preferentially from local DRAM and spill to the CXL NUMA node only when fast-tier capacity is exhausted. The kernel’s NUMA balancing (numa_balancing) enables and configures automatic, page-fault–based balancing. Setting it to NUMA_BALANCING_MEMORY_TIERING (value 2) tells the kernel to treat the NUMA nodes as tiers and promote frequently accessed (“hot”) pages into the fast tier.

echo 2 > /proc/sys/kernel/numa_balancing

Memory-tier demotion (numa_demotion_enabled) under reclaim pressure moves cold pages to the slow tier instead of swapping them to disk.

echo 1 > /sys/kernel/mm/numa/demotion_enabled

Zone reclaim mode is a Linux kernel parameter that controls how aggressively the system reclaims memory from a local NUMA node when that specific node runs out of memory, rather than allocating memory from other remote nodes. It accepts one of the specified policies or a combination. Typical production knob will enable all reclaim policies.

echo 7 > /proc/sys/vm/zone_reclaim_mode

The above setting should not be used in all conditions. It’s highly recommended that the user try combinations of the above settings with benchmarks that closely resemble the workloads and use the combination that works best.

Tools for traffic generation and performance validation

While a detailed discussion of each benchmark and the traffic type deserve a separate discussion, some common benchmarks and tools are mentioned below that should help the reader get started.

Memory structural test

Memtester

Latency

Intel Memory Latency Checker (MLC) for x86 platforms

Bandwidth

Google Stressful Application Test (SAT/GSAT/stressapptest)

Google Multichase – pointer chasing benchmark

TPCH with DuckDB

Heimdall

When expander memory appears as its own NUMA node, numactl+membind forces traffic onto CXL-attached DRAM.

numactl –cpubind=0-15 –membind=2 <command to run memory traffic>

The example below runs on node 0 CPUs but allocates memory on node 2. CXL memory (see Part 1, Figure 2); swapping –membind between 0 and 2 gives a direct local-DRAM versus CXL comparison. On single-socket systems, the CXL device may enumerate as NUMA node 1.

Matching CXL link width to memory bandwidth

When sizing a CXL memory expander, usable bandwidth is not simply the PCIe/CXL rate on the connector. Traffic crosses two stages: the host-facing PCIe/CXL link and the DDR channels behind the Type 3 controller. End-to-end bandwidth is therefore the lesser of the two.

Effective Bandwidth = min(PCIe/CXL link bandwidth, DDR bandwidth behind CXL)

Recycled DDR4 is often slower, or with fewer active channels than native DDR5. Subsequently, the DRAM side can limit throughput before a full-width link saturates. In that case, a x16 link may not add much, and an x8 (or narrower) link can already match what DDR4 sustains. This frees up lanes, cutting expander cost and power, and leaving host I/O for GPUs, NICs, and other devices. Size the link to the slower of the two bandwidths, not to the maximum PCIe generation width.

A cross-layer validation mindset

CXL Type 3 memory expanders offer a practical way to grow capacity and effective memory bandwidth for data- and memory-intensive workloads where traditional DDR scaling is constrained by I/O, cost, and signal integrity. But successful deployment is not only a silicon or link problem.

Host-visible expander memory remains physically and administratively distinct from socket-local DRAM, so discovery, NUMA topology, performance, and RAS must be validated as a cross-layer problem spanning CPU, firmware, kernel parameters, device firmware, and user-space policy.

This three-part series outlined system context and platform prerequisites; the boot timeline from power through DVSEC, decode/mem_enable, CDAT/DOE, ACPI tables, and driver attach; and user-space tooling plus transport-level checks for CXL.mem enablement and HDM validation.

Future work includes switched and multi-device topologies, CXL 3.x pooling models, formal compliance automation, and standardized regression coupling protocol evidence with OS topology and workload QoS.

Acknowledgment

The author thanks Linux CXL kernel developers (the detailed notes and exchanges in lwn.net are extremely valuable), the open-source CXL community, the CXL Consortium, and platform engineers at CXL memory expander vendors and hyperscalers. Any errors remain the author’s own.

Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).

Editor’s Note

The views and content of the article are the author’s own and not affiliated to any of his current or previous employers.

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• CXL Adds Port Bundling to Quench AI Thirst
• CXL: The key to memory capacity in next-gen data centers
• From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)

The post Test, debug, and validation of CXL memory expanders appeared first on EDN.

Yours truly can’t try to do the splits without ending up in the hospital, and suspects many of you would find the maneuver equally complicated-to-impossible…as does, it turns out, USB.

In last week’s initial post of this series, I discussed ongoing imperfections in the latest-generation USB-C standard, specifically with respect to single-source-to-sink interconnect, and encompassing power transfer, data interchange, and both-simultaneously setups.

• Nebulous-at-best identified cable capabilities and their user impacts
• Polarity dependencies on resultant performance
• The broader pros and cons of an industry standard which encourages compliance but doesn’t require independently assessed compatibility

In doing so, I was following up on other points already raised in my prior coverage, based on multiple case studies personally experienced by me.

• USB: Deciphering the signaling, connector, and power delivery differences
• USB Power Delivery: incompatibility-derived foibles and failures
• USB 3: How did it end up being so messy?

That includes the necessity for “sink” devices using USB-C for power-input purposes (including charging of embedded batteries) to connect solely to power sources via USB-A-to-USB-C adapter cables, versus newer and more logical dual-ended USB-C alternatives, in order to achieve proper-operation outcomes. Such workarounds presumably result from subpar USB Power Delivery (USB-PD) implementations.

At the conclusion of that prior post, I wrote:

I’ve got one more notable USB-C-related implementation-challenge situation to discuss, but after just passing through 2,000 words, I’m going to save it for next week’s part-two post.

Background to my curiosity

That’s where today’s follow-up blog comes in. Specifically, if you haven’t already figured it out from the title and subhead, I’m going to cover splitters, which assist in interconnecting a single source with multiple “sinks”, again with power, data, or both transfer aspirations.

My main impetus for recent interest in the topic is the portable power stations from EcoFlow and others that I’ve been acquiring, using, testing, and writing about of late. Take, for example, the EcoFlow RIVER 2 that I first covered in detail in February 2025.

It has only two USB-A power outputs, both 12 W max (industry-standard 5V@2.4A, absent any proprietary QC enhancements). And although its USB-C facilities are USB-PD cognizant (5/9/12/15/20V@3A, 60 W max), there’s only one of them. So, if my wife and I both want to fast-recharge our smartphones via USB-C during an extended power outage, for example, how might we be able to accomplish this without arm-wrestling or a shouting match? With a splitter, of course.

Here’s one example of the concept, an early “category creator” market entrant, Anker’s 140W 2-in-1 USB-C to USB-C cable.

We’ll revisit it later in this piece. It comes in 4’ and 6’ length options and black and white color variants and is analyzed in detail in this Reddit thread and linked teardown.

Proportional power allocation (or not)

Back in prior-generation USB days, specifically for power splitting purposes, the implementation and usage were reasonably straightforward. The only source output voltage option was 5 V. The output current was whatever the source max’d out at. And the parallel-connected “sinks” consumed whatever subset of the available electrons each of them could successfully allocate to itself.

The only notable issues (unless I’m overlooking something; readers, let me know in the comments) with this elementary implementation were practical:

• Each “sink” device might recharge slower than if it had the source all to itself.
• Some of the “sinks” might not work reliably because their available allocated percentage of the current was insufficient for requisite power and/or recharge purposes.
• Others might not work because they required a voltage higher than 5 V (Apple laptops, for example, something I learned while researching adapters for part 1 of this series).
• And in the opposite-trend direction, if the source was subpar in its design, the high aggregate “sink” current demand might result in excessive output voltage drop sufficient to take all connected power destinations offline.

With USB-C (specifically, USB-PD), things unsurprisingly have gotten a “bit” more complicated. As my colleague Bill Schweber noted in his recent treatise on the topic, “USB-PD allows for multiple loads to be charged at the same time, each with different requirements”. And of course he’s right. But, then again, only with a properly implemented USB-PD ecosystem.

To wit, I’ve also come across plenty of case study examples on Reddit and elsewhere detailing situations, both hypothetical in their proposed root causes and confirmed by postmortem analysis, wherein someone plugged a laptop into one output of a splitter followed by a mouse, keyboard or some other more elementary device into the other output, a second device which (incorrectly) was then also subjected to the first device’s required high voltage and promptly emitted “magic smoke”, followed by demise.

So, what’s a splitter supplier to do? (At least) three options exist, as I see it:

• Bail on USB-PD and power everything by 5V@3A only (with already-discussed consequent potential functional issues).
• Negotiate with every connect device and run ‘em all at the lowest voltage that they all have in common. Safe? Sure. But also functional interruption-prone with every splitter output-tethered device connection and removal. Want your SSD to power-cycle mid-write each time something else mates with or detaches from the splitter? Me neither.
• Or follow the USB-PD spec to the nth degree, aspiring for per-splitter-output voltage and current optimization to the capabilities and preferences of the associated connected “sink” device, and hoping that your silicon and software “building block” suppliers have adequately accounted and compensated for all possible edge and corner cases.

Good luck with that, product developers and users alike.

Selective data directionality

Ready for our next implementation complication? What, if anything, do you do about your customers’ potential desires for the connection between the splitter input and any/all output(s) to transport not only power but also data? In all the product implementations I’ve come across so far (stay tuned for the details to come shortly), bidirectional USB 2.0 (480 Mbps) rates are best-case supported, either assigned consistently to a dedicated output connector or to “the first output to connect to a device,” not simultaneously to all possible splitter outputs. But why?

Keep in mind that, akin to the passive Ethernet splitters that I discussed recently, there’s no active switching going on here. That’s what more complex (and costly) USB hub devices are for, if it’s what you need. Instead, once again, (at least) three implementation options exist with humble splitters, again as I see it (sound off in the comments, readers, if I overlooked or conversely overstated something):

• Bail on data carriage and focus only on power transfer. You’ll still need to comprehend the Configuration Channel (CC) signals if you want to support USB-PD, however.
• Pick a splitter output and run the bidirectional data solely and consistently between it and the input.
• Or decide that the first device that connects to the splitter’s multiple outputs is the only one that has the opportunity, if it chooses to take advantage of it, to leverage not only power but also bidirectional data transfer facilities. And what happens when that device later disconnects from the splitter? Unclear.

Case study implementation diversity

I’ve so far collected four USB-C splitters in recent months, for both personal-use and teardown purposes. As you’ll see shortly, they handle both power and data transfer very differently, a divergence scenario that I find very interesting, as it implies leverage of different reference designs if not entirely different chip-supplier foundations (therefore the teardown angle).

In alphabetical order, beginning with the product you’ve already been introduced to earlier:

• Anker 2-in-1 USB-C to USB-C cable
  • Length options: 4’ and 6’
  • Color options: black and white
  • Outputs: 2
  • Power carriage: 140 W (max). “When two devices are used simultaneously, the first device plugged in receives higher power. The actual power each device receives depends on its power needs.”
  • Data carriage: USB 2.0 (480 Mbps) to first connected device
• Belkin 2-in-1 USB C to USB c Cable
  • Length: 5’
  • Color options: black and white
  • Outputs: 2
  • Power carriage: 140 W (max). “With two devices, smart power sharing splits power and the first device plugged in may get priority.”
  • Data carriage: USB 2.0 (480 Mbps) to first connected device

• Baseus Flash 2 in 1 USB C cable
  • Length: 4.9’
  • Color: black and white
  • Outputs: 2
  • Power carriage: 100 W (max)
  • Data carriage: USB 2.0 (480 Mbps)
    • Note: data transfer is apparently supported only in the latest v2 design. Conversely, with the seemingly initial product version I’d purchased back in September 2024, “Please note that this cable is designed specifically for charging purposes and does not support data transfer or video signal transmission.”

• MPATIBY 4 in 1 USB C cable
  • Length: 5’
  • Color: Black and grey (the version I own: various other options also available)
  • Outputs: 4
  • Power carriage: 5V-only: “The usb c multi charging cable does NOT support fast charging.”
  • Data carriage: USB 2.0 (480 Mbps), consistently and only to one of the outputs, with a uniquely labeled connector.

Online expertise recommendations, and in conclusion

Back in the early days of USB-C, when Nexus smartphones and M1 Apple Silicon-based laptops were getting destroyed by dodgy cables, hubs, chargers and other third-party implementations (or at least that’s what Apple was blaming), an engineer at Google named Benson Leung was the “knight in shining armor” that everyone was relying on to both publicly shame the miscreants and tell users what they should be buying instead. Benson’s seemingly still at Google and remains active on Reddit re USB-C matters, even though his Linkedin profile reports he’s now primarily working on other stuff.

More generally, I consistently found myself directed toward relevant discussion threads on the UsbCHardware subreddit (for which Benson is one of the moderators) as I was web searching while researching various topics in preparation for writing this piece, links to several of which I’ve already shared in both parts of this writeup series. Quality time spent there to get up to speed, while as-usual-for-Reddit filtering out the cruft, is recommended for any USB-C devotee.

And with that, I’ll wrap up for today. As always, I welcome your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• USB-C’s lingering incompatibilities and other complexities, part 1: Direct-connect complications
• USB: Deciphering the signaling, connector, and power delivery differences
• USB Power Delivery: incompatibility-derived foibles and failures
• USB 3: How did it end up being so messy?
• USB-C and Power Delivery: Too much of a good thing?

The post USB-C’s lingering incompatibilities and complexities, part 2: Splitter issues appeared first on EDN.

The aerospace industry is undergoing a profound power architecture shift. For decades, radiation-hardened (rad-hard) silicon MOSFETs were the undisputed workhorses of spaceborne DC-DC converters. However, as modern satellite payloads demand higher efficiency, tighter density, and lower mass, silicon is hitting its physical limits.

Enter gallium nitride (GaN) high electron mobility transistors (HEMTs). Boasting a wider bandgap, superior electron mobility, and inherent robustness against certain radiation mechanisms, GaN is the key to unlocking next-generation space power densities. Yet, translating these raw material advantages into flight-ready, highly reliable hardware requires a deep understanding of its unique driving requirements and its interaction with rad-hard pulse width modulation (PWM) controllers.

The rad-hard landscape: Silicon vs. GaN

Space radiation hazards generally fall into two categories: Total ionizing dose (TID) and single event effects (SEE).

In silicon MOSFETs, TID causes a build-up of trapped holes in the thick gate oxide, leading to a severe negative shift in threshold voltage (Vth) and increased leakage current. On the other hand, GaN HEMTs lack a traditional gate oxide, utilizing a Schottky or p-GaN gate structure instead. Because there is no oxide to trap charges, rad-hard GaN devices exhibit exceptional inherent tolerance to TID, often surviving exposure well past 100 krad(Si) to 1 Mrad(Si) with minimal parameter shifts.

While GaN shines under TID, SEE is where the engineering nuances lie. Silicon MOSFETs are susceptible to single event burnout (SEB) and single event gate rupture (SEGR) due to heavy ion strikes creating parasitic bipolar conduction paths or destroying the gate oxide.

But GaN HEMTs don’t suffer from traditional SEB or SEGR because they are majority-carrier devices without parasitic bipolar structures. However, they are prone to single event transients (SETs) and catastrophic degradation at high drain-to-source voltages (VDS). Under heavy ion bombardment, localized high electric fields near the drain can cause high-current leakage paths. Consequently, a VDS derating of 30% to 50% of the maximum rated voltage is standard practice for spaceflight GaN applications.

Alex Lidow, CEO and co-founder of Efficient Power Conversion (EPC), notes the physical limitations of legacy materials: “Silicon has had a glorious 60-year run, but it has hit its theoretical performance wall. In space applications, where every gram of weight translates directly to launch cost, GaN isn’t just an alternative—it’s an absolute architectural necessity.”

Driving the delicate GaN gate

The primary challenge when designing a flight-ready GaN converter is managing the gate drive. Silicon MOSFETs typically feature a comfortable gate threshold of 2 V to 4 V and can tolerate gate voltages up to ±20 V. GaN HEMTs are far less forgiving:

• Low threshold voltage: GaN devices typically turn on at a mere 1.5 V to 2.0 V.
• Fragile gate rating: The absolute maximum gate-to-source voltage (VDS) is often capped at a tight -5 V to +6 V.
• Ultra-low gate charge (QG): GaN switches an order of magnitude faster than silicon. While this minimizes switching losses, it introduces severe dv/dt and di/dt sensitivities.

If the gate drive circuit experiences even minor parasitic inductance, the rapid dv/dt transition can couple back through the device’s Miller capacitance (CGD), generating a transient voltage spike on the gate. If this spike exceeds 1.5 V, it triggers a catastrophic spurious turn-on (shoot-through), potentially destroying the power stage. Conversely, if the gate driver overshoots beyond 6 V due to ringing, the gate permanently degrades.

Interfacing with heritage PWM controllers

Because dedicated rad-hard GaN-integrated drivers are still emerging, power engineers frequently pair discrete rad-hard GaN FETs with established, flight-proven rad-hard analog PWM controllers.

These heritage controllers were designed to drive the heavy, capacitive gates of silicon MOSFETs, delivering output swings from 0 V to 12 V or higher. Interfacing these high-voltage controllers with a delicate 5-V GaN gate requires a meticulously designed intermediate drive stage and layout discipline.

• Voltage clamping: Direct connection is catastrophic. Engineers must employ a high-speed level shifter or a dedicated, rad-hard gate driver buffer (for example, ISL71020M) that accepts standard PWM logic levels and provides a tightly regulated 5-V drive output.
• Asymmetric gate resistance (RG): The gate resistor network must be split into separate turn-on (Rgon) and turn-off (Rgoff) paths via a diode-resistor network. Rgon is optimized to purposefully slow down the turn-on dv/dt to suppress gate ringing. Rgoff is kept near 0 Ω to provide a low-impedance hold-down path, ensuring the gate remains firmly below the threshold voltage during rapid drain voltage transitions.
• Dead time management: GaN HEMTs lack a native body diode; so, they conduct in reverse through the channel when the gate is off. During this dead time, the reverse voltage drop (VSD) can be quite high (2 V to 3 V). If the PWM controller introduces excessive dead time, efficiency penalties from reverse conduction negate the switching advantages of GaN. Therefore, designers must utilize PWM controllers with highly precise programmable dead-time control or implement an external low-forward-drop Schottky diode in parallel.

In my years managing power electronics design, I have watched countless clean schematics fall apart under the oscilloscope simply because an engineer treated a fast wide-bandgap loop layout like a legacy 100-kHz silicon board.

When marrying a heritage 12-V PWM architecture to a 5-V gate, your layout must be an absolute work of art. Parasitic inductance can easily destroy the gate on the very first pulse if the loop area isn’t locked down.

Packaging innovation and real-world use cases

The unique performance GaN metrics are actively reshaping the size, weight, and power (SWaP) equation across various orbital profiles.

In satellite bus power, utilizing isolated GaN-based flyback or forward topologies allows engineers to push switching frequencies past 500 kHz—up from the standard 100 kHz legacy limit—directly translating to a 60% reduction in magnetics volume. In point-of-load (POL) converters, synchronous buck configurations supply core logic rails for spaceborne FPGAs and deep-space processing computers with near-zero reverse recovery losses. Furthermore, in space robotics and motor control, three-phase GaN inverter stages enable compact, motor-integrated electronics housings that bypass heavy shielded cabling.

To support these high-frequency applications, manufacturers have developed innovative, low-inductance packaging structures specifically engineered to eliminate the internal bond wires that cripple traditional high-reliability packages.

Vendor landscape and flight heritage

Navigating the space-qualified GaN marketplace requires examining components that meet the rigorous screening levels required for aerospace reliability. Below are three design case studies.

1. EPC Space

The EPC Space family of devices commands a long track record in commercial-volume rad-hard discrete GaN deployment. Its enhancement-mode (eGaN) discrete FETs (such as 60-V EPC7014) and integrated power modules have accumulated an impressive lineage, with thousands of devices actively operating in orbit since January 2019. These components are heavily utilized in LEO small-sat constellations and GEO communication platforms, powering intermediate bus converters and high-speed pulsed laser drivers for autonomous LiDAR systems.

Figure 1 EPC Space’s hermetic packaging replaces traditional wire bonds with broad, low-profile bottom contact pads to eliminate loop inductance. Source: EPC

2. Infineon Technologies

Infineon’s CoolGaN family represents the entry of traditional military-standard (MIL-PRF-19500) JANS-grade rigor into the wide-bandgap space ecosystem. Leveraging its heritage in spaceborne silicon MOSFETs, Infineon modernized GaN packaging by removing wire bonds entirely. It PowIR-SMD package delivers a 49% footprint reduction compared to legacy housings and reduces internal parasitic package inductance by 97%—dropping to a mere 0.1 nH. This nearly eliminates internal gate ringing, allowing clean interfacing with fast PWM controllers.

Figure 2 The PowIR-SMD technology minimizes internal parasitic inductance down to 0.1 nH via an advanced die-free construction. Source: Infineon

Regarding the validation of these advanced architectures, a high-reliability engineering expert at Infineon stated: “Removing internal wire bonds was the final frontier for GaN in space. By developing a die-free, surface-mount package like PowIR-SMD, we didn’t just solve thermal management—we completely neutralized the parasitic gate inductance that historically caused engineers to shy away from high-speed wide-bandgap switches in critical flight hardware.”

3. Renesas

Renesas entered the space-qualified GaN arena by executing a brilliant ecosystem play: combining its decades-long legacy of rad-hard analog power management with high-reliability GaN FETs like ISL73024SEH. These devices are frequently designed alongside dedicated multi-phase synchronous PWM controllers—such as the ISL73847SEH—to form the fundamental backbone of spaceborne core power bricks.

Figure 3 The Renesas/Intersil radiation-hardened GaN family is engineered in rugged, space-qualified ceramic flatpacks optimized for severe thermal environments. Source: Renesas

Achieving mission success

While designing deep space profiles, we must ruthlessly enforce gate-clamping rules. Designing radiation-hardened GaN converters for space applications is ultimately an exercise in managing extremes. GaN offers game-changing thermal and volumetric efficiencies, but its unforgiving gate drive margins and extreme switching speeds mandate a departure from legacy silicon layout rules.

The accumulated flight data from the GaN industry pioneers has rewritten the rulebook for space power systems, dispelling early engineering anxiety through years of anomaly-free orbital operation. When carefully controlled by a robust, rad-hard PWM controller, these devices provide a mature, predictable, and remarkably rugged path toward achieving unparalleled power density in the cosmos.

Bharrat Mehta, a senior space scientist, is former deputy project director of Indian Space Research Organization (ISRO).

 

 

Related Content

• GaN Transistor for Space Missions
• Infineon unveils rad-hard GaN transistors
• Deep Space Challenges Rad-Hard IC Development
• Test and Measurement Priorities for GaN-Based Power Electronics
• GaN in Space: Unlocking Efficiency and Performance in Satellite Systems

The post Rad-hard GaN converters: Design insights for space hardware appeared first on EDN.

The RTC 27 Click board from Mikroe provides ultra-low-power timekeeping with alarm, watchdog, and timestamp functions. Based on the mikroBUS add-on board socket standard, it integrates the NXP PCF8525 nano-power CMOS real-time clock and calendar chip with an I2C interface. The board is the 2000th member of the Click family, enabling developers to quickly build proof-of-concept designs, prototypes, and embedded applications.

Using the PCF8525’s default temperature compensation engine and integrated temperature sensor, the RTC 27 Click corrects crystal frequency drift, achieving typical ±30-ppm accuracy across temperature and up to 5× better timekeeping than an uncompensated RTC design. It provides time and calendar information, including year, month, day, weekday, hour, minute, second, and 1/100 second.

The RTC 27 Click operates with 3.3-V and 5-V logic voltage levels, while the PCF8525 consumes a typical 64 nA in timekeeping mode with a 3.3-V supply. This makes the board well suited for battery-powered and always-on designs, including portable instruments, wearables, industrial systems, and IoT applications.

The RTC 27 Click is available from Mikroe and its distributors with single-unit pricing of $19.

RTC 27 Click product page 

Mikroe

The post Low-power RTC simplifies embedded timekeeping appeared first on EDN.