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When doing analog design, especially at higher frequencies ranging into the microwave region, it’s normal to focus on devices and the performance they enable in the specific topology. But there’s another aspect of microwave design that’s important to keep in mind: the role of advanced materials and the atomic-scale physics that allows conception, construction, and test of the advanced devices need to reach toward the multi-gigahertz part of the spectrum.

This is demonstrated by a recent Cornell University-led development related to voltage-tunable capacitors, or varactors, that combine high performance with low loss—and the road to get there. Traditional varactor technologies, while effective, often hit a performance ceiling due to intrinsic material limitations, particularly when it comes to dielectric losses that degrade signal quality.

A federal research program was initiated in 1999 to find materials for varactors that would offer lower dielectric losses at higher frequencies. The “back story” of success here is yet another example of how progress is often not linear, predictable, or obvious, despite the way it’s often portrayed.

The research team’s success here is due to persistence and following a very different path, as the project has been a long journey. While nearly every scientific team in the program focused on using barium strontium titanate, the Cornell team looked at layered crystalline materials, a type of perovskite structure known as Ruddlesden-Popper thin films, characterized by their exceptionally low energy loss at microwave frequencies.

Unfortunately, these films also had a major drawback: according to the accepted understanding of their crystal symmetry, they shouldn’t have been able to provide the tunability needed for practical devices.

A member of the research team was developing a new technique for measuring the dielectric properties of thin films across a wide range of frequencies. One of his measurements of strontium titanium oxide with composition Sr4Ti3O10, a layered Ruddlesden-Popper thin film, suggested something remarkable: the supposedly untunable material might, in fact, be tunable after all.

But there was a problem: the effect only appeared in an in-plane geometry, in which the electric field moved sideways through the material. Real-world devices such as voltage-tunable capacitors used in microwave circuits generally require an out-of-plane design, in which the electric field moves vertically through the film, enabling smaller, more efficient components.

Researchers spent a decade trying to find a way to preserve their low microwave loss while making them more tunable and more practical. They then asked a more radical question: what if they could change the symmetry of the material itself? If so, it might be possible to change the symmetry in a specific family of Ruddlesden-Popper compounds made from barium, strontium, titanium, and oxygen.

In a true multi-institution effort with collaborators at Cornell, the University of Connecticut, Rice University, the University of Maryland, Boise State University and the National Institute of Standards and Technology (NIST), they engineered a new version of the material by inserting carefully spaced rock-salt layers. The strategy effectively rewrote the material’s internal rules, allowing it to exhibit the out-of-plane behavior needed for practical devices while preserving the low-loss characteristics that had made the Ruddlesden-Popper thin films attractive in the first place.

By engineering a film structure that introduces a unique rock-salt atomic layer interleaved with every “n” perovskite unit cell, the researchers created a new class of thin films whose symmetry properties could be precisely controlled (Figure 1).

Figure 1 Researchers used advanced microscopy to confirm the atomic structure of an engineered Ruddlesden-Popper material. The diagrams show how alternating layers in the crystal helped produce the material’s unusual combination of tunability and low energy loss. Source: Cornell University

From possible breakthrough to despair, then to a solution

But this success led to another dead-end, as the new out-of-plane devices posed an entirely different metrology problem. The frequencies most relevant for modern communications systems are among the most difficult to measure accurately because at those high frequencies, the signal from the material can be distorted by the test structure itself—the metal electrodes, wiring, and geometries surrounding the dielectric. So, when the researchers first tested the new Ruddlesden-Popper devices at microwave frequencies, the results were confusing.

Addressing this issue, a NIST-based group began to develop a new metrology approach capable of characterizing the material in an out-of-plane, metal-insulator-metal capacitor geometry at frequencies beyond the reach of conventional techniques. They added a “control structure” using a sheet of metal that had the same topology as the device. Measuring that control structure let the team perform an additional round of calibration, subtracting away distortions caused by the test structure itself, and isolating the dielectric’s true microwave response (Figure 2).

Figure 2 The microwave measurement setup used by the NIST team in Boulder, Colorado. Source: NIST via Cornell University

Their custom-tailored composition exhibits a remarkable relative tunability of 51% under an applied electric field of 250 kV/cm, which is almost double the performance of many conventional tunable dielectrics. At the same time, it maintains an impressively low dielectric loss that translates to a material quality factor of about 200. For the best version, the measured dielectric tuning figure of merit (FOM) showed tenfold improvement for out-of-plane tunable dielectrics at 10 GHz.

Figure 3 Various perspectives on microwave characterization are displayed at ambient temperature. Source: Cornell University

Will this lead to new varactors that you can buy? Obviously, it’s too early to say; there are still many potential obstacles on the path to commercialization, if it even happens.

But I do think the right screenwriter could make an exciting story out of this long quest with its advances, insight, contrary thinking, roadblocks, and eventual success. It would be nice to see a true story of science discovery and innovation captured and brought to a more general audience (can you think of any recent ones other than the 2023 blockbuster movie Oppenheimer?).

The work is detailed in their intense paper with a deceptively simple title “Breaking symmetry yields a low-loss out-of-plane tunable microwave dielectric” published in Nature Electronics; while that paper is behind a paywall, a “student” preprint copy is posted at ResearchGate here. In addition, there’s a fairly technical yet very readable description of the work posted at Bioengineer.org (why there—I can’t say).

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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The post Deep physics, materials science enhance dielectrics, varactors appeared first on EDN.

The iconic LM2917 tackles frequency-to-current conversion with (very) few externals.

Almost exactly 50 years ago—in June 1976, to be precise—National Semiconductor introduced the LM29x7 series, offering deceptively simple monolithic solutions to a frequently encountered signal processing problem: the flexible and accurate conversion of frequency into an analog signal.  I say “deceptively simple” because actually, these chips are very capable interfaces with versatile inputs, internal active zener voltage references (with the LM2917), and a configurable output that includes an opamp-driven uncommitted Darlington transistor.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Although initially targeted at automotive applications, the LM29x7 series’ flexibility makes them highly handy in other contexts, including industrial applications like monitoring turbine-type flow meter flow rate and small motor tachometry. Figure 1’s facile conversion of a frequency input to a universal 4-20mA current loop format shows how minimalist—it makes do with just nine paltry passives—such a circuit can be when implemented with a LM2917.

Figure 1 A 2917 with internal voltage reference converts a 0-5kHz input to a 4-20mA output.  Single-pass calibration of both ends of the output span is available. First step: input 0Hz and adjust R1 for 4mA output. Second step: input 5kHz and adjust R2 for 20mA. Third step: there is no third step. You’re done.

Here’s how it works.

Incoming pulses are converted by the internal Schmidt trigger comparator and charge pump into constant-current (180uA) pulses delivered to pin 3. Each pulse cycle carries a charge quantum Qp = VzC1 so that the average current out of pin 3 as a function of the Finput frequency is I3 = Fin Qp = Fin Vz C1. For the values shown, that works out to I3 = 7.56uA/kHz = 0 to 38uA as Fin goes from 0 to 5kHz. For calibration stability, C1 should be a temperature-stable type like C0G.

The R1…R4 resistor network hung from pin 3 converts this 0 to 38uA to 0 to 4v which is added to a 1v offset supplied by R3. The resulting 1 to 5v total is converted by the internal output opamp and Darlington via current sense R6 to the final 4 to 20mA output. R7 provides some bias current cancellation, which is useful since the thirsty opamp inputs can draw as much a 500nA. If uncorrected, that could create a 50mV voltage offset error on pin 3. Meanwhile, C2 provides ripple-suppression filtering.

However, none of this explains why R1 and R2 are variable. Here’s why. Although U1’s spec’d linearity and temperature coefficient are good, its initial tolerances aren’t so great: about +/-10%.  See “gain constant K” in Table 7.5 here (PDF). Therefore some post-assembly final calibration is pretty much unavoidable, which is the purpose of R1’s (4mA zero) and R2’s (20mA full-scale 5kHz) tweakability.  But at least if you do the adjustments in the right order (first R1, then R2), they won’t interact and calibration can be completed in s single pass.

So it shouldn’t Hz too much. (No such promises for his jokes, however! Ed.)

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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The post Painlessly convert Hz to 4-20mA current loop appeared first on EDN.

Are you an engineer contemplating your next “skillset” move in the AI era? If so, the ‘Mind of the Engineer’ survey is for you. The survey delves into multiple engineering disciplines, the latest technology trends, and emerging design skillsets to formulate empirical observations about where today’s engineering landscape is heading and how engineers should prepare for this AI-powered paradigm shift.

More importantly, this survey touches a hot nerve: AI’s potential to eliminate engineering jobs. Will AI fundamentally change what it means to be an engineer in the next five years? And do engineers trust AI-generated outputs, and do these outputs reflect biases in training data?

The survey also tests grounds for young engineers, where AI and machine learning (ML) skills are hot favorites. Will these disciplines take over computer science and engineering? Should engineers go for self-study efforts through books, papers, blogs, and YouTube videos, or should they opt for education courses or certificates with Coursera, edX, Udemy, and IEEE?

The survey also attempts to gauge where engineers stand in terms of effectively using AI tools in electronics design and manufacturing processes. That includes agentic AI, formal AI, AI certifications, LLMs, and AI-assisted EDA tools. Also, how comfortable engineers are in AI/ML model development and deployment.

The survey also digs deeper into how engineers are using chatbots/assistants such as ChatGPT, Claude, Gemini, and Copilot Chat. Then there are AI coding assistants like GitHub Copilot, Cursor, and Tabnine. The survey attempts to establish where these tools stand in an engineer’s day-to-day work and what the actual productivity gains are.

That brings us to a sensitive and crucial issue: Will AI tools eliminate more engineering jobs than they create? Are AI tools making engineers significantly more productive overall? Will AI fundamentally change what it means to be an engineer in the coming years?

However, the survey isn’t all about AI; cybersecurity and quantum computing are presented as pressing issues on many engineers’ minds. For instance, where does quantum computing stand in its deployment timeline? And how aware engineers are in terms of quantum-safe products and post-quantum cryptography.

Next, the survey covers quickly emerging technologies such as chiplets and advanced packaging. Likewise, power electronics stars—silicon carbide (SiC) and gallium nitride (GaN)—are also there. Not to be discounted, edge AI, a rapidly emerging offshoot of AI technology, is there as well.

AspenCore, publisher of EDN, is conducting the “Voice of the Engineer” survey. Once you complete this survey, you will become eligible to be randomly selected as one of 10 respondents to receive an Amazon.com Gift Card valued at USD 100 (or local equivalent). Results of this survey will be announced at a major industry event with a fanfare. They will also be posted on EE Times, EDN’s sister publication.

Participate in the survey and be part of this timely engineering conversation about the future of AI and the electronics industry at large.

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The post ‘Mind of the Engineer’ survey: A reality check on where EEs stand on AI appeared first on EDN.

If you periodically need to see the frequency response of a circuit, this easy, inexpensive project can help you out.

Editor’s note: This is a two-part series on how to create a noise generator with an adjustable bandwidth and a consistent amplitude. The previous entry: 

• Making noise with a BANG, part 1: Concept and hardware

The operation and firmware

As I mentioned last time, I was able to reuse much of the firmware from a previous Design Idea project. The Arduino C code consists of three files. One is the initialization code for the DAC, while another contains code for the LCD/touch screen operations. The third is the main code. Let’s look at these one at a time.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The DAC initialization code does just what it says and is designed to get a DAC output as fast as possible. The LCD/touch screen code is the largest piece of the software puzzle. Before discussing it “under the hood”, let’s take a quick look at the some of the LCD/touch screen display outputs. Figure 1 shows most of the screens used in the BANG.

Figure 1 The BANG LCD screens are designed to be both intuitive and informative.

The first screen you see after the power-up splash screen is what I call the main screen. It allows you to select an output, but let’s hold off discussing this implementation aspect in detail until later. For now, just understand that on power-up, it will default to the noise output on the AC and DC BNC connectors.

Also on the main screen is the “Change Bandwidth” selection that will allow you to set the bandwidth for the noise (noise bandwidth is measured from 0 Hz). When you press “Change Bandwidth”, the screen will change to the keypad and allow you to enter your desired number. Note that if you exceed the maximum 225 kHz it will default to 225 kHz. Similarly, if you enter a number less than the minimum of 500 Hz it will default to 500 Hz. After hitting “ENTER” you will return to the main screen.

On the main screen, selecting “About” will take you to a screen showing lots of interesting information such as your selected bandwidth and the gain it will apply to the noise during filtering. You’ll also see the sample rate (which is fixed), firmware version, and (for those that are interested) your current IIR filter’s coefficients. Next, it shows the battery voltage and charge level. (If you do not have a battery installed you may see fully charged numbers as it is instead reporting the charger voltage. There is a #define in the top portion of the main code that you can set to “false” instead, in which case this line won’t be displayed if you don’t have a battery installed.) The last item shown is the incoming USB voltage.

The last screen shown in Figure 1 is the one displayed when “RUN” is selected on the main screen. If you see this screen, the noise signal is being generated and is being output to the BNC connectors.

Let’s talk a little about the code for creating these screens. It’s a bit long and mostly involves setting colors, drawing boxes, selecting fonts, aligning text in the box, and capturing positions of key presses. Almost all of this is done using higher level calls to the downloadable “Adafruit GFX Graphics Library”. Here’s a short example of the code showing how to display the word “BANG” in red against a grey background:

tft.fillScreen(tft.color565(0xe0, 0xe0, 0xe0)); // Grey tft.setFont(&FreeSansBoldOblique50pt7b); tft.setTextColor(ILI9341_RED); tft.setTextSize(1); tft.setCursor(13, 100); tft.print("BANG");

The third C file is the main code, which mostly directs calls to the correct LCD screen, executes miscellaneous housekeeping operations, and (of course) generates the noise signal, the latter starting with the bandwidth selected from the touchscreen. Using this value, we generate the coefficients for a digital 2-pole low-pass Butterworth IIR filter. The next step is to get a value for the gain we will be using on the noise signal. This is done by calling a function that has the bandwidth as an input and returns a gain number. Here is the code for that function:

//****************************************************** // AGC * // Does an automatic gain adjust to the * // random number amplitude. Run once after * // startup or a change in the LP filter. * //****************************************************** float AGC(float cutoff_freq) { float agcGain = 1; // Calculate agc gain based on the set bandwidth if (cutoff_freq >= 50000) agcGain = 31.0 * pow(cutoff_freq, -0.292); // for 225kHz to 50kHz else agcGain = 393.769851 * pow((cutoff_freq - 97.8961702), -0.524598029); // Curve fit of freq vs. amplitude data gainOffset = 1024.0f * (2.0f - agcGain); // Adjustment for shift in DC level return agcGain; }

You’ll see that there are two different formulas used for agcGain, based on whether the bandwidth selected is greater than 50 kHz. This dual-equation method makes curve fitting more accurate. These formulas were derived from data I generated by setting a bandwidth and then adjusting the gain in code to get a desired amplitude. The data was then used to generate curve-fitted equations (kudos to Standards Applied Engineering Tools, whose Curve Fitting Online utility gave by far the most accurate curve fit of all the tools I found and tried). Later, I’ll also detail how AI did (or, maybe more accurately, didn’t) with generating the same curve fit equation(s).

You can see from the second equation that the power function is based on -0.52; roughly the square root of 2 as we talked about at the beginning of part 1 of this series. The reason it is not exactly a square root of 2 function is because some noise, beyond the cutoff frequency of the 2-pole digital IIR filter, still exists in this roll-off portion of the filtered signal – i.e., it is not a brick wall filter.

Figure 2 shows a graph of this gain vs. bandwidth selected.

Figure 2 This graph shows the linear gain vs. bandwidth result for the equations used in this design.

With the bandwidth entered and the gain calculated, it is then incorporated into the coefficients of the lowpass IIR filter. This approach optimizes the calculations; we don’t need to add another multiplier inside the speed-optimized output loop.

Ok: we’re now ready to generate the noise signal. When the user selects “RUN”, the code enters a tight loop. In it, we get a random number from the true random number generator (TRNG). Next, we run the number through the IIR filter, which also applies the gain. Then, the lower 12 bits of this number are sent out of the DAC. (A note: the DAC has a slew rate of somewhere around 1 µS per volt to minimize the effect. The number is scaled to keep the signal mean coming from the DAC to around 1/2 Vcc.) This loop continues until the user selects “STOP”.

Those of you following closely may be thinking something along the lines of the following right now: “Another way to generate a noise signal of a given amplitude is to simply generate the random samples at a lower sample rate”. The downside of this alternative approach is that the analog reconstruction filter would need to be adjusted to follow the sample rate, which seems like a much more difficult analog design task. Also, we would still need to perform the digital low-pass filtering for anti-aliasing.

It’s time to look at the output of the BANG. Figure 3’s scope display shows the AC output time domain signal on the left and the FFT on the right. The BANG is set to give an output with a 25 kHz bandwidth.

Figure 3 This scope plot shows the BANG output with a 25 kHz bandwidth setting.

The enclosure

The BANG’s enclosure derives from a custom 3D-printable model (see later for a file-download link). It includes three parts: the main body, the base/PCB mount, and a stylus for the touchscreen. The main body’s download is modeled with two filament colors but can alternatively be printed in one color. If printed in a single color, the text is still readable, as it is also embossed. The base holds a 120 mm x 80 mm PCB. I used a protoboard as there were a minimal number of parts and was faster to build than designing and waiting for a custom PCB.

Wait, there’s more

While TRNGs are common in larger processors, they’re more rare in smaller micros. Most compilers therefore use pseudo-random number generators instead. But since this system was generating 32-bit true random numbers, it occurred to me that such a data stream may also have other uses, such as in cryptography systems, input data for testing code, a “seed” for pseudo-random number generators, or even helping you select “picks” for playing the lottery.

More broadly, it seemed like a waste to not have a way to output these generated numbers. So, I included support for this feature, via USB, in two format options – ASCII data or binary data. The desired format can be chosen from the “Select Output” LCD page shown in Figure 4 (as mentioned earlier, the power-up default is the noise generator output via the analog BNC connectors).

Figure 4 The design includes support for outputting the 32-bit true random numbers generated, over USB and in two format options.

Note that although the data is 32 bits, it can be sliced or appended to form any size random number you require. For example, you can use one bit of the 32-bit source, which will still be random, or you can append two 32-bit output numbers to create a truly random 64-bit number.

Comments on AI use

I only used AI (and then only experimentally) for one part of the project, the curve fitting of test data to create the equation(s) for the AGC. The result was…interesting. I’d already developed the earlier discussed frequency-to-gain equations for the AGC algorithm, but I thought I should also try AI to see what it came up with. I fired up Microsoft Copilot and gave it the frequency vs gain data that I’d already created by iteratively setting a frequency and then adjusting gain in the code until I got the fixed amplitude I was looking for.

Copilot noted that it looked like a power equation – good. Then it gave me a very simple equation: gain = 1.96 * freq-0.52 . Wow, I thought, much simpler than the equations I’d came up with. But it seemed too good to be true, so I got out a calculator. At a frequency of 10 kHz the gain should be around 3. When you make the calculation on the AI’s formula you get around 0.016. When I asked Copilot to use its equation on 10 kHz, it said the gain would be 3.68. Another AI with a case of cognitive dissonance. Perhaps obviously, I used the other formula instead!

Conclusion

This is a fairly easy and inexpensive project to build. If you periodically have the need to see the frequency response of a circuit, it may help you out.

Note that the schematic, code, 3D print files, Arduino software, links related to various parts of the project, and additional notes and pictures on the project’s design and construction can be downloaded for free at the MakerWorld website.

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

Related Content

• Making noise with a BANG, part 1: Concept and hardware
• A digital filter system (DFS), Part 1
• A digital filter system (DFS), Part 2

The post Making noise with a BANG, part 2: Software, integration and operating results appeared first on EDN.

Conflicting application requirements can turn system-on-chip (SoC) design into a hall of mirrors. In particular, choosing a process technology can become a maze of contradictions and puzzles.

Then there is higher speed, which generally requires more power. Next, the technology that delivers the necessary performance and power efficiency may be unacceptable due to cost or supply-chain constraints.

However, a design partner who can customize foundational IP—logic cell libraries or memories—and shepherd the custom cells through the design flow, manufacturing, and testing can often bring an SoC design safely through the maze.

One recent engagement with a crypto-mining client illustrates the importance of custom foundational IP in resolving these trade-offs. And it also shows how the impact of custom cells can ripple through the design flow, from tape-out and beyond, emphasizing the need for a design partner with expertise in both IP creation and SoC implementation.

A unique application

Crypto mining is the process of generating new coins in a cryptocurrency. For many such currencies, including the ubiquitous Bitcoin, the process requires a so-called proof-of-effort: a computationally intensive task with no known shortcut.

Factoring a huge number is an example: the only way to find the prime factors is to keep trying new prime numbers. In principle, the cryptocurrency’s governors would publish a large number, the crypto miners would set to work searching for factors, and the first miner to publish all the factors would receive a new coin.

Obviously—luck aside—the miners with the most computing power will get the most coins. That leads to a computing arms race. Less obviously, this game consumes a tremendous amount of energy—one reason China attempted to ban crypto mining in 2021. To make the enterprise profitable, the miners need to stay on the leading edge of computing performance while minimizing capital investment and operating costs. These costs are dominated by power consumption.

Under those pressures, crypto miners quickly migrated from farms of CPU-based server boards to FPGAs, and then to vast arrays of ASIC hardware. Today, miners demand high computing performance, very low power consumption, very low front-end investment, and low unit cost—a set of contradictory requirements.

The mining SoC

This was the scenario presented to us by our crypto-mining client. Together, we determined that the lowest-cost approach that met their performance and power requirements would be a FinFET process with an extremely low operating voltage.

In fact, we had fully characterized 0.5-V logic libraries for this process. There was just one problem. The library could not meet the client’s speed requirements. The problem, it turned out, was the registers. This library, like virtually all standard logic libraries, uses a conventional master-slave D-type flip-flop. But it could not operate reliably at the required clock frequency. So, we decided to create a custom D-type flip-flop cell.

The D flip-flop

The D-type flip-flop has been a fundamental element in digital design for decades, used for everything from state machines to registers (Figure 1).

Figure 1 Schematic highlights a 32-bit D-flip-flop used to implement D-type registers. Source: Faraday Technology

The cell’s performance and stability are vital to any RTL design. The conventional cell design uses two stages and two clock phases. The first stage captures the input data on one clock edge, and the second stage latches the captured data on the second clock edge. In most designs, this requires routing two very accurately timed clock phases to every flip-flop cell.

We believed we could eliminate one of these clock signals and achieve a higher operating speed. Eliminating one clock would also substantially reduce the cell’s power dissipation and could reduce area and routing congestion.

But could we accomplish this, and hit the required frequency? And could we do all that while sacrificing the inherent stability of the dual-phase clock approach and still have a device that is resistant to process variations and electrical upset?

The TSPC flip-flop

Our exploration of circuit designs led to the development of the true single-phase clock (TSPC) D-type flip-flop (Figure 2).

Figure 2 Schematic of a traditional positive-edge triggered TSPC flip-flop showing how a TSPC flip-flop would meet the customer’s power requirements. Our proposed circuit design allowed the TSPC flip-flop to also operate over the necessary frequency range. Source: Faraday Technology

However, circuit design and proof of concept were just the beginning. We fully simulated the circuit in SPICE to understand the layout and sensitivities of this novel cell. We needed to characterize the TSPC flip-flop not only in isolation but also in a dense layout surrounded by other cells, under marginal, noisy clocks, and process variations. At last, we reached our goals for both performance and reliability.

The SoC design using our TSPC flip-flop met our crypto-mining client’s speed requirements. The cell also achieved a 40% reduction in power at rated speed compared to the conventional D-type flip-flop cell it replaced. It reduced the area by about 7%. And from a functional perspective, the TSPC cell was simply a normal D-type flip-flop.

But our detailed characterization of the cell revealed differences in the new device’s operating characteristics. These differences would influence the implementation flow for the SoC.

The cell in use

One unique characteristic of the TSPC cell influences front-end design, specifically power management planning. The single-phase clock for the TSPC flip-flop must not stop during operation, or the flip-flop state may be lost. This places significant limits on the use of power-management techniques such as clock gating and clock throttling. A design that interrupts the register clock must tolerate an unpredictable state when the clock resumes.

Other special characteristics of the cell further influence downstream design. For example, the cell is quite sensitive to clock signal integrity. This requires careful, skilled planning of clock networks from the outset and equally careful routing of clock trees. Conventional clock-tree synthesis tools may not deliver the necessary signal quality across all flip-flop instances, resulting in unreliable operation.

The cell is also sensitive to process variations, even at a local level. This issue can impact yield, but it can be overcome by careful placement during logic layout. We generally use manual insertion to instantiate the TSPC cells, as we have found them unsuitable for use with synthesis tools. Once the cells are placed, routing constraints are relatively minimal. The foremost issue is to maintain signal integrity on the clock lines.

Timing analysis is straightforward, of course, using the TSPC cell’s timing data. Signoff is also conventional—with the enhanced attention to clock integrity. Thanks to our exhaustive characterization and refinement of the cell design, there are no special process corners to be investigated. During test, some changes to the test vectors may be helpful to inspect the unique behavior of the cells.

A new degree of freedom

SoC designers are used to trading off power, speed, and process to meet design requirements. But sometimes no setting of these knobs will achieve the desired result. Our crypto-mining client faced this challenge: running an affordable, available FinFET process at 0.5 V would achieve all design goals except maximum speed. But consuming more power or moving to a more advanced process node in exchange for more speed was not an acceptable trade-off.

The solution was to move outside the power-performance process box with customized foundational logic. Faraday determined that we could meet the client’s needs with only one custom cell—a novel D-type flip-flop design. But once characterized, we found that the cell would place significant demands on the implementation team, from power planning through test design (Figure 3).

Figure 3 To reduce power consumption, we used a TSPC circuit to replace a master-slave flip-flop; but TSPC has an operating frequency limit, so we proposed a solution to this limitation. Source: Faraday Technology

The TSPC flip-flop thus could have become only academic exercise. However, it became an out of the box solution here. Today, the crypto-mining SoC is in volume production and meets all design requirements. The chips are out there, searching for coins and earning their living.

Jason Kang is director of IP technology at Faraday Technology. He has over 20 years of experience in fundamental IP development, PDK integration, and IP model characterization. His expertise lies at the intersection of advanced-node design flows, device modeling, and EDA methodologies, with a strategic focus on silicon implementation and the emerging field of AI-driven design automation.

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The post Crypto mining SoC unearths a need for custom IP appeared first on EDN.

Whether it actually accomplishes the function intended (or at least asserted), the low price tag and enduring controversy sufficed to motivate a look inside.

Electronic pest control devices have a longstanding reputation (largely-to-completely justified, my own research of others’ studies has concluded) for being ineffective at encouraging mice and other rodents, along with a variety of insects and arachnids, to flee in their actively broadcasting presence. Sometimes it’s because they don’t work at all; the speaker inside might be a flat-out “dummy”, or at minimum nonfunctional over the claimed operating frequency range, for example (all conveniently obscured by the fact that you’re not supposed to be able to hear them anyway). And even when working as designed, there’s little to no evidence that ultrasonic pummeling does anything meaningful to deter pests, particularly after long-term use.

That all said, a teardown video from fellow teardown-er “Big Clive” that I recently came across still piqued my interest.

Clive, like me, made no definitive judgement as to the functional viability of the device, while still noting the overall skepticism derived by studies from others. That said, observations such as the following would, I felt, be unexpected in a product solely intended as a scam:

The PCB in this unit looks very competently designed, with good clearances and logical design. The bulk of the unit’s magic is in the software, and they’ve been quite clever in creating a swept ultrasonic output, while also pulse width modulating the indicator LED. It could even be said that the programmer may have been showboating.

So, when I subsequently came across a set of six ultrasonic pest repellers selling for $14.99 total, I couldn’t resist (nor could others, apparently, as inventory eventually sold out). They’re AC-powered, and each unit is claimed to cover up to 1,600 square feet. I’ll start with some “stock” shots, several of which include “creative” grammar and spelling terms. Can you spot them?

Dual smart chip? Inquiring minds want to know.

I’m not going to proactively point out all of the “creative” English language examples in these, to avoid ruining your investigatory fun, but “Desinsectisation” is just…awesome.

A half dozen for a bit more than a dozen (dollars)

Now for some real-life shots, as usual beginning with the outer box, also as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

I couldn’t resist:

Now let’s peer inside:

Remove one of the still-wrapped devices:

and the sliver of literature below them comes into view:

which, of course, I promptly tore while getting it out:

English on one side I’d expected. German on the other? Unexpected.

Here’s our now-“unclothed” patient:

When I first glanced at the screw heads on the back side, their seeming deviation had me wondering whether this was some sort of crude intrusion-prevention security scheme.

Turns out the bottom one had just come into my possession already partially stripped:

And have you yet noticed a curious omission both from the outer packaging and the device itself? Ponder for a bit…I’m not going anywhere…

…time’s up! Although there’s a FCC logo on the back of the box, there’s no actual FCC certification ID to be found anywhere. Even though…y’know…it’s a broadcast device. Anyhoo, onward:

Let’s plug ‘er in before taking ‘er apart. Thar she glows, just like in the stock photos:

For what it’s worth, my Collie seemingly wasn’t phased in the slightest by the supposed ultrasonic broadcast!

Getting to the guts

And now let’s dive inside:

Here’s the supposed ultrasonic-frequency transducer:

and the diminutive PCB:

See that screw, identical to the other two you’ve already seen, at the bottom? Interestingly, at least to me, there’s another screw hole, this one unpopulated, above the PCB. Apparently, the chassis was designed for multiple PCB variants, including one larger than this one. Regardless, removing the screw led to subsequent easy removal of the PCB itself.

Leaving nothing particularly exciting behind.

Let’s start with the PCB front side, which you’ve already seen in several past photos:

There are indeed two main ICs here, to the earlier “dual chip” reference, although still stretching the association. The upper four-lead one, toward the left side of the photo, is faintly marked “MB6F” and appears to be a bridge rectifier, with the “BD1” PCB mark presumably standing for “bridge diode” (not, in this case at least, ferrite bead). Its presumed-by-me function, as we’ve seen before, is to act as a crude AC/DC converter in conjunction with a yet-to-be-seen low pass filter (capacitor).

The other IC, labeled U1, eight-lead and below and to the right of its companion, is absent any topside mark and therefore something of a mystery, although if I was a betting man, I’d lay odds it’s an inexpensive MCU, akin to the one in Big Clive’s teardown victim. What about those glowing LEDs you saw in the earlier plugged-in device photo? They’re at the far upper right and left, with their PCB markings on the other side, which you’ll see next.

They operate somewhat oddly. When I preview them through my smartphone’s camera and display in “still” image capture mode, they generally blink at what I’m guessing is a 60-Hz rate. That said, they also occasionally dim and then return to their prior illumination intensity, and sometimes the blinking also temporarily ceases. When previewed in “video” mode on the smartphone (which I know because I tried to capture a clip of the aforementioned behavior), they exhibit constant illumination. Mysterious!

You might have also noticed PCB sites for two other LEDs, LED3 and LED4, although they seem to be unpopulated, along with multiple other unpopulated locations on this side of the PCB. Chassis placeholders for multiple PCBs…placeholders for additional components on this PCB variant…once again, all very mysterious!

In closing, let’s flip the PCB over.

At top is capacitor C2 which, given its proximity both to the AC inputs to the PCB and to the bridge rectifier, I’m guessing is our aforementioned low-pass filter. The resistor below is specifically labeled “FR1”, presumably referencing its augmented fuse function.

Aside from one other electrolytic capacitor, along with pass-through holes to solder sites on the other side of the PCB for the dual two-wire harnesses (one going to the “ultrasonic speaker”, the other to the AC plug), that’s it of note.

And with that, I’ll conclude for today. At some point after this teardown is published, as usual allowing time for reader questions, I’ll put the device back together, presumably still functional afterward (to whatever degree that term is relevant in this particular case).

But what do I do then? Donate the lot to some pest-plagued recipient hoping against hope for a miracle? Or donate all of ’em to the dump? Let me know your thoughts on this ethical quagmire, or anything else I’ve discussed here, in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Ultrasonic device claims to repel pests appeared first on EDN.

What looks like a simple port is in fact a silent architect—quietly shaping how energy and data flow between your car and your mobile world. Hidden inside that small rectangle of metal and plastic is a choreography of power regulation, signal integrity, and protocol negotiation.

It’s the unseen engineering that turns a “plug” into a lifeline, ensuring your EV and your phone don’t just connect, but truly communicate.

From socket to smart port

Once upon a dashboard, the humble “cigarette lighter” socket was nothing more than a dumb power tap—12 volts, no questions asked. Fast forward to today, and the USB-C port in your EV is no longer a passive outlet; it’s an intelligent node in a vast digital ecosystem. That tiny connector is the handshake between two massive computers: your phone and your car.

It juggles a delicate balance, delivering high-wattage energy to keep devices alive while simultaneously orchestrating millisecond-sensitive data streams that define navigation, entertainment, and even safety. In short, your USB port is not just a plug; it’s a bridge, a translator, and a silent engineer behind the scenes of modern mobility.

Power architecture: From traction to tablet

Unlike traditional cars, EVs don’t carry an alternator humming under the hood. Instead, they rely on a DC-DC converter—a silent workhorse that steps down the traction battery’s 400-V or even 800-V supply to the familiar 12-V rail that powers the cabin. That same rail feeds the USB ports, infotainment systems, and auxiliary electronics.

Think of it as an “infinite power bank”: charging your phone at 15 W for an hour consumes only about 0.015 kWh. Put that in perspective, a 75 kWh Tesla battery could technically recharge an iPhone 15 Pro Max more than 4,000 times. In other words, your EV’s energy reserves make mobile charging almost trivial, yet the engineering behind that seamless handoff is anything but.

Figure 1 Onboard DC-DC converter services the low-voltage auxiliary rail by extracting energy from the high-voltage traction battery. Source: Brogen EV Solution

Sidenote: Instead of combustion fuel, the high-voltage traction pack stores electrical energy at hundreds of volts, driving the motor and, through the DC-DC converter, sustaining the 12-V system.

The “signal” side: The handshake

If the power architecture is the muscle, the signal side is the brain. In USB-C, no current flows until a negotiation takes place. That negotiation happens over the Configuration Channel (CC) pins, where your EV and your phone exchange digital hellos before any electrons move.

Through this handshake, they decide critical roles: Who is the host? (almost always the car), and how much voltage can the phone safely accept?—whether it’s 5 V for legacy devices, 9 V or 15 V for fast-charging, or even 20 V for high-power modes. Only after this millisecond-level dialogue does energy begin to flow, ensuring that what looks like a simple plug-in is actually a carefully choreographed agreement between two computers.

Figure 2 Integrated electronics drive a 60-W USB-C car power socket, providing native support for Power Delivery, Quick Charge, and other fast-charging protocols. Source: Pro Car

Once the roles and voltage levels are agreed, the conversation doesn’t stop—it deepens into data protocols. Over the very same power pins, USB Power Delivery (USB-PD) runs a digital dialogue, negotiating charging speed and ensuring both sides stay within safe limits.

Parallel to that, separate high-speed differential pairs carry the real payload: the streams of audio, video, and control signals that make Apple CarPlay and Android Auto feel seamless. In effect, your EV’s USB port is multitasking—one channel whispering about volts and watts, another racing to deliver maps, playlists, and messages—all in perfect sync.

The challenge: Noise and interference

Your EV’s cabin is far from electrically serene. High-frequency switching from motor inverters and power electronics creates a “dirty” environment filled with electromagnetic noise. To keep your USB connection clean, manufacturers rely on shielded twisted pairs (STP) cables designed to resist interference and preserve signal integrity, so your music and navigation don’t glitch under the influence of stray magnetic fields.

But shielding alone isn’t enough. The electronics inside the USB interface must also withstand sudden voltage spikes and magnetic surges. That’s where common-mode transient immunity (CMTI) comes in; it’s a design requirement that ensures the transceivers can survive and keep data flowing even when the EV’s power electronics throw out nanosecond-scale noise bursts. Without strong CMTI performance, those spikes could corrupt packets or drop connections.

Figure 3 Oscillogram illustrates an EV-style CMTI spike waveform during a high-speed transient event. Source: Author (AI-generated)

Sidenote: In high-performance EV architectures, the drive for faster switching efficiency can turn CMTI into a critical bottleneck. As platforms move to 800-V systems, the steep voltage transitions (dv/dt) from wide bandgap (WBG) semiconductors—notably SiC and GaN—produce intense high-frequency transients. These spikes can leak through parasitic capacitances in isolation barriers (in gate drivers or digital isolators), risking shoot-through events where both switches conduct simultaneously, a destructive failure mode for traction inverters.

Especially, GaN’s ultra-fast switching makes it more vulnerable. To protect control logic and safeguard costly WBG modules, modern EV designs now require isolated gate drivers with ultra-high CMTI ratings (often >150 kV/µs, specified for both positive-and negative-going transients), a design safeguard that directly underpins range, reliability, and performance.

Also, it’s worth noting that there are two types of CMTI: static and dynamic. Static CMTI refers to the test condition where the input is held at a fixed logic high or logic low, and the output state is monitored during a common-mode transient strike. The requirement is that the gate driver output remains in its specified state across variations in process, voltage, and temperature.

Dynamic CMTI, by contrast, evaluates immunity while the device is actively switching. This measures whether the transient causes timing jitter or pulse distortion—making it the more demanding metric and the true limiter in fast-transition EV platforms using WBG devices.

And then there’s the subtle menace of ground loops: a cheap, poorly shielded cable can create electrical conflict between the car’s ground and your phone’s ground, producing that familiar buzzing in the speakers. What seems like a trivial accessory choice can make the difference between crystal-clear audio and noisy rides.

Why do some ports “only charge”

Ever noticed that not every USB port in your car lets you run CarPlay or Android Auto? That’s by design. Many automakers follow a hub strategy: one “Master Data Port” up front, usually near the driver, and several “dummy ports” in the rear that are charge-only. The reason is cost and complexity.

A data-capable port requires an automotive-grade controller, shielded wiring, and careful integration into the infotainment system—all of which add expense and engineering overhead. By contrast, a charge-only port is far simpler: just a buck converter stepping down voltage to feed your device. It’s a deliberate hardware trade-off, balancing convenience for passengers with the realities of automotive design budgets.

V2L: The ultimate USB upgrade

If USB-C feels powerful, Vehicle-to-Load (V2L) takes the idea to an entirely new scale. Cars like the Hyundai IONIQ 5 or Kia EV6 don’t stop at charging your phone; they turn the whole vehicle into a rolling generator. Instead of 60 W from a USB-C port, V2L delivers up to 3.6 kW through a standard AC outlet at 120 V (North America) or 230 V (Europe/Asia). That’s enough to run a full desk setup: monitor, laptop, and lights, all powered via a USB-C multi-charger.

And in trucks like the Ford F-150 Lightning, the concept scales even further with Pro Power Onboard, offering up to 9.6 kW across multiple AC outlets. At that level, the EV isn’t just a power bank; it’s a backup generator capable of supporting tools, appliances, or even parts of a home during an outage. In essence, V2L is the logical extension of the same engineering principles—scaling from watts to kilowatts—while keeping the promise of mobility and connectivity intact.

Sidenote: V2L technology depends on a coordinated handshake between the vehicle and adapter, primarily through the Proximity Pilot (PP) and Control Pilot (CP) pins defined by IEC 61851. The PP resistor identifies the adapter type and signals readiness, while the CP line maintains PWM-based communication for safe connection and disconnection.

In bi-directional on-board chargers, detection of the correct PP resistance or proprietary handshake prompts the system to enter discharge mode, closing internal contactors to deliver AC power outward. If the CP signal drops or the adapter is unplugged, the vehicle instantly opens the contactors to prevent arcing—ensuring safe, reliable V2L operation across varying manufacturer implementations.

Figure 4 A universal V2L adapter with a mode selector supports multiple EV platforms by initiating the vehicle’s power-discharge sequence. Source: Author

The future: Wireless vs. wired

Convenience is pushing hard toward wireless, but the trade-offs are real. Wireless charging pads promise a cable-free cabin, yet they come with hidden costs: extra heat from inductive transfer and a slight latency in power delivery compared to the precision of a wired USB-C port. That means slower charging and less efficiency, especially when you’re juggling multiple devices.

On the data side, the shift is already happening. Wireless CarPlay and Android Auto bypass the USB port entirely, riding on the car’s internal Wi-Fi signal. In this setup, the USB port is relegated to pure power duty, while your phone streams navigation, music, and messages over a wireless link. It’s a glimpse of the future—where the port becomes less about data and more about energy, while the car’s network takes over the role of digital bridge.

The car as a service

We used to choose cars based on horsepower; now we choose them based on their digital horsepower. Infotainment speed, connectivity options, and seamless integration with our mobile lives have become as decisive as torque or acceleration. And at the center of that experience sits the most-used interface in the cabin: the USB port.

It’s no longer just a plug—it’s the gateway to energy, data, and the services that define modern mobility. In this sense, the car has evolved into a platform, a service hub on wheels, where the humble port is the everyday touchpoint between driver, device, and digital ecosystem.

From volts to vision, engineering isn’t just power, it’s empowerment.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post More than a plug: The hidden USB engineering in your EV appeared first on EDN.

Selective oscillation achieves desired attention aspirations absent undesirable side effects.

Someone I knew long ago had a small electronics company with a client who wanted to make an attention-grabbing light display for a store window. This fellow’s office was set up with six light sources that were to be part of that display, where each source was a mirrored half-globe roughly one foot in diameter with a very bright light bulb that would turn on and off at its own independent rate.

As these bulbs would flash on and off asynchronously, the visual effect was quite stunning. There was one problem, though. Now and then, all six bulbs would go dark at the same time and when they did, the visual effect was actually jarring. That was a problem. I was asked if there was something we could do to avoid the jarring darkness, but quite frankly, I had no idea how this could be achieved with the items at hand.

This past December, a local diner set up a flashing light display out front in celebration of the holiday. It reminded me of my past-history display issue…and then I realized something.

Figure 1 A selective flashing light display still cultivates sizeable viewer attention.

The diner’s flashing light display was as visually striking as the globe set up was supposed to have been, but the diner’s display never went entirely dark. That was because only some of the light sources were blinking. Most of the light sources stayed lit all the time. Only a few of them needed to be blinking to achieve the desired visual effect.

Had I been smarter, I might have been able to solve that client’s problem. But since I don’t have a time machine, I couldn’t go back and do anything.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The automotive industry is undergoing a fundamental transformation. Vehicles are no longer static machines defined at production. They are becoming dynamic, software-defined platforms that evolve over time through updates, new features, and continuous improvements.

This shift is changing the role of semiconductors. What was once a supporting function is now central to how vehicles operate, differentiate, and deliver value. As software increasingly defines the vehicle experience, compute and power architectures must support far more than fixed functionality.

By the next decade, software-defined vehicle (SDV) architectures are expected to dominate new vehicle platforms. Automakers are investing heavily to move toward systems that can adapt over long lifecycles, even as software and AI evolve at a much faster pace.

The result is a new set of challenges that go beyond incremental improvements in performance.

A growing mismatch between lifecycles

At the core of the SDV transition is a structural mismatch.

While vehicles must operate safely and reliably for more than a decade, software does not follow the same timeline. New capabilities are introduced continuously—through AI model updates, over-the-air (OTA) features, and evolving applications that extend beyond the original vehicle design.

This creates a system that operates on multiple timelines at once. Safety-critical control systems require stability and certification, while AI-driven functions demand flexibility and rapid iteration. Traditional architectures struggle to accommodate both.

The conventional model, built around tightly coupled hardware and software and distributed electronic control units (ECUs), cannot scale to this level of complexity. Even as industry transitions toward centralized and zonal architectures, the underlying challenge remains: how to support continuous evolution without increasing risk.

Compute is now a system-level challenge

At the same time, the demand for in-vehicle compute is increasing dramatically.

Advanced driver assistance, higher levels of autonomy, and AI-driven experiences all require high-performance processing at the edge. These workloads must operate within strict constraints—limited power, tight thermal envelopes, and automotive-grade reliability.

Monolithic system-on-chip (SoC) designs make it difficult to balance these competing demands. A single device must meet performance, cost, safety, and lifecycle requirements simultaneously, which introduces inefficiencies and limits flexibility. As a result, compute is no longer a component decision. It’s a system-level problem that affects how the entire vehicle is designed and evolves over time.

Moving toward heterogeneous and modular architectures

The industry is beginning to respond by shifting toward more flexible architectures.

Instead of integrating all functionality into a single chip, new designs increasingly rely on heterogeneous systems that combine multiple compute elements—CPUs, GPUs, and AI accelerators—working together. This approach allows different parts of the system to be optimized independently while still functioning as a unified platform.

More importantly, it enables alignment with real-world requirements. Safety-critical functions can rely on mature, well-understood technologies, while AI workloads can take advantage of leading-edge processing. Memory, connectivity, and I/O can be placed where they deliver the best efficiency.

This shift reflects a broader transition from optimizing individual components to designing systems that balance performance, cost, and lifecycle considerations.

This system-level evolution is already visible in current automotive compute platforms.

High-performance SoC families such as R‑Car illustrate how architectures are adapting to SDV requirements. These platforms bring together heterogeneous compute, safety capabilities, and efficient power management in a scalable framework that can be deployed across different vehicle domains.

They are designed not only for central compute in ADAS and autonomous applications, but also to integrate with zonal controllers and broader vehicle systems. This enables automakers to build platforms that can evolve over time, rather than redesigning from scratch for each new generation.

The key point is not peak performance alone. It’s the ability to deliver consistent, predictable behavior across a wide range of use cases and over long operational lifetimes.

Supporting diverse OEM strategies

The transition to software-defined vehicles is not uniform across the industry.

Some automakers are moving toward fully centralized architectures, while others are adopting hybrid or zonal approaches. Different strategies reflect different priorities, including cost structure, time-to-market, and control over software ecosystems.

This diversity requires flexibility. Suppliers must support multiple architectural paths and allow automakers to make trade-offs that fit their specific goals. An open, scalable approach becomes increasingly important as vehicles evolve from isolated products to connected, long-lifecycle platforms.

AI is accelerating the need for change

Artificial intelligence is amplifying these challenges.

Early automotive AI focused on discrete functions such as perception. Today, vehicles must handle multiple AI-driven workloads simultaneously, from sensor fusion to planning to in-cabin interactions. These systems must operate in real time while meeting strict safety requirements.

This shifts the focus away from simplified performance metrics toward broader system considerations. Latency, determinism, power efficiency, and data movement all become critical. Supporting AI at scale requires architectures that can orchestrate diverse workloads efficiently while maintaining predictable performance. This reinforces the need for heterogeneous, system-level design.

From products to platforms

In other words, as complexity increases, the industry is moving toward integrated platforms.

Automakers are no longer looking solely for components. They are looking for solutions that combine hardware, software, and development ecosystems in a way that reduces integration risk and accelerates deployment.

This shift reflects a broader change in the semiconductor industry—from delivering individual devices to enabling complete system solutions. And this transition to software-defined vehicles is a long-term shift that will unfold over the next decade.

What is already clear is that success will depend on the ability to design systems that balance long-term reliability with rapid innovation. This requires new thinking—not just in silicon, but in architecture, development processes, and ecosystem collaboration.

The industry is moving beyond optimizing individual parts. It’s designing vehicles as cohesive, adaptable systems. And compute sits at the center of that transformation.

Vivek Bhan is senior VP and GM of high-performance computing at Renesas Electronics.

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The post Rethinking automotive compute in the software-defined era appeared first on EDN.

Revisiting the past can leave the reader with a range of reactions, including both bemusement at then-embryonic developments and amazement at the accuracy of forecast extrapolations.

After reading the sentence that follows this one, pause for a moment and guess when it was first written, prior to plunging forward in my own prose:

The amount of effort and money put into artificial intelligence has been quite limited, and there are only about a half-dozen major centers of such activity in the world.

Clearly, this quote is a “few” years old! Consider, for example, that last September Gartner forecasted that worldwide spending on AI would hit $1.5 trillion for that (last) year. The above quote is from renowned astrophysicist Carl Sagan’s treatise, “Broca’s Brain: Reflections on the Romance of Science”, first published in 1979, with which I recently reconnected over a long weekend read.

Most people overestimate what they can achieve in one year and underestimate what they can achieve in ten years. (Bill Gates)

Specifically, it came from chapter 20, “In Defense of Robots”, which in its original form was titled “In Praise of Robots” and appeared in the January 1975 edition of Natural History magazine. Unsurprisingly, given that the source material is more than a half-century old at this point, some of it is charmingly dated. Consider, for example, this chapter excerpt:

There will be strong pressures for continued miniaturization of intelligent machines. It is clear that remarkable miniaturization has already occurred. Vacuum tubes have been replaced by transistors, wired circuits by printed circuit boards, and entire computer systems by silicon chip microcircuitry. Today, a circuit that used to occupy much of a 1930 radio set can be printed on the tip of a pin.

Or, speaking of the current state of intelligent machines, this passage:

The ten best chess players in the world still have nothing to fear from any present computer, but the situation is changing. Recently, a computer for the first time did well enough to enter the Minnesota State Chess Open. This may be the first time that a non-human has entered a major sporting event on the planet Earth…The computer did not win the chess open, but this is the first time one has done well enough to enter such a competition. Chess playing computers are improving extremely rapidly.

And then there’s this, focusing on Sagan’s primary area of expertise, space:

In the exploration of Mars, unmanned vehicles have already soft-landed, and only a little further in the future they will roam about the surface of the Red Planet as some now do on the Moon.

What would Sagan have thought about the fact that, as I’m writing these words, NASA just announced that its Perseverance rover has traveled the distance of a marathon on Mars, notably much of it autonomously? He wouldn’t, I’d argue, be at all surprised. And that, dear readers, is at the core of why I’m focusing on his book, and this chapter in particular, today. To wit, immediately after the prior quote, he elaborated on his prognostication “tease”, writing:

The Viking landers deposited on Mars in summer of 1976 have a very interesting array of sensors and scientific instruments, which are the extension of human senses to an alien environment. The obvious post-Viking device for Martian exploration, one which takes advantage of the Viking technology, is a Viking rover in which the equivalent of an entire Viking spacecraft, but with considerably improved science, is put on wheels or tractor treads and permitted to rove slowly over the Martian landscape.

But now we have a new problem, one that is never encountered in machine operation on the Earth’s surface.  Although Mars is the second closest planet, it is so far from the Earth that light travel becomes significant. At a typical relative position of Mars and the Earth, the planet is 20 light minutes away. Thus, if the spacecraft were confronted with a steep incline, it might send a message of inquiry back to Earth. Forty minutes later, the response would arrive saying something like, “For heaven’s sake, stand dead still!” But by then, of course, an unsophisticated machine would have tumbled into a gully.

Consequently, any Martian rover requires slope and roughness sensors. Fortunately, these are readily available and are even seen in some children’s toys. When confronted with a precipitous slope or large boulder, the spacecraft would either stop until receiving instructions from the Earth in response to its query and televised picture of the terrain, or back off and start in another and safer direction. Much more elaborate contingency decision networks can be built into the onboard computers of spacecraft of the 1980s.

Any sufficiently advanced technology no longer distinguishes itself from pure magic. (Arthur C. Clarke)

The fundamental point of In Defense of Robots, at least per my interpretation of it, is to provide Sagan with a platform to answer a question he posited at the beginning:

The powerful abilities of computing machines to do arithmetic hundreds of millions of times faster than unaided human beings are legendary. But what about really difficult matters? Can machines in any sense think through a new problem? Can they make discussions of the branch-contingency-tree variety with which we think of as characteristically human?

Sagan’s answer to that question was an unqualified “yes”, and here’s what he thought it would look like, again specific to astrophysics and related topics:

In the development of such machines we find a kind of convergent evolution. Viking is, in a curious sense, like some great outsized clumsily constructed insect. It is not yet ambulatory and is certainly incapable of self-reproduction, but it has an exoskeleton, it has a wide range of insect-like sensory organs, and it is about as intelligent as a dragonfly.

But Viking has some advantages that insects do not. It can, on occasion, by inquiring of its controllers on Earth, assume the intelligence of a human being. The controllers are able to reprogram the Viking computer on the basis of the decisions they make.

As the field of machine intelligence advances, and as increasingly distant objects in the solar system become accessible to exploration, we will see the development of increasingly sophisticated onboard computers, slowly climbing the phylogenetic tree from insect intelligence to crocodile intelligence to squirrel intelligence and, in the not very remote future, I think, to dog intelligence.

That said, Sagan was also keen to expand far beyond astrophysics with his forecasts, even to the realm of psychoanalysis. Consider chatbots’ increasingly common use as virtual therapists, albeit with diverse user experiences and outcomes, as you read the following excerpt:

In a time when more and more people in our society seem to be in need of psychiatric counseling, and when timesharing of computers is widespread, I can even imagine the development of a network of computer psychotherapeutic terminals something like arrays of large telephone booths in which for a few dollars a session we are able to talk to an attentive tested and largely non-directive psychotherapist. Ensuring the confidentiality of the psychiatric dialogue is one of the several important steps still to be worked out.

Or consider something a bit “closer to home” for the broad engineering community, that of humanoid and other robotic systems for industrial and other related applications:

If intelligent machines for terrestrial mining and space exploratory applications are pursued, the time cannot be far off when household and other domestic robots will become commercially feasible…There are many common tasks, ranging from bartending to floor washing, that involve a very limited array of intellectual capabilities, albeit substantial stamina and patience.

All-purpose ambulatory household robots, which perform domestic functions as well as a proper 19th century butler, are probably many decades off, but more specialized machines, each adapted to specific household functions, are probably already on the horizon. It is possible to imagine many other civic tasks and essential functions of everyday life carried out by intelligent machines.

Much in life is simply a matter of perspective. It’s not inherently good or bad, a success or failure; it’s how we choose to look at things that makes the difference. (David Niven)

But I can’t help but wonder: was Sagan too sanguine about the societal upheaval caused by AI-powered robotic (and broader AI) supplant?

For the development of domestic and civic robots to be a general civic good, the effect of re-employment of those human beings displaced by the robots must be of course arranged. But over a human generation, that should not be too difficult, particularly if there are enlightened educational reforms. Human beings enjoy learning.

If anything, he seemed more concerned that human beings’ overreaction (at least in his eyes) to such displacement might unnecessarily delay or even preclude this transition and broader transformation, to the broader detriment of our species (thereby at least in part explaining, I suspect, the shift from robot “praise” to “defense” from the 1975 article to 1979 book chapter):

We appear to be on the verge of developing a wide variety of intelligent machines capable of performing tasks too dangerous, too expensive, too onerous, or too boring for human beings. The development of such machines is, in my mind, one of the few legitimate spin-offs of the space program. The efficient exploitation of energy and agriculture, upon which our survival as a species depends, may even be contingent on the development of such machines.

The main obstacle seems to be a very human problem, the quiet feeling that comes stealthily and unbidden, and argues that there is something threatening or inhuman about machines performing tasks as well or better than human beings, or a sense of loathing for creatures made of silicon and germanium rather than proteins and nucleic acids. But in many respects, our survival as a species depends on our transcending such primitive chauvinisms.

In part, our adjustment to intelligent machines is a matter of acclimatization. There are already cardiac pacemakers that can sense the beat of a human heart. Only when there is the slightest hint of fibrillation does the pacemaker stimulate the heart. This is a mild but very useful sort of machine intelligence. I cannot imagine the wearer of this device resenting its intelligence [EDITOR NOTE: as regular readers will likely already understand, I particularly resonated with this point].

I think in a relatively short period of time there will be a very similar sort of acceptance for much more intelligent and sophisticated machines. There is nothing inhuman about an intelligent machine. It is indeed an expression of those superb intellectual qualities that only human beings, of all creatures on this planet, now possess.

Whether or not you resonate with Sagan’s perspectives in the excerpts I’ve shared, I suspect you’ll (near-)universally agree with my admiration for the accuracy of his prophecies, along with the rare combination of intelligence and open-mindedness (with at least one notable exception) that were at their foundation. Regardless, I encourage you to pick up a copy of Broca’s Brain: Reflections on the Romance of Science and give it a read for yourself.

It’s only $6.99 on Kindle as I write this (and as I read it), and I also commonly come across both hardcover and paperback copies of it at used bookstores. There’s always also your public library, of course. And worst case, I stumbled across a YouTube video of someone reading the (bulk of the) text of the In Praise of Robots chapter:

Fair warning: there’s at least one several-paragraph section missing (I suspect due to a multi-“take” merging edit error, not intentionally), ironically the one from which the quote that opened this writeup came. And the regularly changing “psychedelic” special effects (which I suspect were an attempt, apparently successfully, to circumvent copyright infringement algorithms) compel me to encourage you to focus solely on the audio. But, hey…free!

Regardless of how you end up consuming Broca’s Brain, I hope you find it a fruitful experience, versus a waste of time. Be sure to come back here afterward and share your thoughts in the comments, ok? Thanks!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Carl Sagan’s prescient thoughts on AI and robots appeared first on EDN.

Samsung’s PM1763 PCIe 6.0-based enterprise SSD features 9th-generation V-NAND flash memory and a new 4-nm controller. Optimized for AI and HPC servers, the drive is available in 4-TB, 8-TB, and 16-TB capacities. The 16-TB model delivers sequential read and write speeds of up to 28,400 MB/s and 21,900 MB/s, respectively—up to twice the performance of its predecessor, the PM1753.

According to the company, the PM1763 can transfer a 40-GB LLM in approximately 1.4 seconds, helping minimize data latency between processors and accelerators while improving overall AI processing efficiency. The SSD is optimized for liquid-cooled server environments through direct-to-chip cooling. This design enables sustained peak performance while improving power efficiency by up to 1.8 times compared to the previous generation.

To address security requirements for AI and virtualized infrastructure, the PM1763 supports post-quantum cryptography (PQC), the Security Protocol and Data Model (SPDM) 1.4, and Commercial National Security Algorithm (CNSA) 2.0. It also provides link encryption based on the TEE Device Interface Security Protocol (TDISP) to reinforce data protection across storage interfaces.

Samsung has now begun mass production of the PM1763 SSD.

PM1763 product page 

Samsung Electronics  

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Using a vertically stacked-die design, AOS’s DFN6×5 AmpStack package integrates two MOSFETs configured as a high-side/low-side half-bridge. It increases power density and maximizes available PCB space compared to a solution using two discrete DFN5×6 MOSFETs. The package enables high-density power conversion applications ranging from megawatt AI factories to power tools.

The AOPL66801 80-V MOSFET showcases the new half-bridge package with an optimized switch-node clip connecting the high-side and low-side MOSFETs. This architecture minimizes parasitic inductance within the package. Compared to a standard discrete solution, it also reduces PCB parasitic inductance, minimizing phase-node voltage ringing and decreasing stress on the MOSFETs. Key specifications for the AOPL66801 include:

An integrated Kelvin sense pin maintains gate-voltage stability during high di/dt switching. The dedicated connection provides a more effective high-side gate-drive path, helping reduce switching losses. The device also supports a maximum junction temperature of 175 °C for increased thermal capability.

The AOPL66801 is available now in production quantities with a 16-week lead time. Pricing is $6.16 per unit in 1000-piece quantities.

AOPL66801 product page 

Alpha & Omega Semiconductor 

The post Stacked-die half-bridge boosts MOSFET power density appeared first on EDN.

The Vishay 34 PHE absolute position sensor provides 10-turn linear or rotary displacement sensing with a 3600° range. Using non-contact Hall-effect technology, it delivers up to ±1% linearity (full stroke), 1° resolution, and a service life of more than 10 million cycles.

According to Vishay, the 34 PHE is priced 40% lower than previous-generation devices. It is designed for servo loop motion control systems requiring high accuracy and long-term stability in harsh environments. Typical applications include industrial motor and actuator displacement tracking, solar panel alignment systems, and flow control valve positioning.

The sensor features IP65 sealing and withstands vibration up to 20 g and shock up to 50 g. Integrated reverse-voltage and overvoltage protection (−14 VDC and +28 VDC) reduces the need for external protection circuitry. It supports single or dual analog ratiometric outputs or a digital PWM output. In dual-output mode, the two channels track position in opposite directions to enable basic fault detection. The 34 PHE reports its position immediately after power-up, even following a power loss, without requiring recalibration, homing, or initialization.

Samples and production quantities of the sensor are available now, with lead times of 14 weeks.

34 PHE product page 

Vishay Intertechnology 

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VeriSilicon’s CPP2000 Camera Post-Processing IP improves image quality for reliable vision performance in robotics, drones, and other mobile vision applications. It is designed for straightforward SoC integration and processes YUV images from image signal processors using a range of image enhancement techniques.

The IP supports image and video processing at up to 8K resolution, applying motion-compensated temporal filtering, advanced spatial noise reduction, chroma adjustment, dynamic contrast enhancement, and edge enhancement to improve noise suppression, sharpness, contrast, and overall detail fidelity.

The CPP2000 is implemented as a modular, streaming hardware pipeline in which each stage operates as a dedicated accelerator, enabling continuous real-time processing from input to output. Multiple hardware configuration options are available to address varying requirements for power, performance, area, and latency across applications.

CPP2000 product page  

VeriSilicon

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Taiyo Yuden has introduced the HVX(-K) and HTX(-K) series of AEC-Q200-qualified conductive polymer hybrid aluminum electrolytic capacitors. The 46-device lineup is intended for noise suppression and power smoothing in power supply circuits for automotive control and safety functions such as power steering and ADAS.

The hybrid capacitors provide improved capacitance characteristics over the earlier HVX and HTX series. For instance, the 80-V RAHTX181M1RGP5005K offers a capacitance of 180 µF and a rated ripple current of 3900 mA RMS at 135°C. The devices are available in seven case sizes, with diameters of 6.3 mm to 12.5 mm and heights of 7.7 mm to 16.5 mm.

By combining a conductive polymer with an electrolyte solution, the hybrid capacitors achieve the low ESR of conductive polymers while retaining the self-healing properties of aluminum electrolytic capacitors, enhancing both performance and reliability.

The HVX (-K) and HTX (-K) series are now in production. Detailed information can be found here.

Taiyo Yuden

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A self-heated Darlington transistor pair makes a simple, sensitive, and sturdy airflow sensor. But first an annoying non-linearity needs unbending.

If you take a self-heated transistor in a TO-92 package and force it to hold a constant temperature differential above ambient, the power input required to keep it stuck to setpoint will be determined by its thermal impedance ZT relative to the air, as given by:

ZT = ZJ + 1/(SC + KT √AF )

where:

ZJ = junction-to-case thermal impedance = 44°C/W
SC = still-air case-to-ambient conductivity = 6.4 mW/°C
KT = “King’s Law” thermal diffusion constant = 0.75 mW/°C√fpm
AF = air flow in ft/min

Wow the engineering world with your unique design: Design Ideas Submission Guide

The AF term suggests the arrangement might be handy for air flow measurement, because of the way it makes ZT, and therefore power input for a given differential, a function of air speed.  Figure 1 shows the resulting power vs AF relation a differential (Dt) = 31oC. Do note, however, the annoying non-linearity.

Figure 1 This graph shows the power dissipated vs air speed of a TO-92 held at a constant 31oC above ambient Pw = 31/ZT.

Figure 2 shows a practical thermostat circuit to achieve and maintain this delta-T while outputting a signal predictably related to Pw.  It utilizes a Darlington sensor transistor pair (Q1 and Q2) to compensate for ambient temperature and convert the resulting nonlinear Pw curve into a linearized airflow readout.  Its current mode output is compatible with the long cable runs often seen in airflow measurement applications.

Figure 2 This linearized Darlington anemometer circuit supports a 4-20mA current mode output.  Adjust R10 to calibrate 4mA (zero fpm), R11 to calibrate 20mA (250fpm).

Here’s how it works.

Q1 serves as the self-heated sensor modeled in the Figure 1 math, with Q2 providing ambient temperature compensation.  Opamp A2 runs a feedback loop that forces the Vbe differential between Q1 and Q2 (and thus the temperature differential between Q1 and ambient) to hold a constant 31oC.  It does this (with the help of Darlington current gain) by forcing Q1’s current draw (I) through R3 to drive Q1’s power dissipation (Pw) to follow the fig.1 curve of heat-vs-air flow.  The resulting voltage developed (IR3) is the basis of the air speed measurement.

Okay so far.  But how does compensation for Figure 1’s nonlinearity happen?   Well, happily the function of Q1’s Pw vs collector current I isn’t linear either.  In fact Pw = 5vI – I2R3.  That quadratic I2 term is the key.  It creates the lovely linearizing curve shown in Figure 3.

Figure 3 This graph details Q1 power dissipation vs  collector current.  Pw = 5vI – I2R3.

The 2nd-order curvature of Figure 3 compensates for the bend in Figure 1. Although the match isn’t perfect, when converted to the 4-20mA by opamp A1, the realized output is a calibrated readout of air speed that differs from ideal by less than +/- 5% from 0 to 250fpm, as shown in Figure 4.

Figure 4 This graph’s data relates anemometer output vs airspeed: FPM = 15.6(Iout – 4mA) +/-10FPM.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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The post Solid state airflow sensor with linear 4-20mA output appeared first on EDN.

The costs of designing and producing an analog ASIC chip can be grouped into three main parts: human capital, software tools, and prototype fabrication. While all three are equally critical to success, it’s important to note that design tools and wafer foundries are ubiquitous. All semiconductor companies have equal access to them, and it’s rare that a problem with the performance of an analog ASIC comes from the tools used or the wafer foundry that produced it.

Human capital: The ultimate differentiator

If you’re considering an analog ASIC, specification development, circuit design, and physical layout are the most critical steps. These are the true differentiators between the “doers” and “pretenders” (for more on this, read my article “For a Successful Analog ASIC, First Weed Out the Pretenders”).

They require the highest level of analog design skills. I’m referring to teams of craftsmen that have done hundreds of complex precision analog chips that meet requirements others said were impossible. These individuals typically have 30 to 40+ years of experience and can command salaries exceeding $350K per year. They are scarce, they are expensive, and they are worth every penny.

If you remember one thing from the paper mentioned above, let it be this: human capital is the ultimate differentiator.

The feasibility study: De-risking the design

It all starts with a feasibility study conducted by the engineers who will be designing the chip. Figure 1 below shows the steps involved.

Figure 1 The feasibility study must be conducted by the engineers designing the chip. Source: Javelin ASIC Devices

The feasibility study is a risk aversion step intended to identify and quantify risks and establish a plan to mitigate them for a successful result. Additionally, it allows the design team to quantify the time required to do the design and assess a fixed cost to complete it.

Done properly, it can take up to two months to complete the study; more if significant invention is involved, less if the chip is an amalgamation of off-the-shelf existing silicon. These costs range from $20K to $70K and are always credited to the full development if a contract is executed. Since some simulation is required, costly software tools are involved early on.

Figure 2 Human capital and software tools unite in the design phase. Source: Javelin ASIC Devices

Design phase: From specification to architecture

Several things occur during the design phase. The preliminary specification becomes a working document and grows from a 4–6-page product definition paper to an in-depth datasheet that may well exceed 50 pages, becoming more detailed with minimum and maximum limits, definitions of registers, power requirements, and more.

The thoroughness of the datasheet is a measure of the craftmanship of the design team. The datasheet drives the wafer fabrication process selection that matches the requirements for voltage, current, noise, precision, cost, and more to the most optimal foundry and a specific process.

The architecture of the ASIC is defined in functional blocks and teams with decades of experience with those blocks (charge pumps, 24-bit and higher A/D converters, precision low-drift Vrefs, and chopper-stabilized amplifiers) are created and assigned. Whenever possible, programmability using registers is added to tighten Gaussian distributions and maximize yields.

Collaboration, reviews, and designer governance

Weekly calls with the customer’s engineers are scheduled to report on status progress and offer design alternatives that may improve performance, reduce chip size (cost), avoid environmental impacts (electrical noise and temperature variations), add functionality, and more. At the completion of each major block, a design review should be scheduled with the customer’s engineering team that dives deep into a transistor-level explanation of how each aspect of the block works. It includes schematics, simulation result targets compared against specification requirements, and an overview of any external components required.

Software design tools are acquired for the duration of the project. Quarterly calls with customer corporate management are established to review schedules and cash flows. Digital teams are assembled to manage logic, memory, and register requirements.

Test strategy: Third-party vs. custom systems

In parallel with the design of the ASIC itself is the design of the test system. Sometimes evaluating a precision analog ASIC can be as challenging as the chip itself. There are two schools of thought. One is to generate a test specification to be supplied to a third-party test house that fits the capabilities of their array of commercially available test systems.

These companies will review the specifications and recommend which brand of tester is best suited. They will charge a one-time fee for the development of any unique hardware and software program needed to interface your ASIC to their tester. Getting everything up and running can easily cost between $100K and $200K.

An alternative that Javelin uses is to develop a custom test system, specifically tailored for the ASIC. We build two identical systems—one for the wafer probe and one for the final test of the packaged chip. They can be collocated in any test house and interface with the required handlers, or they can be stand-alone.

We prefer this approach because it assures perfect correlation between the wafer probe and final testing. And surprisingly, it’s less expensive. This approach offers complete flexibility in moving testing from one location to another without incurring duplicated tooling costs.

Custom ASIC economics vs. commodity products

When a commodity analog semiconductor company develops a standard product intended to be sold to thousands of disparate customers, they absorb all development costs and amortize it into their unit pricing, hoping their marketing department has identified sufficient sales potential to recover the costs and still show a profit in the long term.

However, when a custom ASIC is involved, the story changes slightly. There is only one customer, and it’s responsible for paying for the complete development. In exchange, it gets exclusivity to the chip.

Exclusivity is important because the justification for paying development costs often includes integrating proprietary IP or creating new inventions to achieve performance advantages over competitors using off-the-shelf components. Other advantages include a significantly smaller size, lower power consumption, protection from product obsolescence, and much more.

Software tools: Powerful but expensive

Although the development costs associated with creating the new IC also include wafer fabrication and package assembly, I want to stay focused on human capital and software tools for a moment. There’s more to it than meets the eye. For those not familiar with chip development costs, the numbers can be intimidating.

While the semiconductor industry often focuses on the multi-billion-dollar capital expenditures of leading-edge digital nodes, the economics of analog IC development follow a distinctly different trajectory. Development does not involve huge capital equipment investments. The investment comes in the form of human capital and tool rental.

Over the past few decades, the tools for supporting analog chip design have improved dramatically, driven in part by the growth in analog applications in automobiles, consumer products, and sensor calibration and signal conditioning, in which precision and accuracy, along with quality and reliability, are of paramount importance. A few of the most popular tools used by analog designers include Cadence Virtuoso and Spectre, Synopsys Primetime, and Mentor Graphics Calibre.

Regardless of whom you select to do your analog ASIC, they will likely use these same tools, as they are available to everyone. However, they are expensive and these costs need to be accounted for. Prices aren’t published and NDAs prevent users from disclosing them, but estimates for a single, fully featured seat for analog/mixed-signal design (layout and simulation) range from $150k-$300k per year. A seat is typically one “open window” for one user, so you can see how the dollars add up quickly.

Prototype fabrication and mask costs

Most silicon fabricators offer multi-product wafers (MPW) for some or all of their processes. These are highly valuable tools for seeing silicon samples at a low cost. They afford the ability to locate and remove any errors prior to production.

On popular processes, they are run monthly, but on others they are run less so, maybe two, three, or six times a year. If you miss the window with an available tape-out, it could be a long wait. MPWs are not required, but when available, they are an important step in evaluating early silicon and debugging test systems well ahead of production.

Whether engaging an MPW or not, the final significant tooling expense is the production mask set. Prices vary from wafer fab to wafer fab and are dependent on the number of masks required to make the ASIC. Figure on spending $75K to $150K.

Figure 3 Test and assembly operations are a critical part of ASIC fabrication costs. Source: Javelin ASIC Devices

Experience matters: Mitigating risk in ASIC development

If an off-the-shelf new chip design runs into a problem, the semiconductor company has the option to simply delay introduction while their engineers sort things out. That is not an option for your ASIC. You are counting on it to be available on a specific date to support the launch of your new or next-generation product.

Don’t be fooled by companies claiming they have been in business for 20 or 30 years. That means very little. What’s important is the experience of the folks doing the work. How long has each engineer been designing analog ASICs?

Everyone makes mistakes, but mistakes are part of learning. You need teams that have made the mistakes decades ago and learned from them. Don’t let your project become a learning experience for novices. You deserve to see the resumes of the people responsible for your ASIC. Ask to see them and insist on speaking with the engineers themselves.

Which brings up another point: you deserve to have direct access to any engineer working on your ASIC. Don’t accept some project manager or marketing manager acting as a gate keeper to be the focal point for all communications between you and your supplier. They add no technical value and insert delays in communications, which more often than not are time critical.

Bob Frostholm is co-founder and CMO of Javelin ASIC Devices.

Related Content

• Analog ASICs Made Simple
• 7 Steps to a Successful Analog ASIC
• Demystifying Analog and Mixed-Signal ASICs
• 7 myths of analog and mixed-signal ASIC design
• A 12-point overview of the advantages of custom analog ASICs

The post Understanding all costs involved in analog ASIC development appeared first on EDN.

Part 1 of this min-series established why CXL Type 3 memory expanders matter for capacity-bound workloads and where expander memory sits in the latency–capacity pyramid relative to local DRAM. It also explained what must align across the stack before memory becomes usable—CPU and BIOS enablement, kernel CXL support, device firmware, RAS paths, and the NUMA topology that Linux exposes through cxl_pci. Next, it delved into why many CXL problems surface, such as placement or bandwidth imbalance rather than obvious enumeration failures.

This part builds on that foundation with the tools and timeline you need day-to-day to navigate system bring-up. You will learn which user-space utilities reveal what the OS actually sees on the CXL fabric, how to differentiate between “device present” to “memory consumable,” and how to walk the boot sequence from slot power and DRAM training through DVSEC discovery, CEDT read, CDAT delivery, ACPI handoff, and finally driver bind-framing each stage as a validation checkpoint with recognizable failure signatures.

Let’s get to work.

Kernel drivers establish whether a CXL Type 3 device is present, configured, and represented as memory, but validation engineers spend much of their time during bring-up reconciling what firmware advertised, what the driver registered, and how user-visible policy (NUMA placement, DAX/region modes, namespace layout) matches the intended deployment. That reconciliation is difficult from dmesg and kernel logs alone. Practical programs rely on a small set of user-space utilities that expose sysfs and kernel abstractions in forms suitable for automation and field triage.

Essential user-space tooling

cxl/libcxl (often shipped with ndctl sources as “CXL tools”)

The cxl command-line interface and libcxl library walk the CXL sysfs hierarchy—ports, endpoints, memdevs, and decoders—and print structured output, commonly JSON. This is the closest thing to a standard “show me what the OS thinks on the CXL fabric” tool; serial numbers, capacity hints, which PCI function hosts a memdev, and whether decode topology looks sane before debugging performance or NUMA. It’s usually the first stop after dmesg when firmware and driver disagree about what should be visible.

ndctl

ndctl provides user-space administration for the LIBNVDIMM/regions/namespaces model that Linux also uses for some persistent-memory-class bring-up paths. Depending on kernel and platform integration, CXL-attached memory may surface as a separate NUMA node or through PMEM-style abstractions. ndctl lists regions, creates or destroys namespaces, and clarifies whether capacity is in a state software can consume, not merely whether a PCI device exists.

daxctl

daxctl manages direct-access (DAX) devices and related system-RAM or devdax configuration knobs exposed by the kernel. Some deployments expose memory through DAX-oriented paths, especially when treating capacity like PMEM/DAX rather than only anonymous DRAM. daxctl helps verify mode, online/offline behavior, and whether the system matches workload expectations. Misconfiguration here often looks like “memory is there but unusable, wrong interface, or wrong policy.”

numactl and numastat

numactl controls NUMA placement policy; numastat reports per-node memory statistics. Expander memory frequently lands as a separate NUMA node or as far memory relative to a socket. These tools prove placement hypotheses during bring-up, bind threads and allocations, measure local versus remote behavior, and catch cases where OS defaults silently place hot pages on CXL. Many “CXL is slow” bugs are NUMA policy bugs, not link bugs.

acpica-tools

This suite provides a useful utility, acpidump, which extracts ACPI tables from the kernel and dumps the raw values of the specified ACPI table. While a user should not need this during regular bring-up, it can be very useful in sticky situations when the DDR memory enumerates but does not show up either as a NUMA node or as a PMEM device. In such cases, it might be useful to dump certain acpi tables and parse raw values via a debug script.

lspci and setpci (pciutils)

Since CXL Type 3 memory expanders attach over a PCIe/CXL link, pciutils belongs in every bring-up kit alongside CXL-specific tools. lspci lists PCI functions on the bus, reports vendor and device IDs, class codes, negotiated link speed and width, and—when invoked with verbose flags—the extended capability chains that expose CXL and DVSEC registers. It’s often the fastest way to confirm that the endpoint is visible at the transport layer, that link training reached the expected generation and lane count, and that the kernel bound the intended driver (for example cxl_pci).

setpci reads and writes configuration-space dwords for targeted experiments during debug—checking capability offsets, toggling test bits where platform policy allows, or verifying that firmware left key control fields in the expected state. Used together, lspci answers “what does the bus see?” (peek) and setpci supports “can we inspect or adjust a specific config field?” (poke) before diverting attention to higher-level CXL utilities or firmware logs.

Topology and observability helpers

lstopo/hwloc produce human-readable CPU–memory topology maps—useful to confirm how the OS labels CXL memory relative to sockets. lspci/setpci (pciutils) confirm the PCI/CXL function at the bus level when debugging binding (cxl_pci versus overrides) and link issues. A verbose lspci dump reveals device capabilities that Part 3 decodes in detail.

Another, currently open-source, tool for viewing the PCIe hierarchy is pcicrawler, which shows the PCIe topology similar to lspci but in a nicer format.

From power-on to usable memory

The end-to-end path for a CXL Type 3 memory expander runs from first application of host and slot power to the point the operating system can issue CXL.mem accesses to host-managed device memory (HDM). Exact timing and responsibility splits vary by CPU, root complex, memory expander ASIC, and BIOS, but the dependencies recur. In other words, power and clocks before reset release; DDR readiness before credible capacity reporting; configuration-space discovery before decode programming; and table exchange before stable OS topology.

Boot sequence is shown for a system with CXL memory expander. Source: Author

1. Power, clocks, and ASIC bring-up

The sequence begins when host platform and slot power are applied. The expander ASIC must reach an internally consistent state: regulators settle, oscillators stabilize, PLLs lock, and on-chip reset completes so an embedded control processor can execute first-stage firmware. The host must provide a stable PCIe reference clock and manage PERST# deassertion per PCIe/CXL electrical requirements, so the endpoint is not expected to train before clocks and power are valid. During this phase, the device is not yet advertising complete HDM metadata.

2. On-device DRAM: controller release, training, and SPD

The ASIC releases reset to the DDR controller and run DRAM initialization and training for attached DIMMs. Firmware discovers configuration and capacity through serial presence detect (SPD) reads. In parallel, the ASIC initializes high-speed SerDes and the PCIe/CXL controller. There is a critical interval where HDM must not be treated as authoritative.

Firmware clears or gates HDM metadata until DRAM discovery completes—conceptually mem_info_valid = 0. Only after capacity and layout are known does firmware program HDM-related fields in PCIe extended configuration space via CXL-designated vendor-specific extended capability (DVSEC) structures and assert mem_info_valid = 1.

3. PCIe link training, DVSEC, and HDM registration

As link training toward the host begins, firmware populates HDM capability structures through DVSEC containers—HDM instance count, per-region sizing, and validity flags. Setting “memory info valid” is the device’s contract that subsequent host reads from HDM descriptors consistent with trained DRAM.

4. PCIe/CXL link up and configuration-space discovery

When the physical link reaches DL_Up at negotiated width and speed, the host enumerates the endpoint as a PCI function, parsing capability lists to discover CXL entries, DVSEC registers, and HDM decoders.

5. Decode programming and mem_enable

Platform firmware must program host-side address decoding, so HDM contributes to the system physical address map. A common milestone is establishing the system physical address window and asserting memory enable (mem_enable). When mem_enable is recognized, device firmware may finalize the coherent device attribute table (CDAT) for OS/firmware NUMA heuristics.

6. CDAT delivery via DOE and mailbox exchange

CDAT is typically transported using data object exchange (DOE) over CXL.io. The CXL mailbox command interface supports diagnostics and device management. Treat DOE/CDAT success and mailbox responsiveness as separate health checks.

7. Firmware table construction and OS handoff

Host firmware synthesizes ACPI tables, including CXL Early Discovery Table (CEDT), System Resource Affinity Table (SRAT), and Heterogeneous Memory Attribute Table (HMAT), exposing HDM ranges as distinct memory affinity domains—often NUMA nodes.

8. OS driver binding

On Linux, cxl_pci binds to the PCI/CXL function, exposes memdev objects, and enables memory to be onlined. Once complete, the host can issue CXL.mem loads, stores, and DMA through the programmed decode window.

Read the boot flow as a chain of implied tests—power/clock/PERST, DDR training, valid HDM, stable link, decode/mem_enable ordering, CDAT/DOE liveness, ACPI coherence, driver bind, and memory online. Failures produce characteristic signatures at each stage.

Part 3 applies this framework to hands-on test and debug: lspci field interpretation, NUMA verification with numactl, memory-mode configuration with daxctl, and workload tools for bandwidth and stress validation.

Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).

Editor’s Note

Part 1 of this mini-series on CXL Type 3 memory technology explains why AI and data-intensive workloads are driving interest in memory expanders and how CXL Type 3 devices differ from local DIMMs even when they appear as ordinary RAM. Part 3 covers integration modes and when boot parameters apply.

The views and content of the article are author’s own and not affiliated to any of his current or previous employers.

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This noise generator has an adjustable bandwidth and a consistent amplitude no matter what bandwidth is selected.

When working on a recent Design Idea for an adjustable filter, I wanted to use an electrical noise source to generate an FFT spectrum graph on my oscilloscope. To set up the test, I reached for my signal generator, which I knew had a noise generator option. I hooked the signal generator to the filter input and the scope to the filter output and turned on the scope’s FFT display function. I then set the filter to 10 kHz and set the signal generator noise standard deviation to its maximum of 3.0 volts.

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The output of the filter was a minuscule signal. Here’s what I’d ignored – the signal generator outputs a white noise signal with a 3.0 v standard deviation, but its bandwidth is 25 MHz. When I reduced the bandwidth with the filter, the amplitude dropped. With a perfect brick wall filter, this would reduce the standard deviation by the square root of (10 kHz/25 MHz). So, the 3.0 v standard deviation becomes about 60 mV after filtering. This small signal can be easily corrupted by noise existing in a test setup.

This standard deviation reduction comes from the way white noise signals add. Basically, if a signal is uncorrelated white noise and you add it to a second uncorrelated white noise source of the same standard deviation, the combined signal’s standard deviation will increase by the square root of 2. Alternately, when you filter out half of the spectrum of a noise signal with a brick wall filter, the standard deviation will decrease by the square root of 2.

It occurred to me that a noise signal generator should compensate for this reduction if you want to use a narrower portion of its bandwidth. For example, if the project under test is a device for audio, maybe you only need a noise source spanning only up to 50 kHz. Or maybe you’re testing a signal chain’s response for a low-frequency vibration sensor; in this case maybe a 1 kHz span is enough. But in either example you will want the signal’s standard deviation to be large enough to get a clean FFT.

So, how would I create a testing device to give me a noise generator that has an adjustable bandwidth and a consistent amplitude no matter what bandwidth is selected? The first thought was the typical white noise generator created with reversed biased Zener diode or base-emitter transistor junction followed by an adjustable low-pass filter and then an amplifier with some form of automatic gain control (AGC). But then it occurred to me that a micro I’d used recently has a random number generator and a fairly fast DAC for output…hmm.

Let’s take a look at what I came up with (Figure 1). First the name – the concept for this project idea is a Bandwidth Adjustable Noise Generator, which gives rise to the device’s nondescript acronymic moniker of “BANG”. The BANG is a micro-based generator that allows you to set the bandwidth you desire using a touchscreen. It then generates a noise signal with the standard deviation digitally compensated for that bandwidth.

Figure 1 The BANG is a micro-based generator that allows you to set, on a touchscreen, the bandwidth you desire. It then generates a noise signal with the standard deviation digitally compensated for that bandwidth. The device also has a knob to manually adjust the generated signal.

The device also has a good old-fashioned knob to manually adjust the generated signal somewhat, so you can tweak it. Its output has a maximum output of around 3.1 v and is available as an AC signal (biased at 0 v) or a DC signal (biased at around 1.65 v). The bandwidth adjustment of the noise signal goes from 225 kHz to 500 Hz, and this adjustment is accomplished using an LCD and touchscreen.

The hardware

The heart of the BANG is a Microchip Technology ATSAMD51 processor. The adjustable digital filter project mentioned earlier also used a ATSAMD51, which has a true random number generator (TRNG). It’s best to let the Microchip data sheet describe this feature:

The True Random Number Generator (TRNG) generates unpredictable random numbers that are not generated by an algorithm. It passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 140-3.”

These 32-bit numbers sound perfect for constructing a noise signal source! Using the same processor as before also meant I could reuse a large portion of the LCD and touch screen code, IIR digital filter code, battery monitor code, and various other initialization and housekeeping pieces. Besides the micro, another major piece of the design is the touchscreen, which is an ILI9341 2.8″ 240×320 pixel TFT LCD with a SPI interface.

The other major electronic piece is the analog back end (ABE). One part of the ABE is a reconstruction filter (sometimes referred to as an anti-imaging filter) attached to a DAC on the micro. It essentially filters out-of-band high frequency content carried along with the digitally generated noise signal as it is sent out of the DAC. The filter is a 4-pole Sallen-Key low pass filter with a cutoff frequency of 250 kHz (I used TI’s Webbench filter design tool to calculate the component values). The ABE section also has a potentiometer-adjustable gain stage from around 0.25x to around 2.5x of the ADC signal. The last part of the ABE is a simple output buffer driving the AC and DC outputs. Figure 2 shows the complete schematic.

Figure 2 The heart of the BANG is a Microchip Technology ATSAMD51 processor.

There are a few odds-and-ends on the schematic that I haven’t mentioned yet. First, the micro format I used is an Adafruit Feather M4 Express Arduino board, powered via USB or, alternately, a 3.7 v lithium polymer battery. The Arduino board also contains a charger for the battery. Being able to power it from the battery may be more convenient in some situations, and better yet, it can provide ground isolation if desired in your setup.

The USB pin shown is actually a regulated 3.3 v source that is used to power the rest of the circuitry. You’ll also notice a voltage divider, connected to an ADC on the micro, used to measure the USB voltage for display purposes. The ON/OFF switch actually connects to the EN (enable) pin. The BANG is powered off when the EN pin is pulled to ground. A Vcc/2 reference circuit can also be seen and is used to provide a center voltage for the single-supply operated op-amps.

More to come

Next time, I’ll describe the BANG’s firmware, integration, and operating results. Until then, I welcome your thoughts in the comments on what I’ve discussed so far!

Note that the schematic, code, 3D print files, Arduino software, links related to various parts of the project, and additional notes and pictures on the project’s design and construction can be downloaded for free at the MakerWorld website.

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

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The post Making noise with a BANG, part 1: Concept and hardware appeared first on EDN.

It seems as if every technical advance these days is either directly related to AI software and data centers, or at least tries to establish such a connection, even if that connection is somewhat of a tenuous “stretch.” Despite this, there are a lot of innovative and interesting projects underway that are very analog-centric, with little or no AI association. These advances show what “small” analog can do, where small refers to both physical size and focused functionality.

Consider a neural implant dubbed the Microscale Optoelectronic Tetherless Electrode, or MOTE, developed at Cornell University (Figure 1). Measuring about 300 microns long and 70 microns wide (yes, that’s microns), researchers maintain it’s the smallest neural implant capable of wirelessly transmitting brain activity data.

Figure 1 This brain-implantable MOTE measures just 300 microns long and 70 microns wide and requires no tether or wireless RF link for power or data. Source: Cornell University

It’s connected via red and infrared laser beams that pass harmlessly through brain tissue. The MOTE transmits data back using tiny pulses of infrared light, which encode the brain’s electrical signals. An aluminum gallium arsenide (AlGaAs) semiconductor diode both captures light energy to power the circuit and emits light to communicate the data.

The device also includes a low-noise amplifier and optical encoder, all built using the standard CMOS process technology. The optical link uses pulse position modulation (PPM) for its data encoding as that format is very power efficient, especially in this situation (Figure 2).

Figure 2 System overview shows a MOTE implanted in an awake mouse brain to chronically record neural activity in vivo—incoming light powers the MOTE, and the MOTE, in turn, emits the PPM pulses communicating the recorded data (a). Optical microscopy image compares a MOTE with a strand of human hair (b). MOTE is powered and is communicating optically; it’s continuously powered at a shorter wavelength and communicates at a longer wavelength, making the powering system easier to implement and avoiding power–communication crosstalk (c). Source: Cornell University

The dual-use diode, dubbed a photovoltaic light-emitting diode (PVLED), provides space-saving benefits, functioning as both an LED and a data-link transmitter. An external 623-nm LED source provides power to the PVLED, while MOTE emits 825-nm PPM pulses that encode electrophysiological signals.

The diode is used as a photovoltaic for 93.4% of the time and as an LED for 0.06% of the time, with the remainder of the time spent on transitions. By concentrating the transmitted power into short, bright pulses and encoding information in the timing of those pulses, PPM is much more resistant to noise than amplitude modulation and is very power efficient.

Atomic layer deposition (ALD) of SiO2, Si3N4 and Al2O3 encapsulates MOTE against corrosive biological media without substantially increasing its volume (total encapsulation thickness is under 1.5 µm). High-pressure platinum (Pt) sputtering then provides not only favorable electrode impedance but also an effective and conformal light shield to prevent incident light from generating unwanted photocurrents in the electronics. Critically, each fabrication step is done in parallel, simultaneously fabricating close to 100 MOTEs per chip—and scalable to thousands of MOTEs per square centimeter of silicon (Figure 3).

Figure 3 Bulk fabrication of MOTEs (left) integrating two disparate technologies—CMOS (silicon based) and PVLED (AlGaAs based)—and a cross-sectional view (right) of a fully fabricated MOTE illustrating how the ALD dielectrics and sputter Pt together constitute a shield against biological media and unwanted photocurrents. Source: Cornell University

The underlying CMOS circuits provide low-noise amplification, stable biasing and PPM encoding, and drive the PVLED as an LED (Figure 4). Overall power budget is miserly: nominal power consumption is just one microwatt, divided among the amplifier (50.0%), encoder (10.5%), LED driver (26.2%), and support circuits (13.3%).

Figure 4 Systemic description of a MOTE and its external counterpart for communication—MOTE’s output PPM pulses are detected by an external photodiode before being passed through a decoder (a). Schematics of the front-end amplifier based on pseudo-resistors (left) and the charge pump for optical pulse generation shown on the right (b). Power and area distributions of a MOTE in which the amplifier and filter take most of the power for low-noise amplification (left), and the frame and integration overhead for protection against unwanted light and photocarriers take most of the area, as shown on right (c). Source: Cornell University

How well did they do?

By design, incident LED irradiance is limited to less than 70 mW/mm2, well below the allowed threshold of 250 mW/ mm2, which may inflict heat damage in the brain. The team first performed Petri-dish “static” tests before moving on to live rats. The heads of the implanted live mice were “restrained” while computer-controlled motor moved a rod to stimulate a whisker of an awake, head-fixed mouse.

The implant successfully recorded spikes of electrical activity from neurons as well as broader patterns of synaptic activity—all while the mice remained healthy and active. In two of the six implanted mice, they placed MOTEs on the brain surface, from which they were able to measure the electrocorticographic (ECoG) signals; in the other four mice, they inserted MOTEs into the barrel cortex.

As expected, MOTEs captured the neural responses to whisker stimulations and transmitted the neural signal spike. MOTES were left in the test “subjects” for up to 300 days and continued to function, although there was some degradation in performance, which the Cornell researchers attribute to deterioration of the platinum electrodes.

Why even bother with such a project, rather than using conventional “stick-in” electrodes? In addition to the obvious limitation imposed by the associated wired tether or even a wireless interface attached to the rat, one of the motivations is that traditional electrodes can irritate the brain as the tissue moves around the implant and thus can trigger an immune response. Their goal was to make the device small enough to minimize that disruption while still capturing brain activity faster than imaging systems, and without the need to genetically modify the neurons for imaging.

In you want to know more about the project, its circuitry, and the test results on the rats (I didn’t feel the need to go into detail on that!), check out their detailed and highly readable paper “A subnanolitre tetherless optoelectronic microsystem for chronic neural recording in awake mice” published in Nature Electronics.

Whether it’s rat implants or something non-biologic, these projects—with their tight focus, custom die, minimized number of functional blocks, and no frills or features beyond what is absolutely needed—show what analog designs can do in micropower and microsize designs, and that innovative analog design has not reached a terminal point. As the late, great analog designer Bob Pease liked to remind us, “one good op amp can do more than a thousand logic gates.”

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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