EDN Network

Samsung’s PM1763 PCIe 6.0-based enterprise SSD features 9th-generation V-NAND flash memory and a new 4-nm controller. Optimized for AI and HPC servers, the drive is available in 4-TB, 8-TB, and 16-TB capacities. The 16-TB model delivers sequential read and write speeds of up to 28,400 MB/s and 21,900 MB/s, respectively—up to twice the performance of its predecessor, the PM1753.

According to the company, the PM1763 can transfer a 40-GB LLM in approximately 1.4 seconds, helping minimize data latency between processors and accelerators while improving overall AI processing efficiency. The SSD is optimized for liquid-cooled server environments through direct-to-chip cooling. This design enables sustained peak performance while improving power efficiency by up to 1.8 times compared to the previous generation.

To address security requirements for AI and virtualized infrastructure, the PM1763 supports post-quantum cryptography (PQC), the Security Protocol and Data Model (SPDM) 1.4, and Commercial National Security Algorithm (CNSA) 2.0. It also provides link encryption based on the TEE Device Interface Security Protocol (TDISP) to reinforce data protection across storage interfaces.

Samsung has now begun mass production of the PM1763 SSD.

PM1763 product page 

Samsung Electronics  

The post Enterprise SSD accelerates AI server data transfer appeared first on EDN.

Using a vertically stacked-die design, AOS’s DFN6×5 AmpStack package integrates two MOSFETs configured as a high-side/low-side half-bridge. It increases power density and maximizes available PCB space compared to a solution using two discrete DFN5×6 MOSFETs. The package enables high-density power conversion applications ranging from megawatt AI factories to power tools.

The AOPL66801 80-V MOSFET showcases the new half-bridge package with an optimized switch-node clip connecting the high-side and low-side MOSFETs. This architecture minimizes parasitic inductance within the package. Compared to a standard discrete solution, it also reduces PCB parasitic inductance, minimizing phase-node voltage ringing and decreasing stress on the MOSFETs. Key specifications for the AOPL66801 include:

An integrated Kelvin sense pin maintains gate-voltage stability during high di/dt switching. The dedicated connection provides a more effective high-side gate-drive path, helping reduce switching losses. The device also supports a maximum junction temperature of 175 °C for increased thermal capability.

The AOPL66801 is available now in production quantities with a 16-week lead time. Pricing is $6.16 per unit in 1000-piece quantities.

AOPL66801 product page 

Alpha & Omega Semiconductor 

The post Stacked-die half-bridge boosts MOSFET power density appeared first on EDN.

The Vishay 34 PHE absolute position sensor provides 10-turn linear or rotary displacement sensing with a 3600° range. Using non-contact Hall-effect technology, it delivers up to ±1% linearity (full stroke), 1° resolution, and a service life of more than 10 million cycles.

According to Vishay, the 34 PHE is priced 40% lower than previous-generation devices. It is designed for servo loop motion control systems requiring high accuracy and long-term stability in harsh environments. Typical applications include industrial motor and actuator displacement tracking, solar panel alignment systems, and flow control valve positioning.

The sensor features IP65 sealing and withstands vibration up to 20 g and shock up to 50 g. Integrated reverse-voltage and overvoltage protection (−14 VDC and +28 VDC) reduces the need for external protection circuitry. It supports single or dual analog ratiometric outputs or a digital PWM output. In dual-output mode, the two channels track position in opposite directions to enable basic fault detection. The 34 PHE reports its position immediately after power-up, even following a power loss, without requiring recalibration, homing, or initialization.

Samples and production quantities of the sensor are available now, with lead times of 14 weeks.

34 PHE product page 

Vishay Intertechnology 

The post Hall-effect sensor measures 10-turn position appeared first on EDN.

VeriSilicon’s CPP2000 Camera Post-Processing IP improves image quality for reliable vision performance in robotics, drones, and other mobile vision applications. It is designed for straightforward SoC integration and processes YUV images from image signal processors using a range of image enhancement techniques.

The IP supports image and video processing at up to 8K resolution, applying motion-compensated temporal filtering, advanced spatial noise reduction, chroma adjustment, dynamic contrast enhancement, and edge enhancement to improve noise suppression, sharpness, contrast, and overall detail fidelity.

The CPP2000 is implemented as a modular, streaming hardware pipeline in which each stage operates as a dedicated accelerator, enabling continuous real-time processing from input to output. Multiple hardware configuration options are available to address varying requirements for power, performance, area, and latency across applications.

CPP2000 product page  

VeriSilicon

The post IP enables 8K image and video post-processing appeared first on EDN.

Taiyo Yuden has introduced the HVX(-K) and HTX(-K) series of AEC-Q200-qualified conductive polymer hybrid aluminum electrolytic capacitors. The 46-device lineup is intended for noise suppression and power smoothing in power supply circuits for automotive control and safety functions such as power steering and ADAS.

The hybrid capacitors provide improved capacitance characteristics over the earlier HVX and HTX series. For instance, the 80-V RAHTX181M1RGP5005K offers a capacitance of 180 µF and a rated ripple current of 3900 mA RMS at 135°C. The devices are available in seven case sizes, with diameters of 6.3 mm to 12.5 mm and heights of 7.7 mm to 16.5 mm.

By combining a conductive polymer with an electrolyte solution, the hybrid capacitors achieve the low ESR of conductive polymers while retaining the self-healing properties of aluminum electrolytic capacitors, enhancing both performance and reliability.

The HVX (-K) and HTX (-K) series are now in production. Detailed information can be found here.

Taiyo Yuden

The post Hybrid capacitors target automotive power appeared first on EDN.

A self-heated Darlington transistor pair makes a simple, sensitive, and sturdy airflow sensor. But first an annoying non-linearity needs unbending.

If you take a self-heated transistor in a TO-92 package and force it to hold a constant temperature differential above ambient, the power input required to keep it stuck to setpoint will be determined by its thermal impedance ZT relative to the air, as given by:

ZT = ZJ + 1/(SC + KT √AF )

where:

ZJ = junction-to-case thermal impedance = 44°C/W
SC = still-air case-to-ambient conductivity = 6.4 mW/°C
KT = “King’s Law” thermal diffusion constant = 0.75 mW/°C√fpm
AF = air flow in ft/min

Wow the engineering world with your unique design: Design Ideas Submission Guide

The AF term suggests the arrangement might be handy for air flow measurement, because of the way it makes ZT, and therefore power input for a given differential, a function of air speed.  Figure 1 shows the resulting power vs AF relation a differential (Dt) = 31oC. Do note, however, the annoying non-linearity.

Figure 1 This graph shows the power dissipated vs air speed of a TO-92 held at a constant 31oC above ambient Pw = 31/ZT.

Figure 2 shows a practical thermostat circuit to achieve and maintain this delta-T while outputting a signal predictably related to Pw.  It utilizes a Darlington sensor transistor pair (Q1 and Q2) to compensate for ambient temperature and convert the resulting nonlinear Pw curve into a linearized airflow readout.  Its current mode output is compatible with the long cable runs often seen in airflow measurement applications.

Figure 2 This linearized Darlington anemometer circuit supports a 4-20mA current mode output.  Adjust R10 to calibrate 4mA (zero fpm), R11 to calibrate 20mA (250fpm).

Here’s how it works.

Q1 serves as the self-heated sensor modeled in the Figure 1 math, with Q2 providing ambient temperature compensation.  Opamp A2 runs a feedback loop that forces the Vbe differential between Q1 and Q2 (and thus the temperature differential between Q1 and ambient) to hold a constant 31oC.  It does this (with the help of Darlington current gain) by forcing Q1’s current draw (I) through R3 to drive Q1’s power dissipation (Pw) to follow the fig.1 curve of heat-vs-air flow.  The resulting voltage developed (IR3) is the basis of the air speed measurement.

Okay so far.  But how does compensation for Figure 1’s nonlinearity happen?   Well, happily the function of Q1’s Pw vs collector current I isn’t linear either.  In fact Pw = 5vI – I2R3.  That quadratic I2 term is the key.  It creates the lovely linearizing curve shown in Figure 3.

Figure 3 This graph details Q1 power dissipation vs  collector current.  Pw = 5vI – I2R3.

The 2nd-order curvature of Figure 3 compensates for the bend in Figure 1. Although the match isn’t perfect, when converted to the 4-20mA by opamp A1, the realized output is a calibrated readout of air speed that differs from ideal by less than +/- 5% from 0 to 250fpm, as shown in Figure 4.

Figure 4 This graph’s data relates anemometer output vs airspeed: FPM = 15.6(Iout – 4mA) +/-10FPM.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Self-heated Darlington transistor pair comprises new air flow sensor
• Linearized portable anemometer with thermostated Darlington pair
• Nonlinearities of Darlington airflow sensor and VFC compensate each other
• Improve thermal airflow sensor PSRR with just two resistors
• A groovy apparatus for calibrating miniature high sensitivity anemometers

The post Solid state airflow sensor with linear 4-20mA output appeared first on EDN.

The costs of designing and producing an analog ASIC chip can be grouped into three main parts: human capital, software tools, and prototype fabrication. While all three are equally critical to success, it’s important to note that design tools and wafer foundries are ubiquitous. All semiconductor companies have equal access to them, and it’s rare that a problem with the performance of an analog ASIC comes from the tools used or the wafer foundry that produced it.

Human capital: The ultimate differentiator

If you’re considering an analog ASIC, specification development, circuit design, and physical layout are the most critical steps. These are the true differentiators between the “doers” and “pretenders” (for more on this, read my article “For a Successful Analog ASIC, First Weed Out the Pretenders”).

They require the highest level of analog design skills. I’m referring to teams of craftsmen that have done hundreds of complex precision analog chips that meet requirements others said were impossible. These individuals typically have 30 to 40+ years of experience and can command salaries exceeding $350K per year. They are scarce, they are expensive, and they are worth every penny.

If you remember one thing from the paper mentioned above, let it be this: human capital is the ultimate differentiator.

The feasibility study: De-risking the design

It all starts with a feasibility study conducted by the engineers who will be designing the chip. Figure 1 below shows the steps involved.

Figure 1 The feasibility study must be conducted by the engineers designing the chip. Source: Javelin ASIC Devices

The feasibility study is a risk aversion step intended to identify and quantify risks and establish a plan to mitigate them for a successful result. Additionally, it allows the design team to quantify the time required to do the design and assess a fixed cost to complete it.

Done properly, it can take up to two months to complete the study; more if significant invention is involved, less if the chip is an amalgamation of off-the-shelf existing silicon. These costs range from $20K to $70K and are always credited to the full development if a contract is executed. Since some simulation is required, costly software tools are involved early on.

Figure 2 Human capital and software tools unite in the design phase. Source: Javelin ASIC Devices

Design phase: From specification to architecture

Several things occur during the design phase. The preliminary specification becomes a working document and grows from a 4–6-page product definition paper to an in-depth datasheet that may well exceed 50 pages, becoming more detailed with minimum and maximum limits, definitions of registers, power requirements, and more.

The thoroughness of the datasheet is a measure of the craftmanship of the design team. The datasheet drives the wafer fabrication process selection that matches the requirements for voltage, current, noise, precision, cost, and more to the most optimal foundry and a specific process.

The architecture of the ASIC is defined in functional blocks and teams with decades of experience with those blocks (charge pumps, 24-bit and higher A/D converters, precision low-drift Vrefs, and chopper-stabilized amplifiers) are created and assigned. Whenever possible, programmability using registers is added to tighten Gaussian distributions and maximize yields.

Collaboration, reviews, and designer governance

Weekly calls with the customer’s engineers are scheduled to report on status progress and offer design alternatives that may improve performance, reduce chip size (cost), avoid environmental impacts (electrical noise and temperature variations), add functionality, and more. At the completion of each major block, a design review should be scheduled with the customer’s engineering team that dives deep into a transistor-level explanation of how each aspect of the block works. It includes schematics, simulation result targets compared against specification requirements, and an overview of any external components required.

Software design tools are acquired for the duration of the project. Quarterly calls with customer corporate management are established to review schedules and cash flows. Digital teams are assembled to manage logic, memory, and register requirements.

Test strategy: Third-party vs. custom systems

In parallel with the design of the ASIC itself is the design of the test system. Sometimes evaluating a precision analog ASIC can be as challenging as the chip itself. There are two schools of thought. One is to generate a test specification to be supplied to a third-party test house that fits the capabilities of their array of commercially available test systems.

These companies will review the specifications and recommend which brand of tester is best suited. They will charge a one-time fee for the development of any unique hardware and software program needed to interface your ASIC to their tester. Getting everything up and running can easily cost between $100K and $200K.

An alternative that Javelin uses is to develop a custom test system, specifically tailored for the ASIC. We build two identical systems—one for the wafer probe and one for the final test of the packaged chip. They can be collocated in any test house and interface with the required handlers, or they can be stand-alone.

We prefer this approach because it assures perfect correlation between the wafer probe and final testing. And surprisingly, it’s less expensive. This approach offers complete flexibility in moving testing from one location to another without incurring duplicated tooling costs.

Custom ASIC economics vs. commodity products

When a commodity analog semiconductor company develops a standard product intended to be sold to thousands of disparate customers, they absorb all development costs and amortize it into their unit pricing, hoping their marketing department has identified sufficient sales potential to recover the costs and still show a profit in the long term.

However, when a custom ASIC is involved, the story changes slightly. There is only one customer, and it’s responsible for paying for the complete development. In exchange, it gets exclusivity to the chip.

Exclusivity is important because the justification for paying development costs often includes integrating proprietary IP or creating new inventions to achieve performance advantages over competitors using off-the-shelf components. Other advantages include a significantly smaller size, lower power consumption, protection from product obsolescence, and much more.

Software tools: Powerful but expensive

Although the development costs associated with creating the new IC also include wafer fabrication and package assembly, I want to stay focused on human capital and software tools for a moment. There’s more to it than meets the eye. For those not familiar with chip development costs, the numbers can be intimidating.

While the semiconductor industry often focuses on the multi-billion-dollar capital expenditures of leading-edge digital nodes, the economics of analog IC development follow a distinctly different trajectory. Development does not involve huge capital equipment investments. The investment comes in the form of human capital and tool rental.

Over the past few decades, the tools for supporting analog chip design have improved dramatically, driven in part by the growth in analog applications in automobiles, consumer products, and sensor calibration and signal conditioning, in which precision and accuracy, along with quality and reliability, are of paramount importance. A few of the most popular tools used by analog designers include Cadence Virtuoso and Spectre, Synopsys Primetime, and Mentor Graphics Calibre.

Regardless of whom you select to do your analog ASIC, they will likely use these same tools, as they are available to everyone. However, they are expensive and these costs need to be accounted for. Prices aren’t published and NDAs prevent users from disclosing them, but estimates for a single, fully featured seat for analog/mixed-signal design (layout and simulation) range from $150k-$300k per year. A seat is typically one “open window” for one user, so you can see how the dollars add up quickly.

Prototype fabrication and mask costs

Most silicon fabricators offer multi-product wafers (MPW) for some or all of their processes. These are highly valuable tools for seeing silicon samples at a low cost. They afford the ability to locate and remove any errors prior to production.

On popular processes, they are run monthly, but on others they are run less so, maybe two, three, or six times a year. If you miss the window with an available tape-out, it could be a long wait. MPWs are not required, but when available, they are an important step in evaluating early silicon and debugging test systems well ahead of production.

Whether engaging an MPW or not, the final significant tooling expense is the production mask set. Prices vary from wafer fab to wafer fab and are dependent on the number of masks required to make the ASIC. Figure on spending $75K to $150K.

Figure 3 Test and assembly operations are a critical part of ASIC fabrication costs. Source: Javelin ASIC Devices

Experience matters: Mitigating risk in ASIC development

If an off-the-shelf new chip design runs into a problem, the semiconductor company has the option to simply delay introduction while their engineers sort things out. That is not an option for your ASIC. You are counting on it to be available on a specific date to support the launch of your new or next-generation product.

Don’t be fooled by companies claiming they have been in business for 20 or 30 years. That means very little. What’s important is the experience of the folks doing the work. How long has each engineer been designing analog ASICs?

Everyone makes mistakes, but mistakes are part of learning. You need teams that have made the mistakes decades ago and learned from them. Don’t let your project become a learning experience for novices. You deserve to see the resumes of the people responsible for your ASIC. Ask to see them and insist on speaking with the engineers themselves.

Which brings up another point: you deserve to have direct access to any engineer working on your ASIC. Don’t accept some project manager or marketing manager acting as a gate keeper to be the focal point for all communications between you and your supplier. They add no technical value and insert delays in communications, which more often than not are time critical.

Bob Frostholm is co-founder and CMO of Javelin ASIC Devices.

Related Content

• Analog ASICs Made Simple
• 7 Steps to a Successful Analog ASIC
• Demystifying Analog and Mixed-Signal ASICs
• 7 myths of analog and mixed-signal ASIC design
• A 12-point overview of the advantages of custom analog ASICs

The post Understanding all costs involved in analog ASIC development appeared first on EDN.

Part 1 of this min-series established why CXL Type 3 memory expanders matter for capacity-bound workloads and where expander memory sits in the latency–capacity pyramid relative to local DRAM. It also explained what must align across the stack before memory becomes usable—CPU and BIOS enablement, kernel CXL support, device firmware, RAS paths, and the NUMA topology that Linux exposes through cxl_pci. Next, it delved into why many CXL problems surface, such as placement or bandwidth imbalance rather than obvious enumeration failures.

This part builds on that foundation with the tools and timeline you need day-to-day to navigate system bring-up. You will learn which user-space utilities reveal what the OS actually sees on the CXL fabric, how to differentiate between “device present” to “memory consumable,” and how to walk the boot sequence from slot power and DRAM training through DVSEC discovery, CEDT read, CDAT delivery, ACPI handoff, and finally driver bind-framing each stage as a validation checkpoint with recognizable failure signatures.

Let’s get to work.

Kernel drivers establish whether a CXL Type 3 device is present, configured, and represented as memory, but validation engineers spend much of their time during bring-up reconciling what firmware advertised, what the driver registered, and how user-visible policy (NUMA placement, DAX/region modes, namespace layout) matches the intended deployment. That reconciliation is difficult from dmesg and kernel logs alone. Practical programs rely on a small set of user-space utilities that expose sysfs and kernel abstractions in forms suitable for automation and field triage.

Essential user-space tooling

cxl/libcxl (often shipped with ndctl sources as “CXL tools”)

The cxl command-line interface and libcxl library walk the CXL sysfs hierarchy—ports, endpoints, memdevs, and decoders—and print structured output, commonly JSON. This is the closest thing to a standard “show me what the OS thinks on the CXL fabric” tool; serial numbers, capacity hints, which PCI function hosts a memdev, and whether decode topology looks sane before debugging performance or NUMA. It’s usually the first stop after dmesg when firmware and driver disagree about what should be visible.

ndctl

ndctl provides user-space administration for the LIBNVDIMM/regions/namespaces model that Linux also uses for some persistent-memory-class bring-up paths. Depending on kernel and platform integration, CXL-attached memory may surface as a separate NUMA node or through PMEM-style abstractions. ndctl lists regions, creates or destroys namespaces, and clarifies whether capacity is in a state software can consume, not merely whether a PCI device exists.

daxctl

daxctl manages direct-access (DAX) devices and related system-RAM or devdax configuration knobs exposed by the kernel. Some deployments expose memory through DAX-oriented paths, especially when treating capacity like PMEM/DAX rather than only anonymous DRAM. daxctl helps verify mode, online/offline behavior, and whether the system matches workload expectations. Misconfiguration here often looks like “memory is there but unusable, wrong interface, or wrong policy.”

numactl and numastat

numactl controls NUMA placement policy; numastat reports per-node memory statistics. Expander memory frequently lands as a separate NUMA node or as far memory relative to a socket. These tools prove placement hypotheses during bring-up, bind threads and allocations, measure local versus remote behavior, and catch cases where OS defaults silently place hot pages on CXL. Many “CXL is slow” bugs are NUMA policy bugs, not link bugs.

acpica-tools

This suite provides a useful utility, acpidump, which extracts ACPI tables from the kernel and dumps the raw values of the specified ACPI table. While a user should not need this during regular bring-up, it can be very useful in sticky situations when the DDR memory enumerates but does not show up either as a NUMA node or as a PMEM device. In such cases, it might be useful to dump certain acpi tables and parse raw values via a debug script.

lspci and setpci (pciutils)

Since CXL Type 3 memory expanders attach over a PCIe/CXL link, pciutils belongs in every bring-up kit alongside CXL-specific tools. lspci lists PCI functions on the bus, reports vendor and device IDs, class codes, negotiated link speed and width, and—when invoked with verbose flags—the extended capability chains that expose CXL and DVSEC registers. It’s often the fastest way to confirm that the endpoint is visible at the transport layer, that link training reached the expected generation and lane count, and that the kernel bound the intended driver (for example cxl_pci).

setpci reads and writes configuration-space dwords for targeted experiments during debug—checking capability offsets, toggling test bits where platform policy allows, or verifying that firmware left key control fields in the expected state. Used together, lspci answers “what does the bus see?” (peek) and setpci supports “can we inspect or adjust a specific config field?” (poke) before diverting attention to higher-level CXL utilities or firmware logs.

Topology and observability helpers

lstopo/hwloc produce human-readable CPU–memory topology maps—useful to confirm how the OS labels CXL memory relative to sockets. lspci/setpci (pciutils) confirm the PCI/CXL function at the bus level when debugging binding (cxl_pci versus overrides) and link issues. A verbose lspci dump reveals device capabilities that Part 3 decodes in detail.

Another, currently open-source, tool for viewing the PCIe hierarchy is pcicrawler, which shows the PCIe topology similar to lspci but in a nicer format.

From power-on to usable memory

The end-to-end path for a CXL Type 3 memory expander runs from first application of host and slot power to the point the operating system can issue CXL.mem accesses to host-managed device memory (HDM). Exact timing and responsibility splits vary by CPU, root complex, memory expander ASIC, and BIOS, but the dependencies recur. In other words, power and clocks before reset release; DDR readiness before credible capacity reporting; configuration-space discovery before decode programming; and table exchange before stable OS topology.

Boot sequence is shown for a system with CXL memory expander. Source: Author

1. Power, clocks, and ASIC bring-up

The sequence begins when host platform and slot power are applied. The expander ASIC must reach an internally consistent state: regulators settle, oscillators stabilize, PLLs lock, and on-chip reset completes so an embedded control processor can execute first-stage firmware. The host must provide a stable PCIe reference clock and manage PERST# deassertion per PCIe/CXL electrical requirements, so the endpoint is not expected to train before clocks and power are valid. During this phase, the device is not yet advertising complete HDM metadata.

2. On-device DRAM: controller release, training, and SPD

The ASIC releases reset to the DDR controller and run DRAM initialization and training for attached DIMMs. Firmware discovers configuration and capacity through serial presence detect (SPD) reads. In parallel, the ASIC initializes high-speed SerDes and the PCIe/CXL controller. There is a critical interval where HDM must not be treated as authoritative.

Firmware clears or gates HDM metadata until DRAM discovery completes—conceptually mem_info_valid = 0. Only after capacity and layout are known does firmware program HDM-related fields in PCIe extended configuration space via CXL-designated vendor-specific extended capability (DVSEC) structures and assert mem_info_valid = 1.

3. PCIe link training, DVSEC, and HDM registration

As link training toward the host begins, firmware populates HDM capability structures through DVSEC containers—HDM instance count, per-region sizing, and validity flags. Setting “memory info valid” is the device’s contract that subsequent host reads from HDM descriptors consistent with trained DRAM.

4. PCIe/CXL link up and configuration-space discovery

When the physical link reaches DL_Up at negotiated width and speed, the host enumerates the endpoint as a PCI function, parsing capability lists to discover CXL entries, DVSEC registers, and HDM decoders.

5. Decode programming and mem_enable

Platform firmware must program host-side address decoding, so HDM contributes to the system physical address map. A common milestone is establishing the system physical address window and asserting memory enable (mem_enable). When mem_enable is recognized, device firmware may finalize the coherent device attribute table (CDAT) for OS/firmware NUMA heuristics.

6. CDAT delivery via DOE and mailbox exchange

CDAT is typically transported using data object exchange (DOE) over CXL.io. The CXL mailbox command interface supports diagnostics and device management. Treat DOE/CDAT success and mailbox responsiveness as separate health checks.

7. Firmware table construction and OS handoff

Host firmware synthesizes ACPI tables, including CXL Early Discovery Table (CEDT), System Resource Affinity Table (SRAT), and Heterogeneous Memory Attribute Table (HMAT), exposing HDM ranges as distinct memory affinity domains—often NUMA nodes.

8. OS driver binding

On Linux, cxl_pci binds to the PCI/CXL function, exposes memdev objects, and enables memory to be onlined. Once complete, the host can issue CXL.mem loads, stores, and DMA through the programmed decode window.

Read the boot flow as a chain of implied tests—power/clock/PERST, DDR training, valid HDM, stable link, decode/mem_enable ordering, CDAT/DOE liveness, ACPI coherence, driver bind, and memory online. Failures produce characteristic signatures at each stage.

Part 3 applies this framework to hands-on test and debug: lspci field interpretation, NUMA verification with numactl, memory-mode configuration with daxctl, and workload tools for bandwidth and stress validation.

Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).

Editor’s Note

Part 1 of this mini-series on CXL Type 3 memory technology explains why AI and data-intensive workloads are driving interest in memory expanders and how CXL Type 3 devices differ from local DIMMs even when they appear as ordinary RAM. Part 3 covers integration modes and when boot parameters apply.

The views and content of the article are author’s own and not affiliated to any of his current or previous employers.

Related Content

• Stripped Down CXL Scales Memory Wall
• CXL Efforts Focus on Memory Expansion
• CXL Adds Port Bundling to Quench AI Thirst
• CXL: The key to memory capacity in next-gen data centers
• From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)

The post CXL Type 3: Tooling and boot path from power-on to usable memory appeared first on EDN.

This noise generator has an adjustable bandwidth and a consistent amplitude no matter what bandwidth is selected.

When working on a recent Design Idea for an adjustable filter, I wanted to use an electrical noise source to generate an FFT spectrum graph on my oscilloscope. To set up the test, I reached for my signal generator, which I knew had a noise generator option. I hooked the signal generator to the filter input and the scope to the filter output and turned on the scope’s FFT display function. I then set the filter to 10 kHz and set the signal generator noise standard deviation to its maximum of 3.0 volts.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The output of the filter was a minuscule signal. Here’s what I’d ignored – the signal generator outputs a white noise signal with a 3.0 v standard deviation, but its bandwidth is 25 MHz. When I reduced the bandwidth with the filter, the amplitude dropped. With a perfect brick wall filter, this would reduce the standard deviation by the square root of (10 kHz/25 MHz). So, the 3.0 v standard deviation becomes about 60 mV after filtering. This small signal can be easily corrupted by noise existing in a test setup.

This standard deviation reduction comes from the way white noise signals add. Basically, if a signal is uncorrelated white noise and you add it to a second uncorrelated white noise source of the same standard deviation, the combined signal’s standard deviation will increase by the square root of 2. Alternately, when you filter out half of the spectrum of a noise signal with a brick wall filter, the standard deviation will decrease by the square root of 2.

It occurred to me that a noise signal generator should compensate for this reduction if you want to use a narrower portion of its bandwidth. For example, if the project under test is a device for audio, maybe you only need a noise source spanning only up to 50 kHz. Or maybe you’re testing a signal chain’s response for a low-frequency vibration sensor; in this case maybe a 1 kHz span is enough. But in either example you will want the signal’s standard deviation to be large enough to get a clean FFT.

So, how would I create a testing device to give me a noise generator that has an adjustable bandwidth and a consistent amplitude no matter what bandwidth is selected? The first thought was the typical white noise generator created with reversed biased Zener diode or base-emitter transistor junction followed by an adjustable low-pass filter and then an amplifier with some form of automatic gain control (AGC). But then it occurred to me that a micro I’d used recently has a random number generator and a fairly fast DAC for output…hmm.

Let’s take a look at what I came up with (Figure 1). First the name – the concept for this project idea is a Bandwidth Adjustable Noise Generator, which gives rise to the device’s nondescript acronymic moniker of “BANG”. The BANG is a micro-based generator that allows you to set the bandwidth you desire using a touchscreen. It then generates a noise signal with the standard deviation digitally compensated for that bandwidth.

Figure 1 The BANG is a micro-based generator that allows you to set, on a touchscreen, the bandwidth you desire. It then generates a noise signal with the standard deviation digitally compensated for that bandwidth. The device also has a knob to manually adjust the generated signal.

The device also has a good old-fashioned knob to manually adjust the generated signal somewhat, so you can tweak it. Its output has a maximum output of around 3.1 v and is available as an AC signal (biased at 0 v) or a DC signal (biased at around 1.65 v). The bandwidth adjustment of the noise signal goes from 225 kHz to 500 Hz, and this adjustment is accomplished using an LCD and touchscreen.

The hardware

The heart of the BANG is a Microchip Technology ATSAMD51 processor. The adjustable digital filter project mentioned earlier also used a ATSAMD51, which has a true random number generator (TRNG). It’s best to let the Microchip data sheet describe this feature:

The True Random Number Generator (TRNG) generates unpredictable random numbers that are not generated by an algorithm. It passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 140-3.”

These 32-bit numbers sound perfect for constructing a noise signal source! Using the same processor as before also meant I could reuse a large portion of the LCD and touch screen code, IIR digital filter code, battery monitor code, and various other initialization and housekeeping pieces. Besides the micro, another major piece of the design is the touchscreen, which is an ILI9341 2.8″ 240×320 pixel TFT LCD with a SPI interface.

The other major electronic piece is the analog back end (ABE). One part of the ABE is a reconstruction filter (sometimes referred to as an anti-imaging filter) attached to a DAC on the micro. It essentially filters out-of-band high frequency content carried along with the digitally generated noise signal as it is sent out of the DAC. The filter is a 4-pole Sallen-Key low pass filter with a cutoff frequency of 250 kHz (I used TI’s Webbench filter design tool to calculate the component values). The ABE section also has a potentiometer-adjustable gain stage from around 0.25x to around 2.5x of the ADC signal. The last part of the ABE is a simple output buffer driving the AC and DC outputs. Figure 2 shows the complete schematic.

Figure 2 The heart of the BANG is a Microchip Technology ATSAMD51 processor.

There are a few odds-and-ends on the schematic that I haven’t mentioned yet. First, the micro format I used is an Adafruit Feather M4 Express Arduino board, powered via USB or, alternately, a 3.7 v lithium polymer battery. The Arduino board also contains a charger for the battery. Being able to power it from the battery may be more convenient in some situations, and better yet, it can provide ground isolation if desired in your setup.

The USB pin shown is actually a regulated 3.3 v source that is used to power the rest of the circuitry. You’ll also notice a voltage divider, connected to an ADC on the micro, used to measure the USB voltage for display purposes. The ON/OFF switch actually connects to the EN (enable) pin. The BANG is powered off when the EN pin is pulled to ground. A Vcc/2 reference circuit can also be seen and is used to provide a center voltage for the single-supply operated op-amps.

More to come

Next time, I’ll describe the BANG’s firmware, integration, and operating results. Until then, I welcome your thoughts in the comments on what I’ve discussed so far!

Note that the schematic, code, 3D print files, Arduino software, links related to various parts of the project, and additional notes and pictures on the project’s design and construction can be downloaded for free at the MakerWorld website.

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

Related Content

• A digital filter system (DFS), Part 1
• A digital filter system (DFS), Part 2

The post Making noise with a BANG, part 1: Concept and hardware appeared first on EDN.

It seems as if every technical advance these days is either directly related to AI software and data centers, or at least tries to establish such a connection, even if that connection is somewhat of a tenuous “stretch.” Despite this, there are a lot of innovative and interesting projects underway that are very analog-centric, with little or no AI association. These advances show what “small” analog can do, where small refers to both physical size and focused functionality.

Consider a neural implant dubbed the Microscale Optoelectronic Tetherless Electrode, or MOTE, developed at Cornell University (Figure 1). Measuring about 300 microns long and 70 microns wide (yes, that’s microns), researchers maintain it’s the smallest neural implant capable of wirelessly transmitting brain activity data.

Figure 1 This brain-implantable MOTE measures just 300 microns long and 70 microns wide and requires no tether or wireless RF link for power or data. Source: Cornell University

It’s connected via red and infrared laser beams that pass harmlessly through brain tissue. The MOTE transmits data back using tiny pulses of infrared light, which encode the brain’s electrical signals. An aluminum gallium arsenide (AlGaAs) semiconductor diode both captures light energy to power the circuit and emits light to communicate the data.

The device also includes a low-noise amplifier and optical encoder, all built using the standard CMOS process technology. The optical link uses pulse position modulation (PPM) for its data encoding as that format is very power efficient, especially in this situation (Figure 2).

Figure 2 System overview shows a MOTE implanted in an awake mouse brain to chronically record neural activity in vivo—incoming light powers the MOTE, and the MOTE, in turn, emits the PPM pulses communicating the recorded data (a). Optical microscopy image compares a MOTE with a strand of human hair (b). MOTE is powered and is communicating optically; it’s continuously powered at a shorter wavelength and communicates at a longer wavelength, making the powering system easier to implement and avoiding power–communication crosstalk (c). Source: Cornell University

The dual-use diode, dubbed a photovoltaic light-emitting diode (PVLED), provides space-saving benefits, functioning as both an LED and a data-link transmitter. An external 623-nm LED source provides power to the PVLED, while MOTE emits 825-nm PPM pulses that encode electrophysiological signals.

The diode is used as a photovoltaic for 93.4% of the time and as an LED for 0.06% of the time, with the remainder of the time spent on transitions. By concentrating the transmitted power into short, bright pulses and encoding information in the timing of those pulses, PPM is much more resistant to noise than amplitude modulation and is very power efficient.

Atomic layer deposition (ALD) of SiO2, Si3N4 and Al2O3 encapsulates MOTE against corrosive biological media without substantially increasing its volume (total encapsulation thickness is under 1.5 µm). High-pressure platinum (Pt) sputtering then provides not only favorable electrode impedance but also an effective and conformal light shield to prevent incident light from generating unwanted photocurrents in the electronics. Critically, each fabrication step is done in parallel, simultaneously fabricating close to 100 MOTEs per chip—and scalable to thousands of MOTEs per square centimeter of silicon (Figure 3).

Figure 3 Bulk fabrication of MOTEs (left) integrating two disparate technologies—CMOS (silicon based) and PVLED (AlGaAs based)—and a cross-sectional view (right) of a fully fabricated MOTE illustrating how the ALD dielectrics and sputter Pt together constitute a shield against biological media and unwanted photocurrents. Source: Cornell University

The underlying CMOS circuits provide low-noise amplification, stable biasing and PPM encoding, and drive the PVLED as an LED (Figure 4). Overall power budget is miserly: nominal power consumption is just one microwatt, divided among the amplifier (50.0%), encoder (10.5%), LED driver (26.2%), and support circuits (13.3%).

Figure 4 Systemic description of a MOTE and its external counterpart for communication—MOTE’s output PPM pulses are detected by an external photodiode before being passed through a decoder (a). Schematics of the front-end amplifier based on pseudo-resistors (left) and the charge pump for optical pulse generation shown on the right (b). Power and area distributions of a MOTE in which the amplifier and filter take most of the power for low-noise amplification (left), and the frame and integration overhead for protection against unwanted light and photocarriers take most of the area, as shown on right (c). Source: Cornell University

How well did they do?

By design, incident LED irradiance is limited to less than 70 mW/mm2, well below the allowed threshold of 250 mW/ mm2, which may inflict heat damage in the brain. The team first performed Petri-dish “static” tests before moving on to live rats. The heads of the implanted live mice were “restrained” while computer-controlled motor moved a rod to stimulate a whisker of an awake, head-fixed mouse.

The implant successfully recorded spikes of electrical activity from neurons as well as broader patterns of synaptic activity—all while the mice remained healthy and active. In two of the six implanted mice, they placed MOTEs on the brain surface, from which they were able to measure the electrocorticographic (ECoG) signals; in the other four mice, they inserted MOTEs into the barrel cortex.

As expected, MOTEs captured the neural responses to whisker stimulations and transmitted the neural signal spike. MOTES were left in the test “subjects” for up to 300 days and continued to function, although there was some degradation in performance, which the Cornell researchers attribute to deterioration of the platinum electrodes.

Why even bother with such a project, rather than using conventional “stick-in” electrodes? In addition to the obvious limitation imposed by the associated wired tether or even a wireless interface attached to the rat, one of the motivations is that traditional electrodes can irritate the brain as the tissue moves around the implant and thus can trigger an immune response. Their goal was to make the device small enough to minimize that disruption while still capturing brain activity faster than imaging systems, and without the need to genetically modify the neurons for imaging.

In you want to know more about the project, its circuitry, and the test results on the rats (I didn’t feel the need to go into detail on that!), check out their detailed and highly readable paper “A subnanolitre tetherless optoelectronic microsystem for chronic neural recording in awake mice” published in Nature Electronics.

Whether it’s rat implants or something non-biologic, these projects—with their tight focus, custom die, minimized number of functional blocks, and no frills or features beyond what is absolutely needed—show what analog designs can do in micropower and microsize designs, and that innovative analog design has not reached a terminal point. As the late, great analog designer Bob Pease liked to remind us, “one good op amp can do more than a thousand logic gates.”

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

Related Content

• Hot car-seat deaths and sensor solutions
• When sensors are easy, but sensing is hard
• “Wideband” still elusive in electronic noses
• A 12-point overview of the advantages of custom analog ASICs

The post Neural implant merges photovoltaics with custom analog, PPM encoding appeared first on EDN.

The memory wall is no longer a theoretical concern. It’s the defining bottleneck in today’s AI, automotive, and data center system-on-chips (SoCs). CPUs operate at GHz frequencies with single-digit nanosecond cycle times, yet DRAM latency remains stubbornly at 60─100 ns, and memory-mapped I/O (MMIO) accesses to on-chip accelerators across complex networks-on-chip (NoC) can take even longer.

As SoC designs scale up with more accelerators, larger memory subsystems, and deeper interconnect fabrics, the cost of every cache miss and every device register access grow. No single architectural feature can solve this. It demands a multi-dimensional approach.

This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core. Our evaluation confirmed that outstanding transaction capability delivers significant benefit, up to 39%, when memory accesses are independent, but only 6% under pointer-chasing patterns where hard data dependencies prevent parallelism.

This demonstrates exactly why a single-dimensional solution is insufficient. The Andes AX46MPV addresses memory latency from multiple angles: outstanding transactions to exploit memory-level parallelism when access patterns allow, hardware prefetching to predict and fetch data before the core needs it, and software prefetch support to give programmers direct control over latency hiding.

Together, these capabilities form a comprehensive latency tolerance strategy—ensuring robust CPU performance whether the bottleneck is cacheable DRAM access or uncacheable MMIO traffic across the SoC.

Below are the six key premises that can help design engineers formulate a latency tolerance strategy to ensure robust CPU performance amid memory bottlenecks.

1. The memory wall problem

Modern workloads, such as AI inference, databases, and graph analytics, are memory bound. As mentioned above, CPUs now operate at GHz frequencies with single-digit nanosecond cycle times, while DRAM latency remains stubbornly at 60─100 ns. This gap, commonly known as the memory wall, means a single cache miss can stall the processor for hundreds of cycles, leaving expensive compute resources idle.

The bandwidth–latency paradox

Technologies like high-bandwidth memory (HBM) and DDR5 are engineered for high bandwidth but realizing that bandwidth requires the CPU or GPU to sustain hundreds of outstanding memory requests simultaneously. Without a deep request pipeline, the memory bus sits idle between transactions, wasting the very bandwidth these technologies were designed to deliver. In other words, bandwidth is only as useful as the processor’s ability to keep the memory channel busy.

Beyond AI: The automotive case

The memory wall is not confined to data center workloads. In automotive SoCs, DRAMs are often soldered directly onto the PCB to withstand vehicle vibration. This soldering, combined with PCB routing constraints, can result in longer signal paths and increased DRAM access latency. Therefore, the CPU’s ability to sustain multiple cacheable in-flight requests is also critical in automotive systems.

2. The MMIO dimension: Long latency beyond DRAM

The memory wall problem extends beyond cacheable DRAM to uncacheable MMIO as well. Modern SoCs integrate many peripherals and accelerators, such as AI engines, NPUs, and DMA controllers. The CPU configures and communicates with these devices through MMIO register accesses.

Each MMIO access is uncacheable and must travel on the on-chip bus. If the CPU can only issue one MMIO transaction at a time, programming a sequence of accelerator registers becomes painfully slow. This is a real bottleneck in systems where the CPU orchestrates multiple accelerators and needs to rapidly set up DMA transfers, kick off inference jobs, or poll status registers.

Real-world example: Meta’s MTIA accelerator

A concrete illustration is Meta’s MTIA—Meta Training and Inference Accelerator—which uses Andes RISC-V cores inside each processing element (PE). Within the chip, these cores access system registers and remote PE resources through an on-chip AXI interconnect, using uncached MMIO accesses whose latency varies depending on the physical distance across the grid.

Figure 1 Here is a look at the MTIA platform, the first-generation silicon targeting Meta’s recommendation systems. Source: Meta

The growing NoC latency challenge

As AI chips grow larger and more complex, accelerator blocks are spread further across the die, connected by NoC. An MMIO access to a block on the far side of the NoC can take 50─200+ cycles just for routing, and even longer under congestion. This makes the CPU’s outstanding MMIO transaction capability a meaningful factor in overall system throughput.

3. FlatBuffers: A memory subsystem stress test

We chose Google’s FlatBuffers library not as a representative AI workload, but as a stress test for the CPU memory subsystem. FlatBuffers is an open-source, cross-platform serialization library designed for zero-copy data access, meaning it reads serialized data in place without a separate deserialization step. While this library design is efficient in many respects, it creates memory access patterns that are particularly challenging for CPU caches and memory subsystems.

What makes FlatBuffers demanding

FlatBuffers uses indirect, offset-based data navigation: accessing any field requires reading an offset, computing a field address, and then following that address to the actual data. This results in multiple dependent memory accesses per field lookup.

The read path, in particular, involves classic pointer chasing, which means each access depends on the result of the previous one. The chasing depth is configurable and can be set to a high value (for example, 2,000), meaning the traversal spans far more data than a single cache line can hold.

As a result, cache misses are frequent and unpredictable. Accesses tend to be small and scattered, touching a few bytes at one location before jumping to an entirely different cache line. Combined with extensive small function calls for field accessors, FlatBuffers stresses the instruction cache, branch predictor, and memory subsystem simultaneously.

Figure 2 Read pointers involve chasing in FlatBuffers. Source: Andes Technology

Establishing a performance floor

By evaluating under these deliberately demanding conditions, we establish a performance floor for the CPU. Real-world workloads, which typically exhibit more regularity and spatial locality, can be expected to benefit even more from the core’s architectural features for latency tolerance.

4. What we learned: Outstanding transactions under two access patterns

Our evaluation on the Andes AX46MPV RISC-V core revealed that the architectural benefit of outstanding transactions varies dramatically depending on the memory access pattern, not just the cache miss rate.

FlatBuffer Create: Independent accesses, high benefit

In the FlatBuffer Create kernel, the CPU allocates buffers, writes fields, and builds the serialized data structure. These memory accesses are largely independent of each other; that is, the address of one write does not depend on the result of a previous read. Despite a low DRAM access frequency of just 0.23%—shared cache misses as a proportion of total instructions—the core achieved a 20% to 39% performance benefit from its outstanding transaction capability.

The range depends on how we model the worst case without outstanding transactions. The upper bound of 39% assumes every DRAM access fully stalls the pipeline for the entire memory latency with no instruction overlap whatsoever, which is a deliberately pessimistic assumption. The lower bound of 20% assumes that some instructions can still be executed during a DRAM stall, effectively halving the DRAM access cycles.

The actual benefit likely falls somewhere within this range, but even at the conservative end, a 20% gain from just a 0.23% miss rate demonstrates that when cache misses are independent, the hardware can issue multiple requests simultaneously and continue useful work while waiting. This is the ideal scenario for memory-level parallelism: rare but independent misses that can be fully overlapped.

FlatBuffer Read: Pointer chasing, limited benefit

The FlatBuffer Read kernel tells a very different story. This workload is dominated by pointer chasing. The CPU reads an offset, dereferences it to compute the next address, reads that location, follows the next offset, and so on. Each memory access depends on the result of the previous one, creating a strict chain of data dependencies.

Despite a much higher DRAM access frequency of 1.99%, the core achieved only a 6% performance benefit from outstanding transactions. The small gain likely comes from brief windows where the access pattern allows limited parallelism. Perhaps when reading multiple independent fields within a single FlatBuffer object after resolving its base pointer. But the dominant pointer-chasing pattern fundamentally limits how much latency the hardware is able to hide.

The key insight: Not all cache misses are equal

This contrast carries an important implication for system architects and workload designers. The value of outstanding transaction capability depends not on how many cache misses occur, but on whether those misses are sufficiently independent to be overlapped. Workloads with parallel, unrelated memory accesses can see dramatic benefits; workloads with serialized, data-dependent accesses will see far less improvement, regardless of how many outstanding transactions the hardware supports.

5. Beyond outstanding transactions: Prefetching as a complementary strategy

Outstanding transactions are most effective when cache misses are independent and can be issued in parallel. However, not all workloads exhibit this pattern. When the access pattern has some regularity but not enough parallelism to exploit, outstanding transactions alone are insufficient. This is where prefetching can provide partial relief.

The Andes AX46MPV includes both hardware prefetch and software prefetch capabilities. Hardware prefetching detects regular access patterns, such as sequential or strided accesses, and speculatively fetches data into the cache before the core requests it. Software prefetch instructions give programmers explicit control, allowing them to insert prefetch hints at strategic points in the code where the hardware prefetcher cannot anticipate the access pattern on its own.

Together with outstanding transactions, these prefetch mechanisms form a multi-layered defense against memory latency, each addressing a different dimension of the problem.

6. A multi-dimensional approach to the memory wall

When cache misses occur in a modern SoC, whether to cacheable DRAM or to uncacheable MMIO device registers across a complex interconnect, the resulting latency is a multi-dimensional problem. No single feature eliminates it. The Andes AX46MPV architecture addresses this challenge from multiple angles: outstanding transactions exploit memory-level parallelism when access patterns allow it, hardware prefetching predicts and fetches data before the core needs it, and software prefetch gives developers an additional tool to partially overlap latency.

Our FlatBuffers evaluation makes this concrete: outstanding transactions deliver a 20─39% gain when cache misses are independent, but under pointer-chasing patterns, the benefit drops to 6%. For SoC designers, this underscores a practical truth: understanding your workload’s access patterns is just as important as the hardware features themselves.

For those building the next generation of AI, automotive, and data center platforms, this kind of comprehensive, multi-dimensional latency tolerance is not a luxury. It’s a necessity.

Mia Chang is a solution architect at Andes Technology with more than 10 years of experience spanning semiconductor circuit modeling and CPU synthesis. She works directly with AI compute and automotive customers, performing in-depth kernel-level analysis to uncover performance bottlenecks in real-world system designs.

Author Acknowledgement

This article would not have been possible without the support of several colleagues. The CCBU team carried out the FPGA measurements that underpin our evaluation. Our NA team provided thoughtful reviews and suggestions that helped sharpen this article. Our knowledgeable architect and R&D team behind the AX46MPV were always willing to discuss the questions and challenges we encountered during benchmark analysis with us. Thank you all.

Related Content

• The Memory Wall Is Real, Here Is the Door
• AMD Snaps MEXT to Break the Memory Wall
• AI-Driven Memory Shortage Upends IT Budgets
• Massive AI Storage Demand Creates a New Memory Wall
• Why CXL Type 3 memory matters, what your platform must provide

The post Memory wall: Why cache miss tolerance defines CPU performance now appeared first on EDN.

Unintended fluids dripping from above? Accumulating from below? The T300 alerts you to them all. And mysteriously threaded contacts suggest other uses, too.

Back in March, I covered the activation and ongoing usage impressions of three interrelated TP-Link smart home devices: the Tapo H100 smart hub:

display-inclusive Tapo T315 hygrometer:

and Tapo T300 smart water leak sensor:

Toward the end of that March piece, and reiterating a quote I’d initially included in a mid-May follow-up post, I wrote:

I’ve also got a redundant Tapo H100 smart hub and T300 smart water leak sensor, both sitting on the shelf, queued up for teardown, along with a display-less sibling of the T315 hygrometer, the Tapo T310 Smart Temperature and Humidity Sensor:

The Tapo T310 was tore down and analyzed within that same mid-May writeup, with the teardown of the Tapo H100 predating it in late April. And now, in early July, we’re completing the dissection triumvirate with the spare Tapo T300, which I as-always aspire to return to fully functional form post-disassembly for ongoing leak-monitoring use somewhere in the residence.

Revisiting past history

You already saw a set of box and other real-life shots for the sibling Tapo T300 in the initial mid-March entry in this series (assuming you read it, that is); that particular unit now resides at the base of my downstairs water heater. The “dumb” leak sensor previously at that location now sits below the also-downstairs whole-home water filter; another is at the back of my icemaker-augmented combo refrigerator/freezer in the kitchen.

As usual, I’ll start out with some outer box shots, also as usual accompanied by a 0.75″/19.1 mm diameter U.S. penny for size comparison purposes.

This last image of the bottom of the package reveals (among other things) the hardware version (v1.6, succeeding the original v1, as well as with its own v1.8 successor) and serial number:

The hardware version matches that of the Tapo T300 currently in use, although serial numbers differ (of course). Here’s a revisit of the associated box-bottom shot you saw in March:

Open sesame

Let’s see what’s inside:

starting with a sliver of quick-start literature (PDF…here are the accompanying full user guide and datasheet) and some protective foam:

Here’s our patient, still swathed in a translucent protective sleeve:

And now unclothed, once again echoing sibling-device images you saw back in March:

As before (referencing the packaging photos), with the exception of this bottom shot:

versus this differing-serial-number vantage point of the in-use sibling device:

in both cases (and in contrast to the bottom-perspective packaging precursors) now including the always-informative common FCC ID (2AXJ4T300).

The Tapo T300 comes already battery-equipped, as you’ve probably already ascertained from the translucent strip of plastic that begs for removal prior to first-time use, but a power-source swap will sooner-or-later be necessary (“up to three years” before replacement is the claim). The removal of two screws should gain us access to the battery compartment:

Toldja so (there’s two AAAs/LR03s inside):

Next up, four screws, one in each corner, this time with hex heads:

We have liftoff

And with them removed, the two sections of the case separate straightaway, with no further implements of destruction or elbow grease required:

The inside of the bottom portion is largely unmemorable. Nice gasket, though, for likely-already-obvious liquid-intrusion-prevention purposes (IP67). Speaking of liquids, note the four metal pass-throughs, one on each corner, originating with the bottom-side contacts you saw earlier:

The other, larger portion is much more interesting (IMHO, at least):

Leak warning-sound transducer aka “buzzer” (claimed 90 dB!) on the side:

Let’s get that PCB outta there. Removing two more screws should do the trick:

That’s what I’m talkin’ about:

Toward the right are a pair of additional feed-through contacts from the top, intended to catch drips coming from above (vs. already-pooled fluids from below in the prior four-contact case). In the middle is a visible-light pass-through originating at the multi-color multi-function status LED, which I’m betting we’ll see shortly. And at left is the mechanical button portion of the topside control switch. The buzzer on the side, fed by the red-and-black two-color wiring harness, you’ve already met, right?

Simply simple

Now for the PCB itself, beginning with the bottom side, you’ve already glimpsed in past shots.

The proximity contacts for the previously pointed out bottom-side contacts are in the corners, labeled P11-P14. Two of the four battery terminals are here; you might have already noticed that the other two are attached to the case itself. And although at first glance, I’d thought the sizeable cylinder on the left edge was an electrolytic capacitor, the “L323” PCB marking next to it suggests otherwise (analog experts: is this what’s known as a “radial inductor”?). Note, too, that the D6 diode site below and to its right is unpopulated, seemingly, unless my eyes are playing tricks on me.

Now for the more interesting (IMHO) topside (which, bafflingly, is screenprinted “BOTTOM”):

Dominating the landscape at left is the PCB mounted portion of the aforementioned control switch. Below and to its right is a sixteen-lead square IC labeled as follows (I “think”…the “S” and “5” symbols aren’t distinctly different):

300A
S906
S15

Readers’ suggestions as to its identity and function(s) are welcomed. My bet is that, as with the Tapo T310 Smart Temperature and Humidity Sensor, it’s another obscured-marking CC1 series-variant of Texas Instruments’ MSP430 embedded controller family, for (among other things) “Sub-1 GHz dual-band” wireless connectivity. More on that connectivity bit in a moment.

Above and to its right, and at the PCB center, is the status LED. To its right is another, larger IC, this one more easily identifiable; it’s the same Cmsemicon BAT32G135GE application processor that I’d found in the earlier Tapo T310 Smart Temperature and Humidity Sensor teardown. To its right are two more landing pads, labeled T9 and T10 and this time corresponding to the earlier noted topside-located drip-sensing contacts.

And above the entire circuitry assemblage is ANT5, the embedded antenna for the company’s proprietary ultra-low power wireless protocol. Since this application’s data rate (as with hygrometry) is low, unlike with a smart camera (for example), additional Wi-Fi connectivity isn’t necessary in this case.

Speaking of sides, I’ll wrap up for today with four more PCB perspectives related to its backside, since that’s where the bulk of the “vertical” parts are located.

Along with one other tidbit that I came across during my research. You might have already noticed that two of the four contacts on the bottom of the device aren’t solid; instead, they seemed to have unfilled (not to mention M2 screw-threaded) centers. You’d be spot-on with that observation, although nothing I’ve found in the product documentation explains why.

Well, this guy (or gal; dunno) used them to transform the Tapo T300 into a door open/close sensor. If it wasn’t already obvious, the Tapo T300 doesn’t directly leverage a moisture sensor, as a hygrometer does (for example). Instead, it detects normally absent current flow between any of the three paired sets of two contacts, interpreting that conductivity as evidence of fluid presence. The switch used in this creative design derivation, in its “closed” position, generates the same current flow. And this same concept can also be employed for other purposes. Nifty!

Over to you for your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• The Tapo Hub: TP-Link joins the low-bandwidth, long-range RF club
• Smart hygrometers: Still largely useful even without integrated visual monitors
• TP-Link’s Tapo H100: Smart sensing unencumbered
• Tapo or Kasa: Which TP-Link ecosystem best suits ya?

The post TP-Link’s Tapo T300 sensor detects water and other liquid-leak dangers appeared first on EDN.

Artificial intelligence (AI) may dominate today’s conversations about smart cities and autonomous mobility, but beneath the pavement lies a technology that has quietly kept traffic flowing for decades. Inductive loop detectors (ILDs)—simple wire coils paired with reliable electronics—continue to deliver dependable vehicle detection, enabling adaptive traffic lights, toll systems, and roadway monitoring.

In a landscape buzzing with AI-driven vision and radar, ILDs stand out as the proven, resilient infrastructure that provides clarity and consistency, reminding us that not all progress depends on novelty—sometimes it rests on steady signal amid the noise.

Applications of inductive loops

In principle, an inductive loop (or induction loop) is an electromagnetic detection system that uses a moving magnet or an alternating current to induce an electric signal in a nearby wire. They are widely applied in transmitting and receiving communication signals and are also integral to hearing-assist devices, where audio signals are magnetically transmitted directly to compatible hearing aids, improving clarity in public venues such as theaters, lecture halls, and places of worship.

Inductive loops also play a crucial role in vehicle detection—embedded beneath road surfaces, they sense the presence of cars and trigger traffic lights or vehicle presence indicators. In addition, they serve in metal detectors and other object-sensing applications, but their impact on accessibility and traffic management makes them especially vital.

The rest of this post deals with inductive loop vehicle detectors.

Inductive loop vehicle detectors

Among current vehicle detection technologies, the inductive loop system remains the industry standard due to its optimal balance of performance, reliability, and cost-effectiveness.

At their core, inductive loop detectors operate by sensing changes in inductance when a metallic object disturbs an electromagnetic field.

This field is generated by a cable loop embedded directly into the roadway; as a vehicle passes over, it alters the coil’s inductance, triggering a detection signal. These systems provide the essential control logic for automating infrastructure, such as operating gates and traffic barriers, managing signal timing at intersections, or dispensing tickets in parking facilities.

Figure 1 A vehicle induction loop presence detector triggers gate mechanisms and logs traffic data for access management. Source: Roger Trade Centre

The system comprises two primary components: the sensing element and the electronic module. The sensing element consists of a wire coil buried within the pavement and a lead-in cable with the loop’s specific geometry defining the boundaries of the detection zone. The electronic module connects to this loop to monitor electromagnetic changes that indicate a vehicle’s presence.

Once a vehicle is detected, the module processes the resulting data according to its specific programming. This information can be acted upon immediately to trigger traffic signals or automated gates, stored locally for subsequent traffic pattern analysis, or integrated as a critical data point into a larger, networked management system.

Furthermore, the physical installation of the sensing element requires a saw cut, which involves milling a narrow groove—typically 1 to 2 inches deep—directly into the asphalt or concrete. Once the wire coil is laid within this channel, the slot is filled with a specialized loop sealant to protect the hardware from moisture and traffic-induced stress.

While this method enables precise placement and easy retrofitting on existing roads, the integrity of the saw cut is vital. Any degradation in the sealant or shifting in the pavement can lead to wire breakage, resulting in system failure or “ghost” detections.

Figure 2 A basic sketch illustrates an inductive loop vehicle detector system. Source: Author

More inductive loop vehicle detector essentials

Over the years, engineers have experimented with various inductive loop geometry configurations to optimize vehicle detection. While early designs were constrained by the limitations of rudimentary electronics, modern technological advancements have rendered many of those barriers obsolete.

This evolution necessitates a reevaluation of traditional standards to accommodate the sophisticated configurations now in widespread use. Today, selecting the ideal geometry requires a comprehensive analysis of site-specific parameters, including adjacent lane interference, the required detection zone area, the specific vehicle types being monitored, and the physical distance between the loop and the electronics module.

In practice, these loops are deployed to capture two primary types of data: presence and passage. Presence detection—monitoring a vehicle within a specific zone or lane—typically requires loops with larger surface areas. Conversely, detecting the passage of a vehicle over a specific point is best achieved using a single, smaller loop.

Once geometry is established, the next critical factor is the number of turns. While the geometry defines the physical detection zone, the number of turns dictates the loop’s inductance value. It is essential to account for the lead-in cable’s inductance, as it contributes to the total input inductance of the system. Engineers must balance these values carefully, as decreasing the loop inductance below recommended thresholds can significantly compromise system stability.

Furthermore, it’s important to note that a vehicle passing over a small portion of a large loop generates a significantly smaller change in inductance than it would when passing over a smaller loop. For maximum system reliability, the detector must be able to register the greatest possible change in inductance when a vehicle enters the detection zone.

Since the detector monitors an inductance shift that is directly proportional to the percentage of the loop area displaced by a vehicle, smaller loop areas inherently provide higher sensitivity. Consequently, when wide-area coverage is required—such as along large gates—multiple smaller loops are often connected to a single detector channel rather than using one oversized loop.

When connecting multiple loops to a single channel, it is standard practice to use identical loops. These loops should share the same dimensions, shape, and number of turns. Maintaining uniform inductance across all connected loops ensures a consistent level of detection sensitivity across the entire monitored area, preventing “dead zones” where a vehicle might go undetected.

For the sake of brevity, this discussion omits foundational concepts such as fundamental inductive theory, loop phasing, and detection height considerations. Furthermore, specialized topics—including the cancellation of undesired magnetic fields through twisted-pair wiring—are left as a subject for further study for those voracious readers seeking a more exhaustive understanding of the underlying physics.

Now, let’s look at some practical pointers for the circuit design notebook.

Practical design pointers

You can build an inductive loop vehicle detector prototype by embedding a wire coil in the roadway and monitoring its inductance. The coil functions as part of a high-frequency oscillator; when a metallic vehicle passes over the loop, it induces eddy currents that decrease the loop’s inductance. This causes a measurable shift in the oscillator’s frequency, which a microcontroller can then process to reliably detect the vehicle.

Success in loop design hinges on balancing sensitivity with environmental stability. Start by documenting the specific loop geometry and the gauge of the wire used, as these factors directly dictate the magnetic field’s reach.

It’s also essential to log the chosen operating frequency; ensuring your system stays within the recommended frequency range for your specific hardware helps avoid interference from nearby power lines or electronic equipment. Finally, always record the layout of the lead-in cables, ensuring they are tightly twisted to minimize noise, and note the pavement conditions to account for any metal reinforcement that might dampen the detector’s response.

As a quick design starting point, you can utilize a Colpitts oscillator built from standard components. The oscillation frequency—typically ranging from 30 kHz to 150 kHz—is determined by the capacitor values and the inductance of the coil windings. The oscillator output is then fed to a microcontroller, which measures the frequency to determine whether a vehicle has been detected.

For better stability, it is recommended to isolate the wire loop from the sensor electronics using a 1:1 ratio isolation transformer, though this is not strictly mandatory. It’s easy to find inspiring design ideas similar to this all over the web.

It’s worth trying a directional loop setup to track traffic flow more accurately. By tracking the activation sequence of two independent sensors, a directional logic loop detector identifies which way a vehicle is headed. The system registers movement based on which loop is tripped first, allowing it to differentiate between opposing flows of traffic.

This capability is particularly useful for shared entrance/exit points in parking facilities and alerting systems to wrong-way drivers on highway ramps. Moreover, these detectors often automate barrier gates, initiating an “open” command for traffic arriving from one side and a “close” command for those departing from the other side.

Figure 3 A directional logic loop detector tracks vehicle direction by monitoring two separate loops. Source: Author

Closing the loop

Inductive loop vehicle detectors prove that even in a world obsessed with complex sensors, the fundamental laws of electromagnetism remain the gold standard for reliability. While computer vision and LIDAR grab the headlines, these buried wire loops continue to quietly power our infrastructure with unmatched precision and weather resistance.

For engineers and makers out there, this technology is a playground of untapped potential—whether you’re optimizing urban traffic flow or building an automated entry system for your own workshop. Don’t just settle for off-the-shelf solutions; grab a spool of wire, dive into the physics, and start prototyping your own detection systems today.

Let’s see what kind of smarter, more responsive world you can build from the pavement up.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• The Inductive Nature of Voltage-Control Loops
• 6 Considerations for Integrating Sensors in Vehicles
• How Can OEMs Use Connected Vehicle Sensor Data?
• Inside DSP on Automotive Signal Processing: Street Smarts
• The Autonomous Car Industry in 2024: Sensors, Software and Safety

The post Inductive loop vehicle detectors: Still steady in the noise of AI appeared first on EDN.

Stress exceeding the levels prescribed in absolute maximum ratings specifications may lead to chip malfunctions. Key word: may.

Within the last decade, I was the head of a captive tier 1 automotive embedded electronics department for a global vehicle supplier. Our job was two-fold: on the one hand to build electronic units for our own vehicles whenever an external tier 1 could not meet our price and time-lines, and on the other hand to support external tier 1 companies as well as our own vehicle engineers to deliver robust and first-time right solutions.

Do you have a memorable experience solving an engineering problem at work or in your spare time? Tell us your Tale

Our vehicle engineering team was in the process of doing final testing of a prestigious export consignment of buses destined for a UN peace-keeping mission. A initial batch of two hundred buses were undergoing on-road tests when we discovered that around twenty of them were exhibiting electronic cabin climate control subsystem malfunctions.

This particular subsystem had been developed by a globally reputed tier 1 supplier. Their engineering team was promptly summoned to troubleshoot and fix the problem. Unfortunately, the initial troubleshooting progressed for two weeks without any desired outcome. Finally, we as in-house electronics experts were asked to intervene and rescue the seemingly intractable situation.

Their team leader described the associated circuit block that was a suspected culprit as follows:

A three terminal low-dropout regulator (LDO) with a fourth enable pin is used to power the climate control logic. Whenever we wish to reduce drain on the battery by turning off the climate control system, the LDO is disabled by deactivating the fourth enable pin. Unfortunately, this LDO is misbehaving in all the twenty malfunctioning buses. Their “enable pin” always remains disabled internally, shutting off the output!

“What is your diagnosis?,” we asked. “Your vehicle environment is full of transient spikes reaching up to 70 volts,” he countered. “We have tied the enable pin through a resistor to the 24 V battery bus. No wonder the LDO is refusing to work, since its rating is exceeded.”

“You need to clean-up your vehicle transients to ensure the health of our system,” he advised, showing us a report issued by a certified laboratory. “Our control unit has passed the automotive transient burst tests as per international automotive transient norms. If our design was erroneous, our unit should have failed during the transient test.”

In summary, according to him, our vehicle was inflicting worst transients than those prescribed in automotive test transient specifications. I went through the supplier’s schematic, along with the LDO datasheet. The latter document clearly indicated that the absolute maximum rating for the enable pin was 45V DC. Like all datasheets, however, it also cautioned engineers that any stress exceeding the levels prescribed in the absolute maximum rating may lead to chip malfunction.

I pointed out the datasheet note, explaining to him that a transient suppressor in his circuit was needed to limit external transients to below 45V. My team immediately set to work, installing external transient suppressor units in each bus so that the consignment could be released overnight. But the supplier engineers were not convinced, repeatedly pointing out the claimed “passed” conclusion from the test laboratory.

Automotive global transient test norms specify an acceptance criterion as follows:

• The unit should first pass an in-advance functional test
• The unit can now undergo a “transient burst” test that bombards the power bus with spikes as high as 150V
• The unit should then again pass the same functional test as prior

Note, however, that an absolute maximum rating of 45V is applicable to the worst-case rated LDOs in the field. In contrast, the majority of the chips withstand much higher voltages during operation. This explained why a majority of the buses did not suffer from the malfunction. When a supplier submits samples to the laboratory, test agencies do not test “violation of absolute maximum rating”. They only apply the acceptance criterion in terms of successful functional tests both pre- and post-transient test.

But the supplier engineering team was not prepared to accept above argument. “If you don’t agree with us, let’s meet again tomorrow. This time, please also bring with you the LDO supplier’s application engineer. Both of you should declare in one voice that your circuit does not violate absolute maximum ratings. We have no time to argue now; we need to expedite corrective measures overnight.”

The next morning, we met again with the the climate control supplier engineer, this time also including the semiconductor application engineer in the discussion. The semiconductor engineer confirmed our understanding, much to the dismay of the supplier engineer. Our buses were happily dispatched to their destination after adding necessary protection units and are running without problem to this very day.

Let me summarize the lessons and insights from this case study, which I also frequently share with my automotive clients and trainees:

• An absolute maximum rating of, say, 45 volts does not mean that all chips would get destroyed at 46 volts and beyond. That said, other chips’ operating life may, however, still be reduced.
• Understand the limitations of engineering tests based on visual observations of correct functionality for electronic units. The unit may be violating datasheet limits, ratings, operating conditions etc., but may still seem to be working flawlessly.
• An accurate way to ensure robust and flawless behavior across a mass-produced population of units is to record voltage and other electrical signatures in a laboratory for key circuit points. Doubly ensure that the same is not violating any data sheet limits.
• It is good engineering practice to jointly audit key circuit blocks with the assistance of authorized chip application engineers. Most semiconductor companies are happy to do so, since it preserves their field reputations. They will also gladly prescribe proactive measures to strengthen circuit designs in order to avoid subsequently facing “field surprises” such as this incident.

Vishwas Vaidya is a graduate of the Indian Institute of Technology in Delhi, India. Currently, he is self-employed as an engineering consultant and industry faculty member in the field of embedded systems for global automotive clients and high-repute academic institutions. Vishwas’ articles and research reports have appeared in many worldwide engineering publications.

Related Content

• Stress analysis
• Semiconductor Reliability and Quality Assurance–Failure Mode, Mechanism and Analysis (FMMEA)
• Design for reliability: You have the tools
• Electronic Components Derating – Made Easy

The post Absolute illiteracy about absolute maximum ratings appeared first on EDN.

Applications in the AI era are memory starved. They need more capacity and, in many cases, more effective memory bandwidth than traditional server designs. Generative AI and large language models (LLMs) store trillions of parameters that must be accessed frequently. And real-time inference for translation, chatbots, and similar services demands low-latency memory paths.

Larger memory footprints enable bigger batch sizes, improving training and inference efficiency. However, while the fastest memory sits on die—in CPU caches—capacity there is inherently limited. For decades, systems have relied on double data rate (DDR) interfaces for high-capacity, relatively low-latency off-chip memory.

Adding more DDR to a CPU, however, runs into hard limits: each interface consumes scarce I/O pins (288 pins on modern DDR4/DDR5 modules), demands strict signal integrity at ever-higher data rates, and carries significant cost. An alternative that has gained real traction is Compute Express Link (CXL) Type 3 memory expanders—devices that attach over a CXL link and present additional system memory to the host.

CXL is a cache-coherent interconnect that lets a CPU access device-resident resources with semantics closer to memory than traditional PCI Express (PCIe) peripherals. A Type 3 memory expander exposes DRAM (and, in some designs, other media) as byte-addressable memory that firmware and the operating system can map and allocate like conventional RAM—after discovery, decode programming, and policy setup.

The critical implication for bring-up and validation is that this memory is logically host-visible yet physically and administratively distinct from local dual inline memory modules (DIMMs). That distinction affects discovery, non-uniform memory access (NUMA) topology, performance, and error-handling paths through firmware and the OS.

Figure 1 The memory-latency pyramid describes relative ordering and validation implications. Source: arXiv

The memory latency–capacity pyramid

System memory is best understood as a latency–capacity pyramid. Small, fast, most expensive structures—CPU caches—sit at the top. Larger, slower, progressively cheaper tiers sit below; local DRAM, then expansion memory, and then I/O-backed storage. Absolute nanoseconds vary by CPU generation, CXL version, link width, topology (direct attach versus retimer or switch), firmware tuning, and contention; the pyramid describes relative ordering and validation implications, not a single fixed latency table.

Local DDR, typically attached near the CPU socket, offers the lowest DRAM access times the OS sees for general-purpose allocation. CXL Type 3 expander memory is DRAM-class and byte-addressable from software’s perspective, but it’s reached across a CXL fabric hop (often with additional buffering and coherency handling).

It therefore sits below local DDR—higher average and tail latency, sometimes behaving like “far memory” in NUMA terms. In other words, imaging CPU 0 accessing DDR memory is attached to CPU 1 in the system, as shown in Figure 2.

Figure 2 Here is a typical two-socket system with a CXL memory expander device attached to CPU 0 via a Gen5, x16 CXL bus. Source: Author

For bring-up, that placement matters as correctness tests may pass while performance and quality-of-service (QoS) tests fail. Workloads with pointer chasing, fine-grained random access, or strict tail-latency budgets are the first to expose suboptimal placement, interleaving, or contention.

Storage and networked memory (NVMe, RDMA, and similar) form the broad base of the pyramid with much higher latency and usually block or page semantics. CXL memory is not in the same tier as SSDs, but it’s meaningfully different from local DIMMs for latency-sensitive software. On a typical two-socket system, the access latency of DDR behind a CXL device can be comparable to accessing DDR attached to the adjacent CPU—a useful mental model when setting performance expectations.

Platform prerequisites: A cross-layer contract

Whether CXL Type 3 memory becomes reliably visible, addressable, and serviceable depends on aligned support across the stack: CPU CXL capability and enablement; system BIOS/firmware support for discovery, decode, and ACPI tables; kernel CXL enumeration and memory management; and expander device firmware for DRAM training, HDM reporting, and mailbox/DOE services. All layers must agree.

Consider CXL Integrity and Data Encryption (IDE); it requires CPU support, BIOS enablement, and device firmware support to be usable end to end. Similarly, the kernel needs a CXL-aware path to recognize the device class, bind memory resources, and transition capacity to an online state the allocator can use.

Reliability, availability, and serviceability (RAS) matter equally. Corrected and uncorrected error notifications must propagate from hardware through firmware to OS subsystems that can log, isolate, or offline affected regions. Because behaviors evolve quickly across kernel releases, validation plans should treat OS version, configuration (huge pages, numactl policies, memory mode), and boot/firmware settings as explicit test variables. Failures are often misattributed to the expander when the root cause is a policy or enablement gap.

Host-managed expander memory generally relies on the in-kernel CXL/memory management stack rather than a monolithic device-specific driver, though platform integrations may include monitoring agents, telemetry exporters, or hardware management interfaces that affect how engineers observe link state, temperature, power, and error counters during bring-up.

Linux and the NUMA story

On Linux, a Type 3 memory expander normally appears as a PCI/CXL function. In upstream kernels with CXL support enabled, the in-tree cxl_pci module is the default bind target. A stock Type 3 host-managed device (HDM) endpoint typically comes up under cxl_pci rather than a vendor-specific host driver for basic enumeration.

The cxl_pci module is PCI-facing glue: it attaches to the device, brings up CXL.io access (including the configuration mailbox), and registers the endpoint with the CXL core so the rest of the stack can expose memory devices to the OS.

In a NUMA machine, the operating system groups CPUs and memory into nodes and treats local memory as cheaper than remote memory. DRAM next to a socket is usually the lowest-latency memory for CPUs in that socket, so the scheduler and allocator try to keep threads and pages on nearby nodes (subject to policy).

CXL Type 3 expander memory is still host-coherent and byte-addressable, but it’s physically and topologically distinct from local DIMMs. Platforms and operating systems therefore commonly expose expander memory ranges as a distinct NUMA node, or as memory with different affinity and distance metadata in ACPI proximity hints. The same application binary can run correctly while performance changes sharply depending on where pages are allocated and whether threads migrate across sockets.

For CXL bring-up and validation, the NUMA story is central. Issues often appear as unexpected remote access or imbalanced bandwidth rather than hard functional failures. Engineers must verify not only that memory is online, but that placement and distance metadata match the intended system topology.

What comes next

Part 2 of this series introduces the user-space tooling ecosystem—cxl/libcxl, ndctl, daxctl, numactl, and topology helpers—and traces the full boot sequence from slot power and DRAM training through DVSEC discovery, decode programming, CDAT delivery, ACPI table handoff, and OS driver binding. Part 3 turns to practical test and debug: interpreting lspci output, validating HDM ranges, exercising CXL-attached memory with numactl, and selecting bandwidth and stress tools for validation gates.

Together, these three parts provide a vendor-neutral, OS-focused playbook for engineers, bringing CXL Type 3 memory expanders from first power-on to production-ready validation.

Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).

Editor’s Note

This is Part 1 of the mini-series on CXL Type 3 memory technology. Part 2 of this series introduces the user-space tooling ecosystem. And Part 3 turns to practical test and debug work.

The views and content of the article are the author’s own and not affiliated to any of his current or previous employers.

Related Content

• Stripped Down CXL Scales Memory Wall
• CXL Efforts Focus on Memory Expansion
• CXL Adds Port Bundling to Quench AI Thirst
• CXL: The key to memory capacity in next-gen data centers
• From GPUs to Memory Pools: Why AI Needs Compute Express Link (CXL)

The post Why CXL Type 3 memory matters, what your platform must provide appeared first on EDN.

Converting frequency signals to loop current signals creates an economical result for process industry applications.

Process industry applications commonly employ multiple motors. Their speeds are monitored by tachometers using magnetic pickups from gear wheels mounted on the motors’ shafts. The tachometers produce pulses whose frequencies are proportional to their speeds. Local displays of speeds is generally done by counter/timer-based LEDs or LCDs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Special modules incorporating expensive counter/timers find use for recording these speeds in control room-based programmable logic controllers (PLCs) and more complex distributed control systems (DCSs). Shielded cables are necessary to carry these pulse signals to the control room, as the signals may induce noise in adjoining cables carrying conventional analog signals. Such an approach is expensive. A more economical alternative solution would be to convert each frequency signal to a 4-20 mA  loop current signal and then transport it to the control room using less expensive cables like those carrying analog signals. Figure 1’s circuit does exactly this.

Figure 1 In one switch SW1 position, this circuit converts 0-50 kHz frequency signals to 4-20 mA loop current alternatives. In the other switch position, the circuit converts 0-5V into 4-20 mA loop current.

The frequency to voltage conversion circuit discussed here is based on an industry-standard LM2907 IC. This chip is extensively used in automotive applications and hence is easily available and inexpensive. It needs only three components to set the basic relationship between frequency and voltage. It uses a charge pump circuit to convert frequency to voltage.

• V output = Vcc*F*R*C (In Figure 1’s circuit, R=R5, C=C4)
• U2 is wired to give a 12 V output, which is fed to the circuit. F is pulse frequency.
• With Vcc as 12V and substituting the component values shown in the circuit, the voltage output works out to 0.264V/KHz.

Exact values for R5 and C4 are not necessary; approximate values are sufficient. The signal is amplified by U1B so that a voltage relationship of 1V/KHz is obtained by tuning potentiometer RV1. C5 filters ripples; increasing its value filters ripples more effectively but also increases the response time. The portion of the circuit surrounding U3 converts 0 to 5KHz into 0 to 5 volts.

The remaining portion of the circuit converts 0/5V into 4/20 mA loop current. R2 determines the “zero” current of 4 mA. If an exact-value resistor is not available, R2 may be replaced with a potentiometer. R13 determines the current span value. Again, if an exact-value resistor is not available, it can be replaced with a potentiometer.

The current going through R2 plus the current going through R13 must be equal to current through R4, as these currents are at the + input of operational amplifier U1A, whose -ve input is grounded. A detailed description of a loop current converter with governing equations can be found in my earlier Design Idea “A 0-20 mA source current to 4-20 mA loop current converter”.

As a bonus, this circuit converts 0-5V into 4-20mA loop current by flipping switch SW1 to the alternative 0-5V input position. Multiple industrial sensors and transmitters generate 0-5V outputs for the parameters they monitor. This circuit may be used to comfortably connect such sensors and transmitters to PLCs and DCSs. Linearity and accuracy are primarily dictated by the LM2907 IC. A simulation study of this circuit indicates accuracy of better than +/- 5%.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

• 4/20mA to 0/20mA loop current converter for grounded loads
• Full circle current loops: 4mA-20mA to 0mA-20mA
• Another silly simple precision 0/20mA to 4/20mA converter
• Silly simple precision 0/20mA to 4/20mA converter
• A 0-20mA source current  to 4-20mA loop current converter

The post Tachometer frequency to 4-20mA loop current converter appeared first on EDN.

Solid-state drives (SSDs) are among the evolutionary success stories of modern computing. They replaced spinning disks, eliminated mechanical bottlenecks, and enabled the high-speed data access that today’s applications depend on. Plus, they fit into ever-smaller form factors, which we all love.

But as workloads evolve—especially with the rise of edge AI—SSDs are bumping against a critical limitation: heat.

What was once a distant consideration has become a frontline performance constraint. Today’s SSDs are faster, denser, and more heavily utilized than before. And the devices they live in—ultrabooks, tablets, gaming handhelds, and emerging AI-enabled wearables—are thinner, more compact, and often fanless. This clash of trends is creating a perfect thermal storm.

The forecast is ominous—both for consumers and system designers. SSDs will continue buckling under real-world workloads; they’ll throttle data speeds when things get hot; and users will pay the price in diminished performance.

But there must be a cooler way out.

The new reality of sustained workloads

Historically, many storage workloads—the read/write patterns of moving data—were burst-oriented. Opening files, launching applications, and saving documents created short spikes in activity, followed by idle periods that allowed components to cool. Under these conditions, passive thermal solutions such as heat spreaders, vapor chambers, and thermal pads were sufficient.

That’s no longer the case.

Modern workloads, particularly those driven by AI, are sustained and data intensive. Running local LLMs requires loading gigabytes of parameters from storage into memory. AI-powered photo and video editing tools generate continuous read/write cycles during rendering and export. Even gaming has evolved, with real-time asset streaming and procedural generation placing constant demands on storage subsystems.

They are prolonged, high-throughput operations that keep SSD controllers and NAND flash memory active for extended periods. And that changes everything.

Thermal throttling: Hidden performance killer

SSDs are designed with thermal safeguards to prevent damage. Most standard, high-speed controllers begin to throttle performance when temperatures reach approximately 70°C to 80°C. Once that threshold is crossed, the drive reduces its speed to lower heat output.

From a reliability standpoint, this is essential. From a performance standpoint, it’s detrimental. In practical terms, thermal throttling of SSDs can reduce throughput by 20% to 30% or more. A drive capable of delivering 2.0 GB/s may drop to 1.5 GB/s under sustained load. For users, this translates into longer file transfers, slower application performance, and increased latency in AI-driven tasks.

Usually, such performance degradation is unpredictable. And in edge AI applications, where consistent performance is critical, this variability can be unacceptable.

Why passive cooling is no longer enough

The root of the problem lies in the limitations of passive cooling. Passive thermal solutions are designed to spread heat away from hotspots, redistributing it across a larger surface area. This can delay temperature spikes and improve short-term performance, but it doesn’t actually remove heat from the device.

In compact, sealed systems where SSDs operate, heat accumulates over time. Without airflow to carry that heat away, temperatures inevitably rise until throttling occurs.

This challenge is exacerbated by modern device design. In many ultrathin laptops and handheld systems, SSDs are positioned near CPUs, GPUs, and other heat-generating components. The thermal environment is already saturated, leaving little headroom for additional heat dissipation.

The industry has pushed passive cooling to its limits with advanced materials and clever mechanical designs. But physics imposes a hard boundary. Without active airflow, sustained high-performance operation is not achievable.

Micro-cooling: A new approach to active thermal management

How to achieve that airflow? Traditional active cooling relies on fans. Fans move air, enabling heat transfer that effectively removes thermal energy from a system. In desktops and larger laptops, this approach works well.

But fans are not a universal solution. They take up space, generate noise, consume power, and introduce mechanical complexity. In ultra-thin devices, wearables, and sealed systems, integrating a fan is often impractical or undesirable. As a result, many edge devices are designed without active cooling, despite the increasing thermal demands placed on their components. Still, there’s a need for active cooling that fits within the constraints of modern device design.

Micro-cooling (µCooling) technology offers a new approach. Instead of miniaturizing traditional fans, µCooling uses piezoMEMS technology to generate airflow through microscopic motion inside a silicon chip. Often referred to as a “fan on a chip,” µCooling devices are fabricated using semiconductor processes, making them extremely compact, thin, and reliable.

Because they have no moving mechanical parts, µCooling devices avoid many of the drawbacks associated with conventional fans. They operate silently, consume minimal power, and can be integrated into tight spaces where traditional cooling solutions cannot fit. But most importantly, µCooling “fans” move heat out of a system and away from SSDs, something no passive cooling solution can accomplish.

What µCooling means for SSD performance

For SSDs, the introduction of µCooling is transformative. By generating localized airflow around the SSD controller and NAND components, µCooling systems can actively remove heat before it accumulates to critical levels. This helps maintain operating temperatures below throttling thresholds, even during sustained workloads.

Instead of experiencing performance degradation over time, SSDs can sustain higher throughput for longer durations. This is particularly valuable for AI workloads, where consistent data access speeds are essential. In practical terms, this means faster model loading, smoother real-time processing, and more reliable performance during extended tasks such as video rendering or large-scale data transfers.

µCooling also enables system designers to rethink thermal constraints. With active cooling available at the micro level, they can push performance boundaries without being limited by the thermal management challenges.

Enabling the future of edge AI devices

The evolution of SSDs has always been about addressing bottlenecks—first mechanical, then architectural. The next bottleneck is clearly thermal. Without addressing heat, we can’t realize the full potential of modern storage systems in edge devices. Throttling will undermine performance gains, and the user experience will suffer.

µCooling provides a path forward. By bridging the gap between passive and traditional active cooling, it enables a new class of thermal solutions tailored to the needs of modern electronics. It ensures that SSDs, a critical component of the data pipeline, don’t become a bottleneck. And that’s crucial.

As edge AI continues to proliferate, the importance of efficient thermal management will only increase. Devices are expected to do more—process more data, run more complex models, and deliver richer experiences—within smaller and more constrained form factors. Storage systems must keep pace with the demands for sustained, not just peak, performance.

Mike Housholder is VP and GM of thermal management at xMEMS.

 

 

Related Content

• SSDs Get Smarter
• SSD drive performance chart
• Smarter SSDs bring on-drive processing
• SSD performance measurement: Best practices
• Startup Touts SSD Architecture, Private Label Model

The post SSDs are hot: Why AI demands micro-cooling appeared first on EDN.

Part 1 of this mini-series on advanced packaging outlined the basic comparison between CoWoS, wafer-scale integration, and CoWoP. It established why the package substrate, silicon wafer, and platform PCB represent different settings for future AI system bottlenecks.

Part 2 continues with the advanced CoWoP concept: pitch translation, transition patches, VRM and memory placement, Universal Chiplet Interconnect Express (UCIe) routing, and trusted realization governance.

The most challenging CoWoP part is not only whether the package substrate can be reduced or removed. The harder question is whether the architecture can physically transition from silicon-interposer pitch to platform-PCB pitch.

A wafer-level interposer, silicon bridge, or advanced redistribution structure operates in a fine-pitch environment. Micro-bumps, hybrid bonding, and high-density redistribution can exist in the tens-of-microns range. A platform PCB, even an advanced HDI board, operates at a much larger manufacturing scale, closer to hundreds of microns for practical solderable attach and board-level assembly.

This creates a major geometric discontinuity:

• Interposer/wafer-level interface: roughly tens of microns
• Platform-PCB attach interface: roughly hundreds of microns

Trying to force the primary interposer to absorb this entire fan-out directly would consume expensive interposer area, increase routing complexity, reduce yield, and weaken the economic argument for CoWoP. Therefore, the more practical CoWoP architecture may require an intermediate transition structure.

• Die/HBM → wafer-level interposer → transition redistribution patch → platform PCB

This patch is not simply another conventional package substrate. It’s a localized pitch-translation and CTE-management layer. Its role is to convert the silicon/interposer interface into a PCB-compatible attach interface while preserving electrical, mechanical, and thermal continuity.

A useful name for this structure is interposer-to-PCB transition patch, or more specifically, pitch-transition redistribution patch. This transition patch becomes the governed bridge between wafer-level precision and platform-level manufacturability.

Glass as a local transition patch

One possible implementation is a thin glass-core transition patch. A 2-3-layer glass-based transition patch could provide dimensional stability, CTE compatibility with the silicon/interposer side, and a controlled vertical path through TGVs. In this use case, glass is not being treated as a full package substrate replacement; it’s being used as a local transition bridge between wafer-level precision and board-level attach.

The concept is similar in spirit to wafer-to-package redistribution: expand the pitch in controlled stages rather than forcing one layer to absorb the entire geometric transformation. The transition could look like this in silicon die/HBM:

• Micro-bumps or hybrid bonding at fine pitch
• Primary wafer-level interposer
• First-stage redistribution
• Glass-core transition patch with TGVs
• Second-stage fan-out toward PCB pitch
• Platform PCB

The value of the glass patch is that it may preserve the CTE and dimensional-stability advantages near the interposer while providing a more manufacturable path toward the PCB. This matters because the hardest interface may not be the PCB alone or the interposer alone. It may be the transition between the two.

A glass transition patch can potentially help with:

• Fine-pitch registration
• CTE continuity near the silicon/interposer side
• Controlled vertical fan-out through TGVs
• Reduced interposer area devoted only to fan-out
• More stable pad alignment across thermal cycling
• A shorter vertical PDN path toward the platform PCB

But the glass patch also introduces its own realization needs:

• TGV reliability
• Glass/copper stress
• Attach fatigue
• Inspection accuracy
• Edge cracking
• Lifecycle drift

In other words, glass can make the transition more governable.

Organic as a compliant transition patch

Another possible implementation is a high-density organic transition patch. An organic patch may not match the dimensional stability of glass, but it may provide mechanical compliance. That compliance could help absorb shear stress between a rigid silicon/interposer structure and a larger platform PCB that expands, warps, and bends differently under thermal and mechanical loading.

This creates an important trade-off. A glass transition patch may offer stronger dimensional stability, stronger CTE matching to silicon/interposer, better fine-pitch registration, and a stronger TGV-based vertical transition. An organic transition patch may offer better mechanical compliance, more familiar substrate processing, and potentially better stress absorption between rigid silicon and PCB.

This trade-off is exactly why CoWoP should be treated as a governed realization problem, not only a layout concept. The transition patch becomes a decision point. The best material may depend on system size, thermal cycling, pitch requirements, power density, board stiffness, rework needs, reliability targets, and cost.

CoWoP as an interposer-to-patch-to-PCB corridor

With the transition-patch concept included, CoWoP becomes technically more credible. The architecture is not simply interposer directly attached to PCB, as shown below.

Interposer → controlled transition patch → platform PCB

It means CoWoP is not only a substrate-removal concept. It’s a pitch-transition, CTE-governance, and system-integration concept. The package substrate may be reduced, localized, or re-architected, but the realization burden does not disappear. It moves into a new corridor where the interposer-to-transition patch-to-platform PCB corridor must govern:

• Pitch translation
• Pad registration
• TGV or via integrity
• CTE continuity
• Attach fatigue
• Return-path continuity
• PDN impedance
• Decoupling location
• Thermal spreading
• Inspection and test
• Lifecycle reliability

Why CoWoP may be attractive for VRM placement

One of the strongest opportunities is power delivery. In advanced AI packages, the VRM is often physically far from the die. The power-delivery path must travel through the PCB, package substrate, interposer, bumps, and on-die distribution. This creates loop inductance, PDN impedance challenges, transient-response limitations, dI/dt sensitivity, resonance concerns, and pressure to place decoupling capacitance closer to the load.

Moving active power components onto the interposer or package may reduce distance, but it introduces other risks:

• Thermal density
• Active-component integration complexity
• Manufacturing risks
• Repairability concerns
• Reliability uncertainty

CoWoP may offer a more practical middle path. The VRM can remain on the PCB, where active power components are more manufacturable, serviceable, thermally manageable, and familiar to the design ecosystem. At the same time, however, the vertical corridor from platform PCB to transition patch to interposer may become shorter and more direct than the conventional package-substrate path.

So, the value is not that the VRM is placed on interposer; the value is that the VRM can stay on the PCB while the power corridor to the interposer becomes shorter, more controlled, and potentially lower inductance. That may reduce part of the package-dominated loop inductance and improve the power-delivery architecture without forcing active VRM components into the interposer itself.

This creates a new chiplet power architecture opportunity: PCB-side VRM, transition-patch power delivery, lower package burden, and governed PDN evidence. But the power problem is not solved automatically. The transition patch must preserve current return paths, minimize spreading inductance, support decoupling strategy, avoid PDN anti-resonance, and remain reliable under thermal cycling.

In short, while the corridor is shorter, it still must be governed.

Why CoWoP may be attractive for DDR and LPDDR

Memory is another important area. HBM will remain critical for high-bandwidth AI accelerators, but not every memory requirement should necessarily move onto the package. DDR and LPDDR placed on package can create manufacturing, warpage, thermal, test, yield, and reliability concerns.

So, memory on the PCB remains attractive because it’s more familiar, more serviceable, and more compatible with established board-level manufacturing. The problem is distance and signal quality.

In a conventional architecture, the memory path may be:

Die → interposer → package substrate → PCB → DDR/LPDDR with CoWoP

The path may become closer to:

Die → interposer / wafer-level routing → transition patch → platform PCB → DDR/LPDDR

This does not make PCB memory identical to on-package memory. However, it may improve the compromise: memory can remain on the PCB while the routing path becomes shorter, more direct, and potentially more controllable than the conventional package-to-board path.

That is a meaningful system architecture advantage. It may also reduce pressure to place every useful memory element inside the package, which can help with manufacturability, reliability, thermal control, and module yield.

But DDR/LPDDR on the PCB still demands careful governance.

• Timing margin
• Impedance control
• Crosstalk
• Return path
• Via transitions
• Thermal drift
• Board manufacturing variation

CoWoP may improve the memory compromise, but it does not eliminate memory convergence risk.

Why CoWoP may help UCIe and chiplet routing

UCIe and other chiplet interconnect strategies need dense routing, controlled impedance, short paths, clean return current, low jitter, and manageable power/thermal interaction. However, in conventional 2.5D architectures, much of the high-density routing is constrained by interposer size, substrate escape, package boundary, and board transition.

CoWoP may create more flexibility by making the platform PCB part of the high-density system-integration fabric. This could support more flexible routing between chiplets, memory, power, and system I/O. It may also support larger integration footprints without relying on ever-larger package substrates.

But this is also where the challenge appears. The platform PCB can no longer be treated as an ordinary board. It becomes part of the advanced-package realization path. That means PCB materials, dimensional accuracy, layer stack-up, shielding, via structures, reference planes, surface finish, warpage, inspection, and assembly control all become part of the governed convergence problem.

The transition patch makes this more realistic, but it also introduces a new boundary that must be modeled, measured, inspected, and qualified.

The new CoWoP challenges

CoWoP may reduce several package-level burdens, but it does not eliminate complexity. It shifts complexity into a new interposer-to-transition patch-to-platform PCB corridor. The key challenges include:

• Low-loss platform PCB materials
• Interposer-to-transition patch attach reliability
• Transition-patch-to-PCB attach reliability
• Pitch translation from fine-pitch interposer scale to PCB attach scale
• TGV or via reliability inside the transition patch
• Warpage and CTE mismatch
• Board flatness and dimensional control
• High-density routing precision
• Shielding between dense high-speed traces
• Return-path continuity across multiple interfaces
• PDN impedance and resonance
• VRM placement and transient response
• Decoupling location and effectiveness
• DDR/LPDDR timing and signal integrity
• UCIe routing and crosstalk
• Thermal spreading from die and HBM into board-level structures
• Inspection accuracy
• Rework strategy
• Lifecycle reliability

These challenges are solvable, but they require a different mindset. CoWoP does not simply move packaging onto a PCB. It asks the PCB ecosystem to operate closer to semiconductor-grade precision, while also asking the package ecosystem to think beyond the traditional package substrate. This is why CoWoP is not only a packaging innovation. It is a governed realization challenge.

Three architectures, three bottleneck locations

The most useful way to compare these architectures is by asking where each one places the system bottleneck. CoWoS places the bottleneck in advanced package scaling: interposer size, package substrate capability, HBM integration, substrate supply, package warpage, thermal design, SI/PI, PDN, and board transition.

Wafer-scale integration places the bottleneck in system adaptation around a very large silicon object: power delivery, cooling, mechanical design, yield management, redundancy, system serviceability, and workload mapping.

CoWoP places the bottleneck in the interposer-to-transition patch-to-platform PCB realization corridor: pitch translation, CTE continuity, low-loss PCB materials, precision manufacturing, attach reliability, power delivery, memory routing, UCIe flexibility, shielding, return-path continuity, inspection, and lifecycle evidence.

None of these paths eliminates convergence complexity. Each path chooses where complexity will live.

Why CoWoP needs a trusted realization layer

CoWoS, wafer-scale integration, and CoWoP all create different evidence domains, but the same fundamental governance problem remains. Which evidence is mature enough to support a deterministic engineering decision?

For CoWoS, the evidence includes interposer routing, substrate PDN, HBM integration, warpage, thermals, package attach, SI/PI, EM/IR, and board transition. For wafer-scale integration, the evidence includes wafer yield, defect tolerance, power delivery, cooling uniformity, mechanical stability, redundancy, board interaction, and system operation.

For CoWoP, the evidence includes interposer-to-transition-patch attach, transition-patch-to-PCB attach, platform PCB materials, VRM proximity, loop inductance, decoupling strategy, LPDDR/DDR routing, UCIe flexibility, shielding, return-path continuity, warpage, inspection, and lifecycle reliability.

The common requirement is governed convergence. This is where a scalable trusted realization layer (STRL) becomes important. STRL does not need to decide that one packaging structure is always superior. Instead, it asks whether each corridor has enough normalized, admissible, causally grounded evidence to support closure.

In this sense, CoWoP is a powerful new vector for trusted realization because it converts the platform PCB from a passive board into an active realization corridor. With the transition-patch concept included, the sharper statement is: CoWoP converts the interposer-to-transition patch-to-platform PCB boundary into a governed realization corridor.

Platform PCB as an active realization corridor

The most important idea is this: CoWoP may turn the platform PCB into the next active control plane for AI system realization. This does not mean the board replaces the interposer. It means the board becomes more deeply integrated into the convergence path.

The platform PCB must support power delivery, memory routing, thermal interaction, high-speed signaling, mechanical stability, shielding, and manufacturing precision. The board is no longer downstream from the package. It becomes part of the package-system continuum.

That creates a new research and industry-development opportunity: Interposer + transition patch + platform PCB as a governed system EM corridor. This corridor can be evaluated across:

• Power delivery and transient response
• Loop inductance and dI/dt sensitivity
• Decoupling effectiveness
• UCIe/chiplet routing flexibility
• DDR/LPDDR signal integrity
• Shielding and crosstalk
• Thermal spreading
• Mechanical stability
• CTE and warpage
• Manufacturing yield
• Inspection and test
• Field reliability

This is not only convergence theory; it’s a practical architecture direction.

Evidence domains for a governed CoWoP corridor

For CoWoP to become a credible production architecture, the key evidence domains must be governed together, not separately.

A CoWoP realization corridor would need evidence from:

• Interposer layout and redistribution
• Micro-bump or hybrid-bonding interface quality
• Transition-patch material selection
• TGV/via resistance and reliability
• Pad registration and pitch expansion
• CTE transition and shear stress
• Patch-to-PCB attach integrity, platform PCB flatness, and dimensional stability
• VRM phase-current behavior
• PDN impedance and transient droop
• Decoupling effectiveness across frequency
• DDR/LPDDR timing margin
• UCIe crosstalk and return-path continuity
• Thermal gradients and cycling stress, inspection, rework, and lifecycle failure signatures

In conventional workflows, these may be treated as separate domains. In a governed realization architecture, they become one corridor. That is the role of STRL:

• Normalize evidence
• Preserve causality
• Qualify admissibility
• Support bounded engineering authority

Why this idea matters now

The current package stack is under pressure. AI packages are becoming larger, more complex, more thermally constrained, more power-hungry, and more challenging to manufacture. Moreover, package substrates face size, availability, yield, warpage, layer-count, PDN, and cost challenges.

At the same time, memory, UCIe, power delivery, thermal design, and system-level integration are becoming harder to close independently. CoWoP may not be mature enough today to replace CoWoS in mainstream high-volume AI accelerators. But the direction is important.

If low-loss PCB materials, precision board manufacturing, inspection capability, transition-patch technology, and interposer-to-board attach reliability continue to improve, CoWoP may become one of the important platform-level architectures for future AI systems. The reason is simple.

It reduces the number of realization layers between silicon and system, but only if the transition boundary is engineered correctly. Instead of managing interposer, package substrate, and PCB as three separate convergence domains, CoWoP points toward a tighter corridor: interposer → transition patch → platform PCB.

That can potentially improve power-delivery proximity, reduce package-dominated loop inductance, keep active VRM components on the board, preserve DDR/LPDDR manufacturability, support flexible UCIe routing, and reduce some package-size and substrate-related burdens. But it also demands stronger governance.

What makes CoWoP practical

CoWoS proved that advanced packaging is central to AI scaling. Wafer-scale integration proved that silicon-scale system integration can unlock a different class of compute architecture. CoWoP may become an important middle path: wafer-level density brought closer to the platform PCB, with power, memory, routing, and system realization governed through a shorter corridor.

However, the most important CoWoP challenge is not only substrate removal; it’s the transition from silicon/interposer scale to PCB scale. The opportunity is not that CoWoP solves every problem. The opportunity is that it relocates the problem to a corridor that may be more scalable, more board-integrated, and more compatible with practical power and memory placement.

The challenge is that this corridor must be governed. Low-loss materials, pitch translation, transition-patch reliability, VRM proximity, PDN impedance, loop inductance, decoupling, LPDDR routing, UCIe flexibility, shielding, thermal behavior, warpage, and lifecycle reliability must be treated as one convergence problem. This is where STRL becomes relevant.

The future question is not only whether CoWoP can be built. The future question is whether the interposer-to-transition patch-to-platform PCB corridor can remain electrically, thermally, mechanically, manufacturability, and operationally converged across lifecycle. That is trusted realization.

It’s also the next bottleneck. And it may also be the next opportunity.

Interoperability moves data. STRL qualifies evidence. Governed convergence closes decisions.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 2 of the mini-series on advanced packaging. Part 1 highlighted the basic comparison between CoWoS, wafer-scale integration, and CoWoP technologies.

Related Content

• True Wafer-Level Packaging
• Wafer Level Chip Size Package (WLCSP) Guidelines
• Intel’s Embarrassment of Riches: Advanced Packaging
• Nvidia, TSMC, and advanced packaging realignment in 2025
• Intel flash move could put wafer-level packages on the map

The post The interposer-to-PCB realization corridor in CoWoP appeared first on EDN.

Built around the NXP RW612 wireless MCU, Quectel’s FCM365X module combines dual-band Wi-Fi 6, Bluetooth LE 5.4, Zigbee, and Thread connectivity in a single device. It integrates a 260-MHz Arm Cortex-M33 processor with TrustZone, 1.2 MB of SRAM, and 8 MB of flash, with optional PSRAM expansion.

The FCM365X gives developers the flexibility to support multiple wireless protocols while simplifying device design. Zigbee and Thread enable low-power, reliable mesh networking across smart home and industrial IoT ecosystems, with Thread emerging as a key technology for Matter-enabled devices.

Suited for power-constrained applications, the FCM365X offers multiple low-power modes and keep-alive mechanisms. Standard interfaces include GPIO, SDIO, UART, USB, SPI, and JTAG, while the QuecOpen SDK enables access to I²C, I²S, ADC, LCD, and PWM. The module also complies with WPA-PSK, WPA2-PSK, and WPA3-SAE security standards and uses AES-128 encryption.

The FCM365X is housed in an LCC+LGA surface-mount package with a compact footprint of 25.5×18.0×3.16 mm. A timeline for availability was not provided at the time of this announcement.

FCM365X product page 

Quectel Wireless Solutions

The post Wireless module simplifies multiprotocol IoT design appeared first on EDN.

The TPM1R408RH 80-V N-channel MOSFET is built on Toshiba’s latest-generation low-voltage U-MOS11-H process. It features an optimized device structure with an RDS(on) of 1.4 mΩ—about 26% lower than the 80-V TPM1R908QM based on the previous-generation U-MOS X-H process. It also improves the RDS(on)-Qg tradeoff, reducing figure of merit by ~45% versus the TPM1R908QM.

These reductions lower power loss in switch-mode power supplies for industrial equipment such as AI data centers and communication base stations. The TPM1R408RH also suppresses drain-source voltage spikes during switching, reducing EMI. This helps minimize late-stage design rework and simplifies filter and snubber circuits.

The MOSFET is supplied in the SOP Advance(E) package, which delivers approximately 65% lower package resistance and approximately 15% lower thermal resistance than Toshiba’s current SOP Advance(N) package. This reduces conduction losses and improves thermal performance, enabling higher power density in compact power supply designs.

The TPM1R408RH is available through Toshiba’s authorized on-line distributors.

TPM1R408RH product page 

Toshiba Electronic Devices & Storage 

The post 80-V MOSFET improves power supply efficiency appeared first on EDN.