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A fundamentally new approach is required to fuse AI-driven automation and multiphysics intelligence across the entire design and manufacturing flow. That was the crux of the keynote by Synopsys president and CEO Sassine Ghazi at the SAFE Forum 2026, held by Samsung Foundry in San Jose, California.

Ghazi especially mentioned design and technology co-optimization (DTCO) initiatives for synthesis and layout, as well as sign-off, delivering meaningful power, performance, and area (PPA) enhancements. He also talked about the design partnership between Samsung Foundry and Synopsys, which encompasses production-ready, AI-powered EDA tools, certified interface IP, and silicon-based test capabilities.

Hyung-Ock Kim, VP and head of the Foundry Design Technology Team at Samsung Electronics, echoed similar views, stressing the need for close alignment across design, test, and manufacturing to ensure the success of AI and multi-die designs on advanced nodes.

He also presented an update on Samsung Foundry’s collaboration with Samsung for production-ready, AI-powered digital and analog flows. “Our continued close collaboration with Synopsys delivers silicon-based, customer-validated solutions that help our customers reduce design integration risk, improve silicon predictability, and move confidently from design to production for their most innovative solutions,” Kim said.

Ravi Subramanian, chief product management officer at Synopsys, briefed on AI-powered digital and analog flows for Samsung’s second- and third-generation 2-nm processes. “As designs become more heterogeneous, customers need production-ready, silicon-proven solutions that address complexity and minimize risk from silicon to systems,” he said. “Our work with Samsung Foundry translates years of DTCO and silicon learning into enablement that helps our customers get their advanced designs to market quickly and with confidence.”

The partnership encompasses AI-powered EDA flows, multiphysics sign-off, interface IPs, and silicon-based test patters. Source: Synopsys

Below are the five key tenets of this design partnership between Samsung Foundry and Synopsys.

1. Production-ready digital and analog flows for 2-nm process

As part of DTCO initiatives, Synopsys Fusion Compiler delivers measurable power and performance improvements in the third-generation 2-nm class process compared to the second-generation 2-nm class process.

2. Sign-off with certified multiphysics capabilities

Synopsys PrimeShield process sensitivity analysis and PVT Explorer support design-specific optimization and engineering change order (ECO) decisions during sign-off. That leads to frequency improvement of up to 2.7% within 5% leakage current degradation. Moreover, Synopsys Totem-SC, a newly certified electromigration (EM) and IR drop analysis solution, improves silicon design power integrity and reliability in second-generation 2-nm and 4-nm class processes.

3. 3DIC with hybrid copper bonding

Samsung Foundry and Synopsys have joined hands to enable scalable 3D multi-die designs through certified multiphysics signoff solutions delivered within Synopsys 3DIC Compiler, a unified exploration-to-signoff platform being validated on a hybrid copper bonding (HCB) 3D test chip.

This platform brings together planning, implementation, and multiphysics analysis to enable co-optimization across integrated compute, memory, and advanced packaging systems for Samsung’s 3DIC solutions with HCB technology. And it replaces manual, margin-based approaches with automated, AI-driven system optimization to accelerate productivity and enhance the quality of results (QoR).

4. Interface and foundation IP portfolio

Synopsys offers a broad portfolio of IPs across Samsung Foundry’s advanced processes, ranging from 14-nm, 8-nm, and 5-nm processes to the latest 4-nm and second-generation 2-nm nodes. The interface IP offerings cover UCIe, PCIe 7.0, 112G/224G, MIPI, LPDDR6, DDR5 MRDIMM Gen2, and USB4. Likewise, its foundation IPs include embedded memories, logic libraries, GPIOs, security IP, and Silicon Lifecycle Management (SLM).

5. AI-powered tests

Samsung Foundry and Synopsys are also applying silicon-proven methodologies to design-for-test (DFT) and manufacturing test capabilities to reduce test cost and improve test quality for designs on advanced process nodes. Furthermore, physically aware tests and failure diagnosis at the die and multi-die level improve test quality and failure analysis turnaround time with results validated on silicon at Samsung Foundry.

For instance, Samsung Foundry teams employed Synopsys TestMAX along with AI-assisted automatic test pattern generation (ATPG) technologies to reduce test patterns and test cycles by up to 20%. Samsung Foundry customers leveraging these AI-powered, silicon-based design and manufacturing test capabilities acknowledge test efficiency improvements of up to 20%.

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The post 5 takeaways from Samsung Foundry’s design tie-up with Synopsys appeared first on EDN.

A welcome career transition (and employer-responsibility expansion) begs for a hardware-plus-software evolution. Hold his beer; this engineer’s got this.

As some of you may have already noticed (assuming you even care about such things), my relationship with EDN recently (and happily) re-deepened. After being a full-time as a (senior, eventually) technical editor from 1997 to 2011, I returned beginning a year later, this time as a content contributor. And now I’ve added associate editor to my EDN repertoire.

“Wait,” you might be asking, “isn’t Aalyia Shaukat the associate editor at EDN?” You’re part-right; for nearly four years, she was. And for a couple of recent months, she (somehow) worked a double shift of jobs. But she’s now the full-time editor-in-chief at Power Electronics News, where she’s already rockin’ the house with her talent abundance. And I’m grateful to follow in her EDN associate editor footsteps, along with continuing my own frequent content-contribution cadence.

What’s this all got to do with “de-commingling (or if you prefer simpler vocabulary, “separating”) LAN equipment”? An excellent question. Now that I’m more intimately interacting with the EDN website and other publication (and publisher, and corporate owner) resources and services, I needed to set up a standalone computer so that nothing attacking my home office LAN could make its way to the corporate network and other facilities, too. That said, I remained heavily broadband-reliant. And I wasn’t up for setting up a completely separate Comcast service connection just for a single (albeit also a singularly important) computer. What to do?

Just call me “guest”

That last part was actually the easiest part to solve, it turns out. My home LAN, as mentioned before, is based on a multi-node mesh implemented using multiple Google Nest Wifi routers, with the primary one connected to the cable modem in the furnace room.

One nifty nuance of the Google Nest Wifi system (shared by not only other Google LAN equipment generations and gear from other suppliers, mind you) is that you can set up a distinct “guest” network that by default (which I’ve left unchanged in my case) is packet-isolated from the main LAN beyond their shared WAN connection.

The computer I’m dedicating to my EDN associate editor work is one you’ve seen before; a Microsoft Surface Pro 7+ (SP7+):

along with my longstanding tech-gear companion, a Kensington Dock:

mated as so:

LAN-migrating the SP7+ was easy-peasy. I disconnected the wired Ethernet cable from the back of the Kensington Dock, switched the computer from my main “RockyMountainBri” wireless network to “RockyMountainBri-guest”, and…that was it. And since my Brother multifunction laser printer was right next to the computer, I didn’t even need to bother migrating the wireless network that the MFC was connected to, foregoing printing support for the rest of my LAN in the process. I just ran a USB cable from the Kensington Dock to it, and…I was done. Perhaps obviously, by the way, any real guests are no longer able to use my “guest” wireless network.

Split personality

How do I handle the fact that, still acting as a contributing editor along with my other contributor colleagues, I’m now in effect submitting content to myself for subsequent publication, now wearing my associate editor hat? My contributing editor workflow is unchanged, actually. The only thing that’s different is the email address I now send my stuff to.

It used to be that I’d submit content from my personal email account to Aalyia’s corporate email address. Now, instead, it’s my corporate email address that the goods go to. I’m still using one of my other systems for initial writing—typically but not always a Mac. But, to maintain “firewall” purity between my newly transformed associate editor work system and the rest, I exclusively receive corporate email (and don’t send or receive personal email) on the SP7+.

Going loc(al, not o)

And what about backing up and archiving all this content I’m now receiving? Regular readers may remember that I’ve long been a fan, along with a frequent implementer and upgrader, of network-attached storage (NAS) for such (and other) purposes. That said, unless I wanted to dedicate a NAS solely to my “guest” network and connect it exclusively over slow Wi-Fi, I was going to need to transition to some other solution.

Therein lies the admittedly and intentionally somewhat obscure title of this piece. Instead of network-attached storage, I wanted something locally tethered. It had to be at least dual drive configuration, with RAID 1 support so I didn’t lose everything if a hard drive died. And ideally it’d run hardware RAID to avoid bogging down the computer. Yes, I know, if the RAID controller fails, you’re dead in the water, too, which is why I also wanted something that was reasonably popular. That way, I could, if necessary, find a replacement to slot the HDDs into without too much trouble.

I figured I’d start my search using the term “DAS”, for direct-attached storage. Interface technologies I’d used in the past—Firewire, Thunderbolt, and eSATA among them—weren’t relevant to this particular hardware configuration, so I settled on USB 3.x, as fast a flavor as possible, over USB-C. My (perhaps imperfect) search yielded exactly one result, QNAP’s TR-002, which ironically is primarily intended to capacity-expand the company’s NASs but can also find use as a standalone storage peripheral.

Tomato, tomahto

At this point, I reset my lingo-options list, expanding beyond “DAS” to also include “enclosure”. That change helped a lot from a results-options list length standpoint. What I’ve ended up with is the Mercury Elite Pro Dual from a company I’ve mentioned multiple times before, Other World Computing (aka, OWC) and bought open-box (with 1-year warranty) for $167.50.

It’s hardware RAID-based, supporting four different operating modes (albeit only one at a time):

• RAID 0 “Drive Striping”
• RAID 1 “Drive Mirroring” (the mode I’m using)
• Span, and
• Independent Drives

Its interface to the computer is 10 GBps USB 3.2; perhaps obviously, I’m direct-connecting it to the SP7+ versus going through the Kensington Dock intermediary. It also embeds a three-port hub, a particularly attractive proposition given the SP7+’s dearth of integrated connections. And here’s a rarity (as I’ve written about before); the hub’s USB-C and dual USB-A ports are all 10 Gbps peak bandwidth-capable, too.

Why, you might be asking, did I go with HDDs instead of SSDs? I’ll turn around and ask you a question in response to yours: have you priced SSDs lately? That said, HDD price tags are also skyrocketing lately, although they still hold a tangible edge over solid-state alternatives especially at higher capacities. And in my case, I thankfully was able to repurpose a couple of spare 3TB HDDs I’d already bought in the “before times” and still had sitting around unused (I’ll have more to say here in an already-planned upcoming follow-up post).

Software completes the magic trick

The last, but not the least, question: how to integrate it with my computer for mirroring and broader backup purposes? I planned on consistently using the SP7+’s upgraded-by-me 1 TByte SSD as primary storage of in-process and completed associated editor work, so one-way mirroring (versus two-way syncing) that portion of the SSD to external storage would be fine.

But I wanted that mirroring to be file-by-file, not lumped together into some unified-file or otherwise nonstandard format (Apple’s Time Machine, for example) that would make it difficult to resurrect the contents if primary storage in the computer failed, say, or if I needed to physically pass the external storage device to someone else. And, of course, I’m also looking for cheaper solutions, so open source or another free source would be best.

I found my solution in a two-part open-source program suite, developed and maintained by the FreeFileSync project and supporting Linux, MacOS and Windows platforms. FreeFileSync itself does the sync-and-mirror heavy lifting for both files and the folders containing them. And the closely related RealTimeSync monitors directories for content changes, which then kick off FreeFileSync (or any other operation more broadly).

This discussion thread was very helpful when I was setting up RealTimeSync and FreeFileSync on my system. And ever since then, it’s run like a charm; the only time it pauses is when it detects an abnormally large number of changes (multiple directories-and-files moved at once) and wants my OK before it proceeds.

Oh, and by the way…since I’ve got plenty of empty capacity available, at least at this early stage in my associate editor career, I’m also using the OWC Mercury Elite Pro Dual more broadly as a successor to the NAS for my ongoing computer-wide backup purposes using Windows’ built-in File History and (deprecated but still functional) Backup and Restore facilities that I’ve mentioned before. With that, I’ll wrap up for today. I hope what I’ve shared will be of help to at least some of you in similar configuration situations either now or in the future. As always, please share your thoughts on what’s worked (or not) for you in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

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• The Microsoft Surface Pro 5 succession: Selections, motivations, and initial impressions
• Beefing up backup
• USB 3: How did it end up being so messy?

The post De-commingling (?) LAN equipment: It’s all in what you call it appeared first on EDN.

The planet is facing a crisis in energy demand versus supply, and data centers are at the center of this dilemma due to the increasing demand from new data-intensive applications. This article will explore the causes of data center inefficiency and speculate on methods to improve efficiency. It will also acknowledge the U.S. Department of Energy’s analysis on energy efficiency, which provides a basis for this work.

Energy demand and where it’s being used

The announcement that Three Mile Island nuclear reactor was being recommissioned to power an AI data center might have been shocking news to some, but it’s no secret in the industry that the exploding demand for energy is outpacing our ability to deliver power to data centers. For the first time, power efficiency is now a higher priority to data center architects than performance of the individual components.

Semiconductor Research Corp. modeled this increase in energy demand in the context of the planet’s projected energy generation capacity, which includes the assumption that more nuclear power plants will be deployed. Figure 1 shows a daunting projection, and the potential for the lines of supply and demand to intersect around the year 2055 has the electronics industry rethinking its choices in how data centers can be designed.

Figure 1 The worldwide energy consumption trends show that we will eventually consume more energy than we produce. Source: Stanford University

Sadasivan Shankar at Stanford University broke down the places where we are spending that energy. In addition to AI, another culprit in energy demand is cryptocurrency. When combined, AI and crypto are consuming over 1.5% of the planet’s energy already. Some projections estimate that their data consumption will increase to 3% by 2030 and 4.4% by 2035 (see Figure 2). Note the scaling for the Y-axis in Figure 2: Applications such as cryptocoin mining require 18 orders of magnitude more energy than the base instructions on which the computers operate.

Figure 2 The energy demands for AI and cryptocurrency are a magnitude greater than that of other operations. Source: The U.S. Department of Energy

With this in mind, it makes sense to determine the efficiency of a data center by measuring the work accomplished for each watt that is spent. Figure 3 breaks down the power consumption per operation. It’s critical to note that almost every operation in the top two-thirds of the table refers to moving data around, while the bottom third of the table represents data processing.

Figure 3 Data centers consume different amounts of power for different functions. Source: Wolley Inc.

The memory, storage, and communications hierarchy is commonly shown as a pyramid, with processor registers at the top, various levels of cache followed by DRAM, then storage and communications at the bottom. This article will use this simplistic model, as shown later in Figure 5. The pyramid’s biggest issue is that it does not highlight how each resource is on a separate bus. In addition, moving information from one resource to another typically involves multiple movements on many buses, each of which consumes power and generates heat.

Figure 4 shows an example in which an application is read from the disk though the CPU across one channel—for instance, a PCIe—to be written to the memory over another channel (for example, a DDR), only to be read back to the CPU one cache line at a time to execute the application and store the temporary results back to the memory.

Figure 4 Here is how data movement demands high power. Source: IEEE

The application may read content across a communications channel, such as PCIe to a wide area network, then crunch that data to be written back to the disk. Even in this simple example, it’s obvious that data processing is an exceptionally minor outcome and that data movement is dominant. The percentage of data operated upon rather than moved around is close to zero as to be unmeasurable.

Why focus on memory?

Memory utilization is a focus area because there is a high potential to make substantial improvements in energy efficiency. Memory consumes as much power as many CPUs, at about 22% of server power. The increasing number of tiers of memory creates both the best and worst of trends.

The good news is that more power-efficient memories are being added closer to the processor. The bad news is that these near-memory tiers have limited capacity and require additional larger capacity, higher power memories to keep filling the datasets into the local memory. The power consumption of each tier adds to the total power footprint.

High bandwidth memory (HBM), for example, offers an interface around 1.5 pJ/bit, which compares favorably to a double data rate memory module at 15pJ/bit (see Figure 5). Unfortunately, these memories still burn significant power—for instance, 75 W or 100 W per HBM stack—and they are co-located with the high-power processor on the same substrate. This makes cooling extremely challenging compared to DDR modules, which are around 15 W each but located farther from the processor in areas that may be air-cooled.

Figure 5 Memory and accompanying storage consume considerable amounts of energy. Source: Monolithic Power Systems

Efficiency by tier

Speculation can improve system performance tremendously, but speculation always implies waste as well—even processor registers have implied waste. A system variable with a 32-bit integer that never assumes a value outside the range 1 to 10 has an implied waste factor of 87.5%. Processor caches have very high hit rates of 95% and higher, so one could invert that number to imply a 5% waste. DRAM access efficiency drops the further the memory is from the processor, with direct attached DDR memory at 27% waste and CXL-attached DDR at over 40% waste.

These numbers may not sound bad until one considers the activity inside each DRAM that allows cache line hit rates. The majority of processors operate with a 64-byte cache line. Consider how 64 bytes map to the internal structure of a DRAM. Each DRAM has an internal page buffer of 1 kB, and DRAMs are typically combined into ranks for 10 DRAMs energized per access (see Figure 6).

Figure 6 DRAMs are typically combined into ranks for 10 DRAMs energized per access. Source: Monolithic Power Systems

To fulfill a single cache line, a DRAM module is “activated” to read 1 kB from each DRAM into its sense amplifiers, or 10 kB across the width of the module. 64 bytes are read and sent to the processor. DRAM activation is destructive—the cells of the memory core are wiped out by the activation—so the cells must be rewritten from the sense amplifiers back into the core. The math for a single random access is 20 kB moved for 64 bytes of work, or 99.7% waste.

This factor of 0.3% efficiency is only against that movement of a 64-byte cache line. If that DRAM tier is operating at a 60% hit rate, efficiency drops to 0.18%. If only 1 byte from that cache line was actually needed, the waste factor increases to 99.98%. As you can see in this simple example, data center efficiency is rapidly approaching zero.

Another form of speculation that improves system performance is execution and access speculation, where a processor may pre-load code on both sides of a branch condition in case the branch is taken. Many SSDs do the same, pre-loading pages that may be accessed. These forms of speculation have 100% waste if the branch is not taken or the access is never made.

Total cost of ownership (TCO)

With electricity access becoming a bottleneck for data center expansion, architects are finally acknowledging that total cost of ownership (TCO) is a primary factor driving system design. While processor vendors focus strictly on performance, their customers are forced to determine whether they can power these machines and cool them. By some estimates, cooling a data center is currently consuming 43% of the cost of operating a data center, which is equivalent to the 43% required to run the machines themselves.

This expenditure is driving architects to measure efficiency not only as petaFLOPS/second but also petaFLOPS/watt-hour.

Improving memory energy efficiency

Improving the accuracy of speculative accesses is an obvious key to taming memory subsystem power consumption. Similar to telling a doctor “It hurts when I do this,” system architects should ask the question, “Is this speculative access successful often enough to pay for the energy consumed?”

For example, if a CXL memory module is in a memory pool and shared by multiple processors, what is the hit rate on any particular bank of DRAM? Should a page be left open, delaying precharge in case of another hit on that row of memory or be closed, issuing the precharge immediately under the assumption it will not be accessed?

Non-uniform memory access (NUMA) has been in server architectures for years to allow tightly coupled processors to share memory resources as demand shifts. However, multiple hops for each memory access can more than triple the power consumed, whereas moving the task to a processor closer to the memory resource can significantly reduce power (see Figure 7). Computational storage is a variation of task relocation that has had some success, though this success is limited by standards for the tasks executed on the devices.

Figure 7 For a server DRAM module, moving the task to a processor closer to the memory resource can significantly reduce power. Source: Monolithic Power Systems

Similarly, placing data in the appropriate tier of memory can have a significant impact on energy consumption. Figure 8 shows the temperature of the data, where hot data is accessed often, and cold data is accessed less often.

Figure 8 Map data based on how often it’s accessed to determine its temperature (where “hotter” data is accessed more often). Source: Monolithic Power Systems

Persistent memory is a system option that can be exploited for data reliability. Persistent memory is either based on a memory technology that does not lose its contents if the power fails (for example, MRAM) or uses an energy source to maintain data integrity by saving DRAM contents in a non-volatile memory (NVM), such as a flash-on power failure. Persistent memory can also be thought of as a significant way to reduce system power by eliminating the need for “checkpointing,” or saving intermediate results (see Figure 9). In many systems, checkpointing is responsible for 7% to 8% of the system traffic and therefore power.

Figure 9 Persistent memory can reduce checkpointing. Source: Monolithic Power Systems

Hybrid memory modules that combine storage and direct access memory on the same module are available to minimize system traffic as well. For example, flash memory mounted as an SSD can be coupled with DRAM, which is directly accessed by a cache line at a time. The efficiency of hybrid modules comes from the statistic of the typical 4-kB block moved from SSD to system memory; only 100 bytes on average are used, which results in an efficiency of only 2.5%.

Software has a huge impact on efficiency

Hardware cannot fix every challenge; software plays a significant role in taming this beast, too. Zooming in on the power consumed by data type, orders of magnitude more power are used for complex and large data types such as floating point, whereas integer math consumes far less power (see Figure 10). This may be as simple as programmers considering the range of values needed by variables in their software. For example, “for (i=0; i<10; i++)” does not need for i to use a 32-bit counter value.

Figure 10 Software plays a significant role in energy consumption. Source: The U.S. Department of Energy

The choice of variable types is sometimes the result of using the wrong programming language for the task (see Figure 11). Not all programming languages allow much flexibility in choosing the data types for variables, and these impacts are magnified tremendously by the matrix math employed by languages such as Python, a common tool for AI applications. Python has another energy-consuming characteristic: the programmer source is compiled to bytecode and then interpreted by a virtual machine as opposed to C programming, which compiles to processor native codes.

Figure 11 Programming languages can be ranked based on their energy consumption. Source: Wireunwired Research

You can’t fix what you can’t measure

Measuring runtime power is a key to tuning efficiency. The voltage regulators for memory modules—such as the MPQ8894, MPQ8895, and MPQ8896—are power management integrated circuits (PMICs) with an integrated system management interface to I2C, I3C, or SidebandBus. This system management interface allows the host system to interrogate the PMIC while the system is running. The current used by each voltage rail can be read from the PMIC to calculate the total power for the memory module while running test and measurement programs, or even while customer applications are running.

Triggers may be configured into the PMICs, and these devices can keep logs of any conditions that exceed the expected maximums. The host system may respond to the triggers by reading the telemetry registers and then acting on those conditions, such as by throttling applications that exceed system-imposed limits.

Choosing the right PMIC is a power-saving measure. With improved 4% power regulation efficiency when compared to competing solutions, this results in a total data center power reduction of 2%. For a typical 300 megawatt-hour installation, this would reduce power by 6 MWh and CO2 emissions by roughly 4 metric tons per year.

The power balancing act

Data centers are projected to keep increasing power demands until they become physically or financially impossible to expand. So, the total cost of ownership has become a focus for all datacenter architects as they balance the needs for performance from their customers with the reality of providing those services in a cost-effective manner.

Data center efficiency, as measured by the data processed vs. data moved around, is embarrassingly low. However, there are several ways to adjust efficiency, from cache management parameters to speculation priorities. Resource and job allocation over fabrics such as NUMA and CXL enable new classes of optimization.

The careful selection of energy efficient components such as voltage regulators can play a significant role in reducing the energy use of a data center. Every percentage of efficiency improvement leads to major reductions in CO2 emissions, a leading cause of pollution. Voltage regulators, for instance, take a holistic view of the system solution, providing high efficiency coupled with methods for measuring and fine tuning the solution to achieve optimal power savings.

Software plays a huge role in efficiency as well, from the low-level allocation of data types to the choice of programming languages for each task. In addition, measuring system efficiency at runtime helps data center operators monitor the health of the system and give insight into ways to improve or limit power as needed. Next, telemetry information helps system software to understand where energy is being used.

Most importantly, TCO analysis requires a change in mindset from operations per second to operations per watt-hour, a major shift forced on the industry by skyrocketing power demand. The use of high efficiency voltage regulators helps reduce data center energy usage, which lowers the cost of providing data services.

Bill Gervasi is principal memory solutions architect at Monolithic Power Systems.

Related Content

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• Space-Station Tech Pivots to Cool AI Data Centers
• Data Centers in Space: A Brilliant Idea or Delusional?
• Data center power meets rising energy demands amid AI boom

The post Taming the beast: Memory efficiency in an AI/crypto world appeared first on EDN.

Toshiba is sampling its TXZ+ Entry-Class M4H microcontroller group for small-scale system control of consumer and industrial equipment. Powered by a 120-MHz Arm Cortex-M4 core with an FPU, the devices deliver the real-time performance needed for applications ranging from home appliances to factory automation.

M4H MCUs operate from a 2.7-V to 5.5-V supply, supporting 5-V powered equipment. A built-in high-speed oscillator provides ±1% accuracy across a –40°C to +105°C temperature range, eliminating the need for an external oscillator. Integrated peripherals include a 12-bit ADC, timers, UART, SPI, I²C, and DMA. The devices also feature an advanced programmable motor driver for brushless DC motor control.

Engineering samples are available for evaluation, along with starter kits, sample software, CMSIS-compliant drivers, and support for major IDEs.

TXZ+ Entry-Class M4H product page 

Toshiba Electronic Devices & Storage

The post Entry-level MCUs ease system control appeared first on EDN.

Two 3.3-kV SiC power modules from Wolfspeed target high-voltage energy infrastructure, including AI data centers, renewable energy systems, and grid equipment. The HAB900C33LM4 half-bridge baseplate module supports applications above 800 A, while the IBB020A33GM4 full-bridge baseplate-less module is rated for 100 A. Both modules accommodate 2-kV and higher DC-link architectures, allowing designers to reduce power stages and use simpler 2-level topologies.

Part of the LM platform, the HAB900C33LM4 half-bridge module is intended for converters used in solar, grid-scale energy storage, and wind-power systems. Wolfspeed states that it delivers up to 42% lower switching losses than comparable SiC products and more than 90% lower switching losses than IGBTs under the same test conditions. A member of the WolfPACK family, the IBB020A33GM4 baseplate-less device is designed for modular converter architectures, including solid-state transformers and series-stacked or parallel systems.

Both power modules use Gen 4 SiC technology and advanced packaging techniques, including sintered die attach, to enhance durability and power-cycling performance. Wolfspeed says the modules also maintain switching performance over temperature, helping reduce the size of magnetics and EMI filters while increasing system power density.

Samples of the HAB900C33LM4 and IBB020A33GM4 in industry-standard packages are available through Wolfspeed’s direct sales representatives.

Wolfspeed

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AMD has introduced the Ryzen AI Halo developer platform alongside Ryzen AI Max PRO 400 Series processors to support next-generation agentic AI systems. Both platforms are designed to run AI workloads locally, reducing reliance on cloud infrastructure while supporting low-latency operation, real-time response, and large memory footprints. AMD says the platforms target AI-enabled PCs and workstation-class systems that can execute complex AI workflows, including autonomous agents, on a single machine.

The Ryzen AI Halo developer platform is powered by Ryzen AI Max+ 395 processors and provides up to 128 GB of unified system memory, allowing developers to run AI models with up to 200 billion parameters locally. Designed as a compact AI development system, it supports both Linux and Windows environments and works with frameworks including PyTorch, vLLM, llama.cpp, Ollama, ComfyUI, and LM Studio. AMD ROCm software optimization further supports local execution of large language models, diffusion models, and agent-based workflows.

Based on AMD’s Zen 5 architecture, Ryzen AI Max PRO 400 Series processors combine RDNA 3.5 graphics, an XDNA 2 NPU, up to 192 GB of system memory, and 160 GB of VRAM. The processors target commercial AI PCs, mobile workstations, and compact desktop systems handling AI, simulation, and visualization workloads.

Ryzen AI Halo systems will be available through Micro Center, with pre-orders starting in June 2026. AMD plans to expand the platform in the third quarter of 2026 with Ryzen AI Max PRO 400 Series processors.

Advanced Micro Devices 

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The MLX81119 RGB LED controller from Melexis integrates a 1-A DC/DC converter to reduce power dissipation in automotive lighting systems. The converter generates an optimized local LED supply voltage programmable from 2.5 V to 6 V.

Unlike external DC/DC converters, which add heat, components, and layout complexity, the MLX81119’s converter dynamically adjusts the LED supply voltage to match the active color mix and operating conditions. This helps minimize power losses and thermal stress. With lower power dissipation, reduced component count, and smaller space requirements, the MLX81119 is well-suited for space-constrained vehicle applications such as door panels, dashboards, and charge-port lighting.

The MLX81119 provides 18 low-side current sources configurable up to 60 mA with independent 16-bit PWM control. It supports up to six RGB LEDs per device for smooth color transitions and lighting animations. Built-in direct and indirect temperature sensing enables active compensation across all channels to maintain stable color points over the automotive temperature range.

Along with a 16-bit MCU and 32 KB of flash, the MLX81118 integrates a complete LIN system, including a transceiver and protocol handler compliant with LIN 2.x and SAE J2602. It also supports implementations up to ASIL B for functional safety-relevant interior and exterior lighting applications.

MLX81119 product page 

Melexis

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An automotive bipolar Hall-effect latch from Diodes, the AH3711Q provides high magnetic sensitivity with operate and release points of ±10 Gauss. It can be used for brushless DC motor control, rotational speed measurement, linear and incremental rotary encoders, and position sensing. Typical applications include tailgate opening and closing mechanisms, motorized sunroofs, and power windows.

The high sensitivity of the AH3711Q enables detection of weaker magnetic fields, allowing the use of smaller magnets to reduce system size and BOM cost. Increased magnetic margin also permits greater duty-cycle reduction, lowering power consumption and extending battery life.

Operating over a 3-V to 27-V range, the Hall-effect latch integrates a reverse-blocking diode and Zener clamp on the supply, while the output includes overcurrent limiting and a Zener clamp. A chopper-stabilized design minimizes switch-point drift across the full -40°C to +150°C temperature range. These features protect against 40-V load dumps, reverse polarity, and short circuits. High 8-kV HBM and 1-kV CDM ESD ratings further enhance robustness in harsh environments.

The AEC-Q100 qualified AH3711Q is priced at $0.20 in 2,000-piece quantities.

AH3711Q product page

Diodes Inc.

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Huawei’s new chip design and how it aims to bypass Moore’s Law amid a lack of access to the latest EUV lithography is now the talk of the tech town. At the heart of this semiconductor breakthrough is 3D stacking—which Huawei calls LogicFolding—alongside aggressive use of hybrid bonding technology. Huawei’s He Tingbo recently presented details of this 1.4 nm chip—to be released in 2031—at an industry event in Shanghai, China.

Read the full story at EDN’s sister publication, EE Times.

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Simple circuit ratios sensor capacitance to reference capacitor to measure micrometers.

It’s hard to imagine a simpler electromechanical sensor than the capacitance type, consisting of little more than two plates (or even just one if the sensed target is conductive) separated by a dielectric (e.g. air).  Sensor capacitance is approximately: C = 8.854pF S/d where S = area of the plates and d = their separation (both in meters).  C then becomes a sensitive readout of plate separation.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Here’s a plausible example. With 38mm diameter circular plates and initial separation of 1mm, you get a nominal capacitance of C = 8.854pF * 0.0382 * pi / 4 / 0.001 = 10pF.  C would span 3.3pF at d = 3mm to 33pF at d = 0.3mm which, with a little math, can be converted into the distance between the plates.  But how to measure C?

For that, we’ll need an interface circuit.  The one in Figure 1 is a suitably simple match for the simplicity of the capacitive sensor itself, consisting of just 8 inexpensive off-the-shelf (OTS) parts.  Here’s how it works.

Figure 1 U1a and U1b cross-coupled Schmidt trigger timers form a ~1MHz RC multivibrator. For the example sensor dimensions and parts values, Output duty factor = x = Out / 5V = d/(d + 1mm). Therefore d = x/(1 – x)

U1a and U2a form an RC timer with a time constant equal to R1Csense while U1b and U2b do the same job for R2Cref.  Cross coupling them as shown in Figure 1 creates a square wave oscillator whose ~1MHz cycle on U1 pin 3 consists of dwelling at +V for Tref = 50ksec Cref = 500ns and at zero for Tsense = 50ksec Csense = 500ns / d where d, as earlier, is measured in mm. 

Thus, the Output duty factor “x” = Tref / (Tref + Tsense) = 500ns / (500ns + 500ns / d) = 1/(1 + 1/d) = d/(d + 1). Starting from x = d/(d + 1), a bit of rearranging yields x(d + 1) = d, then xd + x = d, x = d(1 – x), and finally d = x/(1 – x).  Figure 2 shows how this math performs when the Out signal is fed into a 12bit ADC.

Figure 2 This graph shows sensor performance when Out is connected to a 12bit ADC using +5V for its reference. The black curve (left axis) = plate separation (d) in millimeters, while the red curve (right axis) = ADC least significant bit (LSB) resolution in micrometers.  Note that the resolution is close to 0.1% (d/1000) over much of the range.

Details of circuit operation include the inherent matching and tracking of U1’s gates simply because they share the same chip, and of accurate duty factor digitization if the connected ADC uses +5V as its reference voltage.  Asterisked parts (R1, R2, and Cref) are precision types.  Stray wiring and layout capacitances should be scrupulously minimized.

If there’s a chance the sensor plates might come into contact and short out, then it’s a good idea to protect U2 with a series capacitor.  0.1uF (from the same bag as C1 and C2) will work well and be sufficiently larger than Csense such that its precision and stability (or lack of thereof) won’t matter.  I’d also put another one in series with Cref, although it’s not strictly necessary, just so things look more balanced.

If your application needs position sensing in two dimensions (e.g. an XY stage), the other halves of  U1 and U2 are ready and willing, which helps to keep things capaciously and suitably simple!

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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Microcontrollers (MCUs) come in a wide array of sizes for every application, from power optimized 8-bit to 32-bit high-performance MCUs running a dedicated operating system. The amount of MCUs needed to achieve a specific application is a difficult question with no correct answer. Going too high on the spectrum creates a more expensive design, while going too low makes it difficult or impossible to implement, wasting development time.

One way to help select a product is by seeing the reference designs and demos that someone else has already made. This provides a benchmark, or point of reference, that can be used to figure out if an application is feasible and cost-effective.

As an example of this, consider this IoT irrigation demo. The demo runs on the PIC32CM-GC00 family of MCUs, which sports an ARM Cortex-M23 CPU at 72 MHz. An M23 class CPU is an entry-level device architecturally, but the max frequency of 72 MHz is higher than most, which allows this part to perform tasks that are too intensive for entry-level, but don’t require the complexity of a mid-range or high-performance CPU.

In this demo, MQTT networking for smart connectivity, a 320 × 480 display over SPI with 16-bit color, and a capacitive touch keypad for user interactions were implemented on this device, as shown in Figure 1.

Figure 1 The unmounted demo includes MQTT networking, SPI-enabled display, and capacitive touch keypad. Source: Microchip

The reason this demo is achievable on an entry-level device is because of the high CPU clock speed, ample memory, and hardware peripherals. A similar device with a lower CPU clock would struggle in this application under the computational demands of rendering graphics and the latency of transferring data from the MCU to the display controller; or, in other words, the time it takes for a graphics packet to be sent to the display. These performance hits wouldn’t be a hard design failure; instead, it would be a “soft” failure from a usability perspective, which substantially impacts the user experience and perception.

Another performance benefit for embedded designs in graphics is the display controller. Unlike a larger television or computer monitor, the display controller can offload some of the more intensive tasks, like refreshing the display or storing the image buffer. Then, the embedded system only needs to send new pixel data for the changed sections in memory, saving a large number of resources.

Selective refreshing is simple in concept, but when there are a lot of assets moving around, it becomes much more challenging to implement in an efficient manner. Rather than reinventing the wheel, this application uses the Legato graphics library to handle the rendering, and Microchip Graphics Suite to design the graphic user interface (GUI).

Microchip Graphics Suite is a visual editor that allows designers to place objects and set up assets for use at runtime. The demo control screen in Microchip Graphics Suite is shown in Figure 2. When done designing, it generates code that invokes Legato underneath to handle the rendering operations.

Figure 2 Here is the view of the main screen in Microchip Graphics Suite. Source: Microchip

Moving on to the next major piece of this demo, networking. By itself, networking on its own is a herculean task. I’ve written and debugged bare-metal networking code before, and it’s a pain with hundreds of edge cases and little idiosyncrasies that break things. Besides the base complexity of implementing the protocols, the application code must format, send, receive, and parse data on a regular cadence.

Rather than go through that process again, networking and MQTT for this design were implemented by using an add-on board with a networking coprocessor that handles the network management for the main MCU. This greatly reduces the overhead on the main MCU, and it also reduces development costs. Rather than spending engineering time and (my) sanity troubleshooting a network stack implementation to figure out why the networking is not working as expected, the add-on is already tested and is known to be working.

And, to verify that this device would fit the demo needs, I verified it before writing code by using the out-of-the-box (OOB) sample for the module. The OOB program uses a PC to send commands to the add-on board and print the responses. These are saved to a log file which can be cross-referenced later to verify the sequence of operations needed to communicate with the board. Once I am confident that the module will work for this demo, development of a simple networking driver can begin. The RNWF02 add-on board (EV72E72A) uses AT commands to communicate.

Figure 3 The RNWF02 add-on board employs AT commands for communications. Source: Microchip

While the RNWF02 board handles most of the networking complexities, the networking driver on the PIC32CM-GC00 MCU still needs to keep track of the various states of connectivity the hardware is in. For instance, the Wi-Fi connection could be completed, but the device is waiting to receive a DHCP assignment. Without DHCP, an MQTT connection cannot be completed. Another possibility is that the networking is fully functional, but the MQTT broker did not accept the connection.

Finally, there is one more piece to the networking puzzle, the server side. This isn’t the direct responsibility of the main MCU, but it’s still needed to verify the module works as expected. For testing MQTT, I used the Eclipse Mosquitto plug-in broker running on a local network Home Assistant device.

Home Assistant has a few things going for it; it’s open source (Apache 2.0) and it creates a nice, visual remote GUI for the user to interact with, without going through the same process of designing and implementing an interactive user interface (Figure 4). In an end-product, a customized app would likely be used instead, but this provides a good proxy.

Figure 4 The remote GUI is built around the open-source Apache 2.0 tool. Source: Source: Microchip

The last noteworthy element to discuss in this demo is the capacitive touch keypad. This uses the MCU’s built-in peripheral touch controller (PTC) in conjunction with the touch library to determine which keys are being pressed on the keypad. Ordinarily, using the touch library is very simple, with a call to touch_process() in the main loop and checking if the measurements are done.

The touch library handles sample timings inside of its own functional calls. But in this case, since graphic rendering can take a lot of time (milliseconds), even when optimized, the touch library may not run as often as it wants, which leads to poor touch performance and, by proxy, a bad user experience.

To solve this problem, the application calls the touch library from periodic interrupt and queues but doesn’t process any touch events that occurred. Then, when the main loop is hit again, the events are dequeued and processed. This ensures the device maintains a responsive touch interface, even under heavy CPU load.

The takeaway from this application is that high-performance entry-level devices can fill a niche where an application needs to perform an intensive operation, like graphics or networking, while not being complex enough to justify a more sophisticated CPU.

At the end of the day, the point of an irrigation controller is to switch valves on and off on a timer, which is trivial for almost any MCU to accomplish. But the other value-added functions make this too intensive for entry-level performance parts, and that’s where MCUs like PIC32CM-GC00 fit in nicely.

Robert Perkel is a senior application engineer for Microchip Technology. In this role, he develops technical content such as App Notes, contributed articles, and videos. He is also responsible for analyzing use-cases of peripherals and the development of code examples and demonstrations.

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Manufacturers of circuit-protection devices have significantly improved the performance of their safety components to protect electronic devices and equipment from a range of failures caused by electrical surges and electrostatic discharge (ESD), as well as overvoltage, overcurrent, and overtemperature conditions.

At the same time, manufacturers of circuit-protection devices such as fuses, transient-voltage suppressor (TVS) diodes, and varistors have focused on providing more packaging options, particularly surface-mount variants in smaller sizes. These more compact designs help to improve assembly and reduce costs by enabling designers to switch from through-hole to surface-mount packaging.

Here is a selection of 10 circuit-protection devices, introduced over the past year, that not only deliver enhanced performance but also tackle the need to streamline assembly and reduce printed-circuit-board (PCB) space.

Fuses

Littelfuse Inc. launched its NANO2 415 SMD Series Fuse last year, targeting space-constrained applications. The fuse is designed to provide true buffering for 250-V applications with unpredictable voltage fluctuations.

The NANO2 is the company’s first surface-mount fuse with a 1,500-A interrupting rating at 277 V, safeguarding against unpredictable surges. (The device is a 2025 Electronic Products Award Winner.)

The SMD fuse allows designers to replace through-hole devices, which helps to reduce production costs and streamline assembly processes. It also enhances surge-withstand and pulse-withstand capabilities with higher I2t values than competitive solutions, according to the company.

The NANO2 415 SMD Series is an SMD alternative to the through-hole Littelfuse 215 Cartridge Series, offering a higher voltage rating (277 V, versus 250 V). These fuses can be used in a range of applications, including consumer electronics, appliances/white goods, home automation, industrial systems, and automotive.

Littelfuse’s NANO2 415 SMD Series Fuse (Source: Littelfuse Inc.)

For 12-V power rails in servers, data centers, and telecom infrastructure, Alpha and Omega Semiconductor Ltd. (AOS) offers the AOZ17517QI series 60-A eFuse, designed to integrate accurate analog current- and voltage-monitoring signals. This current-limiting-protection eFuse monitors and protects critical power rails in data centers and telecom infrastructure to protect the main power bus from interruption due to abnormal load under fault conditions.

The eFuse leverages AOS’s advanced co-packaging technology that combines a high-performance IC with protection features and the company’s latest high-safe-operating-area (SOA) Trench MOSFET. The AOZ17517QI series’ MOSFET offers low, 0.65-mΩ on-resistance that isolates the load from the input bus when the eFuse is off. Key specs include an operating voltage range of 4.5 V to 20 V and a 27-V absolute maximum rating.

Other features include programmable soft-start, startup SOA management, and other protection circuitry, including programmable overcurrent protection, short-circuit protection, undervoltage lockout, overvoltage clamp, and thermal shutdown protection.

Multiple eFuses can be used in parallel for higher-current applications. Multiple devices can operate concurrently and distribute the current during the startup phase. The series is available in two versions: the AOZ17517QI-01 (auto-restart) and AOZ17517QI-02 (latch-off), both housed in a 5 × 5-mm QFN-32L package.

AOS’s AOZ17517QI eFuse (Source: Alpha and Omega Semiconductor Ltd.)

If you’re looking for greater options in a fuse family, Bourns Inc. expanded its Multifuse MF-LSMF polymeric positive-temperature-coefficient (PPTC) resettable fuse line with nine new models. This series now offers a wider hold current and increased voltage. The new fuse models provide hold currents up to 7 A and voltage up to 72 V, with select models in SMD packaging.

The entire MF-LSMF fuse line leverages the company’s freeXpansion technology that boosts performance by incorporating higher hold currents, increasing voltages, and enhancing resistance stability in a compact footprint. These features enable the fuses to protect low-DC-voltage ports in USB, IEEE 1394, and powered Ethernet IEEE 802.3af ports.

These fuses shield against overcurrent and overtemperature events within the specified parameters. They are suited for low-voltage telecom equipment, industrial control, security systems, and portable electronics.

In addition, the MF-LSMF Series’ SMD terminals are manufactured with electroless nickel immersion gold plating for greater component reliability and longevity. This is in comparison with the nickel-tin plating commonly used for competitive fuse terminals, which are susceptible to issues such as whisker formation, oxidation, and corrosion and can cause fuse short-circuits, according to Bourns. The devices are RoHS-compliant and halogen-free.

Bourns’s MF-LSMF Series PPTC resettable fuses (Source: Bourns Inc.)

Another fuse family designed to provide more options for designers is Vishay Intertechnology Inc.’s S2F and S3F series of thin-film chip fuses in three package sizes (0402, 0603, and 1206).

The Vishay Sfernice S2F and S3F devices ensure circuit continuity with minimal resistance and reliable interruption under overload conditions. They provide options for fast- or very fast-acting protection. Applications include secondary circuit protection across a broad range of electronic systems in which stability and precision are critical.

The fuses are UL 248-14–compliant and cover rated currents from 0.315 A to 7 A. Both series combine low resistance with body temperature rise below 75°C at 100% rated current.

The key distinction between the two series is their fusing speed at 200% overload. The fast-acting S2F series is designed to open in less than one minute, while the very fast-acting S3F series is designed to open in less than five seconds. The S2F series provides protection where brief overloads are tolerable without immediate interruption, while the S3F series is optimized for sensitive circuits that require the quickest possible response, Vishay said.

These options enable designers to tailor fuse performance to the specific protection needs of their applications. The devices are lead-free, halogen-free, and RoHS-compliant.

Vishay’s thin-film chip fuses (Source: Vishay Intertechnology Inc.) TVS devices

Semtech Corp. recently expanded its SurgeSwitch family with the TDS5311P protection device as an alternative to conventional TVS diodes. Described as the industry’s first circuit-protection device to deliver near-constant clamping voltage for USB Power Delivery (PD) Extended Power Range (EPR) applications at 48 V, the TDS5311P protects power buses operating at up to 53 V. It is purpose-built for USB PD EPR systems operating at 48 V across industrial equipment, rugged mobility devices, and high-performance portable systems.

Designers face a protection gap at 53 V, Semtech said: “Conventional TVS diodes clamp inconsistently, with clamping voltage shifting across current levels and temperature ranges.”

In comparison, the TDS5311P is reported to maintain a nearly constant clamping voltage from the first microsecond of a surge event through maximum rated current, across the full −40°C to 125°C industrial temperature range.

The TDS5311P, built on the SurgeSwitch’s surge-rated FET architecture, handles 1,512-W peak pulse power and 24-A peak pulse current. It meets the IEC 61000-4-5 industrial surge standard. The protection device is housed in a small, 2.0 × 2.0-mm DFN-6 package.

Also claiming improvements over traditional solutions, Littelfuse has introduced the 5.0SMDJ-FB series of TVS diodes to protect sensitive electronic equipment from voltage transients caused by lightning and other transient-voltage events. The series delivers up to 15% lower clamping voltage over traditional solutions and maintains breakdown voltage above the reverse standoff voltage. This ensures reliable protection for sensitive downstream components such as next-generation DC/DC converters.

The lower clamping voltage via Littelfuse’s foldback technology enhances circuit-protection performance in TVS components, including I/O interfaces, VCC bus, and other vulnerable circuits used in telecom, computer, industrial, and consumer electronic applications, specifically for power over Ethernet systems, AI and data center servers, ICT equipment power supplies, and industrial DC power distribution.

The 5,000-W surface-mount solution in a DO-214AB package provides protection in harsh environments. The operating junction temperature range is −65°C to 150°C. It is a drop-in replacement for the legacy 5.0SMDJ Series with the same compact DO-214AB (SMC) footprint. It meets IEC 61000-4-2 ESD 30 kV (Air) and 30 kV (Contact) and is recognized to UL 497B as an isolated loop circuit protector.

Littelfuse’s 5.0SMDJ-FB series (Source: Littelfuse Inc.)

Microchip Technology Inc. recently introduced its JANPTX family of non-hermetic plastic TVS devices that meet the MIL-PRF-19500 qualification for high-reliability protection in aerospace and defense applications.

These surface-mount TVS devices are claimed as the first in the industry to achieve MIL-PRF-19500 qualification in a plastic package. This packaging offers a lightweight (0.25 grams), cost-efficient solution while meeting stringent military performance requirements.

The JANPTX product line is available in voltage ranges from 5 V to 175 V and offers several variants:

• JANPTX1N5555UJ
• JANPTX1N5558UG
• JANPTX1N5629AUJ
• JANPTX1N5665AUG
• JANPTX1N5907UG
• JANPTX1N5907UJ

The JANPTX family protects sensitive electronic components in demanding environments with a high peak pulse power rating of 1.5 kW and clamping response times measured at less than 100 picoseconds in internal tests. They are designed for surface-mounting and protect against voltage transients such as lightning strikes, ESD, and electrical surges.

The advanced design of these surface-mount, unidirectional TVS devices supports protection from switching transients, induced RF effects, electromagnetic pulse, and secondary lightning events and meets IEC61000-4-2, IEC61000-4-4, and IEC61000-4-5 standards. Applications include airborne avionics, electrical systems, and other mission-critical applications in which low voltage and high reliability are essential.

Microchip’s JANPTX TVS devices (Source: Microchip Technology Inc.)

Taiwan Semiconductor Co. Ltd. expanded its automotive-grade 24-V Super Clamp TVS diode series with its first compact SMC/SMB surface-mount devices. Super Clamp TVS diodes provide ultra-low clamping voltage and high surge current in space-constrained automotive designs.

The Super Clamp snapback devices provide lower clamping voltages, higher peak pulse currents, and lower voltage ratings than conventional TVSes, according to the company. This allows circuit designers to use fewer, less costly components without impacting circuit reliability.

In addition, the new devices—SMC (LSMC24CAH) and SMB (LSMB24CAH)—offer package options that can help reduce PCB space. The complete TVS series is offered in three package types: the DO-214AB (SMC), DO-214AA (SMB), and DO-218AB.

When used in compact, surface-mount PCB layouts, Super Clamp TVSes can reduce part count and eliminate the need to overdesign to achieve automotive-level reliability. The TVS devices, with maximum pulse currents of up to 300 A, provide a margin of system protection much higher than alternative options, according to the company. They are also reported to provide higher protection than MOVs and GDTs, which are subject to failure after repetitive transients.

Varistors

Kyocera AVX recently released high-temperature, automotive-grade multilayer varistors (MLVs) for 48-V power supply systems. The new addition to the TransGuard VT Series, claiming the first in the industry to offer MLVs rated for 175°C operation, supports operating temperatures extending from −55°C to 175°C with zero derating across the entire range. They are qualified to AEC-Q200, IEC 61000-4-2, and ISO 10605.

The TransGuard VT Series MLVs are zinc oxide–based, ceramic semiconductor devices that offer reliable, bidirectional overvoltage protection and EMI/RFI attenuation capabilities in compact SMT packages that reduce the need for discrete MLCCs. They offer high current- and energy-handling capabilities, multi-strike capabilities, and low leakage.

The TransGuard TVS devices meet the highest human-body model ESD classification, at Class 6, which means they can reliably withstand over 25,000 V of ESD, Kyocera said. They also have the lowest moisture-sensitivity level, at MSL 1, providing an unlimited floor life under the specified conditions. It also means they don’t require any special dry packing or handling procedures and don’t need to be baked before reflow soldering.

The new 48-V System VT Series MLVs are designed for motor vehicles with 48-V power supplies, rated for operating temperatures up to 150°C, and additionally qualified to VDA-320. The devices are available in five EIA chip sizes (0805, 1206, 1210, 1812, and 2220) and rated for 56-VDC or 40-VAC working, 100- to 110-V clamping, 48-V jump start, 30 to 1,500 A, and 0.2- to 9-J transients. The capacitance ranges from 80 to 2,800 pF. Applications include electric vehicles, including e-bikes, e-scooters, golf carts, and passenger and commercial vehicles, as well as their charging stations.

Several TransGuard VT Series MLV part numbers, including a few of the 48-V System VT Series MLVs, are also available with the company’s FlexiTerm terminations, which can withstand severe vibrations, up to 5 mm of mechanical board flexure, and up to 3,000 temperature cycles extending to 150°C without any internal cracking, exceeding the AEC-Q200 testing requirement of 1,000 cycles at up to 125°C.

Kyocera AVX’s 48-V TransGuard VT Series MLVs (Source: Kyocera AVX)

TDK Corp. has introduced the MT40 series of ThermoFuse varistors (B72240M) for surge protection of up to 50 kA. They target applications such as inverters, industrial power supplies, outdoor lighting, telecommunications systems, and surge-protection devices.

TDK calls the MT40 series a new generation of surge-protection components (SPCs), with a compact design and advanced safety features thanks to their patented overmolding technology and integrated thermal disconnecting system. These SPCs provide protection up to 50 kA in a compact package size of 38.0 × 15.2 × 40.9 mm.

Designed for extreme electrical conditions, the MT40 series offers a peak surge-current capability of up to 50 kA (8/20-μs pulse) and a short-circuit current rating of up to 200 kA. The series is recognized as a UL 1449 Type 1CA component assembly, which means they can be used in applications with AC voltages ranging from 150 V to 550 V and DC voltages from 200 V to 750 V.

Other features include a galvanically insulated, normally open micro-switch for remote monitoring and an optional visual indicator. The operating temperature range is −40°C to 85°C. They are RoHS-, REACH-, and PFAS-compliant.

TDK’s MT40 series of ThermoFuse varistors (Source: TDK Corp.)

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One of the biggest drivers of growth and advances in medical electronics is the integration of artificial intelligence. AI, particularly AI-enabled diagnostic imaging, is a major driver of innovation, helping address the rising data volume and decision complexity produced by imaging-diagnostics equipment. Although wearables and implantables are a significantly smaller piece of the medical electronics pie, these segments are also driving improvements, particularly for sensors, analog front ends (AFEs), power-management devices, and wireless system-on-chips (SoCs).

(Source: Adobe Stock)

In the May/June 2026 issue, we look at how underlying technologies are driving improvements in medical electronic devices, from imaging-diagnostics equipment to wearables diagnostics such as continuous glucose monitors (CGMs).

The medical electronics market is expected to reach $11.9 billion in 2026, with a compound annual growth rate of 6.7% from 2026 to 2031, according to Mordor Intelligence. More than 600 AI-enabled devices were approved by the FDA by mid-2024, resulting in near-real-time workflows for image analysis, reducing both scan times and interpretation backlogs, according to the market research firm.

Contributing writer Abhishek Jadhav looks at how AI-powered medical imaging is turning data into faster diagnoses. Jadhav reports that computed tomography (CT) and magnetic resonance imaging (MRI) have created a growing challenge of data and decision-making. As imaging generates more information to interpret, AI helps to improve these systems by supporting faster, smarter workflows for higher-accuracy diagnoses.

He addresses the use of AI across the medical imaging pipeline and how it is augmented through a range of tasks, from the moment an exam is ordered to the final clinical interpretation; AI models in imaging diagnostics to perform complex tasks such as detecting minute pathological changes, precisely segmenting anatomical structures, and fusing information from different clinical sources; and how integrating AI into medical imaging brings enormous improvements in speed and operational efficiency.

Contributing writer Stefano Lovati looks at some real-world examples of AI/ML integration into medical systems and how it is improving imaging, robotic surgery, and remote monitoring. As AI/ML is increasingly integrated into medical systems, it is delivering smarter and faster care by bringing intelligence closer to where the data is created and used, he said.

Lovati finds that recent advances in computer vision, large language models, edge computing, and real-time signal processing are improving medical diagnosis and reducing the latency between data acquisition and actionable clinical results. This is enabling advances in robotic surgery and remote monitoring while delivering more integrated systems to improve patient care.

In the wearables space, one of the key advances in medical electronics is CGMs. These wearable devices enhance quality of life and allow clinicians to adjust therapy based on accurate, continuous data streams, reports Marco Doms, senior manager of business development of new platforms at Littelfuse Inc. He looks at the role of CGMs in connected healthcare as well as engineering challenges, including integrating protection and sensing for reliable operation, thermal monitoring and patient safety, and regulatory and compliance considerations.

CGMs have reshaped diabetes management by delivering real-time glucose readings, Doms said. But behind this innovation are complex engineering challenges: developing a device that operates safely and reliably on a micro-scale power budget and maintains precise sensing accuracy in all conditions while fitting into a small form factor, he said.

A key component driving improvements in medical electronics is sensors. With the wide range of medical devices, from wearable glucose monitors to CT and MRI scan equipment, there is a variety of sensors incorporated into these devices. Lovati looks at some key sensor technologies, such as pressure and temperature sensors, as well as biosensors and accelerometers.

He also examines how medical sensors work together with AFEs, power-management devices, and wireless SoCs to deliver solutions that maximize diagnostic accuracy, reliability, and efficiency.

Also in this issue is a product roundup of sensors launched at Sensors Converge 2026. This year’s conference spotlighted sensor and sensing solution breakthroughs for applications from wearables and smartphones to industrial and automotive. Sensor manufacturers continue to focus on shrinking solutions while addressing the need for lower-power-consumption devices.

Don’t miss the top 10 circuit-protection devices introduced over the past year. These new devices deliver enhanced performance and address the need to streamline assembly and reduce printed-circuit-board space.

Cover image: Adobe Stock

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The first 50G passive optical network (PON) gateway system-on-chip (SoC) incorporates a neural processing unit (NPU) for edge AI inference and offers native compatibility with the Wi-Fi 8 standard. Broadcom’s BCM68850 CPE gateway claims to offer NPU-accelerated solutions across cable, PON, Wi-Fi, and set-top box platforms, ensuring resilient infrastructure for AI offloading and high-efficiency multi-gigabit workloads.

BCM68850 aims to reshape the broadband edge as the home’s central intelligence hub. Source: Broadcom

The gateway SoC delivers full 50G throughput to meet multi-gigabit bandwidth. Besides a dedicated NPU, which reduces cloud latency and enhances data privacy by keeping sensitive information on premises, it also features a dedicated CPU for third-party and operator applications that leverage industry-standard middleware.

That, in turn, optimizes CPU and memory resources to ensure the home gateway can handle the massive data throughput required by edge AI-centric applications. “Home gateway solutions such as Broadcom’s BCM68850 SoC are critical to future-proofing the network edge,” said Jaimie Lenderman, practice leader for optical, IP, and broadband infrastructure market research at Omdia.

The standalone 50G PON Gateway SoC claims to provide an industry-standard ITU-T path for operators to future-proof their networks by processing and transmitting high-density payloads in a fraction of a millisecond. Moreover, its “burst and release” capability ensures near-zero-jitter essential for latency-critical applications.

Broadcom is currently sampling the BCM68850 home gateway SoC to its early access customers and partners.

Related Content

• Guaranteeing QoS in PON Designs
• Broadcom delivers Wi-Fi 8 chips for AI
• Gateways bridge gap between home, Net
• CES 2026: Wi-Fi 8 silicon on the horizon with an AI touch
• Gateway lets consumer control home appliances over mobile wireless nets

The post The 50G PON gateway SoC supports edge AI, Wi-Fi 8 appeared first on EDN.

How to deal with the reality that a standard buck controller power stage won’t work for negative-input conversion.

Telecommunications equipment, industrial test and other applications require a negative input to negative output voltage conversion. Because dedicated controllers for this topology are rare, you need a workaround to generate a stable output.

One solution I’ve found is to connect a boost controller’s GND pin to the negative input rail, which repurposes the device as a negative-input, negative-output buck controller and eliminates additional gate-drive circuitry. It then becomes possible to have a level-shifted feedback network regulate the output. So in this power tip, I’ll discuss two approaches using a traditional switch-mode power-supply: one using a buck controller with external field-effect transistors (FETs) and one using a buck converter with integrated FETs.

Comparing standard and negative-input, negative-output buck controllers

The power stage of a standard buck controller (Figure 1) closely resembles a negative-input, negative-output topology.

Figure 1 This simplified, standard buck controller schematic resembles that of a negative-input, negative-output topology.

A buck controller operates by applying a pulse-width modulation waveform to an inductor-capacitor filter. Each switching cycle starts when the main switch turns on, increasing the inductor current. Current flows from the input capacitor through the inductance to the output capacitor and back to the input capacitor. During the off time, the current commutates to the low-side diode (or switch) and the inductor current decreases.

Why a standard buck controller power stage won’t work for negative-input conversion

A negative-input, negative-output buck controller behaves very similarly to a standard buck controller. The main difference is that all currents flow in the opposite direction.

You cannot use a standard buck controller power stage, though, because of the orientation of the diode and metal-oxide semiconductor field-effect transistor (MOSFET) (with its internal body diode). Rotate these components as shown in Figure 2.

Figure 2 This simplified schematic details a negative-input negative-output buck controller.

Note that the output voltage cannot become more negative than the input voltage.

As an example, with a –48V input and a 50% duty cycle, the controller generates a –24V output. The controller’s control law decreases the negative output voltage toward the level of the negative input by increasing the “on” time of the main FET. So at a theoretical 100% duty cycle, the output voltage nearly equals the input voltage of –48V.

A standard buck controller will also not work here because both the input and output voltages are negative. For a negative-input, negative-output buck controller, the main FET connects to –Vin, and the cathode of the diode connects to GND. However, a boost controller works if you connect the GND pin to the negative input – a necessary step because otherwise all internal signals would be negative, creating a problem. Another reason is that a boost controller uses a ground-referred gate driver. Connecting the GND pin to the input voltage allows you to drive the FET without additional circuitry.

Using a nonsynchronous boost controller as a negative-input, negative-output buck controller

Figure 3 shows an example schematic using the Texas Instruments (TI) nonsynchronous boost controller to drive the main FET of a negative-input, negative-output buck controller.

Figure 3 This simplified schematic showcases Texas Instruments’ LM5155 boost controller.

Because –Vin is connected to the GND pin, all internal signals reference –Vin. Since –Vin typically varies across an input voltage range, this behavior can cause difficulties when enabling or disabling the device, regulating the output, or other protection features. Typically, you will need a level shifter (for example, an isolated type or one with bipolar FETs) to regulate the negative output voltage.

Configuring a boost converter for negative-input operation

A boost converter with internal switches can also work in theory, because the source of the main switch connects to the GND pin and the drain of the rectifier FET connects to the Vout pin.

Figure 4 shows a block diagram of a boost converter and the connection of the switches to the integrated circuit (IC) pins.

Figure 4 This boost converter block diagram includes the switches’ connections to the integrated circuit pins.

The challenge in using a converter is that many signals are internal. Some ICs integrate the output voltage divider, which makes regulating a negative output voltage difficult. Because all internal voltages reference the negative input, the output voltage would follow the input voltage. In that case, you can use the COMP output instead of the internal feedback. Connecting an optocoupler as a level shifter between COMP and GND provides one method to regulate the negative output.

Figure 5 shows how to connect a boost converter to a negative-input, negative-output buck power stage. The GND pin connects to the negative input, and the Vout pin (or FB pin) connects to power-stage ground. You can short the FB pin and use the COMP pin with an optocoupler to regulate the output. Keep all voltages, including current-sense signals, below the maximum limits of the boost converter.

Figure 5 This simplified schematic employs the boost converter shown earlier.

Design considerations

You can use a nonsynchronous boost controller such as TI’s LM5155 or TPS40210 as a simple, cost-effective solution for generating a negative output from a negative input. To increase the efficiency, replace the diode with a MOSFET, though doing so requires a synchronous boost controller that drives two switches. Negative voltages can easily cause confusion. In particular, you must check all internal signals and verify that no voltages are exceeding the controller’s maximum rating.

Florian Mueller is a systems engineer and Member Group Technical Staff in TI’s Power Supply Design Services group. He has a master’s degree in electrical engineering from the Technical University of Haag, Germany. Florian’s main focus lies on industrial high-voltage designs for different end equipment.

 

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• Power Tips # 141: Tips and tricks for achieving wide operating ranges with LLC resonant converters
• Power Tips #123: Using a double-boost converter to extends the power range of high-conversion-ratio designs

The post Power Tips #153: How to generate a regulated negative output from a negative input using a boost controller appeared first on EDN.

In embedded systems, where failure is not an option, NOR flash devices storing boot code, firmware images, and critical application data are subject to gradual wear over their operational lifetime. That wear is not invisible; it’s reflected in internal device registers accessible at runtime without the need for external test equipment. Per-sector erase cycle counts, single-bit and double-bit error correcting code (ECC) event counters, and hardware-accelerated cyclic redundancy check (CRC) integrity results collectively form a health profile.

This profile covers user-defined address ranges and is updated continuously as the system operates. On certain device variants, an on-board temperature sensor provides confirmation that the device is running within its rated thermal envelope. These are no fault flags that fire after something has gone wrong. They are observable quantities whose value lies in being monitored over time.

The central premise of flash diagnostics is shift from reactive fault handling to proactive health monitoring. Fault handlers consult device status when an operation fails.

In contrast, diagnostics applications read the same registers on a schedule, build a time series, and watch for early indicators of wear. Early warning paves the way for preventative maintenance, fixing impending problems before they trigger failure.

Reading wear, ECC, CRC, and thermal trends over time

Program/erase cycle counts per sector are the most direct measure of wear. Flash arrays in real-world applications are not erased uniformly. Sectors holding frequently updated data, such as fault codes logged by an automotive ECU or a partition used for over-the-air updates, accumulate cycles at a much higher rate than sectors holding static firmware.

Some NOR flash memories—such as Infineon’s SEMPER NOR Flash—offer built-in wear leveling defenses that distribute P/E cycles across the full address range. A diagnostics application periodically tracking per-sector counts can identify this imbalance early and provide the system with the information needed to act, whether by redistributing write activity or by flagging sectors approaching their service limit.

ECC event counts add a sensitivity that cycle counts alone cannot provide. Single-bit events are corrected transparently by on-chip logic and produce no visible effect on system operation, but their rate carries information about how individual cells are aging. A sector whose single-bit event rate begins to rise is showing early signs of cell wear, something the cycle count alone may not yet reflect.

When this trend is observed, rewriting the sector contents to restore cell charge state is one response the diagnostics system can initiate. To ameliorate system performance, the process can be scheduled during low-activity periods. Whether and at what threshold to trigger a refresh is a configurable decision. Double-bit events represent a harder boundary: the device detects them but cannot correct them, and their occurrence is recorded with sector address and timestamp for subsequent analysis.

CRC integrity checks over defined address ranges complement the bit-level view ECC provides, catching consistency issues that fall outside the scope of individual ECC words. For example, CRC is often used to validate a full firmware image region after an OTA update completes. Thermal reading, where available, confirms whether the device has been operating within its rated temperature range. This data assists in evaluating whether observed ECC trends reflect normal aging or accelerated cell wear from sustained thermal stress.

Diagnostics across AUTOSAR, Linux, and bare metal

The same NOR flash device frequently appears in multiple ECU variants within a single vehicle platform, each running a different software environment. A diagnostics software module such as SEMPER Diagnostics Library can be configured to span this portfolio, covering AUTOSAR Classic and Adaptive, Linux, QNX, RTOS, and bare-metal environments without changing the underlying health monitoring logic. What differs between environments is only the integration surface.

In AUTOSAR, the diagnostics module fits as a complex device driver. Positioned above the memory hardware abstraction layer, it accesses device-specific commands and register reads that the standard flash driver interface does not expose, while making its outputs available to upper-layer software components through defined RTE ports.

Figure 1 Here is how SEMPER Diagnostic Library software architecture operates in AUTOSAR environment. Source: Infineon

In a POSIX environment such as Linux or QNX, the same logic runs in user space and issues health queries through the IOCTL mechanism on an extended driver. Where the system is a heterogeneous SoC, a diagnostics agent in the real-time domain writes health query results to a shared memory region. A counterpart Linux user-space process then reads through a character device, packages with device identification and timestamps, and routes to a storage destination.

Within Linux, the Memory Technology Device (MTD) subsystem is the integration point for the flash driver, and IOCTL commands on an extended MTD driver are the mechanism by which device-specific health metrics cross the user-space boundary without touching standard read/write paths. On bare-metal or RTOS systems, the library links directly with the memory driver and is scheduled by the task manager.

In the case of SEMPER NOR Flash, SEMPER Diagnostics Library provides the diagnostic data, and the user is free to log it to local flash, route it to the cloud, store it in an external database, or any other destination that fits their system architecture. Similarly, fleet-connected deployments can route the same data off-device for population-level analysis. The underlying algorithms are identical across all environments; only the integration scaffolding differs.

Diagnostics library: Architecture and demo

Figure 2 Integration examples are shown for SEMPER Diagnostics Library module across different software environments. Source: Infineon

Figure 3 The demo setup is running SEMPER Diagnostics Library on Linux (RaspberryPi) while showing Erase Count and ECC Errors per sector. Source: Infineon

The SEMPER NOR Flash diagnostics software dashboard, shown below, visualizes per-sector erase counts and ECC counts in real time, along with device metadata—Device ID, Chip Size, Protocol, ECC State, Address Mode, Page Size—giving engineers a turnkey view of the flash health profile without requiring custom tooling.

Figure 4 The diagnostics software dashboard visualizes per-sector erase counts and ECC counts in real time. Source: Infineon

Fleet telemetry and predictive maintenance

Health metrics tagged with a unique device identifier and correlated with vehicle operating history become qualitatively more useful at scale. Patterns invisible at the level of a single device become apparent when data from a large population is examined holistically.

For example, a correlation between a specific duty cycle profile and accelerated sector wear may appear random as a single event, but causal when considered in aggregate. This is the difference between diagnosing a device that has already failed and identifying a population that may fail while every unit in it is still functioning normally.

Estimating useful lifetime also benefits from the same accumulated data. A static model applying a single worst-case endurance figure will produce overly conservative estimates. SEMPER Diagnostics Library’s adaptive lifetime estimation concept goes further: observed erase count progression, ECC event rates, and thermal history enable a per-device estimate that reflects how that specific unit has been used with the potential to refine it further through fleet-level pattern recognition, identifying trajectories that have historically preceded reliability events.

Act before wear

NOR flash devices save a continuous stream of health data in their internal registers, yet most systems discard it. Per-sector erase counts, ECC event trends, CRC integrity results, and thermal confirmation collectively describe how a device is aging under its actual operating conditions. The information is available at runtime, and no additional hardware is required to harvest it. The longer it is collected, the more valuable it becomes.

A diagnostics framework such as SEMPER Diagnostics Library captures this data, made possible via hardware such as SEMPER NOR memory, consistently across AUTOSAR, Linux, and bare-metal environments, routes it across processing domain boundaries, and makes it available for both on-device response and population-level analysis.

This gives engineers advanced notice to act before wear affects system reliability. In applications where that lead time separates a scheduled maintenance event from an unplanned failure, the case for building it in from the start is clear.

Saurabh Tripathi is senior applications engineer at Infineon Technologies.

Related Content

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• Flash 101: NAND Flash vs NOR Flash
• NOR Flash Next in AI-Driven Memory Crunch
• NOR flash memory certified for ASIL-D functional safety
• How NOR flash helps overcome design challenges in wearables

The post Flash diagnostics and health monitoring for NOR memory appeared first on EDN.

Engineers must carefully manage power, protection, and sensing interactions at every design level to achieve reliable, always-on operation in a body-worn form factor. (Source: Getty Images)

Continuous glucose monitors (CGMs) have reshaped diabetes management by delivering real-time glucose readings, freeing patients from frequent finger-stick testing. These compact, wearable devices not only enhance quality of life but also allow clinicians to adjust therapy based on accurate, continuous data streams.

Behind this innovation lies a complex engineering challenge: Designers must develop a device that operates safely and reliably on a micro-scale power budget, fits within a compact, body-worn form factor, and maintains precise sensing accuracy in all conditions. Every component, whether analog, digital, power management, or protective, must contribute to long-term reliability and patient comfort. In many designs, even microamp-level leakage or a single mechanical failure point can limit device lifetime or compromise reliability.

Magnetic sensing, particularly tunnel magnetoresistance (TMR) technology, offers a practical approach for implementing sealed, contactless activation and other event-based state-detection functions without materially impacting battery life. This article examines the role of magnetic sensing in CGM architectures, explains the operating principles of TMR switches, and discusses their applications for activation, alignment confirmation, and auxiliary-state detection. Design tradeoffs, implementation considerations, and package-level constraints are also explored to help engineers evaluate when TMR sensing is appropriate in CGM designs.

The role of CGMs in connected healthcare

CGMs are central to modern diabetes care. They measure glucose concentration in interstitial fluid using a sensor inserted beneath the skin, which transmits readings wirelessly to a smartphone, insulin pump, or cloud-based management system.

Connected drug delivery system example (Source: Littelfuse Inc.)

The benefits of CGMs are well-established: reduced glycemic variability, better HbA1c levels, and fewer hypoglycemic episodes. As the technology matures, CGMs are now prescribed for a wider population, including patients with Type 2 diabetes, gestational diabetes, and even pre-diabetic conditions, expanding their relevance across preventive medicine and chronic care.

From an engineering perspective, these devices embody the broader trend toward connected, always-on healthcare systems, in which safety, data integrity, and energy efficiency are equally critical.

System architecture and design constraints

A typical CGM system includes five key components:

• The glucose sensor and analog front end amplify and condition microvolt-level signals from the biosensor.
• The microcontroller processes data, handles algorithms, and manages wireless communication via Bluetooth Low Energy or proprietary protocols.
• The power-management circuitry regulates energy from a small rechargeable or disposable battery.
• The wireless interface communicates readings to companion devices or cloud platforms.
• Temperature sensing, protection, and activation circuits safeguard operation and enable user interaction.

Simplified CGM system block diagram (Source: Littelfuse Inc.)

These modules must function continuously for seven to 14 days on a single charge, all while exposed to motion, sweat, temperature fluctuations, and electrostatic discharge (ESD). Component size, thermal behavior, and power efficiency dictate patient comfort and product usability.

Engineering challenges unique to CGM design

Engineering challenges in CGM design include achieving ultra-low power consumption and extreme miniaturization in limited PCB space while maintaining electrical safety/isolation and environmental resilience. Designs must also meet stringent regulatory compliance requirements:

• Ultra-low power consumption: Every microamp of leakage current reduces battery life. Components must have negligible quiescent draw.
• Miniaturization: Patch-style and implantable CGMs allow only millimeters of PCB space, demanding small-package, high-performance devices.
• Electrical safety and isolation: Circuit faults must be contained quickly to protect the patient and device integrity.
• Environmental resilience: Resistance to sweat, vibration, and humidity ensures consistent operation throughout the wear cycle.
• Regulatory compliance: Designs must comply with IEC 60601, ISO 13485, and 21 CFR 820 requirements for safety, quality, and EMC performance.

Meeting these demands requires careful component selection and system-level integration.

Magnetic activation for sealed, contactless operation

Power-on and reset functions are fundamental in wearable devices. Traditional mechanical pushbuttons introduce contamination paths, wear over time, and complicate waterproofing. The activation circuit keeps energy consumption during the shelf life to a minimum, ensuring the device remains safe to operate after 24 months. Magnetic activation provides a contactless alternative that enhances durability and hygiene.

Three magnetic-switching technologies are available: reed relays, Hall-effect sensors, and TMR switches. Each presents tradeoffs in power consumption, sensitivity, and footprint (see Table 1 for a comparison). In practice, the key differentiator is standby current, whereby TMR operates in the nanoamp range, versus milliamps for typical Hall-effect devices.

Table 1: Sensing technologies comparison (Source: Littelfuse Inc.)

TMR sensors offer a highly effective combination of performance characteristics for CGM applications: nanoamp-to-microamp power levels, compact LGA packages, and omnipolar detection for flexible magnet placement.

For example, Littelfuse TMR magnetic switches detect flux changes as low as 9 Gauss and draw only 160 nA in low-speed mode. Their contactless operation enables features such as automatic power-on when the device is applied to the skin or activation during packaging removal. Because they have no moving parts, TMR switches are immune to vibration and moisture, providing a lifetime of tens of billions of switching cycles.

TMR magnetic switches such as the TMR LGA4 Switch LF21173TMR enable contactless activation through a sealed enclosure. (Source: Littelfuse Inc.)

By eliminating mechanical interfaces, engineers reduce mechanical failure risk, improve sealing, and extend battery life—all critical for patient-worn electronics. This approach makes TMR switches particularly attractive for designs in which activation must remain available throughout storage and use without impacting overall system power budgets.

Thermal monitoring and patient safety

Temperature sensing plays multiple roles in CGM design:

• Electronic safety monitoring detects abnormal heat buildup from circuit faults or battery degradation.
• Patient protection prevents surface temperatures that could irritate or burn the skin.
• Sensor compensation adjusts for temperature-dependent enzymatic reactions that influence glucose readings.

Compact NTC thermistors, such as Littelfuse’s 0803-KR, 0603-RB, and 1206-LR series, offer ±5% accuracy in packages as small as 1.6 × 0.8 × 1.0 mm. Engineers often use multiple thermistors: one near the biosensor for reaction compensation and another near the battery or power-management circuitry for thermal safety monitoring.

Precise thermal feedback not only protects users but also enhances measurement accuracy, contributing directly to clinical reliability.

The number, location, and role of temperature sensors vary by CGM architecture, but designers generally distinguish between temperature sensing for safety monitoring and temperature sensing used for measurement compensation.

Integrating protection and sensing for reliable operation

Effective CGM design blends protection, sensing, and activation elements into a cohesive system. Integration offers several key benefits:

• Extended battery life through ultra-low leakage protection and sensing components
• Improved mechanical reliability by eliminating moving parts and exposed contacts
• Simplified certification when using pre-qualified components compliant with medical standards
• Enhanced user confidence through consistent, failure-free performance

When these design principles are applied, engineers can focus on refining algorithms, connectivity, and patient-experience features rather than troubleshooting hardware faults.

Regulatory and compliance considerations

Every CGM must meet stringent international standards to ensure safety and performance. Table 2 outlines the most relevant to electronic subsystems.

Table 2: Applicable international standards for CGM compliance (Source: Littelfuse Inc.)

Choosing electronic components with existing documentation for these standards can streamline risk management files and accelerate regulatory review.

Future trends in CGM and wearable design

As wearable healthcare expands, designers are targeting a reduction in device size, longer lifetimes, multi-sensor integration, and cloud-connected analytics. Each evolution places an even greater emphasis on power efficiency and electrical safety.

Emerging technology trends include:

• The integration of multi-parameter sensors (glucose, lactate, temperature, and hydration)
• The use of energy-harvesting or inductive-charging technologies to extend operating life
• The implementation of advanced protection monitoring, such as built-in diagnostics for ESD or fuse status
• The development of biocompatible, flexible electronics to further improve patient comfort

Component suppliers that offer medically focused design support and validated protection portfolios will play a crucial role in accelerating these innovations.

CGMs exemplify the convergence of biomedical science and advanced electronics. To achieve reliable, always-on operation in a body-worn form factor, engineers must carefully manage power, protection, and sensing interactions at every design level.

By integrating TMR magnetic switches for contactless activation, NTC thermistors for safety and compensation, low-leakage ESD/TVS diodes for transient protection, and miniature medical-grade fuses for fault isolation, developers can meet the strict performance and safety requirements of modern medical devices.

The result is a new generation of CGMs that are smaller, more power-efficient, and more reliable, meeting the practical constraints of wearable system design while enabling accurate, continuous monitoring.

About the author

Marco Doms is a senior manager of business development new platforms at Littelfuse Inc. Doms studied electrical engineering and holds a Ph.D. in MEMS. He was the head of R&D at two other sensor companies before joining Littelfuse in 2022. Doms has a long history in position sensors (especially xMR) and managing R&D and Innovation teams—from chip to system level. At Littelfuse, he started as an innovation manager, led the EBU Advanced Development team, and introduced an Innovation/Idea Management process. In his current role, Doms is responsible for several platforms with entirely new products or product features that require additional internal and customer coordination.

Marco Doms is senior manager of business development for new platforms at Littelfuse Inc.

The post Designing low-power CGMs with TMR-based magnetic sensing appeared first on EDN.

While its vehicle battery resurrection skills are uncertain at best, this device also offers other useful abilities.

Two-plus years back, within my teardown of my PowerStation PSX3:

which I described at the time as being:

…(among other things) a portable recharger and jump-starter of vehicles’ cells. It’s also a portable tire inflater. And it’s an emergency light and USB power source, too…

I took advantage of the opportunity to also editorially “rip” into three newer solid-state and Li-ion battery-based versions of the same concept:

I tried three of these widgets, one claiming to deliver 1200 A of “peak” cranking juice:

Another spec’ing 1500 A:

And a third that promised to deliver 2000 A:

They all promptly went back to Amazon as full-refund returns. Now granted, if someone had left their interior dome light on too long and the battery was drained too low to successfully turn over the engine but still had some “life” one of these might suffice…And I’ll grant them one other thing: they’re certainly small and light.

But 2000 A of cranking current? Or even 1500 A? Mebbe for a fraction of a second, the time necessary to drain an intermediary capacitor, but not long enough to resurrect a significantly drained battery. Therefore, the quotes I put around the word “peak” earlier. Such products exemplify the well-worn saying, “mileage may vary”. Give me an old-school lead acid battery instead, any day!

Regarding my “They all promptly went back to Amazon as full-refund returns” comment, while that was my original intent, I didn’t end up fully actualizing it. The “1200 A” and “1500 A” variants indeed did get shipped back to the retailer. But, curiosity-motivated, I decided to keep the “2000 A” model, Spanarci’s ZETA2000, around if for no other reason than as a future teardown candidate.

Calling Cupertino…

That future is today. As usual, I’ll start with some outer box shots (sparing you the blank sides), as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

Although my skepticism about the device’s jump-starting potential is already obvious at this early point in the writeup, I was admittedly impressed by the aesthetics and overall packaging of the product. Dare I even say it was Apple-reminiscent?

The cleverly labeled “Never Say Never” envelope, reminiscent (at least to me) of SpaceX’s three autonomous spaceport drone ships (i.e., floating rocket booster landing pads), “Of Course I Still Love You”, “Just Read the Instructions” and “A Shortfall of Gravitas”, contains literature bits:

Gee, I wonder what’s inside this translucent plastic sleeve?

To stretch the suspense, I’ll temporarily set it aside and investigate the lower box level instead:

Within is the to-vehicle battery cable harness, conveniently accompanied by USB-A-to-USB-C and USB-C-to-USB-C cables useful both for recharging the device’s internal battery pack and for powering other connected devices. Hold that thought:

Here’s the male connector at the end of the cable harness…

Burlesque finale

And here’s what it plugs into…

at out dissection patient, finally unswathed for its reveal. Top first:

Here’s the front:

Underneath the rubberized flap labeled “INPUT OUTPUT” at the right end are, likely unsurprisingly, first a bidirectional USB-C PD 30-W connector used for both device charging and for charging/powering another tethered device, such as a smartphone. The other, USB-A in form factor, is unidirectional (output-only) for similar tethered device “juicing” purposes.

Onward. Left side:

Rear; under this flap, cryptically (ha!) labeled “JUMPER CABLE” is the battery-cable harness connector you saw earlier:

And what the heck is that on the right side? A multi-LED strip, creating a 300-lumen four-mode (50% and 100% brightness stable, and both SOS and strobe pattern) flashlight, that’s what it is!

Last but not least, here’s the bottom view:

accompanied by a zoom-in of the specs:

Before opening ‘er up, I’ll note a few other feature set nuances. Like the conventional (i.e., AC-powered) solid-state charger that I tore down earlier this month, it supports various safety features such as short-circuit and “reverse” protection:

That said, there’s also “FORCE” support for dead cells and daring users:

The teardown’s the thing…

And now, let’s dive inside. Zoom back out on that earlier bottom overview shot and you’ll discern eight round rubber pieces, one in each corner and two more both at top and bottom:

I bet you can guess what comes next:

Eureka! Screw heads (trust me, they’re there, deep inside the recessed dimness)!

And what comes after that, dear readers? You got it right:

Dare I draw another analogy to Apple craftsmanship? Seriously, I’m impressed with the neatness and overall robustness of the insides, too!

Here’s the inside of the case topside:

…wherein I’ll detail the insides of the thing

And the overview that’s likely of greater interest to all of you!

Dominating the landscape, aside from the display, that is:

is the largest IC on this side, at center (horizontally) and toward the bottom (vertically). It’s Holtek’s HT67F489 8-bit RISC microcontroller, unsurprisingly with an integrated LCD controller and also containing (among other things) 8 Kwords of flash memory (4 Kwords on the more modest HT67F488 sibling, which the datasheet informs me (PDF) has been discontinued, anyway), 256 bytes of RAM and 64 bytes of EEPROM (none on the HT67F488). Also note two mode-select switches at far right, which mate to rubberized front panel buttons.

Let’s get that PCB out, shall we? Three screws hold it in place:

Guess what comes next?

In addition to noticing the now-absent screws (and their previously visible heads) in the next photo, I’d also like to draw your attention to the smaller but still-square IC to the right of the aforementioned HT67F489. It’s Southchip Semiconductor Technology’s SC2001 USB-PD controller. Given what you already know about the capability of the USB-C connector on the front of the device, this chip’s presence and functions shouldn’t be a surprise.

Here goes nothing:

My, what a big power source you have…

At left is the 44.4 Wh lithium polymer battery pack:

To its right is a beefy Sanyi Seiko SEV8-P-112DM 4-pin high-power relay:

soldered to a mini-PCB:

And the remainder of the compartment mostly consists of a bunch of now-disconnected wire harnesses:

The destination of one of them was, I admit with no shortage of chagrin, initially identity-baffling to me, until I pulled it out. See that gold-colored half-oval to the far right?

Oh yeah. The LEDs. Duh on me:

Underneath that large green region on the PCB underside is, as far as I can feel, nothing notable save for mounting-bracket sites and solder points related to the LCD on the other side:

The PCB-mounted speaker in one corner delivers a loud “beep” tone if, for example, you’ve got your to-battery connections reversed:

The one next to it is “just” an inductor (L1 is peeking out from the PCB under the white glue):

It, along with the rest of the components surrounding it (and some of those on the other side), implements a largely unmemorable power management subsystem.

In closing, I’ll share a side view of the USB-C and USB-A connectors; since the PCB is upside-down from its normal operating orientation, so are they:

…the better to incinerate you with, my dear

With that, I’ll close for today. Speaking of closing, I’ll keep the device disassembled for a while post-publication of this teardown. Then I’ll carefully reassemble it in the hopes of resurrecting it. If you smell smoke, see flame, or hear a loud “boom”, you’ll know my efforts didn’t succeed.

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• NOCO’s Genius 1: A trickle charger that tries harder
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• Dead lead-acid batteries: Desulfation-resurrection opportunities?

The post Portable jump starters: A dubious primary use case, but not a total waste appeared first on EDN.

Gas discharge tubes (GDTs) harness the physics of controlled sparks to provide reliable surge protection, making them a fundamental safeguard for modern electronic circuits.

They are deceptively simple devices that rely on ionized gas to tame the chaos of voltage surges. When a transient spike threatens sensitive circuitry, a GDT responds with a controlled spark, safely channeling excess energy away from the system.

Compact, rugged, and reliable, these components have become indispensable in applications ranging from telecom lines to industrial equipment. In essence, GDTs turn sparks into protection, making them a cornerstone in the engineer’s surge-defense toolkit.

It’s worth noting that GDTs are sometimes referred to as plasma arrestors. The two names describe the same device; a sealed tube filled with inert gas that forms a plasma arc when voltage exceeds its breakdown threshold. “GDT” is the term most often used in engineering literature and standards, while “gas plasma arrestor” tends to appear in catalogs or marketing to highlight the plasma discharge mechanism.

Inside the spark: How GDTs work

From the first spark to the final safeguard, gas discharge tubes show how even the simplest devices can deliver powerful protection where it matters most. To understand why, let us take a closer look at how they work.

At the heart of a GDT is a sealed chamber filled with inert gas such as neon or argon. Two electrodes face each other across a small gap inside this chamber. Under normal operating conditions, the gas is non-conductive, and the tube behaves like an open circuit. But when a voltage surge pushes the potential across the electrodes beyond the breakdown threshold, the gas ionizes. This ionization triggers a plasma discharge—controlled spark—that suddenly makes the tube conductive.

The plasma arc provides a low-resistance path, diverting the surge current safely away from sensitive components. Once the surge subsides and the voltage drops below the sustaining level, the plasma extinguishes, and the tube returns to its insulating state. This simple cycle—breakdown, conduction, recovery—is what makes GDTs both rugged and reliable in protecting circuits against transient overvoltages.

Figure 1 A medium-duty 2-electrode gas discharge tube safeguards telecommunications, industrial, and consumer electronics from voltage surges. Source: Bourns

Shared sparks, shared protection

Building on the fundamentals, the next nuance lies in how protection is applied across conductors. A two-lead GDT serves as a straightforward single-path protector, perfect for shunting individual DC rails or coaxial cables to ground. But when you place two separate two-lead tubes across a data pair, they will never fire at precisely the same instant, leaving a harmful “transverse voltage” between the lines.

A three-lead GDT solves this by enclosing both conductors in a common gas chamber. The moment one side ionizes, the entire tube triggers, discharging both lines to ground simultaneously. This synchronized action delivers the balanced protection that sensitive telecommunications and differential data circuits demand.

Figure 2 A 3-lead GDT ensures simultaneous crowbar action across differential lines, preventing unbalanced residual voltages during a surge event. Source: Littelfuse

It’s important to note at this point that standard GDTs are commonly available in both 2- and 3-electrode configurations, whereas high-voltage variants are primarily limited to 2-electrode designs with select 3-electrode exceptions. While 2-electrode devices are typically deployed for either line-to-ground or line-to-line protection, a 3-electrode GDT provides the advantage of addressing both protection paths within a single component.

Practical implementation of GDTs

When selecting a GDT for a specific application, the primary objective is to ensure the device remains inactive during normal operation while reacting instantaneously to overvoltage transients. This requires careful evaluation of key electrical parameters, starting with the DC spark-over voltage. To prevent “nuisance” triggering, the GDT’s minimum breakdown rating should typically be 1.2 to 1.5 times the peak operating voltage of the system.

Furthermore, because GDTs are “crowbar” devices, engineers must account for follow-on current, the current that continues to flow through the ionized gas after the surge has passed. If the system’s power source can sustain this arc, additional current-limiting components or a coordinated circuit design may be necessary to ensure the GDT successfully resets to its high-impedance state once the transient is cleared.

However, follow-on current is often absent from GDT datasheets because it’s not a fixed constant of the device, but rather a system-dependent behavior. A GDT is essentially a triggered short circuit; once ionized, its resistance drops so low that the resulting current is determined almost entirely by your power supply’s voltage and internal impedance.

While manufacturers provide the arc voltage and the glow-to-arc transition current, they cannot predict your specific source’s capacity to sustain that arc. Consequently, engineers must use those parameters to calculate the “holdover” risk themselves, often necessitating components like metal oxide varistor (MOV) to effectively “starve” the arc and allow the GDT to reset.

To round out the technical profile, several other parameters define a GDT’s performance and longevity. Maximum impulse spark-over voltage is critical, as it indicates the highest voltage level the device allows during a fast-rising surge before it triggers. To gauge durability, engineers look at nominal impulse discharge current, which is the peak surge current the GDT can survive for a set number of pulses, and alternating discharge current, which measures its ability to handle sustained AC faults.

Additionally, maximum capacitance must be minimal to ensure signal integrity in high-frequency lines, while minimum insulation resistance ensures the GDT remains electrically “invisible” until a surge occurs.

Figure 3 Plot illustrates the GDT voltage breakdown characteristic. Source: Author

As a worthy take on paper, the GDT’s protective behavior is defined by its transition through distinct electrical phases, captured sequentially in Figure 3. The process initiates with the sparkover voltage, the exact point where the internal gas ionizes and becomes conductive. Immediately following this breakdown, the voltage falls to a relatively stable plateau known as the glow region, where current flows but remains limited.

As the surge energy intensifies, the device undergoes the rapid glow to arc transition, the critical threshold where the discharge collapses into a highly conductive plasma. This leads immediately to the arc voltage, the final “crowbar” state where the voltage drop plummets to its absolute lowest point. Identifying this transition sequence is vital, as the low arc voltage is precisely what triggers the risk of sustained follow-on current from the system’s power source.

GDTs are often evaluated against IEC 61000‑4‑5, the international surge immunity standard, because their protective behavior directly addresses the transient overvoltages defined by this test. The standard specifies surge waveforms—most notably the 1.2/50 µs voltage impulse and the 8/20 µs current impulse—to replicate lightning‑induced or switching transients. In these scenarios, GDTs act as frontline protectors, clamping and diverting surge energy away from sensitive equipment to ensure compliance and resilience.

Bonus insight: How to test a GDT surge arrestor

Have you ever wondered how to verify whether a GDT surge arrestor is still healthy and ready to protect against lightning, static, or electromagnetic pulse (EMP) events? An EMP is a sudden burst of electromagnetic energy—often from lightning strikes, solar storms, or even man-made sources—that can damage sensitive electronics. The only definitive way to confirm a GDT’s readiness is to make the device “fire”.

The most reliable approach is a DC high-voltage ramp test, performed with a power supply or a megohmmeter. Because a GDT behaves like an open circuit under normal conditions, you gradually increase the DC voltage across its terminals until it reaches the rated breakdown point. To ensure safety and prevent excessive current once the tube fires, a series resistor should always be included in the test circuit. This resistor limits the surge current, protects the power supply, and prevents overstressing the GDT during repeated tests.

Sparking applications, igniting ideas

Gas discharge tubes prove their worth across a wide spectrum of systems. In telecommunications, they safeguard MDF modules, xDSL equipment, RF systems, antennas, and base stations. In industrial and consumer electronics, they protect power supplies, surge protectors, alarm systems, and even irrigation systems.

Positioned in front of and in parallel with sensitive lines—power, communication, signal, and data transmission—GDTs shield equipment from transient surges caused by lightning strikes or switching operations. Under normal conditions they remain invisible to the signal, but when an overvoltage surge arrives, they switch to a low-impedance state and divert the energy safely away from the circuitry.

These sparks of protection are more than circuit defense; they are design opportunities. For makers and engineers, the challenge is to take this proven sequence from sparkover to arc and reimagine it in your own projects. Every surge control is a chance to build systems that are not only safer but smarter. So let the sparks inspire you: experiment boldly, refine relentlessly, and turn protective theory into resilient innovation.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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• Gas Discharge Tubes: Old Protection in a New Bottle–Literally

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Medical imaging has become one of the most critical pillars of modern healthcare to provide insights into diagnosis, treatment planning, and disease management. However, the very success of imaging modalities such as computed tomography (CT) and magnetic resonance imaging (MRI) has created a growing challenge of data and decision-making. As imaging generates more information to interpret, artificial intelligence helps to improve these systems by supporting faster, smarter workflows for higher-accuracy diagnoses.

The volume of imaging studies has increased substantially over the past decade, putting additional pressure on the shortage of radiologists. At the same time, technological advances in scanner hardware have enabled the acquisition of thinner slices and higher-resolution images, with a single CT or MRI exam consisting of hundreds or thousands of images.

In clinical settings, the challenge is not whether scans have sufficient data but whether the health system can reconstruct, review, quantify, and interpret the data fast enough to support timely clinical decisions. We look at the use of AI and some of the popular deep-learning models in medical imaging and diagnostics while also examining how AI is being integrated across the imaging workflow.

AI enhances medical imaging systems such as CT or MRI scanners by supporting faster, smarter workflows for higher-accuracy diagnoses. (Source: Adobe Stock) AI across the medical imaging pipeline

AI is moving medical imaging and diagnostics from early-generation concepts and narrow automation toward broader integration across the imaging pipeline. The integration of AI is augmenting a wide range of tasks, from the moment an exam is ordered to the final clinical interpretation, to improve speed, accuracy, consistency, and efficiency. This approach addresses the critical bottleneck in the modern imaging workflow, turning a linear and often manual process into a more optimized, data-driven, and intelligent system.

The influence of AI begins even before a single image is acquired. This includes administrative and logistical steps that are important for optimization. For example, natural-language-processing models can analyze a patient’s clinical history and the reason for an exam within the electronic health record to help automate the selection of the most appropriate imaging protocol.

During the acquisition stage, AI contributes to image quality and efficiency. In CT, AI can automate and optimize scan ranges and radiation dose parameters based on the patient’s specific anatomy to ensure diagnostic-quality images are obtained at the lowest possible radiation exposure.

Image reconstruction is another impactful application of AI. Deep-learning reconstruction has changed this process. These models are trained on a large dataset of high-quality images to produce images with significantly lower noise and higher signal-to-noise ratio from under-sampled or low-dose raw data. For MRI, this means scan times can be reduced by up to 75% in some cases, without sacrificing image quality.

Once the images are created, AI is used for analysis and interpretation. In this phase, it helps radiologists in extracting clinically relevant information. Automated segmentation is the key task in which AI algorithms delineate anatomical structures, organs, or pathologies with high precision. This is an important prerequisite for quantitative analysis and is used to accelerate standardized assessment workflows, such as for the prostate imaging reporting and data system.

After the segmentation, AI tools for detection and triage can screen images for critical findings, such as intracranial hemorrhage, pulmonary embolism, or large vessel occlusions in stroke patients. However, AI in this setting is changing the order, speed, and consistency of review. A triage algorithm can bring a suspected emergency case to the top of the queue, while the radiologist remains responsible for confirming the findings, considering clinical context, and issuing the final report.

AI models in modern imaging diagnostics

The growth in powerful deep-learning architectures today serves as the engine for modern medical AI to perform complex tasks such as detecting minute pathological changes, precisely segmenting anatomical structures, and fusing information from different clinical sources.

Convolutional neural networks (CNNs) have become the go-to architecture for most AI medical imaging applications, especially in radiology. Their design is inspired by the human visual cortex and is well-suited for processing grid-patterned data such as images.

While CNNs are useful for classification tasks, medical imaging requires a more granular understanding of spatial information, such as tracing the boundaries of an organ or tumor. This task involves assigning a class label to every pixel in an image. For this purpose, encoder-decoder architectures, most popularly the U-Net, have become the de facto standard.

The U-Net design addresses this challenge by combining semantic context with low-level, high-resolution spatial information. The architecture has two main components: the encoder and the decoder. As the image data goes deeper into the encoder, the spatial resolution decreases, but the number of feature channels increases. This allows the architecture to capture context-rich information from the image.

The decoder’s role is to take the compressed, high-level feature representation from the encoder and progressively up-sample it back to the original image resolution to generate a pixel-wise segmentation map. It achieves this by using a learned transposed convolution to increase spatial dimensions.

The U-Net architecture uses skip connections that create a pathway for information to flow from the encoder to the decoder at corresponding levels of resolution. This fusion provides the decoder with the fine-grained spatial details that were lost during the down-sampling.

This is necessary in many diagnostic cases that are not a simple classification problem. The model not only needs to identify that a tumor, lesion, or abnormality is present, but it also outlines the boundary, calculates volume, compares change over time, or separates healthy tissue from pathology. This pixel-level requirement is why encoder-decoder architectures have become key to segmentation workflows.

The success of this concept has led to variants designed to further improve performance. U-Net++, for example, introduces nested and dense skip pathways to reduce the semantic gap between the encoder and the decoder feature maps, while Attention U-Net integrates attention mechanisms that allow the model to focus on the most relevant image regions. Other advanced versions, such as nnU-Net, provide a self-configuring framework that automatically adapts the network architecture and preprocessing steps for any given segmentation task.

However, CNNs have limitations in modeling long-range dependencies and global context within an image. This led to the exploration of Vision Transformers in medical imaging. Transformers can model relationships across wider image regions, which is useful for tasks in which pathology, anatomy, and clinical context are distributed across a larger field of view.

But at the same time, they face a domain gap between the natural images on which many of these models are pretrained and the unique characteristics of medical images. The black-box nature of these models raises concerns about interpretability, which is important for clinical trust and high-stakes decision-making.

How AI improves medical insights

Integrating AI into medical imaging brings enormous improvements in speed and operational efficiency. By automating time-consuming tasks at multiple stages, AI targets the workload pressures and delays that modern radiology faces. This results in faster diagnoses and more timely patient intervention.

AI is also increasing the accuracy of the diagnostic quality of medical imaging by reducing variability. Human interpretation is always subject to limitations because of fatigue, perceptual errors, and inter-reader variability, whereby different radiologists may interpret the same image differently. AI provides a more powerful set of tools to augment human perception.

AI systems are particularly strong in pattern-recognition tasks and have demonstrated the ability to detect subtle abnormalities that may be missed by the human eye. In lung cancer screening with CT, for example, studies have shown that AI algorithms can achieve a nodule-detection sensitivity exceeding 95% for nodules of 4 mm or larger.

In lung cancer screening with CT scans, AI algorithms can improve nodule-detection sensitivity and reduce the risk of a missed diagnosis. (Source: Adobe Stock)

A research study shows that AI detected 8.4% more lung nodules in patients with complex lung diseases. Similarly, in mammography, AI models have performed comparably to human experts in detecting breast cancer in certain validation studies. These systems function as a highly effective second reader that can help radiologists focus on potential concerns and reduce the risk of a missed diagnosis.

In addition, radiomics is built upon the foundation of AI-driven quantification. For example, radiomic features extracted from pre-treatment CT images have been used to predict survival in lung cancer patients, while signatures from MRI scans have shown a correlation with recurrence risk in glioblastoma patients.

What’s next

The current advancements are setting the stage for a future in which AI will be deeply integrated into diagnostics and patient care. One of the most important future directions is the maturation of multimodal AI and foundation models for a wider range of data types, including imaging, genomics, proteomics, digital pathology, clinical notes, and even real-time physiological data from wearable sensors.

The future of AI is likely to be one of human-AI collaboration. AI will handle the data-intensive tasks of detection, measurement, and quantification, while radiologists focus on higher-order tasks of complex synthesis and clinical correlation.

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