EDN Network

RA0 microcontrollers from Renesas are low-cost devices that offer low power consumption and a feature set optimized for cost-sensitive applications. The MCUs can be used in such applications as consumer electronics, system control for small appliances, building automation, and industrial control systems.

Based on an Arm Cortex-M23 core, the 32-bit MCUs consume 84.3 µA/MHz in active mode, dropping to just 0.82 mA in sleep mode. A software standby mode cuts current consumption even further, allowing the device to sip just 0.2 µA. These features, coupled with a high-speed on-chip oscillator for fast wakeup, make the MCUs particularly well-suited for battery-operated products.

The first devices in the RA0 series, the RA0E1 group, operate from a supply voltage of 1.6 V to 5.5 V. This means there is no need for a level shifter/regulator in 5-V systems. An on-chip oscillator improves baud rate accuracy and maintains ±1.0% precision over a temperature range of -40°C to +105°C.

Other features of the RA0E1 group of MCUs include: 

• Memory: Up to 64 kbytes of code flash and 12 kbytes of SRAM
• Analog Peripherals: 12-bit ADC, temperature sensor, internal reference voltage
• Communications Peripherals: 3 UARTs, 1 Async UART, 3 Simplified SPIs, 1 IIC, 3 Simplified IICs
• Safety: SRAM parity check, invalid memory access detection, frequency detection, A/D test, immutable storage, CRC calculator, register write protection
• Security: Unique ID, TRNG, flash read protection

RA0E1 microcontrollers are shipping now. Package options include 20-pin LSSOP, 32-pin LQFP, and QFN with 16, 24, or 32 leads.

RA0E1 product page

Renesas Electronics 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Renesas expands general-purpose MCU choices appeared first on EDN.

The first entry in Teledyne’s 650-V power module family, the TDGM650LS60 integrates a 650-V, 60-A GaN transistor and isolated driver in a single package. The module, which is now available off-the-shelf, acts as a load switch or solid-state switch. Fast switching time and the absence of moving parts make the TDGM650LS60 useful for high-reliability applications in the space, avionics, and military sectors.

The TDGM650LS60 tolerates up to 100 krads of total ionizing does (TID) radiation and operates over a temperature range of -55°C to +125°C. It’s enhancement-mode GaN transistor has a minimum breakdown voltage of 650 V and a stable on-resistance of 25 mΩ. Coupled with the driver’s 5-kV isolation, the TDGM650LS60 ensures robust and reliable operation in challenging environments.

Occupying a 21.5×21.5-mm footprint, the TDGM650LS60 module has solder-down castellation for surface-mount style mounting. A preliminary datasheet can be accessed by using the link to the product page below.

TDGM650LS60 product page

Teledyne e2v HiRel Electronics    

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Hi-rel GaN load switch ships off-the-shelf appeared first on EDN.

A Bluetooth LE 5.4 module, the HCM511S from Quectel, leverages the power of an Arm Cortex-M33 core, along with 352 or 512 kbytes of flash memory. The module, which also provides 32 kbytes of RAM, brings efficient performance to compact connected devices such as digital keys, portable medical devices, and battery-operated motion sensors.

According to Quectel, the Bluetooth module’s transmit power of +6 dBm achieves long-distance transmission, allowing low-power devices to connect cost effectively. Optional support for Bluetooth mesh nodes increases network scalability and allows greater device density over a mesh topology. The HCM511S also offers up to 18 GPIOs, which can be multiplexed for various interfaces, including ADC, USART, I2C, I2S, PDM, SPI, and PWM.

The MCU Bluetooth module comes in a 16.6×11.2×2.1-mm LCC package and weighs just 0.57 g. It operates over a temperature range of -40°C to +85°C. In addition to being certified by the Bluetooth Special Interest Group, the HCM511S is also certified for use in Europe, America, Canada, China, Australia, and New Zealand.

Engineering samples of the HCM511S MCU Bluetooth module are available now.

HCM511S product page

Quectel Wireless Solutions  

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Bluetooth module taps Cortex-M33 processor appeared first on EDN.

Enabling high compute performance at the edge, the Titanium Ti375 FPGA from Efinix packs a quad-core hardened RISC-V block and 370,000 logic elements. It employs the company’s high-density, low-power Quantum compute fabric wrapped with an I/O interface.

The 32-bit hardened RISC-V block (RISCV321 with M, A, C, F, and D extensions and six pipeline stages) offers a Linux-capable MMU, FPU, and custom instruction capability. Paired with an Efinix Sapphire SoC, the Ti375 FPGA helps designers turn a tiny chip into an accelerated embedded compute system.

The Ti375 is manufactured on a 16-nm process and comes in a fine-pitch BGA package with a choice of 529, 676, 900, or 1156 balls. Its full-duplex serializer/deserializer transceiver operates at data rates from 1.25 Gbps to 16 Gbps and supports multiple protocols, including PCIe 4.0, Ethernet SGMII, and Ethernet 10GBase-KR. The FPGA also features a LPDDR4 DRAM controller and MIPI D-PHY.

Samples of the Titanium Ti375 FPGA are shipping now to early access customers.

Ti375 product page

Efinix

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post FPGA integrates hard RISC-V cores appeared first on EDN.

It’s common for I2C systems to have both standard and fast devices on the same bus.

For I2C systems, the speed and power consumption both depend on the values of pullup resistors: the values of them should be low enough to secure the fast charge of the bus capacitance.

Wow the engineering world with your unique design: Design Ideas Submission Guide

But the low values increase power consumption, the low values can also present too heavy a load for the transmitter.

The variable topology of the bus can make the situation somewhat more complicated.

Hence when your system is power-restricted and you need to use several I2C chips at different I2C modes, you have to compromise between these chips. Or you can use the adaptable pullup, which is shown in Figure 1.

Figure 1: The adaptable pullup where a closed transistor connects additional resistors R5 and R6 in parallel to the main pullup resistors R1 and R2

The circuit is rather simple: a closed transistor connects additional resistors R5 and R6 in parallel to the main pullup resistors R1 and R2. 

The connection can be controlled by GPIO for example, as shown in Figure1, and should be done before the fast data exchange takes place.

Another solution is shown in Figure 2, which represents one-half of the whole circuit (the second half for SDA is omitted for brevity). The circuit uses an analog switch (for instance, TS5A3159 of TI) to disconnect the “fast” part of the bus. While it’s disconnected, the resistor R5 provides a high (idle) voltage level on the bus. Note that the capacitance of the switch, which can be large enough (20 to 100pF), should be taken into account.

Figure 2: Alternative adaptable pullup solution that uses an analog switch to disconnect the “fast” part of the bus.

—Peter Demchenko studied math at the University of Vilnius and has worked in software development.

Related Content

• Active pullup/pulldown network saves watts
• Pull-up Resistors
• A self-testing GPIO
• Logic Probe has a wide voltage range

The post Adaptable pullup appeared first on EDN.

Wide bandgap semiconductors have taken both power electronics and high frequency circuits by storm, replacing so many applications that were previously dominated by silicon-based devices, e.g., LDMOS HPAs in base stations, IGBTs in high voltage DC/DC conversion etc. Specifically within power electronics, it is no secret that certain applications are demanding power dense solutions that operate at high switching frequencies to minimize switching losses. From traction inverters, onboard chargers, and high voltage DC-DC converters in EVs to uninterruptible power supplies (UPSs) and solar power converters in industrial/commercial applications; WBG semiconductors have carved out an extensive niche for many next generation electronics. 

The SiC substrate has established itself for EV and some industrial applications. However, a bit more recently GaN has surfaced as a strong option for many overlapping applications. Understanding the major differences between these substrates in the context of high power circuits and their respective manufacturing considerations might shed light on the future of these two popular compound semiconductors. 

WBG materials are inherently able to operate at higher switching frequencies and with higher electric fields than the conventional Si substrate. When a semiconductor is heated up, its resistance tends to go down due to thermally excited carriers that are more abundant at higher temperatures, causing conduction. Higher bandgap semiconductors will require higher temperatures (more energy) to excite electrons across the bandgap from the valence band to the conduction band. This translates directly to more power handling capabilities and higher device efficiencies. 

This can be seen in Table 1 where SiC and GaN exhibit much higher breakdown electric field, electron mobility, saturation velocity, and thermal conductivity than Si—all factors that enhance switching frequency and power density. However, high switching frequencies will lead to more losses and a lower efficiency FET, this is where optimizing the power device figure of merit (FoM) [Rds(on) x Qg], or optimizing the channel resistance and gate charge for lower conduction and switching losses, is critical.  

Table 1 Properties of Si, SiC, and GaN.

Generally, GaN FETs max out at around 650-V with power applications around 10 kW while 750-V and 1200-V SiC FETs are not unusual and applications can range from 1 kW up to the megawatts (Figure 1). SiC’s excellent thermal conductivity allows for similar power ratings in significantly smaller packages. However, GaN devices are able to switch faster (note the significantly higher electron mobility) which, in turn, can translate to a higher dV/dt, potentially allowing for more converter efficiency. 

Figure 1: Power versus frequency plot for various power devices. Source: Texas Instruments

SiC, the recent golden child of power electronics, gained massive traction after Tesla’s announcement using exclusively SiC in the Model 3 back in March of last year. Since SiC MOSFETs were commercialized by Cree in 2010, the demand for SiC has steadily ramped up with key players taking advantage of available tax credits from the CHIPS act to grow operations and drive down the cost per wafer. Wolfspeed (formerly Cree), for instance, recently invested a total of $5 billion in a new production facility, the John Palmour (JP) manufacturing center to develop 200 mm (~8-inch) wafers. 

However, it isn’t that simple: getting a foothold in SiC fabrication requires expensive equipment that is exclusively used for SiC. SiC boules are grown  at  temperatures in excess of 2700℃ at a rate at least 200 times slower than Si, which requires a large amount of energy. GaN on the other hand can largely use the same equipment as Si semiconductor processing where GaN epitaxial wafers can be grown on its respective substrate (often Si, SiC, or sapphire) at a temperature of 1000 to 1200℃—less than half that of SiC. SiC wafers are also nearly 50% thinner than Si wafers (up to 500 μm), leading to a fairly brittle material that is prone to cracking and chipping—another quality that requires specialized processing equipment. 

According to Gregg Lowe, CEO at Wolfspeed, 6-inch SiC wafers cost ~$3,000 in 2018, a cost that has been trimmed down to ~$850 for a 7-inch wafer just 6 years later in 2024. And, as SiC power devices continue to mature, costs per wafer will continue to go down. A major leap in optimizing costs are growing wafer sizes and increasing the number of devices per wafer. For GaN-on-Si, this is relatively simple, larger diameter fabs can produce thousands of 8-inch wafers per week with excellent line yields (98%) afforded by CMOS process control. However, similar economies of scale can be applied to SiC wafer production as companies now advance toward 8-inch wafers where just ten years ago, mass production of 150 mm (~6-inch) wafers were really just on the horizon. And, while the SiC devices themselves may be more expensive than Si and GaN counterparts, the fact is, far less power devices are required to maintain the same performance. On the system level, this means less gate drivers, magnetics, and other peripherals devices that might otherwise be used in an Si-based design. 

Because of its excellent high frequency characteristics, GaN has already established itself as a suitable III-V semiconductor for high frequency circuits such as MMICs, hybrid microwave circuits, etc., along with other compound semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP). GaN is particularly relevant for high power amplifiers (HPAs) in the transmit signal chain. Many of the GaN foundry services currently available generally address high frequency applications with GaN-on-SiC however, more recently, foundries are shifting their focus towards GaN-on-Si for both RF and power applications. Table 2 highlights some of the GaN process technologies for different companies globally. Note the table does not include all GaN foundries such as Global Foundries or UMC which will likely be major contenders in Gan-on-Si technologies.

Table 2: Select GaN foundries and specifications on their technology.  

SiC and GaN serve very distinct parts of the power spectrum, however, can higher voltage GaN devices be designed to creep up the spectrum and contend with SiC? The GaN pHEMTs that dominate GaN fabrication have breakdown voltages (~0.6 to 1.5 MV/cm) that generally cap out at around 650 V due to the inherent limits of its critical breakdown field [1-2]. Methods of reaching the intrinsic limits of 3 MV/cm are being explored in research in order to improve the breakdown characteristics of GaN devices. 

More and more manufacturers are showcasing their 700-V GaN solutions. There have been talks of a 1200 V GaN FET; Transphorm released a virtual design of their 1200 V GaN-on-Sapphire FET in May of last year. Outside of this much of the talk of GaN moving up the power spectrum has remained in the R&D space. 1200-V Vertical GaN (GaN-on-GaN) transistors are also being researched by NexGen Power Systems with their Fin-JFET technology [3], a success that has allowed the company to receive funding from the US department of energy (DOE) to develop GaN-based electric drive systems. However, many of these solutions are not GaN-on-Si.

GaN-on-Si simply might have the major advantage of bandwagoning on the silicon semiconductor industry’s already established technology maturity, however, using the Si substrate comes with some design challenges. There are two major constraints: a large lattice mismatch and an even larger thermal mismatch between the GaN epitaxial layer and the host substrate causing tensile and compressive strains on the two substrates resulting in dislocations and higher defect densities (Table 3). Other substrates are being researched to overcome this issue, Qromis, for instance, has recently engineered a ceramic poly-aluminum nitride (AlN) layer that is CMOS fab compatible and CTE-matched to GaN. 

Table 3  Lattice and thermal mismatch between GaN and Si, sapphire, and SiC. Source: [4] 

While GaN wafers are generally more convenient to manufacture, they do require a precious metal that is, by nature, in limited supply. There was strain on the gallium supply with the 2019 tariffs on Chinese imports ratcheted up significantly causing a 300% increase in gallium metal imported from China compared to 2018 where the surplus was likely stockpiled. China’s restrictions on gallium exports in August of last year further diminished the already small amount imported from China. The bans could have potentially signaled a problem as China produces nearly 98% of the world’s low-purity gallium. 

However, the issue has not truly disrupted gallium-based wafer production (GaAs or GaN), largely due to the stockpiling and shifting to other sources for the rare metal (Table 4). Many countries now have the incentive to scale up the operations that, over a decade ago, were shut down due to China’s overproduction. Still, this may be something to consider if China further restricts its exports in the short term. It may also be important to note that since GaN wafers are produced by growing GaN crystals on top of a variety of substrates, relatively small amounts of gallium are used per device as compared to GaAs pHEMTs that are grown on semi-insulating GaAs wafers. So, while this may have been something to consider given the recent history of restricted gallium supplies, it has not really impacted GaN production and likely won’t in the future.

Table 4: US imports of unrefined gallium by country or locality according to USGS [5].

As it stands SiC and GaN dominate distinct parts of the power spectrum and therefore distinct applications with only some overlap. However, if GaN FETs can successfully increase in drain-source voltage without stifling its current massive manufacturing advantage, it may very well break out of its current place largely in consumer electronics (e.g., USB chargers, AC adapters, etc.) into higher power applications that SiC power devices currently dominate. SiC manufacturing has not stagnated though, and steady progress is being made in wafer size and yield to drive down the cost of SiC. 

Aalyia Shaukat, associate editor at EDN, has worked in the design publishing industry for seven years. She holds a Bachelor’s degree in electrical engineering, and has published works in major EE journals.

Related Content

• Silicon carbide (SiC) counterviews at APEC 2024
• APEC 2023: SiC moving into mainstream, cost major barrier
• GaN Power Devices: Challenges and Improvements
• Selecting GaN or SiC devices with a Focus on Reliability

References

1. Tian Z, Ji X, Yang D, Liu P. Research Progress in Breakdown Enhancement for GaN-Based High-Electron-Mobility Transistors. Electronics. 2023; 12(21):4435. https://doi.org/10.3390/electronics12214435
2. Exploring an Approach toward the Intrinsic Limits of GaN Electronics. Sheng Jiang, Yuefei Cai, Peng Feng, Shuoheng Shen, Xuanming Zhao, Peter Fletcher, Volkan Esendag, Kean-Boon Lee, and Tao Wang. ACS Applied Materials & Interfaces 2020 12 (11), 12949-12954. DOI: 10.1021/acsami.9b19697
3. R. Zhang et al., “Vertical GaN Fin JFET: A Power Device with Short Circuit Robustness at Avalanche Breakdown Voltage,” 2022 IEEE International Reliability Physics Symposium (IRPS), Dallas, TX, USA, 2022, pp. 1-8, doi: 10.1109/IRPS48227.2022.9764569.
4. Kaminski, Nando, and Oliver Hilt. “SiC and GaN Devices – Wide Bandgap Is Not All the Same.” IET Circuits, Devices & Systems, vol. 8, no. 3, 2014, pp. 227-236. https://doi.org/10.1049/iet-cds.2013.0223. 
5. “Gallium Statistics and Information.” U.S. Geological Survey, [last modified August 29, 2023], usgs.gov/centers/national-minerals-information-center/gallium-statistics-and-information.  [accessed on  2023-10-26].

The post GaN vs SiC: A look at two popular WBG semiconductors in power appeared first on EDN.

The news about Samsung snapping an advanced packaging order for Nvidia’s AI chips paired with high-bandwidth memory (HBM) chips underscores the strategic importance of next-generation packaging solutions. According to a report published in South Korean media outlet The Elec, Samsung’s advanced packaging team will provide interposer and 2.5D packaging technology for Nvidia’s AI processors.

It’s important to note that the GPU and HBM building blocks in these AI processors are supplied by other companies—most likely Nvidia’s GPUs manufactured on a TSMC process node and HBM chips designed and produced by Samsung’s archrival SK hynix.

What’s more important is how industry watchers relate this development to the insufficient capacity of TSMC’s chip-on-wafer-on-substrate (CoWoS) technology, which stacks chips and packages them onto a substrate. However, this supply shortage connected with the recent earthquake in Taiwan doesn’t hold much weight, and it’s most likely related to supply and demand issues.

Samsung calls its 2.5D packaging technology iCube; it places one or more logic dies such as CPUs and GPUs and several HBM dies on top of a silicon interposer, making multiple dies operate as a single chip in one package. It deploys parallel and horizontal chip placement to boost performance and combat heat buildup.

Figure 1 The iCube technology offers warpage control even with large interposers, and its ultra-low signal loss is paired with high memory density. Source: Samsung

Samsung’s advanced packaging pivot

Trade media has been abuzz with reports about Samsung beefing up its advanced packaging division by hiring more engineers and developing its own interposer technology. The company reportedly procured a large amount of 2.5D packaging equipment from Japanese semiconductor equipment supplier Shinkawa.

Another report published in The Elec claims that Applied Materials and Besi Semiconductor are installing hybrid bonding equipment at Samsung’s Cheonan Campus. Hybrid bonding enhances I/O and wiring lengths compared to existing bonding methods. TSMC offers hybrid bonding in its 3D packaging services called System on Integrated Chip (SoIC). Intel has also implemented hybrid bonding technology in its 3D packaging technology called Foveros Direct.

Media reports suggest that Samsung has recently ramped up the production capacity at its key site for advanced production in Cheonan to full utilization preceding Nvidia’s advanced packaging orders. Industry observers also expect that this advanced packaging deal with Nvidia could pave the way for Samsung to win the supply of HBM chips for pairing with GPU’s maker’s AI devices.

SK hynix is currently the major supplier of HBM chips for Nvidia’s AI processors, and Samsung is frantically working to close the gap. In fact, when Samsung established the advanced packaging business team in December 2023, the company’s co-CEO Kye-Hyun Kyung hinted about seeing the results of this investment in the second half of 2024.

Advanced packaging in Samsung’s roadmap

Kyung also pinned his hopes on a competitive advantage with Samsung’s memory chips, chip fabrication, and chip design businesses under one roof. Advanced packaging stands out in this semiconductor technology portfolio due to its intrinsic link to large and powerful AI chips and system-in-package (SiP) devices.

Figure 2 Next-generation packaging technologies are in the limelight due to the massive demand for AI chips. Source: Samsung

Like TSMC and Intel Foundry, Samsung is aggressively investing in advanced packaging technologies like silicon interposers while also steadily expanding its production capacity. Interesting times are ahead for next-generation packaging solutions.

Related Content

• Is 3D IC The Next Big Profit Driver?
• Heterogeneous Integration and the Evolution of IC Packaging
• Understanding the Big Spend on Advanced Packaging Facilities
• Tighter integration between process technologies and packaging
• Advanced IC Packaging: Fundamentals for the ‘More than Moore’ Era

The post Samsung’s advanced packaging pivot with Nvidia production win appeared first on EDN.

Despite massive, large-scale integration being ubiquitous in contemporary electronic design, discrete MOSFETs in the classic CMOS totem pole topology are still sometimes indispensable. This makes tips and tricks for driving them efficiently with logic level signals likewise useful, because it can be a “bit” tricky, especially if other than standard logic voltage levels are involved. 

If (happily) they are not, we have Figure 1.

Figure 1 The simplest case of logic signal totem pole drive—direct connection works if V++ <= VL.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In the lucky circumstance that the totem FET source pins are connected to positive and negative rails that match the logic levels, a simple direct connection (a wire) will suffice. All that’s needed for success then is that:

1. The FET ON/OFF gate-source voltage level lies within the logic signal excursion, and
2. The logic signal source has sufficient drive to cope with the paralleled FET input capacitances.

Item 2 is particularly important, because it affects the archenemy of totem pole efficiency, cross-conduction. 

It often happens that, during the transition between Q1-conducting and Q2-not to the opposite state, there will be an interval of overlap when both transistors conduct. This is “cross-conduction”, and it wastes power, sometimes a lot. The longer its duration, the greater the waste. The duration of cross-conduction depends on the time required for the logic signal to complete the 0/1 or 1/0 transition, which depends on how long it takes to charge and discharge the respective gate input capacitances. The cross-conduction gremlin is somewhat mitigated by the fact the capacitance that delays one FET’s turn-off also delays its complementary partner’s turn-on, but speed is still vital.

Now suppose Q1’s V++ source voltage is higher than VL. What now? Figure 2 shows a simple solution: AC coupling.

Figure 2 AC coupling can solve the problem of positive rail voltage mismatch if the control signal runs continuously.

Of course, this simple fix will only work if the logic signal can be relied upon to always have an AC component. That is to say, if only its duty cycle is never 0% (always OFF) nor 100% (always ON): 0% < DC < 100%. C1 should have at least an order of magnitude greater capacitance than Q1’s gate capacitance (e.g., 1 nF). While D1 can usually be an ordinary junction diode (e.g., 1N4148), a Schottky type can be a better choice if a few extra hundreds of mV of gate drive are needed.

AC coupling can also come to the rescue if the totem’s negative rail is below ground, as shown in Figure 3. The same DC limitation applying, of course.

Figure 3 Ditto for AC coupling and negative rail mismatch, too.

So, what to do if DC doesn’t obey the rules, and we can’t rely on a simple diode to define signal levels? See Figure 4.

Figure 4 “Grounded” gate Q3 maintains C1 charge when logic signal stops.

Small-signal transistor Q3’s configuration as a common-gate, non-inverting high-speed amplifier transfers necessary steady-state current to Q1. Choose R2 to be a low enough resistance to source Q2’s maximum expected source-to-gate leakage current (R2 = 10k will typically be a very conservative choice), then R1 = R2(V++/VL – 1).

And of course, as illustrated in Figure 5, the same trick works for a negative totem rail.

Figure 5 Grounded gate Q4 shifts logic signal to negative rail referred C2 and Q2.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Power Tips #108: Current sensing considerations in a bridgeless totem pole PFC
• A comparison of interleaved boost and totem-pole PFC topologies
• Power Tips #115: How GaN switch integration enables low THD and high efficiency in PFC
• The NE555 current spike

The post Driving CMOS totem poles with logic signals, AC coupling, and grounded gates appeared first on EDN.

A few months back, LA Computer Company (whose website is still up as I write these words, although it may no longer be when you read them), a retailer from whom I’d purchased a number of products over the years, announced that it was closing up shop and “fire sale-ing” its remaining inventory. I subsequently purchased several items from the company, one of which was a “Refurbished 4-Bay Portable Tower Enclosure 12TB (4x3TB)” further described as a “Refurbished 4 bay Thunderbolt 2 enclosure with 4 x 3TB hard drives installed.” The product photo (no longer available, alas) was generic, but the price was compelling, so I took a chance.

What arrived was a cosmetically imperfect but still functional AKiTiO Thunder2 Quad enclosure:

This last stock photo is particularly apropos, as the initial computer I intend to tether the enclosure (and HDDs inside) to is my own “trash can” Mac Pro:

And after the Mac Pro exits Apple’s supported-products stable, I’ll still be able to use the AKiTiO external storage device with newer Macs (along with Thunderbird-supportive Windows systems) in conjunction with an Apple adapter:

What of those HDDs inside the enclosure? They’re 7,200 RPM Seagate ST3000DM001 3.5” drives (here’s a PDF spec sheet for the entire Barracuda product family generation, code-named “Grenada”), with 6 Gbps SATA interfaces and 64 Mbyte RAM caches onboard. This particular variant integrated three 1 TByte platters, each with two associated read/write heads (one on either side), and also came in fewer-platter and lower-capacity versions.

I was initially surprised when Google search results on the product code revealed a Wikipedia page dedicated to the ST3000DM001, but all became clear when I started reading it. Suffice it to say that going with the “industry’s first 1TB-per-disk hard drive technology” more than a decade ago may have incurred at least some long-term usage risk for Seagate and its customers, in contrast the product family’s generally positive initial review results. Specifically, Backblaze, a well-known cloud storage company who uses lots of mass storage devices (both rotating and solid-state) and regularly publishes data on various drives’ reliability, found the ST3000DM001 exhibiting atypically high failure rates. Quoting from the company’s April 2015 report:

Beginning in January 2012, Backblaze deployed 4,829 Seagate 3TB hard drives, model ST3000DM001, into Backblaze Storage Pods. In our experience, 80% of the hard drives we deploy will function at least four years. As of March 31, 2015, just 10% of the Seagate 3TB drives deployed in 2012 are still in service.

Root cause? Here’s one working theory, according to German data recovery company Datenrettung (who was specifically discussing the drives’ usage in Apple’s 5th-gen Time Capsule):

The parking ramp of this hard drive consists of two different materials. Sooner or later, the parking ramp will break on this hard drive model, installed in a rather poorly ventilated Time Capsule. The damage to the parking ramp then causes the write/read unit to be destroyed and severely deformed the next time the read/write unit is parked. When the Time Capsule is now turned on again or wakes up from hibernation, the data disks of the Seagate hard drive are destroyed because the deformed read-write unit drags onto it.

Is Datenrettung right? Maybe. Some of my skepticism comes from the brutally honest “rather poorly ventilated Time Capsule” observation in the company’s comments. Apple has long been all about sleek, svelte, quiet, and otherwise boundary-pushing system design, and this isn’t the first time that a propensity for overheating has been the end result. Take my G4 Cube, for example. Or my first-generation MacBook Air. Or, more germane to this particular conversation, my own 3rd-gen Time Capsule, which also exhibited overheating-induced functional compromise but used an older, lower-capacity drive from an unknown manufacturer.

My skepticism further increased when I came across an excellent dissection at Tom’s Hardware:

By its own admission, Backblaze employed consumer-class drives in a high-volume enterprise-class environment that far exceeded the warranty conditions of the HDDs. Backblaze installed consumer drives into a number of revisions of its own internally developed chassis, many of which utilized a rubber band to “reduce the vibration” of a vertically mounted HDD.

 The first revision of the pods had no fasteners for securing the drive into the chassis. As shown, a heavy HDD is mounted vertically on top of a thin multiplexer PCB. The SATA connectors are bearing the full weight of the drive, and factoring the vibration of a normal HDD into the non-supported equation creates the almost perfect recipe for device failure.

 Backblaze has confirmed it still has all revisions of its chassis installed in its datacenters and that it replaced failed drives into the same chassis the original drive failed in. This could create a scenario where replacement drives are repeatedly installed into defective chassis, thus magnifying the failure ratio.

 Backblaze developed several revisions of the custom chassis due to its admitted vibration problems with the early models, and the company shared the designs with the public. However, Backblaze did not indicate which type of enclosures each drive failed within, leaving speculation that the chassis may be the real root of the problem (among others).

The bolded emphasis in this last paragraph is mine:

The Backblaze environment employed more drives per chassis and featured much heavier workloads (both of which accelerate failure rates tremendously) than the vendors designed the client-class HDDs for. This ultimately helped Backblaze save money on their infrastructure. The Seagate 3 TB models failed at a higher rate than other drives during the Backblaze deployment, but in fairness, the Seagate drives were the only models that did not feature RV (Rotational Vibration) sensors that counteract excessive vibration in heavy usage models — specifically because Seagate did not design the drives for that use case.

So, to save cost, Backblaze went with HDDs that weren’t designed for this particularly demanding application. And when those HDDs failed at higher rates than those that were designed for that particularly demanding application, the company questioned the reliability of the HDDs instead of questioning its own procurement criteria (which, as Tom’s Hardware noted in February 2016, “was borne of necessity; it began during the Thailand floods when HDDs were excessively high priced”).

Supposedly, said Tom’s Hardware, “Backblaze issued numerous disclaimers about the applicability of the findings outside of its own unique (and questionable) use case.” Candidly. I’m not sure where those disclaimers appeared; I sure don’t see them within the report itself. Regardless, “the damage from the information dealt Seagate an almost immeasurable blow in the eyes of many consumers.” And that, I’ll frankly proffer, is profoundly unfair. The courts, who tossed out a class-action lawsuit subsequently filed by one complainant, apparently concurred.

For what it’s worth, all four of my Seagate 3TB HDDS are seemingly working just fine so far. They came pre-configured, formatted HFS+ and in a clever performance-plus-reliability RAID combo:

• Each pair configured RAID 0 “striped” (for performance), with
• Both pairs then combined via RAID 1 “mirrored (for reliability)

Undoing all this upfront configuration (which admittedly did have the advantage of relying solely on the software RAID 0/1 facilities already built into MacOS) was a bit tricky, but I accomplished it. I’ve now got an APFS-formatted, RAID 5-configured array via SoftRAID (now owned by Other World Computing, who coincidentally also acquired AKiTiO a few years ago). And although the intermediary Thunderbolt-to-quad-SATA translation hardware would normally make it infeasible to assess HDD health via ongoing S.M.A.R.T. monitoring, SoftRAID neatly manages this bit (maybe, more accurately instead worded, “these bits”?), too.

HDDs are, as my own teardown showcases, complicated pieces of hardware-plus-software. That they work at all, far from reliably for many years, validates my August 2022 observation that they’re “amazing engineering accomplishments”:

• One or (usually) multiple platters, spinning at speeds up to 15,000 RPM. Each platter mated to one or (usually) two read/write heads, hovering over one or both sides of the rapidly rotating platter only a few nanometers away, and tasked with quickly accessing the desired track- and sector-stored details.
• Low-as-possible power consumption and high-as-possible ruggedness and reliability, in contrast to other contending design considerations.
• And ever-more data squeezed onto each platter, thanks to PRML (partial-response maximum-likelihood) sensing and decoding and now-mainstream PMR (perpendicular magnetic recording), next-generation SMR (shingled magnetic recording) and emerging successor HAMR (heat-assisted magnetic recording) storage techniques.

But, in order for them to work reliably for many years, they need to be used as intended. Backblaze seemingly didn’t do so. Was an inherent compromise in Seagate’s design at least partly to blame? Maybe. Reiterating what I said earlier, the ST3000DM001 and its product-family siblings marked Seagate’s initial entry into the 1 TByte-per-platter domain. Ironically, the Hitachi HUS724030ALE641 HDD I tore apart nearly two years ago, which dated from April 2013, was also a 1 TByte/platter design.

But that wasn’t the Hitachi HDD that Backblaze compared the Seagate ST3000DM001 against. It was the much older HDS5C3030ALA630, which not only required 5 platters (and 10 read/write heads) to achieve that same total-capacity metric, but also only ran at 5940 RPM rotational speeds. When you unwisely try to compare apples and oranges, you undoubtedly encounter variances. And in summary. I guess that’s my guidance to all of you: be wise. Don’t be fooled by sensationalist clickbait, whether related to technology, politics, or anything else, that presents you with a cherry-picked subset of the total applicable dataset in attempting to persuade you to accept a distorted conclusion. Question your own assumptions? Yes. But also question others’ assumptions. As well as their underlying motivations. I welcome thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• Peeking inside an HDD
• Question your assumptions: Diagnosing computer disruptions
• HDDs vs SSDs: It’s all about the random speeds
• Power vs energy: SSD and HDD case studies

The post Fairly evaluating HDD reliability appeared first on EDN.

An off-the-shelf secure authentication IC combined with cloud-based security software-as-a-service (SaaS) claims to manage and update embedded security credentials in the field instead of being limited to a static certificate chain implemented during manufacturing.

Microchip’s ECC608 TrustMANAGER authentication ICs are paired with Kudelski IoT’s keySTREAM device-to-cloud solution for securing key assets end-to-end in an IoT ecosystem throughout a product’s lifecycle. The combo enables custom cryptographic credentials to be accurately provisioned at the endpoint without requiring supply chain customization and can be managed by the end user.

Figure 1 Here is how a security silicon component (left) works with IoT cloud software for in-field provisioning. Source: Microchip

ECC608 TrustMANAGER, a secure authentication IC designed to store and protect cryptographic keys and certificates, is managed by the keySTREAM SaaS. Their combination allows end users to set up a self-serve root Certificate Authority (root CA). Next, the associated public key infrastructure (PKI) secured by Kudelski IoT creates and manages a dynamic certificate chain and provisions devices in the field the first time they are connected.

Once claimed in the SaaS account, the IoT devices are automatically activated in the user’s keySTREAM service via in-field provisioning. In other words, security ICs like ECC608 TrustMANAGER come with a pre-provisioned set of keys that will be controlled by keySTREAM at the time the IoT device connects for the first time.

The operation—called in-field provisioning of the PKI— happens in-field, and after in-field provisioning, the fleet of devices containing the ECC608 TrustMANAGER is first claimed and then activated in the user’s keySTREAM account.

An IoT device is “claimed” when the purchased batch of security ICs shows up in the keySTREAM account but not connected yet. It’s “activated” when the purchased batch of security ICs is connected to keySTREAM and the in-field provisioning takes place.

Figure 2 Specialized authentication semiconductors tie up with IoT security services for reliable cybersecurity on embedded systems. Source: Microchip

It’s a pivotal moment in the industry’s quest to secure the IoT landscape and make provisioning easier. Especially when the volume of connected devices rapidly increases, and security standards and regulations steadily tighten.

Moreover, security standards and upcoming regulations increasingly require the upgradability of security infrastructure for IoT devices. This poses a dilemma for traditionally static IoT security implementations, which require physical upgrades like changing out the security ICs in each device to stay in compliance.

The combo of silicon components and key management SaaS automates provisioning and facilitates easy device ownership management without changing hardware. It also streamlines the supply chain processes for distribution partners.

Related Content

• Best practice for end-to-end IoT security
• Practical steps to security for IoT devices
• Navigating IoT security in a connected world
• Legal requirements for IoT security start to emerge
• Hardware-Based Design Approach for Smart-Home IoT Security

The post Authentication IC ties up with IoT SaaS for in-field provisioning appeared first on EDN.

Microchip has added its ECC608 TrustMANAGER with Kudelski IoT’s keySTREAM software as a service (SaaS) to its Trust Platform of devices, services, and tools. The cloud-based key-management SaaS integrates with the ECC608 secure authentication IC to increase the security of IoT network-connected products. It also simplifies setup and lifecycle management.

The ECC608 TrustMANAGER IC stores and protects cryptographic keys and certificates, which are then managed and updated in the field via keySTREAM. This combination allows the setup of a self-serve root Certificate Authority and associated public key infrastructure (PKI). Users can create and manage a dynamic certificate chain and provision devices in the field the first time they are connected.

The ECC608 is the first security IC in the TrustMANAGER series. To get started, download the Trust Platform Design Suite and test the KeySTREAM use case under the ECC608.

Prices for the ECC608 TrustMANAGER start at $0.75 each in lots of 10,000 units. An activation fee is applied only after the device has been connected for the first time.

TrustMANAGER product page

Microchip Technology

Kudelski IoT

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Security IC teams with key-management SaaS appeared first on EDN.

A multichannel oscilloscope calibration system, the Fluke 9500C automates time-consuming testing to maintain scope accuracy and reliability. The 9500C provides simultaneous output on all channels and can be fully automated with MET/CAL software for hands-free operation.

A core component of the 9500C mainframe is the 9540C active head. Each mainframe can control up to five heads, enabling the calibration of a 4-channel oscilloscope with an external trigger. The ability to actively drive all four active heads at the same time with simultaneous output results in faster test times and eliminates lead changes.

The compact 9.4×4.6×2.2-cm active head generates calibration signals at the oscilloscope input. It enables the 9500C to deliver various signals: DC levels up to ±220 V, calibrated amplitude square waves up to 210 V pk-pk from 10 Hz to 100 kHz, and leveled sinewaves from 0.1 Hz to 4 GHz with precisely controlled pulse edges.

If full automation is not immediately required, the 9500C can be configured with just a few, or even one, active head. Additional heads can be easily added as needs change. To request a price quote, use the link to the product page below.

9500C product page

Fluke Calibration 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Instrument improves oscilloscope calibration appeared first on EDN.

LoRa Corecell full-duplex gateway reference designs from Semtech are tailored to address applications operating in the U.S. 915-MHz and China 490-MHz ISM bands. Both the SX1302CFD915W1-H (915-MHz) and SX1302CFD490GW1 (490-MHz) reference designs leverage Semtech’s LoRa Core SX1302 digital baseband IC and SX1255/7 RF transceiver.

The reference design files are available to download from the Semtech website. While evaluation kits are not offered for purchase, the hardware used in the design comprises a Corecell board populated with the LoRa Core chips, a duplexer, and a Raspberry Pi. The design supports full-duplex operation with eight uplink channels and one downlink channel.

Using the capabilities of the SX1302 baseband IC, the uplink channels can detect up to 64 LoRa packets and simultaneously demodulate 16 125-kHz LoRa packets with spreading factors between SF5 and SF12. The SX1302 also provides one 125/250/500-kHz demodulator for single SF operation and one (G)FSK demodulator for legacy applications.

The gateway implementation achieves a tenfold reduction in power compared to the previous generation of LoRa baseband ICs. With a discrete power amplifier and low-noise amplifier, transmit output power at the antenna port can be up to +27 dBm. Receive sensitivity can be as low as -140.8 dBm for the U.S. 915-MHz band and -137.4 dBm for the China 490-MHz band.

To learn more about the LoRa Corecell full-duplex gateway reference designs, read Semtech’s blog here.

SX1302CFD915GW1-H product page

SX1302CFD490GW1 product page

Semtech

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Reference designs offer LoRa gateway solutions appeared first on EDN.

Toshiba’s SmartMCD series of gate drivers with embedded MCUs offers sensorless control of three-phase BLDC motors in automotive applications. The first entry in the series, the TB9M003FG combines a 32-bit Arm Cortex-M0 core, 64 kbytes of flash memory, and power control functions for driving N-channel power MOSFETs in drive systems for water pumps, oil pumps, fans, and blowers.

The integration of a microcontroller helps reduce design size and component count, while enabling complex motor control. To minimize the load on the MCU, the gate driver employs a vector engine and hardware for sensorless sinewave control. Communication interfaces include a LIN transceiver and controller, two full-duplex serial interfaces (UARTs), and one SPI-I/F.

The TB9M003FG is AEC-Q100 Grade 0 qualified and operates over a temperature range of -40°C to +175°C. Toshiba has started volume shipments of the SmartMCD TB9M003FG gate driver. A reference design using the TB9M003FG in a motor drive circuit for automotive body electronics is available here.

TB9M003FG product page 

Toshiba Electronic Devices & Storage 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Smart gate driver controls automotive motors appeared first on EDN.

The integrated Type 2GT multiband LoRa radio module from Murata reduces IoT device complexity and streamlines the certification process. It provides LoRa and Long Range-Frequency Hopping Spread Spectrum (LR-FHSS) communication over sub-GHz and 2.4-GHz ISM bands, as well as the satellite S-Band.

Along with Semtech’s LR1121 RF transceiver, the Type 2GT module contains a temperature-compensated crystal oscillator, a second 32-kHz crystal, an RF switch, and an RF matching network. Communication interfaces include SPI and multiple GPIOs. Housed in a 9.98×8.70×1.74-mm metal LGA package, the Type 2GT operates over a temperature range of -40°C to +85°C with a supply voltage of 1.8 V to 3.6 V.

The Type 2GT radio module is certified to European CE and American FCC standards, the Japanese TELEC standard, and the Canadian IC standard. Designers can reuse the module’s RF test reports across different certification authorities, easing compliance challenges.

Samples of the Type 2GT LoRa transceiver are available now. The part has also entered mass production.

Type 2GT product page

Murata Manufacturing 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post LoRa module aims to simplify wireless design appeared first on EDN.

A new family of microcontrollers optimized for machine learning (ML) applications at the edge claims to enable real-time command and response, eliminating the need for cloud connections while substituting high-performance microprocessors.

Infineon Technologies has unveiled the next generation of PSOC microcontrollers that are AI-enabled for real-time responsiveness in connected home devices, wearables, and industrial applications. The new PSOC Edge E8 series of MCUs—E81, E83, and E84—facilitates compute responsive AI while balancing performance and power requirements and providing embedded security for Internet of Thing (IoT), consumer, and industrial applications.

Figure 1 The new edge MCUs enable developers to quickly move from concept to product and facilitate ML-enabled IoT, consumer, and industrial applications. Source: Infineon

The PSOC Edge E81 utilizes the Arm Helium DSP technology and Infineon’s NNLite Neural Network (NN) accelerator. It uses a combination of Cortex-M55 plus DSP for the high-performance domain and Cortex-M33 and DSP for the low-power domain. E81 microcontrollers are primarily targeted at cost-effective design solutions.

The PSOC Edge E83 and E84 microcontrollers, while offering the same combination for high-performance and low-power domains, also use the Arm Ethos-U55 micro-NPU processor and provide a 480x improvement in ML performance compared to existing Cortex-M systems. At the same time, E83 and E84 use the NNlite accelerator for ML applications in the low-power compute domain.

The microcontroller trio

Steve Tateosian, senior VP of industrial MCUs for IoT, wireless and compute business at Infineon, spoke to EDN before the release of PSOC Edge E8 series MCUs. He said that the ML-enabled edge MCU classification aims to facilitate the right product for the right application at the right price point. He quoted a thermostat as an example to explain how these MCU tiers work.

With an E81 microcontroller, a basic thermostat may have an LCD doing cloud-based natural language recognition. On the other hand, a mid-range thermostat may want to recognize voice locally by implementing natural language on device itself, thus removing cloud from the equation altogether. That’s an E83 microcontroller.

Finally, for Nest-like high-end devices, designers can add features like gesture and motion control as well as low-power graphics display—up to 1028×768—for a rich graphical user interface (GUI). “All three devices support voice/audio sensing for activation and control, while the E83 and E84 MCUs deliver increased capabilities for advanced HMI implementations, including ML-based wake-up, vision-based position detection, and face/object recognition,” said Tateosian.

Figure 2 Three ML-enabled PSOC edge MCUs aim to facilitate the right product for the right application at the right price point. Source: Infineon

“Designers can create a cost-effective solution with E81, but if they want to add a stronger ML acceleration hardware, they move to E83,” he added. “They can use E84 if they want to add graphics support.”

Design support services

All three edge MCUs support extensive peripheral sets, on-chip memory, robust hardware security features and a variety of connectivity options including USB HS/FS with PHY CAN, Ethernet, WiFi 6, BTBLE, and Matter. “The PSOC Edge E8 series MCUs feature a rich peripheral mix with many options in terms of in-memory as well as external memory support,” Tateosian said.

When designing ML applications on edge devices, engineers must be conscious of the amount of code in general,” he added “So, the amount of memory as well as the type of memory located on the MCU are critical.” These MCUs offer an elegant solution in terms of on-chip RAM encompassing SRAM and RRAM content.

Hardware design support includes an evaluation base board with Arduino expansion header, sensor suite, BLE connectivity for provisioning and Wi-Fi for smartphone, and cloud connectivity. On the software side, the new PSOC Edge E8 series MCUs are compatible with the earlier versions of PSOC for edge MCUs to ensure that design engineers can reuse their software investments.

Moreover, Infineon’s ModusToolbox software platform provides a collection of development tools, libraries, and embedded runtime assets to complement the development experience. It also integrates Imagimob Studio, which Infineon acquired through its purchase of the Swedish firm last year. It delivers end-to-end ML development capability spanning from data to model deployment.

Infineon will demonstrate the capabilities of this MCU series for AI and ML applications at Embedded World in Nuremberg from 9 to 11 April 2024.

Related Content

• Key technologies push AI to the edge
• Edge Intelligence Ticks Many Boxes For AI
• Microcontrollers take on growing role in edge AI
• Custom AI Inference Has Platform Vendor Living on the Edge
• The AI-centric microcontrollers eye the new era of edge computing

The post The ML-enabled edge MCUs available in three design tiers appeared first on EDN.

Introduction

Solar day lamps (SDL) are simple and cost-effective. A few examples of SDLs have been described in [1], [2] and [3]. An SDL without any energy storage element suffers from frequent changes in the light intensity. Also, a backup is required after sunset. The design of a hybrid lamp is given here. It uses solar PV panels and mains power sources and provides constant light output. This design can utilize solar energy even when the panel output is down to 10%. Proportionately, that much load is reduced on the mains supply.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Block diagram

The block diagram of proposed hybrid lamp is shown in Figure 1. It consists of an array of LEDs lamps: A1 to A9. Each of these lamps consists of five, 1 W white LEDs connected in series. These LEDs are controlled using the LED driver circuits.

Figure 1 Block diagram of the hybrid lamp design with 9 LEDs lamps where each lamp consists of five, 1 W white LEDs connected in series and all LEDs are controlled using LED driver circuits.

LEDs are powered using a 30 watt-peak (Wp) PV panel as well as from an adapter (AC-DC converter) as shown in Figure 1. The LED drivers are controlled through 9 digital output (DO) pins of the MCU. Solar panel voltage Vpvs is sensed using a potential divider circuit and is connected to the ADC input pin of MCU. Similarly, current flowing through the first LED array A1 is sensed and is connected to another ADC pin. The adapter output voltage VMF is sensed using potential divider circuit and is connected to a digital input (DI) pin of the MCU. This is a digital signal which is used to sense whether adapter power is available or not. One more DO pin is connected to the “adapter standby mode” pin to reduce power consumed by the adapter when all arrays are powered from solar panel and adapter is on no load.

Circuit Diagram

Figure 2 shows the circuit diagram. The adapter output VM is connected to the top (red) rail of the circuit. After passing through diode D19 (1N5822), voltage VMD is applied to the circuit. Similarly, the middle rail (yellow) is connected to the solar panel output Vpv. After passing through diode D20, voltage Vpvd is applied to the circuit. A big filter capacitor C2 (10000 µF 35V) is connected across panel terminals. This capacitor will eliminate sudden changes in panel voltage so that the firmware runs smoothly.

Figure 2 Circuit diagram of the proposed hybrid lamp where the adapter output VM is connected to the top (red) rail of the circuit and to the solar panel output Vpv is connected to the middle rail (yellow).

LED driver circuit for array A1 is shown in full detail. Array A1 consists of 5 white LEDs connected in series. It is connected to the ground terminal through R1; a 10 Ω, 2 W resistor. The voltage drop across R1 (Ipv1) is connected to ADC1 (pin 24) of the MCU IC3 ATMEGA 8 as shown in Figure 3. A1 is driven by two PNP transistors T3 and T4 (2N4033). Transistor T3 is controlled by the digital output PD0 of the MCU through NPN transistor T1 (BC546). The PD0 signal is inverted using the NOT gate of IC1 (74HCT04). This signal drives transistor T2 which drives T4.

When PD0 is LOW → T3 OFF, T4 ON (A1 on solar and green indicator LED2 ON)
When PD0 is HIGH → T3 ON, T4 OFF (A1 on mains and red indicator LED1 ON)

In the same way, remaining arrays A2 to A9 are controlled through their respective digital output signals. Note that resistors R2 to R9 are connected to the anodes of the LED array. This is done to reduce the wiring, as single ground wire connects to all the cathodes of the last LEDs of A2 to A9.

Figure 3 The MCU connection diagram.

The MCU and LED driver circuits are powered using regulator IC4 (LM7805). It’s input is connected to both VMD and Vpvd power rails through D21, D22, R77 and R78. Hence, 5 volts is available on either solar or mains power sources.

Figure 4 shows the circuit diagram of all digital outputs. It includes two 74HCT04 ICs, IC1 and IC2, for inverting a total of 9 digital output signals. The 18 output lines are connected to the LED driver circuits through 18 diodes D1 to D18 (1N4148). Figure 5 shows the assembled PCB with LED driver circuits and the MCU interface.

Figure 4 Interconnection diagram of all digital outputs, 18 output lines are connected to the LED driver circuits through 18 diodes (D1 to D18).

Figure 5 Assembled PCB showing LED driver circuits and MCU interface.

 Adapter (AC-DC converter) selection

Figure 6 shows the adapter used in the prototype having output voltage of 18 V. However, ideally to match the voltage at max power (Vmp) of the solar panel we need 17.5 V. One diode in series can drop the voltage by about 0.7 V. There are adapters available which have provisions for adjusting the output voltage within ±10% tolerance. Using this type of adapter, it is possible to set the output voltage to 17.5V.

Figure 6 Photographs of the 30 Wp, 2’ x 2’ solar panel (top) and 18V, 3 A adapter (bottom). A diode is used to drop the voltage closer to the ideal 17.5 V to match the Vmp of the solar panel.

 Specifications and calculations

The solar panel specifications are as follows:

1. Power Rating (P) = 30 Wp
2. Voltage at MAX Power (Vmp) = 17.5 V
3. Current at MAX Power (Imp) = 1.714 A

The calculations for the LED lamp are as follows:

1. Forward voltage of white LED = 3.12 V
2. Current through array A1 = [17.5 – (5 x 3.12)] / 10Ω = 0.19 A
3. Power consumed by array A1 = 17.5 * 0.19 = 3.325 W
4. Power consumed by 9 LED arrays = 9 x 3.325 = 29.9 W

Algorithm

As discussed earlier, the hybrid lamp draws power from both solar PV panels and the adapter. If both supplies are present, then it runs a maximum power point tracking (MPPT) algorithm to maximize solar power. Table 1 shows the operating modes.

Table 1 Operating modes of the hybrid lamp. If both supplies are present, the design runs an MPPT algorithm to maximize solar power.

 Variables

The following are the variables used for the algorithm:

• n: Number of arrays which are PV Powered (n = 9 is initially set to handle full solar power)
• PV_POWER: power drawn from PV panel
• PRESENT_MODE: present mode of operation
• NEW_MODE: new mode of operation

The permissible numerical values of PRESENT_MODE and NEW_MODE are as follows where valid value(s) of n are indicated in the brackets for each mode:

• 0: Solar Day Lamp mode (n = 9)
• 1: Mains Powered mode (n = 0)
• 2: MPPT (n varies from 1 to 9)

 Constants

The following are the constants used for the algorithm:

• POWER_MIN: The minimum value of power. If PV power is < POWER_MIN, then declare solar not present. (POWER_MIN = 1 W or 1600 counts)
• P_DELTA: This value is used for generating hysteresis. (P_DELTA = 1 W OR 1600 Counts)
• VPV_MIN: This value is used for checking whether PV power is available or not. PV Power is not available if Vpv < VPV_MIN. (16 V OR 800 Counts of ADC0)

Data

The following is the data used for the algorithm:

• Array P(n): This data is used by the algorithm to control LED lamps A1 to A9. Table 2 shows the array of constants defined over 10 power levels.

Table 2 An array of constants defined for 10 power levels.

ADC details

The following are the ADC specifications. A count of 1024 corresponds to a 5 V input to the ADC pin:

• ADC resolution: 10 bits (1024 counts)
• ADC reference voltage = 5 V

Vpv calculations

Solar panel output Vpv calculations are as follows:

• VPV_MIN = 16 V (when MPPT is running, Vpv is maintained above VPV_MIN)
• ADC input voltage for VPV_MIN = 16 * 0.2444 = 3.91 V
• ADC count for 3.91 V = (1024/5) * 3.91 = 801

VPV_MIN calculations

VPV_MIN calculations are as follows:

• VPV_MIN = 16 V (when MPPT is running, Vpv is maintained above VPV_MIN)
• ADC input voltage for VPV_MIN = 16 * 0.2444 = 3.91 V
• ADC count for 3.91 V = (1024/5) * 3.91 = 801

 Ipv calculations

Solar panel output current Ipv calculations are as follows:

• Panel power at maximum power point = 30 W
• Current at maximum power point = 30/17.5 = 1.714 A
• When all arrays A1 to A9 are ON, Current through each array = 1.714/9 = 0.19 A
• Drop across 10 Ω resistor R1 = 10 * 0.19 = 1.9 V
• ADC Count for 0.19 Amp = (1024/5) * 1.9 = 390 count

Power calculations

Finally, the power calculations can be seen below:

• Read ADC0 → Count for VPVS
• Read ADC1 → Count for IPV1
• PV_POWER_32 = ADC0 * ADC1 * n
• PV_POWER = PV_POWER_32 / 64 (Shift right by 6 bits)
• PV power generated when one array is ON = 876 * 390 = 341640 counts
• PV power generated when 9 arrays are ON (30W) = 341640 * 9 = 3074760 counts

To limit the resolution to 16 bits, the counts are divided by 64:

• Count for 30 W -> 3074760 / 64 = 48043.125
• Count for 1 W -> 48043/ 30 = 1601.4375 Count or 1600 approx

Flow charts

The flow charts required for development of embedded firmware are given in Figure 7, Figure 8, Figure 9, and Figure 10. At power ON, the algorithm initializes timer, ports, modes and enables timer interrupt. The algorithm is executed inside the timer interrupt service routine.

Figure 7 Initialization flow chart where at power ON, algorithm initializes timer, ports, modes and enables timer interrupt.

Figure 8 A portion of the interrupt service routine where the algorithm is executed.

Figure 9 The rest of the interrupt service routine where the algorithm is executed.

Figure 10 The MPPT flow chart that is run if both supplies are present.

 Fabrication and testing

The LED lamp metal core PCBs (MCPCBs) were mounted on three aluminum channels. The aluminum channels absorb the heat generated by these PCBs and provide structural support. The controller PCB is mounted on the back side of the LED array. The working of hybrid lamp is captured in the photographs shown in Figure 11 and Figure 12 where the lamps are working on 100% solar power and 100% mains power respectively. The lamp is placed in front of a mirror to check the light output from LED array. Simultaneously, we can see the PCB and the indicator LEDs. From these two Figures, it is clearly seen that we get same light output whether the array is solar powered or mains powered.

Figure 11 Lamp working on 100% solar energy (all green indicator LEDs are ON).

Figure 12 Lamp working on 100% mains power (all red indicator LEDs are ON).

In order to capture the dynamic workings of the lamp, when the solar energy is varying and the MPPT algorithm is running, see the video below.

In this video, we are able to see LED array light output in the mirror and also observe the indicator LEDs changing from green to red and vice versa sequentially. In this case, the solar panel is rotated in the sunlight to vary the PV power generated. This video confirms that the MPPT algorithm is working properly as the LED array gives a constant light output when there is wide variation in solar power. One green LED is ON, meaning 11% of the energy is coming from solar. So, depending upon the number of green LEDs that are ON, we can calculate the percentage reduction in the load on the mains power supply.

When the whole array is running on solar power, we can make the digital output line going to the standby input of the adapter high (refer to Figure 1). Thus, reducing the power consumed by the adapter under no-load condition. Please note that this feature has not been implemented in the present code.

 Power ASIC design

The hardware complexity can be reduced by designing a dedicated power ASIC. The main features of the proposed ASIC are as follows:

1. Number of LED driver circuits: 16
2. MAX Voltage rating of drivers : 50 V
3. MAX current rating of each driver: 0.5 A
4. Regulated control power supply: 5 V, 1A
5. Sensing circuits for: Vpvs, Ipv1, VM

 Design of a 500 W fixture

Based on the hybrid lamp design given here, a larger lighting fixture can be designed. Here, an example of such a system, which uses a single 500 Wp solar panel is given. The high-level details of proposed design are as follows:           

1. PV panel specifications: 500 Wp, Vmp = 35 V, Imp = 14.2 A
2. LED lamp power rating:11 Watts (11 white LEDs connected in series)
3. Number of lamps: 64 (8 x 8 array)
4. Number of ASICs required: 4

This lighting fixture can be installed in large shopping centers, hospitals, offices etc., where it will provide constant light while maximizing the utilization of available solar energy. Even on a cloudy day it can reduce the load on the mains supply by 10 to 20%. Such a system will have an ROI of 3 to 4 years. Furthermore, it offers many other benefits such as decentralized design, very short wiring, lower transmission losses and provides light in the daytime if the mains power fails.  

Vijay Deshpande recently retired after a 30-year career focused on power electronics and DSP projects, and now works mainly on solar PV systems.

Related Content and references:

1. Solar day lamp designs use passive and active current limiting circuits
2. Solar day lamp designs provide low-cost lighting solutions, Part 1
3. Solar day lamp designs provide low-cost lighting solutions, Part 2

The post Solar-mains hybrid lamp appeared first on EDN.

Some of the commentary in response to Part 1 on this topic suggested that the two 1 pF capacitors, C4 and C5, had to be put in series for lack of availability of 0.5 pF parts.

A simulation of that presented circuit is seen as follows:

Figure 1 The circuit with a floating node and its Bode plot simulation.

Part selections differ somewhat from the original. These op-amps are virtual, the JFET is merely an available part from the simulation software and the diode represents the original photodiode. For all of that, these are all close enough. Please note the Bode plot of this configuration.

To keep using the pair of 1 pF capacitors, the following schematic is the same as above but with the addition of one more resistor, R8, in parallel with C4.

Figure 2 The circuit without a floating node (an additional resistor R8 added in parallel with C4) and its Bode plot simulation.

At 10 MΩ, resistor R8 provides a DC path for the formerly floating node to keep that node’s voltage from unpredictably shifting. Note that the Bode plot for this modified circuit is indistinguishable from the plot seen before.

Other options for tethering the formerly floating node exist as well. For example, R8 could be tied from the C4 and C5 junction to ground, again, with no visible effect on the Bode plot.

The best choice is best left to the designer.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

 Related Content

• No floating nodes
• Design precaution: Leave nothing floating
• Floats like a butterfly, stings like a bee
• The ground illusion: Don’t let it come back to get you

The post No floating nodes, Part 2 appeared first on EDN.

Anemometers are an important category of environmental sensor. Articles about their design, data capture, and linearization have comprised topics featured in EDN Design Ideas, several quite recently.

Less well covered, however, has been the topic of accurate, inexpensive, (even improvisational) methods for their testing and calibration.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The calibration method shown here is suited for sensitive, low air speed, miniature, solid-state thermal airflow sensors with full-scale ranges up to 250 fpm (2.8 mph), two of which are illustrated in Figure 1 and Figure 2. This type is particularly useful in applications like HVAC setup and forced-convection cooling airflow distribution measurement and monitoring.

Figure 1 GO/NOGO thermal low speed airflow sensor, ON/OFF airspeed threshold is set by R4.

Figure 2 Linearized battery powered low speed thermal anemometer.

 The airspeed measured by any anemometer is relative to the instrument. Whether it’s the air or the anemometer (or both) that’s actually moving is irrelevant. This simple calibrator consists of a repurposed phonograph turntable capable of accurate operation at the traditional rotational speeds of 33.3, 45, 78 rpm, and of course, zero. See Figure 3.

Figure 3 “Groovy” anemometer calibrator built from salvaged phonograph.

 Conveniently, the diameter of a standard phonograph record is one foot. So, an airspeed sensor mounted on the periphery of an ordinary discarded vinyl record will be moved through the air at:

Air speed (feet per minute) = π * RPM
33.3 rpm = 105 fpm
45 rpm = 141 fpm
78 rpm = 245 fpm

 Connections between the rotating anemometer sensor, external (stationary) power supply, and instrumentation are easily provided by a simple slipring commutator improvised from standard 3.5-mm 4-circuit audio jack and plug. The former is supported by an inverted plastic funnel glued to the record while the latter is affixed to the tone arm. Some light lubrication on the plug may be beneficial in minimizing potentially problematic drag on the turntable motor.

A suitable counterweight positioned diametrically opposite to the sensor under test can help balance the turntable against static (weight) and dynamic (centripetal) forces acting on the rotating circuitry.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Linearized portable anemometer with thermostated Darlington pair
• Adding one resistor improves anemometer analog linearity to better than +/-0.5%
• Proper function linearizes a hot transistor anemometer with less than 0.2 % error
• 15-bit voltage-to-time ADC for “Proper Function” anemometer linearization
• Transistor linearly digitizes airflow

The post A groovy apparatus for calibrating miniature high sensitivity anemometers appeared first on EDN.

When I did my first teardown of a LED-based light bulb nearly eight years ago, I figured it’d be a one-and-done. In coming to that premature conclusion, however, I didn’t consider the added functionality (such as network connectivity) enabled by the reduced power draw of the LED illumination subsystem versus that of the incandescent precursor. And I also didn’t take into account the diversity of functions (dimmable, three-way, etc.) and legacy form factors that LED upstarts would need to support. Here’s the to-date teardown list, which doesn’t even count LED illumination sources that aren’t bulb-shaped, like touch-activated and motion-sensing panels:

• Conventional
• Zigbee-controlled
• Wi-Fi-augmented
• Bluetooth-enhanced
• Multicolor
• Three-way
• Battery-backed, and
• Filament-based

Today’s teardown “victim” falls into the “legacy form factor” category. About three years ago, I decided to swap out around a dozen and a half (so far) of the nearly three dozen total mix of BR30 and BR40 incandescent bulbs that were already installed and in use in ceiling “cans” throughout the house when we bought it. The bulbs I’ve to date converted to all-BR40 LED successors had two common characteristics:

• They were easy to reach using only a conventional ladder (which, you’ll soon see, has been handy for not only initial but also ongoing access purposes), and
• They were in locales, such as the kitchen and my office, that saw frequent use, therefore particularly benefitting from LED conversion from a power consumption standpoint.

Speaking of which, here’s one of the “daylight” (5000K color temperature) replacements installed in my office, both off:

and dimly illuminated:

While I can’t definitively say that I’ve noticed a tangible drop in our residence utility bill post-swap, I certainly now feel better about turning (and keeping) the lights on than I did before. That said, the transition hasn’t been perfect. To my earlier “dimly illuminated” comment, all the multi-bulb circuits I’ve converted so far are “fed” by dimmer switches, thereby necessitating dimmer-compatible LED lights. Specifically, I’d bought a couple of these Sunco bulb 10-packs:

to leave me with some spares inventory, which I’d hoped I wouldn’t need to tap into for a while. Check out this conceptual cutaway of what mine supposedly look like inside:

Granted, mine are 17W/100W equivalents, not the 7W/50W equivalent one shown here. Regardless…hold that thought

Are they “zero flickering”? Not exactly. The bulk of the time I try to use them? Yes, actually. But…well, let me start by requoting a portion of my December 2023 teardown (this time with grammatical corrections made by yours truly to the original source):

Most dimmers installed today are designed to be used with high-power circuits to drive traditional filament lamps which were all quite uniform and dimmable by just a voltage change. LED lamps, on the other hand, are low-power and more complex. An LED bulb is a solid-state product that has built in circuitry (called a driver) that takes high-voltage AC input current and converts it to low-voltage DC current to drive the LEDs. Furthermore, driver specifications are not uniform across the LED industry.

There are many different types of dimmers installed in homes and offices, of various specifications (e.g., resistive; leading-edge and trailing-edge and electronic). So, when using new LED lamps with existing dimmers, matching old technology with new can be challenging.

 The drivers in dimmable LED lamps may work with many types of dimmers but not all. For instance, LED lamps tend to work better with trailing-edge dimmers rather than leading-edge dimmers. An existing dimmer may also have a minimum load that is too high for an LED lamp. For example, a 60 W filament lamp may use a dimmer that has a minimum load of 25 W, but the replacement LED has a power rating of 6.5 W – below the level required by the dimmer. Dedicated LED dimmers conversely have a very low minimum power rating.

The dimming experience can also be different with LED. Overall, the LED dimming performance is regulated by the capability of the LED driver/chip and the compatibility of the dimming circuit. Since there are a huge number of possible combinations of lamps and dimmers, it is very difficult to produce an LED lamp that works in all dimming environments.

LEDs currently have a lower dimming range than a filament lamp – LEDs currently dim down to about 10% of the total light output whereas filaments may go down to 1-2%. Low-voltage transformers as used with MR16 12V spotlights also add to the complexity.

Some of the issues that may occur when a dimmer is incompatible with an LED lamp are:

• Flickering – Lamps will flicker (can also occur if a non-dimmable lamp is used).
• Drop-out – No light output at the end of the scale.
• Dead travel – When the dimmer is adjusted, there is no matching change in light output (light may not dim to acceptable level).
• Not smooth – The light output may not go from dim to bright [editor note: and/or vice versa] linearly.
• Multiple lamps – issues may become apparent when multiple lamps are added.
• Damage or failure – LED driver, circuit or LED is damaged or fails.
• Load below minimum – The power load of the LED lamp is below the minimum required by the dimmer.
• Mixed models – Different models of LED will likely have different drivers, since drivers behave differently this could result in dimming issues.

I’ve personally experienced variants of several of these imperfections so far:

• One/multiple/all the bulbs in a given circuit will turn on only dimly, and flicker-filled, even at a supposed “full power” dimmer switch position.
• One-to-multiple of the bulbs won’t turn on at all, even with the others fully illuminated.
• Dimming the circuit causes one-to-multiple of the bulbs to either turn completely off or to stubbornly remain fully illuminated.
• etc.

The “fix” in all these cases? Turn them all off and back on again.

And regarding my earlier “spares inventory, which I’d hoped I wouldn’t need to tap into for a while” comment…again, reality hasn’t matched the hype. I’m reminded of the comment left by reader “vandamme0” to that previous December 2023 teardown:

Today I learned…that you can make outrageous lifetime claims based on single diode reliability at optimum temperature, and nobody calls you out on it because nobody keeps receipts for 18 years, 50,000 hours, or whatever you claim.

So far over the past three years, I “think” I’ve had three BR40 LED bulbs fail (which, if you’ve already done the math, you realize compelled me to buy more spares). Keeping in mind that “electronics things that break make great teardown candidates”, I held onto them, one of which is showcased here. That failure rate may not seem bad in the grand scheme of things, until you realize that:

• They represent ~20% of the population of LED bulbs that I initially installed, and
• None of the remaining BR30 and BR40 incandescent bulbs, all of which again were already installed and in operation when we arrived here a decade ago, have failed.

When I say “failed”, I should clarify. They “sorta” failed. After I’d turn on a bank of lights for a while, one of the bulbs would spontaneously turn off completely. Turning the bank of lights off and back on again wouldn’t immediately resuscitate it. But if I waited a while, the bulb would come back on…again, only for a while. I noticed that if I unscrewed it and removed it from the “can” it’d resurrect more quickly. Regardless, as time went on, the offender would fail more rapidly and take longer to revive; eventually, I’d just give up, grab the ladder, and swap it out.

The most likely potential failure mechanism, I suspect (and you may have already discerned), is heat. Incandescent bulbs get quite warm in ventilation-deficient “cans”, mind you, but the only thing they’re “cooking” is their filaments. With LED bulbs, on the other hand, there’s not only the LEDs themselves to consider but also all the circuitry in the base. And in a ceiling “can” there’s one other factor to consider; the bulb is pointing downward, which means that (as with similarly oriented CFL bulbs I’ve used and disassembled in the past) the heat rising off the LED array ends up baking the circuitry in the base above it. Lest you wonder, by the way, if I’m using my bulbs in an inadvisable configuration, this “stock” Sunco photo should set your mind at ease:

Enough setup; let’s dive into the dissection. I’ll as-usual start with some overview shots, accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

Some closeups of the markings around the side:

And finally, the tip of the base, both coin-accompanied and standalone:

Last time, the globe (I belatedly realized, to my dismay) was:

• Glass
• Sealed, and
• Gas-filled

This time, conversely, it was plastic and definitely not sealed:

Providing a convenient pathway to the interior:

Mission accomplished:

Rim variance around the circumference:

And now what you’re all really here to see:

Removing those two screws in the earlier photos didn’t get me very far:

so, I redirected my attention to the base:

That’s more like it:

Here’s another closeup of the front of the PCB “plate”, this time unencumbered by its prior surroundings, revealing the ring of “daylight” colored LEDs, a smattering of other circuitry (the IC at left marked BP5178F is the LED constant current driver, while the one at bottom right labeled TB120S is the bridge rectifier, both from unknown manufacturers), and the pass-through connection for the two wires on the other side:

But what’s that other two-lead pass-through connector for? Let’s flip the plate over:

It’s…umm…an electrolytic capacitor:

At this point, with no lack of intentional snark, I’ll reinsert the conceptual cutaway from earlier:

Giggle snort

We’re almost done; let’s get that metal “dish” (acting primarily as a heatsink, methinks…note the thermal paste residue) under the “plate” off to see if there’s anything underneath of note:

And the answer is…nope. That’s all, folks!

As always, your thoughts are welcome in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• Teardown: What killed this LED bulb?
• Teardown: Zigbee-controlled LED light bulb
• Teardown: Wi-Fi LED light bulb
• Teardown: Bluetooth-enhanced LED bulb
• Teardown: Cutting into a multicolor LED light bulb
• Freeing a three-way LED light bulb’s insides from their captivity
• Dissecting a battery-backed LED light bulb
• Figuring out a dimmable filament LED light bulb
• Teardown: What caused these CFL bulbs to fail?

The post The LED-based BR40: A bulb begging for placement that’s drafty appeared first on EDN.