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This engineer combines a fellow contributor’s design and analysis data with his own to deliver a “bit” better circuit result.

In his recent Design Idea, “DAC implementations: The spread-bit PWM strikes back”, frequent and favored contributor Christopher Paul does a terrific analysis of “spread-bit” versus “clustered-bit” PWM DACs. Something in Christopher’s results that I found particularly super impressive (and surprising) was his detailed tabulation of settling times for spread-bit DACs (see his Table 1). When combined with his design methods for precision 3rd order unity-gain ripple filters, they provide peak-to-peak ripple amplitudes of Vpp = 1/N.

What’s especially nifty is that, when normalized for length of the PWM cycle time (2b / 1mHz clock) and tabulated for some popular resolutions from b = 8 to 16, the number of PWM cycles required for the output voltage to settle to within one least significant bit (LSB) does a very interesting thing. It hovers around only 2 to 3 cycles. That was an impressive result. But of course it made me wonder if there might be a way to do perhaps even a a bit better.

Wow the engineering world with your unique design: Design Ideas Submission Guide

So I started digging. I didn’t really expect to succeed. But I found a candidate—from the Design Ideas archives of nearly two decades ago. The circuit in Figure 1 of “Fast-settling synchronous-PWM-DAC filter has almost no ripple” (full disclosure: also written by yours truly) avoids most of the problems of low-pass filtering by combining a differential integrator, A1, with a sample-and-hold amplifier, A2, in a feedback loop operating synchronously with the PWM cycle, T2 in Figure 2 of that same article.

If you make the integrator time constant equal to the PWM cycle time—that is, R1C1 =T2 —and, if the sample capacitor, C2, equals the hold capacitor, C3, then the filter can acquire and settle to a new DAC value in exactly one PWM-cycle time, i.e., a “unicycle!” Ripple suppression of the synchronous filter is, in theory, infinite. The only practical limit (there’s at least one of those, isn’t there?) is nonzero-charge injection from S2 into C3. However, the choice of a low-injected-charge switch for S2 and appropriately generous capacitances for C2 and C3 can easily result in ripple amplitudes in the order of microvolts.

Rewind to the present.

Figure 1 below shows that legacy circuit updated and supplied with an integrator time constant settling-time trim (R1). This simple mod completely removes the requirement stated in the 2008 Design Idea that the single-cycle settling critically depends on C2 and C3 being precisely equal.

Figure 1 This “unicycle” DAC ripple filter combines a differential integrator, A1a, with a sample-and-hold amplifier, A1b, in a feedback loop operating synchronously with the PWM and sample-and-hold timing signals. Note that the integrator time constant shown is centered around 65.4ms and 16bit “clustered bit” PWM resolution.

You can just twiddle R1 to precisely achieve the single-PWM-cycle (unicycle) settling. Note that this single adjustment not only effectively compensates for and cancels out the C2 and C3 tolerance, but also accommodates all integrator feedback loop passive components (i.e., R2, C1, C2, and C3). The compensation even includes U1 internal switch Rons.

However neither R1 nor the passive component tolerances have any effect on Vout = PWMdutycycle x Vref conversion accuracy, which is inherent—apart from small effects due to op amp A1 non-idealities (mainly comprising finite DC gain and input offset) and single-digit-ohms U1 internal switch mismatch. The latter are minimized by the paralleling of the U1a and U1b sections shown in Figure 1.

If  R1 is adjusted so that (R1 + R2)C1C3/C2 = Tpwm = 216 /1MHz, a precise unicycle settling will complete in exactly one 16-bit 65.536ms PWM cycle time (Figure 2). The final Vout = PWMdutycycle x Vref is inherent and is unaffected by R1 adjustment or passive part tolerances.

Figure 2 This settling DAC timing diagram sketch details the unicycle result.

It’s perhaps also worth noting that because rapid settling for this circuit doesn’t rely on “spread-bit” techniques with their dependence on software execution times, microcontrollers’ built-in PWM peripherals can be used for timing signal generation. This of course makes order-of-magnitude faster PWM frequencies and even faster settling times available. If required, that is.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• DAC implementations: The spread-bit PWM strikes back
• Cancel PWM DAC ripple with analog subtraction
• Implementing a DAC: The battle of the PWMs
• Cancel PWM DAC ripple and power supply noise

The post Clustered-bit PWM DAC pedals and settles in a “unicycle” appeared first on EDN.

An automotive sensor power supply appears deceptively simple to design but in fact poses many formidable challenges. The regulated output voltage is required to be 5V or 3.3V, depending on the logic bus voltage for the CPU. A simple low-dropout (LDO) regulator may dissipate considerable power across it even with a few tens of mA total sensor load.

The traditional approach uses a DC-DC convertor that provides a pre-regulated supply bus of around 6.5V. Note, however, that the output also needs to be protected from short-circuits to both ground and the battery bus. Hence a conventional sensor supply solution uses a three-terminal regulator IC-based power supply, preceded by a switching pre-regulator.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The circuit showcased in this Design Idea (Figure 1) gets rid of the DC-DC converter and also incorporates an in-built low-cost short-circuit trip based on a transistor linear regulator.

Figure 1 Component identities and values for the circuit showcased in this Design Idea are included in the list that follows.

• Q1, Q2 and Q3 = NPN MPSA 42
• Q4 = PNP MPSA 92
• R1,R2 = 1 KΩ
• R3 = 10KΩ
• R4 = 10 Ω
• R5 = 47 KΩ
• R6 = 100 KΩ
• R7 = 1 KΩ
• R8 = 100 Ω
• D3,D4 = 1N 914
• D2 = Zener 6.2V, 500mW
• D1 = Shottkey diode RB521 CS 30 L
• C1 = 100 KF, 50V

A single CPU pin interfaces with the sensor supply output circuit as shown. The CPU pin plays a dual role:

• It senses the sensor supply output through the R1,R3 potential divider. This is required for scaling the sensor outputs to ensure measurement accuracy. The CPU pin needs to be configured as an analog input for this purpose.
• It can be used to disable the sensor supply output by turning off the series pass transistor Q1. The CPU pin needs to be configured as an output for this purpose. A logic low level issued at the CPU output pin turns off Q3. The diode D4 ensures holding Q3 off even if the worst-case low-level CPU output is around 0.7V.

The series pass transistor can be turned off to conserve the power being dissipated in it when analog input sensing is not required. This system design countermeasure allows us to omit a switching pre-regulator to conserve continuous power dissipation across the series pass transistor.

Careful analysis of the sensor signal acquisition task reveals that the sensor signal typically needs to be read only for a few microseconds every, say, 100 milliseconds. Some slowly varying signals such as temperature may even be read only every second. Hence, for more than 99% of the total time, sensor signal acquisition is not necessary. We can therefore safely disable the sensor supply by turning off its series pass transistor.

As discussed previously, the series pass LDO is responsible for power dissipation if it is directly powered from the vehicle battery, since it drops a large voltage across it. But if we cleverly keep it off most of the time, we do not really need any DC-DC pre-regulation to conserve power.

Analysis of various current levels and role/values/ratings of various components are as follows:

• Q1: MPSA42 is a 500 mA NPN transistor with a minimum current gain of 40. A suitable higher-rated transistor may be used for higher current applications.
• Q2: This current limit transistor with current limiting resistor R4 = 10 Ω sets the current limit to approximately 700 mV/10 = 70 mA. This is just above the rated output current of 50 mA.
• D2 is a 6.2V 500 mW Zener (1N4735) in series with D3  (1N914), together generating a voltage reference of around 7V. The downstream voltage drops of the Q1 and Q2 base emitter junctions, coupled with the Schottkey diode RB521CS30L, generates a nominal regulated voltage of around 5V.
• The R1 and R2 chain of 1 KΩ each feeds around 2.5V to the CPU monitoring the analog voltage. This CPU can appropriately scale the sensor voltages gathered by its analog inputs to attain the desired accuracy.
• Transistor Q4 is a MPSA92 PNP with 500 mA collector current and a minimum current gain of 25. It acts as an isolating switch to isolate the current drive fed to the base of series pass transistor Q1.
• R7 and R8 together (1.1 KΩ) provide a current of around 4.4 mA to the series pass transistor base along with Zener reference D2. Assuming that the Q1 base current requirement is 1.2 mA or less, the Zener/diode combination will be adequately supplied with more than 3 mA of current. This current will firmly bias the Zener in its breakdown region.
• Resistor R5, along with transistor Q3, serve to switch on/off the base current of Q4 to restore/isolate the base drive to the series pass transistor Q1. Diode D4 firmly holds Q3 in the off state when the CPU issues a logic low level (≤0.7V) at its output interface pin.
• The collector current of the transistor Q3 in it on state will be around 1.2 mA , taking into account the diode D3 drop.
• When the sensor supply is to be turned off, the CPU interface issues a logic low level to the junction point of R1/R2. This turns off Q3 and hence Q4. D4’s role is described earlier to firmly hold Q3 in its off state.
• An off-state Q4 further turns off the base current plus Zener current supply to the series pass Q1. This in effect switches off the sensor supply.
• The CPU interface needs to be judiciously tailored depending on the logic low level of the CPU output. Based on the maximum low logic level output voltage, a suitably high value series resistance/divider may need to be inserted.
• The Schottky diode D1 protects the sensor supply from short to battery field condition as dictated by automotive norms

This idea illustrates the architectural philosophy for the sensor supply architecture discussed. Based on the actual application constraints the component values will have to be tailored.

For high voltage battery buses such as 24 V or 48 V, the resistors’ values and transistor selections need to be suitably altered to meet power and voltage requirements. Since we are aiming to turn on the series pass for around a millisecond for every 0.1 second or higher, a power transistor with robust “thermal capacitance” may be needed for optimal thermal performance with higher voltage buses.

The discerning designer is expected to make suitable changes to the transistor ratings and resistor values, without violating the basic design philosophy, to suit diverse automotive scenarios such as a battery bus of 24V or 48 V. Depending on the application scenario, the designer may also choose to use a separate CPU output pin with an extra dedicated NPN transistor across R2 to switch Q3.

Vishwas Vaidya is a graduate of the Indian Institute of Technology in Delhi, India. Currently, he is self-employed as an engineering consultant and industry faculty member in the field of embedded systems for global automotive clients and high-repute academic institutions. Vishwas’ articles and research reports have appeared in many worldwide engineering publications.

Related Content

• Automotive low side output switch architecture suitable for 8 to 48 volt buses and beyond
• When can a sensor be used in an automotive system?

 

The post Automotive sensor power supply without a switching pre-regulator appeared first on EDN.

A dissimilar laser technology versus the single-mode sibling trades off operating range for cost, at least theoretically. But it’s still faster than the LED-based predecessor.

Last month’s premiere small form-factor pluggable (SFP) module teardown of a single-mode optical transceiver showcased either a Fabry-Perot– or distributed-feedback-(DFB) based semiconductor diode laser operating at 1310 nm.

I’m not sufficiently versed in the technology to visually differentiate between the two—knowledgeable reader insights are welcomed—but I know enough to know that today’s 850 nm multimode optical module uses neither of them.

Requoting my previously published tutorial on SFPs and their siblings:

SFP modules most commonly run at the following wavelengths (all are center frequencies):

• 850 nm (“multimode”)
• 1300 nm (“multimode”)/1310 nm (“single-mode”)
• 1550 nm (“single-mode”)

The distinction between multimode and single-mode fiber optics is important to comprehend and keep in mind, as the two technologies are not interchangeable (although some modules will work with both associated cable material types).

Multimode was historically much less expensive to implement, at the trade-off of lower usable transmission distance. It features a comparatively larger cable core (50 to 62.5 microns) that lets multiple light signals travel down different paths at the same time, and it usually uses lower-cost LEDs or vertical-cavity surface-emitting lasers (VCSELs).

Single-mode features a comparatively tiny core (about 8 to 10 microns), which allows only a single ray of light to pass straight through without bouncing off the edges, and it uses focused lasers as a light source. Its historical cost disadvantage versus “multimode” has more recently decreased, due in part to the availability of non-proprietary, widely compatible modules. And as noted earlier, it generally specifies much longer usable transmission distances.

Different emitter, same dim red glow

The “uses lower-cost LEDs or vertical-cavity surface-emitting lasers (VCSELs)” excerpt from the above is strictly accurate, although in the modern era it’s half-obsolete. Near-infrared LEDs were indeed leveraged with early sub-Gbit 850 nm SFP modules.

However, as a helpful reference I came across notes, “their maximum rate of about 622 Mb/s meant that they could not support 1 Gb/s or higher transmission.” Therefore, I expect to find an 850 nm VCSEL transmitter inside today’s teardown victim, along with a spectrally tuned variant of the earlier 1310-nm receiver.

I first visually confirmed the 850 nm spectrum association by plugging the module into a SFP cage-inclusive multi-port switch in a dark room and (quickly!) discerning the light coming out of the module’s transmit connector.

You might ask why it’s perceptible (and smartphone camera-capturable) at all, given that the human visual spectrum range extends only to around a 750 nm wavelength (corresponding to a ~400 THz frequency). To answer that question, I’ll refer you to another excerpt from my earlier requote: “all are center frequencies”. Even though 850 nm (~3.5 THz) itself may be beyond the range of human visual perception, the transmitter’s bell curve(-ish) output profile seemingly still has a modicum of signal strength at the visual wavelength end of its overall distribution.

Today’s patient, another SFP module (versus higher-speed SFP+), was bundled with a media converter I’ll keep as a spare for potential future lightning-strike galvanic isolation purposes.

Initial perspectives

I’ll as-usual start with some overview shots, as-usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes.

Top.

This time accompanied by a close-up of the embossed transmit and receive direction arrows also mentioned in last month’s teardown (and more generally found in all optical modules I’ve seen).

Right side (as before, with “right” referencing its orientation when inserted in a network switch or other gear’s SFP port).

Bottom (as was the case last time, note the retractable retaining pin).

And left side.

The SFP connector end, from both right-side-up and upside-down module perspectives.

Same goes for the optical fiber connector end, first with the dust cap still in place.

And now post-dust cap removal.

Dissection time

As before, bending back on the side tab you might have noticed earlier (if not, please go back and see), holding the outer and inner enclosure pieces together, is our pathway to the insides. There are two tabs, one on each side, although only the left side one was initially depressed.

As usual, the multiple hinge and associated pieces, conceptually similar to those we saw last month, fell out as the enclosure halves separated.

And there we are.

One screw is all that keeps the PCB attached to the metal assembly surrounding it.

Free at last.

Here’s the bottom of the PCB.

The optical receiver module is on top at the left edge, visually similar to the one found in last month’s single-mode SFP module albeit tuned for a different incoming signal wavelength, with the 850 nm VCSEL-based transmitter below it and conversely looking very different than its 1310 nm laser predecessor shown in the following comparison photo.

Now for the PCB topside of today’s patient.

The ordering is (obviously) reversed in this case; transmitter at top left and receiver below it. And what of the two ICs on this side? Let’s take a closer look.

The larger of the two has the following four-line topside mark; see also my notes in brackets.

1138142
780KF VJ [The second character might instead be the letter O]
PHL [There’s another three-digit code to the right, but it’s obscured by the yellow paint. In a photo I found online, it’s “141” but seemingly not in this case; I think that the first character is “B”]
e4 [This seems to be a company logo, given that it’s surrounded by a circle. Next to it is, judging from other photos I’ve seen, the two-character code “ES”, albeit again yellow paint-obscured]

A Google search on the phrase “1138142 IC” suggests that STMicroelectronics is the supplier but doesn’t reveal anything about the chip’s function. Reader insights are welcomed!

The smaller IC is marked as follows; again, note my comments in brackets.

532R
B809 [As before, the third character here may instead be the letter “O”]

As before with the single-mode module, I’m assuming this is an EEPROM storing data such as the module’s serial number, vendor name, compatibility codes, and calibration data.

In closing, the SFP interface and LC (Lucent Connector) ends of the PCB are visually identical to the ones found in last month’s module, so I’ve decided to spare you the photo redundancy. See last month’s teardown images for representations of how these ones also look. And as always, please share your thoughts on what I’ve found today in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• SFP: The single-mode module autopsy
• SFP: Add-in module delivers diminutive performance and flexibility
• TP-Link MC220L: Media conversion keeps the network well
• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• Design considerations in high-speed fiber networks

The post SFP: The multimode module autopsy appeared first on EDN.

Spin a heavy wheel or vibrate a piece of silicon, and you get a traditional gyroscope. Spin two beams of light inside a coil of fiber, however, and you get a masterclass in relativistic physics turning into precision navigation.

Figure 1 The VG2103S series rugged single-axis fiber optic gyroscope provides accurate motion sensing under severe shock and vibration. Source: MostaTech

From the whirring bearings of mechanical gyros to the silicon pivots of MEMS, navigation has long relied on moving parts. But in the fiber optic gyroscope (FOG), it’s light itself that spins—racing through coils of glass to sense the Earth’s rotation.

The fiber optic gyroscope remains a marvel of solid‑state engineering, bridging Einstein’s relativity with modern tactical guidance. By harnessing the Sagnac effect in a coil of optical fiber, it delivers precision without moving parts, an elegant fusion of physics and practicality that continues to define high‑end navigation systems.

Core physics: Re‑introducing the Sagnac effect

Counter‑propagating beams

At the heart of the fiber optic gyroscope lies a deceptively simple idea: send two light beams in opposite directions through a long coil of fiber. If the coil is stationary, the beams return in perfect synchrony. But when the coil rotates, one beam travels a slightly longer path while the other travels a shorter one, creating a measurable difference.

Rotation and phase shift

That difference is tied directly to the rotation rate, Ω. The result is a phase shift, ΔΦs, between the counter‑propagating beams. In essence, the gyroscope translates angular velocity into an optical interference pattern—a bridge between motion and light.

Engineering reality check

On paper, the equations look straightforward. In practice, the challenge is immense: engineers must detect phase shifts on the order of microradians. That’s where the true marvel begins—not in the physics itself, but in the precision engineering that makes such delicate measurements reliable in real‑world navigation systems.

Anatomy of a FOG: The key components

The light source

At the front end sits the superluminescent diode (SLED). Unlike a narrow‑line laser, the SLED provides broad spectral output that suppresses coherence noise. This choice minimizes Rayleigh scattering and back‑reflection artifacts, ensuring the gyroscope’s signal remains clean enough to resolve microradian phase shifts.

Figure 2 Superluminescent diodes provide the low coherence and high brightness required for high-performance fiber optic gyroscopes (FOGs). Source: AeroDiode

The fiber coil

The coil is the heart of the sensor. Engineers rely on polarization‑maintaining (PM) fiber to keep the light’s polarization stable as it races through kilometers of glass. Without PM fiber, environmental stress—temperature gradients, vibration, or bending—would scramble the polarization state and corrupt the phase data. The coil’s stability is what makes the Sagnac effect measurable in practice.

The phase modulator

To translate tiny phase differences into usable signals, the system employs integrated modulators, often lithium niobate (LiNbO3) devices driven by precision op‑amps. By biasing the interference pattern, the modulator shifts the signal into a measurable regime, allowing the electronics to lock onto rotation‑induced phase shifts with high fidelity.

From open‑loop to closed‑loop: The engineering polish

The limitation

An open‑loop fiber optic gyroscope is conceptually straightforward: measure the interference pattern directly and infer rotation from the phase shift. But this simplicity comes at a cost. Scale‑factor drift creeps in over time, and the dynamic range is limited; as a result, large rotations push the system out of its linear regime, degrading accuracy.

The solution

Closed‑loop architecture solves these shortcomings with elegance. Instead of letting the Sagnac phase accumulate unchecked, the system applies a digital phase ramp that continually cancels the shift. By driving the interferometer back to its null point, the feedback loop keeps the output linear, stable, and immune to drift. The measured rotation rate is then encoded in the feedback signal itself—a clever inversion that transforms fragility into robustness.

Yet even feedback isn’t the whole story; thermal and mechanical realities still test the limits of precision.

Thermal and mechanical dynamics: Shupe effect vs. mechanical dither

Beyond optical stability, real-world gyroscopes must withstand environmental and physical constraints that threaten measurement accuracy. In fiber optic gyroscopes, asymmetric temperature gradients across the coil cause localized thermal expansion and refractive index shifts—an error known as the Shupe Effect that generates false rotation signals.

To eliminate this without moving parts, engineers utilize quadrupolar winding patterns, placing symmetrical sections of fiber side-by-side, so counter-propagating light beams experience identical thermal fluctuations.

By contrast, ring laser gyroscopes (RLGs), another class of optical gyros, face a mechanical challenge called lock-in, where backscattering from internal mirrors causes counter-propagating laser beams to synchronize at low rotation rates, creating a dead zone.

To bypass lock-in, RLGs rely on piezo-driven motors to mechanically “dither” (vibrate) the gyro thousands of times per second. While effective, this mechanical movement introduces wear, acoustic noise, and complexity—highlighting the key advantage of the FOG’s purely solid-state design.

FOG vs. the world: MEMS and RLGs

Gyroscopes come in three dominant flavors, each tuned to a different mission profile. MEMS gyros are the cheapest and most compact, finding their way into smartphones, drones, and consumer gadgets. Their bias stability is modest, and while they’re perfect for short‑term orientation, they drift too quickly for long‑duration navigation.

Fiber optic gyros or FOGs occupy the middle ground. They cost more than MEMS but deliver far higher stability and an extraordinary lifespan, thanks to their solid‑state design with no moving parts or gas reservoirs to degrade. This makes them ideal for tactical missiles, subsea navigation, and autonomous vehicles where reliability and precision matter more than price.

At the high end sit ring laser gyros or RLGs. They achieve ultra‑high stability, rivaling the best FOGs, but at a steep cost. Their reliance on helium‑neon gas means eventual degradation, yet they remain the gold standard for submarines and commercial aircraft, where absolute precision justifies the expense.

Figure 3 Honeywell GG1320 ring laser gyro delivers precise rotation sensing, enabling navigation and stabilizing aerospace, marine, and defense platforms. Source: Honeywell Aerospace

Variants of the fiber optic gyroscope

From the classic interferometric FOG (IFOG) to newer digital FOGs (DFOGs) and integrated gyroscope systems (IGS), the architecture has steadily evolved while retaining the same Sagnac foundation.

The IFOG remains the workhorse, using long coils of polarization‑maintaining (PM) fiber to preserve phase integrity and deliver tactical‑grade accuracy. DFOGs build on this by embedding digital feedback and advanced signal processing, often with quadrupolar winding patterns of PM fiber to suppress thermal drift, extending dynamic range and robustness. Resonant and hybrid designs push sensitivity further, employing ultra‑low‑loss PM fiber loops or specialty coated fibers, though they demand complex stabilization.

Meanwhile, integrated gyroscope systems and chip‑scale photonic FOGs are beginning to replace kilometers of fiber with silicon photonic waveguides, aiming to replicate PM fiber performance in miniature. Across all these variants, the choice of fiber is decisive: single‑mode fiber may suffice for low‑cost experiments, but only polarization‑maintaining fiber—and its emerging photonic equivalents—ensures the stability needed for navigation‑grade gyroscopes.

Performance metrics and outputs

Fiber optic gyroscopes are defined by their precision metrics. Angular random walk (ARW) sets the short‑term noise floor, and FOGs achieve values far lower than MEMS, translating into smoother orientation data. Bias stability—the long‑term drift of the zero point—remains their hallmark, often holding steady for years without recalibration. Their solid‑state design makes them inherently shock‑ and vibration‑proof, with no moving parts to resonate or wear.

Input range spans from ultra‑low rotation rates to thousands of degrees per second, while bandwidth supports rapid maneuvers without lag. Magnetic response is negligible compared to MEMS, since light rather than moving charges carries the signal.

Start‑up time is typically short, with modern digital FOGs locking in within seconds. On the output side, legacy analog formats provide voltage‑scaled signals, while digital FOGs deliver direct digital outputs, ensuring seamless integration with navigation computers and minimizing conversion errors.

Output conventions

Beyond raw analog and digital rate formats, commercial FOGs often provide standardized outputs such as CLOCK OUT and DELTA OUT. CLOCK OUT serves as a timing reference, aligning the gyro’s data stream with system processors, while DELTA OUT delivers the incremental angle (Δθ) per sampling interval. These conventions simplify integration into inertial navigation systems, where synchronized timing and accumulated angle increments are essential for accurate position and attitude computation.

Commercial coil configurations

In commercial interferometric FOGs, the fiber coil is engineered with meticulous care, since its geometry directly governs thermal stability and bias drift. Wet coils embed the fiber in resin or epoxy, damping vibration and stabilizing temperature, while dry coils leave the fiber free‑wound with mechanical cushioning, allowing natural expansion but demanding tighter control of stress.

Winding patterns are equally decisive: the original quadrupole winding cancels first‑order thermal gradients by alternating coil segments, while the modified quadrupole refines this symmetry to suppress residual Shupe errors. More advanced schemes such as time‑delay fiber (TDF) winding distribute the optical path to average out environmental fluctuations, further reducing bias instability.

Octupolar and higher‑order windings extend these principles, trading complexity for incremental gains in stability. Together, the choice of wet vs. dry construction and the winding geometry transforms a simple fiber coil into a rugged, navigation‑grade sensor core.

Coil mounting styles

Beyond wet and dry construction, fiber coils are packaged in different mechanical styles. Flanged coils can be built wet or dry, clamped between rigid end plates for stability. Hubbed coils are wound around a central hub and are typically resin‑embedded (wet only) to lock the fiber in place.

Freestanding coils dispense with rigid supports, relying on resin encapsulation (wet only) to maintain geometry. These mounting choices balance mechanical ruggedness, thermal expansion control, and ease of integration into navigation‑grade assemblies.

Figure 4 Standard freestanding fiber gyro coils showcase the physical construction and reel structure used in closed-loop FOG systems. Source: Yoec

Axis configurations and INS integration

Commercial FOGs are offered in single‑axis modules for specialized sensing, or multi‑axis assemblies—typically three orthogonal coils—to deliver full 3D rotation data. These triads form the angular‑rate backbone of an inertial navigation system (INS), where FOGs are paired with accelerometers to compute position and altitude without GPS.

Single‑axis FOGs find use in stabilization platforms and precision pointing, while double‑ and triple‑axis units dominate navigation, guidance, and autonomous vehicle control. The modularity of coil design allows vendors to scale from compact one‑axis sensors to rugged INS‑grade packages, ensuring that the same interferometric principle can serve both niche instrumentation and mission‑critical navigation.

Non‑ITAR FOGs

Vendors often distinguish between ITAR‑restricted gyroscopes and non‑ITAR models. International Traffic in Arms Regulations (ITAR) governs military‑grade hardware and technical data, limiting export and use.

By contrast, non‑ITAR FOGs are commercial versions cleared for civilian applications—aviation, marine navigation, robotics, and autonomous vehicles—without the licensing hurdles. They still deliver navigation‑grade performance, but are designed for open markets where accessibility and integration matter more than classified specifications.

Deployment and future directions

Fiber optic gyroscopes have already proven themselves in submarines, tactical missiles, aircraft, and autonomous vehicles—anywhere long‑term stability and ruggedness matter more than cost. Their mean time between failures often exceeds decades, a testament to solid‑state reliability.

While FOGs occupy the mid‑tier between low‑cost MEMS and high‑end RLGs, research is pushing further: silicon photonics promises chip‑scale integration, and quantum gyroscopes based on cold atoms may one day bypass optical fibers altogether. Together, these paths suggest that navigation without GPS will only grow more precise and more accessible.

The elegance of the fiber optic gyroscope lies not only in the Sagnac physics but in the way engineers tame optical noise, stabilized polarization, and perfected feedback loops to build a sensor with zero moving parts. What results is a navigation instrument immune to wear, capable of microradian precision trusted in the harshest tactical environments.

Looking forward, the same principles are migrating into silicon photonics. Chip‑scale integrated optics promise to deliver FOG‑like precision in miniature packages, opening the door to navigation systems that are lighter, cheaper, and more ubiquitous. The journey from spinning bearings to spinning light may soon culminate in spinning photons on a chip—bringing Einstein’s relativity into everyday devices.

For makers, engineers, and serious tinkerers, the challenge is clear: don’t just admire the elegance—experiment with it. Build your own interferometer, wrestle with coherence noise, and see how far you can push solid‑state precision. The fiber optic gyroscope is more than a marvel; it’s an open invitation to innovate.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Modeling the MEMS gyroscope
• Gyroscope Accuracy Beats MEMS
• InvenSense spins first pitch-and-yaw MEMS gyro
• CEA-Leti’s NEMS-Based Gyroscope Operates at 50 kHz
• BAW gyroscope sensors transform inertial MEMS apps

The post Fiber optic gyroscopes: Elegant engineering of modern inertial navigation appeared first on EDN.

The increased sophistication and performance expectation of the automotive drive train, especially in electric vehicles (EVs) and to a lesser extent in hybrid and even internal combustion engine (ICE) vehicles, is accelerating the usual push/pull improvement effect between advanced components and their end products.

I recently saw a press release from Texas Instruments for the RES80A-Q1, a 50-MΩ precision-resistive divider for use at extremely high voltages up to 2,000 V DC (Figure 1). These simple matched-resistor dividers are used to ratiometrically divide a high voltage down to a much lower voltage, so it can be measured with conventional electronic circuitry to give the vehicle battery management system (BMS) the data it requires.

My initial thought was that this part must be targeted toward the traditional uses of these components such as X-ray machines or high-voltage physics projects and their electric fields. But then I saw the part was qualified to AEC-Q200—the automotive-grade rating for passive components—and the primary use for this resistive divider is in high-voltage EV battery packs.

Figure 1 The RES80A-Q1 50-MΩ resistive divider has two precisely ratioed resistors in series with a center tap. It’s used for dividing an input voltage down to a more-manageable value (below). Source: Texas Instruments

While it’s conceptually a simple component, its actual fabrication is sophisticated, and its specifications are very tight. It’s built on high-performance analog-wafer process with an insulative silicon dioxide (SiO2) layer that encapsulates the resistors and enables sustained use at up to 2,000 V DC. The tiny 8-pin SOIC package has a nominal body size 7.5 mm × 5.85 mm; but it also features creepage and clearance distances of at least 8.5 mm between its high-voltage and low-voltage pins, as required by various safety mandates.

It features high ratio-matching precision, with the measured ratio of each divider within ±0.1% (maximum) of the nominal. Figure 2 shows the standard high-voltage to low-voltage (RHV:RLV) ratios offered.

Figure 2 The AEC-200 qualified passive component is available with different pre-set ratios to match the specifics of voltage division of the source. Source: Texas Instruments

This precision is maintained over the specified temperature range and aging with a cumulative drift of only ±0.2% (max). Therefore, the lifetime tolerance of an uncalibrated RES80A-Q1 remains within a ±0.3% (max) envelope.

In short, the performance of this apparently simple ratiometric device is impressive, and beyond what I thought a mass-market application such as automotive-voltage measurement would require. As a standard catalog item, it’s available to automobile subsystem OEMs, but also to the broader market.

We’ve seen this spillover scenario many times, especially with technology advances that occur as component vendors introduce new products which are useful to other, unrelated applications. As standard catalog parts, they can be “picked up” by non-automotive designs to simplify their sourcing challenges while avoiding the need for a low-volume part that may need to be custom fabricated and evaluated at considerable cost in time and money.

But what about the automotive end user?

While the off-the-shelf availability of specialized components such as this resistive divider is a good thing, there’s also downside to the increased sophistication of cars that does concern me. On one side, modern feature-laden cars are generally more reliable than cars of a few decades ago. According to the Kelly Blue Book, the average U.S. car is now over 12 years old. Though I am usually skeptical of such statistics as they are often based on extrapolations and “guesstimates”, the data on cars is very robust and accurate.

Industry “watchers” attribute this longevity to two factors. First, cars are better built and generally more reliable. Second, new cars are so expensive that in many cases, it pays to keep fixing them for more years.

However, their increased complexity and enhancement features, and the advanced components and circuitry these require, make it much harder to diagnose problems and more costly to fix them. Now, many replacement parts are highly specific to a specific vehicle’s make, model, and year.

It wasn’t always this way. Decades ago, an auto vendor used many parts in common across individual models; sometimes they were common even across brands (think fuses). For example, the car headlights were limited by regulations to just a few sizes and types; you could get a replacement at any auto-supply store and replace it in a few minutes. Now they are integrated into the car body and are unique to each make, model, and year, but do offer improved illumination along with greatly reduced drag (Figure 3).

 

Figure 3 Those were the days: Until the later 1900s, automobile headlights were standardized with just a few available sizes and form factors. Things have changed now, as the headlight assembly is an integral, structural part of the car. Sources: Pinterest and Etsy

Today’s repair-related supply chain is more extended and fragile: my low-mileage 2019 car was off the road for two months while I waited for a replacement electronic door-lock module. There were also hard-to-find issues related to module vampire/parasitic drain, killing the battery.

In the case of these high-performance passive components for cars, do their performance benefits outweigh the long-term owner-centric challenges they also bring? That’s an unresolved question and is different for different car owners and their specific circumstances.

Have you ever used a specialized passive AEC-Q200 part in a non-automotive design? Why did you choose that route? Was the choice worthwhile in the end, or did unexpected surprises with respect to performance, availability, cost, or support make you reconsider that decision?

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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The post Automotive demands driving passive components to extreme performance appeared first on EDN.

Hard science data is typically no barrier to enduring belief for the conspiracy theorist. Nevertheless, this engineer tries, tries again.

“As I went to Bonner, I met a pig without a wig, upon my word and honour.”
-Mother Goose rhyme

Upon my own word and honor, I once met an engineer, a living and breathing, bipedal, mammalian being, seemingly well educated in the sciences, who insisted that the entire Apollo space program was a fake and that nobody had ever actually landed on the moon. 

I told him how when Armstrong and Aldrin were at Tranquility Base, they installed a set of corner reflectors that are still there and which are still operational. NASA and other groups send pulsed laser beams to the reflectors, which bounce those beams right back from whence they came. Measurements of the round-trip transit times tell how far away the reflectors are, and thus how far away the moon is, to extreme accuracy.

The reflector illustration is seen in Figure 1, a screen shot from a Neill deGrasse Tyson clip on YouTube. Notice the landing legs of the Lunar Excursion Module (LEM) to the image’s upper left.

Figure 1 The enduring presence of corner reflectors on the Moon also validates a past human presence there.

Much to my further astonishment, my colleague never even heard of corner reflectors. Let’s have a look.

Just for jollies, I made a corner reflector of my own out of some aluminum foil. I photographed the thing using a supplemental flash from lots of different orientations. The flash reflection was always returned right back at me as well as to the camera, no matter the crudeness of my handmade foil arrangement (Figure 2).

Figure 2 Flash illuminations returned by a homemade corner reflector mimic the behavior of those on the Moon.

The underlying geometry can be illustrated in a two-dimensional sketch (Figure 3).

Figure 3 Geometry illustrates the underlying principles of a corner reflector’s function.

Clearly, these reflectors were put there by human beings, not by little green men or bug-eyed monsters (Figure 4), so this guy started thinking that maybe the Apollo program was for real after all.

Figure 4 An example bug-eyed monster, this one Mars-originated, but often Moon-inhabiting (and Bugs Bunny-bothering).

That said, however, he was still not one-hundred percent certain of the Apollo program’s existence. And he was conversely still quite confident in the concepts set forth in Erich von Däniken’s “Chariots of the Gods?”, because space alien visitors were an acceptable and logical explanation for so many other things…

Sigh.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Apollo 11 corner reflector appeared first on EDN.

Sometimes thinking like a geek pays off. Especially when you’re dealing with overheated Judge Judy fanatics.

A recurring problem at the transmitter site of the television station I worked at was the cause of no small amount of labor and expense. Periodically the building’s cooling system failed, which is a bit of an emergency during hot weather, especially as it could cause the transmitter to overheat and shut down. Lots of Judge Judy fans out there wouldn’t be happy. And they could be brutal with their criticism.

Do you have a memorable experience solving an engineering problem at work or in your spare time? Tell us your Tale

The HVAC system used a two-stage heat exchanger, with three fans. The fans draw air past the hot condenser coils and fins and exhaust the heated air out of the top of the unit. When the cooling load is light, the outer two fans run, and the center fan is turned off. When the load is heavy, or the outside air temperature is high, all three fans run.

Every year or so the center motor would burn out, shorting one phase of 480V to the motor’s case. Fortunately, the transmitter site was wired as 480 volts delta. A delta system can withstand a short of a single phase to ground, something a wye system cannot do. As Figure 1 shows, the main electrical panel at the site had lamps from each phase to ground. If a phase was shorted, its lamp would go out and we’d know we had a problem.

Figure 1 A delta system can withstand a short of a single phase to ground, something a wye system cannot do.

The cause of the burnouts was well-known. When the HVAC system has only two fans running, the two outer fans are pulling air not only through the fins, but down through the center fan as well (Figure 2). This causes the idle motor and fan to run backwards as the air flow is reversed. The fan could get up a pretty good head of steam in a short time.

Figure 2 This HVAC system doesn’t include a damper.

Then, when the center motor is called to start, it has more than its usual start-up inertia to overcome, and in fighting the reversed magnetic field, produces a high back EMF. This increases the voltage stress across the motor’s windings as well as the current through them. After enough of this abuse, one of the windings will give up the ghost and short to the motor’s case.

Over the years we replaced a good number of motors, before and during my time at the station. On one of these occasions, I was up on the roof with our HVAC contractor, discussing the problem (and the Red Sox, as this was Boston and such conversation is mandatory). One thought was to install sheet-metal walls to divide the interior into thirds, isolating the center section, but this was not at all an easy project.

Then my inner geek kicked in. Just as a carpenter might think there’s no problem that can’t be solved with a good sized hammer and nails, or a handyman with duct tape, I tend to think in terms of electronics. So it occurred to me that what we needed was an “air-diode.” Let the air flow up and out, but not down and in.

Believe me, I felt like an idiot a moment later when I realized that such a thing already exists in a very simple device: a damper. It’s just a group of hinged sheet metal plates that, when mounted horizontally, will open when the fan is blowing and allow air to flow, and close via gravity when the fan is not blowing, blocking the air flow (Figure 3). Lucky for me our HVAC man hadn’t thought of it either, so I didn’t feel so bad. And he agreed that it was a good idea. He got a damper of the right size, installed it, and never had to return to replace a burned out motor again.

Figure 3 This HVAC system includes a damper, which can be either open or closed.

Incidentally, I’ve never understood the reasoning behind the wide-open cavity in the fan units. Drawing outside air down through the idle fan means an equivalent amount of air is not being drawn through the fins, which greatly reduces cooling efficiency. I know this from unfortunate experience, when I once accidentally left an access panel open on a heat exchanger (at a different TV station). The result was an overheated and shut down TV transmitter (see earlier mention of Judge Judy fans).

Robert Yankowitz retired as Chief Engineer at a television station in Boston, Massachusetts, where he had worked for 23 years.  Prior to that, he worked for 15 years at a station in Providence, Rhode Island.

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The post Not all diodes use electrons appeared first on EDN.

A speedier LAN “freeway” is of no benefit if “vehicles” on it are still molasses slow. Fortunately, this engineer’s curiosity is matched by upgrades both available used and already in inventory.

As part of my pending infrastructure upgrade, one of the key LAN clients that I want to make sure is accessible as speedily as possible, as well as generally performing as optimally as possible, is my longstanding-use quad-HDD QNAP TS-453Be NAS:

The TS-453Be has dual integrated 1 GbE wired interfaces, only one of which I’m currently using due to my current switch’s available port count limitations.

That said, I’ve long been tempted to add an active splitter to the mix, as the NAS’s Linux O/S foundation supports two different multi-LAN interface merging options: specialized Port Trunking, i.e., LACP (Link Aggregation Control Protocol), which necessitates the use of a high-end managed switch, and the more general-purpose SMB Multichannel alternative approach.

However, since I was planning on more broadly moving to a primary switch that included multiple 10G SFP+ cages, each optionally configurable as a 10 GbE port via an Ethernet adapter module, I decided to instead “go for the gusto” and use a PCIe add-in board to upgrade the TS-453Be to use a single 10 GbE interface. QNAP sells such a card, the QXG10G1T, which has a $139 MSRP although, due to supply constraints, many retailers currently sell it for $200 or more (AQUANTIA, the board’s network controller supplier, was acquired by Marvell seven years ago).

Bracket barrier

Instead, however, and after stumbling across an encouraging Reddit thread, I (at least initially) decided to alternatively go with a much less expensive generic AQUANTIA AQC107-based add-in card sourced from Walmart’s website.

The Reddit thread discussion suggested that there was no difference between ones like it and the pricier branded card, at least from a software driver standpoint. QNAP hadn’t hard-coded a specific identifier code into the card’s firmware, for example, and therefore hadn’t customized the Linux build it was using to recognize only that code as valid. This was a refreshing change from the usual norm taken by some SFP-supportive networking equipment suppliers, for example.

But when the board arrived, I realized that I still couldn’t let QNAP off the “proprietary” hook scot-free. The earlier QXG10G1T stock photos showed the board with only its preinstalled low-profile bracket, variants of which I’d also come across in the past with low-profile graphics cards, for example.

 

The QNAP product page also mentioned the inclusion of a full-height conventional bracket. And it further referenced an also-bundled “specialized (for selected QNAP NAS) bracket”, photos of all of which I happened to find included with a used-board eBay listing I came across.

The latter bracket, unfortunately, is the one that the QNAP TS-453Be calls for. Unsurprisingly, it was not included with the generic AQC107-based add-in card I’d bought, or any other I could find.

I also couldn’t find any means of purchasing the proprietary flat low-profile bracket from QNAP directly. Perhaps obviously, I assume that the company would prefer that I instead buy the entire kit from it.

Investigation prior to capitulation

I could hack away at the standard low-profile bracket to jerry-rig it into place, as I belatedly realized upon re-read that the original Reddit thread originator had done (I’d originally misinterpreted that he’d only had the full-height bracket in his possession). Or, I suppose, I could 3D-print one. What I confess I just ended up doing instead was bailing and buying that used board I’d found on eBay, which thankfully works fine and still saved me a notable amount of coin versus the MSRP, not to mention the subsequent (and current) further marked-up prices (the screenshot still reports 1 GbE connectivity because of the legacy switch on the other cable end).

I’ve kept the generic add-in card, too, for use in adding 10 GbE support to future Macs, Hackintoshes and/or PCs, along with any more amenable NASs that might come into my possession in the future. And, prior to settling on the used QNAP-branded card, I temporarily installed the generic one in the NAS after first removing its mounting bracket entirely, to personally confirm what I’d already read re its claimed software compatibility.

Here’s where the add-in card goes.

Cue irony; the dimple on the included standard low-profile bracket’s 90° bent end exactly matches the location of the drilled hole in the (flat) cover plate, suggestive of a likely chassis location match were I to drill a hole at the dimple, too. The problem, of course, is that even if I could cleanly un-bend that end, it’d still protrude beyond the remainder of the bracket’s edge. It wouldn’t fit in the chassis unless I also hacksawed or otherwise dealt with the bracket excess.

Absent the bracket, the add-in card is fully functional, albeit tenuously so from a mechanical stability (therefore also electrical connectivity) perspective.

The only quirk I came across, which ironically also affects the QNAP-branded board, is that the front panel LED only activity-illuminates when the integrated 1 GbE facilities are in use, not those of the 10 GbE add-in card.

Other networking options

What about the NAS’s five integrated USB 3.2 Gen 1 (5 Gbps) ports (one front, four back)? Instead of using a full-blown add-in card, could I instead connect up one or even a few (for multi-LAN interface merging purposes) 2.5 GbE or 5 GbE USB adapters? Yes, it turns out, but with some qualifiers. QNAP once sold a branded 5 GbE adapter, the QNA-UC5G1T, based on an AQUANTIA-now-Marvell AQC111U controller.

But per the QNAP website, it’s discontinued, with retailer stock also depleted. It also only works with Intel x86-based QNAP NASs, not Arm-based models such as my TS-231K and TS-328 (as a backup plan, they both at least also have dual integrated 1 GbE ports). There’s no O/S support for Port Trunking multi-port merging, only for SMB Multichannel. And the only third-party AQC111U-based adapters I’ve come across, from Sabrent, Startech and TRENDnet, are also discontinued.

Things are a bit more encouraging on the 2.5 GbE front, however. QNAP doesn’t (and as far as I can tell, never did) sell a branded one, but I’ve successfully tested several third-party adapters based on Realtek RTL8156 network controllers (LAN-disconnected in the following image, albeit still system-recognized, which was my point in including the screenshot in the first place).

Again, the compatibility is x86-only; whatever Arm-compiled Linux build QNAP is using doesn’t seem to bundle the necessary driver support. And per Reddit chatter, it seems to be somewhat hit-and-miss as to whether a given adapter can be reliably powered from a given NAS directly versus requiring a powered-hub intermediary. But for those of you out there with x86-based NASs (or potentially even Arm-based NASs from other manufacturers using other operating system foundations) that don’t have add-in card support, it’s potentially better than nothing.

Volatile and nonvolatile memory enhancements

Another TS-453Be update I’ve recently done wasn’t motivated by network upgrades, per se. Instead, it was predominantly fueled by fundamental curiosity. As I’d mentioned back in late 2020, the NAS arrived with 2 GBytes of DDR3 SDRAM installed as a single SoDIMM, which I promptly updated to 8 GBytes total, albeit not at the highest possible hardware-supported speed bin given that I’d used two spare SoDIMMs I already had on-hand versus buying others.

I mentioned at the time that “some users report being able to run up to 16 GBytes total, but success is seemingly hit-and-miss, as is longevity, and since I don’t want to deal with stored data corruption I “passed” on this experiment.” Well, even though the Celeron J3455 isn’t (officially, at least) Windows 11-compatible, not to mention the lack of a system TPM (trusted platform module), Microsoft has now extended Windows 10 support for a second straight year, so far.

I suspect this may not be the final end-of support postponement, considering stubbornly high replacement-system building block prices. I’m already running Roon Server using Docker, with other containerized apps possible in the future. And with support extended, I may put virtualized Win10 back on the TS-453Be, too. My earlier test-drive had been successful albeit slow; I later uninstalled it due to the sizeable necessary HDD “footprint”. Doubling onboard memory should help performance in all these cases, due to resultant decreased virtual memory thrash. So while the NAS was open, I also dropped two 8 GByte SoDIMMs in. All’s stable so far, I’m happy to say.

And speaking of overall performance, while the four HDDs inside the NAS are enterprise 7,200 RPM variants (Hitachi Global Storage Technologies’, now Western Digital’s, Ultrastar 7K4000 HUS724040ALE640), they are HDDs. Even configured as RAID 5, I suspect their inherent random access latencies will become increasingly intolerable once the network-access latency between them and the LAN client(s) they’re communicating with are diminished as potential bottlenecks.

To wit, I have another QNAP add-in card on order, which I plan to at least temporarily in-system exchange for the currently installed QXG10G1T. It’s the QM2-2P10G1TB, which also comes with three bracket options (at least I hope this used one does, otherwise I’ll ship it back posthaste).

Versus the QM2-2P-244A I’d mentioned back in late 2020, this one includes support for dual M.2 NVMe SSDs and 10 GbE connectivity, as noted in the following conceptual cutaway.

To clarify upfront, I won’t be using the flash memory modules as “raw” storage. Instead, I’ll leverage QTier to harness them as a read/write cache. You can tell that the associated QNAP technology page is dated because it claims you can “take advantage of declining SSD prices.” Fortunately, I still have a few M.2 NVMe spares lying around from the pre-constraint days.

To be clear upfront, I’m not expecting anything dramatic improvement-wise from a performance perspective. Although the add-in card has a PCIe Gen3 x8 interface, the NAS connector I’ll be plugging it into only implements PCIe Gen2 x2, traffic-shared between the network controller and two SSDs, all factors leading to yet another potential bottleneck. Still, the comparative results should be interesting.

Once I get both the QNAP NAS and its supportive LAN infrastructure upgraded, I’ll run some benchmark tests and report back the results. Until then, I as-always welcome your thoughts in the comments on what I’ve discussed thus far!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post NAS upgrades: Proprietary lockouts and surmounts appeared first on EDN.

pSemi offers the PE566212 and PE566213 2.4-GHz SOI front-end modules (FEMs) for Bluetooth, Zigbee, and Thread applications. Each module integrates a power amplifier, low-noise amplifier, and RF switch in a compact 1.8×1.8×0.63-mm LGA package, simplifying RF design. Applications include smart home devices, wireless audio, wearables, and sensing systems.

The FEMs provide transmit output power up to +20 dBm, a receive noise figure of 1.8 dB at 13 dB of gain, and typical bypass-path loss of 0.8 dB. According to pSemi, the FEMs offer 5 to 10 times the range of a standalone SoC. Based on pSemi’s UltraCMOS+ SOI process, they offer a highly integrated silicon-based alternative to GaAs- and SiGe-based front ends.

The PE566212 supports Bluetooth Basic Data Rate (BDR) and Bluetooth Low Energy (BLE), with 22.5 dB of transmit digital gain control in 1.5-dB steps. The PE566213 adds Bluetooth Enhanced Data Rate (EDR) support at up to +11.5 dBm and offers 15 dB of transmit digital gain control in 1-dB steps. Applications include smart home devices, wireless audio, wearables, and sensing systems.

The front-end modules are available now, along with corresponding evaluation boards.

PE566212 product page 

PE566213 product page

pSemi

The post Integrated FEMs ease 2.4-GHz RF design appeared first on EDN.

A liquid-cooling cold plate, Frore’s LiquidJet Diamond integrates a diamond heat spreader to cool hotspots in high-power-density AI GPUs. Its 3D, short-loop, multistage cooling architecture can be customized to match a GPU’s power map, directing coolant to the hottest areas before cooling the rest of the GPU die, high-bandwidth memory (HBM), and other SoC chiplets.

Compared with conventional skived cold plates, LiquidJet Diamond achieves up to 75% higher heat-transfer efficiency and more than 150% higher maximum power density. Frore also claims 16–22°C lower GPU temperatures and 30–35% higher AI tokens-per-watt efficiency.

Beyond thermal performance and hotspot management, LiquidJet Diamond offers a seamless drop-in upgrade for hyperscale data centers. Frore says its manufacturing process combines semiconductor-fabrication precision with the production capacity needed to meet the quality and volume requirements of AI data center deployments.

LiquidJet Diamond product page 

Frore Systems 

The post Diamond spreader tames AI GPU hotspots appeared first on EDN.

Aetina’s AIE-KT78/68 edge AI systems are powered by NVIDIA Jetson Thor platforms featuring the Blackwell GPU architecture for deterministic industrial control. Targeting collaborative robots (cobots), humanoid robots, and autonomous machines, these compact systems run multimodal AI models locally, reducing reliance on cloud processing and associated latency. Supported workloads include generative AI, large language models (LLMs), vision-language models (VLMs), and vision-language-action models (VLAs).

The AIE-KT78 uses the Jetson T5000 system-on-module, with 128 GB of LPDDR5X memory on a 256-bit interface and up to 2,070 FP4 TFLOPS of AI compute performance. The AIE-KT68 features the Jetson T4000 system-on-module, with 64 GB of LPDDR5X memory on the same interface and up to 1,200 FP4 TFLOPS.

Each system provides QSFP28 connectivity with up to 4×25-Gbps bandwidth, dual 10GbE RJ45 ports, and support for up to eight GMSL2 camera inputs to handle data from cameras, LiDAR, radar, and other sensors. A dedicated 1GbE RJ45 EtherCAT port operates as an independent EtherCAT master, synchronizing motors, joints, sensors, and actuators for deterministic control.

Both edge AI platforms run Linux with the full NVIDIA AI software stack.

AIE-KT78/68 product page 

Aetina

The post Systems reduce latency in edge AI automation appeared first on EDN.

Renesas Electronics has launched its first family of 100-V enhancement-mode (E-mode) discrete GaN power transistors. The company says the RTP100E005G1FL, RTP100E2P6G1FL, RTP100E1P8G1FL-DSC and RTP100E1P2G1FL-DSC low-voltage GaN FETs achieve industry-leading hard- and soft-switching figure-of-merit (FOM). They deliver up to 35% lower hard-switching FOM and up to 63% lower soft-switching FOM than comparable GaN devices.

Offered in FCLGA packages that maintain a silicon-compatible footprint, the GaN FETs let designers migrate from silicon MOSFET layouts without significant PCB rework. The RTP100E005G1FL and RTP100E2P6G1FL have typical on-resistance of 5 mΩ and 2.6 mΩ, respectively. The dual-side-cooled RTP100E1P8G1FL-DSC and RTP100E1P2G1FL-DSC have on-resistance of 1.8 mΩ and 1.2 mΩ, respectively. Depending on application requirements and power-conversion architecture, the transistors can achieve up to 40–70% lower switching losses and up to twice the power density at the system level.

The 100-V family targets high-power-density applications, including AI data centers, humanoid robotics, and factory automation. Package options and a wide range of on-resistance values allow the transistors to address different power levels and applications, including synchronous rectification, multiphase buck conversion, and industrial motor drives.

The new low-voltage GaN power transistors are available now, along with corresponding evaluation boards.

Renesas Electronics 

The post 100-V GaN FETs lower switching FOM appeared first on EDN.

METCASE has redesigned its COMBIMET 19-in. rack-mount enclosures to provide greater rigidity and more usable panel space. The aluminum cases are suitable for networking and communications equipment, industrial computers, sound and studio systems, laboratory instruments, and industrial control applications.

The COMBIMET range now offers 68 standard model, size, and color permutations. Improved tabs create stronger, more reliable connections between enclosure components, while enlarged hidden apertures behind the front and rear panels allow more room for displays, controls, switches, connectors, and ventilation. Standard case heights range from 1U to 6U, with depths of 10.43 in., 14.37 in., and 24.00 in.

Enclosures have removable top, base, and rear panels for easy access to electronics. Both the top and base come with or without vents as standard. Units are available in black or light gray. COMBIMET enclosures can also be customized in size, panel design, color, finish, and graphics to meet specific application requirements.

Sales inquiries can be directed to sales@metcaseusa.com.

COMBIMET product page

METCASE

The post Updated rack enclosures offer flexible design options appeared first on EDN.

This silly simple circuit cancels out potentially serious digital potentiometer zero- and full-scale errors.

Everybody (well, most everybody) knows that digipots tend to be more accurate when used as variable voltage dividers (i.e., in potentiometer mode) and not so much when used as variable resistors (in rheostat mode). In pot mode, many error-promoting effects like resistance element tolerances and temperature coefficients cancel out (well, mostly). But even when pots are used as actual pots, some small non-idealities might still sneak by. One (okay, two) of these are zero- and full-scale ratio errors.

Figure 1 shows a simple Dpot output buffer that should work fine when the error terms are small.

Figure 1 Dpot U1 runs in straightforward voltage-division potentiometer mode with unity-gain buffer A1 providing isolation from output loading. So everything should be nicely ideal with Vsigout = Vsigin(Rwa/Rba).

Unfortunately, sometimes the errors are not so small. For example, if U1 were an 8-bit (1/256) resolution MAX5451, then typical values for full-scale and zero-scale errors are listed in its datasheet as 8lsb = 3.1%, which makes the actual achieved accuracy look more like only 5 bits instead of the claimed 8.

Vsigout = Vsigin((Rwa/Rba)(1 – Fullscale) + (Rwb/Rba)(Zeroscale))
Fullscale = Zeroscale = 0.031 (typical)
Vsigout = Vsigin(Rwa/Rba) +/-3%

In any precision-critical application, those 3% offsets are likely to be unacceptable. Fortunately, Figure 2 suggests how a simple 3-resistor error-nulling fix is possible.

Figure 2 If R1 = R2 x (scale error) then the errors disappear and Vsigout = Vsigin(Rwa/Rba).

Here’s how it works. Note that, for best performance, R2 and R3 should equal each other to ~0.1% and R1 should be adjusted equal to R1 = ScaleErrorPercentage x R2. An easy way to accomplish this is as follows:

1. Adjust U1 to its maximum UP setting. Then Rwa = Rba.
2. Set SigIn = V+ – 100mV or so. The exact voltage isn’t critical; we’re just insuring that A1 won’t saturate.
3. Connect a sensitive voltmeter between SigIn and SigOut.
4. Adjust R1 to null the meter reading and force Vsigout = Vsigin.

Done.

In some applications, error cancellation might be good enough with R1 equal to a fixed value calculated from the datasheet figures, instead of needing post-assembly calibration. 31 kΩ, for example, would align with the MAX5451’s data.

Which might niftily null some non-negligible production costs.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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• Push to increase, decrease a digital potentiometer
• Synthesize precision bipolar Dpot rheostats

The post Nifty nulling of non-negligible dpot “scale” errors appeared first on EDN.

Apple branding is front and center in the company’s resurrected smart home “push”. Although broader ecosystem compatibility is also feasible, you’d never know it from the messaging.

Within my 2024 CES coverage, I devoted a section to the industry-developed Matter smart home interoperability standard, which had originated in December 2019, as well as to the associated Thread wireless protocol. I was not encouraged by the then-current industry-adoption status, nor with the implementation robustness of what few implementations did exist, although I clung to a sliver of sooner-or-later “hope springs eternal” optimism.

The Matter smart home communication standard, built on the foundation of the Thread (based on Zigbee) wireless protocol, had no shortage of associated press releases and product demos in Las Vegas this week. But to date, its implementation has been underwhelming (leading to a scathing but spot-on recent diatribe from The Verge, among other pieces), both in comparison to its backers’ rosy projections and its true potential.

Not that any of this was a surprise to me, alas. Consider that the fundamental premise of Matter and Thread was to unite the now-fragmented smart home device ecosystem. If you’re an up-and-coming startup in the space, you love industry standards, because they lower your market-entry barriers versus larger, more established competitors. Conversely, if you’re one of those larger, more established suppliers, you love barriers to entry for your competitors.

Therefore the lukewarm-at-best (and more frequently, nonexistent or flat-out broken) embrace of Matter and Thread by legacy smart home technology and product suppliers. Suffice it to say that I’m skeptical about Matter and Thread’s long-term prospects, albeit only cautiously so. I just don’t know what it might take to break the logjam that understandably prevents competitors from working together, in spite of the reality that a rising tide often does end up lifting all boats…or if you prefer, it’s often better to get a slice of a large pie versus the entirety of a much smaller pie.

I’ve also appropriately scattered Matter and Thread mentions within a series of follow-up pieces, most notably my subsequent CES 2025 summary.

A year later, is the situation better? Not really, candidly. For a more in-depth supplier-sourced perspective, I encourage you to read Aalyia’s coverage of her time spent last week in Silicon Labs’ product suite, including an interview with Daniel Cooley, CTO of the company. Cooley is spot-on when he notes that “it is not unusual for standards adoption to progress slower than desired.” I’ve seen this same scenario play out plenty of times in the past, and Matter and Thread (assuming they eventually achieve widespread success) won’t be the last. I’m reminded, for example, of a quote attributed to Bill Gates, that “We always overestimate the change that will occur in the next two years and underestimate the change that will occur in the next 10.”

Cooley is also spot-on when he notes that Matter and Thread don’t necessarily need to go together; the Matter connectivity standard can alternatively use Ethernet (either wireless, aka Wi-Fi, or wired) for transport, along with Bluetooth Low Energy for initial device setup purposes. And granted, there has been at least some progress with both Matter (in particular) and Thread over the past year.

Version 1.4 of the Matter specification, announced last November, promises (quoting from Ars Technica’s coverage) “more device types, improvements for working across ecosystems [editor note: a concept called “Enhanced Multi-Admin”], and tools for managing battery backups, solar panels, and heat pumps”, for example. And at CES, the Connectivity Standards Alliance (CSA), which runs Matter, announced that Apple, Google, and Samsung will accept its certification results for their various “Works With” programs, too. That said, Amazon is notably absent from the CSA’s fast-track certification list

As I write these words in October 2026, we’re nearing two years since Matter 1.4’s release. The spec is now at the v1.6 level, with further enhancements including belated support for cameras and other sensors, along with energy management systems; you can read all the details at the associated Wikipedia entry. And speaking of Silicon Labs, for additional background info I’ll commend to your attention a still-relevant EDN article series published in early 2023 and authored by Rob Alexander, the company’s Principal Product Manager for Matter:

• How can device makers streamline Matter certification
• Why Matter matters
• How to connect existing smart home devices to Matter

That all said, industry adoption still seems like it’s stuck in first gear, that is assuming it’s (arguably) moving forward at all. And specific to Apple, whose re-engagement with the smart home market went public earlier today, Matter seems to be little more than a convenient alternative means of achieving baseline access to Apple’s otherwise proprietary HomeKit ecosystem without need to pony up for a paid license, as was timely exemplified by yesterday’s TP-Link smart plug teardown. Indicative of this seeming irrelevance, Matter and Thread are mentioned only in passing in Apple’s press release covering partnerships with other companies.

Enter the brand-new HomeView

If I had to bet, I’d wager that the HomeView smart home hub has been stuck in the ready-for-production queue for a while now, awaiting a sufficiently robust AI-enhanced successor to the legacy Siri assistant service. The outcome product’s industrial design hearkens back to both Amazon’s latest-generation Echo Show series, released a year ago, and to Apple’s own 2002-2004 era iMac G4 computer.

Shown here is the product variant with a down-firing woofer and two passive radiators built into the base; a wall-mountable version with only the two 7” full-range drivers in the display is also available. Both cost $299, run an app-restricted operating system also branded HomeView, functionally reminiscent of the Apple Watch UI and with an intriguing derivative-of-CarPlay angle, and are based on the Apple Silicon A18 SoC; the DRAM size wasn’t announced (although in the iPhone SoC variant, it’s 8 GBytes). And there’s zero mention of Matter or Thread anywhere in the press release this time, although on-site media inquiries revealed that HomeView can in fact act as both a Matter controller and bridge, along with as a Thread border router.

The above conceptual usage promo video is admittedly compelling (IMHO, at least); I’ll cover shortly the privacy ramifications and implementation of the multi-user scenario shown in it.

Evolutionary advancements also garner announcements

The HomePod mini smart speaker was originally introduced in October 2020, with more colors added to the product line mix a year later (and a teardown by yours truly ~1.5 years after that), so a redesign was arguably overdue. We didn’t get much today, but it was at least something. The SoC inside is now the S10, versus the prior S5, both originally intended for various Apple Watch generations and this time Apple Intelligence-capable.

Then there’s the Apple TV 4K, the newest generation of which candidly and bafflingly seems to have been cut off at the knees by its creator on day one. Its SoC upgrade from the A15 Bionic in the 2022 version of the device to the A18 affords it AI capabilities…but Apple’s also bringing Siri AI to both the 2022 and 2021 versions of the device (presumably predominantly cloud processing-based in these older, latter cases), so if you already own one, you’re good. The newest version embeds a three-microphone array that lets you shout at it from afar…but the remote controls included with legacy Apple TV 4K versions already embed a microphone.

And speaking of remote controls, the newest Apple TV 4K’s version embeds a speaker so you can prompt it to emit a locating sound if it’s stuck between the cushions of your sofa…but that same remote control can also be purchased separately for $59 for use with legacy Apple TV 4K versions. And did I mention that the newest Apple TV 4K costs $299, both a $50 uptick from the current price of its equivalent-capacity predecessor (which itself saw a $100 price increase from the original $149 earlier this year) and twice the price of Google’s TV Streamer 4K (which itself is notably pricier than equivalents from Roku, Walmart, and the like)? The only other notable benefit that the newest Apple TV 4K affords is integrated stereo and surround sound support, but actualizing this particular aspiration necessitates one or two matched pairs of only second-generation HomePods and/or HomePod minis.

Privacy-assuring redundancy

Wrapping up, the aspect of today’s announcements that I actually found most interesting was what Apple referred to at the end of the HomeView press release as “Private and Secure by Design” and I alluded to by the “Distributed identity validation” mention in this piece’s title.

If you haven’t yet seen the conceptual usage promo video I embedded earlier, please go back and watch it before continuing. Two things you’ll likely note straightaway are that:

• The HomeView device dynamically recognizes each user audibly by voice and/or visibly by face, and
• The HomeView device responded by dynamically tailoring its UI to each user’s preferences as well as more generally by replying using that user’s dataset.

Voice and face recognition are admittedly getting more responsive and reliable all the time, but they’re still not perfect. The latter’s not even an option with the camera-less HomePod mini v2 and 2026 iteration of the Apple TV 4K. And when you’re dealing with a user’s personal information—emails and text messages, calendar and contacts data, music and image libraries, etc.—you need to be absolutely sure of who you believe you’re interacting with, no matter that you’re presumably interacting with someone who lives in the home where the device is located.

That’s why personalized AI is only available on today’s announced devices for users who:

• Have registered Apple accounts, and
• Have unlocked FaceID-capable iPhones (translation: not the latest iPhone Duo, for example) and iPads logged into those accounts and either connected to the same Wi-Fi network as the HomeView, HomePod mini v2 and/or 2026-version Apple TV 4K, or recently on Wi-Fi but currently logged in via cellular (I’m assuming this latter exception handles cases where someone’s iPad or iPhone briefly drops Wi-Fi).

It also, of course, conveniently excludes Android smartphone and tablet owners and the like. Ahem.

That’s “all” I’ve got for you today. Rumors suggest that Apple’s got another event scheduled for two weeks from today. We’ll see; if so, I’ll see you back here then. For now, as always, I welcome your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Apple’s question for the developer: Are you up for an AI do-over?
• The 2025 WWDC: From Intel, Apple’s Nearly Free, and the New Interfaces Are…More Shiny?
• The 2024 WWDC: AI stands for Apple Intelligence, you see…
• Apple’s processor cadence: A pending stutter-step for improved long-term edge inference?

The post Apple heads Home: Distributed identity validation, and how much does Matter matter? appeared first on EDN.

Rising 5G adoption across industrial IoT, connected automotive, and smartphones is driving demand for application-specific 5G chips and modules. Chipmakers are increasingly targeting 5G-Advanced, satellite non-terrestrial network (NTN) connectivity, 5G fixed wireless access (FWA), and 5G New Radio (NR).

Many of these 5G chips and modules deliver 3rd Generation Partnership Project (3GPP) Release (R) 17 and R18 features with backward compatibility, and now support R19 for 5G-Advanced, while setting the stage for 6G development. Chipmakers also target 5G RedCap (reduced capability) for cost-effective 5G devices in IoT applications.

Many of these solutions focus on higher integration and flexibility options to simplify development as well as reduce power consumption and footprint. Part of the integration effort also includes AI to enhance performance.

Here is a sample of 10 5G chips and modules introduced over the past year with higher performance that drive 5G adoption across a range of applications.

Modems and platforms

Qualcomm Technologies Inc. launched the X105 5G Modem-RF, featuring the industry’s first 3GPP R19-ready modem, which lays the foundation for 6G development and testing. The Qualcomm X105 5G-Advanced platform improves data speeds and power efficiency while claiming breakthroughs in quad-band GNSS and integrated NR-NTN support. Its integrated fifth-generation AI processor uses agentic AI in the modem to detect, classify, and optimize data traffic types based on user scenarios.

Qualcomm claims several industry firsts with the X105 platform. It features the first 6-nm RF transceiver, achieving up to 30% lower power consumption and 15% smaller board footprint than the previous generation; the first quad-frequency (L1, L2, L5, L6) GNSS engine with integrated multi-constellation support; and improved location accuracy.

The 5G Modem-RF also supports video calling, video streaming, data, voice, and messaging over NR-NTN. It delivers 14.8-Gbits/s peak download speeds while achieving up to 13.2 Gbits/s with sub-6-GHz bands. Qualcomm said it addresses the need for more uplink capacity and data speeds, achieving 4.2-Gbits/s peak uplink throughput.

With an R19-ready architecture, the X105 Modem-RF system is designed to accelerate 5G-Advanced adoption across smartphones, FWA, mobile broadband, automotive, XR, PCs, robotics, and industrial IoT.

Qualcomm’s X105 Modem-RF system (Source: Qualcomm Technologies Inc.)

Broadcom Inc. announced an integrated 5G and Wi-Fi 8 FWA platform in partnership with Samsung Electronics Co. Ltd. The broadband-optimized reference platform integrates Broadcom’s BCM6776 Wi-Fi 8 system-on-chip (SoC) with Samsung’s B1320 5G modem. Claimed as an industry-first platform, it combines 3GPP R17 connectivity with the emerging Wi-Fi 8 (IEEE 802.11bn) standard.

The ​​Broadcom BCM6776 is a highly optimized, tri-band Wi-Fi 8 SoC. Key features include a quad-core Arm network processor with support for two-stream 40-MHz channels in the 2.4-GHz band and four-stream 160-MHz channels in the 5- and 6-GHz bands, delivering a complete Wi-Fi 8 platform in a single chip.

Other features include integrated 2 × 2 2.4-GHz and 4 × 4 5-GHz and 6-GHz Wi-Fi 8 MAC/PHY/radio functionality, which simplifies system design and lowers cost; an integrated multi-gig PHY; and on-chip 2.4-GHz power amplifiers and support for third-generation digital pre-distortion, which reduces external components and improves RF efficiency. Dual PCIe Gen3 controllers enable simultaneous tri-band applications with a single additional chip.

The platform reduces bill-of-materials costs, simplifies board design, and reduces active power consumption by 50% compared with previous generations, according to Broadcom.

The Samsung B1320 is a highly integrated, power-efficient, 5-nm chipset solution that supports 3GPP R17. It can achieve 5G downlink speeds of 3.43 Gbits/s and uplink speeds of 1.17 Gbits/s. It supports a 4Rx/2Tx radio chain. The 5G modem with a quad-core Arm CPU and the BCM6776’s network processor can support full Wi-Fi to 5G throughput. The platform also includes a Power Class 1.5 RF transceiver, power management, and a GNSS receiver. It also supports NR-NTN and NB-NTN for satellite communications.

Qualcomm also delivers 5G to wearables with its Snapdragon Wear Elite Platform. The personal AI platform delivers personal, always-on, intelligent wearable computing devices. It works across WearOS by Google, Android, and Linux with a neural processing unit (NPU) for on-device AI and an advanced suite of ultra-low-power connectivity solutions.

Claiming a first‑of‑its‑kind, multimode connectivity architecture, the Snapdragon Wear Elite Platform integrates six advanced technologies:

• 5G RedCap delivers advanced, low-power cellular connectivity for connected intelligent applications.
• Micro‑power Wi‑Fi enables always‑on Wi‑Fi connectivity at significantly lower power for intelligent wearables, according to Qualcomm, which require continuous AI context synchronizing, richer data exchange, and seamless coordination with nearby devices and cloud services.
• Bluetooth 6.0 enables proximity‑aware interactions.
• UWB provides secure, precise, proximity‑based interactions.
• GNSS delivers advanced AI processing for precise location context.
• NB‑NTN enables satellite‑based, two‑way messaging and critical communications from intelligent wearables when cellular and Wi‑Fi coverage are unavailable.

Delivering advanced power efficiency and faster speed, the platform delivers a 5× improvement on single-core CPU performance and up to 7× faster GPU for app launching, multitasking, and smoother rendering. This enables the Snapdragon Wear Elite to run complex, 2 billion–parameter AI models locally, faster, and more securely.

The advanced power management enables 30% more battery use than the previous generation. When recharging is needed, rapid charging powers a device up to 50% in approximately 10 minutes.

Qualcomm’s Snapdragon Wear Elite Platform (Source: Qualcomm Technologies Inc.) 5G SoCs and RF chips

In late 2025, MediaTek introduced its Dimensity 9500 SoC, delivering new levels of on-device AI, console-class gaming, and power efficiency. According to MediaTek, the 9500 is designed to “supercharge the next wave of flagship 5G smartphones.”

The Dimensity 9500 features a third-generation All Big Core CPU design combining a 4.2-GHz ultra core, three premium cores, four performance cores, and four-lane UFS 4.1 storage. It delivers up to 32% higher single-core and 17% higher multicore performance than the previous generation, while the ultra core achieves up to 55% lower power consumption at peak performance, for longer battery life and greater productivity, and claims up to 30% more power efficiency while multitasking in games and social audio call apps.

The platform also features a new cache and memory architecture, claiming the industry’s first support for four-channel UFS4.1. It doubles read/write speeds and accelerates large AI model loading by 40%. In addition, the second-generation Dimensity Scheduling Engine delivers smoother responsiveness and sustained efficiency even under heavy workloads, according to MediaTek.

The Dimensity 9500 integrates the Arm G1-Ultra GPU, providing up to 33% higher peak performance and 42% improved power efficiency, and introduces higher frame rate interpolation, up to 120-fps raytracing, for console-level, quality gaming.

MediaTek said integrating the ninth-generation MediaTek NPU 990 with Generative AI Engine 2.0 doubles compute power and introduces BitNet 1.58-bit large model processing, which reduces power consumption by up to 33%. The Dimensity 9500 is also the first integrated compute-in-memory architecture for its newly added Super Efficient NPU.

Doubling its integer and floating-point computing capabilities enables 100% faster, 3 billion–parameter LLM output; 128K token long text processing; and 4K ultra-high-definition image generation, while reducing peak-performance power consumption by 56%, according to the company.

The Dimensity 9500, with the MediaTek Imagiq 1190, supports RAW-domain pre-processing, up to 200-MP capture, 30-fps continuous focus tracking, a new portrait engine, and cinematic 4K 60-fps portrait video. It also provides the latest MiraVision Adaptive Display technology.

The platform’s connectivity suite includes Bluetooth call enhancement, Wi-Fi fast transfer, and multi-network intelligence. The AI-powered communication technologies are reported to deliver up to 10% lower power in 5G and 20% lower power with Wi-Fi, while 5CC carrier aggregation increases bandwidth by 15%. In addition, AI positioning and network selection technologies offer 20% higher accuracy, as well as 50% lower network latency thanks to AI congestion prediction, according to the company.

Qorvo Inc. recently introduced a family of RF switches for 5G radios, designed to simplify multiband radio architectures. The family spans from 50 MHz to 10 GHz. These devices reduce component count, improve signal integrity, and enable more efficient RF system design across 5G infrastructure, as well as industrial, drone, and test applications.

Designers face increasing challenges maintaining isolation and signal integrity without adding size, loss, and complexity, as 5G radios expand to support wider bandwidths and more frequency bands, Qorvo said. Many designs rely on cascaded switch architectures or multiple narrowband devices, which increase insertion loss, degrade linearity and signal integrity, and add board space and design effort, according to the company.

The wideband, high-isolation RF switch family addresses these challenges, eliminating the need for cascaded switches in 5G radios. “This approach reduces insertion loss, maintains signal linearity, and simplifies design, improving receiver performance in applications such as digital pre-distortion feedback,” Qorvo said.

The family comprises three devices:

• The QPC6144 for high-isolation switching is a SP4T wideband switch that delivers greater than 65-dB isolation in a single device, eliminating the need for cascaded switches.
• The QPC6122 (SP2T) for compact wideband switching and QPC6188 (SP4T) for flexible wideband routing provide wideband absorptive switching across 50 MHz to 10 GHz, enabling a single platform approach to RF routing. These devices reduce component count and simplify design. They also maintain low insertion loss and strong linearity across wide bandwidths for calibration paths, general signal routing, and multiband operation.

Qorvo’s wideband, high-isolation RF switch family (Source: Qorvo Inc.)

Sivers Semiconductors announced earlier this year the general availability of its highly integrated 7- to 15-GHz Alpine0715 (Daybreak) multi-beamforming transmit/receive front-end IC for emerging 5G/6G FR3 applications and multifunction defense arrays. The FR3 frequencies are used for 5G-Advanced and 6G network deployments, delivering sub-6-GHz and wider bandwidths at mmWave frequencies.

The Alpine0715, housed in a 7.95 × 7.0-mm WLCSP package, offers high linear output power, low noise figure, high efficiency, and integrated beam-table memory in a single device, the company said, and the reconfigurable multi-beamforming architecture enables smaller, lower-cost antenna arrays

Featuring four dual-polarization TX and four dual-polarization RX elements, the Daybreak beamformer IC delivers 27-dB gain and 20-dBm OP1dB TX performance and 32-dB single-channel gain and <3-dB NF RX performance.

5G modules

At electronica India 2026, Cavli Wireless announced two 5G modules targeting automotive, IoT, and M2M applications. The AQ62 5G Autograde is an automotive-grade 5G NR sub-6-GHz module designed for next-generation telematics and connected vehicle applications, and the CQM211 5G NR Advanced sub-6-GHz module, compliant with 3GPP R16, is designed for IoT and M2M applications.

The CQM211 5G NR module delivers multi-gigabit 5G connectivity with LTE Cat 16 fallback and flexible integration options for new and existing hardware platforms. The module targets high-bandwidth applications such as Industry 4.0 equipment, smart surveillance systems, routers, gateways, mobile Wi-Fi, and other edge applications requiring high-speed connectivity.

Key specs include a Cortex-A7 processor clocked at up to 1.8 GHz, 2× carrier aggregation over NR, dual-band GNSS, a PCIe Gen3 interface, and DBI display support. It is available in LGA and M.2 form factors.

The AQ62 5G Autograde module for connected automotive applications delivers an embedded software environment for developing advanced applications such as telematics control units, ADAS systems, OBD solutions, and hybrid tracking applications. The AQ62, built on Yocto Linux Kernel 5.15 with SDK support, provides high-speed 5G NR connectivity with LTE Cat 18 fallback. It supports 3GPP R16.

The 5G NR automotive module features a quad-core Arm Cortex-A55 processor, L1+L2/L5 GNSS, and dual-SIM dual-standby support. The module also provides optional NG-eCall and NTN band support. The AQ62 is available in five regional variants: worldwide (WW), North America (NA), Eurasia and Japan (EAJ), India (IN), and Eurasia (EA).

Designed to accelerate Android-based IoT applications, Quectel Wireless Solutions announced two Android 16 smart modules: the SE505FE entry-level 5G smart module and the SH602FA high-performance 4G smart module. The modules provide integrated wireless connectivity and multimedia capabilities in compact form factors.

Here, we’ll focus on the 5G module, which provides Android-powered 5G connectivity to a wider range of IoT applications. The module is built on the MediaTek MT8863T chipset with a 2× Cortex-A76 and 6× Cortex-A55 processor architecture and Mali-G57 GPU. It supports 5G sub-6-GHz and LTE Cat 4, together with Wi-Fi 6, Bluetooth 5.2, and GNSS. Typical applications include AR/VR devices, digital signage, smart gateways, tablets, industrial PDAs, robotics, and intelligent video platforms.

The SE505FE series modules support multiple-input/multiple-output technology. Quectel said the concurrent use of multiple antennas at the receiver end on the same frequency band minimizes bit error rate and optimizes data speed, which improves communication quality.

The module supports multi-constellation GNSS (GPS, BDS, GLONASS, Galileo, and QZSS) receiver for fast and accurate positioning and offers a range of interfaces, including LCM, camera, touch panel, microphone, UART, USB, I2C, and SPI. It supports cameras up to 32 MP at 30 fps and 1080 × 2520 video recording and playback at 120 fps.

The module is housed in a 42.5 × 56.2 × 2.95-mm LGA package. The SE505FE series is available in three variants: SE505FE-EM, SE505FE-NA, and SE505FE-WF (supports Wi-Fi and Bluetooth only).

Quectel’s RM255C-GL and RG255C-NA (Source: Quectel Wireless Solutions)

Quectel also expanded its mid-tier 5G family with RedCap 3GPP R17 variants: the RM255C-GL for global markets and the RG255C-NA for North America.

5G RedCap has emerged as the technology to address the mid-tier connectivity gap between high-speed eMBB and narrowband IoT as 5G expands into industrial and IoT domains, Quectel said.

The RM255C-GL is a 5G sub-6-GHz RedCap module in the M.2 form factor, developed in accordance with 3GPP R17. It supports peak data rates of up to 223-Mbits/s downlink and 123-Mbits/s uplink, with 5G sub-6-GHz standalone operation and LTE Cat 4 fallback. It is backward-compatible with R15 and R16.

The RM255C-GL is pin-to-pin-compatible with Quectel’s RM5x0N and RM50xQ 5G series and both pin-to-pin and size-compatible with selected LTE-A and 4G modules, including the EM06, EM12 series, EM160R-GL, and EM05, which helps simplify the migration from LTE to 5G RedCap.

The module integrates Qualcomm IZat Gen 9VT location technology with optional multi-constellation GNSS support (GPS, GLONASS, BDS, Galileo, QZSS, and NavIC) for fast and accurate positioning. It also supports a range of interfaces, including USB 2.0, PCIe 2.0, and PCM, and offers USB drivers for Windows 10/11, Linux, and Android, extending the module into a wider range of RedCap applications.

The RG255C-NA 5G RedCap sub-6-GHz, housed in an LGA module, is designed in compliance with 3GPP R17. Purpose-built for industrial-grade applications, it supports key 5G capabilities including URLLC and network slicing. The module delivers peak data rates of up to 223-Mbits/s downlink and 123-Mbits/s uplink. It operates in 5G sub-6-GHz standalone mode with LTE Cat 4 fallback and is backward-compatible with R15 and R16.

The module is compatible with Quectel’s compact EG2x 4G module series, simplifying design upgrades while meeting mid-speed application requirements for higher capacity, low latency, and enhanced reliability in industrial and commercial deployments, the company said.

The RG255C-NA also integrates Qualcomm IZat Gen 9VT location technology, supporting multi-constellation GNSS including GPS, GLONASS, NavIC, BDS, QZSS, and Galileo. The integrated GNSS receiver streamlines product development and provides fast and accurate positioning, Quectel said.

The module also features a suite of industry-standard interfaces, including USB 2.0, PCIe 2.0, PCM, UART, SGMII, and SPI, along with USB driver support for Windows 10/11, Linux, and Android.

The RM255C-GL and RG255C-NA have completed the required regulatory and industry conformance certifications. The RG255C-NA is certified to FCC, IC, and PTCRB standards, while the RM255C-GL has achieved CE, RCM, FCC, IC, GCF, and PTCRB certifications.

The post 5G chips and modules power phones, wearables, IoT, and vehicles appeared first on EDN.

Knowing the mains frequency is important in many industries; the speeds of AC motors, for example, are dependent on it. The motor speed= (120*F)/P, where F is the mains frequency and P is the number of poles. Since P is a fixed number for any motor, speed varies in proportion to mains frequency. This frequency can be easily measured by MCU-based projects within a small gating time. The period is measured and 1/T is computed to obtain the frequency.

For non-MCU projects, the mains frequency can be measured with a simple counter within a gating time of 1 second. For 50 Hz (as followed in countries like mine, India), this will show 50 ± 1. If you increase the gating time to 10 seconds, the reading will be 500 ± 1. Finally, if you set the gating time to 100 seconds, the counter will show 5000 ± 1 which can be made to read 50.00. This accuracy is acceptable, but the gating time is too high for the measurement to update within a reasonable period.

What is the alternative? If you can multiply the frequency by 100 and then feed it to the counter, the counter will read 5000 within a gating time of 1 second, which can be made to show 50.00. You will get a resolution of 0.01 Hz while keeping the gating time as 1 second. This is what’s done by the circuit in Figure 1, which implements a by-100 frequency multiplier based on a modified PLL (phase lock loop).

Figure 1 This circuit multiplies the AC mains frequency by 100 and displays the result using a simple counter scheme. The component values shown assume a 50 Hz mains source.

How does it work?

• Transformer T1 gives an output of 6V AC; this same transformer can be used to produce 5V DC required to power the circuit. U1A is used as zero cross detector, whose output is the mains waveform converted to a square wave with a 50% duty cycle.
• The 6V AC output routes to pin 1 of U2A, an exclusive OR gate. This IC acts as a phase detector.
• U3, a 555 timer, functions as 5,000 Hz square wave generator.
• This frequency is divided by 10 using U4A, a 4518 counter.
• U4B, another 4518 counter, and U5, a 4585 comparator, operate as a frequency divide-by-5 circuit. In digital comparator U5, another 4585, inputs A0, A1, A2 and A3 are connected to the outputs Q0, Q1, Q2 and Q3 of the U4B previous stage. Input B3, B2, B1 and B0 are hardwired as 0101 (5). When the count in U4B reaches 5, its A=B output sends a pulse to U6A (another 4518 counter) and resets U4B so that it starts counting from zero again.
• U6A’s Q0 output divides the input frequency by 2.
• Thus, the combination of U4A, U4B, U5 and U6A operates as divide-by-100 circuit.
• This divide-by-100 output is connected to pin 2 of U2A, again acting as phase detector.
• U2A’s output feeds a low-pass filter circuit formed by R2 and C1, and is then connected back to pin 5 of the 555, circuit which works as voltage-controlled oscillator (VCO).
• Thus, the PLL circuit closes and the 555 output is then read in the counter as the AC mains frequency multiplied by 100.

If the mains frequency variation is in a narrow range of, say, 48 to 52 Hz, this PLL circuit works nicely. The power supply and ground pins of the digital ICs are not shown in the circuit diagram.

Note that since the divide-by-10 output of the 4518 IC is not a square wave with 50% duty cycle, the divide-by-10 second stage was done in two parts: divide-by-5 and divide-by-2, thus solving the challenge of the closing of the phase lock loop.

60 Hz operation notes

Countries such as the United States instead use a 60 Hz mains frequency. With some component changes, this circuit will also measure 60 Hz ± 2 Hz accurately.

• Transformer T1 should be a 110V/6V AC, 60Hz variant.
• The 555 multivibrator should be tuned to oscillate at 6000 Hz. R3=R4=11K and C2=0.01uF.
• For the low pass filter, R2=110K and C1=2.6uF.

The following video shows the operation of this circuit for 49.55 Hz and 50.55 Hz simulated mains frequencies.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

• Frequency division by any even number, with a 50% duty cycle output
• Unmasking the ghosts in your grid with power quality analyzers

The post Measure the AC mains frequency with an ordinary counter appeared first on EDN.

AI-assisted chip engineering is increasingly capable of reaching meaningful design milestones. But reaching GDS does not establish that the resulting engineering outcome is better. If AI agents are going to participate more deeply in semiconductor design, the next question must move beyond capability: Did the AI beat an engineering benchmark that engineers already trust?

And if it appears to have done so, can the engineering data prove the improvement rather than relying on one successful run or thousands of tool logs? That is the natural next step in the trust discussion.

The problem is no longer only whether AI can make engineering decisions. It’s whether those decisions can be evaluated using the same discipline engineers already use to evaluate designs. A useful framework is:

Target workload → Workload/Memory model → Engineering benchmark → DOE → RSM/Regression → Predict → Verify with EDA → Measure error → Compare → Repeat

Two ideas are central. First, the benchmark must represent the workload the silicon is actually intended to serve. Second, the AI-generated design history must be converted into measurable engineering evidence.

Benchmark must start with the workload

For an AI accelerator, frequency, power, area, and timing are not really the beginning of the problem. They are consequences of the workload. Relevant assumptions may include model type, context length, concurrency, compute intensity, memory footprint, HBM capacity, memory bandwidth, interconnect traffic, and communication behavior.

A long-context inference workload may create very different memory requirements from a short-context workload. A compute-bound workload may favor one architecture. A memory-bound workload may favor another.

So, before asking whether AI beat a benchmark, engineers first need to ask: Was the benchmark derived from the workload the chip is actually expected to serve? Because a statistically excellent optimization against the wrong workload is still the wrong design.

The chain therefore begins with:

Workload → Compute and memory behavior → Hardware requirements → Engineering benchmark

Only after that do conventional design metrics become meaningful.

Define a benchmark engineers already trust

The reference implementation could come from an existing production design, a previous tapeout, an experienced engineering team, a conventional EDA flow, or another controlled implementation. The important point is comparability.

The AI-generated design and the reference should be evaluated against equivalent conditions:

• Workload
• Process technology
• PDK and libraries
• Frequency target
• Timing requirements
• Power budget
• Area constraint
• Operating corners
• Physical-design constraints
• Memory requirements
• Sign-off requirements

Against the same workload and engineering problem, what did the AI actually improve? Then the comparison becomes meaningful.

Passing the requirement isn’t enough

A benchmark should include margin, not merely pass/fail. Suppose two implementations both reach 2.2 GHz. One closes timing with +5 ps of margin. The other closes with +45 ps. Both technically pass. But they are not equivalent engineering results.

The same principle applies to power, area, IR drop, EM, thermal behavior, routing, memory bandwidth, and corner margin. The useful question becomes: How far inside the acceptable engineering region did the AI place the design?

That is more informative than simply asking whether it crossed a threshold.

AI creates an engineering dataset

An AI-assisted design process may explore far more alternatives than a human team could practically investigate manually. Those iterations can contain combinations of:

• Frequency
• WNS/TNS
• Power
• Area
• Placement
• Congestion
• Routing
• IR drop
• EM
• Thermal behavior
• Memory behavior
• Physical violations

Those observations should not automatically be treated as disposable logs. They can become an engineering dataset. The question then becomes: Can the data describe the design space well enough to evaluate the AI result quantitatively?

DOE can structure the exploration

Design of experiments (DOE) provides one established way to organize the search space. Possible controllable variables might include floorplan parameters, placement density, clock constraints, cell sizing, buffering, voltage, routing strategy, power-grid parameters, memory configuration, or other design-specific controls. Measured responses could include timing, frequency, power, area, congestion, temperature, IR drop, EM, memory bandwidth, and physical violations.

Conceptually, engineering response = f (design variables)

For AI accelerators, workload parameters can also enter the problem: engineering response = f (design variables, workload variables). That allows the analysis to examine not only how the design responds to physical controls, but how sensitive it is to changing workload assumptions.

Turn data into a predictive model

Response surface methodology, regression, or other surrogate modeling approaches can then be used to describe relationships in the explored design space. The exact mathematical model is less important than the engineering principle: Do not treat thousands of AI-generated engineering states as unrelated observations. Build a quantitative model of the design space.

That model can expose useful relationships. Which variables dominate timing? Where does frequency improvement become expensive in power? When does area reduction create unacceptable congestion? How sensitive is memory demand to workload assumptions? Where does the feasible engineering region begin to disappear?

Now the AI-generated history becomes more than activity. It becomes interpretable engineering evidence.

The model must earn trust too

Regression does not automatically make a model trustworthy. Useful statistical measures may include R², adjusted R², predicted R², RMSE, residual behavior, and lack-of-fit. But for this application, there is an even more important test: How accurately does the model predict the next actual EDA result?

Suppose the model predicts: WNS = +25 ps and the actual EDA result is: WNS = +23 ps. That is useful predictive agreement. If the prediction is +25 ps and the actual result is −40 ps, the model has missed something important. Prediction error can therefore become part of the engineering evidence.

Across repeated runs, engineers can ask:

• Is the error small?
• Is it stable?
• Is it biased?
• Is it improving?
• Does it become worse in a particular design region?

That leads to one of the most important principles in the framework: The AI should not only show that the design improved. It should also show that its prediction of the design agrees with actual engineering results. Trust increases when prediction and engineering reality repeatedly agree.

Compare the distribution, not the best run

One good result is not enough. The AI-assisted process should be repeated under controlled conditions. For important engineering responses, evaluate:

• Mean
• Standard deviation
• Percentiles
• Confidence interval
• Range
• Outliers
• Success rate
• Margin relative to requirements

The question is: What does this method usually produce, and how tightly distributed are the outcomes? One exceptional tapeout is interesting. A repeatable distribution of strong outcomes is much more convincing.

That is especially important when the system contains stochastic optimization, multiple agents, changing starting points, or large search spaces.

Optimization quality lives in the trade-offs

A design can improve one metric while becoming worse elsewhere. Useful relationships may include:

• Frequency vs. power
• Frequency vs. area
• Timing margin vs. power
• Area vs. congestion
• Performance vs. thermal density
• Performance vs. memory bandwidth

The important question is not simply whether one number improved. It is: Did the AI discover a better engineering trade space for the target workload? That is a much stronger benchmark than asking which run produced the highest frequency or smallest area.

The benchmark must be able to move

AI hardware introduces another complication. The workload itself can evolve while the silicon is being designed. Model architecture can change. Context length can increase. Concurrency can grow. Memory behavior can shift. The balance between compute and communication can change.

An accelerator optimized perfectly against one workload assumption may reach tapeout only to discover that the target has moved. So another useful question is: How sensitive is the AI-generated design to plausible changes in workload assumptions?

So, the objective is not to design one chip for every possible future workload. It is to understand whether the useful engineering region is broad or narrow.

A trustworthy method must be able to say “No”

A good evaluation framework should not exist only to prove that AI works. It must also be capable of proving that it did not. Perhaps frequency improves but power and area deteriorate enough that the conventional benchmark remains better.

Perhaps the average result improves but variability becomes unacceptable. Perhaps the model fits historical observations but predicts new EDA results poorly. Perhaps one impressive result hides a low overall success rate. Perhaps the AI optimizes the silicon well against a workload assumption that is no longer representative.

A trustworthy methodology must therefore be capable of concluding that, for this workload and engineering problem, the AI-assisted approach did not beat the benchmark. That is part of engineering trust.

Trusted EDA can remain the arbiter

None of this requires AI to replace established sign-off tools. A practical model is:

AI-assisted exploration and optimization → Trusted conventional analysis and sign-off

AI may perform more of the search, optimization, debug, and closure work. Established EDA can remain the independent engineering reference. The immediate test is therefore not whether AI becomes the sign-off authority. It is: Can AI repeatedly produce designs that survive trusted sign-off?

That makes adoption much more practical.

Manufacturing alignment is the final check

Even after the AI beats the design benchmark, one additional question remains. Before hardware exists, actual manufacturing yield and reliability are still unknown. But the tapeout already contains indicators of how demanding the physical realization may become:

• Routing density
• Local current density
• Thermal concentration
• Physical margin
• Variation sensitivity
• Die area
• I/O requirements
• Package requirements
• Test complexity

So engineers should ask: Did the AI achieve the improvement in a way that remains reasonably aligned with the intended manufacturing target? This does not claim to predict actual manufacturing yield. It asks whether the AI won the design benchmark by creating a much harder downstream physical problem.

From AI capability to engineering evidence

The complete framework is:

Target workload → Workload/Memory model → Engineering benchmark → DOE → RSM/Regression → Predict → Verify with EDA → Measure error → Compare → Repeat

The result is not an AI score. It is engineering evidence. Target workload defines what the silicon must execute. Workload/Memory model translates that workload into compute, bandwidth, capacity, and communication requirements.

Engineering benchmark establishes the trusted reference and required margins. DOE structures the exploration. RSM/Regression models the engineering response space. Predict estimates the outcome of the next move.

Verify with EDA tests that prediction against engineering reality. Measure error quantifies predictive accuracy. Compare evaluates improvement, margins, and trade-offs against the benchmark. Repeat establishes whether the result is reproducible.

The question for the industry

AI-assisted semiconductor engineering is increasingly demonstrating that AI can perform meaningful chip-design work. The next challenge is harder. It must prove that the engineering result is actually better.

That requires the correct workload, a benchmark engineers trust, quantitative modeling, predictions tested against real EDA results, and measured prediction error, repeated experiments, trade-off analysis, and trusted sign-off.

The question therefore becomes: Can AI beat a benchmark engineers already trust for the workload the silicon is intended to serve—and can the engineering data prove that it did? That is a much higher standard than an impressive demonstration.

But semiconductor engineering already knows how to work this way. Perhaps the path to trusting AI is not to abandon established engineering discipline. It is to apply that discipline directly to AI-generated design.

• Define the workload
• Define the benchmark
• Model the response
• Predict
• Verify
• Measure the error
• Compare
• Repeat

Then ask the question that matters: Did the AI actually beat the benchmark—and can the engineering data prove it?

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

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• Applied Materials Bets $5B on a New Model for Chip Innovation
• How AI is reshaping IC signoff: Trust, speed, and intelligent workflows
• The Magic of Agentic AI Will Come From a Holistic Approach to Chip Design

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They look like simple, passive lumps of material molded onto a cable or dropped onto a PCB but looks can be highly deceiving. To the uninitiated, a ferrite bead is just a mysterious black cylinder taking up space on a wire. But underneath that boring exterior lies an engineer’s secret weapon for turning pesky high-frequency noise into harmless heat.

To understand a ferrite bead, you have to look past the standard inductor symbol often used for it on a schematic. At low frequencies, a ferrite bead does behave like a garden-variety inductor, offering low DCR (DC resistance) and letting your desired signals pass right through.

But as the frequency climbs into the megahertz range, the magic happens. The bead’s inductive reactance (XL) takes a backseat to its resistive component (R). Instead of reflecting high-frequency noise back into your circuit like a pure inductor would—which can cause unwanted resonance and ringing—the ferrite bead acts like a frequency-dependent sponge, trapping that electromagnetic interference (EMI) and dissipating it as a tiny amount of thermal energy.

To see why this shift happens, it helps to look at the bead’s equivalent circuit.

The core physics: How they actually work

To understand ferrite beads, it helps to look at how they are modeled in a circuit. A bead isn’t just a simple inductor (L). Instead, it is best modeled as an inductor (L) and a lossy resistor (R) in series, both in parallel with a parasitic capacitor (Cp). This combination explains why their behavior transforms so dramatically as frequency changes.

At low frequencies, the inductive element dominates. The bead behaves like a small coil, storing energy in its magnetic field and reflecting disturbances back toward the source. In this regime, signals pass through almost unaffected, while the bead quietly resists sudden changes.

As the frequency rises, however, the bead’s resistive component takes over. Instead of bouncing noise back into the circuit, the bead begins to absorb it. High‑frequency EMI is converted into tiny amounts of heat inside the ferrite material. This lossy behavior is what makes beads so effective at cleaning up noisy power rails and suppressing RF interference.

The parasitic capacitor adds another wrinkle: at very high frequencies, it can provide a bypass path, limiting the bead’s effectiveness. That’s why datasheets often show impedance curves that peak and then roll off.

Mathematically, the bead’s impedance is expressed as Z = R + jX, where X is the reactance (from inductance or capacitance). At low frequencies, X dominates. At high frequencies, R becomes the star of the show, ensuring that unwanted signals aren’t reflected but instead dissipated.

This dual nature—reactive at low frequencies, resistive at high—makes ferrite beads uniquely suited to tame the invisible chaos of EMI.

Figure 1 A mixed-signal IC filtering scheme attenuates digital supply noise from sensitive analog power domains. Source: Analog Devices Inc.

Note at this point that ferrite beads come in several distinct forms tailored to different circuit needs: multilayer chip beads use internal printed traces for compact surface-mount filtering; wirewound beads coil insulate copper wire around a core to handle higher DC currents with minimal power loss; leaded through-hole beads offer sturdy mounting for traditional power electronics; and snap-on cable cores (chokes) clamp around external cables to stop them from acting as RF antennas. Regardless of their physical design, all these types share the same core function—absorbing high-frequency EMI and dissipating it harmlessly as heat.

Strip away the form factors—whether it’s a tiny chip bead soldered to a modern PCB, a leaded through-hole bead in a power circuit, or a snap-on choke on a laptop cord, all ferrite beads do the same job. They act as “high-frequency sponges” that absorb unwanted EMI and turn it into heat. On circuit boards, chip beads clean up power lines right at the source, while on external cables, ferrite cores keep long wires from becoming broadcast antennas that violate regulatory limits.

Ferrite bead vs. standard inductor

While inductors and ferrite beads may look alike, their roles in a circuit are fundamentally different. A standard inductor is designed to store energy in its magnetic field, with a high Q factor that minimizes losses and allows it to resonate cleanly with capacitors. Its purpose is precision—shaping signals and conserving energy.

A ferrite bead, on the other hand, is intentionally engineered to be lossy. Its resistive element rises sharply at targeted high frequencies, ensuring that instead of ringing with noise, it absorbs and dissipates it as heat. In effect, inductors are tools for energy conservation and resonance, while ferrite beads are noise suppressors, sacrificing efficiency at high frequencies to protect circuits from EMI.

This purposeful lossy behavior is why beads are so common on USB cables, power rails, and RF lines, where stability and quiet operation matter more than resonance.

The trap: Current saturation and DC bias

Here’s where ferrite beads reveal a hidden weakness that many beginners overlook: DC current ruins their effectiveness. The culprit is magnetic saturation. As a steady DC current flows through the bead, the ferrite core material begins to saturate. In this state, the core can no longer respond linearly to changes in magnetic flux, and its effective permeability drops sharply.

The consequence is dramatic. Impedance, which is the bead’s measure of resistance to unwanted high‑frequency signals, collapses. A bead that proudly advertises 600 Ω of impedance at a given frequency might deliver only 50 Ω if you push it near its maximum rated DC current. Instead of choking off noise, it becomes nearly transparent, letting interference slip through unchecked.

Figure 2 Key performance specifications—including impedance, rated current, and operating temperature—are shown from a leaded ferrite bead datasheet. Source: Author

This is why datasheets specify a maximum DC bias current: it’s not just a thermal limit, but a functional one. Exceeding it means the bead stops being a noise filter and starts behaving like a weak wire. For engineers, the lesson is clear—always size ferrite beads with headroom for DC current. Otherwise, your carefully chosen EMI suppression component may silently fail, leaving your design vulnerable to the very noise it was meant to kill.

How to read a ferrite bead datasheet

A ferrite bead’s datasheet is more than a list of part numbers—it’s a roadmap to understanding how the bead will behave in your circuit. The most important plot is the impedance vs. frequency curve. At low frequencies, the curve is dominated by reactance (X), showing the bead’s inductive nature.

As frequency rises, the resistive component (R) overtakes X, and the curve peaks—this crossover frequency marks the point where the bead stops reflecting noise and starts absorbing it. That peak is the sweet spot for EMI suppression.

Figure 3 These impedance-frequency characteristics of a surface-mount ferrite bead are adapted from the manufacturer datasheet. Source: Micros

As you can see the plot displays X (reactance) dominating at lower frequencies (~10–30 MHz) and dropping near 100 MHz, while R (resistance) rises to equal/exceed X and dominates the total impedance Z around 100 MHz.

Another critical parameter is the DC resistance or DCR. While often overlooked, DCR tells you how much voltage drop the bead will introduce on a power rail. A bead with high impedance but excessive DCR can starve sensitive circuits of voltage.

The trick is to balance; choose a bead with a strong impedance peak at your noise frequency, but low enough DCR to keep your power rails stable. Reading datasheets this way ensures you’re not just picking a bead; you’re engineering a reliable noise filter.

Material matters: Curie temperature and resistivity

Ferrite beads are not only defined by their geometry but also by the ferrite material itself, and two parameters—Curie temperature and resistivity—play a decisive role in bead choice. The Curie temperature marks the point at which the ferrite loses its magnetic properties; MnZn ferrites typically sit around 200–300 °C, while NiZn variants can reach 350 °C or higher, meaning that operation near this limit causes permeability to collapse and impedance to vanish.

Resistivity differences further shape performance: MnZn ferrites, with relatively low resistivity in the 10–100 Ω·cm range, are well suited to suppressing lower-frequency noise below about 1 MHz but suffer eddy current losses at higher frequencies. Whereas NiZn ferrites, with resistivity in the 103–106 Ω·cm range, excel in the 10–100 MHz band and beyond, making them the preferred choice for RF and high‑speed digital suppression.

The design lesson is clear—match bead material to the noise spectrum and respect the Curie limit, because thermal stress or the wrong resistivity profile can silently erase EMI suppression.

Practical applications and best practices

Ferrite beads earn their keep in real-world designs by strategically blocking noise where it matters most. They are commonly placed in power supply filtering, forming part of LC rails to keep voltage lines clean. They also shine in decoupling pi-filters, where they help isolate noisy digital blocks from sensitive analog domains—such as keeping a microcontroller’s chatter away from an ADC’s quiet input stage.

But placement requires caution. A classic pitfall is dropping a ferrite bead directly next to a ceramic decoupling capacitor. Together, they can form an unintended LC tank circuit that resonates at certain frequencies. Instead of suppressing noise, this setup can actually amplify it, creating spikes that defeat the bead’s purpose.

The best practice is to space beads thoughtfully, use them in conjunction with resistive damping when necessary; to fix this, engineers often damp the circuit by adding a small series resistor or using a high-ESR electrolytic/tantalum capacitor in parallel with the ceramic capacitor. And always check impedance curves to ensure they’re working in your target frequency band. In short, ferrite beads are powerful tools, but only when applied with care.

Beads of truth: What textbooks miss

Ferrite beads may look like humble black cylinders or chips, but they embody a subtle engineering truth: they’re not inductors, they’re intentional noise killers. What they don’t teach you in school is that their effectiveness hinges on details often buried in datasheets—DC bias limits, impedance crossover points, and placement pitfalls that can turn a filter into a noise amplifier. Mastering ferrite beads means thinking beyond the schematic symbol and into the physics of saturation, loss, and frequency response.

So, the next time you spot that “mystery cylinder” on a USB cable or a bead on a power rail, remember it’s not there to store energy; it’s there to sacrifice it, converting interference into harmless heat. As an engineer, your job is to wield that sacrifice wisely. Read the curves, respect the ratings, and place beads with intent. Do that, and you’ll transform a quiet component into a powerful ally against EMI.

Now take a fresh look at your current designs. Pull up a ferrite bead datasheet, trace your power rails, and ask yourself: are your beads truly suppressing noise, or just sitting there as decoration? The answer could be the difference between a flaky prototype and a rock‑solid product.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

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• Power Tip 69: A Simple Oversight Can Ruin EMI Performance
• Key parameters to consider when selecting drum core power inductors

The post The secret life of ferrite bead: More than just a lump on a wire appeared first on EDN.

A seemingly newer device reverts to a legacy processor architecture, in comparison to one certified earlier that same year. Does it matter? And was it due to Matter?

This is the end
Beautiful friend
This is the end
My only friend, the end
The Doors, “The End”

In quoting those epic song lyric opening lines, I’m not referencing an ex-girlfriend, as Jim Morrison had reportedly done, but instead applying them to my long-running TP-Link smart plug teardown series. This entry, for the Tapo P110M, marks the end of the publication line (at least as currently planned) for this specific content cadence.

I hope you enjoyed reading about the various devices as much as I enjoyed taking them apart, photographing them, and writing about them.

The series, up to this point, began in February and encompasses the following analyses:

• TP-Link’s Kasa HS103: A smart plug with solid network connectivity
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again
• TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive
• TP-Link’s Tapo P105: A Kasa EP10 clone, or evolutionarily derived?
• TP-Link’s Tapo P125: A smart plug with an Apple HomeKit vibe
• TP-Link’s Tapo P115: Smart plug subtracts Apple, adds energy tracking

Reiterating a frequently uttered mission-statement mantra I most recently chanted last month, my basic aspiration with this project was to ascertain to what degree (if any) differences in the company’s various smart plug products’ feature sets, broadly between the Kasa and Tapo product lines as well as between products within a given line, were due to hardware variability versus (or in addition to) software-implemented inconsistency. Last month’s unveil was a particular hardware-evolution doozy, as it involved the processor architecture (and associated codebase) conversion from Arm (Realtek) to RISC-V (Espressif Systems).

So, what will we find inside the Tapo P110M? Usually, but not always, TP-Link’s Matter smart home and IoT protocol-supportive product variants include “M” as a product name suffix. More generally, in addition to Matter cognizance (or lack thereof), we’ve seen over this past year that the manufacturer also differentiates devices based on parameters such as energy monitoring and reporting capabilities and Apple HomeKit protocol support, not to mention cosmetic variances such as size, shape and weight, switch and activity LED locations, and the like.

The P110M, for example, implements all three aforementioned software enhancements, only one of which (energy tracking) last month’s Tapo P115 shares. Let’s see how, if at all, this differentiation is also reflected in hardware.

Feature set confusion

Here’s a stock shot of the Tapo P110M, to start.

 

Looks curiously familiar, albeit not identical, doesn’t it?

My two-pack came from Amazon’s Resale (formerly Warehouse) website area and set me back $13.77 after a 30%-off promotion active at the time, plus tax. While just now revisiting the product page both there and at TP-Link’s website, I was initially confused, since the latter (not to mention TP-Link’s broader product line overview page) explicitly notates support for Apple’s Home protocol, Siri interface and the like, all absent from the former. However, I suspect Matter cognizance is at the nexus of the discrepancy, as noted at Amazon product page verbiage:

Matter-certified devices, regardless of brand, can work together and are compatible with most major smart home platforms like Amazon Alexa, Apple HomeKit, Google Home, and Samsung SmartThings. Enjoy more flexible and unified control.

Translation, I’m guessing: the Tapo P110M doesn’t support Apple services directly, but instead implicitly via their common Matter-support intermediary.

Here’s the usual suite of outer box shots, complete with the also-as-usual 0.75″ (19.1 mm) diameter U.S. penny accompaniment for size comparison purposes. Top.

Front.

Left side.

Back.

Right side.

And bottom.

Peeling away an edge of the information-obscuring Amazon Resale sticker exposes to view the hardware revision number—v1.6—of what’s inside. And in a rarity, at least from my experience, that’s the only hardware version option listed on the product support page (albeit with multiple to-date associated firmware updates). A refreshing change of pace.

Sticker shock

Let’s now see what’s inside.

One of the two Matter stickers was previously removed from its original backing sheet. Wonder where it went? Hold that thought.

I’ve usually found with returned-and-resold stuff like this that only one of the multiple items in the package has been removed prior to re-placement and shipment back to Amazon. I generally select that same one as my teardown “victim”. But which one was it in this case?

Again, it’s usually the one on the left (or upper left corner for a quad-device box). But the prior owner of this set might have been left-handed; the indent for the device on the right is frayed.

Here’s more visual evidence of the prior owner’s out-of-box device selection preference. There’s the missing sticker, now adhering to the top of the smart plug on the right.

Putting the left-side device aside, let’s continue with the usual overview photo set. Top, again.

Front.

Left side.

Back.

Right….what?

Turns out the Matter QR code and info are already stamped on the device’s right side. Turns out, too, the owner stuck the supplemental sticker on the wrong device, because the info sets don’t match. Truthfully, I don’t think the sticker’s intended for the device at all (unnecessary info redundancy, don’cha know) but if so, it instead should have been stuck on top of the other device.

Maybe owner confusion is at the core of why it ended up getting returned? Dunno. Onward.

As usual, the bottom of the device contains useful info, including the FCC ID (2BCGWBP1100).

Quick aside: the FCC ID for last month’s Tapo P115 is quite similar (2BCGWP110). That’s not confusing at all, right? Its listed “final action date” is February 29, 2024 (a leap year, obviously) while this one’s “final action date” is July 24 of that same year. Therefore the “seemingly newer device…in comparison to one certified earlier that same year” prose in the subhead.

A screw loose

One more stock shot to go: the latest in a line of company-supplied interior concept images:

And that’s enough for the setup; let’s get inside. Practice makes perfect, apparently; this time not only was no bloodshed, but no tabs were snapped, either.

Voila.

Here’s the half you’re undoubtedly all most interested in.

Device-to-device design consistency takes the form, among other things, of the relay, yet another Churod A16-V-105DA2F.

The bottom and right-side views are equally reminiscent and unmemorable.

And, last but not least, what of the digital PCB on the left? I’ll start with the boring side (unless you’re into traces, test points, and/or embedded antenna silhouettes, that is).

That’s what’s known as a tease. Here’s the side you care about, especially after last month’s reveal that it had captured and encompassed a processor architecture shift.

No such momentous luck this time, alas. We’re back to Realtek’s RTL8720CM at left, previously found on several previous TP-Link smart plug designs, along with a Shanghai Belling BL0937 single-phase energy monitoring IC and Eon Silicon’s EN25Q32B 32 Mbit serial flash memory on the right (not found with the Tapo P115, since the NVM was single-package integrated alongside the processor in that case).

And of course there’s also yet another mysterious five-lead packaged device in the lower left corner (I’m still sticking with my guess that these are dual transistor devices), this time marked “TACeE1” . Plus, we can’t forget the switch alongside an LED smack dab in the center.

Why the seeming chronological advancement but architectural back-step from RISC-V is back to Arm this time? My guess is that it has everything to do with Matter. The specification is in the rapid-evolution early phase of its technology lifecycle, and with no offense intended to Espressif Systems, Realtek is the more mature of the two suppliers in this particular product category.

Sound off with your theories and/or broader thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Tapo or Kasa: Which TP-Link ecosystem best suits ya?
• TP-Link’s Tapo P115: Smart plug subtracts Apple, adds energy tracking
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again
• TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive

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