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Foundry PDK aims to train engineers on 2-nm process node
A new process design kit (PDK) from imec aims to provide broad access to a 2-nm gate-all-around (GAA) process node and associated backside connectivity for design pathfinding, system research, and training. This foundry PDK features the necessary infrastructure for digital design based on a set of digital standard cell libraries and SRAM IP macros.
The design PDK—enabling virtual digital designs in imec’s N2 chip manufacturing process technology—comes embedded with EDA tool suites from Cadence Design Systems and Synopsys. And it aims to train the semiconductor experts of tomorrow and enable the industry to transition to next-generation process technologies through meaningful design pathfinding.
Source: imec
Foundry PDKs—which provide chip designers access to a library of tested and proven components—are usually available once process technology reaches a critical level of manufacturability. And here comes the catch: there is restricted access and the need for non-disclosure agreements (NDAs). That, in turn, creates a high threshold for academia and industry to access advanced technology nodes like 2-nm during their development.
What imec’s N2 PDK is trying to do is provide young semiconductor engineers in academia and industry with early access to the infrastructure needed to develop design skills on advanced technology nodes such as 2 nm. “The design pathfinding PDK will help companies to transition their designs to future technology nodes and pre-empt scaling bottlenecks for their products,” said Julien Ryckaert, VP of Logic Technologies.
Next, the accompanying training courses will acquaint engineers with the most recent technology disruptions such as nanosheet devices and wafer backside technology. The training program, starting in the second quarter of 2014, will teach subscribers the specificities of the N2 technology node while offering hands-on training on digital design platforms using the Cadence and Synopsys EDA software.
Yoon Kim, VP of Cadence Academic Network, acknowledged that imec’s design pathfinding PDK represents a major milestone for training the next generation of silicon designers. “Imec used Cadence’s AI-driven digital and custom/analog full flows to create and validate the design pathfinding PDK.”
Likewise, Brandon Wang, VP of technical strategy & strategic partnerships at Synopsys, quoted pathfinding PDK as an example of how industry partnerships can broaden access to advanced process technology for the current and next generation of designers. “Our collaboration with imec to deliver a certified, AI-driven EDA digital design flow for its N2 PDK enables design teams to prototype and accelerate the transition to next-generation technologies using a virtual PDK-based design environment.”
According to imec, the design pathfinding PDK platform will extend to more advanced nodes like 1.4 nm.
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- EU Signs €145bn Declaration to Develop Next Gen Processors and 2nm Technology
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What does Renesas’ acquisition of PCB toolmaker Altium mean?
Renesas increasingly looks like Cisco of the 1990s, when the router pioneer became an acquisition force and transformed itself into a networking giant within a decade. Renesas, the semiconductor industry’s serial acquirer, has announced to snap PCB design toolmaker Altium nearly a month after announcing the purchase of gallium nitride (GaN) design house Transphorm.
Renesas has worked closely with Altium—headquartered in Las Jolla, California, and listed in Australia—for the past couple of years to standardize its PCB design and evaluation boards on the cloud-based Altium 365 platform. While implementing Altium’s uniform PCB design tool, the Japanese chipmaker aimed to streamline its reference designs and product kits in order to reduce design complexity and speed time to market.
In other words, by employing Altium’s cloud-based PCB design platform, Renesas wanted to harmonize the development workflow around its 400-plus evaluation board designs. Eventually, Renesas figured that it needed to own a design platform that’s efficient and easier to use. Moreover, owning a design software platform could become a competitive advantage in its bid to become a solutions provider instead of merely a chip vendor.
So, Renesas, which has been at the forefront of dealmaking in past years, decided to buy Altium for $5.9 billion in a cash deal. “This acquisition is different from our past acquisitions in many ways,” said Renesas CEO Hidetoshi Shibata.
Figure 1 Renesas acquires PCB tool developer Altium after using its cloud-based solutions for nearly two years.
First and foremost, it will diversify Renesas offerings into the software realm. That, in turn, will help design engineers easily integrate semiconductors into complex electronic designs while streamlining the overall design process. It’s worth mentioning here that Altium rejected a $3.9 billion takeover bid from software company Autodesk as too low back in 2021.
Altium’s origin can be traced to a startup, Protel, which was founded in 1985 by a University of Tasmania staffer, Nick Martin, who wanted to develop software for reducing PCB design complexity. The company was eventually renamed Altium and relocated to California.
Figure 2 Altium provides tools for designing circuit boards.
While Renesas has been acquiring semiconductor companies for nearly a decade, this deal tells a different story. It’s about a chip hardware outfit buying a design software firm to bolster its merits of being a solution provider and thus address pressures to lower design complexity and shorten time to market.
That makes sense because Renesas has been assimilating semiconductors from a multitude of suppliers: Intersil, IDT, Dialog, Sequans, and Transphorm. So, it’s crucial that design engineers using Renesas chips can better organize design kits, libraries, and other components effectively.
All this happens mostly at the board level, and Altium’s acquisition aims to facilitate that stage in the system design cycle. And Renesas has vetted these PCB design tools as their user for nearly two years.
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IEEE 1588 grandmaster clock handles 25 Gbps
Microchip’s TimeProvider 4500 (TP4500) is an IEEE 1588 PTP grandmaster clock that furnishes high-speed network interfaces up to 25 Gbps. The hardware timekeeping platform not only offers 1-Gbps, 10-Gbps, and 25-Gbps Ethernet options, but also achieves timing accuracy below 1 ns.
TP4500 gives infrastructure operators a terrestrial alternative for distributing precise time that is not dependent on GNSS. Highly scalable, the platform serves thousands of PTP endpoints for customers deploying C-band gNodeBs. Hardware-assist enhancements, including the latest digital synthesis technology and PolarFire SoC FPGA, allow the system to deliver sub-ns timing accuracy.
Oscillator options for the TP4500 include OCXO, super OCXO, and rubidium. The unit also incorporates a 72-channel GNSS receiver with active thermal compensation. TimePictra synchronization management software allows operators to monitor and track real-time faults and threats with visibility across their entire network.
The TimeProvider 4500 is available now for purchase. Contact a Microchip sales representative or authorized distributor.
TimeProvider 4500 product page
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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Platform simulates Wi-Fi 7 devices and traffic
The E7515W UXM wireless test platform from Keysight offers network emulation with Wi-Fi 7 signaling RF and throughput testing of Wi-Fi 7 devices. It performs Wi-Fi to application and Wi-Fi to cellular internetworking testing of both Wi-Fi clients (STAs) and Access Points (APs) from 380 MHz to 7.125 GHz.
As a turnkey system, the E7515W simplifies Wi-Fi 7 testing and provides insights for both the physical (PHY) and media access control (MAC) layers. The system emulates hundreds of clients at once through traffic simulation without the need for additional equipment. According to Keysight, this capacity exceeds existing market solutions by threefold.
Analysis software for the E7515W provides PHY/MAC level information, such as rate versus range, as well as enhanced Rx sensitivity, Wi-Fi 6/6E/7 radio unit sweep analysis, and full-rate throughput. Based on the same hardware architecture as the E7515B UXM 5G test platform, the E7515W tests more complex devices with 5G and LTE capabilities. It also performs fixed wireless access (FWA) testing for customer premise equipment (CPE).
Request a price quote for the E7515W Wi-Fi 7 test system using the link to the product page below.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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Fast SSD improves computer performance
Joining Samsung’s lineup of consumer SSDs, the 990 EVO delivers a sequential read speed of up to 5000 Mbytes/s, 43% faster than the 970 EVO Plus model. The company also reports that the 990 EVO offers up to a 70% improvement in power efficiency compared to its predecessor.
Available with storage capacities of 1 terabyte and 2 terabytes, the internal NVMe SSD enhances everyday computing experiences like gaming and video/photo editing. In addition to its fast sequential read rate, the drive’s sequential write speed reaches 4200 Mbytes/s. Random read and write operations also get a boost, with speeds of up to 700k and 800k input/output operations/s (IOPS), respectively.
Improved power efficiency allows battery-powered PCs to operate longer between charges. The 990 EVO supports Windows Modern Standby, which enables instant on/off with uninterrupted internet connectivity and seamless notification reception, even in low-power states. What’s more, the SSD’s heat spreader label effectively regulates the thermal condition of the NAND chip.
The 990 EVO supports both PCIe 4.0 x4 and PCIe 5.0 x2 interfaces. Samsung’s Magician software is a set of optimization tools to ensure the best SSD performance. It also streamlines the data migration process for SSD upgrades. Magician protects valuable data, monitors drive health, and provides notification of firmware updates.
The 990 EVO SSD will be available in Malaysia starting next month.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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Low-power MCUs perform diverse tasks
Built with an Arm Cortex-M33 core, NXP’s MCX A14x and A15x series of general-purpose MCUs operate at 48 MHz and 96 MHz, respectively. The devices target a broad range of applications, including motor control, industrial sensing, smart metering, automation, and smart home devices.
Both series offer high levels of integration with scalable device options. Peripherals include timers that generate three complementary PWM pairs with deadband insertion and a 4-Msample/s, 12-bit ADC with hardware windowing and averaging. Along with UART, SPI, and I2C interfaces, the MCUs provide an I3C communication interface. I3C improves on the performance and power use of I2C, while maintaining backward compatibility for most devices.
MCX A microcontrollers employ a capless LDO power subsystem that operates from 1.7 V to 3.6 V. Devices consume 59 µA/MHz (3 V, 25°C) in active mode running Coremark from internal flash. In deep sleep mode, current consumption drops to 6.5 µA with 10-µs wake-up and full SRAM retention (3 V, 25°C). Deep power down mode trims consumption to less than 400 nA with 2.78-ms wake.
Packaging options for the MCX A parts include 32-pin QFN, 48-pin QFN, and 64-pin LQDP. MCUs are I/O and pin-compatible across package types, simplifying migration and upgrades. MCX A14x/15x devices are available now through NXP’s distributor network.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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5G router streamlines industrial operations
Purpose-built for Industry 4.0 use cases, the Digi IX40 router provides global 5G and LTE connectivity with edge intelligence and real-time processing. The IoT cellular router allows enterprises to seamlessly connect multiple wired or wireless machines in demanding environments. It also optimizes the integration of cloud-delivered operational technology with information technology to enable network-wide visibility, monitoring, and control.
The IX40 provides edge intelligence by placing computing power in the device at the edge of the enterprise network where the data is collected. Processing sensor data immediately and closer to where it is generated (instead of sending it to the cloud), reduces latency. The router’s built-in computing power and integrated memory enable rapid machine-to-machine communication and robust real-time data processing.
Other Digi IX40 features include:
- FIPS 140-2 validation for encryption of sensitive data
- Ethernet, SFP, serial, I/O, and Modbus bridging
- Failover options like fiber and 4G LTE for redundancy
- GNSS receiver supporting GPS, GLONASS, BeiDou, and Galileo
- License-free enterprise software: VPN, firewall, logging, and authentication
- Digi Remote Manager for mass configuration and management of remote assets
Typical applications for the Digi IX40 router include advanced robotics, predictive maintenance, asset monitoring, industrial automation, and smart manufacturing. FirstNet-capable models are available for critical applications that require emergency response.
For more information or request a price quote, use the link to the product page below.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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Hotwire thermostat: Using fine copper wire as integrated sensor and heater for temperature control
Conventional thermostats are based on separate temperature sensor and heater devices with means for feedback between them. But in some recent EDN design ideas (DIs) we’ve seen thermostat designs that meld the functions of sensor and heater into a single active device (usually FET or BJT). The ploy can make a better fit to applications where the intended thermal load is physically small or has some other quirk of geometry that makes it inconvenient to apply the classic separate sensor/heater schema. This DI (see the figure) follows the melded concept but takes it in a somewhat different direction by using fine gauge copper wire (e.g., 40 AWG polyurethane insulated) as an integrated temperature sensor and heater.
Here’s how it works.
Miniature thermostat utilizing the tempco and I2R heating of 40 AWG copper wire as a melded sensor/heater.
Wow the engineering world with your unique design: Design Ideas Submission Guide
The resistance and temperature coefficient of a standard 40 AWG copper wire at 25 oC are generally spec’d at 1.07 Ω/foot and +0.393%/oC, respectively. Therefore, L feet of 40 ga can be expected to have an approximate resistance at a given temperature T of:
R(L,T) = 1.07 L(1 + 0.00393(T – 25)) (1)
R = 1.07 L + 0.00421 L T – 0.00421 L 25 (2)
T = (R – 1.07 L + 0.00421 L 25) / 0.00421 L (3)
T = (R – 0.965 L) / 0.00421 L (4)
Equation 4 holds well from R/L = 0.965 Ω/ft at 0o up to 1.6 Ω /ft at 155o (the recommended upper temperature limit for solderable polyurethane wire insulation).
Consider the implications for the use of fine copper wire as a combination temperature sensor and heater.
If a suitable length (between 5 and 15 feet) of wire is placed in a feedback loop driving current through it so as to dissipate enough I2R heating to raise and maintain a temperature that creates a preselected constant wire resistance, then said temperature, and the temperature of any thermal load thermally bonded to it, would likewise be constant! This is exactly what the circuit in the figure does.
Q1’s drain supplies heating; heating current I to the sensor/heater wire (please ignore for a moment the minor contribution from start-up resistor R2). The voltage induced between the terminals of the R wire resistance is then:
V = IR (5)
This causes the A1b, Q2 current source to output:
I2 = V/(R4 + R7) = IR/(R4 + R7) (6)
Which induces a voltage at pin 2 of A1b:
V2 = I2(R5 + R6) = IR(R5 + R6)/(R4 + R7) (7)
Meanwhile, Q1’s source current (also equal to I) sampling resistor R1 produces:
V3 = IR1 (8)
FET control amplifer A1a forces FET gate voltage and thereby R drive current such that:
V2 = V3 (9)
IR(R5 + R6)/(R4 + R7) = R1I (10)
R = R1(R4 + R7)/(R5 + R6) (11)
Thus, heater current, and therefore wire resistance and temperature, are forced to equilibrium values set purely by the resistance ratios listed in Equation 11, with the resultant constant temperature given by Equation 4.
About Q3. The thermostat circuit is intended to be as flexible as possible in regard to wire gauge, length and associated sensor/heater R resistance. To accommodate R < 10 Ω and consequent possibility of potentially damaging peak I values, Q3 removes Q1 gate drive when necessary and limits I to a safe ~1.4 A.
Setup and calibration. In further pursuit of flexibility in accommodating sensor/heater wire length and initial R, this simple calibration procedure is suggested for whenever the wire is replaced.
- Before first power up, allow sensor/heater to fully equilibrate to room temperature.
- Set R4 and R5 fully CCW.
- Push and hold the CAL NC pushbutton.
- Turn the power on.
- Slowly turn R4 clockwise until LED first flickers on.
- Release CAL.
Done. R5 is now “reasonably well” calibrated for a CCW to CW span of zero to 130oC above room temp.
Thermal coupling of the chosen length of sensor/heater wire to the desired thermal load (e.g., thermostated circuit component, test tube, petri dish, etc.) can be done by winding a meander of wire around the load, and securing it with polyimide tape, RTV silicone, or a similar heat tolerant adhesive.
And about R2. Although not significant in the steady state function of the circuit, without R2 the thermostat might be vulnerable to a failure to start when first switched on and might simply sit looking stupid. Indefinitely. Don’t ask how I know this…
Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.
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Indoor solar cells spur design-option reassessments
Conventional solar cells are just that: photovoltaic devices which, by their physics, extract and transform energy from the sun. Their sensitivity and efficiency are matched to the optical-energy spectrum of radiated and received power from the Sun to the extent possible, Figure 1.
Figure 1 The solar optical spectrum is complex and the available power per wavelength is a function of many factors. Source: Pennsylvania State University
In many small-scale applications, these same solar cells are used indoors and powered by ambient light from source’s overhead fixtures (which may be fluorescent or LEDs of various color temperatures), incandescent lamps (yes, some are still out there), diffuse or shaded natural light, and even specialized light such as halogen sources.
Given the indoor situation, two things are obvious:
- The designation as “solar” is somewhat of a misnomer since the Sun is no longer the source and so “photovoltaic” (PV) would be more accurate—but that’s the widely used, colloquial way of describing these cells.
- The energy spectrum of these indoor lighting sources is mismatched to the responsiveness of the solar cells, so efficiency is low.
While there have been some smaller, less-critical indoor products using solar power alone such as small calculators, such harvesting of ambient indoor optical energy is generally limited in its usefulness.
That situation may be changing as several companies have developed solar cells (we’ll stick with that misnomer) based on technologies which are very different from those used by conventional “real” solar cells. These indoor-optimized cells use complex layers of dyes along with specialized physical and chemical processes to achieve their indoor-optimized results.
Both Ambient Photonics (Scotts Valley, CA) and Exeger Operations AB (Stockholm) use variations of dye sensitized solar cell (shortened to DSC or DSSC) technology to produce light-sensitive cells which are optimized for indoor settings. The production process is a high-volume printing-like operation rather than the furnace-based process used for conventional solar cells.
Ambient says they have reinvented the chemistry of the dye sensitized solar cell (DSSC) with novel, proprietary molecules, using light-sensitive dyes to collect photons and convert them into electrons. In their electrochemical system, these light-sensitive dye molecules harvest and produce energy, with the dyes functioning similar to how chlorophyll behaves during photosynthesis in converting photons into energy.
They maintain that their energy-harvesting technology can harness photons across the light spectrum, yielding more than 90 percent conversion efficiency in low-light condition, even when compared to standard DSSC cells, Figure 2. They also function effectively despite the dynamic, changing indoor low-light conditions which are largely a function of the time of day.
Figure 2 Ambient says their DSSC process yields results which are superior to conventional film-based PV cells. Source: Ambient Photonics
Exeger’s dye sensitized solar cell uses a new architecture which they say improves real-life performance, provides greater flexibility, and offers seamless integration possibilities. In their approach, a unique conductive electrode material has replaced the traditional expensive and inefficient indium-tin-oxide (ITO) layer, Figure 3.
Figure 3 The Exeger’s process requires multiple layers of sophisticated materials and films and is compatible with mass production. Source: Exeger Operations AB
Dubbed Powerfoyle, it is flexible and durable and so can be integrated on curved surfaces such as headbands, Figure 4. It can be produced in sizes from 15 cm² to 500 cm², and therefore integrated into products ranging from small IoT sensors to speakers and larger accessories.
Figure 4 A bendable, flexible solar cell opens up new design-in and application opportunities. Source: Exeger Operations AB
For most design engineers, how these companies have achieved their indoor-friendly solar cells is not as important as what these innovations may do with respect to design options and degrees of freedom. Do power sources such as these enable increased consideration of IoT devices (sensors, trackers, shelf labels, and even remote controls) which do not need battery replacement, yet require more power other harvesting schemes (such as ambient RF-harvesting) support? For example, electronic door locks in hotels are an interesting possibility, as they are continually exposed to indoor lighting and used relatively infrequently; in theory, that’s a good combination of harvesting and use cycles.
Applications do not have to be limited to such small devices, either; Exeger has an agreement with a headphone manufacturer for ambient-powered units with the headband capturing ambient light. The same idea can be used for providing power to safety vests and alarm devices.
Of course, the energy source itself is only part of the harvesting chain. For designers, the dominant issue is not “how did they do it” but instead “what can it perhaps do for me?”; “what new opportunities does it provide?”; and “what do I need to do in my design to make use of this power source?”
For example, designers will have to decide on a suitable energy-storage and charging arrangement, whether using a rechargeable battery and the issues of limits on viable charge/discharge cycles, or a supercapacitor and the unique issues of using these non-chemical storage cells.
It will be interesting to see if these indoor-friendly solar cells become a standard part of the design-in possibilities, or if they have downsides which only become apparent when you get into the nitty-gritty design details of product design, manufacturing, use patterns, and long-term performance.
Do you see a viable energy-harvesting role for these non-Sun-driven solar cells? Would they allow you to create something you haven’t been able to do thus far? What possible design-in issues do you see?
Bill Schweber is an EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features.
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Will AI PCs be a new sweet spot for CPUs and DRAMs?
The personal computer (PC) industry is warming up to a new sweet spot: PCs incorporating artificial intelligence (AI) capabilities. Intel and Microsoft—the primary beneficiaries of the PC revolution—are now pushing PCs with AI-enabled CPUs and AI-powered software assistants, respectively, to move AI applications from the cloud to the PC realm.
In other words, AI PCs embedded with specialized chips can run AI models locally without relying on the cloud. That, according to Intel CEO Pat Gelsinger, will make AI services cheaper, faster, and more private than using services based in cloud-centric data centers. “You’re unleashing this power for every person, every use case, every location in the future,” he said at the CES 2024 in Las Vegas.
Intel, while competing with AI powerhouse Nvidia in server space, clearly sees an opportunity to catch up in its forte: PC processors. What it’s doing right now is integrating neural processor units (NPUs) into PC processors; NPUs are specialized semiconductors dedicated to handling AI tasks.
Intel’s Meteor Lake laptop CPU has incorporated an NPU to support third-party AI software features. Its archrival in the PC hardware space, AMD, has also been shipping AI PC processors. Next, Nvidia showcased three new GPUs—RTX 4060 Super, RTX 4070 Ti Super, and RTX 4080 Super—for AI-ready laptops at a virtual event before CES 2024.
Figure 1 Meteor Lake CPU has incorporated an NPU to support AI applications. Source: Intel
Besides AI-ready processors, memory chipmakers like Micron, Samsung, and SK hynix are also eyeing AI PCs to enable AI accelerators to run powerful assistants on personal computers. New laptops currently come with as much as 8 MB of RAM, and it’s likely to double in Windows-based AI PCs. In fact, a large language model (LLM) running an AI assistant could require more than 16 MB of memory.
Take the example of the Llama 2 family of AI models created by Meta, which requires nearly 30 GB of RAM for its modest variant. Moreover, the amount of memory in AI PCs will likely increase with the availability of more powerful AI accelerators and processors.
Figure 2 Copilot AI assistant is built around OpenAI’s GPT-4 model. Source: Microsoft
At the moment, consumers are only warming up to AI personal computers, and it’ll take a while before more native applications are made available for AI PCs. However, both hardware and software for AI PCs will become more powerful over time, and that’s good news for semiconductor devices like CPUs, GPUs, and DRAMs.
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Oscilloscope persistence displays
Persistence displays retain waveform traces on the screen, allowing them to decay over a user set time duration, they allow users to see a history of signal variations on the screen. This feature is very useful if you are adjusting a signal, as it allows you to see the changes as they are made. Some oscilloscope applications require displaying a history of events in order to see how the signal varies over time. Persistence displays are key tools for viewing such signal changes as a function of time over multiple acquisitions. The most common applications that use persistence displays include jitter analysis of a serial data transmission and eye diagrams used for digital communications systems (Figure 1).
Figure 1 The persistence display of timing jitter on an edge. Multiple acquisitions are retained on the display of the edge to show the variation in its timing. Source Arthur Pini
This is an analog persistence view of jitter on a clock edge, it is a monochrome display where the brighter areas are the more often occurring signal paths and the duller areas occur less often. The center area of the transition is brighter, meaning more edges pass at that time than during the times corresponding to the outer edges.
The same data can be viewed in color-graded persistence, a tool used to map the frequency of occurrence spectrally. Most frequent events appear in red while the least frequent events are shown in violet (Figure 2).
Figure 2 A color graded persistence display of the same edge jitter. The red areas occur more often than violet areas. Source Arthur Pini
The intermediate frequency of occurrence is mapped spectrally, from most to least often occurring as red-orange-yellow-green-blue-indigo-violet.
Multiple acquisitions are acquired and stored in a persistence map which shows signal variations over time. The persistence decay time is user-selectable with a time constant from half a second to infinite. A saturation control allows users to control the mapping of frequency of occurrence to intensity or color.
Eye and state transition diagrams
Persistence displays also help analyze data communications signals, where they are used to display eye diagrams and state transition diagrams (Figure 3).
Figure 3 The eye diagrams of the I and Q components and state transition diagrams of a 16-QAM signal rendered in monochrome analog persistence. Source: Arthur Pini
The eye diagrams of a 16-QAM signal show the results of 12,890 acquisitions of the I and Q signal components, which are also cross plotted as an X-Y plot, forming the state transition diagram shown in the upper right corner. Again, the intensity variations are proportional to the amount of time a waveform falls on a particular point on the display. The highly repetitive elements of a signal are brighter than the rarely occurring signal events. The data states, which appear as horizontal lines in the I and Q traces, are written more often and show up brighter than the transitions, which take different paths and occur with less frequency at any given point. The same is true of the state transition diagram where the data states appear as bright dots and the transition paths have a lower intensity.
Persistence histograms
All the data behind the persistence display is available and can be used to quantify the acquired data statistically. One example is to generate a histogram from the persistence display. The oscilloscope used in this article has a function called persistence histogram, it lets the user define either a horizontal or vertical slice through the
persistence display and then forms a histogram as shown in Figure 4.
Figure 4 A persistence histogram with a horizontal slice of the jitter persistence display centered at a level of 0 mV with a width of 10 mV. Source: Arthur Pini
The persistence histogram appears in the trace below the persistence display. Cursors are used to mark the location where the histogram slice originates. In a vertical slice, each bin of the histogram contains a class of related amplitude levels. A horizontal slice, used in the example, produces a histogram where each bin contains a class of related time values.
In the example, the vertical axis of the histogram reads the number of times a specific horizontal pixel is hit. The peak of the histogram corresponds to the central area with a light blue color, while the falling sides correspond to the persistence display changing from indigo to violet. The histogram can be measured using the oscilloscope’s measurement parameters, the measurement parameters P1 through P3 beneath the display grids read the mean, the standard deviation, and the range of the histogram. Parameter help markers annotate the locations of these measurements on the histogram itself.
Persistence histograms can also be applied to eye diagrams showing the horizontal timing uncertainty as well as the vertical deviation (Figure 5).
Figure 5 Application of persistence histogram to an eye diagram permits analysis of noise and jitter on the eye. Source: Arthur Pini
The histogram in the center trace was taken from a horizontal slice through the eye crossing and shows the range of variation in the time of the crossings. The lower histogram was taken using a vertical slice centered between the crossings, it shows the uncertainty in the amplitude of the eye in the center. Some oscilloscopes may not offer measurements that quantify eye characteristics such as eye height and width, .these can actually be obtained using persistence histograms and their associated statistical measurements.
Persistence trace functions
Persistence trace functions take the histogram of the persistence values over a number of vertical slices set by the user and extract the mean, standard deviation, and range of the persistence data at each slice. It then plots the extracted statistical parameter over time (Figure 6).
Figure 6 Examples of the persistence trace mean (second from the top), persistence trace sigma (third from the top), and persistence trace range (bottom) traces. Source: Arthur Pin)
The persistence trace mean function plots the mean value of the histograms at each of the user’s selected intervals. The resultant plot is the average value of the source persistence trace. In this example, the trace is taken from one thousand points along the persistence trace. This function shows the underlying waveform without vertical noise. Persistence trace sigma plots the minimum and maximum values of the standard deviation about the mean using an extrema plot. The plot shows mean + and – one standard deviation. This function provides a view of the rms noise on the source waveform. The persistence trace range plots the minimum and maximum values of the persistence histogram about the mean and shows the range of the histogram. It is the worst-case range of possible values, especially noise, at each point.
Persistence trace mean is the most useful of the functions allowing a quick determination of the average value of a persistence trace. It is also useful to smooth out traces acquired with low sample point counts (Figure 7).
Figure 7 The persistence trace mean shows all the possible states in waveform with a low sample count by retaining multiple acquisitions. Source: Arthur Pini
Waveforms with low sample counts, displayed with linear interpolation, may appear angular and discontinuous however they are not, and over multiple acquisitions, they trace a smooth waveform. Using persistence trace mean to view the waveform allows the persistence history to fill in the intermediate states and smooth the waveform, showing its actual structure.
3-D persistence display
Adding vertical height to a persistence display proportional to the rate of occurrence gives you a three-dimensional (3-D) effect. This 3-D persistence display creates a topographical view of your waveform.
As shown in Figure 8, this is most useful when studying X-Y plots of signals such as QPSK.
Figure 8 The in-phase and quadrature components of a QSPK signal and a three-dimensional persistence plot of a QPSK state transition diagram. Source: Arthur Pini
The three-dimensional plot retains the color or intensity coding of the persistence displays but adds height proportional to the frequency of occurrence of the display pixels. The shape of these peaks provides an alternative view of the frequency of occurrences in your signals. In this example, the data states of the signal which occur most frequently appear as the highest elements in the X-Y display and are coded in red. Transition paths have more variation and occur less repetitively. They are lower on the display and coded in yellow/green. Off path regions are at the bottom of the display, coded in violet. Controls allow for rotating the 3-D plot to view it from different angles.
The 3-D display can be rendered in three different qualities. The first is as a solid, as is shown, and is the default quality. It can also be rendered in the wireframe quality; this is constructed using lines of equal intensity to create the persistence map. The third quality is shaded, which is only available in monochrome persistence. Shaded quality shows the 3-D object as if it were illuminated by projected light, the shading emphasizes the shape of the object.
The value of persistence displays
Whether used to measure jitter, eye diagrams, or state transition diagrams, persistence is a valuable display technique. When combined with math persistence analysis tools and related measurements, it becomes a powerful tool for quantifying signal variations.
Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.
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Current sensors cover DC to 5 MHz
Two wideband current sensors from Allegro, the ACS37030 and ACS37032, ensure efficiency and reliability in GaN and SiC FET power architectures. With an operating bandwidth of DC to 5 MHz, the devices are suitable for electrified vehicles, clean energy solutions, and data center applications.
The ACS37030 and ACS37032 offer current sensing ranges of ±20 A, ±40 A, and ±65 A, with a typical response time of 40 ns. Both devices employ dual signal paths. One path captures low-frequency and DC current using Hall-effect elements. The other path captures high-frequency current data through an inductive coil. These two paths are summed to enable sensing from DC to 5 MHz in a single device.
The current sensors achieve stable and safe control, while reducing EMI. Sensitivity error over temperature is ±2%. The properties of the inductive coil increase signal to noise ratio (SNR) as frequency increases, minimizing noise at the output. The ACS37030 provides a zero current reference output, while the ACS37032 offers an overcurrent fault output.
Housed in compact 6-pin SOIC packages, the sensors have a rated isolation voltage of 3500 VRMS and a basic working voltage of 840 VRMS. They operate over a temperature range of -40° to +150°C. To learn more about the ACS37030 and ACS37032 current sensors, click here.
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PAM4 DSP toolkit optimizes cable design
MaxLinear is offering a product design kit (PDK) to help cable manufacturers integrate the Keystone PAM4 DSP into their active electrical cables. According to MaxLinear, the 5-nm PAM4 DSP can yield up to a 40% power savings over competitor solutions when used in active electrical cable (AEC) applications.
Unlike passive cables, active electrical cables actively boost signals, allowing for longer distances (up to 7 meters for 400G); higher bandwidth; and thinner, lighter cables. Keystone PAM4 DSPs based on 5-nm CMOS technology enable designers to build high-speed cables that maximize reach and minimize power consumption in next-generation hyperscale cloud networks. To ease DSP integration, the PDK includes strong application support, multiple tools to optimize and monitor performance, and both hardware and software reference designs.
Keystone 5-nm DSPs cater to 400G and 800G applications and provide a 106.25-Gbps host-side electrical I/O that aligns with the line-side interface rate. Variants support single-mode optics (EML and SiPh) and multimode optics (VCSEL transceivers and AOCs), as well as AECs. The family also includes companion transimpedance amplifiers.
For more information about the Keystone 5-nm PAM4 DSPs (MxL93642, MxL93643, MxL93682, and MxL93683), click here.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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LTE-M module integrates GNSS receiver
Sara-R520M19, an LTE-M and NB-IoT module from Swiss provider u-blox, delivers accurate positioning data concurrent with LTE communication. Simultaneous GNSS and cellular connectivity is an important factor for applications requiring continuous or cyclic tracking, such as utility metering and asset tracking.
The Sara-R520M10 module incorporates the company’s UBX-R52 cellular chip, M10 GNSS receiver, and dedicated GNSS antenna interface in a 16×26×2.2-mm, 96-pin LGA package. A variant without the GNSS receiver, the Sara-R520, is also available for general-purpose applications. This model features SpotNow, an assisted GPS receiver for applications requiring occasional tracking.
The Sara-R52 series offers 23 dBm of RF output power to ensure stable connectivity. Modules include an Open CPU (uCPU) feature that allows users to run their own software on the chip without the need for an external MCU. An onboard smart connection manager performs automatic connectivity management. Its function is to achieve either the best performance or the lowest power consumption. This is useful when a connection is lost and needs to be re-established.
In addition to the Sara-R52 series, u-blox released the Lexi-R520 LTE-M module. The Lexi-R520 furnishes the same features as the Sara-R520, but in a smaller form factor. Its 16×16×2-mm, 133-pin LGA package lends itself to applications like wearables.
Samples of the LTE-M modules are available now, with volume production scheduled for Q3 2024.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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16-bit audio ADC detects breaking glass
Asahi Kasei’s AK5707 ADC packs an acoustic activity analyzer (AAA) that can be configured to detect specific types of acoustic events, such as breaking glass. This integrated analog acoustic event detector makes the AK5707 16-bit monaural ADC well-suited for IoT security applications, like wireless cameras and smart doorbells.
Consuming just 34 µA, the AK5707’s AAA block listens for acoustic events that fit user-customizable profiles. Upon detection, the AAA activates the ADC and initiates recording to an integrated audio buffer. Simultaneously, it generates an interrupt to wake the external SoC.
Unlike typical loudness-based detection, the AAA constantly tracks the current noise floor and adjusts its detection parameters in response. AAA detection not only reduces false positives, but also increases battery life in noisier environments. Asahi Kasei offers a suite of detection profiles for the AAA, including glass-break, alarm patterns, crying baby, and human voice. These profiles are configurable, with multiple acoustic parameters set by the user.
The 16-bit, 48-kHz ADC block of the AK5707, which can be powered on and off independently of the AAA, achieves a signal-to-noise ratio of 95 dB, while consuming only 200 µA. Built-in AC coupling capacitors allow for a 3.2 mm2 PCB area, including one external capacitor.
The AK5707 comes in a tiny 1.53×1.58-mm WLCSP. It is currently sampling, with mass production scheduled to begin in September 2024.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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Reference design serves Lunar Lake CPU
Cirrus Logic, Intel, and Microsoft are developing a reference design that teams Intel’s forthcoming Lunar Lake processor with Cirrus audio and power devices. The reference platform will help developers create more immersive audio for laptop PCs, while reducing heat generation and extending battery life to enable smaller, thinner designs.
Claiming to bring best-in-class audio to more PCs, the reference design employs the Cirrus Logic CS42L43 SmartHIFI codec, CS35L56 audio amplifier, and CP9314 switched-capacitor power converter. The codec and audio amplifiers deliver louder bass, clearer voice, and lower distortion to both the speaker and the headset. The power converter promises to reduce power and heat, as well as fan noise.
In addition, the audio design will assist with the transition to the MIPI SoundWire interface and Microsoft’s ACX (audio class extension) framework. Along with built-in security features, the design supports next-generation features like spatial audio. It is scalable across different processors, speakers, and notebook designs, allowing OEMs to implement audio subsystems that scale in channel count and features.
Intel’s Lunar Lake processor for portable PCs is expected to launch later this year.
Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.
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Parsing PWM (DAC) performance: Part 2—Rail-to-rail outputs
Editor’s Note: This a four-part series of DIs proposing improvements in the performance of a “traditional” PWM—one whose output is a duty cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to produce a DAC. This second part addresses the inability of “rail-to-rail” op amps’ output swing to encompass supply rail voltages.
Part 1 can be found here.
Recently, there has been a spate of design ideas (DIs) published that deal with microprocessor (µP)-generated pulse width modulators driving low-pass filters to produce DACs. Approaches have been introduced which address ripple attenuation, settling time minimization, and limitations in accuracy. This is the second in a series of DIs proposing improvements in PWM-based DAC performance. Each of the series’ part’s recommendations are, and will be, implementable independently of the others. This DI addresses the inability of “rail-to-rail” op amps’ output swings to encompass their supply rail voltages. Recognizing that an op amp is needed to buffer a filter from a DC load to prevent load-induced errors, and that these devices are useful in implementing more effective analog filters, there is a legitimate interest in mitigating or eliminating this imperfection.
Wow the engineering world with your unique design: Design Ideas Submission Guide
It don’t mean a thing if it ain’t got that swing (well, sort of…)
The common mode input voltages of many rail-to-rail op amps may be 100 mV above their positive and below their negative supply rails, but none have an output common mode voltage range which includes those rails. The OPA376, 2376, and 4376 rail-rail family with its excellent input offset voltage and bias current ratings are no different. The SC70-5, SOT23-5, and SO-8 package versions reach within 40 mV of the rails with a 10 kΩ load from -40°C to 125°C, and within 50 mV with a 2 kΩ load. There are various means of dealing with this limitation.
In the spirit of “Doctor, it hurts when I do this”, “Then don’t do that!”: software could simply prevent the setting of duty cycles which would drive the op amp too near a supply rail. This is rather unsatisfactory if the code which generates the duty cycle values expects that the values of zero and full scale (FS) will be executable. So, suppose an op amp can swing to within X mV of both its positive rail (VDD) and ground; instead of programing the PWM counter with a value of DC, program it with DC’ = DC · (1 – α) + α · FS/2, where α = X mV · 2 / VDD.
If that calculation imposes an unacceptable software burden, there is a related analog approach. In Figure 1, set R = r · α / (1 – α). The full range of DC values is now restricted to a range that the op amp output can replicate.
Figure 1 A purely analog means of avoiding op amp input voltages so close to the supply rails that the output cannot replicate them.
If the resistors have a 0.1% tolerance, the maximum offset error is a little greater than 2-15· VDD. The gain error is larger though: a little less than 2-10 · VDD. With adequate calculation resolution, the method of scaling the duty cycle count in software leads to smaller errors than the purely analog one.
In some applications, it is imperative that a DAC can swing to ground. In others, it must also be able to reach the µP’s positive rail, VDD. To accomplish this, voltage(s) beyond (a) supply rail(s) must be generated. But in no case can the supply voltages’ range exceed that recommended for the op amp, which is 5.5 V for the OPAx376 family. This necessitates different solutions for the common VDD supply values of 1.8, 2.5, 3.3 and 5.0 V. We will now follow with a series of schematics that contain solutions for each of these voltages…
The circuitry for the op amp positive rail (OP+) can be ignored in favor of VDD if the DAC needn’t swing to VDD. Texas Instruments’ LM7705 provides a complete and elegant means of generating a voltage that is only slightly more negative than ground, thereby allowing the op amp output to reach 0 V (Figure 2). This charge pump accepts a supply voltage of from 3 to 5.25 V and provides a regulated output of -230 mV at up to 20 mA. The LM7705 offer features beyond those of a simple charge pump inverter (which requires an external oscillator) in that:
- An inverter sets the negative rail supply voltage to be the negative of the positive supply voltage. At VDD = 3 V and above, 3 V – (-3 V) exceeds the OPAx376’s family’s maximum differential supply voltage VOpRange of 5.5 V. The LM7705 provides just enough negative voltage and no more than is needed.
- The LM7705 has a smaller footprint and incorporates an oscillator and a regulated DC output into a single IC.
Figure 2 This simple and inexpensive inverting charge pump provides a regulated -0.23 V for a rail-to-rail op amp’s negative supply so that the op amp output can swing to, and even below, ground.
But an application might also require swinging to the positive rail. The need to avoid supply voltage ranges exceeding 5.5 V for the OPAx376 leads to different solutions for different values of VDD (always assumed to be within +/- 5% of nominal value). The simplest solution is for the case of VDD equal to 1.8 V (Figure 3).
Figure 3 Solution for staying within the supply operating range for the OPAx376 where VDD = 1.8 V.
The LM2664 is a voltage inverter generating -VDD from + VDD. With the addition of D1, D2, C3 and C4, a voltage of 2 · VDD – 2 · Vd is generated where Vd is the voltage drop across the diodes. OA+ is enough above VDD to allow the op amp output to include the positive rail. The difference between OA+ and OA- is safely within supply operating range (VOpRange) for the OPAx376. If your VDD is between 1.8 and 5.5 V and is less than 1/3 of the VOpRange of your op amp, this simple and cheap circuit could be all you need. But if not…
As shown in Figure 4, the same circuit is the basis for operation from a 2.5V supply, but accommodations must be made to meet VOpRange for the OPAx376. This is accomplished by adding D3 and D4 to incur voltage drops.
Figure 4 Solution for staying within the supply operating range for the OPAx376 where VDD = 2.5 V.
Combinations of +/-5% variations in VDD, tolerances in diode voltage drops, and variations over temperature and load of the above circuit’s output voltages warn against applying the strategy of adding more diodes in series for the case where VDD increases to 3.3V (Figure 5).
Figure 5 Solution for staying within the supply operating range for the OPAx376 where VDD = 3.3 V.
Here the LM2664 performs the same function as it did for a VDD of 1.8 and 2.5 V. But it powers a cheap op amp IC which functions as a positive and a negative voltage regulator. The R6 / R7 divider ensures that the LM358BI operates within its common mode input range. (Its VOpRange is greater than 30 V!) OA+ and OA- voltages are approximately 100 mV beyond VDD = 3.3 V +/-5% and ground. Q1 and Q2 are placed in feedback loops to reduce the regulator output impedance. Since the op amp rails should be decoupled with ground-referenced .1 µF capacitors, this reduced impedance increases the loop’s high frequency break point. The result could be unstable were it not for the combination of C5 and R3 and that of C6 and R1. These pairs filter out the high phase-shift, high frequency feedback taken from the emitters and ensure that only mid frequencies down to DC are being regulated, thus establishing stability. In this circuit, the resistors are 1% tolerance parts.
As shown in Figure 6, the circuit for a 5 V VDD is similar to that for 3.3 V, but simpler. Here the higher Pump+ voltage means that there are no worries about input common mode operation, and we can dispense with R6 and R7. The passive components that make up the regulators are now identical.
Figure 6 Solution for staying within the supply operating range for the OPAx376 where VDD = 5 V.
Encompassing supply rail voltages
In this DI, several different approaches have been presented for producing DACs whose voltage swings encompass supply rails, or at least mitigate the problems associated with those that don’t. Hopefully, one or more are suitable for your application.
Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.
Related Content
- Parsing PWM (DAC) performance: Part 1—Mitigating errors
- A simple, accurate, and efficient charge pump voltage inverter for $1 (in singles)
- Double up on and ease the filtering requirements for PWMs
- Optimizing a simple analog filter for any PWM
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Neon lamp blunder
There was this test system that comprised a huge row of equipment racks into which various items of test equipment would be mounted. Those items were a digital multimeter, an oscilloscope, several signal generators and so forth. Each section of the rack assembly had a neon lamp mounted at its base which was supposed to indicate that 400 Hz AC line voltage was turned on or turned off for the equipment mounted in that rack section.
Planned essentially as follows in Figure 1, the idea did not work.
Figure 1 Neon lamp indicator plan where line voltage was always present and applied to the equipment installed within each section via a power relay where singular SPST contact set operated that section’s neon lamp.
Line voltage was always present but would be applied to installed equipment within each section via a power relay of which one SPST contact set was to operate that section’s neon lamp. The problem was that each section’s neon lamp would always stay lit, no matter the state of the relay and the state of equipment power application.
No neon lamp would ever go dark.
There was much ado about this with all kinds of accusations and posturing, finger pointing, scoldings, searching for a fall guy and so forth but the problem itself was never solved. What had been overlooked is shown as follows in Figure 2.
Figure 2 The culprit was the stray capacitance from the wiring harness that each SPST contact was wired through that kept each neon lamp visibly lit.
Each SPST contact was wired through a harness which imposed a stray capacitance across the contacts of the intended switch. When the SPST was set to be open, that stray capacitance provided a low enough impedance for AC current to flow anyway and that current level was sufficient to keep the neon lamp visibly lit.
Brilliant, huh?
John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).
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∆Vbe differential thermometer needs no calibration
Differential temperature measurement is a handy way to quantify the performance of heatsinks, thermoelectric coolers (TECs), and thermal control in electronic assemblies. Figure 1 illustrates an inexpensive design for a high-resolution differential thermometer utilizing the ∆Vbe effect to make accurate measurements with ordinary uncalibrated transistors as precision temperature sensors.
Here’s how it works.
Figure 1 Transistors Q1 and Q2 perform self-calibrated high resolution differential temperature measurements.
Wow the engineering world with your unique design: Design Ideas Submission Guide
Diode connected transistors Q1 and Q2 do duty as precision temperature sensors driven by switches U1and U1c and respective resistors R2, R3, R13, and R14. The excitation employed comprises alternating-amplitude current-mode signals in the ratio of (almost exactly):
10:1 = (100 µA via R3 and R13):(10 µA via R2 and R14).
With this specific 10:1 excitation, most every friendly small-signal transistor will produce an AC voltage signal accurately proportional to absolute temperature with peak-to-peak amplitude given by:
∆Vbe = Absolute Temperature / 5050 = 198.02 µV/oC.
The temperature-difference-proportional signals from Q1 and Q2 are boosted by ~100:1 gain differential amplifier A1a and A1d, synchronously demodulated by U1b, then filtered by R11, C2, and C3 to produce a DC signal = 20 mV/oC. This is then scaled by a factor of 2.5 by A1c to produce the final Q1–Q2 differential temperature signal output of 50 mV/oC, positive for Q1 warmer than Q2, negative for Q2 warmer than Q1.
Some gritty design minutiae are:
- Although the modulation-current setting resistors are in an exact 10:1 current ratio, the resulting modulation current ratio isn’t quite…The ∆Vbe signal itself subtracts slightly from the 100 µA half-cycle, which reduces the actual current ratio from exactly 10:1 to 9.9:1. This cuts the ∆Vbe temperature signal by approximately -1%.
- Luckily, the gain of the A1a/d amplifier isn’t exactly the advertised 100 either but is actually (100k/10k + 1) =101. This +1% “error” neatly cancels the ∆Vbe signal’s -1% “error” to result in a final, acceptably accurate 20mV/oC demodulator output.
- The modulating/demodulating frequency Fc generated by the A1b oscillator is deliberately set by the R4C1 time constant to be half the power mains frequency (30 Hz for 60 Hz power and 25 Hz for 50 Hz) via the choice of R4 (160 kΩ for 60 Hz and 200 kΩ for 50 Hz). This averages a couple mains-frequency cycles into each temperature measurement and thus improves immunity to stray pickup of power-line coupled noise. It’s a useful trick because some differential-thermometry applications may involve noise-radiating, mains-frequency-powered heaters. For convenience, the R5/R6 ratio was chosen so that Fc = 1/(2R4C1).
- Resistor values adorned with an asterisk in the schematic denote precision metal-film types. Current-ratio-setting R2, R3, R13, and R14 are particularly critical to minimizing zero error and would benefit from being 0.1% types. The others are less so and 1% tolerance is adequate. No asterisk means 5% is good enough.
Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.
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Faraday to manufacture 64-bit Arm processor on Intel 1.8-nm node
The paths of RISC processor powerhouse Arm and x86 giant Intel have finally converged after they signed a collaboration pact to manufacture chips on Intel’s 1.8 nm process node in April 2023. Hsinchu, Taiwan-based contract chip designer Faraday Technology will manufacture Arm Neoverse cores-based server processors on Intel Foundry Services (IFS) using the Intel 18A process technology.
Chip design service provider Faraday is designing a 64-core processor using Arm’s Neoverse Compute Subsystems (CSS) for a wide range of applications. That includes high-performance computing (HPC)-related ASICs and custom system-on-chips (SoCs) for scalable hyperscale data centers, infrastructure edge, and 5G networks. Though ASIC designer won’t sell these processors, it hasn’t named its end customers either.
Figure 1 Faraday’s chip manufactured on the 18A process node will be ready in the first half of 2025. Source: Intel
It’s a breakthrough for Arm to have its foot in the door for large data center chips. It’s also a design win for Arm’s Neoverse technology, which provides chip designers with whole processors unlike individual CPU or GPU cores. Faraday will use interface IPs from the Arm Total Design ecosystem as well, though no details have been provided.
Intel, though not so keen to see Arm chips in the server realm, where x86 chips dominate, still welcomes them to its brand-new IFS business. It will likely be one of the first Arm server processors manufactured in an Intel fab. It also provides Intel with an important IFS customer for its advanced fabrication node.
Intel’s 18A fabrication technology for 1.8-nm process node—boasting gate-all-around (GAA) RibbonFET transistors and PowerVia backside power delivery—offers a 10% performance-per-watt improvement over its 20A technology for 2-nm process. It’s expected to be particularly suitable for data center applications.
Figure 2 The 18A fabrication technology is particularly considered suitable for data center chips. Source: Intel
Intel has already got orders to manufacture data center chips, including one for 1.8-nm chips from the U.S. Department of Defense. Now, a notable chip designer from Taiwan brings Intel Arm-based chips, boosting IFS’ fabrication orders as well as its credentials for data center chips.
The production of this Faraday chip is expected to be complete in the first half of 2025.
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