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Моделюють ризики, вивчають наслідки, прогнозують майбутнє
Науковий простір Київської політехніки розширює свої горизонти: магістрантка кафедри математичного моделювання та аналізу даних НН ФТІ Софія Дрозд, що працює під науковим керівництвом завідувачки кафедри професора Наталії Куссуль, успішно презентувала Київську політехніку на Африканському контине
Pat Gelsinger: Return of the engineer CEO that wasn’t
After more than three years at the helm, Intel’s charismatic and ambitious chief Pat Gelsinger has stepped down and the faltering American semiconductor icon is starting to look for his replacement. It’s not a coincidence that this year Intel will announce its first annual loss since 1986; analysts expect Intel to lose $3.68 billion in 2024.
Intel is a semiconductor industry pioneer with luminaries like Robert Noyce, Gordon Moore, and Andy Grove in its fold. While the case for Craig Barrett, who took over reins from Grove in 1998, hangs in balance, the downfall at Intel’s top spot began with Paul Otellini, who was widely known to refuse Apple to supply chips for iPhones due to a perceived lack of volume.
The downward trend at Intel’s corner office continued under Brian Krzanich and Bob Swan, and then Gelsinger came along with a big bang. Gelsinger, who joined Intel in 1979 at the age of 18 with an associate’s degree from Lincoln Tech, was the lead architect of Intel’s fourth-generation 80486 processor launched in 1989. He also became Intel’s youngest vice president at the age of 32.
Gelsinger continued to rise through the ranks and became the Santa Clara, California-based chipmaker’s first chief technology officer (CTO) in 2001. That’s also when his career’s first anticlimax began. So, restless Gelsinger chose the path of upward mobility by leaving Intel in 2009 and becoming EMC’s president and CFO.
Figure 1 Gelsinger (second from right) is seen with the 386 processor development team. Source: Intel
In 2012, he got the top job at VMware, and after nine years at this cloud computing firm, he returned to then troubled Intel as the turnaround CEO. After the Intel board ousted Bob Swan, who had a finance background, Gelsinger came on board with great expectations. He was being hailed as the engineer CEO taking the reins of an American icon with engineering roots. However, in retrospect, that proved easier said than done.
Intel’s foundry business, the linchpin of Gelsinger’s turnaround plan, is now the elephant in the room, and there is no viable remedy in sight. Besides the semiconductor contract manufacturing business that he envisioned to turn the corner at Intel, other critical areas relate more to execution than vision.
Below is a brief snapshot of the debacles that happened under Gelsinger’s watch:
- Intel, the CPU company by its heritage, has been losing market share in PC and data center processors to competitor AMD. Moreover, x86 rival Arm is making inroads in the highly lucrative server and data center markets.
- Intel seems to have missed the AI wave, and its Gaudi AI accelerators haven’t been selling well.
- While Gelsinger spent a lot of time rubbing shoulders with politicians, his inept remarks about Taiwan’s precarious relations with China offended TSMC, leading Intel to lose massive discounts from the mega-fab for the manufacturing of its processors.
- Intel is also known to have failed in sealing chip supply deals with Sony for the PlayStation console and Waymo for self-driving vehicles.
- In 2023, Intel had to cancel its bid to acquire Israel-based fab Tower Semiconductor for $5.4 billion due to regulatory issues. As a result, it was forced to pay $353 million as the termination fee.
Now, back to the elephant in the room: Intel’s foundry business currently in transition to become an independent subsidiary due to shareholder pressure. It’s probably the straw that broke the camel’s back. Chip contract manufacturing is a long-term business with massive capital investment, and time isn’t apparently on Intel’s side.
More specifically, Intel’s much-publicized 18A process node has announced only a single tape-out while large potential customers such as Apple and Qualcomm are reported to have passed on 18A for technical reasons. The trade media is abuzz about reliability issues facing 18A, and Intel’s isn’t expected to manufacture chips in volume on this node until 2026.
Figure 2 Gelsinger’s departure marks his 45 years of work in the tech industry. Source: Intel
While technology and trade media outlets have seen Gelsinger’s ouster with an element of surprise, we at EDN saw it coming much earlier. Our story “Intel: Gelsinger’s foundry gamble enters crunch,” published on 4 November 2024, offered a blueprint of this inevitable ouster announced on 2 December 2024.
We also think that Intel’s problems aren’t unsolvable. Gelsinger’s successor must avoid grand plans and focus on perseverance, innovation, and execution. Lisa Su did that at Intel’s archrival AMD during the past few years.
Related Content
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- Intel Paints Their AI Future with Gaudi 3
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- Intel unveils service-oriented internal foundry model
The post Pat Gelsinger: Return of the engineer CEO that wasn’t appeared first on EDN.
Single-supply single-ended input to pseudo class A/B differential output amp
From the micromixer topology by Barrie Gilbert [1], this amplifier allows a single-ended input to be converted to a Class A/B current output from a single supply.
Wow the engineering world with your unique design: Design Ideas Submission Guide
As shown in Figure 1 with an LTspice implementation, the circuit employs 6 bipolar transistors (BJTs) in a unique configuration which “directs” the output current from Q3 and Q4 dependent upon input polarity.
Figure 1 LTspice schematic of the micromixer topology with 6 BJTs arranged such that the output current from Q3 and Q4 are dependent upon input polarity.
How it worksC1 serves as a decoupling capacitor which allows the potential at Q1 base to vary from the biased Vbe with the Q1 diode connection. Q2 acts as a mirror to Q1 for positive input signals and cuts off for large negative inputs; while Q3 is a cascode under small signal conditions, and sources large negative input currents.
With ideal equal-sized transistors, all collector currents are equal and set by the base-emitter voltages of Q5 plus Q6, which are determined by the current through R3 as Ibias.
When the input signal is large and positive, input current flows mostly through Q1 which acts as a transconductor and cascode device and Q3 becomes cutoff as its emitter voltage rises. Q2 “mirrors” the Q1 collector current through cascode device Q4, which sinks a replica of the large positive input current as the positive output.
Large signal inputsOn large negative inputs, all the input current is sourced by Q3 as its emitter voltage drops and Q1 becomes cutoff, with Q3’s collector sinking the negative output (Figure 2). Note that for large positive inputs, the output currents are “directed” to either Q4 (+) or Q3(-) and unlimited with ideal devices.
Figure 2 LTspice simulation of differential output in response to large negative signal inputs.
Small signal inputsAs shown in Figure 3, with smaller inputs, the circuit acts like a small signal Class A type as all the transistors operate with an Ibias collector current. So, with zero input current, both Q1 and Q3 conduct Ibias, as does Q2 and Q4 and the circuit acts with a differential output.
Figure 3 LTspice simulation of differential output in response to small negative input current.
Actual resultsFigure 4 shows actual results from the circuit in Figure 1, shown on a DSO with a sine-wave input of 2Vpp @ 1KHz. Figure 5 shows the LTspice simulation results of Figure 1. Note the LTspice plots were set up with color and display offset bias to match DSO display for comparisons.
Figure 4 Actual results of Figure 1 schematic shown on a DSO with a sine-wave input of 2Vpp @ 1KHz.
Figure 5 LTspice simulation results of Figure 1 where the plots were set up with color and display offset bias to match DSO display for comparisons
Also note the slight “cross over distortion” shown in both the DSO and LTspice results—common to conventional Class A/B stages. This can be improved with a higher Ibias at the expense of higher amplifier dissipation.
This topology offers additional features other than just single-to-differential Conversion [1]. It addresses the dynamic input impedance as a function of instantaneous input signal level; an area often not addressed in conventional amplifier discussions.
Signal induced distortion begins with the effective amplifier input impedance changing with dynamic signal level and working against the source impedance creating a non-linear signal dependent voltage/power divider which modulates the input signal level.
Improving input impedanceFigure 6 shows a version where additional resistors are added to improve the input impedance variation with input signal level [2]. Note the inclusion of additional resistors to help balance the input impedance variations over large input signal swings while still maintaining an equal collector current bias for each device as determined by Ibias.
Figure 6 A high dynamic range amplifier with additional resistors to help balance the input impedance variations over large input signal swings while still maintaining an equal collector current bias for each device as determined by Ibias.
As shown in Figure 7 and Figure 8, the LTspice input impedance results were created by taking the derivative of input voltage with respect to input current as the input is swept across a large positive and negative range.
For more details see references [1] and [2].
Figure 7 Small signal input impedance results and output differential current.
Figure 8 Large signal +10 V peak input impedance results and output differential current.
High bandwidth and dynamic range single-to-differential amplifier circuitThese circuits operate in the “current domain” and can offer very high bandwidths with high dynamic range at low static power dissipation from a single supply. In the distant past, the author has implemented this with high frequency SiGe bipolar transistors in a BiCMOS process with good results.
Michael A Wyatt is a life member with IEEE and has continued to enjoy electronics ever since his childhood. Mike has a long career spanning Honeywell, Northrop Grumman, Insyte/ITT/Exelis/Harris, ViaSat and retiring (semi) with Wyatt Labs. During his career he accumulated 32 US Patents and in the past published a few EDN Articles including Best Idea of the Year in 1989.
Related Content
- Simple 5-component oscillator works below 0.8V
- Applying fully differential amplifier output-noise analysis to drive high-performance ADCs
- Differential vs. single-ended data transfer: What’s the difference?
- Understanding output filters for Class-D amplifiers
- Distortion in power amplifiers, Part I: the sources of distortion
- Loudspeakers: Effects of amplifiers and cables – Part 5
References
- Chen, M. R. D. Rodrigues and I. J. Wassell, “A Frechet Mean Approach for Compressive Sensing Date Acquisition and Reconstruction in Wireless Sensor Networks,” in IEEE Transactions on Wireless Communications, vol. 11, no. 10, pp. 3598-3606, October 2012, doi: 10.1109/TWC.2012.081612.111908.
- https://www.eevblog.com/forum/projects/interesting-amplifier-topology/
The post Single-supply single-ended input to pseudo class A/B differential output amp appeared first on EDN.
Міжнародний іспит з японської мови в КПІ ім. Ігоря Сікорського
Кваліфікаційний іспит з японської мови (Japanese-Language Proficiency Test) — це міжнародний стандартизований іспит на підтвердження рівня знань японської мови, що з 1984 року відбувається одночасно в усьому світі серед осіб, для яких японська не є рідною.
Japan investing ¥70.5bn in ¥211.6bn joint DENSO–Fuji Electric plan to boost SiC power semi production
EEVblog 1655 - TIP: Discharge Capacitors SAFELY using ANY Multimeter!
Форум інженерів–механіків 2024
КПІ ім. Ігоря Сікорського вкотре стає центром наукових інновацій та передових технологій у машинобудуванні та авіації, організовуючи масштабні інженерні форуми, як-от Форум інженерів–механіків — щорічний захід від Навчально-наукового механіко-машинобудівного інституту КПІ ім. Ігоря Сікорського.
QPT files patent for die attach process that boosts waste heat removal by up to 15x
Energizer’s PowerSource Pro Battery Generator: Not bad, but you can do better
Back in August, EDN published my coverage of the SLA (sealed lead acid) battery-based Phase2 Energy PowerSource 660Wh 1800-Watt Power Station on sale for $149.99 plus tax at bargains site Meh:
I hypothesized at the time that both it and a Duracell-branded clone, which originally sold for $699.99, were private-label brands of a common design originally sourced from a company called Battery-Biz. And toward the end of that same writeup, I also mentioned a couple of lithium battery-based successor power sources, also Battery-Biz-sourced, among them a $599.99 (versus $1,899.99 original MSRP, believe it or not) Energizer-branded bundle with a 200W solar cell that was also at the time being discount-sold by Meh:
That initial limited-time promotion has subsequently been resurrected several more times (that I’ve seen, maybe more than that) by Meh to date. Why? I’ll let them explain in their own words:
We’ve offered this a bunch now, but we haven’t seen any real drop-off in sales.
The third time I saw it, I decided to take the plunge. The second time, it had been sold in two different configurations: $499 refurbished with a 90-day warranty, or $599 new with full two-year factory warranty. But by the time I got around to acting on my purchase aspiration, refurb inventory was depleted. “No problem,” I thought this time, “what’s available for sale is only $100 more, is brand new, and comes with a much longer warranty period.” Hold that thought.
Here are more stock photos and infographic images from the Battery-Biz website product page (and here’s the user manual, linked to from that same page):
Along with a few more stock images from the promotion page on Meh’s website:
And now, some images of my unit, both in action while being initially charged and accompanying its SLA battery-based sibling:
So why did decide to pull the purchase trigger, aside from out of engineering curiosity? While the Phase2 Energy PowerSource Power Station remains a perfectly acceptable solution for residential backup power in utility outage situations (which we unfortunately seem to be increasingly experiencing of late), as I mentioned back in September, it’s quite a (carrying handles-included, but still) boat anchor. The Energizer PowerSource Pro Battery Generator is comparatively quite svelte: nearly half the total volume (15.35” x 9.5” x 8.8”, versus 19.9″ x 12.8″ x 8.9″) and less than half the weight (23 lbs., versus 58.8 lbs.). However, even though it’s lighter, its battery has 50% higher capacity (991 Wh versus 660 Wh). It recharges faster too: 2 hours to “full” on AC from an initially empty state, versus 10 hours. Its inverter-driven AC outputs are pure sine wave in form, versus simulated. It provides one more DC output, that being 100W USB-C with Power Delivery cognizance. And IMHO, it looks cool, too.
That all said, I actually decided to not keep it (and by the way, Meh was stellar in handling the return, going as far as issuing me a full refund while the bundle was still enroute back to them). Cons of the Energizer PowerSource Pro Battery Generator compared to the Phase2 Energy PowerSource Power Station precursor include:
- Lower cumulative inverter output power—1200-W versus 1440-W continuous/1800-W surge—with the lack of surge support in the Energizer product case due both to the comparative battery technologies in use and the lack of circuitry support (versus, say, the EcoFlow units I told you about in the recent Holiday Shopping Guide for Engineers)
- Lack of support for “chaining” the internal battery to an external supplemental one for runtime extension
- And a permanently attached topside handle, making it difficult to stack other things on top of the Energizer unit should I want to take it on a trip in my camper, for example.
So far, these are minor “nits”. This next one’s more notable, however. As I also mentioned in the recent Holiday Shopping Guide for Engineers, Battery-Biz and Energizer were vague upfront about the exact battery formulation in use with the PowerSource Pro Battery Generator, referring to it only as a “lithium-ion”. Turns out, it’s NMC (Lithium Nickel Manganese Cobalt); no, I don’t know why there’s no upfront “L” in the acronym, either. NMC batteries are typically spec’d for only a few hundred recharge cycles before they need to be replaced. Ironically, this is comparable to the Phase2 Energy PowerSource Power Station’s AGM (absorbed glass mat) SLA battery cycle spec. But it’s much lower than the several thousand cycles oft-touted for LiFePO₄ (lithium iron phosphate), also known as LFP (lithium ferrophosphate), counterparts.
And even this might not have been enough to prompt a return-and-refund request, given the compelling bundle price, except for two other “gotchas”. For one thing, the Energizer PowerSource Pro Battery Generator arrived with obvious already-used cosmetic evidence, contrary to the brand-new claimed condition in the promotion (to be clear, I blame Battery-Biz, not Meh, for this seeming bait-and-switch):
Who knows how many recharge cycles that NMC battery already had on it when I got it?
The accompanying solar panel was also pre-owned, it turns out, with similar cosmetic evidence, plus it arrived damage. I’ll save more details on this twist for my next post in this series. Until then, and as always, please sound off with your thoughts in the comments!
—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.
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- A holiday shopping guide for engineers: 2024 edition
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- Modern UPSs: Their creative control schemes and power sources
- Battery-Powered Large Home Appliances: Good Idea or Resource Misuse?
- The PowerStation PSX3: A portable multifunction vehicular powerhouse with a beefy battery
The post Energizer’s PowerSource Pro Battery Generator: Not bad, but you can do better appeared first on EDN.
MDA / Hercules Graphics Card, work in progress.
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КПІ ім. Ігоря Сікорського офіційно став частиною IREG Observatory!
З гордістю повідомляємо, що наш університет отримав членство у IREG Observatory on Academic Ranking and Excellence – глобальної організації, яка визначає стандарти академічних рейтингів та сприяє поширенню принципів прозорості й академічної досконалості.
IP players prominent in chiplet’s 2024 diary
Chiplets—discrete semiconductor components co-designed and manufactured separately before being integrated into a larger system—are emerging as a groundbreaking approach to addressing many of the challenges faced by monolithic system-on-chip (SoC) designs. They have also become a major venue for increasing transistor density as Moore’s Law slows down.
IDTechEx report “Chiplet Technology 2025-2035: Technology, Opportunities, Applications” asserts that the chiplets approach resembles an SoC on a module, where each chiplet is designed to function in conjunction with others, necessitating co-optimization in design. Moreover, chiplets are increasingly associated with heterogeneous integration and advanced packaging technologies.
While large semiconductor outfits like AMD and Intel were initially prominent in the chiplets world, IP players are now increasingly visible in showcasing the potential of chiplets. That includes established IP players like Arm and Cadence as well as upstarts such as Alphawave Semi.
Cadence’s Arm-based system chiplet
Cadence joined hands with Arm in March 2024 to deliver a chiplet-based reference design, and the outcome of this collaboration is what Cadence calls the industry’s first system chiplet. It integrates processors, system IP, and memory IP within a single package while interconnected through the Universal Chiplet Interconnect Express (UCIe) standard interface.
Figure 1 The system chiplet comprises components such as a system processor, safety management processor, controllers, and PHY IPs for LPDDR5 and UCIe. Source: Cadence
The system chiplet—complying with Arm’s Chiplet System Architecture (CSA)—features of the overall multi-chiplet SoC functionality. It accommodates up to 64 GB/s peak bandwidth for UCIe IP and 32 GB/s peak memory bandwidth for LPDDR5 IP.
AI accelerator chiplet
Another SoC-like emulation on a chiplet platform comes from South Korean AI chip startup Rebellions, which calls its chiplet-based compute accelerator SoC “REBEL. This AI accelerator—designed for generative AI workloads in AI and hyperscale data centers—employs Alphawave Semi’s multiprotocol I/O connectivity chiplets, which integrate PCIe 6.0, CXL 3.1, and Ethernet subsystems with UCIe 2.0 die-to-die connectivity.
Figure 2 The UCIe subsystem serves as the foundation for Rebellions’ REBEL chiplet. Source: Alphawave Semi
It’s another example of a customizable design employing high-speed connectivity and interoperable chiplet architectures. As a result, the chiplet can be deployed as modular building blocks, scalable from single cards to full racks.
The above developments demonstrate how chiplets can help overcome Moore’s Law limits while enhancing function density. Furthermore, they showcase how the chiplets ecosystem allows companies to source different parts from multiple suppliers across various regions.
Related Content
- Startup Tackles Chiplet Design Complexity
- How the Worlds of Chiplets and Packaging Intertwine
- Chiplets advancing one design breakthrough at a time
- Chiplets diary: Three anecdotes recount design progress
- Chiplets diary: Controller IP complies with UCIe 1.1 standard
The post IP players prominent in chiplet’s 2024 diary appeared first on EDN.
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IO-Link actuator board from STMicroelectronics delivers turnkey reference design for industrial monitoring and appliances
ST has introduced an IO-Link reference design for industrial beacons and home-appliance alarms, delivered ready-to-use as a fully built board complete with protocol stack and application software.
The EVLIOL4LSV1 board leverages ST’s L6364Q dual-channel IO-Link transceiver to handle communications and the IPS4260L intelligent low-side power switch for driving the indicator lights. The board can be directly connected to signaling systems such as smart tower lights used in factory automation, funnel material alarms for quantity-remaining or urgency-level awareness, and other system warnings. It also provides a fast way to test the IPS4260L and L6364Q ICs and has a 4-pin M12 connector for an IO-LINK master and a 5-pin SWD connector for programming.
An STM32G071CB microcontroller, which hosts the ST proprietary IO-Link demo stack and the application software, handles system control and diagnostics, communicating with the transceiver and low-side switch.
The L6364Q transceiver is fully protected and supports standardized IO-Link communication speeds including 38.4kbit/s COM2 and 230.4kbit/s COM3. The transceiver can operate in single or multibyte mode, as well as in transparent mode delegating control of IO-Link communications to the microcontroller by a simple URT interface. The in-built protection ensures EMC immunity up to 2.5kVpk surge pulse/500Ω coupling without additional protection elements.
The IPS4260L low-side driver has four outputs for driving loads with one side connected to supply voltage, each individually controlled by a signal such as a digital microcontroller output. It has a wide operating-voltage range, from 8V to 50V, and the current for each output can be independently programmed from 0.5A to 3.0A. The IC integrates overload and overtemperature protection for each channel and provides open-load, overload, and overtemperature diagnostic signals to aid system management and enhance reliability. The reference design also features ST’s SMBJ30CA TVS (transient-voltage suppression) diode to withstand surge pulses with 2Ω coupling on the supply rail.
The post IO-Link actuator board from STMicroelectronics delivers turnkey reference design for industrial monitoring and appliances appeared first on ELE Times.
Відбувся півфінальний матч студентського чоловічого чемпіонату команд м. Києва з баскетболу
Збірна команда КПІ ім. Ігоря Сікорського (капітан Антон Костик, Навчально-науковий видавничо-поліграфічний інститут, НН ВПІ) приймала команду КНЕУ. Наша команда впевнено перемогла з рахунком 84:74!
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Another application of my universal LoRa board: Wireless door switch with Hall sensor.
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