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Sensors—on the front lines of the technological revolution in factory automation—are embedding microprocessors, memory, and communication protocols within the ASIC to offer multiple functions in a single chip, facilitating a new generation of smart factory applications spanning from asset monitoring to industrial robots to manufacturing quality control.

Here is a sneak peek at three sensor designs that enable factory automation applications while ensuring productivity and safety in industrial environments. These sensor designs also incorporate a variety of interfaces to support a wide range of smart factory capabilities.

1. Depth sensor for automation and robotics

This real-time, indirect time-of-flight (iToF) sensor delivers high precision for long-distance measurements and 3D imaging of fast-moving objects. The Hyperlux ID family of depth sensors from onsemi can capture an entire scene and simultaneously process depth measurements in real time.

The sensor combines global shutter architecture with iToF technology to deliver precise, rapid depth sensing. The iToF technology enables it to measure depth by detecting the phase shift of the reflected light from one or multiple vertical-cavity surface-emitting lasers (VCSELs). And the global shutter technology aligns all sensor pixels with the VCSEL, significantly reducing ambient infrared noise from other lighting sources.

Figure 1 The iToF device further extends depth sensing under dynamic scene conditions while capturing fast-moving objects. Source: onsemi

The company claims that the device’s depth-sensing capability of up to 30 meters is 4 times that of standard iToF sensors. Moreover, the sensor can produce both monochrome (black-and-white) images and depth information simultaneously.

That’s vital in factory automation, where the ability to obtain highly accurate depth information quickly and efficiently is becoming critical to improve productivity and safety. So far, iToF sensors have been limited in their use due to minimal range, poor performance in harsh light, and inability to calculate depth on moving objects.

By providing precision measurements of moving objects and high-resolution images, the Hyperlux ID sensors can help reduce errors and downtime and optimize mission-critical processes in a smart factory. In factory automation and robotics, it facilitates object detection to improve navigation and collision avoidance, enhancing safety on factory floors.

Next, in manufacturing and quality control, this depth sensor can measure the volume and shape of objects, detect defects, and ensure that products meet quality standards. In logistics and material handling, the sensor can measure the positions, sizes, and content ratios of pallets and cargo to optimize storage and transportation processes.

2. The AI-enabled IMU

An inertial measurement unit (IMU) with two MEMS accelerometers and a gyroscope tunes this sensing device for activity tracking and high-g impact measurement in smart factory applications such as asset monitoring and event data recorders. The IMU also embeds AI processing—a machine learning core—to perform inference directly in the sensor, continuously registering movements and impacts.

STMicroelectronics’ LSM6DSV320X sensor module, available in a single package, comprises three MEMS sensors. One accelerometer, featuring a maximum range of ±16g, is optimized for robust resolution in activity tracking. The second accelerometer, measuring up to ±320g, quantifies severe shocks such as collisions or high-impact events. Then there is a gyroscope with a ±4000dps range.

Figure 2 The sensor module for industrial safety comprises two accelerometers and one gyroscope. Source: STMicroelectronics

The 3-mm x 2.5-mm sensor module enables smart factory applications—such as personal protection devices for workers in hazardous environments—to fully reconstruct events with high accuracy and assess the severity of factory-floor incidents. The inertial module with dual-sensing capability could also be used to accurately assess the health of factory equipment.

3. Sensor signal conditioner

This signal conditioning IC ensures high accuracy, sensitivity, and flexibility for sensor applications in industrial pressure transmitters, HVAC systems, weight scales, factory automation devices, and smart meters. The ZSSC3240 sensor IC’s flexible configuration makes it highly suitable for smart sensor-based devices for smart factory environments.

Figure 3 The signal conditioner provides higher flexibility for sensor adaptation in smart factory applications. Source: Renesas

Generally, micro-machined and silicon-based sensing elements produce mostly nonlinear, very small signals. And that calls for special technologies to convert the sensor signal into a linearized output.

Renesas’ ZSSC3240 signal conditioning IC facilitates both the design and production of sensor interfaces by providing programmable, highly accurate, wide-gain, and quantization functions, combined with powerful, high-order digital correction and linearization algorithms. So, with a flexible sensor front-end and a broad range of output interfaces, it allows design engineers to develop complete sensing platforms from a single signal conditioning chip.

Special Section: Smart Factory

• Rethinking machine vision in industrial automation
• Smart factory: The rise of PoE in industrial environments
• Precision lasers boost safety and efficiency in smart factories

The post Tale of 3 sensors operating in smart factory environments appeared first on EDN.

Electric vehicles should be better for the environment, powerful, but also affordable. However, their on-board chargers (OBCs) are hindering progress, as existing models are reaching their limits in terms of efficiency, size and reliability. The European Union (EU)-funded HiPower 5.0 project aims to revolutionize this technology...

🤯 Запрошуємо на Онлайн-лекцію “Плагіат та самоплагіат: де межа?” kpi пт, 05/01/2026 - 16:26

Power-supply inductors may be supplanted by piezoelectric energy-storage elements…maybe. And someday.

Today’s step-down DC/DC converters – often converting 48 V down to single-digit voltages — are highly refined topologies, offering efficiencies of 90 percent and higher. Designers can choose among many switched-mode power supply (SMPS) arrangements, each with various subtleties to maximize a desired attribute such as efficiency, transient response, line and load regulation, or output noise. One bill of materials (BOM) aspect that all of these designs share is consistent reliance on magnetics in the form of inductors, to store and release energy as needed during the various operating phases.

But it doesn’t have to be magnetics. A team at University of California at San Diego has developed what they call an “Always-Multi-Path Embedded Flying Capacitor Piezoelectric Resonator-based DC/DC Converter” (that’s a mouthful!) that adds hybrid, multi-path, output-power delivery features to reduce the internal charge-redistribution losses within a piezoelectric resonator.

Their integrated circuit modifies the optimal voltage conversion of the piezo network from 2:1 to 3:1, while adding a switched-capacitor output network and piezoelectric resonators (PRs) to enable continuous multi-path operation. The result is net optimal voltage conversion ratio of 9:1 for the converter. The chip, which is fabricated in a 180-nanometer high-voltage CMOS process, achieves a peak efficiency of 96.2% at a 48-to-4.8 V conversion ratio.

The “flying capacitor” concept itself is not a new development at all; they have been around since the “early days” of electronics. In a classic arrangement, a non-grounded, floating capacitor is first connected to an input source and charged, then it is disconnected for that input and switched to an output to discharge (Figure 1).

Figure 1 The flying capacitor scheme was originally used with electromechanical relays to isolate a signal or power source from the subsequent stage. (Image source: InsightCentral.net)

Also called a switched-capacitor arrangement, it was used for many years to galvanically isolate sensors with electromechanical relays for switching, while modern switching supplies use MOSFETs and other solid-state devices. The switching scheme has also been used in multistage step-up circuits which can deliver thousands of volts from a single-volt source (Reference 3).

What’s wrong with inductors, and why consider using piezoelectric resonators? Inductors are versatile and reliable, but converters using piezoelectric resonators — tiny devices that store and transfer energy using mechanical vibrations — could potentially be smaller, more energy dense, more efficient and easier to manufacture at scale (Figure 2). The UC-SD team claims that inductors have reached a limit in improvement with respect to size and storage density (I suspect inductor vendors would disagree with that assessment).

Figure 2 A piezoelectric resonator (white disk) used by the new chip to perform DC-DC step-down conversion. For comparison, an inductor that is typically used in traditional step-down converters is shown on the left. (Image source: University of California)

Unlike inductors, which store energy in magnetic fields, PRs store and transfer energy through mechanical deformation and piezoelectric effects. They offer several advantages over traditional magnetic devices, including reduced volume due to their thin planar form factors, superior volume-frequency scalability, the ability to be easily batch fabricated, and their potential for direct integration onto silicon chips in future work. The high coupling and quality factor (Q) of PRs makes them attractive when designing high-efficiency, high-performance power systems, especially in the context of next-generation power conversion technologies.

Not surprisingly, an off-the-shelf PR is not suitable for this application. Commercially available units are not optimized for power applications and cannot operate robustly at the high current demands of modern datacenters. Further, the maximum current-carrying capability of a PR is determined by its physical properties such as material, vibration mode, and geometrical design, as well as electrical excitation strategies. For these and other reasons, the team designed a custom PR unit (Figure 3).

Figure 3 The custom piezoelectric resonator (right) overcomes limitations of commercial ones; the resonator size (left) is shown compared to a penny. (Image source: University of California)

Final performance is characterized by many different parameters under different operating conditions, such as those in Figure 4:

Figure 4 Fabrication and measurement images in abundance augment your knowledge base: a) Silicon die photo of the proposed converter; b) Measured waveform of each side of the PR, its differential voltage (VCP), and output voltage under voltage conversion ratio (VCR) = 10 and VCR = 20; c) Efficiency curve versus load current with fixed VCR (=10); d) Efficiency curve versus VCR with fixed load current (=200mA); e) Output current versus operation frequency, where the frequency operates in the inductive region of the PR. (Image source: University of California)

The team does acknowledge some limitations. Because piezoelectric resonators physically vibrate, they cannot be soldered onto circuit boards using conventional approaches and will require different strategies to integrate them into electronic systems. Although the technology is still in its early stages, the researchers say it represents an important step toward overcoming the limitations of today’s power converters. Future work will focus on improving materials, circuit design and packaging

As project senior author Patrick Mercier, professor in the Department of Electrical and Computer Engineering at the UC San Diego Jacobs School of Engineering noted, “Piezoelectric-based converters aren’t quite ready to replace existing power converter technologies yet. But they offer a trajectory for improvement. We need to continue to improve on multiple areas — materials, circuits and packaging — to make this technology ready for data center applications.”

Will this new approach get some traction? I don’t know, nor does anyone. After all, when optimized magnetic-based converters already have efficiency in the 90-95% range along with other favorable attributes, the pain needed to get another point or fraction of a point of improvement may not be worth the gain. On the proverbial other hand, a reduction in size or cost, even at the same efficiency, may be worthwhile.

Their paper “A hybrid piezoelectric resonator-based DC-DC converter” was published in Nature Communications but is behind a paywall; however, the team has posted a preprint here.

References

1. Knowles, “What Are Flying Capacitors?”
2. Insight Central, “Flying Capacitor High Voltage Battery Monitor”
3. EE World Online,  “Generating really high voltages without a tesla coil”

Related Content

• Converter transformation shows how far we’ve come
• Piezo audio devices go micro, provide output in a big way
• Piezo-Based Energy Harvesting May Repel Tooth Decay

 

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Global smartphone shipments grew 1% year-on-year (YoY) in first-quarter 2026 to 298.5 million units, according to market research firm Omdia. The quarter was shaped by two opposing forces. Vendor-led front-loading (as Samsung, Apple, and others accelerated sell-in ahead of expected inflation in memory and component costs) supported momentum and contributed to performance exceeding initial industry expectations. However, macroeconomic headwinds continued to weigh on end-consumer demand. Persistent inflation has compressed household discretionary budgets, creating a widening gap between channel sell-in and underlying sell-out. This imbalance is expected to lead to a more pronounced correction in second-quarter 2026 and second-half 2026...

For coverage of all the key business and technology developments in compound semiconductors and advanced silicon materials and devices over the last month, subscribe to Semiconductor Today magazine...

🎥 У КПІ ім. Ігоря Сікорського відбувся IEEE Kyiv Polytechnic Week kpi пт, 05/01/2026 - 10:00

The image quality isn't great, but considering I got them for free, it's not bad. submitted by /u/SpaceRuthie [link] [comments]

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has appointed two executives to strengthen its leadership team and support its continued growth and engagement with customers, investors and stakeholders, as the firm accelerates global expansion, deepens engagement with policymakers and advances its long-term growth strategy...

Твори Василя Климика в ЦКМ Інформація КП чт, 04/30/2026 - 16:05

Part 1 of this mini-series about PCIe 7.0 fundamentals explained ordering rules and the distinction between relaxed ordering and ID-based ordering. Part 2 elaborates why PCIe 7.0 bandwidth alone isn’t enough and how UIO addresses legacy ordering limitations in this version of high-speed serial interface specification.

As noted earlier, PCIe 7.0 doubles raw link bandwidth compared to PCIe 6.0, increasing full‑duplex throughput from 256 GB/s to 512 GB/s on an x16 link by raising the signaling rate to 128 GT/s in flit mode. However, raw bandwidth does not directly translate into sustained throughput in AI factories.

Large‑scale training and inference systems generate traffic patterns such as GPU collective operations, sharded parameter broadcasts, gradient reductions, and streaming access to disaggregated accelerator and memory resources. These patterns include many independent data streams that cross the PCIe fabric concurrently and continuously.

The legacy ordering model inherited from earlier PCIe generations, including strict ordering, relaxed ordering, and ID‑based ordering, was designed around a producer-consumer abstraction in which ordering conveys semantic meaning to software. Relaxed ordering and ID-based ordering loosen this model selectively.

Relaxed ordering allows certain transactions to bypass global ordering constraints, while still participating in fabric‑enforced ordering rules. ID-based ordering further scopes ordering guarantees to a requester or execution context, preserving program order within that scope. In both cases, the PCIe fabric requires tracking and enforcement of ordering relationships to ensure correctness.

However, fabric‑enforced ordering introduces head‑of‑the-line blocking, increases buffering pressure, and restricts the ability of switches and endpoints to exploit parallel paths. This is particularly the case for multi‑path and non‑tree topologies common in modern AI systems. These effects reduce effective link utilization even though physical bandwidth is available, making it difficult for highly parallel AI workloads to keep PCIe 7.0 links continuously busy.

Addressing legacy ordering limitations with UIO

The unordered I/O (UIO) engineering change notice (ECN) was introduced in the PCIe 6.1 specification and included in PCIe 7.0 to address the specific limitation noted above. UIO introduces a wire-level semantic that shifts producer-consumer ordering responsibility from the fabric to the endpoints. The UIO ECN declares that ordering may be irrelevant for certain traffic classes.

For AI factory workloads, where operations such as reductions, parameter streaming, and telemetry are independent or statistically aggregated and never consumed in program order, enforcing any form of ordering (even per‑ID ordering) adds overhead. UIO removes fabric‑enforced ordering, enabling true multi‑path parallelism and reducing buffering requirements.

This allows PCIe fabrics to sustain higher utilization for concurrent AI traffic. Since UIO enables independent transactions from different request originators to bypass one another safely, AI systems can optimize PCIe 7.0’s increased bandwidth to support rapidly growing model sizes and highly parallel GPU workloads.

UIO is especially effective at reducing read latency because multiple UIO read completions for a single UIO read request may be returned in any address order. This same flexibility applies to UIO write completions, with the additional capability that write completions for the same transaction ID may be coalesced. Since every UIO request has a corresponding completion, the request originator maintains the ordering of its own transactions. This allows the PCIe fabric to forward traffic along multiple paths without violating semantic correctness.

With its low latency, UIO transforms PCIe fabrics into high-throughput, highly parallel forwarding planes capable of accommodating modern AI workloads. Instead of relying on the fabric to manage per-flow sequencing, UIO shifts ordering control back to the source device that initiates the requests.

How UIO reduces latency and unlocks concurrency in AI applications

UIO’s command set and wire semantics reduce latency and boost performance for AI training and inference in several ways.

First, UIO mandates completions for all UIO requests. This gives GPU endpoints precise end-to-end flow control and prevents posted-write “fire and forget” bursts from clogging switch queues. It also cuts head-of-the-line blocking and shortens tail latency, speeding up requests by allowing different types of requests to bypass each other without applying any ordering rules within the PCIe fabric.

One of the classic head-of-the-line blocking examples in the baseline strict ordering rule is that current read requests are not permitted to bypass previous write requests. UIO eliminates this rule, allowing read and write requests to be processed in parallel and completed in any order, as shown in Figure 1.

Figure 1 UIO read and write requests are processed in parallel at the application layer. Source: Cadence Design Systems

In addition, UIO read requests reduce latency and buffering by allowing a completer to return read completions out of order. This enables data to be delivered as it becomes available, rather than delaying responses to preserve requests or address ordering. This improves overall efficiency by giving the device greater freedom to exploit internal data availability and minimizing completion queueing and reassembly overhead.

For example, Figure 2 and Figure 3 show the completion patterns for a single 512 MB MRD request for non-UIO (in-order) and UIO (out-of-order) cases, respectively.

Figure 2 Non-UIO completion responses must be in order for the same MRD request. Source: Cadence Design Systems

For non-UIO, Figure 2 illustrates that completions must arrive in order, starting at byte 0 and ending at byte 511. However, with UIO, the completion order can be random, as shown in Figure 3. The first two completions carry the last two chunks of MRD requests (256-383B and 384-511B) because they are already available in the local cache. After that, the application reads the remaining completion data from its local memory and sends the remaining two completions (0B-127B and 128B-255B).

Figure 3 UIO read and out-of-order completion responses are processed for the same request. Source: Cadence Design Systems

Second, because ordering is enforced at the source rather than at every intermediate hop, packets from unrelated GPU streams can be load-balanced across multiple parallel paths through the PCIe fabric without being serialized by switch-level producer-consumer rules. This increases effective throughput at a given link rate and stabilizes latency underload. In multi-path topologies, system architects often use a non-transparent bridge (NTB) to connect separate systems, enabling cross-system traffic within a larger fabric.

Third, UIO is available only in flit mode. Operating in fixed-size flits with UIO-specific VC3VC4 (via the streamlined virtual channel capability) isolates UIO traffic from legacy flows, minimizes delays, and improves switch buffer utilization.

Figure 4 The above diagram displays a multi-path application example. Source: Cadence Design Systems

Figure 4 shows two interconnected PCIe systems (System 0 and System 1), each with GPUs and local PCIe switches connected via multiple NTB links. The upper NTB link can operate with either UIO-enabled or non-UIO-enabled traffic, while the three diagonal and lower links operate with UIO-enabled NTB.

As a result, independent transactions can flow concurrently across switches SW0–SW3. This topology shows how UIO-based NTB paths improve GPU communication by enabling multipath routing, reducing latency, and increasing bandwidth in large-scale AI systems.

PCIe ordering: A traffic light analogy

A helpful way to think about PCIe ordering is traffic control in a city. Strict ordering is like running the entire city with a single traffic light, and every vehicle must wait its turn and proceed in sequence. While there is no ambiguity, congestion can quickly build up. Relaxed ordering allows certain vehicles to pass through intersections in specific emergency situations, provided it is safe to do so.

While this removes unnecessary traffic jams, it still assumes the traffic system is centrally managed. ID-based ordering further refines this model by assigning each neighborhood its own traffic lights. While cars within the same neighborhood must obey local ordering rules, traffic from different neighborhoods can flow independently. This improves parallelism without sacrificing local correctness.

UIO bypasses traffic light rules entirely. It is akin to routing traffic onto a freeway, where there are no intersections or signals at all, and vehicles move continuously as capacity allows. On a freeway, the infrastructure does not impose sequencing. Instead, the responsibility for safe merging and interpreting arrival order shifts to drivers.

Similarly, with UIO, the PCIe fabric no longer enforces producer‑consumer ordering or completion sequencing. The requester explicitly declares that ordering carries no semantic meaning, allowing the fabric and devices to deliver and complete transactions opportunistically. This maximizes parallelism while minimizing buffering and latency.

These four ordering schemes are a progression rather than a set of alternatives. Strict ordering prioritizes safety and simplicity, while relaxed ordering removes unnecessary global barriers. ID-based ordering preserves correctness within a context while enabling scale, and UIO explicitly abandons ordering when it has no value. This layered model allows PCIe to remain compatible with legacy software while scaling efficiently for modern accelerators, multi‑queue devices, and highly parallel workloads.

Turning PCIe bandwidth into system-level performance

Fully utilizing PCIe 7.0’s 128 GT/s link in today’s AI factories requires more than higher signaling rates. In an environment where thousands of GPUs, accelerators, and memory expanders operate as a single, distributed system, an ordering model that can scale with extreme parallelism is necessary.

Legacy relaxed ordering and ID-based ordering schemes retain implicit ordering constraints that limit their efficiency at PCIe 7.0 speeds, making them increasingly inadequate for AI factories operating at hyperscale.

UIO relaxes fabric‑enforced ordering and enables AI workloads to more effectively utilize multi‑path PCIe fabrics. By shifting ordering decisions to endpoints that already manage synchronization at the runtime and application levels, UIO reduces ordering-related head-of-the-line blocking issues.

Not only does this improve latency under bursty collective traffic, it also supports higher sustained link utilization across dense training and inference clusters. The result: Under AI workloads, PCIe 7.0 can be used more efficiently as a data plane, rather than simply serving as a peak‑bandwidth interconnect.

Vanessa Do is a senior product marketing manager for PCIe IP at Cadence with over 20 years of experience in PCIe design, system validation, and customer engagement. Her background spans PCIe protocol development, FPGA-based customer support, and leading cross‑functional teams to debug complex PCIe issues at the system level.

Editor’s Note

This is Part 2 of the article series about PCIe 7.0 fundamentals. Part 1 explained PCIe’s ordering rules and the distinction between relaxed ordering and ID-based ordering.

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Portable power units have both instantaneous-output and run-time limits, of course, but this situation seems a bit ridiculous. Or, then again, maybe not. But how to tell?

Last December, a few hours after the “kickoff” of our high wind-induced multi-day power outage “adventure”, I had the bright (if I do say so myself) idea to try hooking up our portable power stations (plus extended batteries in two of the three cases):

to the refrigerator-plus-freezer combo in the kitchen, along with both its combo fridge-plus-freezer companion and a standalone chest freezer out in the garage. The weather outside, therefore also the temperature in the garage, was chilly, so I wasn’t terribly worried about anything spoiling in either of those latter two units. Then again, I didn’t know how long the outage would last, and I had three supplemental power solutions at my disposal, so…

A preparatory test-drive admittedly would have been wise

I started (and ended; keep reading) with the cooling combo in the kitchen, my highest priority for perhaps-obvious comparative ambient temperature reasons. It’s a Samsung model RF217ACBP/XAA; here are a couple of stock photos to start:

I dragged from the downstairs furnace room the EcoFlow DELTA 2-plus-Smart Extra Battery “stack”, enabled the former’s AC inverter outputs, and plugged the combo fridge-plus-freezer in. I heard the compressor start up (accompanied by a DELTA 2 front panel display-reported AC output spike)…try to start up is a more accurate description, because after a second or so, the setup seemingly overloaded and gave up trying. Next up, the DELTA 3 Plus and its Smart Extra Battery sibling. Same underwhelming outcome.

The wind was blowing, the outside light was dimming, and my spouse was understandably getting stressed, so I didn’t waste any more time messing around; I promptly bailed on the idea and focused my attention elsewhere. Since I’d already expended the effort to get both “stacks” upstairs, they ended up alternatively finding use in powering table lamps, recharging various battery-powered devices—lanterns, laptops, tablets, smartphones—and the like.

No, I didn’t bother trying to haul upstairs my even heavier SLA battery-based Phase2 Energy unit. And fortunately, save for the spoil-prone contents of our kitchen refrigerator (but not its combo freezer), we didn’t need to toss any food. Still, I was both disappointed and (more than a) bit surprised, because I’d seen success reports from other folks who’d successfully powered food-storage equipment (albeit of unknown capacity and for unknown duration) using EcoFlow and other suppliers’ similar systems in similar circumstances as mine.

Published data also would have been helpful

Given my background experiences with other startup-surge hardware, I was pretty sure I knew how the failure had happened, but not specifically why. So, after the electricity started flowing again, I did some research. First off, I realized I hadn’t enabled either EcoFlow base unit’s X-Boost Mode feature, which might have gotten them over the compressor-start initial-surge “hump”. Please take a moment to “enjoy” the following promo video clips :

As I wrote last February, X-Boost “doubles the output AC power (at a reduced voltage tradeoff that not all powered devices are guaranteed to accept, albeit obviously counterbalanced by higher current)”. Could it have helped? Dunno; I’ll have to try it sometime when I get a chance.

But how much surge current, and at what minimum voltage, does the Samsung RF217ACBP/XAA demand on compressor startup? Ay, there’s the rub. You won’t find it in the user manual, or even the service manual, only steady-state power draw specs. The labels on the side:

and rear of the Samsung RF217ACBP/XAA:

weren’t directly helpful either, although they at least revealed the compressor model number (MK162D-L1U SJ1). But my online browsing using that specific search term was equally fruitless.

Cue the hand-waving

What do online resources say in general? Here’s Google AI Mode’s take on the topic:

A refrigerator typically experiences a startup surge current 3–4 times higher than its normal running amperage, lasting only a few seconds. While running at 1–4 amps, it can spike to 15–30 amps during compressor startup. This inrush current is essential to overcome inertia, usually requiring a dedicated 15–20 amp circuit.

I just checked and confirmed that my kitchen refrigerator breaker is 20A. Feel free to contrast that with the “3.9 Maximum Amperes” claim in the above sticker closeup shot. Sigh.

Ballpark figures are better than nothing, I suppose, albeit still (quite) non-ideal. Am I just overlooking something obvious, or being pedantic, or is the startup surge draw:

• useful information that
• Samsung (at least) isn’t publishing

therefore, compelling consumers to potentially overshoot, buying portable power systems beefier and more expensive than they may actually need (and, apparently, than I bad-pun-intended “currently” own)? Reader thoughts are as-always welcomed in the comments!

My father (the King of Duct Tape) would have been impressed

p.s…while researching this post’s topic online, I came across a mind-blowing (at least to me) somewhat-related Reddit thread that I couldn’t resist sharing: “Fridge kept tripping circuit breaker until I added an extension cord. Why?”. Here’s my stab at the TL;DR summary:

The OP (original poster) eventually determined, in conjunction with his repair tech, that the refrigerator’s defrost heater was failing. But in initially attempting to debug the issue, originally assuming that the outlet wiring might be failing, he used an extension cord (beefy, I hope) to plug the fridge into another outlet, which worked fine. Turns out, the extension cord was still largely coiled and sitting on top of the fridge; the resulting added circuit induction sufficiently opposed the high frequency noise injection coming from the failing defrost heater such that the arc fault circuit interrupting (ACFI) breaker stopped tripping…temporarily, at least.

The entire thread is well worth your perusal if you have sufficient spare time and interest!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Preemptive utilities shutdown oversight: Too much, too little, or just right?
• EcoFlow’s Delta 2: Abundant Stored Energy (and Charging Options) for You
• Portable power station battery capacity extension: Curious coordination
• EcoFlow’s DELTA 3 Plus and Smart Extra Battery: Product line impermanence curiosity
• An assortment of tech-hiccup tales

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Applied Optoelectronics Inc (AOI, a designer and manufacturer of optical and hybrid fibre-coaxial networking products for AI data centers, cable TV and broadband fiber access networks) has been awarded a Texas Semiconductor Innovation Fund (TSIF) grant for $20,852,518 to support its manufacturing expansion plans in Sugar Land, Texas...

Epiwafer and substrate maker IQE plc of Cardiff, Wales, UK has announced a strategic investment from customer MACOM Technology Solutions Inc of Lowell, MA, USA, and other existing shareholders, raising gross cash proceeds of about £81m...

ADI’s ADAA245x series of A2B 2.0 Automotive Audio Bus transceivers delivers 4× higher bus bandwidth (98.3 Mbps full-duplex) than A2B 1.0 devices. Now in production, the transceivers handle up to 119 upstream and downstream audio channels for advanced automotive audio systems, enabling high-definition audio transport across ECU networks.

The ADAA2457 supports Ethernet data tunneling via an Open Alliance SPI (OASPI) interface. All ADAA245x devices are compatible with existing A2B 1.0 cable and connector infrastructure and enable A2B 1.0 branching via device-specific I2S, I2C, and SPI interfaces. The ADAA2455 operates as a sub-node transceiver, while the ADAA2456 and ADAA2457 can be configured as main or sub-nodes.

According to ADI, the transceivers achieve up to 30% system cost reduction through increased functional integration and reduced external circuitry and component count. They also provide low, deterministic latency of 62 µs and are built for straightforward integration.

Learn more about A2B 2.0 and individual transceivers here.

Analog Devices

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Rohm’s ML7670/ML7671 wireless charging chipset provides NFC charging for compact wearables such as smart rings and fitness trackers. Operating in the 13.56-MHz band, NFC charging enables antenna miniaturization for ultra-compact devices. Following the 1-W ML7660/ML7661 chipset, the ML7670/ML7671 is optimized for even smaller wearable designs.

The chipset comprises the ML7670 receiver and ML7671 transmitter and supports wireless power transfer up to 250 mW. Peripheral components, including switching MOSFETs used to power the charging IC, are integrated. ROHM states that the 2.28×2.56×0.48-mm receiver IC reaches 45% power-transfer efficiency at 250 mW output, where it is optimized for compact wearable designs.

Rohm says the 45% power-transfer efficiency is enabled by tailored coil matching, rectifier circuitry, and reduced switching losses. Firmware for wireless power delivery is embedded in the IC, eliminating the need for a host MCU and reducing board space.

The NFC Forum WLC 2.0-compliant chipset is in mass production and is used in the Soxai Ring 2.

ML7670 product page 

ML7671 product page

Rohm Semiconductor

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Vishay has released 16 single and dual FRED Pt ultrafast rectifiers in low-profile DFN6546A packages with wettable flanks. The 200-V devices occupy a 6.5×4.6-mm footprint with a typical height of 0.88 mm. Rated from 6 A to 15 A, they offer a 10% lower profile and 50% higher current than comparable 200-V SMPC (TO-227A) devices.

The rectifiers are designed for high-frequency power conversion and protection in automotive, industrial, and consumer systems, including EV powertrains, ADAS, industrial automation, and telecom equipment. Automotive variants are AEC-Q101 qualified.

For these applications, the rectifiers feature low reverse leakage current and operate over a wide temperature range from −55 °C to +175 °C. A low forward voltage drop of 0.75 V, combined with fast reverse recovery time and low reverse recovery charge, reduces power losses and improves efficiency.

The DFN6546A package’s wettable flanks enable automatic optical inspection (AOI), eliminating the need for X-ray inspection and supporting automated assembly. The devices are MSL 1 qualified per J-STD-020, with a maximum peak reflow temperature of 260 °C.

Samples and production quantities of the single and dual FRED Pt ultrafast rectifiers are available now, with lead times of eight weeks.

Vishay Intertechnology 

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Microchip’s MD-990-0011-B M.2 plug-in timing module delivers precise synchronization for data center servers and 5G vRAN. Developed with Intel, it is compatible with Xeon 6 SoC–based server platforms. It leverages Intel’s vRAN architecture for low-latency time synchronization in distributed AI workloads and real-time applications.

Customized for Intel-based reference designs, the device supports automatic source selection and locking across GNSS, Synchronous Ethernet (SyncE), and PTP networks. Its integrated SyncE synthesizer includes two independent digital PLL channels: one for time and one for frequency. Additional components include an OCXO supporting 4 or 8 hours of 1.5-µs holdover, along with a temperature sensor, EEPROM, and a crystal oscillator to help maintain low jitter.

By integrating these components into a single plug-in module, the MD-990-0011-B simplifies server design and reduces complexity. Its modular approach also speeds installation and maintenance, helping minimize downtime.

The MD-990-0011-B is available in production quantities from Microchip and authorized distributors.

MD-990-0011-B product page 

Microchip Technology 

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The GD32F5HC series of 32-bit general-purpose MCUs from GigaDevice features a 200-MHz Arm Cortex-M33 core with DSP and FPU capabilities. Hardware-based security, ample on-chip memory, and integrated peripherals target both consumer and industrial designs.

On-chip memory includes 2 MB of flash, 320 KB of SRAM, and 32 KB of instruction cache. Multichannel DMA controllers handle complex algorithms, graphics frameworks, and high-speed data flows. QSPI and SPI interfaces enable external PSRAM and flash expansion at up to 45 MHz.

Peripherals include a 12-bit ADC with an integrated temperature sensor and an infrared interface for analog signal processing. Multiple 16-bit and 32-bit timers, along with a real-time clock, enable waveform generation, motor control, and synchronized multi-axis operation.

Security features combine Arm TrustZone with a 2-kbit eFuse for key storage and hardware cryptographic accelerators. Secure boot, storage, debugging, and firmware updates help maintain system integrity across the device lifecycle.

The MCUs operate from a 3.3-V supply and offer four power-saving modes: sleep, deep sleep, standby, and SRAM sleep. Devices are available in BGA64 and QFN56 packages with up to 54 GPIOs.

GD32F5HC product page

GigaDevice

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Проєкти КПІ – переможці конкурсів НФДУ 2026 Інформація КП ср, 04/29/2026 - 15:25