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Happy workbench Wednesday! I’ve been itching to post this since last Thursday haha. I’m Abacus of FooseyRhode and I specialize in repair of a specific type of computer part called an ASIC Hashboard, and those PCBs are what this setup is built around servicing. Honorable mentions at my desk that might catch some curiosity The Overhead Cable Trays. The rail mounted, Digital Microscope. The Heatgun Glory Hole. Soldering Iron suspended by pulleys. The Quad-table-top fans (Fan Deck). 1 and 2.) The overhead cable trays are super helpful for the obvious, but also for storing some accessories out of the way. My primary heatgun for example. With it up there, wrist strain from the heavy heatgun gun hose is practically eliminated. I also mounted my PC and digital microscope up there. Microscope benefits because table vibrations are gone, and computer is just there for cable management. 3.) See image 3. Looks crazy but it’s very necessary for my work. The PCB I work on are typically single layer PCB secured to a giant aluminum plate. A lone heatgun is not capable of achieving solder flow, and hot plates are extremely impractical for PCB like this. Thus, I apply heat from above, and below. Getting the damn thing mounted safely was the hardest part. I used a pneumatic vesa monitor mount, but backwards. I hammered the vesa mount into shape and secured it to a desk beam. Then I secured the opposite end of the mount to the heatgun. 4.) The pulleys just keep the soldering iron cable out of my way. Honestly, I’m just resolving a minor inconvenience for myself with this. 5.) My 3D printed Fan Deck! It’s four 120mm fans powered through a potentiometer so I can control the speed. It’s used primarily when I am diagnosing a board. The boards I work on use around 40-90 amps when operating, but for diagnostic, require only 10-20 amps to test properly. Point being, they heat up very rapidly, and heat affects my diagnostic. The Fan Deck is a means to cool boards down while simultaneously injecting power into them. submitted by /u/FooseyRhode [link] [comments]

CVD Equipment Corp (CVDE) of Central Islip, NY, USA (a designer and maker of chemical vapor deposition, thermal processing, physical vapor transport, gas and chemical delivery control systems, and other equipment and process solutions for developing and manufacturing materials and coatings) has announced the successful growth of single-crystal silicon carbide (SiC) boules grown on CVDE physical vapor transport (PVT) systems and characterized by Stony Brook University (SBU) in support of their new ‘onsemi Research Center for Wide Bandgap Materials’...

And wrote a blog post about it https://atomicsandwich.com/blog/breathing_apparatus submitted by /u/RonnieRehab [link] [comments]

Germany-based Bosch Group has started to introduce third-generation silicon carbide (SiC) chips and is supplying samples to global automakers...

Germany-based Bosch Group has started to introduce third-generation silicon carbide (SiC) chips and is supplying samples to global automakers...

Квест "Святкуємо число Пі" в ДПМ Інформація КП ср, 04/22/2026 - 11:50

Dr Karen Dowling of the Microelectronics Department in the Faculty of Electrical Engineering, Mathematics and Computer Science at TU Delft (Delft Univrsity of Technology) has been awarded an NWO Open Competition ENW-XS grant for her research on materials that can be used in space exploration at extreme temperatures. Specifically, she will investigate the thermoelectric properties of gallium nitride by modelling, fabricating and testing it at temperatures ranging from 500K to 4K...

Dr Karen Dowling of the Microelectronics Department in the Faculty of Electrical Engineering, Mathematics and Computer Science at TU Delft (Delft Univrsity of Technology) has been awarded an NWO Open Competition ENW-XS grant for her research on materials that can be used in space exploration at extreme temperatures. Specifically, she will investigate the thermoelectric properties of gallium nitride by modelling, fabricating and testing it at temperatures ranging from 500K to 4K...

Here is how design engineers can implement over-the-air (OTA) firmware updates for a microcontroller using the “staging + copy” method. The microcontroller—NXP’s RW612 in this design case study—relies on external serial flash. The article highlights the use of NXP’s ROM-resident FlexSPI API to safely erase and program the flash without bricking the device.

Figure 1 RW612 is a wireless microcontroller with an Arm Cortex-M33 application core. Source: NXP

The OTA process involves downloading the new firmware into a secondary staging partition, verifying, and then copying it to the active partition upon reboot. The article also points to a practical, production-ready example for developers.

For a practical application of OTA implementation, check the complete video tutorial that explains how to implement a remote firmware update. In this video, we use the NXP FRDM-RW612 development board with Mongoose Wizard, but the same method applies to virtually any other NXP microcontroller.

OTA firmware update

If you are looking for a practical OTA firmware update example, this article shows a simple “staging + copy” method on the NXP RW612 microcontroller using external FlexSPI flash. It matches what the FRDM-RW612 board setup looks like in real life, and it points to the exact Mongoose source file (ota_rw612.c) that implements the flow.

Figure 2 The FRDM-RW612 development board is designed for rapid prototyping with the RW61x family of wireless microcontrollers. Source: NXP

OTA firmware updates let you ship fixes and features without asking users to plug in a debugger. On Wi-Fi MCUs, such as NXP RW612, OTA is also one of the first things you want because it unlocks faster iteration during development.

There is no single “correct” OTA design. Different products pick different strategies depending on flash size, how paranoid you are about power loss, and how strict your security requirements are. Here are a few common patterns you will see in the wild:

• In-place update (single slot): Download the new firmware and overwrite the currently running image. This uses the least flash, but it has the highest risk; if power is lost while you erase or program, you may brick the device unless a bootloader can recover.
• Staging + copy: Download the new image into a staging area (an “inactive” region), verify it, and then copy it over the active firmware region. This is a very common and practical method because the device keeps running the old firmware while the download happens, and you only switch after you have a complete, verified image.
• A/B (dual slot): Split flash into two full firmware slots and select which one to boot. It’s viable when you can afford the space, because rollback can be as simple as flipping a flag. It does, however, require enough flash for two complete images plus metadata.
• Delta updates: Download only the binary diff from the old version to the new version and reconstruct on the device. Great for saving bandwidth, but the tooling and edge cases can get complicated fast.

In this article, we focus on the staging + copy approach because it’s easy to reason about, does not require two complete bootable slots, and maps nicely onto RW612 designs with external serial flash.

A minimal staging + copy flow looks like this:

1. Reserve a staging region in external flash plus a tiny metadata area.
2. While running the current firmware, download the new firmware into the staging region.
3. Verify the staged image (signature and/or CRC, size checks, and version rules).
4. Reboot into a small bootloader or early-boot update routine.
5. Copy the staged image over the active firmware region, update metadata, and then boot the new firmware.

Here is a practical note: the easiest way to create a staging area is to split the external flash into two partitions. You keep the active firmware in the first partition and use the second partition as the staging area for the download. After verification, you copy from the second partition back into the active region during reboot.

If power is lost during the download, you still have the old firmware. If power is lost during the final copy, a well-designed bootloader can retry the copy or fall back to a known-good image (depending on your layout and policy). Either way, the goal is the same: avoid bricking devices.

External flash and FlexSPI ROM API

A key RW612 detail that influences OTA design: RW612 does not have built-in internal flash for your application image. Instead, designs typically use external serial NOR flash connected over FlexSPI. The FRDM-RW612 development board, for example, includes external serial flash (Winbond) on the board. That means your OTA code ultimately needs to erase and program external NOR flash.

The nice part is that NXP provides a ROM-resident API that can operate that flash through FlexSPI. In the MCUXpresso SDK documentation, you will see this described as the ROM API driver for external NOR flash connected to the FlexSPI controller, with support for initialize, program, and erase operations.

Why a ROM API matters: when you update flash, you want the programming logic to be as reliable as possible. ROM-resident routines are not stored in external flash, so they can still run safely while you are erasing and programming the external device.

Here are references for RW612 and FlexSPI ROM API (MCUXpresso SDK):

• RW612 datasheet (notes off-chip XIP flash and FlexSPI interface)

https://www.nxp.com/docs/en/data-sheet/RW612.pdf

• FRDM-RW612 board user manual (mentions external serial flash on the board)

https://www.mouser.com/pdfDocs/NXP_FRDM-RW612_UM.pdf

• MCUXpresso SDK ROMAPI driver reference (external NOR over FlexSPI)

https://mcuxpresso.nxp.com/api_doc/dev/2349/a00044.html

• MCUXpresso SDK romapi examples index

https://mcuxpresso.nxp.com/mcuxsdk/25.03.00/html/examples/driver_examples/romapi/index.html

• MCUXpresso SDK romapi_flexspi example readme

https://mcuxpresso.nxp.com/mcuxsdk/25.03.00/html/examples/driver_examples/romapi/flexspi/readme.html

• MCUXpresso SDK fsl_romapi example readme

https://mcuxpresso.nxp.com/mcuxsdk/latest/html/examples/driver_examples/fsl_romapi/readme.html

Practical layout tip for RW612 OTA: treat the external flash as your update playground. Reserve space for the active firmware, a staging region, and a small metadata area that records the update state. Keep the metadata redundant (two copies, versioned records, or a simple log) so you can survive an interrupted write.

Mongoose OTA example

If you want something you can build and run quickly, Mongoose includes a working RW612 OTA implementation that demonstrates the staging + copy method on the FRDM-RW612 board. The walkthrough video is at the beginning of this article and the implementation lives in https://github.com/cesanta/mongoose/blob/master/src/ota_rw612.c.

At high level, the Mongoose RW612 OTA example does three jobs:

1. Receive the new firmware image over the network

The transport can be HTTP, HTTPS, or whatever your product uses. In a typical Mongoose setup, you stream the incoming bytes straight to the staging region in external flash, so you don’t need a giant RAM buffer.

2. Write the new image into the staging region using the FlexSPI ROM API

The OTA code erases the destination region (sector erase) and programs data (page program) as the download progresses. This is the part that is RW612-specific: you use the ROM API FlexSPI routines to safely erase and program the external serial NOR flash.

3. Copy staged firmware to the active region and switch over

After the image is fully written and verified, you reboot. Early in boot, the update routine copies the staged image to the active firmware region using the same FlexSPI ROM API. Finally, metadata is updated, so the device knows the update is complete and the new firmware boots.

Below are a few practical details that are worth copying into your own RW612 OTA design:

• Stream to flash

Do not buffer the whole image in RAM. Erase in sector-sized chunks and program in page-sized chunks as data arrives.

• Verify before you copy

At minimum, store and check a CRC of the downloaded image. For production, verify a signature and enforce anti-rollback rules if needed.

• Make the update state robust

Store update metadata in a small, dedicated region (for example, “no update”, “downloaded”, “copy in progress”, and “done”). Consider writing metadata as an append-only record or keep two copies and alternate between them so you can recover from a power cut during the metadata update.

• Handle power loss during the final copy

A common trick is to mark “copy in progress” before you start copying; then if the device reboots unexpectedly, the boot code can resume the copy from where it left off or restart it safely. Another trick is to copy in fixed chunks and persist progress.

If you just want to see it working, start with the demo video, then open ota_rw612.c and trace the flow: where the image bytes land in external flash (staging), how the ROM API based erase and program calls are made, and how the staged image is copied over the active region during reboot.

That’s how RW612 OTA is done in a way that is simple, resilient, and easy to productize.

Sergey Lyubka is director at Cesanta Software.

Related Content

• OTA Software Updates: Where Are We?
• Memory solutions for firmware OTA updates
• Addressing the challenge of automotive OTA update
• OTA: A Core Technology for Software-Defined Vehicles
• The role of phase-change memory in automotive OTA firmware upgrades

The post How to implement OTA firmware update on MCUs appeared first on EDN.

submitted by /u/antthatisverycool [link] [comments]

КПІшники отримали «зелений енергетичний Оскар» kpi вт, 04/21/2026 - 23:02

Quinas Technology Ltd of London, UK (which was spun off from Lancaster University in early 2023, and is developing ULTRARAM non-volatile memory technology) has announced a milestone in its R&D program, confirming the use of atomic layer etching (ALE) to fabricate and refine its quantum-engineered device structures at Saudi Arabia’s King Abdullah University of Science and Technology (KAUST) Core Labs (a system of multi-disciplinary and interconnected research laboratories)...

This little project is the mainboard for a noise activated roller-blind and the circuit incorporates 31 through-hole components and 20 SMD components. Now time to begin testing! PS: Please excuse the soldering submitted by /u/hjw5774 [link] [comments]

Проєктна аспірантура в КПІ ім. Ігоря Сікорського для вступників 2026 року kpi вт, 04/21/2026 - 18:35

Power semiconductor maker ROHM Semiconductor of Kyoto, Japan has developed the latest device of its EcoSiC series: the 5th Generation silicon carbide (SiC) MOSFETs optimized for high-efficiency power applications. The technology is suitable for automotive electric powertrain systems – such as traction inverters for electric vehicles (xEVs) – as well as power supplies for AI servers and industrial equipment such as data centers...

submitted by /u/1Davide [link] [comments]

I have to brag, but first I have to tell on myself a little bit. You should really read the datasheet more thoroughly than I did. On the DRV8304 gate driver in 3PWM mode, the INLx pins need to be connected and pulled high for the phases to be turned on. If the pins are left unconnected or pulled low, the driver will put the phases into coast mode (all MOSFETs disabled). Also DVDD is an output pin, so don't connect it to 3V3. In this image you can see where I cut the trace from 3v3 to DVDD (between the C and the 5 of the C5 reference). Happily, I was able to scrape some soldermask off the trace before the cut, and then bodged some 34AWG magnet wire onto it and connected it to the INL pins to pull them high. After this (and some fixes to a couple of failed joints on other pins) the device was showing correct outputs on the phases. This is the first time I've ever bodged a PCB so I'm really excited I was able to get it working. This is just a test board for a more complete project I'm going to do down the line, so i'm not too worried about the longevity of this fix. But it's good to have this skill in the toolkit. submitted by /u/Direct_Rabbit_5389 [link] [comments]

It seems any expert who can spell “AI” has an opinion on its potential impact. There are countless predictions out there, many made with precision and confidence, and they are often contradictory.

Depending on who you listen to, AI will cause widespread disruption and unemployment, especially at starting and lower middle-levels, open up new vistas and ways of working and getting things done, resulting in the need to hardly do any work, or make us all work harder to stay in place…you get the picture. Whatever answer you want, you can find someone who has provided it.

I’ll jump in and give you my prediction on the impact of AI, with a two-part answer. First, I don’t know, and second, neither does anyone else.

If you look back at the track record of predictions about how past technical advances would unfold, one thing is clear: Most of these prediction underestimate or overestimate the reality, and most of them miss the actual nature of the change that these advances spur.

AI and analog: Round 1

Initially, I thought of doing a “thought experiment” about analog design and AI and go beyond the issues of general analog considerations. But then it made more sense to look at some of the specific stages of analog design, from ICs to circuits and systems, and all the way to final documentation.

However, I realized soon that it was a swamp. There were so many perspectives, so many considerations, and so many exceptions that it would take a lengthy treatise rather than a modest blog to begin to highlight the possibilities. The only meaningful possibility I could think of was using AI to help a beleaguered designer doing “best” component selection.

For example, this might be the task of choosing an op amp that fits the application priorities from among the dozens of vendors and thousands of models. Going further, AI might even help with some trade-off decisions (“show me an op amp that has 10% more dissipation than my stated maximum, if it gives me a 20% improvement in noise”).

AI and analog: Round 2

I then asked myself if it would make sense to instead look at AI and analog from the opposite direction: how can AI help analog-centric systems—meaning those with real-world front-end sensors—do a better job or perhaps implement innovative architectures.

My question was answered when I came across a project from researchers at the University of California, Davis. They used a different approach to miniaturization of a spectrometer that reduced its size to the scale of a grain of sand. This compact spectrometer-on-a-chip is designed for integration into portable devices. Instead of separating light into a spectrum physically, the system relies on computational reconstruction.

Conventional spectrometers rely on dispersive elements such as diffraction gratings or prisms to spatially separate light into its constituent wavelengths. But it requires long path lengths and bulky designs to separate individual wavelengths. The need to spatially disperse the light makes it challenging to miniaturize these delicate and expensive systems, making them unsuitable for portable applications.

On the contrary, the so-called reconstructive spectrometers use a unique set of numerous but compact photoresponsive detectors to directly encode the complex spectral information, which is later extracted using advanced computational algorithms. The team leveraged recent advances in machine learning and computational power, thus enabling further miniaturization toward chip-scale design with reduced manufacturing cost (Figure 1).

Figure 1 Working mechanisms of spectrometers include conventional spectrometers with uniform detector arrays that disperse the light spatially using diffraction gratings, which require long path lengths owing to their bulky nature (a). Then there are reconstructive spectrometers that utilize unique photodetectors capturing the minute variations in the incident light spectrum. The spectral information is then reconstructed using machine learning algorithms (b).

The chip replaces traditional optics with an array comprising 16 silicon detectors, each tuned to respond slightly differently to incoming light. Together, these detectors capture overlapping signals that encode the original spectrum, and they can provide wider bandwidth due to the use of staggered, tailored sensors for each spectrum slice. This process is similar to having multiple sensors that sample different elements of a complex signal, with the full picture emerging only after full analysis.

The analysis is performed using AI where the spectral reconstruction of an unknown spectrum is what has been defined as an inverse problem. The spectral reconstruction of the photon-trapping structures of the spectrometer is performed using a fully connected neural network that solves the inverse problem; an outline of the training and reconstruction process is shown in Figure 2.

Figure 2 Neural network model for spectral reconstruction shows demonstration of the training and reconstruction process of the neural network (a). Training and validation losses plotted against epoch show convergence of the model (b). The model is trained for 2,000 epochs with the loss function converging around 0.03, where comparison of spectral reconstruction uses matrix pseudo-inversion (c), linear combination of Gaussian functions (d), and neural network model (e).

The neural network model outperforms the other two methods in reconstructing the spectral profile of a 3-nm full width at half maximum (FWHM) laser peak. The root-mean-square error (RMSE) and Pearson’s R value (a correlation coefficient) for the neural network model are 0.046 and 0.87, respectively, indicating high accuracy in spectral reconstruction.

The training process involves learning the complex spectral encoding between the photocurrent of photon-trapping structure-enhanced photodetectors and their corresponding spectral information by back-propagating the loss function.

Their detailed modeling, analysis, and experimental results also demonstrated that this approach provided superior noise tolerance compared to traditional spectrometers despite the low photon intensity and small capture area. The fascinating story is presented in a highly readable paper “AI-augmented photon-trapping spectrometer-on-a-chip on silicon platform with extended near-infrared sensitivity” published in Advanced Photonics.

I’ll be honest: When I first saw this paper, my first if somewhat cynical thought was that this was just an attempt to dress up an old analog signal-chain technique with an AI “glow.” There are two basic ways to implement a precision sensor-based path. First, use top-grade components and various circuit topologies such as matched resistors to cancel errors to the extent possible. Second, use lesser components and just calibrate out inaccuracies.

But as I continued to read their paper, I saw that the neural network method added a new level of sophistication and ability to work through inherent weakness in the design and components to deliver an impressive result.

Where do you see AI helping, if at all, in the design cycle of an analog circuit or system? Allowing new topologies for sensor-based systems that were previously not viable or practical.

Related Content

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• Achieving analog precision via components and design, or just trim and go

The post What’s the impact of AI on analog design appeared first on EDN.

AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials at plants in China — has priced its underwritten public offering of 8,560,311 shares of common stock (announced on 20 April) at $64.25 per share...

This design based on an SR latch and two RC networks is, unlike many alternative solutions, neither complex nor expensive.

Single and differential capacitance sensors are widely used to measure linear and angle displacement, pressure, proximity, humidity, fluid level, inclination and acceleration. Both analog and digital circuits are used to interface the sensors (References 1-4). Some of the solutions tend to be complex and expensive (References 5-9).

Wow the engineering world with your unique design: Design Ideas Submission Guide

This Design Idea presents a very simple circuit to interface differential capacitance sensors (Figure 1). It is a relaxation oscillator made of an SR latch and two RC networks. When one of the capacitors is gradually charged through the corresponding resistor, the other capacitor is quickly discharged through a parallel switch. When the charging capacitor reaches the trip voltage VT of its gate, the latch changes its state. The other capacitor starts charging and the first one is quickly discharged. When the second charging capacitor reaches the trip level VT of its gate, the latch flips again returning to the initial state. The charge-discharge process repeats over and over again.

Figure 1 The sensor becomes part of a relaxation oscillator where one of the capacitors is charging when the other one is shorted; the two capacitors periodically swap their operation.

Signal VQ1 goes to a microcontroller, which measures time intervals t1 and t2 and calculates the average value VAVR = VDD * t1 / (t1 + t2). A number needs to be subtracted from this value so when the two capacitors are equal the average value is zero. Thus, the average value will be positive when C1 > C2 and negative when C1 < C2.

Circuit operation was tested with a bank of ten 50-pF capacitors. The left side of Figure 2 shows connections to set a duty cycle of 20%; the right side of the figure sets the duty cycle of 90%.

Figure 2 Sensor operation is simulated with a bank of 10 capacitors.

Figure 3 presents how period T and duty cycle D = t1 / T depend on the value of C1. Period barely changes between 96 and 98 µs, while the duty cycle is proportional to C1. A straight line fits perfectly the duty cycle data (the R2 factor equals 1); however, as Figure 4 shows, the line has a nonlinearity error of ±0.3%.

Figure 3 Circuit responses: at the top, the period is almost the same, below it, the duty cycle depends linearly on the value of C1.

Figure 4 The duty cycle response has a nonlinearity error of ±0.3 %.

The bump shape of the error graph means that a second-order polynomial may improve linearity. Indeed, equation y = 1*10-5 * x2 + 0.182 * x + 4.21 reduces the error down to ±0.1%. Such an equation is easy to implement in the microcontroller firmware.

Jordan Dimitrov is an electrical engineer & PhD with 40 years of experience. Currently, he teaches electrical and electronics courses at a Toronto community college.

Related Content

• From gap to signal: Non-contact capacitive displacement sensors
• Fundamentals in motion: Accelerometers demystified
• An introduction to capacitive sensing

References

1. Regtien P., E. Dertien. Sensors for mechatronics. 2nd ed., Ch. 5, Elsevier, 2018.
2. Northrop R. B. Introduction to instrumentation and measurement. 3rd ed., CRC Press, 2014.
3. Baxter L. Capacitive sensors. http://www.capsense.com/capsense-wp.pdf
4. Differential capacitance pressure sensor circuit. https://instrumentationtools.com/differential-capacitance-pressure-sensor-circuit/
5. Reverter F., O. Casas. Direct interface circuit for differential capacitive sensors. I2MTC 2008 – IEEE International Instrumentation and Measurement Technology Conference, Victoria, Vancouver Island, Canada, May 12-15, 2008.
6. Barile G. et al. Linear integrated interface for automatic differential capacitive sensing. Proceedings 2017, 1, 592.
7. Ferri G. et al. Automatic bridge-based interface for differential capacitive full sensing. 30th Eurosensors Conference, EUROSENSORS 2016. Procedia Engineering 168 (2016) 1585 – 1588.
8. Bai Y. et al. Absolute position sensing based on a robust differential capacitive sensor with a grounded shield window. Sensors (Basel). 2016 May; 16(5): 680. https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4883371/
9. De Marcellis A., C. Reig, M. Cubells-Beltrán. A capacitance-to-time converter-based electronic interface for differential capacitive sensors. MDPI Electronics, Jan 2019.

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