Новини світу мікро- та наноелектроніки

Last week, Intel held its third annual two-day Innovation event, a resurrection of the previous Intel Developer Forums (a “few” of which I attended back in the old days). The day-one keynote, focusing on silicon, was delivered by CEO Pat Gelsinger:

while Greg Lavender, Intel’s chief technology officer, handled the day-two keynote duties, centering on software:

The big news coming out of the show was the public unveil of Intel’s chiplet-implemented Meteor Lake CPU architecture, now referred to as Core Ultra in its high-end configurations (the company is deprecating the longstanding “i” from the Core 3/5/7/9 differentiation scheme):

Chiplets are, as any of you who’ve been following tech news lately, one of the “hottest” things in semiconductors right now. And for good reason, as I wrote (for example) in my 2021 retrospective coverage on processor architectures, specifically about AMD in that case:

Some of AMD’s success is due to the company’s “chiplet” packaging innovations, which have enabled it to cost-effectively stitch together multiple die on a unified package substrate to achieve a given aggregate core count, cache amount and (in some cases) embedded graphics capability, versus squeezing everything onto one much larger, lower-yielding sliver of silicon.

The thing is, the chiplet concept isn’t particularly new. Multi-chip and multi-die modules under a single package lid, whether arranged side-by-side and/or vertically stacked, have been around for a long time. The chiplet implementation has only come to the fore now because:

• Leading-edge processes have become incredibly difficult and costly to develop and ramp into high-volume production,
• That struggle and expense, coupled with the exponentially growing transistor counts on modern ICs, have negatively (and significantly so) impacted large-die manufacturing yields not only during initial semiconductor process ramps but also long-term, and
• Desirable variability both in process technology (DRAM versus logic, for example), process optimization (low power consumption versus high performance) and IC sourcing (internal fab versus foundry), not to mention the attractiveness of being able to rapidly mix-and-match various feature set combinations to address different (and evolving) market needs, also enhance the appeal of a multi- vs monolithic-die IC implementation.

Chiplets are “old news” at this point for Intel’s competitors. As previously mentioned, AMD’s been doing them with its CPUs, GPUs and APUs (CPU-plus-GPU hybrids) since 2019’s Zen 2 microarchitecture-based Ryzen 3000 series. Similarly, Apple’s first homegrown silicon for computers, 2020’s M1 SoC, integrated DRAM alongside the processor die:

The belatedly-but-ultimately unveiled highest transistor count M1 Ultra variant further stretched the concept by stitching together two distinct M1 Max die via a silicon interposer:

And (cue irony) it’s not even a new concept to Intel itself. Way back in early 2005 (speaking of IDFs), Intel was playing catch-up with AMD, which was first to release a true single-die dual-core CPU, the Athlon 64 X2. Intel’s counterpunch, the Pentium D, stitched together two single-core CPU die, in this case interacting via a northbridge intermediary vs directly. Still, what’s old is new again, eh? Intel also leveraged multi-die, single package techniques in 2010’s “Arrandale” CPU architecture, for example, and more recently in the 47-“tile” Ponte Vecchio datacenter GPU.

Although at a high level the “song remains the same”, different chiplet implementations vary in key factors such as the inherent cost of the technology, the performance latency and power consumption of the interconnect, and the ability (or lack thereof) to pack together multiple die tightly both horizontally and vertically. Intel, for example, has branded its latest approaches as EMIB (the Embedded Multi-Die Interconnect Bridge, for 2D multi-die interconnect) and Foveros (for vertical multi-die stacking purposes). Here’s a brief video on the latter:

And all that commonality-or-not aside, Intel’s mixing-and-matching of different slivers of silicon from different fab sources using different process lithographies, not to mention the partitioning of functions among those various silicon slivers, is also intriguing. Meteor Lake comprises four main die, each with its own power management subsystem:

• The Compute tile, fabricated on the company’s own Intel 4 (7 nm EUV) process and integrating a varying mix of “P” (performance) and “E” (efficiency) processing cores. It’s reminiscent of the initial “hybrid” combinations in the company’s 12th generation “Alder Lake” CPUs, but these cores are generationally improved in metrics such as average and peak clock speed, power consumption in various modes, and IPC (the average number of instructions per clock cycle, for both single- and multi-threaded code).
• The SoC tile, fabricated on TSMC’s N6 (6 nm) process. It integrates a network-on-chip processor, thereby acting as the conductor for communication between the other tiles. It also integrates cores for silicon and system security, and for AI inference (I’m guessing the latter derives from Intel’s 2016 acquisition of Movidius, although that’s just an uninformed hunch). And interestingly, it also contains its own “E” processor cores, acting as a lowest-power-consumption compute tile alternative for relevant usage scenarios.
• The GPU tile, whose purpose is likely self-explanatory, is fabricated on TSMC’s N5 (5 nm) process and derived from the technology in the company’s latest Arc Xe discrete graphics processors. That said, the media codec and display controller functions normally found in a GPU aren’t included in this tile. Instead, they’re also in the aforementioned SoC tile.
• And, last but not least, the I/O tile, the smallest (area-wise) of the four, and the one most likely to be omitted from low-end Meteor Lake implementations. As its name implies, it implements “boutique” functions such as Thunderbolt 4. And at least initially, it’ll also be fabricated at TSMC, specifically (as with the SoC tile) on the N6 process.

Initial rumors suggested that initial Meteor Lake products, targeting mobile computing implementations, might show up in October. Whether that month was originally hoped-for or not inside Intel, the official “due date” for CPUs (and presumably also systems based on them) is now December 14, which pushes them out beyond both the holiday 2023 shopping cycle (for consumers) and 2024 purchase cycle (for companies whose fiscal and calendar years coincide).

Why mobile first, versus desktop (or for that matter, server)? Mobile CPUs tend to prioritize low power consumption over peak performance and are also typically “kitted” with lower core counts than their desktop siblings, both attributes resonant with suppliers ramping up new die and packaged chip manufacturing processes. That said, Intel promises that desktop variants of Meteor Lake are also under development for production shipments beginning sometime next year. That said, and as presumed reassurance for skeptics, the company was already demoing its subsequent desktop client CPU, 2025’s Lunar Lake, last week. And as for servers, Intel has a next-generation 144-core (“E”-only) monolithic Xeon CPU also coming out on December 14, with a dual-chiplet 288-core version to follow next year.

One final thing, returning once again to mobile. Not announced last week but sneak-peeked (then quickly yanked) a few weeks prior at a packaging event Intel put on was a Meteor Lake derivative with 16 GBytes of LPDDR5 SDRAM onboard for the ride, alongside the logic “tiles”.

If you’re thinking “Apple Silicon”, you’re conceptually spot-on, an association which Intel management is seemingly happy to encourage. 2024 and beyond should very interesting…

*I realize, by the way, that I may be dating myself with the title of this piece. How many of you are, like me, old enough to remember the Intel Inside branding program, now deprecated (as of, gulp, nearly 20 years ago) but apparently still with a pulse?

Thoughts as always are welcomed in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

 Related Content

• A 2021 technology retrospective: Strange days indeed
• TSMC adds two variants to 2-nm node, will Intel catch up?
• Kill or reform the AXG graphics unit: Intel’s GPU dilemma
• Intel, Tower, and the diary of a failed acquisition bid
• Intel is founded, July 18, 1968

The post Intel’s next-generation CPUs hide chiplets inside* appeared first on EDN.

At iba 2023, NORD DRIVESYSTEMS will present its large range of innovative drives from October 22 to 26, 2023 at the Fairground Munich. The presentation in Hall B3, Stand 490, will focus in particular on NORD solutions for hygienically sensitive applications in the baking and confectionery industry.

NORD-surface-treatment-nsd-tupH.jpg: The nsd tupH surface treatment offered by NORD is a powerful corrosion protection for gear units, smooth-surface motors, frequency inverters and motor starters in wash- down-optimised cast aluminium housings. 

The food industry places great demands on reliable, efficient and easy-to-clean drive solutions. NORD DRIVESYSTEMS offers a wide range of solutions for this area that help to reliably realise hygienically sensitive applications.

Alternative to stainless steel: nsd tupH surface treatment

The nsd tupH process developed by NORD DRIVESYSTEMS makes drive surfaces very corrosion-resistant, similar to stainless steel This is not a coating, but a treatment based on an electrolytic process that creates a protective layer that is permanently bonded to the substrate material. So nothing can detach or flake off.

Drives with the nsd tupH surface treatment are largely resistant to acids and alkalis and can be cleaned reliably and hygienically. The efficient surface treatment is thus perfect for use in hygienically critical areas in the food, beverage, packaging, pharmaceutical or chemical industry. It is also the optimum solution for applications in extremely humid environments, for example in maritime and coastal areas.

Fanless or smooth IE5+ synchronous motors

The new IE5+ motor generation was designed by NORD DRIVESYSTEMS with a special focus on its use in the food or beverage industry as well as the intralogistics sector. The IE5+ generation is available in both fanless and smooth versions up to a power of 4.0 kW with a continuous torque from 1.6 to 18.2 Nm and speeds from 0 to 2,100 min-1. The smooth-surface, hygienic design of the fanless variant is particularly efficient, easy to clean, corrosion-resistant and wash-down capable. It is therefore ideal for reliable use in hygienically sensitive environments. If desired, nsd tupH surface treatment and the protection class IP69K are available. The outstanding feature of the particularly compact and energy-efficient synchronous motors is their constant high efficiency – up to 95% over a wide torque range. As a result, they also offer optimum energy consumption performance in partial load and speed ranges.

NORD-SAFOMI-IEC.jpg: SAFOMI-IEC adapter for MAXXDRIVE® industrial gear units from NORD
DRIVESYSTEMS combined with a drive motor: less components, increased operational reliability SAFOMI-IEC adapter for agitators

The SAFOMI-IEC adapter (SAFOMI = Sealless Adapter For Mixers) from NORD DRIVESYSTEMS, which was specially developed for mixers and agitators has an integrated oil expansion chamber and thus provides the MAXXDRIVE® industrial gear units with decisive advantages such as increased reliability and reduced maintenance. Compact and simple in design, the adapter has an integrated oil expansion volume. Oil tanks and hoses as well as the radial shaft seal that is subject to leakage and wear between gear unit and IEC cylinder are not required. SAFOMI is available for MAXXDRIVE® parallel gear units and in sizes 7 to 11, i.e. for maximum output torques from 25 to 75 kNm. The compact combination of the MAXXDRIVE® industrial gear unit, SAFOMI-IEC adapter and a drive motor is an optimal choice for mixer and agitator applications in order to reduce wearing and attached components.

The post Solutions from NORD DRIVESYSTEMS for the baking and confectionery industry Optimum protection appeared first on ELE Times.

Global resources are becoming increasingly scarce and responsible use of them is crucial to counteracting climate change. With over 57.4 million tons of electronic waste produced annually (2021) at a net worth of nearly $60 billion, e-waste constitutes one of the largest waste streams. Keeping resources circulating in the value chain for as long as possible is one way to tackle this challenge. A circular economy helps extend the lifecycle of products, saving resources and energy. Providing reliable spare parts for electronic devices plays a major role in this concept. Authentication solutions like the Infineon Technologies AG’s (FSE: IFX / OTCQX: IFNNY) OPTIGA Authenticate product family support the verification of spare parts as well as original products and contribute to a trustworthy, sustainable economic approach.

A circular approach to electronic products is defined by what is called the 6R concept: Reduce, reliability, repair, reuse, refurbish and recycle.

To Infineon, circular economy is relevant on different levels: These principles not only guide the company’s waste management for instance by reusing solvents in the manufacturing process. Infineon’s product design also aims to reduce resource consumption and hazardous waste and replace critical substances. On the other hand, Infineon delivers products to customers that help them innovate and create more sustainable solutions to the market based on the principles of circularity.

Sustainable and reliable – thanks to OPTIGA Authenticate security solutions

The Right to Repair regulation, for example, is not only under the umbrella of the European Green Deal, but also part of national sustainability programs worldwide. Infineon security solutions such as the OPTIGA Authenticate family support manufacturing companies in efficiently and purposefully addressing some of the key challenges of these new regulations and in reducing their environmental footprint.

The goal of the EU’s Right to Repair, Battery and Ecodesign initiatives is to save resources and increase energy efficiency of products. With regards to the Right to Repair this means that consumers not only have a right to the availability of spare parts. It should also be kept in mind that in many cases non-professionals have to be able to repair the product. Manufacturers therefore face the challenge of meeting their warranty claims, but also providing spare parts, while at the same time protecting the quality of their brand and their intellectual property as well as protecting the safety of end users.

“The OPTIGA Authenticate product family allows authentication of devices, the verification of spare parts and of the genuineness of original products. This enables product safety for end users and helps manufacturing companies meet quality and performance standards for electronic devices”, explains Josef Haid, Distinguished Engineer Security System Architectures Infineon Technologies. “Authenticators also create more security and transparency for consumers, since they can trust the authenticity and quality of devices and spare parts. Moreover, due to the increased demand for spare parts, it opens up a new market for the industry, covers potential warranty claims, and prevents counterfeiting at the same time.”

Authentication solutions protecting consumers and products

The OPTIGA Authenticate product family can be used in a wide range of replaceable components for example within a smartphone ecosystem. In a smartphone, elements such as batteries, displays and camera modules as well as power adapters, wireless chargers, and headphones (see graphic) can be equipped with authenticators. In addition, OPTIGA Authenticate security solutions can be used in other electronic devices such as power tools, notebooks, light electric vehicles, multicopters, VR/AR applications and many more. The mechanism is very simple: The OPTIGA Authenticate S security chip is integrated in a product, for example, the battery (client) of an e-scooter (host). This allows the host and client to communicate with one another and authenticate themselves, letting the host verify that the battery is original or that it conforms to certain standards. The authentication process itself is managed by the exchange of certificates, keys, and cryptographic tasks.

Authentication solutions such as the OPTIGA Authenticate product family are an easy and cost-efficient way for manufacturers to help meet legal requirements and protect their brand value from potential counterfeits. With the OPTIGA Authenticate product family, Infineon takes another step towards a circular economy, making it possible for its customers to build more sustainable solutions.

The post Circular economy, a path to a sustainable ecosystem: Infineon’s security solutions support the industry, the consumer, and the environment alike appeared first on ELE Times.

Infineon Technologies AG has taken over as head and coordinator of the broad-scope European research project EECONE (European ECOsystem for greeN Electronics), intended to make electronics in Europe more sustainable. The objective is to investigate the corresponding technologies along the entire value chain, from design, manufacture and use all the way to recycling. EECONE is one of the Key Digital Technologies research projects supported by the European Union as a Joint Undertaking. 49 partners are participating in the project, which has a volume of approximately 35 million euros total costs. The project is being funded by the European Union and the national governments of the participating companies with around 20 million euros.

“Electronics are fundamental to improving the sustainability of many applications.
But this is not sufficient, electronics themselves have to become greener,” says
Constanze Hufenbecher, Infineon Management Board member and Chief Digital
Transformation Officer. “Infineon is pleased to take on the lead role in the research
project EECONE in order to advance the circular economy together with our
partners along the value chain. The only way to achieve sustainability from design
and use and all the way to recycling is by working together.”

EECONE is aligned with the 6R concept (Reduce, Reliability, Repair, Reuse, Refurbish, Recycle); the amount of materials required by electronics is to be reduced, electronics are to be made more reliable, easier to fix and use again, and easier to recondition and to recycle. The project will investigate a total of ten application examples from the widest possible variety of fields in terms of developing green electronics. The applications are from the areas Automotive, Consumer Electronics, Health, Information and Communication Technologies, Aviation and Agriculture. Focus points are for example reducing the amount of material used by making circuit boards thinner or smaller, or improving sustainability by introducing materials which are easier to separate during recycling. Facilitating the replacement of not only circuit boards but also of semiconductors is to make it easier to repair devices. The technologies involved could also make it possible to reuse and recycle electronic components. The project will in addition develop technologies which for example generate and store their own power in IoT devices. New, ecologically friendly materials are to make it easier to recycle lithium-ion batteries. Artificial Intelligence will be used to prolong the service lives of electronic equipment, while tools for more sustainable electronic design, including comprehensive impact assessments for the use of electronics, are to be developed as well. EECONE also covers the use, dissemination and standardization of electronics and will train specialists in handling electronic refuse.

The EECONE research project has a planned duration of three years. It will establish decisive foundations for the sustainable development, manufacturing and use of electronics in Europe. The on-site inaugural event of the project will be held in Toulouse on 20 and 21 September 2023.

The post Infineon heads European research project for advancing the circular economy and sustainability of the electronics industry appeared first on ELE Times.

New developer software for STM32H5 leverages ST’s Secure Manager to simplify safe connectivity to AWS IoT devices platform

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, has added new software to its STM32Cube development tools that simplify connecting high-performing Internet of Things (IoT) devices to the AWS cloud.

ST has released the X-CUBE-AWS-H5 expansion package which enables a seamless and secure connection to the AWS cloud. It contains a set of libraries and application examples designed for high-performance microcontrollers of the STM32H5 series, which act as end devices.

The solution is built on the FreeRTOS open-source real-time operating system and ST’s Secure Manager embedded security software. The recently announced STM32H5 Discovery kit is available to use with this solution and lets developers easily and securely connect their STM32H5-based prototypes to AWS IoT Core.

 “The STM32H5 is ready for the next generation of IoT edge devices, bringing the performance to handle complex applications within a tight energy budget,” said Daniel Colonna, STM32 Marketing Director, STMicroelectronics. “The STM32Cube ecosystem helps developers unleash its powerful capabilities, accelerate development, and, with our latest software, connect securely to the powerful storage and data analytics services in the AWS cloud.”

STM32H5 is one of the most powerful Arm® Cortex®-M33 MCU series. Devices are programmed with their own immutable identity at the ST factory. Combined with ST’s Secure Manager, this simplifies registering smart devices to the AWS cloud and removes the need for costly infrastructure otherwise necessary to keep the identities of IoT objects secret during their production. 

Remote provisioning and administration of credentials will also be available via third-party service providers, during the production of devices and in the field.

The isolation properties provided by Secure Manager enable the intellectual property of multiple owners to be protected. This is also known as multitenant IP protection. It is part of a comprehensive set of services that protect the confidentiality and integrity of assets belonging to STM32 developers and partners, through development, manufacturing, and in the field.

This is a perfect fit for edge AI use cases, where models are running on the edge, on devices, protected by the Secure Manager, and further trained and securely updated via the cloud. The STM32Trust TEE Secure Manager makes stronger security simpler.

Overall, the STM32Cube ecosystem with STM32H5 microcontrollers provides developers with a powerful and secure platform for developing IoT applications that comply with future regulations and standards. STM32H5, introduced in March 2023, is the first to support Secure Manager and targets PSA Certified level 3 and SESIP3 certifications.

X-CUBE-AWS-H5 is ready to download now.

For more information, please go to www.st.com/x-cube-aws-h5.

The post STMicroelectronics releases secure software for STM32-powered edge devices connecting to AWS IoT Core appeared first on ELE Times.

The use of multiplexer chips (typically various members of the 405x family) to control gain in transimpedance (current to voltage conversion) signal-processing and data acquisition op-amp circuits, is an established practice. Using a multiplexer (mux) to select the desired feedback resistor generally works well, but mux non-ideality can sometimes introduce significant, or even intolerable, conversion error. This is mostly due, of course, to the fact that the Ron (on-resistance) of the switches that comprise muxes is always greater than zero, and their Roff (off-resistance) is less than infinity. 

Wow the engineering world with your unique design: Design Ideas Submission Guide

Happily, simple circuit topologies exist that can reduce (or even eradicate) the worst of these erroneous effects of these pesky switch parameters, the choice depending on which (Ron or Roff) is the more serious problem in a given application. Figure 1 illustrates a trick that cancels Ron error.

Figure 1 Canceling mux Ron error by taking the output signal from the gain resistor side of switches.

 Typical mux Ron values run from 100 to 1000 Ω, tend to vary significantly with fabrication process (e.g., polysilicon gate vs metal) signal level, supply voltage, and temperature. Because they are electrically in series with the resistors, they switch in and out of the circuit and create corresponding feedback gain error at the amplifier output. These errors aren’t too serious so long as the gain setting resistor is at least a couple orders of magnitude larger than Ron like Figure 1’s R4 is, but can become intolerable for lower values like R1’s.

The Figure 1 circuit entirely evades these issues by employing an additional mux (U1a) to pick the output signal, not directly from A1’s output on U1b pin 13, but from the U1b pin that drives the selected gain resistor (R1 thru R4), thus bypassing and eliminating Ron error.

So much for Ron, but what about the other end of mux switch error spectrum:  Roff? 

Mux Roff resistances are also highly dependent on temperature and fabrication process, usually range from ones to hundreds of megaohms, and are effectively in parallel with the gain setting resistors, and thus can cause troublesome errors when gain resistors are more than a few tens of kiloohms. Figure 2 suggests a work-around when this is the situation.

Figure 2 Canceling mux Roff error by the routing leakage current to ground with Rz.

Figure 2’s Rz resistors serve to route the Vout/Roff leakage currents of U1b to ground, leaving only millivolts to be blocked by U1a. This trick reduces Roff error by orders of magnitude.

Of course, this ploy effectively places two mux Ron resistances in series with the gain-set resistors (R1 through R4), and so it must be used with caution lest it cause more error than it cures.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Nearly 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Fault protection saves multiplexers, switches, and downstream circuitry
• Amplifier cancels common-mode voltage
• Digitally programmable-gain amplifier uses divergent-exponential curve
• A 50 MHz 50:50-square wave output frequency doubler/quadrupler

The post Make gain-control multiplexer Ron and Roff errors (mostly) disappear appeared first on EDN.

Mouser Electronics, Inc., the authorized global distributor with the newest electronic components and industrial automation products, is stocking the latest innovations from Nexperia, a leading global high-volume manufacturer and supplier of discretes, logic and MOSFET devices. A winner of Nexperia’s “2022 E-Tailer of The Year” award, Mouser continues to expand its customers’ product development process by offering more than 13,000 parts from Nexperia.

Nexperia’s extensive portfolio, available from Mouser, includes diodes, bipolar transistors, electrostatic discharge (ESD) protection devices, MOSFETs, GaN FETs and analog and logic ICs that meet stringent automotive industry standards. These products are recognized as benchmarks in efficiency, process, size, power and performance, with industry-leading energy and space-saving packages.

Some of the newest Nexperia products available from Mouser include the Nexperia NEH2000BYJ energy harvesting power management integrated circuit (PMIC). This high-performance energy harvesting solution for low-power applications collects energy generated by ambient sources, such as light, to charge storage elements such as rechargeable batteries or hybrid supercapacitors– thereby eliminating the need for battery swaps. Nexperia’s Maximum Power Point Tracking (MPPT) uses an embedded hill-climbing algorithm to deliver maximum power to the load, independent of specific characteristics of the harvesters. The NEH2000BY does not require any inductor to function, allowing for a reduced BOM cost and a simpler system design for product designers. The companion NEVB-NEH2000BY evaluation boards allow convenient evaluation of the NEH2000BY energy harvesting PMIC. The boards offer a small form factor for easy integration into prototype applications.

The Nexperia NBM5100A/B and NBM7100A/B battery life booster ICs are designed to remove the limitations associated with coin cell batteries to enhance performance. Nexperia Battery Management ICs extend the life of a typical non-rechargeable lithium coin cell battery by up to 10x compared to competing solutions while also increasing its peak output current capability by up to 25x. The NBM5100A and NBM7100A offer support for I2C interfaces, and the NBM5100B and NBM7100B provide support for SPI interfaces, allowing for design flexibility.

The Nexperia NBM5100A/B and NBM7100A/B battery life booster ICs are designed to remove the limitations associated with coin cell batteries to enhance performance. Nexperia Battery Management ICs extend the life of a typical non-rechargeable lithium coin cell battery by up to 10x compared to competing solutions while also increasing its peak output current capability by up to 25x. The NBM5100A and NBM7100A offer support for I2C interfaces, and the NBM5100B and NBM7100B provide support for SPI interfaces, allowing for design flexibility.

Nexperia eMode GaN FETs offer voltage ranges of 100V to 650V with superior switching performance. These FETs deliver fast transition and switching capability and excellent power efficiency with low QC and QOSS values. Nexperia Low Voltage (< 200V) eMode GaN FETs provide optimum flexibility in power systems, enabling faster charging for e-mobility and wired / wireless changing systems, as well as significant space and BOM savings in LiDAR and low noise in Class D audio amplifiers.

As a global authorized distributor, Mouser offers the widest selection of the newest semiconductors, electronic components and industrial automation products. Mouser’s customers can expect 100% certified, genuine products that are fully traceable from each of its manufacturer partners. To help speed customers’ designs, Mouser’s website hosts an extensive library of technical resources, including a Technical Resource Center, along with product data sheets, supplier-specific reference designs, application notes, technical design information, engineering tools and other helpful information.

Engineers can stay abreast of today’s exciting product, technology and application news through Mouser’s complimentary e-newsletter. Mouser’s email news and reference subscriptions are customizable to the unique and changing project needs of customers and subscribers. No other distributor gives engineers this much customization and control over the information they receive. Learn about emerging technologies, product trends and more by signing up today at https://sub.info.mouser.com/subscriber.

The post Authorized Distributor Mouser Electronics Spotlights Latest from Nexperia in Discretes, Power and MOSFET Devices appeared first on ELE Times.

Compact, powerful, and densely populated, the BOXER-8651AI illustrates a design breakthrough for AAEON.

Industry-leading designer and manufacturer of edge AI solutions, AAEON, has released the BOXER-8651AI, a compact fanless embedded AI System powered by the NVIDIA Jetson Orin NX module. Consequently, the BOXER-8651AI takes advantage of the module’s NVIDIA Ampere architecture GPU, featuring 1024 CUDA and 32 Tensor Cores, along with support for NVIDIA JetPack 5.0 and above to provide users with accelerated graphics, data processing, and image classification.

With a fanless chassis measuring just 105mm x 90mm x 52mm, the BOXER-8651AI is an extremely small solution that houses a dense range of interfaces, including DB-9 and DB-15 ports for RS-232 (Rx/Tx/CTS/RTS)/RS-485, CANBus, and DIO functions. Additionally, the device provides HDMI 2.1 display output, GbE LAN, and a variety of USB Type-A ports, supporting both USB 3.2 Gen 2 and USB 2.0 functionality.

The BOXER-8651AI, despite containing such powerful AI performance for its size, is built to operate in rugged conditions, boasting a -5°F to 131°F (-15°C to 55°C) temperature range alongside anti-shock and vibration resistance features. Consequently, the PC is ideally suited for wall mounted deployment across a range of environments.

For storage, the system offers an M.2 3052 B-Key slot to accommodate M.2 2242 B+M Key SSDs and an M.2 2230 E-Key slot, ensuring users can take full advantage of the NVIDIA JetPack 5.0 software stack. Alternatively, these expansion options provide support for add-on modules to facilitate wireless communication, such as 5G, Wi-Fi, and Bluetooth.

The BOXER-8651AI is now available for order via both the AAEON eShop and its standard sales channels.

The post AAEON’s BOXER-8651AI Harnesses NVIDIA Jetson Orin NX Power in Compact, Rugged PC Form appeared first on ELE Times.

Simplifying Designs and Saving Space in Consumer, Industrial, and Networking Applications, Industrial-Grade Devices Feature TLC NAND Flash Technology for Increased Reliability

Alliance Memory introduced new 32GB, 64GB, and 128GB industrial-grade embedded multi-media card (eMMC) solutions. For solid-state storage in consumer, industrial, and networking applications, the ASFC32G31T3-51BIN, ASFC64G31T5-51BIN, and ASFC128G32T5-51BIN integrate high-reliability TLC NAND flash memory with an eMMC controller and flash transition layer (FTL) management software in a single 11.5 mm by 13 mm 153-ball FBGA package.

The devices released today are compliant with the JEDEC eMMC v5.1 industry standard, supporting features such as boot operation, replay protected memory block (RPMB), device health report, field firmware updates, power-off notification, enhanced strobe features for faster and more reliable operation, write leveling, high-priority interrupt (HPI), secure trim/erase, and high-speed HS200 and HS400 modes. The ASFC32G31T3-51BIN, ASFC64G31T5-51BIN, and ASFC128G32T5-51BIN are also backwards-compatible with eMMC v4.5 and v5.0.

The eMMCs will be used in products such as smart watches, tablets, digital TVs, set-top boxes, VR and AR headsets, digital cameras, CCTV, infotainment, surveillance, automation, point-of-sale systems, and emerging embedded applications. For designers, the ASFC32G31T3-51BIN, ASFC64G31T5-51BIN, and ASFC128G32T5-51BIN simplify designs for fast and easy system integration in these products, speeding up product development and time to market while saving space by eliminating the need for an external controller. In addition, the device’s FTL software provides high reliability and stable performance with wear levelling and bad block management.

“With our latest eMMCs, we’ve extended our offering to include densities from 4GB all the way up to 128GB, providing designers with a wide range of options to meet their mass storage needs and solidifying our position as a leading supplier of eMMC technology,” said David Bagby, president and CEO, Alliance Memory. “Furthermore, with their TLC NAND flash technology, our new 32GB, 64GB, and 128GB solutions deliver even higher reliability, endurance, and performance, while maintaining the same ease of integration as our lower density devices.”

The ASFC32G31T3-51BIN, ASFC64G31T5-51BIN, and ASFC128G32T5-51BIN operate over an industrial temperature range of -40°C to +85°C and offer programmable bus widths of x1, x4, and x8. The device’s NAND memory with internal LDO can be powered with a single 3V supply voltage, while the controller can be powered by 1.8V or 3V dual supply voltages.

Samples of the eMMCs are available now. Production quantities are available with lead times of eight to 10 weeks.

The post Alliance Memory Expands eMMC Offering With New 32GB, 64GB, and 128GB Solutions appeared first on ELE Times.

One of the primary goals for the power supply industry is to bring higher power conversion efficiency and power density to power devices in applications such as data centers and 5G. Integrating a driver circuit and power MOSFET—known as a DrMOS—into an IC increases power density and efficiency when compared to a conventional, discrete MOSFET with an individual driver IC.

Moreover, DrMOS’s flip-chip technology further optimizes the voltage regulator’s performance by reducing response time and reducing the inductance between the die and package (Figure 1).

Figure 1 Here is a comparison between conventional wire bond and flip-chip technology. Source: Monolithic Power Systems

However, parasitic inductance on the substrate and PCB significantly impacts the drain-to-source voltage (VDS) spike, and that’s due to resonance between parasitic inductance and MOSFET’s output capacitance (COSS). A high VDS spike can cause a MOSFET avalanche, which leads to device degradation and reliability issues. To prevent an avalanche breakdown on the MOSFET, there are several methods to alleviate voltage stress.

The first method is to apply a higher-voltage, double-diffused MOSFET (DMOS) process on the DrMOS. If this process is adopted in the power MOSFET design, it results in a higher on resistance (RDS(ON)) for the DrMOS due to a reduced number of paralleled DMOS within the same space.

The second method is to use a snubber circuit to suppress voltage spike. However, this method leads to extra loss on snubber circuit. Furthermore, adding a snubber circuit may not effectively lower the MOSFET’s VDS spike since the stray inductance that causes resonant behavior is mainly integrated in DrMOS’s package.

When trying to increase voltage regulator efficiency and reduce the MOSFET’s voltage spikes, the tradeoffs described above can make it difficult to quantify and optimize the effects of parasitic inductance on the PCB and substrate.

This article will first discuss parasitic inductance modeling. Next, the equivalent parasitic circuit model is applied in a SPICE simulation tool to predict the VDS switching spike. Experimental results will be presented to verify the feasibility of the parasitic model.

Parasitic inductance modeling on a DrMOS

To model parasitic inductance, 3D structures of both the DrMOS and PCB were built for a simulation analysis (Figure 2). Parameters such as the material, stack-up information and PCB as well as package layer thickness are crucial for modeling accuracy.

Figure 2 DrMOS and PCB’s 3D-modeling structure can be used to obtain parasitic inductance. Source: Monolithic Power Systems

After 3D-modeling the PCB and DrMOS, the parasitic inductance can be characterized and obtained via ANSYS Q3D extractor. Since this article focuses on the MOSFET’s VDS spike, the main simulation settings of interest are the parasitic parameters on the power nets and driver nets.

When considering the parasitic component obtained from Q3D extractor, the parasitic inductance matrix—including the self and mutual terms of each net on the DrMOS—can be selected under different frequency conditions. Since the resonant frequency for VDS on the high-side MOSFET (HS-FET) and low-side MOSFET (LS-FET) is between 300 MHz and 500 MHz, the parasitic inductance matrix under 300 MHz condition is adopted for further behavior model simulation.

Behavior model simulation on SPICE

After the equivalent parasitic component model is exported from Q3D, the effects of different types of decoupling capacitors on the PCB are taken into account. Due to the capacitance decay after applying a DC voltage on a multi-layer ceramic capacitor (MLCC), it’s important to consider the equivalent circuit of each individual MLCC under certain DC voltage bias conditions. Each consideration should be based on the MLCC’s operating voltage. Figure 3 shows the circuit configuration for the behavior model simulation on SPICE.

Figure 3 A circuit can be configured with a behavior model simulation. Source: Monolithic Power Systems

Table 1 shows the simulation and measurement conditions based on the schematic shown in Figure 3.

Table 1 The data shows the results of experimental test bench. Source: Monolithic Power Systems

Optimizing parasitic inductance

To suppress VDS spike without compromising efficiency, it’s vital to optimize parasitic inductance on the PCB and package. With advanced package technology, input capacitors can be integrated in the package to shorten the decoupling path (Figure 4). Paralleling the embedded capacitors in the package can effectively reduce the equivalent parasitic inductance on the DrMOS.

Figure 4 A 3D DrMOS structure with embedded capacitors optimizes the VDS spike. Source: Monolithic Power Systems

Table 2 shows the equivalent parasitic inductance and VDS spike when utilizing different decoupling capacitor configurations on DrMOS.

Table 2 Equivalent parasitic inductance and VDS spike are shown with different capacitor configurations. Source: Monolithic Power Systems

As the simulation results in Table 2 show, not only is the equivalent parasitic inductance lowered, but the VDS spike on MOSFET is also suppressed. Moreover, thanks to the MLCC’s low-ESR characteristics, no additional power loss is generated on the embedded input capacitors. Therefore, it’s possible to add different embedded input capacitors to reduce parasitic inductance in DrMOS applications.

DrMOS with embedded capacitors

This article has explained the effect of parasitic inductance on the VDS switching spike, as well as several methods to prevent an avalanche breakdown on the MOSFET due to the VDS switching spike. To quantify the effects of parasitic inductance on the VDS switching spike, parasitic inductance modeling is first introduced, and then behavior modeling on SPICE is proposed.

The results obtained via SPICE closely matched the experimental results for DrMOS solutions such as the MP87000-L, which means the behavior model can accurately predict the risk of an avalanche breakdown on the MOSFET.

To effectively suppress the VDS spike without any tradeoffs, embedded capacitors in the package were introduced. The behavior model simulation confirmed that these capacitors can reduce the equivalent parasitic inductance, and thus lower the VDS spike without additional loss.

Andrew Cheng is applications engineer at Monolithic Power Systems (MPS).

Lion Huang is senior staff applications engineer at Monolithic Power Systems (MPS).

Related Content

• Be aware of capacitor parasitics
• Parasitic inductance of a bypass capacitor
• Decreasing parasitic capacitance in IC layouts
• Power Supply Design Notes: Noise and Spikes
• Effects of Switching Frequency on Transient Response

The post Predicting VDS switching spike with SPICE simulation appeared first on EDN.

submitted by /u/giulioz [link] [comments]

submitted by /u/Hapiel [link] [comments]

Recently my £350 Bluetooth dongle had it stupid micro usb connector snap off. I have a 3D printer so I’m going to print a new case to contain one or two 18650 or 21700 batteries. I’ve found a PCB on Amazon that takes a USB-C connection and charges 18650/21700. I know the basics of electronics but wanted to double check before I blow up this £350 dongle Since the battery on it is a 3.7v and 18650/21700 are 3.7v too, can I just go from my 18650 bms to the connector where the old battery is directly? Or will I fry something? I’m worried that it could get fried when charging, I can’t find any specs for the battery it currently has. I won’t be charging the new battery through the dongle as the USB connector has broken off. Instead of trying to fix the traces and add a new one, I want to 1. Replace the battery with something bigger, and 2. Have a way to charge this Thanks for any help :) submitted by /u/A_MrBenMitchell [link] [comments]

This is a capacitive touch sensing number pad for a lock. I've not yet tested it, but the touch sensor is self calibrating, so it should work. I have tested that the sensor works with a loop of wire through the plastic sheet. I used a knife to cut out the traces and pads, but I used a printed template exported from Kicad, so I think I can still call it a "printed" circuit board. I'm aware that trace 5 is broken and has to be repaired. I've also been made aware that lock numpads and computer numpads have the keys in different orders, and I used the wrong one. submitted by /u/MikemkPK [link] [comments]

submitted by /u/AutoModerator
[link] [comments]

CloudSure provides continuous, proactive validation to harness cloud-native efficiencies and ensure reliable operations

Spirent Communications plc, the leading provider of test and assurance solutions for next-generation devices and networks, today announced availability of the industry’s first fully cloud-native solution to help communication service providers (CSPs) and cloud-native network function (CNF) vendors ensure resilient 5G services. An automated test platform, Spirent CloudSure evaluates and validates CNF resiliency within 5G networks with comprehensive testing capabilities to help ensure reliable service delivery, while reducing operational costs, and optimizing customer experience.

“Cloud-native environments represent a revolutionary new technical approach that breaks a handful of highly reliable, vertically integrated 5G functions into thousands of individual software components that run on a cloud optimized for performance and cost, but not reliability,” said Glenn Chagnot, Senior Director of Product Management for Cloud Solutions at Spirent. “Cloud-native marginalizes traditional testing and visibility approaches, demanding completely new processes and tooling to realize the potential benefits. CloudSure provides proactive, pre-deployment validation to test 5G services with real-world traffic operating on an imperfect cloud to ensure services are resilient and always available in operations.”

CloudSure has been engineered to help network operators deliver robust and resilient 5G services to end users in the complex, highly dynamic, cloud-native world. It enables:

• Reliable service delivery: Confirms 5G cloud-native network functions operate reliably under the most challenging cloud conditions for uninterrupted service delivery and long-term revenue growth.
• Reduced operational costs: Optimizes resource utilization and validates complex fault recovery mechanisms to avoid costly outages, 5G service interruptions and reduce operating expenses.
• Enhanced customer experience: Ensures resilient 5G service design, configuration, and performance to deliver high-quality user experiences to improve customer satisfaction and retention.
• Competitive advantage: Enables reliable, high-performing 5G services that meet customer expectations consistently, for a competitive edge in 5G and to attract new customers.

“Cloud-native deployment models are emerging as the foundation of 5G networks, yet CSPs are grappling with the challenge that each CNF has unique performance expectations within the cloud environment,” said Gorkem Yigit, Principal Analyst at Analysys Mason. “Spirent CloudSure steps in to help CSPs gain control over the complexity of these environments through validation, enabling them to deliver high-quality 5G services while realizing the efficiencies and operational benefits of the cloud.”

Ensuring 5G services survive cloud failures and degradations with minimal or no impact to users is essential to successful cloud-native technology adoption. A proactive approach and deeper cross-functional coordination are required to manage the complex and dynamic new environment, to get ahead of technology changes and gain visibility into the new, interdependent cloud-native worlds, with multiple vendors and constant release cycles.

CloudSure provides the new approach required by network operators to ensure 5G service resiliency, optimization and new service acceleration necessary for maximizing long-term revenue and ensuring reliable operations. CloudSure also complements Spirent’s market-leading Landslide 5G network test solution by injecting user-defined real-world cloud impairments and correlating their impact on cloud-native 5G services.

The post Spirent Unveils Industry-First Solution for Validating Resiliency of Cloud-Native 5G Services appeared first on ELE Times.

Enables Designers to Share Data Between Embedded and AI/ML Projects, Streamlining the Creation of Edge and Endpoint AI Applications

Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today announced that it has created interfaces between its Reality AI Tools and its e2 studio integrated development environment, enabling designers to seamlessly share data, projects and AI code modules between the two programs. Modules for real-time data handling have been integrated in Renesas MCU Software Development Kits[1] to facilitate data collection from Renesas kits or customer hardware that use these microcontrollers (MCUs). This integration enables faster design cycles for artificial intelligence (AI) and tiny machine learning (ML) applications at the edge and endpoint of IoT networks.

Since Renesas acquired Reality AI in 2022, it has made a concerted effort to study, improve, and simplify AI design. Reality AI Tools, a software environment built to support the full product development of AI applications, allows users to automatically explore sensor data and generate optimized models. Now Renesas is providing a seamless data pipeline between Reality AI Tools and the e2 studio environment used to program Renesas MCUs. Sensor data collected from Renesas MCU development kits and visualized and labelled in e2 studio can now be transferred to associated projects in Reality AI Tools with the push of a button. In addition, users now have the ability to download and integrate AI/ML classifiers generated in Reality AI Tools from within e2 studio.

“Successful AI implementations are built by developing and training models with real world input from sensor data,” said Mohammed Dogar, Vice President of Global Business Development and Ecosystem at Renesas. “By providing seamless data sharing between our Reality AI Tools and e2 studio products, we’re providing the market’s best solution to enable designers to quickly build accurate and powerful AI applications.”

In addition to data transfers, Renesas is providing cross-platform project awareness between embedded and AI environments. Users can now synchronize and transfer lists of projects in e2 studio from Reality AI Tools. They can also associate an e2 studio project with a Reality AI Tools project and create a new Reality AI Tools project from within e2 studio. For a quick overview of this process, customers can watch a video demonstration available here.

Renesas is also building a library of application examples and reference solutions internally and in collaboration with ecosystem partners. The examples offer a proof-of-concept or blueprint for specific use cases. The Renesas AI application library now features over 30 reference solutions for use-cases ranging across real-time analytics, vision and voice applications.

AI Live – A Collection of Keynotes, Panel Sessions and Tech Talks all About AI

On October 12, 2023, Renesas will present an online, half-day event focused entirely on AI-related topics. In addition to keynotes from executives and industry experts, a lively roundtable discussion is planned. Attendees will also be able to choose from a host of tech talks delving into details of various aspects of AI. Visit the Renesas AI Live event page to register and view the full agenda.

The post Renesas Extends Its AIoT Leadership with Integration of Reality AI Tools and e² studio IDE appeared first on ELE Times.

Took a broken CD V-700 apart and replaced the insides with a microcontroller and a new detector. submitted by /u/FingerNailGunk [link] [comments]