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Test Jig for my USBpwrMe project
 | Since i'm planning to build a bigger batch of USBpwrMe i actually need to test each unit in a fast and repeatable way. Therefore i have designed a test jig that will measure all functions. There are 2 voltage regulators that will supply the test jig itself with 5V but also a 6V regulator to be able to make a test of an over voltage circuit with a threshold of 5.6-5.7V. INA139 will monitor the current of the DUT thru a shunt of 0.5 ohm or less. This will be optimized depending on what the DUT will actually consume. On the test jig board a PIC Mcu will control and manage the whole test and test instructions and results will be presented on a 2x16lcd display. The test is not high tech but the DUT must be manipulated with external resistors and voltages to be tested. This is mostly handled by 3 relays. Connection to the DUT will be easy using the banana connectors and the USB outputs which has corresponding mating connectors on the test jig. Following steps will be performed 1 It will measure the current consumption of the board to see if there is excessive power consumption 2 It will change polarity on the DUT and measure if there is any voltage on the output. 3 It will will apply resistors on the D+ and D- lines och the USB-A connector and measure so that expected voltage appears. 4 It will apply resistors on the CC1 and CC2 line for the USB-C connector. Vbus1, Vbus2, CC1 and CC2 are measured. If negotiation is correct it will enable Vbus. 5 It will change input voltage from 5V to 6V and test so that the OVP protection works. 6 Finally it will test the OVP mode switch by telling user to turn of OVP. And measures that Vbus goes on. The test will hopefully test a unit under 5s. The Gerber files are already sent to manufacturer and are in production. Now you might wonder why a choose a to small board that won't fit the display. Well at first i did. And when i uploaded the gerbers files it was around 40Usd to get it manufactured and shipped. By reducing the height of the board with 3cm the cost was 12Usd. Since it's only a testjigg and will be put into a casing i rather save some money!!! The PCB has 4 layer stack up. Not really needed but it's much easier to route the signals and takes less time. The schematic and routing took around 5hours. Funny thing is that the test jig is way more advanced than the product it is itended to test :) :) [link] [comments] |
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Vcc delay
It was with humble spirit and a good dose of Mea Culpa that a semiconductor company, from whom some very large-scale digital large-scale integration (LSI) chips were purchased, had a problem (later corrected, thank goodness) in that their chips would malfunction when powering up if their +5V rail voltage rose too slowly as the system was being turned on.
The vendor’s recommendation was to apply a 0 V (off) to +5 V (on) rail voltage with a steeper rise time (< 45 ms) than our power supply could deliver. We decided that we needed a switching arrangement that would operate as follows in Figure 1.
Figure 1 Providing a steep +5-V rail voltage rise time.
One problem with making something like this was that the input voltage could indeed rise very slowly through ½ volt to 1 volt to 2 volts, and so forth, which were voltage levels that were well below specification limits for any voltage monitoring IC we could find.
The resulting operations were erratic and unpredictable at arbitrarily low input voltages. This did not help the LSI situation even one little bit. (Yes, I am aware of the pun.)
Remedy was achieved using the following circuit in Figure 2.
Figure 2 Rail voltage switch, four loads.
The result obtained was as follows:
Figure 3 Rail voltage delay and rise time speedup.
This worked predictably down to arbitrarily low power supply voltages because there would be no response whatsoever, as long as the TLV431 didn’t see some voltage high enough to get itself conducting.
When the power supply voltage did get high enough to turn on the TLV431 at the time we’re calling “t1”, the power MOSFETs would turn on, and there would be a downward but very short-duration transient voltage drop from the power supply, which would be recovered from very quickly. The rail voltage thus presented to the LSI chips had a sufficiently quick rise time of its own to make those chips happy.
The end result made a bunch of human beings happy, too.
John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).
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