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Infineon has added three PSOC Edge MCUs with Arm Cores and dual-domain architectures to ramp up edge performance.

The Connectivity Standards Alliance has released its IoT Device Security Specification V1.0 to unify many different standards for global use.

Microchip has added its ECC608 TrustMANAGER with Kudelski IoT’s keySTREAM software as a service (SaaS) to its Trust Platform of devices, services, and tools. The cloud-based key-management SaaS integrates with the ECC608 secure authentication IC to increase the security of IoT network-connected products. It also simplifies setup and lifecycle management.

The ECC608 TrustMANAGER IC stores and protects cryptographic keys and certificates, which are then managed and updated in the field via keySTREAM. This combination allows the setup of a self-serve root Certificate Authority and associated public key infrastructure (PKI). Users can create and manage a dynamic certificate chain and provision devices in the field the first time they are connected.

The ECC608 is the first security IC in the TrustMANAGER series. To get started, download the Trust Platform Design Suite and test the KeySTREAM use case under the ECC608.

Prices for the ECC608 TrustMANAGER start at $0.75 each in lots of 10,000 units. An activation fee is applied only after the device has been connected for the first time.

TrustMANAGER product page

Microchip Technology

Kudelski IoT

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A multichannel oscilloscope calibration system, the Fluke 9500C automates time-consuming testing to maintain scope accuracy and reliability. The 9500C provides simultaneous output on all channels and can be fully automated with MET/CAL software for hands-free operation.

A core component of the 9500C mainframe is the 9540C active head. Each mainframe can control up to five heads, enabling the calibration of a 4-channel oscilloscope with an external trigger. The ability to actively drive all four active heads at the same time with simultaneous output results in faster test times and eliminates lead changes.

The compact 9.4×4.6×2.2-cm active head generates calibration signals at the oscilloscope input. It enables the 9500C to deliver various signals: DC levels up to ±220 V, calibrated amplitude square waves up to 210 V pk-pk from 10 Hz to 100 kHz, and leveled sinewaves from 0.1 Hz to 4 GHz with precisely controlled pulse edges.

If full automation is not immediately required, the 9500C can be configured with just a few, or even one, active head. Additional heads can be easily added as needs change. To request a price quote, use the link to the product page below.

9500C product page

Fluke Calibration 

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LoRa Corecell full-duplex gateway reference designs from Semtech are tailored to address applications operating in the U.S. 915-MHz and China 490-MHz ISM bands. Both the SX1302CFD915W1-H (915-MHz) and SX1302CFD490GW1 (490-MHz) reference designs leverage Semtech’s LoRa Core SX1302 digital baseband IC and SX1255/7 RF transceiver.

The reference design files are available to download from the Semtech website. While evaluation kits are not offered for purchase, the hardware used in the design comprises a Corecell board populated with the LoRa Core chips, a duplexer, and a Raspberry Pi. The design supports full-duplex operation with eight uplink channels and one downlink channel.

Using the capabilities of the SX1302 baseband IC, the uplink channels can detect up to 64 LoRa packets and simultaneously demodulate 16 125-kHz LoRa packets with spreading factors between SF5 and SF12. The SX1302 also provides one 125/250/500-kHz demodulator for single SF operation and one (G)FSK demodulator for legacy applications.

The gateway implementation achieves a tenfold reduction in power compared to the previous generation of LoRa baseband ICs. With a discrete power amplifier and low-noise amplifier, transmit output power at the antenna port can be up to +27 dBm. Receive sensitivity can be as low as -140.8 dBm for the U.S. 915-MHz band and -137.4 dBm for the China 490-MHz band.

To learn more about the LoRa Corecell full-duplex gateway reference designs, read Semtech’s blog here.

SX1302CFD915GW1-H product page

SX1302CFD490GW1 product page

Semtech

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Toshiba’s SmartMCD series of gate drivers with embedded MCUs offers sensorless control of three-phase BLDC motors in automotive applications. The first entry in the series, the TB9M003FG combines a 32-bit Arm Cortex-M0 core, 64 kbytes of flash memory, and power control functions for driving N-channel power MOSFETs in drive systems for water pumps, oil pumps, fans, and blowers.

The integration of a microcontroller helps reduce design size and component count, while enabling complex motor control. To minimize the load on the MCU, the gate driver employs a vector engine and hardware for sensorless sinewave control. Communication interfaces include a LIN transceiver and controller, two full-duplex serial interfaces (UARTs), and one SPI-I/F.

The TB9M003FG is AEC-Q100 Grade 0 qualified and operates over a temperature range of -40°C to +175°C. Toshiba has started volume shipments of the SmartMCD TB9M003FG gate driver. A reference design using the TB9M003FG in a motor drive circuit for automotive body electronics is available here.

TB9M003FG product page 

Toshiba Electronic Devices & Storage 

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The integrated Type 2GT multiband LoRa radio module from Murata reduces IoT device complexity and streamlines the certification process. It provides LoRa and Long Range-Frequency Hopping Spread Spectrum (LR-FHSS) communication over sub-GHz and 2.4-GHz ISM bands, as well as the satellite S-Band.

Along with Semtech’s LR1121 RF transceiver, the Type 2GT module contains a temperature-compensated crystal oscillator, a second 32-kHz crystal, an RF switch, and an RF matching network. Communication interfaces include SPI and multiple GPIOs. Housed in a 9.98×8.70×1.74-mm metal LGA package, the Type 2GT operates over a temperature range of -40°C to +85°C with a supply voltage of 1.8 V to 3.6 V.

The Type 2GT radio module is certified to European CE and American FCC standards, the Japanese TELEC standard, and the Canadian IC standard. Designers can reuse the module’s RF test reports across different certification authorities, easing compliance challenges.

Samples of the Type 2GT LoRa transceiver are available now. The part has also entered mass production.

Type 2GT product page

Murata Manufacturing 

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Cadence Design Systems is a tech-savvy organisation building the most intricate and in-demand electronic system designs, actively developing critical components in segments of IC design, verification, Digital design and signoff, Multiphysics analysis, PCB design, molecular simulation etc., and engineering marvels at the helm of technologies like AI, 3D-IC, mixed-signal, photonics, computational fluid dynamics etc. Also as an industry giant, the team caters to areas like 5G systems and subsystems, aerospace and defense, automotive, hyperscale computing, and life sciences.

Ms Madhavi Rao, Field Marketing Group Director EMEAI at Cadence Design Systems

Rashi Bajpai, Sub-Editor at ELE Times spoke with Ms Madhavi Rao, Field Marketing Group Director EMEAI at Cadence Design Systems on the various technologies Cadence is currently working on and their expertise in the field.

This is an excerpt from the conversation.

 

 

ELE Times: Brief us on Cadence’s Intelligent System Design strategy and the road ahead.

Madhavi Rao: Electronics is pervasive in every aspect of life and business, from consumer applications to automotive to cloud computing, and everything in between. As a result, the need for seamless integration, top performance, low power, small form factor, thermal considerations, and advanced features – to name a few – have become crucial.

To address these complexities, semiconductor and systems companies require comprehensive solutions encompass chips, IP, PCB & packaging, and system design solutions. Cadence has addressed this change in dynamics through its Intelligent System Design strategy, which includes the following key elements:

Design Excellence: Cadence offers an optimized EDA toolkit comprising tools and IP for semiconductor, package, and PCB design, with scalable distributed computing capabilities in the cloud. This allows customers to solve a broad range of large complex challenges.

System Innovation: Expanding beyond EDA to facilitate early software development and to optimize the entire system for various critical factors such as security, responsiveness, power efficiency, electromagnetics, thermal performance, Multiphysics considerations, and more.

Pervasive intelligence: To enable the creation of sophisticated systems, machine learning (ML) technologies have been incorporated into design tools and in workflows.

ELE Times: Cadence Design Systems is well-renowned in the electronics industry for its consumer-centric software used in designing chips and electronic systems. What in your opinion are the latest and upcoming trends that will drive the market of chip designing and the overall semiconductor industry in India?

Madhavi Rao: Over the years, semiconductor companies in India have played a crucial role in providing design services and contributing to research and development efforts for global companies. In the last few years, recognizing the strategic importance of semiconductor manufacturing and design for the country’s economic growth and technological advancement, there has been a greater push from the Government of India to make India self-reliant in electronics, and a semiconductor hub for the world. The government initiatives to attract investment and promote indigenous semiconductor development have created a positive atmosphere for the growth of the semiconductor industry.

Focus on Domestic Manufacturing and Investment in Fab Facilities

Countries the world over, including India, have been focusing on regional self-sufficiency in semiconductor manufacturing.

Indian policymakers and industry stakeholders have expedited their efforts to establish India as a hub for semiconductor manufacturing and supply chains, with various incentives and schemes. Of late we have seen a significant amount of investment from global players to set up fab facilities in India. These fab facilities are expected to catalyze the growth and development of the Indian semiconductor industry, driving innovation, creating jobs, enhancing supply chain resilience, and positioning India as a competitive player in the global semiconductor landscape.

Collaborations are critical in developing the local manufacturing ecosystem. Several international semiconductor companies are investing in India’s semiconductor ecosystem through collaborations, which provide expertise, technology transfer, and investment capital, fuelling the growth of the semiconductor industry in India.

Leveraging the opportunity of the huge domestic market

India’s consumer electronics market is growing exponentially, thanks to factors such as urbanization, increasing disposable income, and government initiatives such as Digital India and Make in India. This growth has led to a significant increase in demand for semiconductor chips. In addition, there are a multitude of opportunities for “designing for India” – creating electronic products that cater to India’s unique needs. This presents a huge opportunity for local entrepreneurs to innovate.

Design and Innovation Ecosystem

Globally, India is recognized as a chip design powerhouse. According to IESA, 20% of the world’s chip designers work out of India. Initiatives like the India Semiconductor Mission strengthen the design and innovation ecosystem, which will be crucial for developing more intellectual property (IP) and design startups in India.

ELE Times: How is Cadence addressing the requirements of 3D-IC design in several areas of implementation, and further help us understand the role of 3D IC technology in strengthening the semiconductor ecosystem in India?

Madhavi Rao: 3D-IC (Three-Dimensional Integrated Circuit) is a technology where multiple layers of integrated circuits (ICs) are stacked on top of each other rather than placed on a single silicon wafer. Compared to traditional two-dimensional ICs, this vertical stacking optimises space utilisation, enhances performance, and improves functionality.

Cadence has a 3D-IC solution that provides 3D design planning, implementation, and system analysis in a single, unified cockpit. It enables hardware and software co-verification and full-system power analysis using emulation and prototyping and chiplet-based PHY IP for connectivity with power, performance, and area (PPA) optimized for latency, bandwidth, and power. The solution also offers co-design capabilities with custom analog design and board design, integrated circuit (IC) signoff extraction, static timing analysis (STA) and signoff with signal and power integrity (SI/PI), electromagnetic interference (EMI), and thermal analysis.

Similar to the evolution of commercial third-party IP, which led to the development of a thriving market for soft and hard IP, the 3D-IC chiplet landscape offers significant opportunities for growth and the emergence of a market for commercial third-party chiplets. This evolution is expected to unfold over the coming years, requiring the definition and enforcement of standards to facilitate seamless integration. This could present a unique opportunity for India to take the lead.

ELE Times: In light of your recent collaboration with MeitY to provide EDA tools for free to companies looking to set up their chip design centres in India under the DLI scheme, how involved is Cadence in promoting the start-up ecosystem in India in the electronics and technology sector?

Madhavi Rao: For more than 20 years, Cadence has been closely involved in workforce development. From the establishment of the government’s Specialized Manpower Development Program (SMDP) Phases I and II, we have been actively taking part in the program. Currently we are working with MeitY for the Chips to Startup Program, aimed at training engineers in VLSI design.

Cadence is proud to be working closely with MeitY to realize the ambition of developing a pool of 85,000 trained engineers by 2027.

Over 350 academic institutions are enrolled in the The Cadence Academic Network, where students have access to Cadence’s world-class technology. In addition, Cadence has been actively engaged with various training institutes that are involved with upskilling, reskilling, and acquiring lateral skills to meet the industry’s demands.

Cadence has been working together with startups to nurture the semiconductor industry’s growth in India by empowering them with access to cutting-edge tools, technologies, and expertise since 2006.

Specific engagements of Cadence’s in promoting startups in India consist of:

• Providing tailored business models for startups.
• Cadence has partnered with startup incubators like FABCi – IIT Hyderabad and Electropreneur Park in Delhi and Bhubaneswar to provide software, guidance, and mentorship to semiconductor and electronics startups.
• Cadence also has strong ties with academic institutions across India, fostering a culture of innovation. Startups benefit from this ecosystem through collaborations on research projects, access to talent, and opportunities for academia-industry partnerships.

Through events, conferences, and customer forums, Cadence facilitates networking opportunities for startups.

ELE Times: With over 30% of its workforce in India, Cadence handles major R&D projects and product development from India. Shed some light on your global R&D goals and how India is helping global operations for Cadence.

Madhavi Rao: Cadence is one of the early MNCs to enter India. We have had a presence in India for over 35 years, with a workforce across Noida, Bengaluru, Ahmedabad, Hyderabad and Pune. 30% of our global employees are based in India.

Cadence offers end-to-end tools for chip and system design, including IP and hardware. Our R&D teams in India collaborate with R&D teams across the world on our product portfolios in digital design and signoff, functional verification, formal verification, hardware and prototyping, IP, custom and mixed-signal design, PCB and IC Packaging design and System design.

ELE Times: Give some insights into Cadence’s Millennium M1 platform, its key features, benefits, and applications.

Madhavi Rao: Designing mechanical systems for new levels of performance and efficiency has become a key priority in the automotive, aerospace and defense (A&D), energy, and turbomachinery industries. To optimize performance and reduce greenhouse gases, automotive designers are focused on improving fuel efficiency, reducing drag and noise, and extending electric vehicle range. Increasing efficiency, reducing carbon emissions and reducing maintenance frequency are top of mind for A&D and turbomachinery design engineers. Advances in multiphysics simulation technology are critical to achieving these goals. Cadence Millennium Platform addresses these needs.

Cadence Millennium Enterprise Multiphysics Platform is the industry’s first hardware/software accelerated digital twin solution for multiphysics system design and analysis. Targeted at one of the biggest opportunities for greater performance and efficiency, the first-generation Cadence Millennium M1 accelerates high-fidelity computational fluid dynamics (CFD) simulations. This turnkey solution includes graphics processing units (GPUs) from leading providers, extremely fast interconnections and an enhanced Cadence high-fidelity CFD software stack optimized for GPU acceleration and generative AI. Millennium M1 instances can be fused into a unified cluster, enabling customers to achieve an unprecedented same-day turnaround time and near-linear scalability when simulating complex mechanical systems.

Key highlights and benefits include:

• Performance: Combines best-in-class GPU-resident CFD solvers with dedicated GPU hardware to provide supercomputer-equivalent throughput per GPU of up to 1000 CPU cores
• Efficiency: Reduces turnaround time from weeks to hours with 20X better energy efficiency compared to its CPU equivalent
• Accuracy: Leverages Cadence Fidelity CFD solvers to provide unmatched accuracy to address complex simulation challenges
• High-Performance Computing: Built with an extensible architecture and massively scalable Fidelity solvers to provide near-linear scalability on multiple GPU nodes
• AI Digital Twin: Rapid generation of high-quality multiphysics data enables generative AI to create fast and reliable digital twin visualizations of the optimal system design solution
• Turnkey Solution: The industry’s first solution that couples GPU compute with modern and scalable CFD solvers, providing an optimized environment for accelerated CFD and multidisciplinary design and optimization
• Flexibility: Available with GPUs from leading vendors, in the cloud with minimum 8 GPU configurations, or on-premises with a minimum 32 GPU configurations—providing a flexible and scalable solution to fit each customer’s deployment needs.

The post Cadence’s Design and Software Strategy Aces Electronic and Technology Marvels appeared first on ELE Times.

A new family of Rohde & Schwarz power analyzers is now available in three models to meet all requirements for measuring voltage, current, power and total harmonic distortion on both DC and AC sources. The R&S NPA101 power meter provides all basic measurements, the R&S NPA501 power analyzer adds enhanced measurement functions and graphical analysis, and the R&S NPA701 compliance tester includes evaluation functions in line with IEC 62301 and EN 50564 for power consumption and EN 61000-3-2 for EMC harmonic emission testing.

The electrical characteristics of a device or module are a fundamental property that is measured throughout the electronics industry, starting with the development, during compliance testing, throughout production and during service. All models of the new R&S NPA family of power analyzers meet the requirements at all of these stages for power measurements at levels from 50 µW to 12 kW, at potential differences from 1 mV to 600 V and currents from 1 mA to 20 A. The R&S NPA501 and R&S NPA701 include interfaces for external probes or shunts to extend the range even further. All three models feature a high sampling rate of 500 ksample/s to detect even the shortest transient ripples in output. The 16-bit resolution A/D convertor ensures an accuracy of ± 0.05 % for both current and voltage readings.

The three instruments of the R&S NPA family include the same 23 standard measurements of power, current, voltage, harmonic distortion and energy. Users can select up to ten measurements to be displayed from a total of 37 to display simultaneously on the screen with a refresh rate of 100 ms. The screen contents can be output as a graphic to the USB port, the values can be recorded over time for all measurements with the logging function. The 5V measurement range provides best-in-class resolution for both power and energy measurements. A choice of Crest factor values of 1, 3 or 6 provides best-in-class flexibility to capture all peaks and maximize dynamic range.

All instruments of the family incorporate a LAN and USB interface for remote control; the R&S NPA501-G and R&S NPA701-G models also have a GPIB interface. A complete set of SCPI commands as well as drivers for LabVIEW, LabWindows/CVI and IVI.net are available for easy integration of the instruments into systems. Users benefit from the compact form and footprint; for system use, two instruments can be mounted side-by-side in a 19” rack.

In addition, all R&S NPA501 and R&S NPA701 models have maximum and minimum peak values for voltage, current and power. With the PASS/FAIL function, users can define up to six sets of maximum and minimum values to check easily whether the DUT’s output remains within the limits. Both instruments also feature a graphical display mode. In the time domain, users can view the power-up inrush characteristic, the voltage and current waveforms simultaneously, or a selection of parameters over longer periods. In the frequency domain, users can view up to the 50th harmonic, logarithmically if required or as a table.

The top model of the family, the R&S NPA701 compliance tester, additionally provides step-by-step procedures in line with IEC 62301 and EN 50564 for power consumption in low-power modes, and EN 61000-3-2 for EMC harmonic emissions. Users who are not familiar with the official standard procedures can be confident that they are performing compliance tests correctly and that the results are valid. The R&S NPA701 is the only power analyzer in its class that does not require a separate PC to perform compliance tests.

The R&S NPA family of power analyzers replaces the R&S HMC8015 power analyzers, both as a drop-in replacement and to use together as required. The instruments are part of the R&S Essentials portfolio, available from Rohde & Schwarz and selected distribution channel partners.

Rohde & Schwarz will demonstrate the new R&S NPA family of power analyzers at embedded world Exhibition in Nuremberg at booth 4-218 in hall 4. For more information on the R&S NPA family of power analyzers visit: www.rohde-schwarz.com/product/NPA

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III–V Epi Ltd of Glasgow, Scotland, UK says that an exceptional 2023 saw unprecedented growth, strengthening its position in both global photonics manufacture and the quantum supply chain...

The latest DC power supplies from Rohde & Schwarz for everyday manual use in the laboratory as well as for automated applications offer an extremely wide range of functions for entry-level instruments. The R&S NGC100 power supply series includes one, two, and three-channel models supplying up to 32 V, 10 A and 100 W DC power.

DC power supplies are essential throughout the electronics industry to provide the basic requirement of accurate and stable DC power from an AC source that may be subject to fluctuations and surges. The new R&S NGC100 power supply series not only meets this fundamental requirement, but also includes features, functions, and remote-control capabilities to support applications far more complex than steady output power. The series includes one, two, and three-channel models supplying 0-32 V per channel at up to 10 A and 100 W power output. The single-channel R&S NGC101 delivers up to 10 A, the two channel R&S NGC102 up to 5 A per channel, and the three-channel R&S NGC103 up to 3 A per channel. Small and light, two R&S NGC100 can be mounted next to each other in a 19” rack to optimize test setup footprints.

Each channel in the two and three-channel models is fully isolated for maximum flexibility. Users can use the channels independently as fully independent, extremely compact power supplies. Or they can combine the channels in series to increase the maximum potential difference to 96 V, or in parallel for currents up to 10 A. Full galvanic isolation means that channels can be connected to supply balanced circuits without worrying about grounding complications.

The basic performance of the R&S NGC100 as a power supply is excellent, both in terms of output range and output quality regarding low ripple and noise. The application support and additional features exceed expectations for this class of instrument. The remote sensing function ensures accuracy as users measure the voltage at the input of the circuit being powered, not at the output of the power supply. Users can also program voltage or current changes for a test sequence avoid steep ramp-ups to protect the device being powered, or simulate operating conditions.

The R&S NGC100 puts safety first by providing a full range of protective functions for electrical and thermal properties. Users can set the time and define sequences for switching on channels. Voltage and current values for the circuit to be powered can be logged.

All models of the R&S NGC100 have a standard dual interface with USB and LAN ports, and an optional GPIB interface is available for remote control. For external control, a digital trigger supports input in 1/2 Transistor-Transistor-Logic format to trigger functions such as logging. It is also possible to input sequences of voltage or current changes from an external program. An analog interface with a maximum input of 10V and 20 mA controls near-immediate changes in output voltage or current across the full range.

The R&S NGC100 power supply series replaces the R&S HMC804x power supplies, both as a drop-in replacement and to use together as required. The instruments are part of the R&S Essentials portfolio, available from Rohde & Schwarz and selected distribution channel partners.

Rohde & Schwarz will demonstrate the new R&S NGC100 power supply series at the embedded world Exhibition in Nuremberg at booth 4-218 in hall 4

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Anritsu Corporation introduces its newly developed Butler Matrix 4×4 (0.6 GHz to 7.125 GHz) MA8114A to expand Butler Matrix module lineup of simulating MIMO connections.

The MA8114A is a Butler Matrix transmission path with 4 input and 4 output ports and supports the 6 GHz band (5.925 GHz to 7.125 GHz), which is not supported by the existing Azimuth STACSIM-WB-(Static Channel Simulator) (ACC-339) used for evaluating 4×4 MIMO throughput of LTE/5G base stations and Wi-Fi devices.

Development Background

LTE/5G Base station and Wi-Fi device vendors use the OTA test environment to evaluate the maximum throughput with 4×4 MIMO for their products. This approach has the problem of low reproducibility of measurement results, however, because the transmission environment varies depending on the distance to the User Equipment (UE). While improving the reproducibility requires connecting the two devices using an RF cable, a simple coupler cannot simulate the MIMO transmission environment. The MA8114A ensures highly reproducible measurements.

The upper-limit frequency for NR FR1 has been extended beginning with 3GPP Release 17, and the 6 GHz band has been added to Wi-Fi 6E/7. The MA8114A supports a frequency range up to 7.125 GHz in preparation for countries launching services on new frequency bands.

Anritsu helps customers build a stable 5G/Wi-Fi evaluation environment and efficiently test throughput.

The product lineup of the Butler Matrix module also includes the Butler Matrix 8×8 (0.6 GHz to 7.125 GHz) MA8118A with 8 input and 8 output ports, which supports a frequency range up to 7.125 GHz as well. The MA8118A can be used not only for 8×8 MIMO throughput evaluation but also to enable efficient testing of devices having multiple RF ports.

Technical Terms

1. Butler Matrix
A type of microwave beamforming phased array proposed in 1958 by Judith Butler et al. with multiple input and output ports to divide power input to one port equally to output ports at different phases.

2. OTA
Abbreviation for Over The Air. As the Tx/Rx radio performance of a wireless device is measured over the air, the use of an OTA chamber, which is an anechoic chamber designed to block external radio waves, is recommended.

The post Anritsu Expands Module Lineup of Simulating MIMO Connections appeared first on ELE Times.

• The new tyre pressure monitoring system improves safety and user experiences
• ST’s software ecosystem tool, STM32Cube.AI, accelerates the development of the edge AI function operating on the STM32 microcontroller

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, has announced that Panasonic Cycle Technology, Co. Ltd. (Panasonic) has adopted the STM32F3 microcontroller (MCU) and edge AI development tool, STM32Cube.AI, for their TiMO A e-assisted bike. ST’s edge AI solutions provide a tyre pressure monitoring system (TPMS) that leverages an advanced AI function to improve rider safety and convenience.

Panasonic is a leading producer of e-assisted bikes in Japan and offers a wide variety of products for various uses to the Japanese market. Their electric-assist bicycle for school commuting, TiMO A, runs an AI application on the STM32F3 MCU to infer the tyre air pressures without using pressure sensors. Based on information from the motor and the bicycle speed sensor, the system generates a warning to inflate the tyres if necessary. ST’s edge AI development tool, STM32Cube.AI, enabled Panasonic to implement this edge AI function while fitting into STM32F3 embedded memory space. This new function simplifies tyre air-pressure maintenance, which enhances rider safety and prolongs the life of tyres and other cycle components. It also helps to reduce the cost and design work, as there is no need for additional hardware such as an air pressure sensor.

“We develop and manufacture e-assisted bikes with the mission of delivering environmentally friendly, safe, and comfortable transportation, accessible to all,” said Mr. Hiroyuki KAMO, Manager, Software Development Section, Development Department of Panasonic Cycle Technology. “ST’s STM32F3 MCU provides cost competitiveness and optimal functions and performance for e-assisted bikes. By combining the STM32F3 MCU with STM32Cube.AI, we were able to implement the innovative AI function without the need to change hardware. We will continue to increase the range of models with AI functions and strive to fulfil our mission by leveraging ST’s edge AI solutions.”

“ST has been actively working on the global proliferation of edge AI in both hardware and software, providing edge AI solutions to a wide range of products including industrial and consumer equipment,” said Marc Dupaquier, Managing Director of Artificial Intelligence Solutions, STMicroelectronics. “This collaboration marks a key step in our efforts, and we are delighted to have contributed to the first implementation of this AI function in Panasonic’s e-assisted bike. We will continue to propose AI use cases and solutions for diverse markets, anywhere we can help to augment our life.”

ST will showcase edge AI solutions, including the STM32 MCU and a variety of AI development tools, at the AI Expo at Tokyo Big Sight (May 22-24, 2024). The e-assisted bike and the motor unit (cutaway sample) from Panasonic Cycle Technology, which features the STM32F3 MCU and STM32Cube.AI, are also scheduled to be displayed at this expo.

How it works
The STM32F3 MCU adopted for the TIMO A is based on the Arm Cortex-M4 (with a maximum operating frequency of 72 MHz) and features a 128KB Flash, along with various high-performance analog and digital peripherals optimal for motor control. In addition to the new inflation warning function, the MCU determines the electric assistance level and controls the motor.

It leverages STM32Cube.AI to reduce the size of the neural network (NN) model and optimize memory allocation throughout the development of this AI function. STM32Cube.AI is ST’s free edge AI development tool that converts NN models learned by general AI frameworks into code for the STM32 MCU and optimizes these models. The tool optimized the NN model developed by Panasonic Cycle Technology for the STM32F3 MCU quickly and easily and implemented it in the flash memory, which has limited capacity.

ST offers a comprehensive edge AI ecosystem for spreading edge AI to devices used in a wide range of scenarios. The ecosystem includes STM32Cube.AI and also the NanoEdge AI Studio autoML tool. Both tools are part of the soon-to-be-available ST Edge AI Suite. All of them are available free of charge.

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NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — has announced a $3m investment in its common stock by strategic investors focused on strengthening and growing the company. The firm has also announced initial purchase orders from new customers in new markets...

A new family of microcontrollers optimized for machine learning (ML) applications at the edge claims to enable real-time command and response, eliminating the need for cloud connections while substituting high-performance microprocessors.

Infineon Technologies has unveiled the next generation of PSOC microcontrollers that are AI-enabled for real-time responsiveness in connected home devices, wearables, and industrial applications. The new PSOC Edge E8 series of MCUs—E81, E83, and E84—facilitates compute responsive AI while balancing performance and power requirements and providing embedded security for Internet of Thing (IoT), consumer, and industrial applications.

Figure 1 The new edge MCUs enable developers to quickly move from concept to product and facilitate ML-enabled IoT, consumer, and industrial applications. Source: Infineon

The PSOC Edge E81 utilizes the Arm Helium DSP technology and Infineon’s NNLite Neural Network (NN) accelerator. It uses a combination of Cortex-M55 plus DSP for the high-performance domain and Cortex-M33 and DSP for the low-power domain. E81 microcontrollers are primarily targeted at cost-effective design solutions.

The PSOC Edge E83 and E84 microcontrollers, while offering the same combination for high-performance and low-power domains, also use the Arm Ethos-U55 micro-NPU processor and provide a 480x improvement in ML performance compared to existing Cortex-M systems. At the same time, E83 and E84 use the NNlite accelerator for ML applications in the low-power compute domain.

The microcontroller trio

Steve Tateosian, senior VP of industrial MCUs for IoT, wireless and compute business at Infineon, spoke to EDN before the release of PSOC Edge E8 series MCUs. He said that the ML-enabled edge MCU classification aims to facilitate the right product for the right application at the right price point. He quoted a thermostat as an example to explain how these MCU tiers work.

With an E81 microcontroller, a basic thermostat may have an LCD doing cloud-based natural language recognition. On the other hand, a mid-range thermostat may want to recognize voice locally by implementing natural language on device itself, thus removing cloud from the equation altogether. That’s an E83 microcontroller.

Finally, for Nest-like high-end devices, designers can add features like gesture and motion control as well as low-power graphics display—up to 1028×768—for a rich graphical user interface (GUI). “All three devices support voice/audio sensing for activation and control, while the E83 and E84 MCUs deliver increased capabilities for advanced HMI implementations, including ML-based wake-up, vision-based position detection, and face/object recognition,” said Tateosian.

Figure 2 Three ML-enabled PSOC edge MCUs aim to facilitate the right product for the right application at the right price point. Source: Infineon

“Designers can create a cost-effective solution with E81, but if they want to add a stronger ML acceleration hardware, they move to E83,” he added. “They can use E84 if they want to add graphics support.”

Design support services

All three edge MCUs support extensive peripheral sets, on-chip memory, robust hardware security features and a variety of connectivity options including USB HS/FS with PHY CAN, Ethernet, WiFi 6, BTBLE, and Matter. “The PSOC Edge E8 series MCUs feature a rich peripheral mix with many options in terms of in-memory as well as external memory support,” Tateosian said.

When designing ML applications on edge devices, engineers must be conscious of the amount of code in general,” he added “So, the amount of memory as well as the type of memory located on the MCU are critical.” These MCUs offer an elegant solution in terms of on-chip RAM encompassing SRAM and RRAM content.

Hardware design support includes an evaluation base board with Arduino expansion header, sensor suite, BLE connectivity for provisioning and Wi-Fi for smartphone, and cloud connectivity. On the software side, the new PSOC Edge E8 series MCUs are compatible with the earlier versions of PSOC for edge MCUs to ensure that design engineers can reuse their software investments.

Moreover, Infineon’s ModusToolbox software platform provides a collection of development tools, libraries, and embedded runtime assets to complement the development experience. It also integrates Imagimob Studio, which Infineon acquired through its purchase of the Swedish firm last year. It delivers end-to-end ML development capability spanning from data to model deployment.

Infineon will demonstrate the capabilities of this MCU series for AI and ML applications at Embedded World in Nuremberg from 9 to 11 April 2024.

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• The AI-centric microcontrollers eye the new era of edge computing

The post The ML-enabled edge MCUs available in three design tiers appeared first on EDN.

In contrast to current cardiac sensors, which can only measure mechanical or electrical data in bulky form factors, the new one-atom-thin device measures both.

Introduction

Solar day lamps (SDL) are simple and cost-effective. A few examples of SDLs have been described in [1], [2] and [3]. An SDL without any energy storage element suffers from frequent changes in the light intensity. Also, a backup is required after sunset. The design of a hybrid lamp is given here. It uses solar PV panels and mains power sources and provides constant light output. This design can utilize solar energy even when the panel output is down to 10%. Proportionately, that much load is reduced on the mains supply.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Block diagram

The block diagram of proposed hybrid lamp is shown in Figure 1. It consists of an array of LEDs lamps: A1 to A9. Each of these lamps consists of five, 1 W white LEDs connected in series. These LEDs are controlled using the LED driver circuits.

Figure 1 Block diagram of the hybrid lamp design with 9 LEDs lamps where each lamp consists of five, 1 W white LEDs connected in series and all LEDs are controlled using LED driver circuits.

LEDs are powered using a 30 watt-peak (Wp) PV panel as well as from an adapter (AC-DC converter) as shown in Figure 1. The LED drivers are controlled through 9 digital output (DO) pins of the MCU. Solar panel voltage Vpvs is sensed using a potential divider circuit and is connected to the ADC input pin of MCU. Similarly, current flowing through the first LED array A1 is sensed and is connected to another ADC pin. The adapter output voltage VMF is sensed using potential divider circuit and is connected to a digital input (DI) pin of the MCU. This is a digital signal which is used to sense whether adapter power is available or not. One more DO pin is connected to the “adapter standby mode” pin to reduce power consumed by the adapter when all arrays are powered from solar panel and adapter is on no load.

Circuit Diagram

Figure 2 shows the circuit diagram. The adapter output VM is connected to the top (red) rail of the circuit. After passing through diode D19 (1N5822), voltage VMD is applied to the circuit. Similarly, the middle rail (yellow) is connected to the solar panel output Vpv. After passing through diode D20, voltage Vpvd is applied to the circuit. A big filter capacitor C2 (10000 µF 35V) is connected across panel terminals. This capacitor will eliminate sudden changes in panel voltage so that the firmware runs smoothly.

Figure 2 Circuit diagram of the proposed hybrid lamp where the adapter output VM is connected to the top (red) rail of the circuit and to the solar panel output Vpv is connected to the middle rail (yellow).

LED driver circuit for array A1 is shown in full detail. Array A1 consists of 5 white LEDs connected in series. It is connected to the ground terminal through R1; a 10 Ω, 2 W resistor. The voltage drop across R1 (Ipv1) is connected to ADC1 (pin 24) of the MCU IC3 ATMEGA 8 as shown in Figure 3. A1 is driven by two PNP transistors T3 and T4 (2N4033). Transistor T3 is controlled by the digital output PD0 of the MCU through NPN transistor T1 (BC546). The PD0 signal is inverted using the NOT gate of IC1 (74HCT04). This signal drives transistor T2 which drives T4.

When PD0 is LOW → T3 OFF, T4 ON (A1 on solar and green indicator LED2 ON)
When PD0 is HIGH → T3 ON, T4 OFF (A1 on mains and red indicator LED1 ON)

In the same way, remaining arrays A2 to A9 are controlled through their respective digital output signals. Note that resistors R2 to R9 are connected to the anodes of the LED array. This is done to reduce the wiring, as single ground wire connects to all the cathodes of the last LEDs of A2 to A9.

Figure 3 The MCU connection diagram.

The MCU and LED driver circuits are powered using regulator IC4 (LM7805). It’s input is connected to both VMD and Vpvd power rails through D21, D22, R77 and R78. Hence, 5 volts is available on either solar or mains power sources.

Figure 4 shows the circuit diagram of all digital outputs. It includes two 74HCT04 ICs, IC1 and IC2, for inverting a total of 9 digital output signals. The 18 output lines are connected to the LED driver circuits through 18 diodes D1 to D18 (1N4148). Figure 5 shows the assembled PCB with LED driver circuits and the MCU interface.

Figure 4 Interconnection diagram of all digital outputs, 18 output lines are connected to the LED driver circuits through 18 diodes (D1 to D18).

Figure 5 Assembled PCB showing LED driver circuits and MCU interface.

 Adapter (AC-DC converter) selection

Figure 6 shows the adapter used in the prototype having output voltage of 18 V. However, ideally to match the voltage at max power (Vmp) of the solar panel we need 17.5 V. One diode in series can drop the voltage by about 0.7 V. There are adapters available which have provisions for adjusting the output voltage within ±10% tolerance. Using this type of adapter, it is possible to set the output voltage to 17.5V.

Figure 6 Photographs of the 30 Wp, 2’ x 2’ solar panel (top) and 18V, 3 A adapter (bottom). A diode is used to drop the voltage closer to the ideal 17.5 V to match the Vmp of the solar panel.

 Specifications and calculations

The solar panel specifications are as follows:

1. Power Rating (P) = 30 Wp
2. Voltage at MAX Power (Vmp) = 17.5 V
3. Current at MAX Power (Imp) = 1.714 A

The calculations for the LED lamp are as follows:

1. Forward voltage of white LED = 3.12 V
2. Current through array A1 = [17.5 – (5 x 3.12)] / 10Ω = 0.19 A
3. Power consumed by array A1 = 17.5 * 0.19 = 3.325 W
4. Power consumed by 9 LED arrays = 9 x 3.325 = 29.9 W

Algorithm

As discussed earlier, the hybrid lamp draws power from both solar PV panels and the adapter. If both supplies are present, then it runs a maximum power point tracking (MPPT) algorithm to maximize solar power. Table 1 shows the operating modes.

Table 1 Operating modes of the hybrid lamp. If both supplies are present, the design runs an MPPT algorithm to maximize solar power.

 Variables

The following are the variables used for the algorithm:

• n: Number of arrays which are PV Powered (n = 9 is initially set to handle full solar power)
• PV_POWER: power drawn from PV panel
• PRESENT_MODE: present mode of operation
• NEW_MODE: new mode of operation

The permissible numerical values of PRESENT_MODE and NEW_MODE are as follows where valid value(s) of n are indicated in the brackets for each mode:

• 0: Solar Day Lamp mode (n = 9)
• 1: Mains Powered mode (n = 0)
• 2: MPPT (n varies from 1 to 9)

 Constants

The following are the constants used for the algorithm:

• POWER_MIN: The minimum value of power. If PV power is < POWER_MIN, then declare solar not present. (POWER_MIN = 1 W or 1600 counts)
• P_DELTA: This value is used for generating hysteresis. (P_DELTA = 1 W OR 1600 Counts)
• VPV_MIN: This value is used for checking whether PV power is available or not. PV Power is not available if Vpv < VPV_MIN. (16 V OR 800 Counts of ADC0)

Data

The following is the data used for the algorithm:

• Array P(n): This data is used by the algorithm to control LED lamps A1 to A9. Table 2 shows the array of constants defined over 10 power levels.

Table 2 An array of constants defined for 10 power levels.

ADC details

The following are the ADC specifications. A count of 1024 corresponds to a 5 V input to the ADC pin:

• ADC resolution: 10 bits (1024 counts)
• ADC reference voltage = 5 V

Vpv calculations

Solar panel output Vpv calculations are as follows:

• VPV_MIN = 16 V (when MPPT is running, Vpv is maintained above VPV_MIN)
• ADC input voltage for VPV_MIN = 16 * 0.2444 = 3.91 V
• ADC count for 3.91 V = (1024/5) * 3.91 = 801

VPV_MIN calculations

VPV_MIN calculations are as follows:

• VPV_MIN = 16 V (when MPPT is running, Vpv is maintained above VPV_MIN)
• ADC input voltage for VPV_MIN = 16 * 0.2444 = 3.91 V
• ADC count for 3.91 V = (1024/5) * 3.91 = 801

 Ipv calculations

Solar panel output current Ipv calculations are as follows:

• Panel power at maximum power point = 30 W
• Current at maximum power point = 30/17.5 = 1.714 A
• When all arrays A1 to A9 are ON, Current through each array = 1.714/9 = 0.19 A
• Drop across 10 Ω resistor R1 = 10 * 0.19 = 1.9 V
• ADC Count for 0.19 Amp = (1024/5) * 1.9 = 390 count

Power calculations

Finally, the power calculations can be seen below:

• Read ADC0 → Count for VPVS
• Read ADC1 → Count for IPV1
• PV_POWER_32 = ADC0 * ADC1 * n
• PV_POWER = PV_POWER_32 / 64 (Shift right by 6 bits)
• PV power generated when one array is ON = 876 * 390 = 341640 counts
• PV power generated when 9 arrays are ON (30W) = 341640 * 9 = 3074760 counts

To limit the resolution to 16 bits, the counts are divided by 64:

• Count for 30 W -> 3074760 / 64 = 48043.125
• Count for 1 W -> 48043/ 30 = 1601.4375 Count or 1600 approx

Flow charts

The flow charts required for development of embedded firmware are given in Figure 7, Figure 8, Figure 9, and Figure 10. At power ON, the algorithm initializes timer, ports, modes and enables timer interrupt. The algorithm is executed inside the timer interrupt service routine.

Figure 7 Initialization flow chart where at power ON, algorithm initializes timer, ports, modes and enables timer interrupt.

Figure 8 A portion of the interrupt service routine where the algorithm is executed.

Figure 9 The rest of the interrupt service routine where the algorithm is executed.

Figure 10 The MPPT flow chart that is run if both supplies are present.

 Fabrication and testing

The LED lamp metal core PCBs (MCPCBs) were mounted on three aluminum channels. The aluminum channels absorb the heat generated by these PCBs and provide structural support. The controller PCB is mounted on the back side of the LED array. The working of hybrid lamp is captured in the photographs shown in Figure 11 and Figure 12 where the lamps are working on 100% solar power and 100% mains power respectively. The lamp is placed in front of a mirror to check the light output from LED array. Simultaneously, we can see the PCB and the indicator LEDs. From these two Figures, it is clearly seen that we get same light output whether the array is solar powered or mains powered.

Figure 11 Lamp working on 100% solar energy (all green indicator LEDs are ON).

Figure 12 Lamp working on 100% mains power (all red indicator LEDs are ON).

In order to capture the dynamic workings of the lamp, when the solar energy is varying and the MPPT algorithm is running, see the video below.

In this video, we are able to see LED array light output in the mirror and also observe the indicator LEDs changing from green to red and vice versa sequentially. In this case, the solar panel is rotated in the sunlight to vary the PV power generated. This video confirms that the MPPT algorithm is working properly as the LED array gives a constant light output when there is wide variation in solar power. One green LED is ON, meaning 11% of the energy is coming from solar. So, depending upon the number of green LEDs that are ON, we can calculate the percentage reduction in the load on the mains power supply.

When the whole array is running on solar power, we can make the digital output line going to the standby input of the adapter high (refer to Figure 1). Thus, reducing the power consumed by the adapter under no-load condition. Please note that this feature has not been implemented in the present code.

 Power ASIC design

The hardware complexity can be reduced by designing a dedicated power ASIC. The main features of the proposed ASIC are as follows:

1. Number of LED driver circuits: 16
2. MAX Voltage rating of drivers : 50 V
3. MAX current rating of each driver: 0.5 A
4. Regulated control power supply: 5 V, 1A
5. Sensing circuits for: Vpvs, Ipv1, VM

 Design of a 500 W fixture

Based on the hybrid lamp design given here, a larger lighting fixture can be designed. Here, an example of such a system, which uses a single 500 Wp solar panel is given. The high-level details of proposed design are as follows:           

1. PV panel specifications: 500 Wp, Vmp = 35 V, Imp = 14.2 A
2. LED lamp power rating:11 Watts (11 white LEDs connected in series)
3. Number of lamps: 64 (8 x 8 array)
4. Number of ASICs required: 4

This lighting fixture can be installed in large shopping centers, hospitals, offices etc., where it will provide constant light while maximizing the utilization of available solar energy. Even on a cloudy day it can reduce the load on the mains supply by 10 to 20%. Such a system will have an ROI of 3 to 4 years. Furthermore, it offers many other benefits such as decentralized design, very short wiring, lower transmission losses and provides light in the daytime if the mains power fails.  

Vijay Deshpande recently retired after a 30-year career focused on power electronics and DSP projects, and now works mainly on solar PV systems.

Related Content and references:

1. Solar day lamp designs use passive and active current limiting circuits
2. Solar day lamp designs provide low-cost lighting solutions, Part 1
3. Solar day lamp designs provide low-cost lighting solutions, Part 2

The post Solar-mains hybrid lamp appeared first on EDN.

Penn State University has launched the Silicon Carbide Innovation Alliance (SCIA), a coalition of industry leaders, academic institutions and government support with a focus on becoming the USA’s central hub for research, development and workforce training in silicon carbide (SiC) crystal technology...