Новини світу мікро- та наноелектроніки

Apple branding is front and center in the company’s resurrected smart home “push”. Although broader ecosystem compatibility is also feasible, you’d never know it from the messaging.

Within my 2024 CES coverage, I devoted a section to the industry-developed Matter smart home interoperability standard, which had originated in December 2019, as well as to the associated Thread wireless protocol. I was not encouraged by the then-current industry-adoption status, nor with the implementation robustness of what few implementations did exist, although I clung to a sliver of sooner-or-later “hope springs eternal” optimism.

The Matter smart home communication standard, built on the foundation of the Thread (based on Zigbee) wireless protocol, had no shortage of associated press releases and product demos in Las Vegas this week. But to date, its implementation has been underwhelming (leading to a scathing but spot-on recent diatribe from The Verge, among other pieces), both in comparison to its backers’ rosy projections and its true potential.

Not that any of this was a surprise to me, alas. Consider that the fundamental premise of Matter and Thread was to unite the now-fragmented smart home device ecosystem. If you’re an up-and-coming startup in the space, you love industry standards, because they lower your market-entry barriers versus larger, more established competitors. Conversely, if you’re one of those larger, more established suppliers, you love barriers to entry for your competitors.

Therefore the lukewarm-at-best (and more frequently, nonexistent or flat-out broken) embrace of Matter and Thread by legacy smart home technology and product suppliers. Suffice it to say that I’m skeptical about Matter and Thread’s long-term prospects, albeit only cautiously so. I just don’t know what it might take to break the logjam that understandably prevents competitors from working together, in spite of the reality that a rising tide often does end up lifting all boats…or if you prefer, it’s often better to get a slice of a large pie versus the entirety of a much smaller pie.

I’ve also appropriately scattered Matter and Thread mentions within a series of follow-up pieces, most notably my subsequent CES 2025 summary.

A year later, is the situation better? Not really, candidly. For a more in-depth supplier-sourced perspective, I encourage you to read Aalyia’s coverage of her time spent last week in Silicon Labs’ product suite, including an interview with Daniel Cooley, CTO of the company. Cooley is spot-on when he notes that “it is not unusual for standards adoption to progress slower than desired.” I’ve seen this same scenario play out plenty of times in the past, and Matter and Thread (assuming they eventually achieve widespread success) won’t be the last. I’m reminded, for example, of a quote attributed to Bill Gates, that “We always overestimate the change that will occur in the next two years and underestimate the change that will occur in the next 10.”

Cooley is also spot-on when he notes that Matter and Thread don’t necessarily need to go together; the Matter connectivity standard can alternatively use Ethernet (either wireless, aka Wi-Fi, or wired) for transport, along with Bluetooth Low Energy for initial device setup purposes. And granted, there has been at least some progress with both Matter (in particular) and Thread over the past year.

Version 1.4 of the Matter specification, announced last November, promises (quoting from Ars Technica’s coverage) “more device types, improvements for working across ecosystems [editor note: a concept called “Enhanced Multi-Admin”], and tools for managing battery backups, solar panels, and heat pumps”, for example. And at CES, the Connectivity Standards Alliance (CSA), which runs Matter, announced that Apple, Google, and Samsung will accept its certification results for their various “Works With” programs, too. That said, Amazon is notably absent from the CSA’s fast-track certification list

As I write these words in October 2026, we’re nearing two years since Matter 1.4’s release. The spec is now at the v1.6 level, with further enhancements including belated support for cameras and other sensors, along with energy management systems; you can read all the details at the associated Wikipedia entry. And speaking of Silicon Labs, for additional background info I’ll commend to your attention a still-relevant EDN article series published in early 2023 and authored by Rob Alexander, the company’s Principal Product Manager for Matter:

• How can device makers streamline Matter certification
• Why Matter matters
• How to connect existing smart home devices to Matter

That all said, industry adoption still seems like it’s stuck in first gear, that is assuming it’s (arguably) moving forward at all. And specific to Apple, whose re-engagement with the smart home market went public earlier today, Matter seems to be little more than a convenient alternative means of achieving baseline access to Apple’s otherwise proprietary HomeKit ecosystem without need to pony up for a paid license, as was timely exemplified by yesterday’s TP-Link smart plug teardown. Indicative of this seeming irrelevance, Matter and Thread are mentioned only in passing in Apple’s press release covering partnerships with other companies.

Enter the brand-new HomeView

If I had to bet, I’d wager that the HomeView smart home hub has been stuck in the ready-for-production queue for a while now, awaiting a sufficiently robust AI-enhanced successor to the legacy Siri assistant service. The outcome product’s industrial design hearkens back to both Amazon’s latest-generation Echo Show series, released a year ago, and to Apple’s own 2002-2004 era iMac G4 computer.

Shown here is the product variant with a down-firing woofer and two passive radiators built into the base; a wall-mountable version with only the two 7” full-range drivers in the display is also available. Both cost $299, run an app-restricted operating system also branded HomeView, functionally reminiscent of the Apple Watch UI and with an intriguing derivative-of-CarPlay angle, and are based on the Apple Silicon A18 SoC; the DRAM size wasn’t announced (although in the iPhone SoC variant, it’s 8 GBytes). And there’s zero mention of Matter or Thread anywhere in the press release this time, although on-site media inquiries revealed that HomeView can in fact act as both a Matter controller and bridge, along with as a Thread border router.

The above conceptual usage promo video is admittedly compelling (IMHO, at least); I’ll cover shortly the privacy ramifications and implementation of the multi-user scenario shown in it.

Evolutionary advancements also garner announcements

The HomePod mini smart speaker was originally introduced in October 2020, with more colors added to the product line mix a year later (and a teardown by yours truly ~1.5 years after that), so a redesign was arguably overdue. We didn’t get much today, but it was at least something. The SoC inside is now the S10, versus the prior S5, both originally intended for various Apple Watch generations and this time Apple Intelligence-capable.

Then there’s the Apple TV 4K, the newest generation of which candidly and bafflingly seems to have been cut off at the knees by its creator on day one. Its SoC upgrade from the A15 Bionic in the 2022 version of the device to the A18 affords it AI capabilities…but Apple’s also bringing Siri AI to both the 2022 and 2021 versions of the device (presumably predominantly cloud processing-based in these older, latter cases), so if you already own one, you’re good. The newest version embeds a three-microphone array that lets you shout at it from afar…but the remote controls included with legacy Apple TV 4K versions already embed a microphone.

And speaking of remote controls, the newest Apple TV 4K’s version embeds a speaker so you can prompt it to emit a locating sound if it’s stuck between the cushions of your sofa…but that same remote control can also be purchased separately for $59 for use with legacy Apple TV 4K versions. And did I mention that the newest Apple TV 4K costs $299, both a $50 uptick from the current price of its equivalent-capacity predecessor (which itself saw a $100 price increase from the original $149 earlier this year) and twice the price of Google’s TV Streamer 4K (which itself is notably pricier than equivalents from Roku, Walmart, and the like)? The only other notable benefit that the newest Apple TV 4K affords is integrated stereo and surround sound support, but actualizing this particular aspiration necessitates one or two matched pairs of only second-generation HomePods and/or HomePod minis.

Privacy-assuring redundancy

Wrapping up, the aspect of today’s announcements that I actually found most interesting was what Apple referred to at the end of the HomeView press release as “Private and Secure by Design” and I alluded to by the “Distributed identity validation” mention in this piece’s title.

If you haven’t yet seen the conceptual usage promo video I embedded earlier, please go back and watch it before continuing. Two things you’ll likely note straightaway are that:

• The HomeView device dynamically recognizes each user audibly by voice and/or visibly by face, and
• The HomeView device responded by dynamically tailoring its UI to each user’s preferences as well as more generally by replying using that user’s dataset.

Voice and face recognition are admittedly getting more responsive and reliable all the time, but they’re still not perfect. The latter’s not even an option with the camera-less HomePod mini v2 and 2026 iteration of the Apple TV 4K. And when you’re dealing with a user’s personal information—emails and text messages, calendar and contacts data, music and image libraries, etc.—you need to be absolutely sure of who you believe you’re interacting with, no matter that you’re presumably interacting with someone who lives in the home where the device is located.

That’s why personalized AI is only available on today’s announced devices for users who:

• Have registered Apple accounts, and
• Have unlocked FaceID-capable iPhones (translation: not the latest iPhone Duo, for example) and iPads logged into those accounts and either connected to the same Wi-Fi network as the HomeView, HomePod mini v2 and/or 2026-version Apple TV 4K, or recently on Wi-Fi but currently logged in via cellular (I’m assuming this latter exception handles cases where someone’s iPad or iPhone briefly drops Wi-Fi).

It also, of course, conveniently excludes Android smartphone and tablet owners and the like. Ahem.

That’s “all” I’ve got for you today. Rumors suggest that Apple’s got another event scheduled for two weeks from today. We’ll see; if so, I’ll see you back here then. For now, as always, I welcome your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Apple’s question for the developer: Are you up for an AI do-over?
• The 2025 WWDC: From Intel, Apple’s Nearly Free, and the New Interfaces Are…More Shiny?
• The 2024 WWDC: AI stands for Apple Intelligence, you see…
• Apple’s processor cadence: A pending stutter-step for improved long-term edge inference?

The post Apple heads Home: Distributed identity validation, and how much does Matter matter? appeared first on EDN.

Lumentum Holdings Inc of San Jose, CA, USA (which designs and makes optical and photonic products for optical networks and lasers), Astera Labs Inc (which provides rack-scale AI infrastructure through purpose-built connectivity solutions) and Corning Inc are giving a joint demonstration of PCIe-over-optics connectivity for AI rack-scale architectures in Astera Labs’ booth #B34 at the 2026 Open Compute Project (OCP) Global Summit at the San Jose McEnery Convention Center (12–15 October). The rack-level demonstration combines an Astera Labs Scorpio Smart Fabric Switch with Lumentum’s 1060nm vertical-cavity surface-emitting laser (VCSEL)-based optical interconnect platform and Corning multi-mode fiber connectivity...

Rising 5G adoption across industrial IoT, connected automotive, and smartphones is driving demand for application-specific 5G chips and modules. Chipmakers are increasingly targeting 5G-Advanced, satellite non-terrestrial network (NTN) connectivity, 5G fixed wireless access (FWA), and 5G New Radio (NR).

Many of these 5G chips and modules deliver 3rd Generation Partnership Project (3GPP) Release (R) 17 and R18 features with backward compatibility, and now support R19 for 5G-Advanced, while setting the stage for 6G development. Chipmakers also target 5G RedCap (reduced capability) for cost-effective 5G devices in IoT applications.

Many of these solutions focus on higher integration and flexibility options to simplify development as well as reduce power consumption and footprint. Part of the integration effort also includes AI to enhance performance.

Here is a sample of 10 5G chips and modules introduced over the past year with higher performance that drive 5G adoption across a range of applications.

Modems and platforms

Qualcomm Technologies Inc. launched the X105 5G Modem-RF, featuring the industry’s first 3GPP R19-ready modem, which lays the foundation for 6G development and testing. The Qualcomm X105 5G-Advanced platform improves data speeds and power efficiency while claiming breakthroughs in quad-band GNSS and integrated NR-NTN support. Its integrated fifth-generation AI processor uses agentic AI in the modem to detect, classify, and optimize data traffic types based on user scenarios.

Qualcomm claims several industry firsts with the X105 platform. It features the first 6-nm RF transceiver, achieving up to 30% lower power consumption and 15% smaller board footprint than the previous generation; the first quad-frequency (L1, L2, L5, L6) GNSS engine with integrated multi-constellation support; and improved location accuracy.

The 5G Modem-RF also supports video calling, video streaming, data, voice, and messaging over NR-NTN. It delivers 14.8-Gbits/s peak download speeds while achieving up to 13.2 Gbits/s with sub-6-GHz bands. Qualcomm said it addresses the need for more uplink capacity and data speeds, achieving 4.2-Gbits/s peak uplink throughput.

With an R19-ready architecture, the X105 Modem-RF system is designed to accelerate 5G-Advanced adoption across smartphones, FWA, mobile broadband, automotive, XR, PCs, robotics, and industrial IoT.

Qualcomm’s X105 Modem-RF system (Source: Qualcomm Technologies Inc.)

Broadcom Inc. announced an integrated 5G and Wi-Fi 8 FWA platform in partnership with Samsung Electronics Co. Ltd. The broadband-optimized reference platform integrates Broadcom’s BCM6776 Wi-Fi 8 system-on-chip (SoC) with Samsung’s B1320 5G modem. Claimed as an industry-first platform, it combines 3GPP R17 connectivity with the emerging Wi-Fi 8 (IEEE 802.11bn) standard.

The ​​Broadcom BCM6776 is a highly optimized, tri-band Wi-Fi 8 SoC. Key features include a quad-core Arm network processor with support for two-stream 40-MHz channels in the 2.4-GHz band and four-stream 160-MHz channels in the 5- and 6-GHz bands, delivering a complete Wi-Fi 8 platform in a single chip.

Other features include integrated 2 × 2 2.4-GHz and 4 × 4 5-GHz and 6-GHz Wi-Fi 8 MAC/PHY/radio functionality, which simplifies system design and lowers cost; an integrated multi-gig PHY; and on-chip 2.4-GHz power amplifiers and support for third-generation digital pre-distortion, which reduces external components and improves RF efficiency. Dual PCIe Gen3 controllers enable simultaneous tri-band applications with a single additional chip.

The platform reduces bill-of-materials costs, simplifies board design, and reduces active power consumption by 50% compared with previous generations, according to Broadcom.

The Samsung B1320 is a highly integrated, power-efficient, 5-nm chipset solution that supports 3GPP R17. It can achieve 5G downlink speeds of 3.43 Gbits/s and uplink speeds of 1.17 Gbits/s. It supports a 4Rx/2Tx radio chain. The 5G modem with a quad-core Arm CPU and the BCM6776’s network processor can support full Wi-Fi to 5G throughput. The platform also includes a Power Class 1.5 RF transceiver, power management, and a GNSS receiver. It also supports NR-NTN and NB-NTN for satellite communications.

Qualcomm also delivers 5G to wearables with its Snapdragon Wear Elite Platform. The personal AI platform delivers personal, always-on, intelligent wearable computing devices. It works across WearOS by Google, Android, and Linux with a neural processing unit (NPU) for on-device AI and an advanced suite of ultra-low-power connectivity solutions.

Claiming a first‑of‑its‑kind, multimode connectivity architecture, the Snapdragon Wear Elite Platform integrates six advanced technologies:

• 5G RedCap delivers advanced, low-power cellular connectivity for connected intelligent applications.
• Micro‑power Wi‑Fi enables always‑on Wi‑Fi connectivity at significantly lower power for intelligent wearables, according to Qualcomm, which require continuous AI context synchronizing, richer data exchange, and seamless coordination with nearby devices and cloud services.
• Bluetooth 6.0 enables proximity‑aware interactions.
• UWB provides secure, precise, proximity‑based interactions.
• GNSS delivers advanced AI processing for precise location context.
• NB‑NTN enables satellite‑based, two‑way messaging and critical communications from intelligent wearables when cellular and Wi‑Fi coverage are unavailable.

Delivering advanced power efficiency and faster speed, the platform delivers a 5× improvement on single-core CPU performance and up to 7× faster GPU for app launching, multitasking, and smoother rendering. This enables the Snapdragon Wear Elite to run complex, 2 billion–parameter AI models locally, faster, and more securely.

The advanced power management enables 30% more battery use than the previous generation. When recharging is needed, rapid charging powers a device up to 50% in approximately 10 minutes.

Qualcomm’s Snapdragon Wear Elite Platform (Source: Qualcomm Technologies Inc.) 5G SoCs and RF chips

In late 2025, MediaTek introduced its Dimensity 9500 SoC, delivering new levels of on-device AI, console-class gaming, and power efficiency. According to MediaTek, the 9500 is designed to “supercharge the next wave of flagship 5G smartphones.”

The Dimensity 9500 features a third-generation All Big Core CPU design combining a 4.2-GHz ultra core, three premium cores, four performance cores, and four-lane UFS 4.1 storage. It delivers up to 32% higher single-core and 17% higher multicore performance than the previous generation, while the ultra core achieves up to 55% lower power consumption at peak performance, for longer battery life and greater productivity, and claims up to 30% more power efficiency while multitasking in games and social audio call apps.

The platform also features a new cache and memory architecture, claiming the industry’s first support for four-channel UFS4.1. It doubles read/write speeds and accelerates large AI model loading by 40%. In addition, the second-generation Dimensity Scheduling Engine delivers smoother responsiveness and sustained efficiency even under heavy workloads, according to MediaTek.

The Dimensity 9500 integrates the Arm G1-Ultra GPU, providing up to 33% higher peak performance and 42% improved power efficiency, and introduces higher frame rate interpolation, up to 120-fps raytracing, for console-level, quality gaming.

MediaTek said integrating the ninth-generation MediaTek NPU 990 with Generative AI Engine 2.0 doubles compute power and introduces BitNet 1.58-bit large model processing, which reduces power consumption by up to 33%. The Dimensity 9500 is also the first integrated compute-in-memory architecture for its newly added Super Efficient NPU.

Doubling its integer and floating-point computing capabilities enables 100% faster, 3 billion–parameter LLM output; 128K token long text processing; and 4K ultra-high-definition image generation, while reducing peak-performance power consumption by 56%, according to the company.

The Dimensity 9500, with the MediaTek Imagiq 1190, supports RAW-domain pre-processing, up to 200-MP capture, 30-fps continuous focus tracking, a new portrait engine, and cinematic 4K 60-fps portrait video. It also provides the latest MiraVision Adaptive Display technology.

The platform’s connectivity suite includes Bluetooth call enhancement, Wi-Fi fast transfer, and multi-network intelligence. The AI-powered communication technologies are reported to deliver up to 10% lower power in 5G and 20% lower power with Wi-Fi, while 5CC carrier aggregation increases bandwidth by 15%. In addition, AI positioning and network selection technologies offer 20% higher accuracy, as well as 50% lower network latency thanks to AI congestion prediction, according to the company.

Qorvo Inc. recently introduced a family of RF switches for 5G radios, designed to simplify multiband radio architectures. The family spans from 50 MHz to 10 GHz. These devices reduce component count, improve signal integrity, and enable more efficient RF system design across 5G infrastructure, as well as industrial, drone, and test applications.

Designers face increasing challenges maintaining isolation and signal integrity without adding size, loss, and complexity, as 5G radios expand to support wider bandwidths and more frequency bands, Qorvo said. Many designs rely on cascaded switch architectures or multiple narrowband devices, which increase insertion loss, degrade linearity and signal integrity, and add board space and design effort, according to the company.

The wideband, high-isolation RF switch family addresses these challenges, eliminating the need for cascaded switches in 5G radios. “This approach reduces insertion loss, maintains signal linearity, and simplifies design, improving receiver performance in applications such as digital pre-distortion feedback,” Qorvo said.

The family comprises three devices:

• The QPC6144 for high-isolation switching is a SP4T wideband switch that delivers greater than 65-dB isolation in a single device, eliminating the need for cascaded switches.
• The QPC6122 (SP2T) for compact wideband switching and QPC6188 (SP4T) for flexible wideband routing provide wideband absorptive switching across 50 MHz to 10 GHz, enabling a single platform approach to RF routing. These devices reduce component count and simplify design. They also maintain low insertion loss and strong linearity across wide bandwidths for calibration paths, general signal routing, and multiband operation.

Qorvo’s wideband, high-isolation RF switch family (Source: Qorvo Inc.)

Sivers Semiconductors announced earlier this year the general availability of its highly integrated 7- to 15-GHz Alpine0715 (Daybreak) multi-beamforming transmit/receive front-end IC for emerging 5G/6G FR3 applications and multifunction defense arrays. The FR3 frequencies are used for 5G-Advanced and 6G network deployments, delivering sub-6-GHz and wider bandwidths at mmWave frequencies.

The Alpine0715, housed in a 7.95 × 7.0-mm WLCSP package, offers high linear output power, low noise figure, high efficiency, and integrated beam-table memory in a single device, the company said, and the reconfigurable multi-beamforming architecture enables smaller, lower-cost antenna arrays

Featuring four dual-polarization TX and four dual-polarization RX elements, the Daybreak beamformer IC delivers 27-dB gain and 20-dBm OP1dB TX performance and 32-dB single-channel gain and <3-dB NF RX performance.

5G modules

At electronica India 2026, Cavli Wireless announced two 5G modules targeting automotive, IoT, and M2M applications. The AQ62 5G Autograde is an automotive-grade 5G NR sub-6-GHz module designed for next-generation telematics and connected vehicle applications, and the CQM211 5G NR Advanced sub-6-GHz module, compliant with 3GPP R16, is designed for IoT and M2M applications.

The CQM211 5G NR module delivers multi-gigabit 5G connectivity with LTE Cat 16 fallback and flexible integration options for new and existing hardware platforms. The module targets high-bandwidth applications such as Industry 4.0 equipment, smart surveillance systems, routers, gateways, mobile Wi-Fi, and other edge applications requiring high-speed connectivity.

Key specs include a Cortex-A7 processor clocked at up to 1.8 GHz, 2× carrier aggregation over NR, dual-band GNSS, a PCIe Gen3 interface, and DBI display support. It is available in LGA and M.2 form factors.

The AQ62 5G Autograde module for connected automotive applications delivers an embedded software environment for developing advanced applications such as telematics control units, ADAS systems, OBD solutions, and hybrid tracking applications. The AQ62, built on Yocto Linux Kernel 5.15 with SDK support, provides high-speed 5G NR connectivity with LTE Cat 18 fallback. It supports 3GPP R16.

The 5G NR automotive module features a quad-core Arm Cortex-A55 processor, L1+L2/L5 GNSS, and dual-SIM dual-standby support. The module also provides optional NG-eCall and NTN band support. The AQ62 is available in five regional variants: worldwide (WW), North America (NA), Eurasia and Japan (EAJ), India (IN), and Eurasia (EA).

Designed to accelerate Android-based IoT applications, Quectel Wireless Solutions announced two Android 16 smart modules: the SE505FE entry-level 5G smart module and the SH602FA high-performance 4G smart module. The modules provide integrated wireless connectivity and multimedia capabilities in compact form factors.

Here, we’ll focus on the 5G module, which provides Android-powered 5G connectivity to a wider range of IoT applications. The module is built on the MediaTek MT8863T chipset with a 2× Cortex-A76 and 6× Cortex-A55 processor architecture and Mali-G57 GPU. It supports 5G sub-6-GHz and LTE Cat 4, together with Wi-Fi 6, Bluetooth 5.2, and GNSS. Typical applications include AR/VR devices, digital signage, smart gateways, tablets, industrial PDAs, robotics, and intelligent video platforms.

The SE505FE series modules support multiple-input/multiple-output technology. Quectel said the concurrent use of multiple antennas at the receiver end on the same frequency band minimizes bit error rate and optimizes data speed, which improves communication quality.

The module supports multi-constellation GNSS (GPS, BDS, GLONASS, Galileo, and QZSS) receiver for fast and accurate positioning and offers a range of interfaces, including LCM, camera, touch panel, microphone, UART, USB, I2C, and SPI. It supports cameras up to 32 MP at 30 fps and 1080 × 2520 video recording and playback at 120 fps.

The module is housed in a 42.5 × 56.2 × 2.95-mm LGA package. The SE505FE series is available in three variants: SE505FE-EM, SE505FE-NA, and SE505FE-WF (supports Wi-Fi and Bluetooth only).

Quectel’s RM255C-GL and RG255C-NA (Source: Quectel Wireless Solutions)

Quectel also expanded its mid-tier 5G family with RedCap 3GPP R17 variants: the RM255C-GL for global markets and the RG255C-NA for North America.

5G RedCap has emerged as the technology to address the mid-tier connectivity gap between high-speed eMBB and narrowband IoT as 5G expands into industrial and IoT domains, Quectel said.

The RM255C-GL is a 5G sub-6-GHz RedCap module in the M.2 form factor, developed in accordance with 3GPP R17. It supports peak data rates of up to 223-Mbits/s downlink and 123-Mbits/s uplink, with 5G sub-6-GHz standalone operation and LTE Cat 4 fallback. It is backward-compatible with R15 and R16.

The RM255C-GL is pin-to-pin-compatible with Quectel’s RM5x0N and RM50xQ 5G series and both pin-to-pin and size-compatible with selected LTE-A and 4G modules, including the EM06, EM12 series, EM160R-GL, and EM05, which helps simplify the migration from LTE to 5G RedCap.

The module integrates Qualcomm IZat Gen 9VT location technology with optional multi-constellation GNSS support (GPS, GLONASS, BDS, Galileo, QZSS, and NavIC) for fast and accurate positioning. It also supports a range of interfaces, including USB 2.0, PCIe 2.0, and PCM, and offers USB drivers for Windows 10/11, Linux, and Android, extending the module into a wider range of RedCap applications.

The RG255C-NA 5G RedCap sub-6-GHz, housed in an LGA module, is designed in compliance with 3GPP R17. Purpose-built for industrial-grade applications, it supports key 5G capabilities including URLLC and network slicing. The module delivers peak data rates of up to 223-Mbits/s downlink and 123-Mbits/s uplink. It operates in 5G sub-6-GHz standalone mode with LTE Cat 4 fallback and is backward-compatible with R15 and R16.

The module is compatible with Quectel’s compact EG2x 4G module series, simplifying design upgrades while meeting mid-speed application requirements for higher capacity, low latency, and enhanced reliability in industrial and commercial deployments, the company said.

The RG255C-NA also integrates Qualcomm IZat Gen 9VT location technology, supporting multi-constellation GNSS including GPS, GLONASS, NavIC, BDS, QZSS, and Galileo. The integrated GNSS receiver streamlines product development and provides fast and accurate positioning, Quectel said.

The module also features a suite of industry-standard interfaces, including USB 2.0, PCIe 2.0, PCM, UART, SGMII, and SPI, along with USB driver support for Windows 10/11, Linux, and Android.

The RM255C-GL and RG255C-NA have completed the required regulatory and industry conformance certifications. The RG255C-NA is certified to FCC, IC, and PTCRB standards, while the RM255C-GL has achieved CE, RCM, FCC, IC, GCF, and PTCRB certifications.

The post 5G chips and modules power phones, wearables, IoT, and vehicles appeared first on EDN.

OVODYO is a desk clock that shows the time by rolling and flipping two 3D-printed spheres shaped like icosahedra. The hours sphere has 12 faces carrying the 12 hours, while the minutes sphere has 12 faces at 5-minute intervals. Six RGB LEDs in the centre indicate the intermediate minutes. The project is by ekaggrat singh kalsi, who describes the build on the project page on Hackaday.io.

The two icosahedral spheres are raised above the clock base by a brass support shaft. An internal drive shaft runs through the centre of the support shaft and drives a set of bevel gears. The gears rotate the outer shells around two axes, periodically cycling through all twelve faces. Only one set of numbers appears upright at a time.

How the bevel gear transmission works

The central shaft drives the central bevel gear. This in turn rotates the 90-degree bevel gear on the lower bevel gear with a 1:1 ratio. The rotation of the 90-degree bevel gear makes the inclined bevel gear rotate on the main bevel gear, with a ratio that flips the sphere.

The two movements follow different cadences. The hours sphere stops every one and a quarter turns, equal to 450 degrees. The minutes sphere stops every 90 degrees, equal to a quarter turn. So the hour advances with a long movement, while the minutes change much more often.

• Hours sphere: 12 faces, stops every 450 degrees
• Minutes sphere: 12 faces, stops every 90 degrees
• Outer diameter of the spheres: about 78 mm
• Overall dimensions: 383 x 78 x 163 mm
• Motors: 15 mm stepper motors with 1:99 gearbox
• Intermediate minute indication: 6 RGB LEDs in the centre

Electronics, Arduino firmware and Hall sensors

The electronic heart is an ATmega8, which drives the motors through a DRV8833. The code is written in the Arduino environment. The base has 3 parts: left and right house the motors and the drive shaft, the centre holds the electronics.

The motors find their starting position using a magnet and a 3144 Hall effect sensor. This way the firmware knows where to restart after every rotation. Since the minutes sphere turns every 5 minutes, to show the intermediate minutes there are 6 RGB LEDs in the centre that light up in sequence and blink. When the last LED finishes blinking the sphere turns and the LEDs reset.

Anyone wanting to rebuild OVODYO has to allow for two stepper motors with gearbox, a dual H-bridge driver and the position sensors. A compact stepper motor with gearbox is the kind of actuator needed to move the spheres without excessive bulk, while for the lighting part you could consider effect RGB LED modules to adapt to the minute indication.

The mechanical assembly remains the most delicate part. The bevel gears must be aligned precisely, because any play adds up along the chain and shifts the numbers relative to the expected position. In addition, the drive shaft must stay centred inside the brass support shaft, otherwise the sphere wobbles as it rotates.

3D printing, dimensions and calibration of the spheres

The two icosahedral spheres and the outer shells come from 3D printing. The outer diameter of the spheres is about 78 mm, so each face must stay readable from across a desk. Calibration of the starting position relies on the magnet and the Hall effect sensor, which give a fixed reference on every cycle.

The overall dimensions of the clock are 383 x 78 x 163 mm. The base is divided into three parts: on the left and right are the motors and the drive shaft, in the centre the electronics. This division simplifies both assembly and maintenance, because the drivers can be reached without dismantling the spheres.

Anyone wanting to follow the project will find the build story signed by ekaggrat singh kalsi on the project page on Hackaday.io. The starting point, however, remains the mechanics: without accurate alignment of the bevel gears, no firmware keeps the numbers upright.

Source: https://hackaday.io/project/206586-ovodyo

Related products

• NEMA 11 stepper motor – 1 A
• LED DJ Flower Effect 4 x 3 W RGBA

The post OVODYO: the desk clock that rolls two icosahedra appeared first on Open Electronics.

Knowing the mains frequency is important in many industries; the speeds of AC motors, for example, are dependent on it. The motor speed= (120*F)/P, where F is the mains frequency and P is the number of poles. Since P is a fixed number for any motor, speed varies in proportion to mains frequency. This frequency can be easily measured by MCU-based projects within a small gating time. The period is measured and 1/T is computed to obtain the frequency.

For non-MCU projects, the mains frequency can be measured with a simple counter within a gating time of 1 second. For 50 Hz (as followed in countries like mine, India), this will show 50 ± 1. If you increase the gating time to 10 seconds, the reading will be 500 ± 1. Finally, if you set the gating time to 100 seconds, the counter will show 5000 ± 1 which can be made to read 50.00. This accuracy is acceptable, but the gating time is too high for the measurement to update within a reasonable period.

What is the alternative? If you can multiply the frequency by 100 and then feed it to the counter, the counter will read 5000 within a gating time of 1 second, which can be made to show 50.00. You will get a resolution of 0.01 Hz while keeping the gating time as 1 second. This is what’s done by the circuit in Figure 1, which implements a by-100 frequency multiplier based on a modified PLL (phase lock loop).

Figure 1 This circuit multiplies the AC mains frequency by 100 and displays the result using a simple counter scheme. The component values shown assume a 50 Hz mains source.

How does it work?

• Transformer T1 gives an output of 6V AC; this same transformer can be used to produce 5V DC required to power the circuit. U1A is used as zero cross detector, whose output is the mains waveform converted to a square wave with a 50% duty cycle.
• The 6V AC output routes to pin 1 of U2A, an exclusive OR gate. This IC acts as a phase detector.
• U3, a 555 timer, functions as 5,000 Hz square wave generator.
• This frequency is divided by 10 using U4A, a 4518 counter.
• U4B, another 4518 counter, and U5, a 4585 comparator, operate as a frequency divide-by-5 circuit. In digital comparator U5, another 4585, inputs A0, A1, A2 and A3 are connected to the outputs Q0, Q1, Q2 and Q3 of the U4B previous stage. Input B3, B2, B1 and B0 are hardwired as 0101 (5). When the count in U4B reaches 5, its A=B output sends a pulse to U6A (another 4518 counter) and resets U4B so that it starts counting from zero again.
• U6A’s Q0 output divides the input frequency by 2.
• Thus, the combination of U4A, U4B, U5 and U6A operates as divide-by-100 circuit.
• This divide-by-100 output is connected to pin 2 of U2A, again acting as phase detector.
• U2A’s output feeds a low-pass filter circuit formed by R2 and C1, and is then connected back to pin 5 of the 555, circuit which works as voltage-controlled oscillator (VCO).
• Thus, the PLL circuit closes and the 555 output is then read in the counter as the AC mains frequency multiplied by 100.

If the mains frequency variation is in a narrow range of, say, 48 to 52 Hz, this PLL circuit works nicely. The power supply and ground pins of the digital ICs are not shown in the circuit diagram.

Note that since the divide-by-10 output of the 4518 IC is not a square wave with 50% duty cycle, the divide-by-10 second stage was done in two parts: divide-by-5 and divide-by-2, thus solving the challenge of the closing of the phase lock loop.

60 Hz operation notes

Countries such as the United States instead use a 60 Hz mains frequency. With some component changes, this circuit will also measure 60 Hz ± 2 Hz accurately.

• Transformer T1 should be a 110V/6V AC, 60Hz variant.
• The 555 multivibrator should be tuned to oscillate at 6000 Hz. R3=R4=11K and C2=0.01uF.
• For the low pass filter, R2=110K and C1=2.6uF.

The following video shows the operation of this circuit for 49.55 Hz and 50.55 Hz simulated mains frequencies.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

• Frequency division by any even number, with a 50% duty cycle output
• Unmasking the ghosts in your grid with power quality analyzers

The post Measure the AC mains frequency with an ordinary counter appeared first on EDN.

STMicroelectronics has highlighted its latest miniature 6-axis motion sensors designed to deliver accurate motion tracking and context-aware sensing for smart devices, drones and other electronic applications. Developed under the company’s Sustainable Technology framework, these sensors combine enhanced precision with compliance with stringent sustainable-materials requirements.

The new sensors combine six-axis motion sensing technology to allow electronic devices to identify and measure motion A 6-axis motion sensor generally includes both a three-axis accelerometer to sense linear acceleration and a three-axis gyroscope that measures the rate of rotation. These measurements combine to help devices recognize changes in position, orientation and movement.

“By maximizing the signal strength and resilience in an extremely compact form factor, the architecture of our latest 6-axis motion sensors will drive powerful new features in smart applications,” said Simone Ferri, Executive Vice President, MEMS Sub-Group, STMicroelectronics. “Moreover, meeting today’s leading sustainable-materials codes such as BPA-free, Pb-free and others helps smart-tech innovators address environmental and regulatory expectations as these become progressively tougher, encompassing additional classes of materials.”

In smart devices, this sensing ability can provide motion sensing, activity tracking, tilt and gesture-based control. In drones, the clear motion data can enable flight control systems to detect movement, track tilt and respond to tilt changes. The sensors can also enable other applications that require accurate motion sensing and event reconstruction.

“ST’s new LSM6DSK320X sensor delivers unprecedented vibration immunity that we just had to integrate and take advantage of immediately in our ongoing reference platform development,” said Jay Blackman, Leader, Betaflight.

“The LSM6DSK320X IMU is the new performance leader for smart and context-aware consumer technology, including UAVs,” said Dr. Zebo Zhou, Chief Technology Officer, Tianhe (Chengdu). “Drone flight controllers place extremely demanding requirements on an IMU: the sensor must not saturate during aggressive maneuvers, must maintain low noise under severe vibrations, and must be compact and power efficient. Of all the available devices we have evaluated, ST’s LSM6DSK320X was the best match.”

Technical Specifications

• The super-symmetric architecture comprises two mirrored electromechanical structures, acting in counter phase to each other, thereby cancelling the effects of external vibrations and shocks. Combined with a fully differential signal chain, this structure maximizes detected-signal strength and resilience.
• The internal structure is also extremely compact, enabling each IMU to contain one gyroscope with two separate accelerometers in a single package. The dual accelerometers allow simultaneous measurement of low-range disturbances up to ±16 g and high-g events up to ±320 g, ensuring these IMUs never miss an event. This contrasts with single-accelerometer IMUs that cannot perform measurements while switching between low-range and high-range modes.
• The consumer-oriented LSM6DSK320X and industrial-grade ISM6HGK256X also contain ST’s machine-learning core (MLC) that embeds AI processing directly in the sensor to reduce the application’s energy consumption and save system resources.
• Developers can leverage extra libraries including ST’s Motion XLF, and sensor-fusion and context awareness software, in addition to basic libraries, that enhance power and flexibility to address diverse applications.
• The new IMUs are supported within the ST MEMS Studio development environment. The STEVAL-MKI257A adapter board for the LSM6DSK320X and STEVAL-MKI258KA adapter board for the ISM6HGK256X will be available in the eSTore and from distributors by November 2026.
• The LSM6DSK320X for consumer applications operates over a broad temperature range, from -40°C to +85°C. The industrial-grade ISM6HGK256X handles temperatures from -40°C to +105°C and is included in ST’s 10-year longevity program that assures long-term component availability.
• The IMUs come in 2.5 mm x 3 mm x 0.83 mm packages and available from $4.6 for the consumer-oriented LSM6DSK320X and $5.1 for the industrial-grade ISM6HGK256X for orders of 1000 pieces.

The post STMicroelectronics Introduces Sustainable 6-Axis Motion Sensors for Smart Devices, Drones appeared first on ELE Times.

Built around Arduino and a special breakout board, it drives a relay when it detects and recognises a previously paired RFID tag; it is also suitable for reading contactless NFC cards.

RFID and NFC: a technology that is now widespread

Recognition and access control performed by turnstiles, gates and motorised doors driven by RFID electronic systems is now an established reality in many fields, involving both companies and apartment buildings; by now many of us carry in our pocket a passive wireless tag (transponder) that lets us enter the workplace, buy a drink from a food vending machine, get into the gym, but also open the front door of the house and clock in at work. The same technology, known as RFID, is the basis of the most recent and now widespread contactless electronic identification and payment systems, also known as NFC, built into debit cards or into mobile devices such as smartphones and tablets.

We devote the project you find in these pages to RFID/NFC technology; it is both a complete application for access control and a development and prototyping platform for very short range identification systems based on passive or active transponders (tags).

How a passive RFID tag works

Before getting into the heart of the project, let us make a preamble that helps in understanding how RFID works: systems of this kind behave as true transponders and are typically passive, meaning that the portable identification device (called a tag) only acts when it is excited by the fixed exciter system and has no autonomous power source of its own. Here is how it works: the detection system has an exciter circuit that generates an electromagnetic field, typically at low frequency (normally around 125 kHz, but systems operating at higher frequencies exist) and radiates it through a coil over a short distance; this ranges from a few cm for contactless payment systems and NFC (where transmission must be kept as narrow as possible to avoid fraudulent interception by hackers and malicious people) to a few tens of cm for pedestrian and vehicle access points.

Induction and identification of the tag

When a tag enters the electromagnetic field, an alternating voltage is induced in the coil inside it; this is rectified by a diode and charges a capacitor, between whose plates enough energy remains to run the tag’s logic. That logic is based on an encoder which, once powered, generates an identification code (usually unique) that drives the base of a transistor; at every logic high level the transistor conducts and electrically “loads” the coil, causing an induced reaction in the coil of the exciter circuit, as a result of which each conduction increases the current draw.

Through a sense resistor the exciter circuit detects the pulses and reconstructs the code produced by the encoder, thus managing to identify the tag. During the periods when the transistor loads the coil, the diode prevents the capacitor from discharging, so that the energy stored in it keeps the encoder running for the time needed to complete identification.

The project

That said, let us look at what the RFID identification system consists of; essentially it is a programmable transponder electronic lock with a user interface for easy use.

The project is based on an Arduino Uno fitted with an LCD Shield, a 5 volt relay module and a module specifically for reading RFID tags and NFC in general. The module in question ( Fig. 1 ) is the PN532, a NFC/RFID tag reader/writer (writing applies to active tags) with a coil integrated in the PCB, I²C, SPI and HSU (High Speed UART) communication interfaces, plus an indicator LED. The board, measuring 43x41x4 mm, can work as an RFID card reader/writer, as an NFC reader for Android smartphones (it only works with some types) and in wireless peer-to-peer mode between two similar devices.

The PN532 module: interfaces and supported tags

The circuit works with a voltage from 3.3 to 5 V and the communication interface, available on a row of pads on one side of the board, is selected via dip-switches as shown in Table 1 . In reality the board, as you can see in Fig.1 , carries two rows of contacts: one with four pads and one with 8; together they form both the data interfaces and the service connections, that is, power supply and control signals.

The row of four pads carries the I²C bus, namely SCL, SDA, common ground and power supply; the 8-pad row carries the complete SPI bus, so SCK, MISO, MOSI and SS, plus Vcc, GND, reset (RST0) and IRQ, which are pins to be used for direct control from a microcontroller: in particular IRQ provides a signal every time a tag detection is made, to request the microcontroller’s attention.

Supported tags and reading distance

Among the tags supported by the module are Mifare 1k, 4k (Mifare is a standard created by NXP Semiconductors and widely used in RFID and NFC cards), Ultralight and DesFire cards, as well as ISO/IEC 14443-4 cards such as CD97BX, CD light, Desfire, P5CN072 (SMX), Innovision Jewel cards such as IRT5001 and also FeliCa cards such as RCS_860 and RCS_854. The ISO/IEC 14443 standard provides for operation with an excitation electromagnetic field at a frequency of 13.56 MHz.

The maximum tag capture and communication distance for our PN532 module is typically between 30 and 70 mm. The module can be used with Arduino to build access control devices, etc., thanks to the library provided for managing it.

The library for managing it is supplied by Adafruit and can be downloaded both from the manufacturer’s site and from the page www.futurashop.it/NFC-RFID?search=RFiD (the library is called adafruit pn532).

Practical build

Good, let us now move on to assembling the system components; to sum up, the hardware as a whole consists of:

• Arduino UNO;
• LCD Keypad Shield (1686-SHIELD-LCD);
• RFID module (2846-PN532);
• 5V-10A relay module (2846-RELAY1CH).

The whole set is available from Futura Elettronica (online shop www.futurashop.it) and the product codes are those shown in brackets. Once the hardware has been obtained, it must be connected with Arduino jumpers following the connections given in the wiring diagram you find in these pages.

As for the RFID module, the connections to Arduino, or rather to the LCD Shield, are:

• the SCK contact goes to pin 13 of the shield;
• the MISO contact goes to pin 12 of the shield;
• the MOSI contact goes to pin 3 of the shield;
• the SS contact goes to pin 2 of the shield;
• the VCC contact goes to the 5V pin of the shield;
• ground (GND) goes to the GND pin of the shield.

Relay connections and user interface

The relay module, on the other hand, connects with its 5V to the 5V of the Arduino (together with the power supply of the RFID module) and GND to a free GND pin of the Arduino (or of the LCD Shield); the relay’s control input must be connected to pin D5 of the Arduino (of the Shield).

To manage the LCD shield, which forms the user interface of the system, the sketch includes the appropriate library (also downloadable from www.futurashop.it), which allows the alphanumeric display to be controlled and the buttons to be read.

Speaking of buttons, in the project they have the following functions:

• UP and DOWN let you move between menu items;
• SELECT is used to choose a menu item;
• DOWN starts interrogation of the transponder;
• LEFT, from the display’s initial screen, lets you test the output relay;
• RST; returns you to the initial screen.

To use the system we recommend enclosing all the electronics in a plastic case machined so that the buttons protrude and the LCD display remains visible; the RFID board can be glued with silicone sealant just below the front panel of the case, which, being plastic, does not interfere in any way with the electromagnetic field generated by the coil or with detection of the induced reaction.

That said, we can look at the system’s features.

Start-up and main menu

So let us take a look at how the whole thing works, starting by saying that it must be powered through the DC jack of the Arduino Uno with a mains power supply able to deliver at least 500 milliamperes and a voltage of 9 to 10 volts.

As soon as the device is powered up, the LCD display shows the words “Access Card Reader” ( Fig. 2 ).

The message “Lettura: Lettura in corso” (Reading: reading in progress) is then shown. The system will then read any tag present within range (the electromagnetic field) of the module, replying with a message granting or denying authorisation. Of course, all this only makes sense if the system has previously stored one or more tags, otherwise authorisation will always be denied; when authorisation is granted, the relay is activated.

From the main screen, pressing the “DOWN” button takes you to the menu, which offers the following options:

• Read Mode (Fig. 3), corresponding to the initial tag reading procedure;
• Edit Mode (Fig. 4), corresponding to the procedure for learning a tag and writing it to the Arduino memory;
• Delete Mode (Fig. 5), which lets you delete all the tags already learned whose code is in the Arduino memory.

Use the “UP” and “DOWN” buttons to scroll through the options, and press “SELECT” to select one. Press “RST” to return to the initial procedure at any time. While the “Main menu” screen is displayed you can press the “LEFT” button to test that the relay works correctly.

Edit mode: registering a new tag

Let’s briefly look at the modes, starting with Edit Mode: once selected, it lets the user register a new tag.

The procedure, which starts when the display shows the screen in Fig. 4, requires you to pass the tag to be learned over the module at a maximum distance of 7 cm, at which point the system automatically acquires its code and saves it among the authorised ones. If the tag is not detected (you will notice because the display content does not change), try passing it at a shorter distance until it is detected.

Bear in mind that the module can recognise certain types of tag, which are also the most common ones, so the tags you want it to learn must be among those summarised a few paragraphs back.

In any case, if the storage operation succeeds, the display will show the message “TESSERA SALVATA” (Fig. 6).

At this point, if you stay in Edit Mode and pass the same tag you have just learned again, its code is removed from memory; this deletion state is confirmed by the message “TESSERA RIMOSSA” (Fig. 7).

Delete mode and read mode

Let’s move on to Delete Mode, which starts when the display shows the screen already seen in Fig. 5; from there, to remove all the previously learned tags from memory you have to press the SELECT button; once you do, the display shows the screen visible in Fig. 8.

When the operation is complete you have to press the “RST” button to return to the main menu. Once the memory has been cleared, the display shows the screen visible in Fig. 9.

We finish with Read Mode: when you enter it from the main menu (with the screen of Fig. 3 on the display) and pass a tag in front of the module, what is shown in Fig. 8 appears.

In practice, when the module detects a tag within its field of action it interrogates it, and during this phase the display shows the message of the aforementioned figure. When the read is complete, two conditions shown in Fig. 9 can occur: if the tag is one of those already learned in Edit Mode, it is recognised and the display shows the message Acc. Consentito, together with the relay switching on. If instead the tag is not recognised as one of those already learned, Acc. Negato is shown and nothing happens to the relay.

Customising the firmware

These are all the functions provided, but of course by “tinkering” with the firmware you can implement others; for example, you can add various kinds of local signalling to the relay output, such as a buzzer that sounds when a tag is recognised or an LED that lights up when the aforementioned condition occurs.

If you want, without “tampering” with the Arduino sketch you can add an LED or a buzzer by connecting them in parallel (the LED requires a limiting resistor, typically 270 ohm…) to the relay coil, that is in series with the collector of an NPN transistor connected in common emitter with its base driven by the Arduino Uno output that controls the relay board.

The firmware

Having looked at the hardware and described how it works, let’s spend a few lines on the firmware that manages the electronic lock.

The sketch to load into the Arduino Uno board is quite bulky, so in Listing 1 we only reproduce the most significant portion, the one dealing with normal operation. You can download the whole sketch (.ino file) together with the files for this issue of the magazine.

Listing 1

if (success) { // Display some basic information about the card if(debug) { Serial.println(“Found an ISO14443A card”); Serial.print(“ UID Length: “);Serial.print(uidLength, DEC);Serial.println(“ bytes”); Serial.print(“ UID Value: “);nfc.PrintHex(uid, uidLength); } cardid = getCardIdAsInt(uid,uidLength); //is MASTER if (cardid == uid_master) { master_mode = 1; master_mode_counter = 0; if(debug) Serial.println(“MASTER detected, going into MASTER MODE “); } // is not MASTER else { int32_t findUid = findRfidInEeprom( uidLength, uid); // is MASTER MODE, include or exclude RFID from storage if(master_mode == 1) { // card rfid already exists so exlude it from storage if( findUid != -1) { if(debug) { Serial.println(“removing card from eeprom”); Serial.println(“ “); lcd.setCursor(0,1); lcd.print(“Tessera Rimossa “); delay(2000); lcd.setCursor(0,1); lcd.print(“Modifica… “); } deleteRfidfromEeprom(findUid, uidLength); } // card rfid not found in storage so include it else if (findUid == -1) { // check if space to store rfid available int32_t storageAddress = getEepromStorageAddress(uidLength); // storage available if(storageAddress >= 0) { if(debug) { Serial.print(“storing card in position = “);Serial.print(storageAddress);Serial.println(“ “); } // storing card writeRfidToEeprom( storageAddress, uidLength, uid); lcd.setCursor(0,1); lcd.print(“Tessera Salvata “); delay(2000); lcd.setCursor(0,1); lcd.print(“Modifica… “); } else { // no storage space available or error if(debug) Serial.println(“memory full or error”); } } master_mode = 0; } // no MASTER MODE, authorise or deny door access else { // card authorised if( findUid != -1) { // open door // write routine for door access, example set an output to high if(debug) Serial.println(“Card authorised”); lcd.clear(); lcd.setCursor(0,0); lcd.print(“Lettura:”); lcd.setCursor(0,1); lcd.print(“Acc. Consentito”); digitalWrite(11,HIGH); delay(2000); digitalWrite(11, LOW); lcd.setCursor(0,1); lcd.print(“Lettura in corso”); } else { // deny access if(debug) Serial.println(“Card not authorised”); lcd.clear(); lcd.setCursor(0,0); lcd.print(“Lettura:”); lcd.setCursor(0,1); lcd.print(“Acc. Negato”); delay(2000); lcd.setCursor(0,1); lcd.print(“Lettura in corso”); } } } delay(500); }

As usual the firmware starts with the definition of the I/Os and the inclusion of the libraries, of which there are two in this project: the one for the RFID reader and the one for the LCD Shield.

The setup follows and then we come to the portion shown in the aforementioned Listing 1, where, depending on the mode we have set using the shield’s buttons, the card (the RFID tag) will be stored, deleted or, in the case of “normal” operation, simply read to compare its identification code with the data in memory; in this case, if the code read is already present in the Arduino Flash memory, the relay on the board is activated.

The relay is activated in pulse mode, that is monostable, and the time it stays in the “energised” state (and therefore with the relay contact closed) is 2 seconds, as defined by this portion of code:

digitalWrite(11,HIGH); delay(2000); digitalWrite(11, LOW);

where digitalWrite (11, HIGH) is the instruction that activates digital line 11 (which controls the relay board), delay(2000) sets the time it stays at high level through the delay with which output D11 returns to low level and, finally, digitalWrite (11, LOW) brings the aforementioned Arduino line back to logic low.

If you want, you can change the relay activation time by changing, in the sketch, the value in brackets after delay, remembering that it is in milliseconds.

Conclusions

So we have reached the end of the description of this project, which, although it was born as an electronic lock with a transponder key, can be used for a variety of applications and, with a few tweaks to the firmware, can find use in identification via NFC thanks to the full support provided by the sensor board and its pairing with a Personal Computer.

Related products

• RFID NFC 13.56 MHz Read-Write Module
• LCD keypad shield for Arduino
• NFC RFID reader with two transponders

The post NFC/RFID Lock with LCD appeared first on Open Electronics.

Nuvoton Technology introduces the NSP2340BA24E Smart Buzzer, integrating voice capabilities and buzzer driving functions into a single IC. Designed to extend the capabilities of conventional piezo buzzers beyond simple beep sounds, the NSP2340BA24E enables direct playback of voice and sound effects, bringing more intuitive and distinctive audio interaction to home appliances, security systems, healthcare devices, industrial equipment, and other smart applications.

Conventional buzzers have long been widely used in electronic products for audible alerts and operation feedback due to their simple architecture and proven reliability. However, as smart devices become increasingly sophisticated, simple beep patterns alone may not provide the intuitive and informative user experience required by modern applications.

Built around the concept of “Beyond the Beep,” the NSP2340BA24E expands the role of the conventional buzzer by enabling richer and more expressive audio feedback.

From Simple Beeps to Voice & Melody

The NSP2340BA24E Smart Buzzer integrates embedded Flash and a buzzer driver, together with a voltage booster and Class-AB amplifier, enabling direct drive of a piezo buzzer for voice and sound-effect playback. This transforms the buzzer from a simple audible alert component into a more informative audio interface.

With voice and diverse audio content, products can communicate operating status, notifications, and warning messages more clearly. Instead of relying solely on different beep patterns to indicate different conditions, the NSP2340BA24E enables more recognizable voice or sound feedback, helping users understand device status more intuitively. This approach allows developers to build upon familiar piezo buzzer designs while creating greater product differentiation and a more engaging audio experience.

Highly Integrated Design for Easier Implementation

The NSP2340BA24E integrates audio content storage, voltage boosting, and buzzer driving capabilities into a highly integrated solution. The NSP2340BA24E supports booster output of up to 24V, along with UART, I²C, and Two-Wire interfaces for host MCU control. It also supports In-System Programming (ISP), allowing audio content to be updated through the host MCU.

With this integrated architecture, developers can more easily introduce Voice & Melody capabilities into products traditionally designed around buzzers, while maintaining flexibility to customize audio content for different products and application requirements.

Expanding the Value of Buzzers Across Smart Applications

The NSP2340BA24E can be applied across a broad range of products requiring audible feedback and status notification. From operation and completion notifications in home appliances to warning alerts in security systems and status feedback in industrial equipment, the NSP2340BA24E allows sound to do more than simply attract attention—it can help users better understand what a device is communicating.

With the NSP2340BA24E Smart Buzzer , Nuvoton extends the conventional piezo buzzer beyond simple beep sounds to richer Voice & Melody experiences, providing developers with greater flexibility in audio design and enabling more intuitive audio interaction for the next generation of smart devices.

The post Nuvoton Introduces NSP2340BA24E Smart Buzzer, Redefining the Buzzer Sound Experience appeared first on ELE Times.

Polar Semiconductor LLC of Bloomington, MN, USA (the only US-owned foundry specializing in high-voltage, power and sensor semiconductors) and IC-Link by imec (the design and manufacturing division of nanoelectronics research center imec of Leuven, Belgium) are collaborating to provide 8-inch production of enhancement-mode (e-mode) gallium nitride (GaN) devices to serve critical markets such as AI data centers, automotive, aerospace & defense, and the industrial grid...

Infineon Technologies AG introduces the XDP8HD40S-1, a high-voltage hot-swap controller designed for digital power path protection and monitoring in next-generation AI server power architectures operating at ±400 Volt and 800 Volt direct current (VDC). As AI clusters scale from 48 V toward higher rack power levels, reliable hot-swap functionality becomes increasingly important for maintaining uninterrupted system operation. The XDP8HD40S-1 enables power modules, converters, GPUs, and server subsystems to be connected and disconnected safely while preserving system integrity, extending Infineon’s power semiconductor portfolio, spanning silicon, silicon carbide (SiC), and gallium nitride (GaN), further into the protection and monitoring layer required for scalable AI infrastructure.

“Future AI data centres require power delivery systems that combine high efficiency, maximum reliability, and comprehensive protection capabilities,” said Magdalene Boebel, Senior Vice President and Business Line Head of Power System ICs at Infineon. “The XDP8HD40S-1 enables system designers to implement reliable hot-swap solutions for ±400 V and 800 V power architectures while providing the monitoring and protection features needed to maximize server uptime and operational efficiency.”

The XDP8HD40S-1 is designed for a range of high-voltage applications, including two-wire 800 V or ±400 V intermediate bus converters and GPUs, 1.500 V intermediate bus converter systems, high-voltage rack and server power delivery, battery backup systems, peak shaving, and 400 V to 800 V single- or dual-side hot-swap implementations. The device is compatible with Infineon’s power semiconductor portfolio, including OptiMOS MOSFETs and CoolSiC JFETs, allowing designers to build efficient, rugged protection stages using the same underlying technologies Infineon has already applied in its 800 VDC AI data center reference designs.

Operating at higher system voltages increases the complexity of controlling inrush current and protecting infrastructure from transient events. The XDP8HD40S-1 integrates digital Safe Operating Area (SOA) control with programmable and preconfigured active protections. Together with a variable pulse SOA control mode (Boost Mode), the device supports optimized startup behavior while maintaining safe operation of the power switch. An integrated gate driver supports external SiC cascode implementations based on a MOSFET and JFET combination, enabling efficient control of high voltage power stages. To further enhance system robustness, the controller incorporates surge immunity protection and supports fast power-switch shutdown with a configurable 1.5 A pull-down current, helping protect AI compute infrastructure during abnormal operating conditions.

The XDP8HD40S-1 supports a broad operating voltage range, with VDDB from 4.5 V to 24 V and VDDA from 4.5 V to 13.2 V, allowing integration into a variety of server and rack-level power systems. For system management and remote diagnostics, the controller includes a PMBus 1.5 interface with enhanced security features for integration into data centre management infrastructure. A built-in black-box recording feature captures critical event information to help accelerate fault analysis and system debugging. Additional protection features include programmable input and output overvoltage and undervoltage protection, external temperature sensor support, and overtemperature protection.

Modern AI server platforms increasingly require real-time visibility into power consumption and system health. The XDP8HD40S-1 addresses this through 12-bit current and voltage analog-to-digital converters, providing measurement accuracies of approximately 1 percent for voltage, 1 percent for current, and 3 percent for power, with analog power monitoring reporting accuracy of 1.5 percent and integrated energy metering for continuous system monitoring. These capabilities support system optimization, predictive maintenance, and power management strategies in high-density AI computing platforms, complementing the reference designs Infineon has already demonstrated for 800 V-to-48 V and direct-conversion architectures now emerging as AI data center rack power continues to rise.

The post Infineon Introduces XDP8HD40S-1 High-Voltage Hot-Swap Controller, Extending its Power Semiconductor Portfolio From Grid to Core for 800 VDC AI Server Architectures appeared first on ELE Times.

HARTING Technology Group, a leading global provider of industrial connectivity, today announced it has joined the NVIDIA MGX ecosystem as a power system component provider for the NVIDIA Vera Rubin NVL72 platform.

HARTING delivers power whip solutions – cable assemblies that distribute power from the building to each rack – as growing AI compute demands reshape how power is distributed within data centres. The solutions span the transition across two generations of NVIDIA MGX power architecture, from 480 VAC to the NVIDIA 800 VDC architecture, designed to support the rapidly increasing power demands of AI factories.

As AI workloads grow and compute density increases, data centres must manage significantly more power within increasingly dense environments without compromising reliability, efficiency or scalability. That shift is placing new demands on the connectivity systems that deliver power to AI compute infrastructure.

“AI is fundamentally changing data centre infrastructure, and HARTING has the engineering expertise to help enable that transformation,” said Philip Harting, Chairman of the Board and CEO, HARTING Technology Group. “Our inclusion in the NVIDIA MGX ecosystem brings our decades of connectivity experience in high power environments, from rolling stock to automotive, to the infrastructure supporting the next generation of AI.” For the NVIDIA MGX platform, HARTING provides a 100A/480VAC power whip for the 3RU 110kW power shelf for NVIDIA Vera Rubin NVL72, supporting the transition to 800 VDC with a next-generation 157A/800 VDC DC-DC power whip connecting the power infrastructure to the compute rack.

“As AI compute becomes more powerful and rack densities increase, the industry has to rethink power distribution from the ground up,” said Christian Gysin, Chief Technology Officer and Member of the Executive Board, HARTING Technology Group. “The transition from 480VAC toward 800 VDC is a significant step in that evolution. Connectivity must support higher power levels while delivering the reliability, safety and scalability these environments demand. That is precisely where HARTING’s engineering expertise comes into play.”

HARTING solutions transmit power, data and signal across mission-critical systems worldwide. The company is drawing on decades of experience in demanding industrial environments and its global engineering and vertically integrated manufacturing capabilities to address the evolving connectivity requirements of AI infrastructure and data centres.

As part of the NVIDIA MGX ecosystem, HARTING will be featured on the NVIDIA AI Factory MGX Ecosystem wall at the OCP Global Summit 2026. The executives from HARTING will honourably attend the NVIDIA MGX ceremony. Besides, two HARTING power whip solutions supporting the NVIDIA Vera Rubin NVL72 platform will also be on display in the HARTING booth (Booth No. C79) demonstrating the power connectivity behind current and next-generation AI infrastructure.

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As AI workloads drive demand for more scalable and flexible data centre architectures, organizations are looking for faster, more efficient ways to move, store and protect data. Microchip Technology is helping to address these needs by expanding its portfolio of data centre solutions with new innovations in PCIe connectivity, NVMe storage and acceleration that support high-performance computing infrastructure.

“Customers are looking for technology partners that can address multiple challenges across the infrastructure stack while helping simplify design and accelerate deployment,” said Brian McCarson, Corporate Vice President and GM of Microchip’s data centre solutions business unit. “By continuing to expand our portfolio, we’re providing the building blocks needed to create more efficient, secure and adaptable platforms for today’s increasingly distributed and data intensive computing environments.”

Designed to bring PCIe Gen 6 connectivity to space- and power-constrained platforms, the Switchtec PCIe 6.0 Low Lane-Count (LLC) switch provides up to 64 PCIe Gen 6 lanes, 32 ports and flexible x2, x4, x8 and x16 bifurcation options. Integrated Direct Memory Access (DMA) supports efficient peer-to-peer data movement between connected devices while reducing host CPU involvement. Like Microchip’s larger Switchtec Gen 6 devices, the LLC switch features PCIe Multicast and partitioning capabilities along with robust security through hardware root of trust and secure boot technologies. The new device delivers PCIe Gen 6 capabilities with a smaller, lower power footprint to extend support to a broader range of data centre and intelligent edge applications.

To address the industry’s requirements for secure, scalable and AI-optimized storage infrastructure, Microchip is updating its Flashtec SSD controller portfolio with an enhanced version of the PCIe Gen 5 NVMe 5016 controller. Building on the controller’s high-performance, power-optimized architecture, the updated device adds support for Commercial National Security Algorithm Suite (CNSA) 2.0 to help customers prepare for emerging post-quantum security requirements. Dual-port capability enables highly available storage architectures through redundant data paths and load balancing, while advanced virtualization, Quality of Service (QoS) management and flexible programmability help optimize performance. Together, these enhancements extend the Flashtec platform’s ability to address evolving NAND technologies, high-capacity SSD designs and next-generation enterprise, hyperscale and AI deployments.

Microchip is also expanding the capabilities of its Adaptec SmartRAID 4300 family of NVMe RAID storage accelerators with a series of enhancements designed to address practical operational needs. The updates are focused on strengthening storage security, minimizing downtime, expanding data protection and simplifying deployment across a wider range of environments. Self-encrypting drives (SEDs) with both local and remote key management, and RAID 6 and RAID 60 options have been added for increased resiliency and security. Broader platform compatibility is enabled through support for Linux, Debian, Ubuntu and Microsoft Windows 11 environments. Additional updates such as dynamic NVMe configuration for in-service management, persistent event logging and peer-to-peer rebuild support for greater CPU offload help reduce management overhead while minimizing service disruption. StorageCore API support further expands integration flexibility, enabling customers to incorporate SmartRAID management into third-party tools through in-band host applications as well as customized out-of-band BMC management frameworks.

The latest additions reflect the company’s ongoing commitment to advancing the performance, availability and security of next-generation computing platforms. Visit the website to learn more about Microchip’s full portfolio of data centre solutions.

Development Tools

Microchip’s data centre portfolio is supported by a suite of development and management tools, including ChipLink software for configuration, diagnostics, telemetry and debug of PCIe switches. Additional support includes software for device monitoring, configuration and firmware management, Flashtec NVMe controller development resources and Adaptec storage management software.

The post Microchip Expands Data Centre Portfolio to Meet Evolving AI Infrastructure Demands appeared first on ELE Times.

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The JetKVM Mini delivers KVM over IP for 39 dollars. The board captures a computer’s video, encodes it in H.264 and sends it to the host over WebRTC. It also drives keyboard and mouse as if they were physically connected. Compared with the original JetKVM, which relied on Linux running on a Rockchip RV1106G3 SoC, the Mini uses an ESP32-P4X for video capture, H.264 encoding, USB and the rest of its functions. The project therefore moves to RISC-V and to a FreeRTOS firmware based on ESP-IDF.

The Mini variant has a 100 Mbps RJ45 Ethernet port. The Mini W adds dual-band WiFi 6, Bluetooth and 802.15.4 for Zigbee and Thread thanks to an ESP32-C5 module. Pricing is 39 dollars for a single unit and 33 dollars per unit in a three-pack bundle. The Mini W costs 42 dollars, or 36 dollars per unit in the three-pack bundle.

ESP32-P4X: dual-core 400 MHz RISC-V CPU and 32 MB of PSRAM

The heart of the Mini is Espressif Systems’ ESP32-P4X. Inside there is a 32-bit dual-core RISC-V HP CPU running at up to 400 MHz, with an AI instruction extension and single-precision FPU, plus a RISC-V LP MCU core at up to 40 MHz. Memory includes 768 KB of HP L2MEM, 32 KB of LP SRAM, 8 KB of TCM, 32 MB of PSRAM, 128 KB of HP ROM and 16 KB of LP ROM. For storage there is 16 MB of flash and a microSD card slot, used for virtual media.

The VPU supports the H.264 and JPEG codecs, with a Pixel Processing Accelerator and a 2D DMA controller. The GPU is a 2D Pixel Processing Accelerator. The display is a 240 x 240 pixel non-touch IPS panel. The HDMI input goes up to 720p60 or 1080p30, with 4K supported through JetKVM OS Services. The H.264-encoded stream is sent to the host over WebRTC.

USB ports, 5V/500mA power and 42 x 42 x 23 mm dimensions

On the connectivity side, the Mini offers two USB 2.0 Type-C ports. The main one runs at 480 Mbps, the second at 12 Mbps. Power is 5V/500mA through a USB Type-C port. Dimensions are 42 x 42 x 23 mm, so the device fits in a fist. Those who want to rework the firmware development side will find in the catalogue the development board with Wi-Fi, Bluetooth and USB Type-C connector, useful for getting familiar with the ESP32 ecosystem before getting hands-on with the KVM.

• 32-bit dual-core RISC-V HP CPU up to 400 MHz with AI extension and FPU
• RISC-V LP MCU core up to 40 MHz
• 768 KB of HP L2MEM, 32 KB of LP SRAM, 8 KB of TCM
• 32 MB of PSRAM, 128 KB of HP ROM, 16 KB of LP ROM
• 16 MB of flash and microSD slot for virtual media
• 240 x 240 pixel non-touch IPS display
• 100 Mbps Ethernet over RJ45 in the Mini variant
• Dual-band WiFi 6, Bluetooth and 802.15.4 in the Mini W via ESP32-C5

The software runs on FreeRTOS with the ESP-IDF framework. Capture and encoding go through JetKVM OS services, while transport to the browser relies on WebRTC. Those who want to follow development and read the code will find the project’s code repository, where the firmware is published and updated. Open source firmware was planned from the start, so the Mini also suits anyone who wants to modify the capture logic or add features.

What a KVM over IP like the JetKVM Mini is for

A KVM over IP is useful when the computer to be controlled is far away or has no operating system running. The Mini gets into the BIOS, the boot screen or the bootloader, because it works at the level of the video signal and keyboard and mouse emulation. That is why it is used for rack servers, for mini PCs without a monitor and for test machines in the lab. The 100 Mbps Ethernet port is enough for a 1080p30 stream, while the W variant frees you from the network cable.

The 240 x 240 pixel IPS display shows status information directly on the device, without opening the browser. The microSD slot also lets you mount ISO images as virtual media, so an operating system can be installed remotely. Finally, the second USB 2.0 Type-C port at 12 Mbps handles the emulation peripherals. Those who want a starting point for their own IoT experiments will find in the catalogue the development kit for IoT projects with WiFi 6 and integrated peripherals, a way to get practice with the radios in the Espressif family.

Source: https://github.com/jetkvm

Related products

• ESP32 – Development board with Wi-Fi, Bluetooth and USB Type-C connector
• ESP32-C6-Zero Wi-Fi 6 IoT Development Kit

The post JetKVM Mini: $39 KVM over IP Built on ESP32-P4X appeared first on Open Electronics.

At the Open Compute Project (OCP) Global Summit, Texas Instruments (TI) debuted the first analog-to-digital converter (ADC) to enable 24/7, low-power, event-based remote monitoring at nanosecond resolution.

As AI workloads rapidly increase, data centres operators face significant challenges around power instability, inadequate real-time monitoring and signal degradation, all of which can lead to costly downtime. TI is addressing these challenges through its new ADC device and other analog solutions designed to tackle the challenges of scaling artificial intelligence (AI) infrastructures. Demonstrations on display in TI’s booth, No. E45, at OCP include:

• Real-time nanosecond-level telemetry: TI’s ADC34DSO75 is the industry’s highest performance 3 gigasamples per second (GSPS) ADC, enabling 24/7, low-power, event-based remote monitoring at nanosecond resolution – thousands of times faster than what current solutions offer. Existing monitoring solutions often fail to detect the nanosecond-level power-rail glitches that cause costly, unplanned downtime in data centres. By combining ultra-high speed sampling with advanced on-chip digital signal processing in a small form factor, the ADC34DSO75 detects and captures transient fault events in real time.

As the industry’s first solution to offer fully remote, event-based telemetry, the device eliminates the need for on-site debugging and oscilloscopes. By providing continuous, high-resolution monitoring of low-voltage, high-current power rails, the ADC34DSO75 helps data centres minimize downtime – which can cost operators hundreds of thousands of dollars an hour – while optimizing grid power efficiency. This compact, efficient solution offers hyperscalers unmatched remote diagnostic capabilities at a fraction of the size and cost of conventional monitoring methods.

• Reliable high-voltage power delivery: The LMI800PS is the industry’s first 800V isolated hot-swap controller, replacing a complex discrete solution requiring five integrated circuits with a single high-density package that delivers in-rush current and power path protection. The integration of an isolated bias supply and PMBus telemetry reduces board area by more than 60% and simplifies high-voltage designs. The LMI800PS enables safe power insertion and fast fault isolation, meeting safety standards with 5kVrms reinforced isolation and more than 8mm creepage. This prevents a single load failure from disrupting the shared power bus and maximizes data centres stability. Supporting both ±400V and 800V distributions, the device provides a scalable solution for diverse rack architectures, accelerating the deployment of high-efficiency power systems required for next-generation AI infrastructures.
• Ultra-low jitter signal integrity: The LMK6B is a bulk acoustic wave (BAW)-based oscillator that delivers best-in-class jitter performance and power-supply rejection ratio (PSRR). As data center transmission rates approach 3.2Tbps, the margin for timing error shrinks significantly, and even minute jitter can increase bit error rates and cause system instability. The LMK6B provides industry-leading jitter performance of 9.6fs at 625MHz, ensuring reliable performance and preserving signal integrity for next-generation, AI-driven networking infrastructures.

“As AI workloads drive massive scale, the need for real-time visibility and architectural stability has never been greater,” said Karthik Vasanth, Vice President and General Manager for TI’s Data, Converters and Clocks business unit. “By delivering industry-leading solutions for high-speed telemetry, advanced power protection and precision timing, TI is enabling hyperscalers and operators to design the next generation of AI data centres with optimized performance and minimal downtime.”

The post TI Unveils New ADC to Enable Nanosecond-Level Telemetry, Minimise Downtime in AI Data Centres appeared first on ELE Times.

AI-assisted chip engineering is increasingly capable of reaching meaningful design milestones. But reaching GDS does not establish that the resulting engineering outcome is better. If AI agents are going to participate more deeply in semiconductor design, the next question must move beyond capability: Did the AI beat an engineering benchmark that engineers already trust?

And if it appears to have done so, can the engineering data prove the improvement rather than relying on one successful run or thousands of tool logs? That is the natural next step in the trust discussion.

The problem is no longer only whether AI can make engineering decisions. It’s whether those decisions can be evaluated using the same discipline engineers already use to evaluate designs. A useful framework is:

Target workload → Workload/Memory model → Engineering benchmark → DOE → RSM/Regression → Predict → Verify with EDA → Measure error → Compare → Repeat

Two ideas are central. First, the benchmark must represent the workload the silicon is actually intended to serve. Second, the AI-generated design history must be converted into measurable engineering evidence.

Benchmark must start with the workload

For an AI accelerator, frequency, power, area, and timing are not really the beginning of the problem. They are consequences of the workload. Relevant assumptions may include model type, context length, concurrency, compute intensity, memory footprint, HBM capacity, memory bandwidth, interconnect traffic, and communication behavior.

A long-context inference workload may create very different memory requirements from a short-context workload. A compute-bound workload may favor one architecture. A memory-bound workload may favor another.

So, before asking whether AI beat a benchmark, engineers first need to ask: Was the benchmark derived from the workload the chip is actually expected to serve? Because a statistically excellent optimization against the wrong workload is still the wrong design.

The chain therefore begins with:

Workload → Compute and memory behavior → Hardware requirements → Engineering benchmark

Only after that do conventional design metrics become meaningful.

Define a benchmark engineers already trust

The reference implementation could come from an existing production design, a previous tapeout, an experienced engineering team, a conventional EDA flow, or another controlled implementation. The important point is comparability.

The AI-generated design and the reference should be evaluated against equivalent conditions:

• Workload
• Process technology
• PDK and libraries
• Frequency target
• Timing requirements
• Power budget
• Area constraint
• Operating corners
• Physical-design constraints
• Memory requirements
• Sign-off requirements

Against the same workload and engineering problem, what did the AI actually improve? Then the comparison becomes meaningful.

Passing the requirement isn’t enough

A benchmark should include margin, not merely pass/fail. Suppose two implementations both reach 2.2 GHz. One closes timing with +5 ps of margin. The other closes with +45 ps. Both technically pass. But they are not equivalent engineering results.

The same principle applies to power, area, IR drop, EM, thermal behavior, routing, memory bandwidth, and corner margin. The useful question becomes: How far inside the acceptable engineering region did the AI place the design?

That is more informative than simply asking whether it crossed a threshold.

AI creates an engineering dataset

An AI-assisted design process may explore far more alternatives than a human team could practically investigate manually. Those iterations can contain combinations of:

• Frequency
• WNS/TNS
• Power
• Area
• Placement
• Congestion
• Routing
• IR drop
• EM
• Thermal behavior
• Memory behavior
• Physical violations

Those observations should not automatically be treated as disposable logs. They can become an engineering dataset. The question then becomes: Can the data describe the design space well enough to evaluate the AI result quantitatively?

DOE can structure the exploration

Design of experiments (DOE) provides one established way to organize the search space. Possible controllable variables might include floorplan parameters, placement density, clock constraints, cell sizing, buffering, voltage, routing strategy, power-grid parameters, memory configuration, or other design-specific controls. Measured responses could include timing, frequency, power, area, congestion, temperature, IR drop, EM, memory bandwidth, and physical violations.

Conceptually, engineering response = f (design variables)

For AI accelerators, workload parameters can also enter the problem: engineering response = f (design variables, workload variables). That allows the analysis to examine not only how the design responds to physical controls, but how sensitive it is to changing workload assumptions.

Turn data into a predictive model

Response surface methodology, regression, or other surrogate modeling approaches can then be used to describe relationships in the explored design space. The exact mathematical model is less important than the engineering principle: Do not treat thousands of AI-generated engineering states as unrelated observations. Build a quantitative model of the design space.

That model can expose useful relationships. Which variables dominate timing? Where does frequency improvement become expensive in power? When does area reduction create unacceptable congestion? How sensitive is memory demand to workload assumptions? Where does the feasible engineering region begin to disappear?

Now the AI-generated history becomes more than activity. It becomes interpretable engineering evidence.

The model must earn trust too

Regression does not automatically make a model trustworthy. Useful statistical measures may include R², adjusted R², predicted R², RMSE, residual behavior, and lack-of-fit. But for this application, there is an even more important test: How accurately does the model predict the next actual EDA result?

Suppose the model predicts: WNS = +25 ps and the actual EDA result is: WNS = +23 ps. That is useful predictive agreement. If the prediction is +25 ps and the actual result is −40 ps, the model has missed something important. Prediction error can therefore become part of the engineering evidence.

Across repeated runs, engineers can ask:

• Is the error small?
• Is it stable?
• Is it biased?
• Is it improving?
• Does it become worse in a particular design region?

That leads to one of the most important principles in the framework: The AI should not only show that the design improved. It should also show that its prediction of the design agrees with actual engineering results. Trust increases when prediction and engineering reality repeatedly agree.

Compare the distribution, not the best run

One good result is not enough. The AI-assisted process should be repeated under controlled conditions. For important engineering responses, evaluate:

• Mean
• Standard deviation
• Percentiles
• Confidence interval
• Range
• Outliers
• Success rate
• Margin relative to requirements

The question is: What does this method usually produce, and how tightly distributed are the outcomes? One exceptional tapeout is interesting. A repeatable distribution of strong outcomes is much more convincing.

That is especially important when the system contains stochastic optimization, multiple agents, changing starting points, or large search spaces.

Optimization quality lives in the trade-offs

A design can improve one metric while becoming worse elsewhere. Useful relationships may include:

• Frequency vs. power
• Frequency vs. area
• Timing margin vs. power
• Area vs. congestion
• Performance vs. thermal density
• Performance vs. memory bandwidth

The important question is not simply whether one number improved. It is: Did the AI discover a better engineering trade space for the target workload? That is a much stronger benchmark than asking which run produced the highest frequency or smallest area.

The benchmark must be able to move

AI hardware introduces another complication. The workload itself can evolve while the silicon is being designed. Model architecture can change. Context length can increase. Concurrency can grow. Memory behavior can shift. The balance between compute and communication can change.

An accelerator optimized perfectly against one workload assumption may reach tapeout only to discover that the target has moved. So another useful question is: How sensitive is the AI-generated design to plausible changes in workload assumptions?

So, the objective is not to design one chip for every possible future workload. It is to understand whether the useful engineering region is broad or narrow.

A trustworthy method must be able to say “No”

A good evaluation framework should not exist only to prove that AI works. It must also be capable of proving that it did not. Perhaps frequency improves but power and area deteriorate enough that the conventional benchmark remains better.

Perhaps the average result improves but variability becomes unacceptable. Perhaps the model fits historical observations but predicts new EDA results poorly. Perhaps one impressive result hides a low overall success rate. Perhaps the AI optimizes the silicon well against a workload assumption that is no longer representative.

A trustworthy methodology must therefore be capable of concluding that, for this workload and engineering problem, the AI-assisted approach did not beat the benchmark. That is part of engineering trust.

Trusted EDA can remain the arbiter

None of this requires AI to replace established sign-off tools. A practical model is:

AI-assisted exploration and optimization → Trusted conventional analysis and sign-off

AI may perform more of the search, optimization, debug, and closure work. Established EDA can remain the independent engineering reference. The immediate test is therefore not whether AI becomes the sign-off authority. It is: Can AI repeatedly produce designs that survive trusted sign-off?

That makes adoption much more practical.

Manufacturing alignment is the final check

Even after the AI beats the design benchmark, one additional question remains. Before hardware exists, actual manufacturing yield and reliability are still unknown. But the tapeout already contains indicators of how demanding the physical realization may become:

• Routing density
• Local current density
• Thermal concentration
• Physical margin
• Variation sensitivity
• Die area
• I/O requirements
• Package requirements
• Test complexity

So engineers should ask: Did the AI achieve the improvement in a way that remains reasonably aligned with the intended manufacturing target? This does not claim to predict actual manufacturing yield. It asks whether the AI won the design benchmark by creating a much harder downstream physical problem.

From AI capability to engineering evidence

The complete framework is:

Target workload → Workload/Memory model → Engineering benchmark → DOE → RSM/Regression → Predict → Verify with EDA → Measure error → Compare → Repeat

The result is not an AI score. It is engineering evidence. Target workload defines what the silicon must execute. Workload/Memory model translates that workload into compute, bandwidth, capacity, and communication requirements.

Engineering benchmark establishes the trusted reference and required margins. DOE structures the exploration. RSM/Regression models the engineering response space. Predict estimates the outcome of the next move.

Verify with EDA tests that prediction against engineering reality. Measure error quantifies predictive accuracy. Compare evaluates improvement, margins, and trade-offs against the benchmark. Repeat establishes whether the result is reproducible.

The question for the industry

AI-assisted semiconductor engineering is increasingly demonstrating that AI can perform meaningful chip-design work. The next challenge is harder. It must prove that the engineering result is actually better.

That requires the correct workload, a benchmark engineers trust, quantitative modeling, predictions tested against real EDA results, and measured prediction error, repeated experiments, trade-off analysis, and trusted sign-off.

The question therefore becomes: Can AI beat a benchmark engineers already trust for the workload the silicon is intended to serve—and can the engineering data prove that it did? That is a much higher standard than an impressive demonstration.

But semiconductor engineering already knows how to work this way. Perhaps the path to trusting AI is not to abandon established engineering discipline. It is to apply that discipline directly to AI-generated design.

• Define the workload
• Define the benchmark
• Model the response
• Predict
• Verify
• Measure the error
• Compare
• Repeat

Then ask the question that matters: Did the AI actually beat the benchmark—and can the engineering data prove it?

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

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• Applied Materials Bets $5B on a New Model for Chip Innovation
• How AI is reshaping IC signoff: Trust, speed, and intelligent workflows
• The Magic of Agentic AI Will Come From a Holistic Approach to Chip Design

The post AI silicon tapeout: Can it beat a benchmark engineers trust? appeared first on EDN.

They look like simple, passive lumps of material molded onto a cable or dropped onto a PCB but looks can be highly deceiving. To the uninitiated, a ferrite bead is just a mysterious black cylinder taking up space on a wire. But underneath that boring exterior lies an engineer’s secret weapon for turning pesky high-frequency noise into harmless heat.

To understand a ferrite bead, you have to look past the standard inductor symbol often used for it on a schematic. At low frequencies, a ferrite bead does behave like a garden-variety inductor, offering low DCR (DC resistance) and letting your desired signals pass right through.

But as the frequency climbs into the megahertz range, the magic happens. The bead’s inductive reactance (XL) takes a backseat to its resistive component (R). Instead of reflecting high-frequency noise back into your circuit like a pure inductor would—which can cause unwanted resonance and ringing—the ferrite bead acts like a frequency-dependent sponge, trapping that electromagnetic interference (EMI) and dissipating it as a tiny amount of thermal energy.

To see why this shift happens, it helps to look at the bead’s equivalent circuit.

The core physics: How they actually work

To understand ferrite beads, it helps to look at how they are modeled in a circuit. A bead isn’t just a simple inductor (L). Instead, it is best modeled as an inductor (L) and a lossy resistor (R) in series, both in parallel with a parasitic capacitor (Cp). This combination explains why their behavior transforms so dramatically as frequency changes.

At low frequencies, the inductive element dominates. The bead behaves like a small coil, storing energy in its magnetic field and reflecting disturbances back toward the source. In this regime, signals pass through almost unaffected, while the bead quietly resists sudden changes.

As the frequency rises, however, the bead’s resistive component takes over. Instead of bouncing noise back into the circuit, the bead begins to absorb it. High‑frequency EMI is converted into tiny amounts of heat inside the ferrite material. This lossy behavior is what makes beads so effective at cleaning up noisy power rails and suppressing RF interference.

The parasitic capacitor adds another wrinkle: at very high frequencies, it can provide a bypass path, limiting the bead’s effectiveness. That’s why datasheets often show impedance curves that peak and then roll off.

Mathematically, the bead’s impedance is expressed as Z = R + jX, where X is the reactance (from inductance or capacitance). At low frequencies, X dominates. At high frequencies, R becomes the star of the show, ensuring that unwanted signals aren’t reflected but instead dissipated.

This dual nature—reactive at low frequencies, resistive at high—makes ferrite beads uniquely suited to tame the invisible chaos of EMI.

Figure 1 A mixed-signal IC filtering scheme attenuates digital supply noise from sensitive analog power domains. Source: Analog Devices Inc.

Note at this point that ferrite beads come in several distinct forms tailored to different circuit needs: multilayer chip beads use internal printed traces for compact surface-mount filtering; wirewound beads coil insulate copper wire around a core to handle higher DC currents with minimal power loss; leaded through-hole beads offer sturdy mounting for traditional power electronics; and snap-on cable cores (chokes) clamp around external cables to stop them from acting as RF antennas. Regardless of their physical design, all these types share the same core function—absorbing high-frequency EMI and dissipating it harmlessly as heat.

Strip away the form factors—whether it’s a tiny chip bead soldered to a modern PCB, a leaded through-hole bead in a power circuit, or a snap-on choke on a laptop cord, all ferrite beads do the same job. They act as “high-frequency sponges” that absorb unwanted EMI and turn it into heat. On circuit boards, chip beads clean up power lines right at the source, while on external cables, ferrite cores keep long wires from becoming broadcast antennas that violate regulatory limits.

Ferrite bead vs. standard inductor

While inductors and ferrite beads may look alike, their roles in a circuit are fundamentally different. A standard inductor is designed to store energy in its magnetic field, with a high Q factor that minimizes losses and allows it to resonate cleanly with capacitors. Its purpose is precision—shaping signals and conserving energy.

A ferrite bead, on the other hand, is intentionally engineered to be lossy. Its resistive element rises sharply at targeted high frequencies, ensuring that instead of ringing with noise, it absorbs and dissipates it as heat. In effect, inductors are tools for energy conservation and resonance, while ferrite beads are noise suppressors, sacrificing efficiency at high frequencies to protect circuits from EMI.

This purposeful lossy behavior is why beads are so common on USB cables, power rails, and RF lines, where stability and quiet operation matter more than resonance.

The trap: Current saturation and DC bias

Here’s where ferrite beads reveal a hidden weakness that many beginners overlook: DC current ruins their effectiveness. The culprit is magnetic saturation. As a steady DC current flows through the bead, the ferrite core material begins to saturate. In this state, the core can no longer respond linearly to changes in magnetic flux, and its effective permeability drops sharply.

The consequence is dramatic. Impedance, which is the bead’s measure of resistance to unwanted high‑frequency signals, collapses. A bead that proudly advertises 600 Ω of impedance at a given frequency might deliver only 50 Ω if you push it near its maximum rated DC current. Instead of choking off noise, it becomes nearly transparent, letting interference slip through unchecked.

Figure 2 Key performance specifications—including impedance, rated current, and operating temperature—are shown from a leaded ferrite bead datasheet. Source: Author

This is why datasheets specify a maximum DC bias current: it’s not just a thermal limit, but a functional one. Exceeding it means the bead stops being a noise filter and starts behaving like a weak wire. For engineers, the lesson is clear—always size ferrite beads with headroom for DC current. Otherwise, your carefully chosen EMI suppression component may silently fail, leaving your design vulnerable to the very noise it was meant to kill.

How to read a ferrite bead datasheet

A ferrite bead’s datasheet is more than a list of part numbers—it’s a roadmap to understanding how the bead will behave in your circuit. The most important plot is the impedance vs. frequency curve. At low frequencies, the curve is dominated by reactance (X), showing the bead’s inductive nature.

As frequency rises, the resistive component (R) overtakes X, and the curve peaks—this crossover frequency marks the point where the bead stops reflecting noise and starts absorbing it. That peak is the sweet spot for EMI suppression.

Figure 3 These impedance-frequency characteristics of a surface-mount ferrite bead are adapted from the manufacturer datasheet. Source: Micros

As you can see the plot displays X (reactance) dominating at lower frequencies (~10–30 MHz) and dropping near 100 MHz, while R (resistance) rises to equal/exceed X and dominates the total impedance Z around 100 MHz.

Another critical parameter is the DC resistance or DCR. While often overlooked, DCR tells you how much voltage drop the bead will introduce on a power rail. A bead with high impedance but excessive DCR can starve sensitive circuits of voltage.

The trick is to balance; choose a bead with a strong impedance peak at your noise frequency, but low enough DCR to keep your power rails stable. Reading datasheets this way ensures you’re not just picking a bead; you’re engineering a reliable noise filter.

Material matters: Curie temperature and resistivity

Ferrite beads are not only defined by their geometry but also by the ferrite material itself, and two parameters—Curie temperature and resistivity—play a decisive role in bead choice. The Curie temperature marks the point at which the ferrite loses its magnetic properties; MnZn ferrites typically sit around 200–300 °C, while NiZn variants can reach 350 °C or higher, meaning that operation near this limit causes permeability to collapse and impedance to vanish.

Resistivity differences further shape performance: MnZn ferrites, with relatively low resistivity in the 10–100 Ω·cm range, are well suited to suppressing lower-frequency noise below about 1 MHz but suffer eddy current losses at higher frequencies. Whereas NiZn ferrites, with resistivity in the 103–106 Ω·cm range, excel in the 10–100 MHz band and beyond, making them the preferred choice for RF and high‑speed digital suppression.

The design lesson is clear—match bead material to the noise spectrum and respect the Curie limit, because thermal stress or the wrong resistivity profile can silently erase EMI suppression.

Practical applications and best practices

Ferrite beads earn their keep in real-world designs by strategically blocking noise where it matters most. They are commonly placed in power supply filtering, forming part of LC rails to keep voltage lines clean. They also shine in decoupling pi-filters, where they help isolate noisy digital blocks from sensitive analog domains—such as keeping a microcontroller’s chatter away from an ADC’s quiet input stage.

But placement requires caution. A classic pitfall is dropping a ferrite bead directly next to a ceramic decoupling capacitor. Together, they can form an unintended LC tank circuit that resonates at certain frequencies. Instead of suppressing noise, this setup can actually amplify it, creating spikes that defeat the bead’s purpose.

The best practice is to space beads thoughtfully, use them in conjunction with resistive damping when necessary; to fix this, engineers often damp the circuit by adding a small series resistor or using a high-ESR electrolytic/tantalum capacitor in parallel with the ceramic capacitor. And always check impedance curves to ensure they’re working in your target frequency band. In short, ferrite beads are powerful tools, but only when applied with care.

Beads of truth: What textbooks miss

Ferrite beads may look like humble black cylinders or chips, but they embody a subtle engineering truth: they’re not inductors, they’re intentional noise killers. What they don’t teach you in school is that their effectiveness hinges on details often buried in datasheets—DC bias limits, impedance crossover points, and placement pitfalls that can turn a filter into a noise amplifier. Mastering ferrite beads means thinking beyond the schematic symbol and into the physics of saturation, loss, and frequency response.

So, the next time you spot that “mystery cylinder” on a USB cable or a bead on a power rail, remember it’s not there to store energy; it’s there to sacrifice it, converting interference into harmless heat. As an engineer, your job is to wield that sacrifice wisely. Read the curves, respect the ratings, and place beads with intent. Do that, and you’ll transform a quiet component into a powerful ally against EMI.

Now take a fresh look at your current designs. Pull up a ferrite bead datasheet, trace your power rails, and ask yourself: are your beads truly suppressing noise, or just sitting there as decoration? The answer could be the difference between a flaky prototype and a rock‑solid product.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Box Level EMI Suppression
• All about surface-mount ferrites
• Active noise control: Engineering silence in audio systems
• Power Tip 69: A Simple Oversight Can Ruin EMI Performance
• Key parameters to consider when selecting drum core power inductors

The post The secret life of ferrite bead: More than just a lump on a wire appeared first on EDN.

VolAnti is an open source acoustic drone detector: it listens to the sound of the propellers instead of the radio signal. That is why it also works against fibre-optic FPV drones, which emit nothing and stay invisible to any receiver. The project is by Agam Rossen and it only detects and alerts, with no jamming, interception or countermeasures.

The heart is an ESP32-S3. Four ICS-43434 MEMS microphones are arranged in a cross, 79 mm from corner to corner, and synchronised from a single source. The four streams are summed: at these frequencies 79 mm is a tenth of a wavelength, so sound from any direction adds up in phase while each capsule’s own noise does not. The gain is about 6 dB of signal-to-noise ratio for free, with a nearly omnidirectional response.

The spectrum is computed with a 2048-point FFT every 512 samples at 16 kHz, that is one window every 32 ms. The detector keeps a running picture of what the site normally sounds like at every frequency and subtracts it. Quiet things are learned in about 6 s, loud broadband bursts in less than a second.

The harmonic comb of the propellers and the six consecutive windows

A propeller with B blades at R revolutions per second generates a harmonic comb with evenly spaced peaks and silent valleys. For every candidate speed from 70 to 2000 Hz the firmware sums the energy on the teeth of the comb, subtracts that in the valleys, normalises and keeps the best score. On top of that the same speed has to win six consecutive windows within 2%: a single high-scoring frame means nothing, noise does not behave like that, a rotor does.

Four independent detectors work on the same spectrum and the alarm is whichever one is sure first. The measured latencies vary a lot from one to another:

• detector 1, fast comb: 0.23 s latency
• detector 2, slow comb: 1.4 to 4 s latency
• detector 3, envelope wash: 1 to 3 s latency
• detector 4, no-floor comb: 5 to 15 s latency

On 6 September 2026 tier 4 triggered the alarm at 104.2 m, 114 yards on the map. On 21 August, on open ground with variable wind, detection was at 14 m with loaded propellers and no false alarm all day. On 28 August, with the first production board, the detector output was identical to the reference on the golden vectors, with a worst frame of 29.4 ms against the 32 ms budget over 1,938 frames and no overrun.

Power, e-paper screen and an 18-byte LoRa packet

Power starts from a 1S 2500 mAh LiPo, charged by the BQ24074 and regulated to 3.3 V by the TPS63020 buck-boost. The claimed runtime is 18-22 h on a single charge. The case measures 91 mm and also houses an e-paper screen. The radio is a Ra-01H module: the LoRa alarm packet is 18 bytes, so a few dozen bytes are enough to let a second VolAnti know there is something in the air.

The frequency has to be set for the country of use: 868 MHz in the UK and the EU, 915 MHz in the United States. In still air and at a quiet site you can expect 100 to 200 m. At a windy or noisy site you can expect 15 to 50 m, and above 8 m/s detection is assumed to be degraded. So far there have been no false alarms in the field sessions.

Rebuilding it takes very little. The breadboard build costs about £35-45 and an evening, while the complete unit costs about £50-80 and a weekend. In Agam Rossen’s repository you will find the firmware, the live simulator, the breadboard guide, the complete unit guide, the flashing instructions, running multiple units, the audio test and the website source.

Assembly needs no exotic tools: soldering, a bit of patience and the willingness to tune the detector to your own site. A school or a farm can build and repair it themselves, without depending on a supplier. For anyone who wants to start from a development board, the ESP32-C6-Zero IoT kit is an option for practising with Wi-Fi 6 and built-in peripherals, while a round ESP32-S3 HMI display with a touch knob and LVGL graphics can serve as the control interface in a more ambitious version.

Source: https://github.com/agamrossen/VolAnti

The post VolAnti: the open source acoustic drone detector that listens to propellers appeared first on Open Electronics.

A seemingly newer device reverts to a legacy processor architecture, in comparison to one certified earlier that same year. Does it matter? And was it due to Matter?

This is the end
Beautiful friend
This is the end
My only friend, the end
The Doors, “The End”

In quoting those epic song lyric opening lines, I’m not referencing an ex-girlfriend, as Jim Morrison had reportedly done, but instead applying them to my long-running TP-Link smart plug teardown series. This entry, for the Tapo P110M, marks the end of the publication line (at least as currently planned) for this specific content cadence.

I hope you enjoyed reading about the various devices as much as I enjoyed taking them apart, photographing them, and writing about them.

The series, up to this point, began in February and encompasses the following analyses:

• TP-Link’s Kasa HS103: A smart plug with solid network connectivity
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again
• TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive
• TP-Link’s Tapo P105: A Kasa EP10 clone, or evolutionarily derived?
• TP-Link’s Tapo P125: A smart plug with an Apple HomeKit vibe
• TP-Link’s Tapo P115: Smart plug subtracts Apple, adds energy tracking

Reiterating a frequently uttered mission-statement mantra I most recently chanted last month, my basic aspiration with this project was to ascertain to what degree (if any) differences in the company’s various smart plug products’ feature sets, broadly between the Kasa and Tapo product lines as well as between products within a given line, were due to hardware variability versus (or in addition to) software-implemented inconsistency. Last month’s unveil was a particular hardware-evolution doozy, as it involved the processor architecture (and associated codebase) conversion from Arm (Realtek) to RISC-V (Espressif Systems).

So, what will we find inside the Tapo P110M? Usually, but not always, TP-Link’s Matter smart home and IoT protocol-supportive product variants include “M” as a product name suffix. More generally, in addition to Matter cognizance (or lack thereof), we’ve seen over this past year that the manufacturer also differentiates devices based on parameters such as energy monitoring and reporting capabilities and Apple HomeKit protocol support, not to mention cosmetic variances such as size, shape and weight, switch and activity LED locations, and the like.

The P110M, for example, implements all three aforementioned software enhancements, only one of which (energy tracking) last month’s Tapo P115 shares. Let’s see how, if at all, this differentiation is also reflected in hardware.

Feature set confusion

Here’s a stock shot of the Tapo P110M, to start.

 

Looks curiously familiar, albeit not identical, doesn’t it?

My two-pack came from Amazon’s Resale (formerly Warehouse) website area and set me back $13.77 after a 30%-off promotion active at the time, plus tax. While just now revisiting the product page both there and at TP-Link’s website, I was initially confused, since the latter (not to mention TP-Link’s broader product line overview page) explicitly notates support for Apple’s Home protocol, Siri interface and the like, all absent from the former. However, I suspect Matter cognizance is at the nexus of the discrepancy, as noted at Amazon product page verbiage:

Matter-certified devices, regardless of brand, can work together and are compatible with most major smart home platforms like Amazon Alexa, Apple HomeKit, Google Home, and Samsung SmartThings. Enjoy more flexible and unified control.

Translation, I’m guessing: the Tapo P110M doesn’t support Apple services directly, but instead implicitly via their common Matter-support intermediary.

Here’s the usual suite of outer box shots, complete with the also-as-usual 0.75″ (19.1 mm) diameter U.S. penny accompaniment for size comparison purposes. Top.

Front.

Left side.

Back.

Right side.

And bottom.

Peeling away an edge of the information-obscuring Amazon Resale sticker exposes to view the hardware revision number—v1.6—of what’s inside. And in a rarity, at least from my experience, that’s the only hardware version option listed on the product support page (albeit with multiple to-date associated firmware updates). A refreshing change of pace.

Sticker shock

Let’s now see what’s inside.

One of the two Matter stickers was previously removed from its original backing sheet. Wonder where it went? Hold that thought.

I’ve usually found with returned-and-resold stuff like this that only one of the multiple items in the package has been removed prior to re-placement and shipment back to Amazon. I generally select that same one as my teardown “victim”. But which one was it in this case?

Again, it’s usually the one on the left (or upper left corner for a quad-device box). But the prior owner of this set might have been left-handed; the indent for the device on the right is frayed.

Here’s more visual evidence of the prior owner’s out-of-box device selection preference. There’s the missing sticker, now adhering to the top of the smart plug on the right.

Putting the left-side device aside, let’s continue with the usual overview photo set. Top, again.

Front.

Left side.

Back.

Right….what?

Turns out the Matter QR code and info are already stamped on the device’s right side. Turns out, too, the owner stuck the supplemental sticker on the wrong device, because the info sets don’t match. Truthfully, I don’t think the sticker’s intended for the device at all (unnecessary info redundancy, don’cha know) but if so, it instead should have been stuck on top of the other device.

Maybe owner confusion is at the core of why it ended up getting returned? Dunno. Onward.

As usual, the bottom of the device contains useful info, including the FCC ID (2BCGWBP1100).

Quick aside: the FCC ID for last month’s Tapo P115 is quite similar (2BCGWP110). That’s not confusing at all, right? Its listed “final action date” is February 29, 2024 (a leap year, obviously) while this one’s “final action date” is July 24 of that same year. Therefore the “seemingly newer device…in comparison to one certified earlier that same year” prose in the subhead.

A screw loose

One more stock shot to go: the latest in a line of company-supplied interior concept images:

And that’s enough for the setup; let’s get inside. Practice makes perfect, apparently; this time not only was no bloodshed, but no tabs were snapped, either.

Voila.

Here’s the half you’re undoubtedly all most interested in.

Device-to-device design consistency takes the form, among other things, of the relay, yet another Churod A16-V-105DA2F.

The bottom and right-side views are equally reminiscent and unmemorable.

And, last but not least, what of the digital PCB on the left? I’ll start with the boring side (unless you’re into traces, test points, and/or embedded antenna silhouettes, that is).

That’s what’s known as a tease. Here’s the side you care about, especially after last month’s reveal that it had captured and encompassed a processor architecture shift.

No such momentous luck this time, alas. We’re back to Realtek’s RTL8720CM at left, previously found on several previous TP-Link smart plug designs, along with a Shanghai Belling BL0937 single-phase energy monitoring IC and Eon Silicon’s EN25Q32B 32 Mbit serial flash memory on the right (not found with the Tapo P115, since the NVM was single-package integrated alongside the processor in that case).

And of course there’s also yet another mysterious five-lead packaged device in the lower left corner (I’m still sticking with my guess that these are dual transistor devices), this time marked “TACeE1” . Plus, we can’t forget the switch alongside an LED smack dab in the center.

Why the seeming chronological advancement but architectural back-step from RISC-V is back to Arm this time? My guess is that it has everything to do with Matter. The specification is in the rapid-evolution early phase of its technology lifecycle, and with no offense intended to Espressif Systems, Realtek is the more mature of the two suppliers in this particular product category.

Sound off with your theories and/or broader thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Tapo or Kasa: Which TP-Link ecosystem best suits ya?
• TP-Link’s Tapo P115: Smart plug subtracts Apple, adds energy tracking
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again
• TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive

The post TP-Link’s Tapo P110M smart plug: Matter and energy monitoring matter appeared first on EDN.