Новини світу мікро- та наноелектроніки

The semiconductor industry is undergoing a major realignment to serve artificial intelligence (AI) and related environments like data centers and high-performance computing (HPC). That’s partly because AI chips mandate new design skills, tools, and methodologies.

As a result, IP suppliers, chip design service providers, and AI specialists are far more prominent in the AI-centric design value chain. Below are four design use cases that underscore the realignment in chip design models serving AI applications.

1. LG engages Tenstorrent

LG Electronics has partnered with Tenstorrent to enhance its design and development capabilities for AI chips tailored to its products and services. The Korean conglomerate aims to link its system design capabilities with AI-related software and algorithm technologies and thus enhance its AI-powered home appliances and smart home solutions.

Tenstorrent is known for its HPC semiconductors for specialized AI applications. The two companies will work together to navigate the rapidly evolving AI landscape to secure competitiveness in on-device AI technology. Meanwhile, LG has established a dedicated system-on-chip (SoC) R&D center focusing on system semiconductor design and development.

Figure 1 Tenstorrent CEO Jim Keller joined LG CEO William Cho at the LG Twin Towers in Yeouido, Seoul, to announce AI chip collaboration.

2. Arm-based AI chiplet

Egis Technology and Alcor Micro are leveraging Neoverse Compute Subsystems (CSS)—part of the Arm Total Design ecosystem—to develop new chiplet solutions targeting the HPC and generative AI applications. “As generative AI applications continue to proliferate, the demand for HPC is rising faster than ever,” said Steve Lo, chairman of Egis Group.

Figure 2 Neoverse Compute Subsystems (CSS) offer a speedier way to produce Arm-based chips by including more pre-validated components besides processor cores. Source: Arm

Egis will provide UCIe IP, an interconnect interface for chiplet architecture, while Alcor will contribute expertise for Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging services and chiplet design. Arm will offer its latest Neoverse CSS V3 platform to enable high-performance, low-latency, and highly scalable AI server solutions.

3. OpenAI’s in-house chip

Tech industry darling OpenAI is working with chip designer Broadcom and chip manufacturer TSMC to create a chip specifically for its AI systems. The Silicon Valley upstart, one of the largest buyers of AI chips, uses chips to train models for AI to learn data and carry out inference where AI applies the data to make decisions or predictions.

According to a Reuters story, OpenAI has been working with Broadcom for months to build its first AI chip focusing on inference. The AI powerhouse has assembled a team of about 20 chip designers, which includes designers who developed Google’s famed tensor processing units (TPUs); Thomas Norrie and Richard Ho are prominent names in this design team.

4. Sondrel wins HPC chip contract

Sondrel recently announced a multi-million design win for a high-performance computing (HPC) chip project. HPC is in a huge demand for AI, data center, and scientific modeling applications that require tremendous computing power. The Reading, U.K.-based chip design service provider has started front-end, RTL design and verification work on this HPC chip.

Figure 3 In HPC chips, it’s imperative that data flow is balanced and that processors are not stalled waiting for data. Source: Sondrel

As Sondrel’s CEO Ollie Jones puts it, HPC designs require large, ultra-complex custom chips on advanced nodes. These chips require advanced design methodologies to create billion-transistor designs at leading manufacturing process nodes.

HPC designs require multicore processors running at maximum clock frequencies while utilizing advanced memory and high-bandwidth I/O interfaces. Then there is network-on-chip (NoC) technology, which enables data to move between processors, memory and I/O while allowing the processors to reliably share and maintain data available in their caches.

The coming AI disruption

Every decade or so, a new technology transforms the semiconductor industry in profound ways. This time around, AI and relating technologies such as HPC and data centers are reshaping chip fabrics to cater to unprecedented data flows inside these semiconductor devices.

It’s a trend to watch because the AI revolution is just getting started.

Related Content

• Special report: HPC enables innovation
• The role of cache in AI processor design
• AI boom and the politics of HBM memory chips
• The Future of Medical Research: HPC, AI & HBM
• Enhancing the Efficiency of AI and HPC Data Centers

The post Four tie-ups uncover the emerging AI chip design models appeared first on EDN.

submitted by /u/BodyDisastrous5859
[link] [comments]

Aelum Inc of Goleta, CA, USA – which uses compound semiconductor materials on large-diameter substrates to develop technologies for mobile, automotive, AI, defense & aerospace, communication and quantum computing – has joined Optica, the global society dedicated to advancing optics and photonics worldwide. The corporate membership aligns Aeluma with a network of industry leaders in light science and technology...

submitted by /u/TheSerialHobbyist [link] [comments]

Having already examined the Colpitts oscillator, we now look at its first cousin, the Clapp oscillator.

Please consider the following illustration in Figure 1.

Figure 1 A Clapp oscillator where the passive components are arranged on the right-hand side for easier viewing. Source: John Dunn

There is an R-L-C network of passive components and an active gain block. This circuit differs from the Colpitts by now using a third capacitor (C3) in series with the inductance (L1) and by now needing a DC path: R2, to ground for the gain block. The output impedance of the gain block is zero and the value of its gain (A) is nominally unity or perhaps a little less than unity. The resistance R1 models the output impedance that a real-world gain block might present.

To analyze this circuit, we take the passive components, redraw them as on the right in Figure 1 and where G1 = 1 / R1, G2 = 1 / R2, and the term S = j / ( 2*π*F), we use node analysis to derive the transfer function E1 / Eo.

The analysis for the Clapp circuit is rather more involved than it was for the Colpitts circuit so for the sake of clarity, I have omitted it here. However, my handwritten notes of that analysis can be seen at the end of this essay. Try not to strain your eyes.

The end result is an expression of the transfer function in a useful form as follows in Figure 2.

Figure 2 Algebraic expression of transfer function for the Clapp oscillator shown in Figure 1. Source: John Dunn

Note that the denominator of this equation is fourth order. It is a fourth order polynomial because there are four independent reactive elements in the circuit, L1, C1, C2 and C3.

Please also note that the order of the polynomial MUST match the number of independent reactive elements in the circuit. If we had come up with an algebraic expression of some other order, we would know we’d made a mistake somewhere.

Graphing the ratio of E1/Eo versus frequency, we see the following in Figure 3.

Figure 3 E1/Eo versus frequency from algebraic analysis. Source: John Dunn

The transfer function of the passive R-L-C network has a pronounced peak at a frequency of 1.62 MHz and a null at a slightly lower frequency. When we run a spice simulation of that transfer function, we find very nearly the same result (Figure 4). I blame the differences on software numerical accuracy issues.

Figure 4 E1/Eo versus frequency from SPICE Analysis. Source: John Dunn

When we let our gain block be a voltage follower—a JFET source follower in the following example—we see oscillation at the frequency of that transfer function peak as shown in Figure 5.

Figure 5 Clapp Oscillator simulation after letting our gain block be a voltage follower. Source: John Dunn

The algebraic derivation of the Clapp oscillator transfer function is shown in handwriting in Figure 6.

Please forgive the handwriting. I just didn’t have the patience to turn this into a printout.

Figure 6 John Dunn’s transfer function derivation. Source: John Dunn

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• The Colpitts oscillator
• Emitter followers as Colpitts oscillators
• Simulation trouble: Bode plotting an oscillator
• Oscillator has voltage-controlled duty cycle

The post Clapp oscillator appeared first on EDN.

AlixLabs AB of Lund, Sweden — which was spun off from Lund University in 2019 and has developed the Atomic Layer Etching (ALE) Pitch Splitting technology (APS) — is participating at SEMICON Japan 2024 at Tokyo Big Sight (11–13 December), marking the public debut for its 300mm wafer process chamber. Its Made in Sweden APS (ALE Pitch Splitting) tools are aimed at allowing the semiconductor industry to scale down to sub-7nm manufacturing processes in a more sustainable way, and is positioned as an alternative to costly double patterning or EUV (extreme ultraviolet) solutions...

Automotive technology firm Valeo and ROHM Semiconductor are collaborating by using their combined expertise in power electronics management to optimize next-generation power modules for electric motor inverters. As a first step, ROHM will provide its 2-in-1 silicon carbide (SiC) molded module TRCDRIVE pack to Valeo for future powertrain solutions...

Sheffield University spin-off Phlux Technology —which designs and manufactures 1550nm avalanche photodiode (APD) infrared sensors — has won an Institute of Physics (IOP) Business Start-Up Award 2024. Presented at the Houses of Parliament in London, the award celebrates young companies leveraging physics for innovation and impact. It recognized Phlux’s Aura family of Noiseless indium gallium arsenide (InGaAs) infrared (IR) sensors, which is said to have set new standards for sensitivity and performance in optical systems such as LiDAR, laser range finders, and optical fiber communications test equipment...

As a genre, DACs are low power devices with power and current output capabilities limited to the milliwatt and milliampere range. There is, of course, no fundamental reason they can’t be teamed up with suitable power output stages, which is indeed common practical practice. Problem solved.

Wow the engineering world with your unique design: Design Ideas Submission Guide

But just for fun, this design idea takes a different path to power by merging a venerable (the “L” stands for “legacy!”) LM337 regulator into a simple (just two generic active chips) 8-bit PWM DAC to obtain a robust 1.5-A capability. It also enjoys the inherent overload and thermal protection features of that time-proven Bob Pease masterpiece.

As an extra added zero cost feature, output voltage accuracy is (mostly: ~90%) determined by the + 2% (guaranteed, typically much better) precision of the LM337 internal voltage reference, rather than relying on the sometimes-dodgy stability of a logic supply rail as basic PWM DACs often do.

Figure 1 shows the circuit.

Figure 1 LM337 joins forces with 4053 CMOS switch to make a macho PWM DAC.

 Metal gate CMOS SPDT switches U1a and U1b accept a 10-kHz PWM 5v signal to generate a +1.25 V to -8.75 V “ADJ” control signal for the U2 regulator. ADJ = +1.25 V causes U2 to output 0 V. It has always struck me somehow strange that a negative regulator like the 337 sometimes needs a positive control signal (in this case for Vout less negative than -1.25 V), but it does. ADJ = -8.75 V makes it make -10 V. 

U1c generates an inverse of the PWM signal, providing active ripple cancellation as described in “Cancel PWM DAC ripple with analog subtraction.”

Current source Q1 reduces zero offset error by nulling the ~65 µA (typical) ADJ pin bias current. The feedback loop established via R2 and R3 makes full-scale -10 V output proportional to U2’s internal reference as previously mentioned.

This does, however, make output voltage a nonlinear function of PWM duty factor with functionality (DF from 0 to 1): Vout = -1.25 DF / (1 – 0.875 DF) as graphed in Figure 2.

 Figure 2 Graph of Vout (0 V to -10 V) versus the PWM duty factor (0 to 1).
[Vout = -1.25 DF / (1 – 0.875 DF)]

 Figure 3 plots the inverse of Figure 2, yielding the PWM DF required for a given Vout.

 Figure 3 Graph of the PWM duty factor (0 to 1) versus Vout (0 V to -10 V).
[PWM DF = Vout / (0.875*Vout – 1.25)]

For the corresponding 8-bit PWM setting Dbyte = 256 DF = 256 Vout / (0.875*Vout – 1.25).

The negative supply rail (V-) can be anything between -13 V (to accommodate U2’s minimum headroom requirement) and -15 V (in recognition of U1’s maximum voltage rating). DAC accuracy will be unaffected. 

U2 should be adequately heatsunk as dictated by heat dissipation equal to output current multiplied by the V- to Vout differential. Up to double-digit Watts are possible. The 337s go into thermal shutdown at junction temperatures above 150oC, so make sure it will pass the wet-forefinger-sizzle “spit test!”

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Cancel PWM DAC ripple with analog subtraction
• Cancel PWM DAC ripple with analog subtraction—revisited
• Cancel PWM DAC ripple with analog subtraction but no inverter
• Cancel PWM DAC ripple and power supply noise
• Fast PWM DAC has no ripple
• Fast-settling synchronous-PWM-DAC filter has almost no ripple
• Minimizing passive PWM ripple filter output impedance: How low can you go?

The post 0 V to -10 V, 1.5 A LM337 PWM power DAC appeared first on EDN.

I wanted to share a reminder that you don’t need a dedicated workbench, shop, or even a large table to work on electronics projects. I don’t have the space or budget for a full setup, so I work at my desk while watching videos. However, constantly running back and forth to grab parts was frustrating and made setup and cleanup take forever. To solve this, I built a portable workbench that I can easily place on my desk or store on a shelf when not in use. Here’s what I did: I used glued wood planks cut to 40cm x 50cm. Made a small shelf for my soldering station by gluing wood scraps together, then secured it with screws. Added a hole at the back for the power supply, handles for easy carrying, and rubber feet to keep it stable on any surface. Screwed my soldering equipment onto the board so everything stays in place. Now, I can set up and start working in seconds, and so far, it’s been a game-changer! front view top view shelf view submitted by /u/Alfagun74 [link] [comments]

I came across a DIY power supply using a DPS5005 Switching Power Supply and decided to give it a go. I'm pretty happy with the housing as that's pretty much all this project is but I still like it. I did however skip the use of a USB C PD board and just use a random 48v supply. I also added more ferrets to the output to try and clean up the switched power. submitted by /u/iamnotatigwelder [link] [comments]

Infineon has announced FreeRTOS support for its 32-bit AURIX TC3x family of automotive and industrial microcontrollers. As a key software layer, the RTOS manages both hardware and software resources, ensuring reliable and timely task execution. Acting as a bridge between the hardware and application software, it simplifies development by abstracting hardware complexities. This approach enhances portability and code reusability, streamlining the development process and reducing time-to-market.

FreeRTOS is a widely used, open-source real-time operating system actively supported and developed by Amazon Web Services (AWS). AWS also offers middleware libraries for FreeRTOS, enabling seamless integration with its cloud services.

“The availability of FreeRTOS enables customers to rapidly build applications on a well-established and feature-rich open-source environment,” said Patrick Will, head of Software Product Management and Marketing for Automotive Microcontrollers at Infineon. “This integration facilitates quick feature evaluation on the AURIX TC3x and provides our customers with an accelerated migration path for non-AUTOSAR projects, particularly in the automotive and industrial markets.”

TriCore AURIX TC3x MCUs offer ASIL-D/SIL-3 compliance and advanced safety features, as well as scalable feature sets and pinouts. The FreeRTOS kernel port for the AURIX TC3x is available here. Corresponding code samples can be found here.

AURIX TC3x product page

Infineon Technologies 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post FreeRTOS teams with Infineon AURIX MCUs appeared first on EDN.

MIFARE DOUX, NXP’s contactless near-field communication (NFC) chip, integrates asymmetric and symmetric cryptography in one IC to simplify key management and distribution. The smart card IC enhances security for EV charging authentication, vehicle access, and other access management applications.

Leveraging public-key infrastructure (PKI), the chip supports asymmetric elliptic curve cryptography (ECC) and symmetric AES-256 cryptography. Additional features include a proximity check to counter relay attacks and transaction signatures to validate NFC transaction authenticity.

MIFARE DUOX holds Common Criteria EAL 6+ certification for both hardware and software, making it well-suited for high-security applications. Built for demanding environments, including outdoor and automotive use, it complies with ISO/SAE 21434 and MISRA-C standards and operates across an extended temperature range of -40°C to +105°C.

The MIFARE DUOX contactless smart card IC is now available.

MIFARE DUOX product page

NXP Semiconductors 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Smart card IC elevates NFC security appeared first on EDN.

The u-blox SARA-R10001DE LTE Cat 1bis module integrates Wireless Logic’s Conexa embedded SIM (eSIM) for global IoT connectivity. Supporting multi-IMSI technology and eUICC, the eSIM streamlines connectivity management by enabling automatic network switching based on coverage, cost, and regulatory needs.

The SARA-R10001DE supports full LTE Cat 1bis band coverage and comes provisioned with multiple Wireless Logic SIM profiles, permitting global deployment with a single SKU. In addition to working seamlessly upon deployment, the eSIM can also be remotely configured through Remote SIM Provisioning (RSP). It also enhances resilience by automatically switching to the best network available to ensure uninterrupted service in diverse regions.

Designed for LTE global coverage, the single-mode SARA-R10001DE provides a straightforward upgrade path for replacing legacy 2G and 3G devices with 4G LTE technology. The 16×26×2.2-mm module includes UART, USB, and GPIO interfaces and operates over a temperature range of -40°C to +85°C.

SARA-R10001DE product page 

u-blox

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post LTE Cat 1bis module packs Conexa eSIM appeared first on EDN.

Identiv’s high-frequency NFC-enabled inlays leverage NXP’s ICODE 3 tag IC, boosting RF performance and read speed. Designed for IoT applications, the ICODE 3 chip includes features suited for healthcare, logistics, industrial use, smart packaging, and specialty retail.

Identiv’s 13.56-MHz ID-Tune I3 and ID-Safe I3 inlays support both vicinity-range operation, reaching up to 1.5 meters, and close-range interactions. In vicinity mode, improved readability, material compatibility, and fast data transfer ensure seamless integration and increase operational efficiency. For close-range use, features such as first-opening indication and flexible counters enhance user engagement and product interactivity.

Key features of the ICODE 3-based inlays include:

• ISO/IEC 15693 and NFC Forum Type 5 tag compliance
• Read rate of up to 212 kbps
• One-lock memory command for tag encoding
• Customizable originality signature of 32 or 48 bytes
• Automatic SELFAdjust mechanism optimizes RF performance across different materials and conditions
• Two password-protected untraceable modes
• Extended NFC features for serialized, dynamic, and contextual messaging when tapped with an NFC-enabled phone

For more information about the ID-Tune I3 and the ID-Safe I3, which includes tamper detection, click on the product page links below.

ID-Tune I3 product page

ID-Safe I3 product page 

Identiv

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post NFC inlays are powered by NXP’s ICODE 3 appeared first on EDN.

PROFET Wire Guard high-side switches from Infineon provide built-in I2t wire protection for 12-V automotive power distribution. According to the manufacturer, these devices more accurately emulate wire stress characteristics compared to conventional fuses by using a selectable I2t protection curve, with six options tailored to specific application requirements.

In addition to I2t protection, the switches offer adjustable overcurrent protection for fast fault isolation and sequential diagnostics, enabling wire harness optimization when replacing mechanical relays and fuses. PROFET Wire Guard smart switches handle currents up to 27 A and a maximum operating voltage of 28 V. A low-power automatic idle mode reduces current consumption to just 50 µA during vehicle parking, while the output stage remains fully switched on.

The five PROFET Wire Guard devices offer pin-to-pin compatibility within the family and come in TSDSO-14 and TSDSO-24 packages. They have been developed and released as ISO 26262:2018 Safety Elements Out of Context (SEooC) for safety requirements up to ASIL D

PROFET Wire Guard product page

Infineon Technologies 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post High-side switches offer integrated wire protection appeared first on EDN.

POET Technologies Inc of Toronto, Ontario, Canada — designer and developer of the POET Optical Interposer, photonic integrated circuits (PICs) and light sources for the data-center, telecom and artificial intelligence (AI) markets — is to expand its optical engine production capacity in Malaysia...

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has appointed Melissa Garrett as senior VP & general counsel, effective 9 December. She succeeds Brad Kohn, who has resigned from the firm for another professional opportunity..

submitted by /u/1Davide [link] [comments]

Further to my prior coverage of this year’s iteration of periodic lightning-damage debacles at my Rocky Mountain foothills residence, I’d earlier mentioned that among the pieces of electronics gear that bit the dust this time was one of my network storage devices (NASs). The setback compelled me to no longer ignore a longstanding chink in my data-backup armor, which I’ve subsequently patched. What it was, and how I fixed it, is the subject of today’s post.

Simplistically speaking, there are (at least) three main ways that a storage device’s data can become compromised:

• If a virus, ransomware or other malware corrupts it, either via a computer it’s directly connected to, another device on the LAN, or a WAN-sourced attack, scenarios for which QNAP offers regularly executed (and updated) integrated scan-and-alert support.
• If a hard drive (or SSD, in some cases) fails. That’s why at minimum my NASs are all dual-drive setups, enabling RAID 1 redundancy, and they preferably contain at least three drives to add RAID 5-delivered performance to the mix, too.
• If the storage device itself dies; the power supply, for example, or something on the motherboard. Sometimes the failing component is straightforward to replace, but other times the NAS is destined only for the teardown pile, followed by the landfill.

The latter situation is the one I encountered recently. As background, I had two NASs active on my network at the time. My four-drive QNAP TS-453Be holds my music and photo libraries, along with decades’ worth of other accumulated personal files:

Its sibling beside it, a three-drive TS-328:

is my network backup destination. Part of the available capacity acts as a Time Machine repository for my Macs, while the remainder handles our various Windows machines, via a combo of File History and the legacy (and deprecated, but still included) Backup and Restore, both of which I’ll likely replace with something third-party and more modern sooner vs later.

The TS-328 is the one that died earlier this year. Although I could still get it to emit a factory-reset “beep”, firmware recovery attempts were fruitless; I’m guessing something(s) vital on the motherboard had fried (a common issue with this model, not just in response to an external “zap”, so I already knew I was running on borrowed time). While its stored data was less critical than that on the TS-453Be, since thankfully none of the computers previously backing up to it had themselves also failed, I wanted to get backup back up (heh heh) and running as quickly and straightforwardly as possible. And clearly, had the TS-453Be failed instead (or in addition), I would have had a more acute situation on my hands.

Step one: resurrect the TS-328. I found a gently used one on eBay (for nearly $100 more than I’d paid for my brand new one five-plus years earlier, although the seller did also throw in a used eight-port GbE switch, but I digress…), which was shipped and arrived promptly. I pulled the HDDs out of the original TS-328 and reinstalled them in the new-to-me NAS in the same order as before. And then I crossed my fingers and punched the power button.

Huzzah; it booted! Since the replacement NAS had only recently been retired by its previous owner, I’d gambled that its firmware version was close-to-identical to that in my expired device, which ended up being the case. There was only a minor discrepancy between the new-to-me NAS’s motherboard firmware version and the newer version stored on my old NAS’s drives, which I was alerted to and an online-supplied firmware update remedied. And speaking of online, I was glad to see that QNAP’s cloud service was smart enough to notice that the device now mated to my HDDs, therefore to my online account, had different hardware than was previously the case (a new MAC address at minimum) and insisted that I re-login and -associate the NAS with it first.

Now to fix my setup’s “chink in the armor” resulting from full-NAS failure potential. Some of you may already be familiar with the “3-2-1 backup rule”; Wikipedia has a concise summary:

The 3-2-1 rule…states that there should be at least 3 copies of the data, stored on 2 different types of storage media, and one copy should be kept offsite, in a remote location (this can include cloud storage). 2 or more different media should be used to eliminate data loss due to similar reasons (for example, optical discs may tolerate being underwater while LTO tapes may not, and SSDs cannot fail due to head crashes or damaged spindle motors since they do not have any moving parts, unlike hard drives). An offsite copy protects against fire, theft of physical media (such as tapes or discs) and natural disasters like floods and earthquakes.

While, as you’ll see in the paragraphs to follow, I’m not following the 3-2-1 rule to the most scrupulous degree—all of my storage devices are HDD-based, for example, and true offside storage would be bandwidth-usage prohibitive with conventional home broadband service—I feel, and hope you’ll agree, that I’ve followed it sufficiently, and that regardless the result is much more robust than it was before. It involves among other things pressing into service the two-drive QNAP TS-231K NAS that I’d also mentioned back in December 2020. I bought three (including a spare) 12 TByte used Hitachi enterprise SATA HDDs with five-year warranties for it from a well-known eBay retailer. Two of the three drives arrived reporting S.M.A.R.T warnings (197+198 sector count code combos, to be precise), but to the retailer’s credit, it replaced them promptly, even proactively sending replacements ahead of the originals’ return.

For my Macs, on which the “primary copy” of the data is stored, implementing the 3-2-1 rule was particularly straightforward. Modern MacOS versions support Time Machine configuration for multiple destinations, which the utility rotates among automatically for consecutive backups. While this means that each backup likely ends up being bigger (i.e., taking longer) than before, given that the precursor backup to that same destination was older than with a conventional single-destination alternative setup, it also means that if one destination fails, you’ve still got relatively current backups available at alternate destinations. In my case, there are two backup destinations, the Time Machine-tailored partitions on the TS-231K and TS-324. And counting the Mac source, you end up with three dataset copies total, if you’re not already keeping track.

What about the Windows systems? Again, the “primary copy” of the data is located on their SSDs. I run Backup and Restore sessions from them to the TS-324 every early-Saturday morning (since they tend to swamp Wi-Fi while in progress). And every early-Sunday morning, the QNAP HBS 3 Hybrid Backup Sync utility then does a full mirror of the archived Windows backup data from the TS-324 to the TS-231K (over Cat 5 this time, but still, why not do this while we’re still asleep?). This time, if one NAS fails, the backup data on the other NAS is no more than a week old. And once again, I end up with three total dataset copies.

The TS-453Be is a bit more complicated. Here, the primary copy of the data is stored on its four-HDD RAID 5 array. I’ve long had an external 2.5” HDD USB-tethered to it for daily sync purposes, which I can quickly grab (theoretically, at least) in case of fire or another emergency. And now, once again on Sunday mornings, the TS-453Be also does a full mirror to the TS-231K.

“Quickly grab” leads to my final discussion topic, involving the different-locations angle on the 3-2-1 rule. As I’ve already confessed, none of my backups are located offsite. However, I’ve installed the TS-231K upstairs in my office (at least for now, until I lose my sanity due to the constantly-clattering-HDDs din), still connected to the router over wired GbE, albeit now with a two-switch hop intermediary, as well as to the two other NASs and other LAN devices. And, as with the TS-324, the TS-453Be manages controlled shutdown of the TS-321K in response to premises power loss in coordination with their common NUT software and my APC UPS.

As I’ve mentioned before, the furnace room downstairs acts as my networking nexus. The probability for fire caused by the one of the furnaces (or any of the other equipment, for that matter) in that room is non-zero, and since that “other equipment” includes the hot water heater, fluid-delivered compromise of the NASs there is also a possibility. And given that “downstairs” is also “ground level”, an outside-sourced fire is also an ongoing concern, one accelerated of late due to climate change-induced environmental effects. But, thinking as I write these words, since my office is directly above the furnace room…yeah, having the TS-231K in my office probably isn’t wise, noise-wise or otherwise. Time to figure out somewhere else to put it.

With that, I’ll wrap up for today and welcome your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• Lightning strikes…thrice???!!!
• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• NAS successors add notable features
• Disassembling a Cloud-compromised NAS
• Exposing a NAS security issue
• NAS failure launches a data recovery mission
• Teardown: Disposable 1-Tbyte NAS drives: How’d that happen?

The post Beefing up backup appeared first on EDN.