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What GAA and HBM restrictions mean for South Korea

EDN Network - Птн, 06/14/2024 - 18:14

The next frontier in U.S. semiconductor restrictions for Chinese companies is gate-all-around (GAA) chip manufacturing technology. According to a Bloomberg report, measures are being discussed to limit Chin’s access to this advanced technology, widely considered a successor to the FinFET technology currently used in manufacturing cutting-edge semiconductor devices.

GAA, also known as gate-all-around field-effect transistor (GAAFET), replaces the vertical fins used in FinFET technology with a stack of horizontal sheets. This GAA structure further reduces leakage while increasing drive current, thus bolstering transistor density and delivering power and performance benefits.

Figure 1 GAA turns FinFET transistors sideways to make channels horizontal instead of vertical to extend semiconductor device scaling and reduce power consumption. Source: Samsung

In March this year, the U.K. imposed controls over GAA transistor technology on companies in China. Now, a source in Bloomberg report claims that the United States and other allies are expected to follow the U.K. in imposing controls on GAA technology this summer.

However, these access controls haven’t been finalized yet, mainly because the early version is considered very broad. It doesn’t make a clear distinction between whether these restrictions are aimed at stopping China from developing its own GAA technology or blocking chipmakers from the United States and its allies from selling GAA-based chips to companies in China.

Among the U.S. allies, South Korea is notable in this affair because Samsung Foundry is a pioneer in commercializing the GAA manufacturing technology in its 3-nm process node. Intel is expected to implement GAA transistor architecture in its 20A node which will be unveiled later this year. TSMC plans to employ GAA technology in its 2-nm process node to be made available in 2026.

That shows Samsung is ahead of the curve in GAA chip manufacturing architecture, so it’ll be interesting to see South Korea’s take on this matter. It’s worth noting that the Bloomberg report quotes anonymous sources and stresses that deliberations are private.

While South Korea and its tech star Samsung are likely to be at the center of this affair, the Bloomberg report also revealed some early-stage discussions about limiting exports of high-bandwidth memory (HBM) chips to China. That will put South Korea at the center of another technology export conflict as two of the three companies supplying HBM chips are from South Korea.

Figure 2 HBM is a high-end memory that stacks DRAMs using vertical channels called through-silicon vias (TSVs). Source: Samsung

Samsung and SK hynix, along with U.S. memory chip maker Micron, currently produce these high-end memory chips, which are considered crucial in AI applications while being paired with artificial intelligence (AI) processors. New restrictions on HBM chips, like GAA, could significantly impact South Korean tech-related exports.

The U.S. semiconductor technology export restrictions imposed on companies in China have mostly impacted chip vendors in the United States, with the exception of lithography expert ASML, which is based in the Netherlands. Now, South Korea could bear the brunt of these potential restrictions on GAA and HBM technologies.

As the Bloomberg report points out, no final decision has been made yet. But it’d be interesting to see how South Korean technology and trade officials respond to such export restrictions, especially, regarding the export of HBM chips, for which Samsung and SK hynix command nearly 90% of the market.

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Mitsubishi Electric sampling 8W and 14W GaN MMIC power amplifier chips

Semiconductor today - Птн, 06/14/2024 - 16:30
On 1 July, Tokyo-based Mitsubishi Electric Corp will begin sampling 8W and 14W gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) power amplifiers, shipped as customer-board-friendly bare chips, suitable for use in emergency communications and Ka-band multi-carrier satellite-communication (SATCOM) earth stations...

A look at spot welding

EDN Network - Птн, 06/14/2024 - 16:03

Joining one flat piece of metal to another flat piece of metal is a common requirement, but sometimes the choice of method lies open. For a case in point, please consider these two kitchen spatulas in Figure 1 and Figure 2.

Figure 1 One side of a pair of kitchen spatulas, one with two rivets and one with two spot welds. Source: John Dunn

Figure 2 The back side of the pair of kitchen spatulas. Source: John Dunn

Handle attachments to the spatula blade are made with two rivets in the tool on the left while the attachments are made in the other tool using spot welds. The fixture used for doing spot welding can be roughly sketched as follows in Figure 3.

Figure 3 A diagram of the fixture used to spot weld where a large current is passed through the junction of two pieces of metal, creating a high enough DC resistance between the electrodes to melt some of the metal. This then cools off and solidifies, fusing the flat pieces of metal to each other in a specific “spot”. Source: John Dunn

The welding process passes a very large current, AC or DC, through the junction of two pieces of metal being joined so that the DC resistance in between the two electrodes gets hot enough to melt some of the metal which then cools off and solidifies to fuse the two pieces of metal to each other at that “spot”, hence the name “spot welding”.

This process can be scaled for very small pieces of work like the two welds on this flashlight D-cell (Figure 4):

Figure 4 Two Very small spot welds on a flashlight D-cell. Source: John Dunn

to very large pieces as in automotive spot welding like Figure 5:

Figure 5 Two spot welds on an automobile door. Source: John Dunn

The more detailed scenario in spot welding involves:

  • When to apply the physical force
  • When to turn on the welding current
  • When to turn it off
  • How long to let the work pieces cool before releasing the physical force
  • Whether the two contacting electrodes need to be given extra cooling measures such as water flow within

The technology is quite sophisticated.

There are also personal cautions to bear in mind. One is that this procedure makes some very strong magnetic fields. If/when the work pieces melt, molten metal can be sprayed out.

“Danger, Will Robinson!”

The other thing is that magnetic fields can do a destructive number on some wristwatches as well as on credit card strips and the like, so if you are operating such a fixture, pay attention to what you may be wearing or carrying on your person.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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Choosing the Right Solution for Industrial Automation: AGVs vs. AMRs

ELE Times - Птн, 06/14/2024 - 14:25

In the realm of industrial automation, mobile Automated Guided Vehicles (AGVs) and Autonomous Mobile Robots (AMRs) are indispensable in enhancing efficiency by transporting materials within factories and warehouses. Both AGVs and AMRs share fundamental attributes and perform similar automation tasks, but their key differences in navigation capabilities and obstacle avoidance set them apart.

AGVs: Precision and Predictability

AGVs operate by following predetermined routes, and they do not deviate from these paths. When an AGV encounters an obstacle, it stops and waits until the obstacle is removed. AGVs employ various sensing techniques to detect their routes:

  1. Magnetic Tape: Sensors under the AGV detect magnetic tape on the factory floor and adjust the vehicle’s position accordingly. Additional magnetic tape can encode specific locations.
  2. Inductive Wire: Embedded wires in the floor guide the AGV, with sensors detecting the wire to maintain the correct path.
  3. Visual Tracking: Coloured tapes or markers like AprilTags are placed on the ground and detected by RGB cameras to map the route and determine location.
  4. Laser Guidance: A 360° laser on the AGV interacts with reflectors installed in the facility, measuring distances and angles to triangulate the AGV’s position.
AMRs: Flexibility and Intelligence

AMRs, on the other hand, utilize Simultaneous Localization and Mapping (SLAM) to navigate autonomously. Equipped with depth sensors, typically Lidar scanners, AMRs create and store detailed maps of their environment. This process involves initially driving the AMR around the facility to accumulate scans and generate a complete map. The map is then stored on the AMR and in fleet management control software and can be enhanced with additional data such as keep-out zones, speed reduction areas, and docking station locations. Goals are set on the map as coordinates, which the AMR navigates between by continuously comparing real-time scans with the stored map and adjusting its route to avoid obstacles.

Advantages and Disadvantages of AGVs

The main advantage of AGVs is their ability to follow a predetermined route with high precision and consistency, making them ideal for high-volume, repetitive tasks. However, AGVs require substantial infrastructural changes, such as installing and maintaining tapes, wires, or reflectors. These components are susceptible to wear and tear, and any necessary adjustments can significantly disrupt operations. Furthermore, AGVs cannot navigate around obstacles autonomously, which can lead to operational downtime.

Advantages and Disadvantages of AMRs

While AMRs have a higher initial cost and are less predictable in terms of exact travel time compared to AGVs, their advantages are substantial. AMRs do not require any infrastructural changes, as they can localize and navigate without markers. Updates to tasks and goals can be made quickly through software, and facility expansions or automation upgrades can be accommodated by generating new maps or extending existing ones.

In dynamic environments, the ease of use, flexibility, and scalability of AMRs provide a clear advantage. Their enhanced sensing capabilities, including longer-range Lidar, 3D depth sensing, radar, and RGB vision technologies, combined with superior computing power and artificial intelligence, enable advanced features and improved human-robot interaction.


In the evolving landscape of industrial automation, the choice between AGVs and AMRs hinges on specific operational needs. AGVs excel in environments requiring high precision and repetitive tasks but come with significant infrastructure and maintenance demands. AMRs offer unparalleled flexibility and adaptability, making them suitable for dynamic and rapidly changing environments. Ultimately, the decision should be based on the specific requirements and future scalability of the automation tasks at hand.

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Rocket Lab allocated $23.9m US CHIPS Act funding

Semiconductor today - Птн, 06/14/2024 - 13:55
Launch services and space systems provider Rocket Lab USA Inc has signed a non-binding preliminary memorandum of terms (PMT) with the Department of Commerce that would see Rocket Lab receive up to $23.9m in direct funding under the CHIPS and Science Act...

Breakthrough in Computer Vision Speeds Up Screening of Electronic Materials

ELE Times - Птн, 06/14/2024 - 13:36

A new computer vision technique developed by MIT engineers is set to revolutionize the screening process for electronic materials, significantly speeding up the characterization phase, which has been a major bottleneck. This innovation could dramatically boost the development of high-performance materials for solar cells, transistors, LEDs, and batteries.

Key Advancements
  1. Speed and Efficiency: The new method characterizes electronic properties of materials 85 times faster than conventional methods. This is achieved through the use of computer vision algorithms that analyze images of printed semiconducting samples.
  2. Key Properties Analyzed: The technique estimates two critical electronic properties:
  • Band Gap: The energy required to activate electrons.
  • Stability: The longevity of the material under various conditions.
  1. Automation and Integration: The technique is designed to be part of a fully automated materials screening system, potentially leading to an autonomous lab setup. This system would continuously make and test new materials based on AI predictions, operating 24/7 until the optimal material is discovered.
  2. Applications and Benefits: The technique can be applied across various fields, including solar energy, transparent electronics, and advanced transistors. It leverages the richness of hyperspectral imaging data, processed by sophisticated algorithms, to quickly and accurately determine material properties.
Detailed Process

Hyperspectral Imaging: Unlike standard cameras, hyperspectral cameras capture detailed images with 300 colour channels. The first algorithm processes this data to compute the band gap swiftly.

Stability Assessment: The second algorithm uses standard RGB images to monitor changes in the material’s colour over time, correlating these changes to stability.

Research and Development

The technique was developed and tested by MIT researchers, including graduate students Eunice Aissi and Alexander Siemenn, with contributions from their colleagues and international collaborators.

Validation and Accuracy: When compared to manual characterization by experts, the new method showed 98.5% accuracy for band gap estimation and 96.9% accuracy for stability, demonstrating both speed and precision.

Future Outlook

The researchers envision integrating this technique into a fully automated materials discovery pipeline, enhancing the speed and efficiency of developing new electronic materials. This innovation holds promise for significant advancements in renewable energy and electronic technologies.

This breakthrough in computer vision and materials science marks a significant step towards more efficient and rapid development of advanced functional materials, essential for the next generation of electronic devices.

For more detailed information, you can refer to the original study published in Nature Communications.

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GaN power module improves inverter efficiency

EDN Network - Чтв, 06/13/2024 - 23:59

A 650-V GaN intelligent power module (IPM) from TI enables up to 99% inverter efficiency for major home appliances and HVAC systems. The DRV7308 IPM integrates 650-V, 205-mΩ e-mode GaN FETs in a half H-bridge configuration, capable of driving three-phase BLDC/PMSM motors with up to 450-V DC rails.

Worldwide efficiency standards for appliances and HVAC systems, such as SEER, MEPS, Energy Star, and Top Runner, are becoming increasingly stringent. TI reports that the DRV7308 helps engineers meet these standards by leveraging GaN technology to deliver enhanced efficiency and thermal performance, with 50% reduced power losses compared to existing solutions. It also achieves low dead time and low propagation delay, both less than 200 ns. This allows higher PWM switching frequencies, which reduce audible noise and system vibration.

Housed in a 12×12-mm, 60-pin QFN package, the DRV7308 is one of the industry’s smallest IPMs for motor drive applications ranging from 150 W to 250 W. Its high efficiency eliminates the need for an external heatsink, shrinking motor drive inverter PCB size by up to 55%. The integrated current sense amplifier, protection features, and inverter stage further reduce solution size and cost.

Preproduction quantities of the DRV7308 IPM are available for purchase on TI.com. Prices start at $5.50 each in lots of 1000 units. An evaluation module is also available for $250.

DRV7308 product page 

Texas Instruments  

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Reference design covers GaN e-mobility charger

EDN Network - Чтв, 06/13/2024 - 23:58

Transphorm has released a 300-W DC/DC GaN-based reference design for 2-wheel and 3-wheel electric vehicle (EV) battery chargers. The TDDCDC-TPH-IN-BI-LLC-300W-RD design guide employs four TP65H150G4PS 650-V, 150-mΩ SuperGaN FETs in TO-220 packages to form an isolated bidirectional battery charger. Although the power level of this reference design is only 300 W, it features a full-bridge LLC topology with the potential for significantly higher power levels.

The reference design illustrates a fully analog implementation without processor firmware for the power stage. Simple jumpers manage power flow in this design, but these will need to be replaced with controls that a battery management system can operate in a real product.

Key specifications of the reference design include:

In addition to EV onboard chargers, the reference design can be used for renewable energy systems, backup power supplies, and vehicle-to-everything (V2X) applications. The design guide and BOM can be downloaded by following the product page link below.

TDDCDC-TPH-IN-BI-LLC-300W-RD product page


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MATLAB library ignites 6G innovation

EDN Network - Чтв, 06/13/2024 - 23:58

The 6G Exploration Library from MathWorks empowers engineers to explore, model, and simulate 6G-enabling technologies with MATLAB. Extending the capabilities of the company’s 5G Toolbox, the add-on library allows users to configure and generate 6G waveform candidates. It efficiently bridges MATLAB to RF instruments or software-defined radios, facilitating over-the-air waveform transmission and precise signal quality measurements.

The 6G Exploration Library contains reference designs and examples, enabling users to:

  • Generate waveforms with parameters extending beyond the limits of 5G NR specifications.
  • Simulate 6G candidate links, including transmitter operations, channel models, RF impairments, and reference receiver algorithms.
  • Explore the impact of hardware impairments at sub-THz carrier frequencies.
  • Model reconfigurable intelligent surfaces (RIS) and experiment with propagation scenarios with and without the presence of blockages.
  • Apply AI techniques to solve 6G wireless communications problems.

MathWorks will showcase the 6G Exploration Library at next week’s IMS 2024 conference. It will also participate in multiple workshops and educational seminars focused on 6G and artificial intelligence.

6G Exploration Library product page


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Isolated probe limits common-mode noise

EDN Network - Чтв, 06/13/2024 - 23:57

An isolated probing system, the R&S RT-ZISO measures fast switching signals in environments with high common-mode voltages and currents. Its power-over-fiber architecture galvanically isolates the DUT from the measurement setup, providing a higher common-mode rejection ratio (CMRR) than conventional differential probes.

The oscilloscope probe delivers accurate differential measurements, offering an input and offset range of ±3 kV, a common mode range of ±60 kV, and a rise time of less than 450 ps. It suppresses fast common-mode signals that can distort and interfere with accuracy, achieving a CMRR of greater than 90 dB (30,000:1) at 1 GHz. Upgradeable bandwidth options for the probing system include 100 MHz, 200 MHz, 350 MHz, 500 MHz, and 1 GHz.

The RT-ZISO probing system connects to any oscilloscope with a BNC or SMA interface. However, it offers seamless operation and control when connected to an R&S oscilloscope. With a CAT III 1000-V safety rating, the RT-ZISO ensures reliable electrical measurements. Additionally, its safe-attach feature allows for easy and secure swapping of probe tips.

To request a price quote for the RT-ZISO isolated probing system, click on the link to the product page below.

RT-ZISO product page

Rohde & Schwarz 

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Industrial sensor unit embeds AI processing

EDN Network - Чтв, 06/13/2024 - 23:57

ST’s ISM330BX 6-axis inertial measurement unit (IMU) combines edge AI processing and sensor fusion for industrial vibration sensing and motion tracking. The compact system-in-package contains a 3-axis digital gyroscope and a 3-axis digital accelerometer featuring a low-noise architecture and bandwidth up to 2 kHz.

The part’s integrated edge-processing engine pairs a machine-learning core with AI algorithms and a finite state machine. This not only offloads the host processor, but also conserves system power. The ISM330BX also employs ST’s sensor fusion low-power (SFLP) algorithm for 3D orientation tracking. Adaptive self-configuration allows the sensor to automatically optimize settings in real-time to achieve best performance and power.

A built-in analog hub connects external analog sensors to the edge-processing engine for data filtering and AI inference. The ISM330BX also features Qvar, ST’s electric charge variation detector. Qvar enables the IMU to integrate touch and close-proximity detection, as well as value-added functions such as water leak sensing.

In production now, the ISM330BX costs $4 each in lots of 1000 units Additionally, the IMU is included in ST’s 10-year product-longevity program for industrial components.

ISM330BX product page 


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SemiQ launches 1700V SiC Schottky discretes and dual diode modules

Semiconductor today - Чтв, 06/13/2024 - 17:35
SemiQ Inc of Lake Forest, CA, USA — which designs, develops and manufactures silicon carbide (SiC) power semiconductors and 150mm SiC epitaxial wafers for high-voltage applications — has added 1700V SiC Schottky discrete diodes and dual diode packs to its QSiC product line...

System-on-chip (SoC) design is all about IP management

EDN Network - Чтв, 06/13/2024 - 16:13

For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual property (IP) blocks from multiple vendors. This makes managing silicon IP the dominant task in the design process.

Generally, less than a tenth of a new SoC design will be newly written RTL code. And often, the high-level chip architectural decisions will be clear: a variation on an existing architecture or a reflection of major data flows in the application layered on a standard bus or network-on-chip (NoC) structure.

But each piece of IP in the design—and there may be dozens of types and hundreds of instances—requires management. The chip designers must define requirements, select vendors and specific products, make any necessary customizations, set configuration parameters, and integrate the IP instances into a working, testable system. This process will consume most of the project resources until physical design.

This reality makes expertise in managing IP a significant factor in the success of an SoC design. Perhaps less obviously, access to IP—particularly the ability to get attention, detailed specifications and documentation, bug fixes, and customization support from large, influential IP vendors—becomes a critical issue. The growing complexity of the IP blocks only adds to the challenge.

Figure 1 IP management is a significant consideration in the success of an SoC design. Source: Faraday Technology

A vital partnership

This situation adds a new dimension to the familiar space of design partnerships. Many SoC design teams have used design-services companies to supplement their teams on specific skills—for example, to do physical design.

In some cases, this supplementing has broadened into a full partnership, with the design partner taking on many steps in the design process. In extreme cases, the client may only have a functional description of the SoC or a proverbial sketch on a napkin at the beginning of the engagement.

However, as IP becomes the center of attention, clients are asking design partners to shoulder IP management as well. Indeed, this can be a powerful lever for the client. Let’s look closer at what this new partnership level entails and what it implies about the ideal design partner.

Flexible engagement

Only a few SoC design relationships start on a scribbled napkin. However, in many more cases, there are some major IP blocks for which the client has only a conceptual understanding. For example, a client may know they need a low-power artificial intelligence (AI) accelerator block for an Internet of things (IoT) chip. However, they may have little information on how these complex blocks perform with different models or how they are structured internally.

Or a team may be writing code for a novel function in their SoC but have no idea how to select and configure a RISC-V CPU core to execute their new code within timing and power constraints. Yet another client may know precisely the UCIe interface requirements for their design, but not exactly how to configure any available UCIe interface IP blocks to meet those requirements.

These differences make flexible engagement vital. A design partner should be able to join the project at any level, from concept through netlist, and mesh smoothly with the client’s design team. Initially, the goal will be working with the client to refine the IP requirements—moving from concept to functional spec to detailed interface, power/performance/area, and layout requirements—so the partners can select the best IP for each instance in the design.

IP selection

With the requirements in hand, the client and design partner will select the IP to be used. At this point, the partner’s role diverges from the traditional idea of a hot-shot bunch of designers-for-hire. The depth of the partner’s relationships with IP vendors becomes crucial.

Figure 2 IP selection is now a crucial part of an SoC design project. Source: Faraday Technology

Ideally, the partner would develop and maintain their extensive IP libraries in-house. This allows the partner to match requirements against its inventory quickly. If a match is close but not perfect, the IP development team has the documentation, tools, and resources to customize the IP block for the client’s specific needs.

A partner needs many strengths beyond skilled design engineers in selecting, customizing, and licensing IP. A broad internal portfolio of silicon-verified IP, backed by the team that designed those blocks, is a huge advantage.

There will be cases when there is no close match. That brings in the IP outsource team, an engineering group exclusively charged with building and maintaining third-party IP relationships. Such a team has a vast global network of IP suppliers, ensuring it can match the client’s requirements.

A global network of time-tested IP licensing and development relationships with third-party IP vendors—and a team dedicated to maintaining that network—is essential. A client should especially investigate a prospective design partner’s relationship with ARM and with the growing ecosystem of RISC-V providers.

IP integration

The design partner will also be deeply involved in IP integration. The IP instances must be configured correctly and then connected to the chip’s underlying bus or network architecture. The correct operation of the assembled SoC design must be verified. Important subjects beyond functional design, such as test architecture, power management, and clock architecture, must be resolved—ideally, uniformly.

The first step, connectivity, begins with selecting IP blocks with the necessary interfaces. However, some blocks may require customization to meet interface requirements perfectly. In other cases, the integration team may have to create a wrapper, controller, or gateway between regions of the design. A large IP design team with this in-house expertise is a huge time saver.

Verification is an equal challenge. Often, an IP block doesn’t behave as expected—or as described—in the assembled SoC design. This is another situation where an internal IP design team is immensely valuable. Even with external IP, a design partner can usually resolve problems without bringing in a third-party vendor.

A detailed knowledge of the internals of the IP blocks is also valuable in power management and when designing for test. Blocks may be designed with specific assumptions about test strategies, the balance of built-in self-test (BIST) versus external access, sleep modes, and how to deploy power or clock gating.

These choices must be harmonized across the design to produce an SoC with a minimal test time and an effective chip-wide power-management strategy. Making those choices may require designers to get elbow-deep into the internals of the IP blocks.

Finding a partner

We have touched upon several issues that require an effective design partner to have deep expertise in IP. The ideal partner for today’s SoC designs would have its extensive internal IP portfolio and a broad network of third-party vendors.

It would have separate engineering groups supporting these two sources. It would also have a flexible engagement model that would divide tasks between client and partner teams on a block-by-block basis based on the client’s resources and expertise.

The dominance of IP in SoC design has changed the nature of the design task and what a client must expect of a design partner.

Efren Brito is technical director at Faraday Americas.

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Cadence and Samsung Foundry Accelerate Chip Innovation for Advanced AI and 3D-IC Applications

ELE Times - Чтв, 06/13/2024 - 15:02
  • AI digital and analog tools optimized for advanced node SF2 gate-all-around (GAA), driving enhanced quality of results and accelerating circuit process node migration
  • Cadence’s best-in-class 3D-IC technology enabled for all of Samsung Foundry’s multi-die integration offerings, accelerating the design and assembly of stacked chiplets
  • Cadence’s broad IP portfolio and tools for next-generation AI designs will enable customers to achieve first-pass silicon success and accelerate time to market

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a broad collaboration with Samsung Foundry that includes technology advancements to accelerate design for AI and 3D-IC semiconductors, including on Samsung Foundry’s most advanced gate-all-around (GAA) nodes. The ongoing collaboration between Cadence and Samsung significantly advances system and semiconductor development for the industry’s most demanding applications, including AI, automotive, aerospace, hyperscale computing and mobile.

Through this close collaboration, Cadence and Samsung have demonstrated the following:
  • AI enables lower leakage power and development of SF2 GAA test chips: Cadence, in close collaboration with Samsung Foundry, has leveraged the Cadence® Cerebrus Intelligent Chip Explorer and its AI technology in both DTCO and implementation to minimize leakage power on their SF2 GAA platform. Compared to the best-performing baseline flow, the Cadence.AI result achieved a more than 10% reduction in leakage power. As part of this ongoing collaboration, a mutual customer is actively involved in the development of a test chip using Cadence.AI for an SF2 design.
  • Cadence backside implementation flow certified for Samsung Foundry SF2: As a result of extensive collaboration between Cadence and Samsung Foundry, a complete Cadence backside implementation flow has been certified for the SF2 node to accelerate the development of advanced designs. The full Cadence RTL-to-GDS flow, including the Genus™ Synthesis Solution, Innovus™ Implementation System, Quantus™ Extraction Solution, Pegasus™ Verification System, Voltus™ IC Power Integrity Solution and Tempus™ Timing Signoff Solution has been enhanced to support backside implementation requirements such as backside routing, nano TSV insertion, placement and optimization, signoff parasitic extraction, timing and IR analysis, and DRC. The Cadence backside implementation flow has been validated with a successful Samsung SF2 test chip, demonstrating the flow is ready for use.
  • Cadence has collaborated with Samsung Foundry to enable solutions for Samsung Foundry’s multi-die offerings: The Cadence Integrity™ 3D-IC platform is enabled for all of Samsung’s multi-die integration offerings, and its early analysis and package awareness features are now compliant with Samsung’s 3DCODE 2.0 version. In addition, Cadence and Samsung have expanded the multi-die collaboration by enabling differentiating technologies like thermal warpage analysis using the Cadence Celsius Studio and system-level LVS with Cadence Pegasus Verification System. Cadence is also supporting Samsung with a package PDK that reduces design time with the Allegro X system. Combined with the Integrity 3D-IC platform, it optimizes the package design flow.
  • AI’s Virtuoso Studio flow successfully deployed for analog circuit process migration: Purpose-based instance mapping in the AI-powered Virtuoso Studio provided rapid retargeting of the schematics, while circuit optimization in Virtuoso Studio’s Advanced Optimization Platform helped Samsung achieve a 10X improvement in turnaround time when migrating a 100MHz oscillator design from 14nm to 8nm. In addition, a FinFET-to-GAA analog design migration reference flow is available for joint customers, with successful experimental results.
  • Cadence mmWave RFIC design flow successfully used to tapeout 14RF circuit design: Cadence and Samsung successfully taped out a 48GHz power amplifier design, representing silicon validation of the robust, full system reference flow that leverages the Cadence EMX Designer to create passive devices with fast modeling and layout automation. Full design EM extraction with the EMX 3D Planar Solver and EM/IR analysis using Voltus XFi and Quantus ensured that the IC met aggressive metrics, Pegasus was used for signoff DRC/LVS, while AWR VSS provided a seamless environment to carry out initial system-level budgeting and post-layout verification. Mutual customers can feel confident utilizing this flow to deliver leading-edge designs to market in a timely manner.
  • Cadence Pegasus Verification System is certified for Samsung Foundry’s 4nm and 3nm process technologies: Through the collaboration with Samsung Foundry, the Cadence physical verification flow is optimized to allow mutual customers using Samsung Foundry’s advanced nodes to reach signoff accuracy and runtime goals for a faster time to market. The Pegasus system is now certified across multiple advanced nodes at Samsung Foundry, which are proven and in production by customers, with simplified, all-inclusive licensing support. The Pegasus system is integrated into the AI-powered Cadence Virtuoso Studio as iPegasus to enable in-design signoff quality DRC and interactive metal fill in the layout implementation, offering up to 4X faster turnaround times.
  • Cadence IP portfolio offers comprehensive industry solutions on advanced Samsung nodes:

Cadence’s latest IP built on Samsung SF5A includes industry-leading PHY IP for 112G-ULR SerDes, PCIe® 6.0/5.0, UCIe™ , DDR5-8400, DDR5/4-6400 Memory and USB 2.0, offering customers complete platform solutions.

Cadence’s PHY IP for PCIe 6.0 on Samsung SF5A has been successfully certified for PCIe 5.0 x8 compliance and demonstrated seamless interoperability with other PCIe 5.0/6.0 system and test equipment, further showcasing its PCIe solution maturity

Cadence is furthering its partnership with Samsung Foundry by pushing the performance envelope, designing advanced memory IP for GDDR7 on Samsung SF4X and SF2, and helping reshape the HPC/AI industry with this new memory standard.

  • Advanced verification for AI design complexity: Samsung Foundry applied Cadence’s advanced verification technologies, such as the Palladium Enterprise Emulation System, JasperC, STG, and Xcelium ML, to tackle rising AI chip complexity and achieve time-to-market requirements in SF3.

“We are honored to partner with Samsung, a true example of a chips-to-systems company, to bring this technology for our joint partners to design the next generation of intelligent systems,” said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. “The hyperconvergence of AI with modern accelerated compute requires a strong silicon infrastructure. With these new AI-powered, certified design flows and standardized solutions, mutual customers can confidently design for Samsung advanced nodes while achieving their design and time-to-market goals.”

“Samsung and Cadence have a close collaboration to advance technology and help our customers deliver competitive designs to the market efficiently,” said Sangyun Kim, Vice President and head of Foundry Design Technology Team at Samsung Electronics. “Our joint efforts enable customers to utilize Samsung’s latest process and technology innovations to push the limits for the most advanced AI, hyperscale computing and mobile SoC designs.”

To learn more about Cadence AI offerings, please visit: Cadence.ai.

The post Cadence and Samsung Foundry Accelerate Chip Innovation for Advanced AI and 3D-IC Applications appeared first on ELE Times.

Industry’s First PCIe 7.0 IP Solution for Next-Gen HPC and AI Chips Designs

ELE Times - Чтв, 06/13/2024 - 14:03

Synopsys recently unveiled the industry’s first complete PCIe 7.0 IP solution, designed to accelerate trillion-parameter HPC and AI supercomputing chip designs. This new IP solution future-proofs bandwidth for hyperscale AI data centre infrastructure, addressing the demanding requirements of transferring massive amounts of data for compute-intensive AI workloads.

Key Highlights of Synopsys’ PCIe 7.0 IP Solution
  1. Complete Solution: Synopsys offers the industry’s only complete PCIe 7.0 IP solution, including the controller, IDE security module, PHY, and verification IP. This solution enables data transfers of up to 512 GB/s bidirectional in an x16 configuration.
  2. Power Efficiency and Low Latency: The pre-verified PCIe 7.0 Controller and PHY IP provide low latency data transfers and up to 50% more power efficiency compared to prior versions while maintaining signal integrity.
  3. Security: The Synopsys IDE Security Module for PCIe 7.0, pre-verified with the Controller IP, offers data confidentiality, integrity, and replay protection against malicious attacks, ensuring a secure data transfer environment.
  4. Experience and Reliability: With more than two decades of PCIe IP experience and over 3,000 design wins, Synopsys offers a low-risk path to silicon success, providing customers with a robust and reliable IP solution.

This solution is crucial for chip makers addressing the bandwidth and latency challenges posed by large language models and compute-intensive AI workloads. Synopsys’ PCIe 7.0 IP solution supports secure data transfers, mitigating AI workload data bottlenecks and enabling seamless interoperability within the ecosystem.

At the PCI-SIG DevCon in Santa Clara, Synopsys demonstrated the world’s first PCIe 7.0 IP over optics, showcasing the technology’s capabilities in real-world scenarios. This includes Synopsys PCI Express 7.0 PHY IP electrical-optical-electrical (E-O-E) TX to RX running at 128 Gb/s with OpenLight’s Photonic IC, and successful root complex to endpoint connection with FLIT transfer using Synopsys PCIe 7.0 Controller IP.

Synopsys’ PCIe 7.0 IP solution is part of a broader portfolio for high-performance computing (HPC) SoC designs, including solutions for 1.6T/800G Ethernet, CXL, and HBM. The company’s extensive interoperability testing, comprehensive technical support, and robust IP performance help designers accelerate time to silicon success and production.

Industry leaders such as Intel, Astera Labs, Enfabrica, Kandou, XConn, Rivos, and Microchip have embraced PCIe 7.0 for AI data center infrastructure, recognizing its importance in delivering high-bandwidth, low-latency connectivity critical for data-intensive and latency-sensitive workloads.

Overall, Synopsys’ PCIe 7.0 IP solution represents a significant advancement in enabling next-generation HPC and AI chip designs, providing a secure, efficient, and high-performance interconnect solution for the evolving demands of hyperscale AI data centers.

The post Industry’s First PCIe 7.0 IP Solution for Next-Gen HPC and AI Chips Designs appeared first on ELE Times.

Infineon receives German Brand Award for “Corporate Brand of the Year”

ELE Times - Чтв, 06/13/2024 - 13:53

Infineon Technologies AG received the German Brand Award in the renowned “Best of Category” as “Excellent Brands – Corporate Brand of the Year”. The German Council of Design recognizes Infineon’s exceptional brand development, highlighting the company’s dedication to establishing a consistent brand that harmonizes seamlessly with its corporate strategy.

“To receive the German Brand Award as Corporate Brand of the Year is a special recognition for Infineon’s brand development over the past years,” said Andreas Urschitz, Member of the Management Board and Chief Marketing Officer of Infineon. “We are a global technology and thought leader with a clear vision and decisive actions. As a company, we are dedicated to driving decarbonization and digitalization through our solutions and in our business areas, together with our customers and partners. This commitment is deeply rooted in our corporate strategy, our brand, and within the entire global Infineon team.”

The award underlines Infineon’s commitment to excellence and innovation in brand strategy and design. It also reflects a strategic and decisive approach in the brand and corporate strategy, which ultimately enhances the company’s market presence with its audience.

The jury of the German Brand Award, which consists of members of the German Council of Design, acknowledged Infineon’s brand identity that resonates with its target audience while continuously staying true to its core values and vision. The jury’s statement states: “Infineon has been a strong brand for 25 years – and also ‘Corporate Brand of the Year’ in 2024. The semiconductor manufacturer has decisively developed its strategy and design to link the brand even more closely with the corporate strategy. The close integration, including vision, mission and values, is exemplary and contributes to an outstanding positioning. Only a few companies in the competitive arena have such a consistent and distinctive brand. The dedicated 360-degree brand development and, above all, implementation is credible and has a high unique selling point.”

The German Brand Award is the award for successful brand management, initiated by Germany’s design and brand authority. Judged by a top-tier jury of experts from brand management and brand science, the German Brand Award discovers, presents and honors unique brands and brand makers.

The post Infineon receives German Brand Award for “Corporate Brand of the Year” appeared first on ELE Times.

TI unveils industry’s first GaN IPM to enable smaller, more energy-efficient high-voltage motors

ELE Times - Чтв, 06/13/2024 - 13:37

News highlights

  • 650V intelligent power module (IPM) enables more than 99% inverter efficiency for appliances and HVAC systems by integrating TI’s gallium nitride (GaN) technology.
  • Engineers can reduce solution size by up to 55% as a result of the IPM’s high integration and its efficiency which removes the need for an external heat sink.

Texas Instruments (TI) (Nasdaq: TXN) today introduced the industry’s first 650V three-phase GaN IPM for 250W motor drive applications. The new GaN IPM addresses many of the design and performance compromises engineers typically face when designing major home appliances and heating, ventilation and air-conditioning (HVAC) systems. The DRV7308 GaN IPM enables more than 99% inverter efficiency, optimized acoustic performance, reduced solution size and lower system costs. It is on display at the Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM) Conference, held June 11-13 in Nuremberg, Germany.

“Designers of high-voltage home appliances and HVAC systems are striving to meet higher energy-efficiency standards to support environmental sustainability goals around the world, said Nicole Navinsky, Motor Drives business unit manager at TI. “They are also addressing consumer demand for systems that are reliable, quiet and compact. With TI’s new GaN IPM, engineers can design motor driver systems that delivers all of these expectations and operates at peak efficiency.”

Improve system efficiency and reliability with TI GaN

Worldwide efficiency standards for appliances and HVAC systems such as SEER, MEPS, Energy Star and Top Runner are becoming increasingly stringent. The DRV7308 helps engineers meet these standards, leveraging GaN technology to deliver more than 99% efficiency and improve thermal performance, with 50% reduced power losses compared to existing solutions.

In addition, the DRV7308 achieves industry-low dead time and low propagation delay, both less than 200ns, enabling higher pulse-width modulation (PWM) switching frequencies that reduce audible noise and system vibration. These advantages plus the higher power efficiency and integrated features of the DRV7308 also reduce motor heating, which can improve reliability and extend the lifetime of the system.

To learn more about the benefits of GaN technology, read the white paper, “How three-phase integrated GaN technology maximizes motor-drive performance.”

Advanced integration and high power density reduce solution size and costs

Supporting the trend of more compact home appliances, the DRV7308 helps engineers develop smaller motor drive systems. Enabled by GaN technology, the new IPM delivers high power density in a 12mm-by-12mm package, making it the industry’s smallest IPM for 150W to 250W motor-drive applications. Because of its high efficiency, the DRV7308 eliminates the need for an external heatsink, resulting in motor drive inverter printed circuit board (PCB) size reduction of up to 55% compared to competing IPM solutions. The integration of a current sense amplifier, protection features and inverter stage further reduces solution size and cost.

To learn about designing more efficient, compact motor systems, see the GaN IPM page on TI.com.

This high-efficiency, high-voltage GaN IPM is the latest example of TI innovations to help solve engineering challenges and transform motor designs.

TI’s reliable high-voltage technology at PCIM 2024

Visitors to PCIM can see new products and solutions from TI that are enabling the transition to a more sustainable future with reliable high-voltage technology in Hall 7, Booth 652. In addition to the DRV7308 GaN IPM, TI highlights at PCIM include:

  • Next-generation electric vehicle (EV) propulsion system: TI is demonstrating a new 800V, 750kW SiC-based scalable traction inverter system for EV six-phase motors, in collaboration with EMPEL Systems. The demonstration features high power density and efficiency using TI’s high-performance isolated gate drivers, isolated DC/DC power modules and Arm® Cortex®-R MCUs.
  • Speaking session: TI’s manager of high-voltage power systems applications, Sheng-Yang Yu, will speak on June 11 at Markt & Technik panel discussion: “Will SiC ultimately Hold its Own against GaN?”
  • Speaking session: TI’s manager of renewable energy systems, Harald Parzhuber, will speak on June 12 at Bodo’s Power Systems panel discussion: “GaN Wide Bandgap Design, the Future of Power.”

For more information about all of TI’s speakers and demonstrations at PCIM, see ti.com/PCIM. 

Available today on TI.com

Pre- production quantities of the DRV7308 three-phase, 650V integrated GaN IPM are available for purchase now on TI.com.

  • Pricing starts at US$5.50 in 1,000-unit quantities.
  • Available in a 12mm-by-12mm, 60-pin quad flat no-lead (QFN) package.
  • The DRV7308EVM evaluation module is also available at US$250.
  • Multiple payment, currency and shipping options are available.

The post TI unveils industry’s first GaN IPM to enable smaller, more energy-efficient high-voltage motors appeared first on ELE Times.

Anritsu, in Collaboration with Sony Semiconductor Israel, Acquires Industry-First GCF Certification for Non-terrestrial Network (NTN) NB-IoT RF Conformance Testing

ELE Times - Чтв, 06/13/2024 - 13:17

Anritsu Corporation announces that the first NTN NB-IoT RF conformance tests have been validated on the New Radio RF Conformance Test System ME7873NR, powered by Sony Semiconductor Israel (Sony)’s Altair device.

The ME7873NR has acquired Global Certification Forum (GCF) certification for NB-IoT RF conformance testing in the Certification Agreement Group (CAG)#78[*] for the first time in the industry. The conformance tests are defined by 3GPP in TS 36.521-4 corresponding to the core requirements of TS 36.102 and have been submitted by Anritsu to the 3GPP Radio Access Network Working Group 5 (RAN WG5).

“We are pleased to collaborate with Anritsu on this important initiative,” said Levana Asraf Fouks, Sr. Director, System Validation & PM Manager, System Engineering at Sony Semiconductor Israel. “Our combined expertise means that our customers benefit from enhanced capabilities to meet their own evolving needs. By partnering with Anritsu from the early stages, we’re able to work towards a swift certification process for modules and devices. The validation of NTN NB-IoT RF conformance tests is a major step forward for the industry.”

“NTN NB-IoT, which is defined by 3GPP Release 17, is a standard determining the current use of NB-IoT in the NTN and enables new use cases and monetization opportunities for vertical industry segments,” said Keiji Kameda, General Manager of the Mobile Solutions Division at Anritsu Corporation. “We are proud that our collaboration with Sony enables us to help the industry validate new features so they can quickly reach the market and attain certification in GCF/PTCRB to realize new devices that enable new applications.”

Product Outline

The ME7873NR is an automated system for 3GPP TS 38.521/TS 38.533 5G NR RF and RRM tests.

The ME7873NR supports NB-IoT NTNs as specified in 3GPP TS36.521-3 and TS36.521-4, in anticipation of future support for 5G NTNs. Customers can also upgrade from ME7873LA to ME7873NR by simply adding a control PC. Anritsu contributes to a smooth transition from NB-IoT NTN to NR NTN.

The post Anritsu, in Collaboration with Sony Semiconductor Israel, Acquires Industry-First GCF Certification for Non-terrestrial Network (NTN) NB-IoT RF Conformance Testing appeared first on ELE Times.


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