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Nearly four decades ago (in his Designs for High Performance Voltage-to-Frequency Converters), famed designer Jim Williams cataloged five fundamental techniques for voltage to frequency conversion. One of those five is reproduced in Figure 1.

Figure 1 Precision charge pump closes feedback loop to make “crude V→F” accurate from “Designs for High Performance Voltage-to-Frequency Converters”.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Williams concisely summarizes how this famous topology works: “The DC amplifier controls a relatively crude V→F. This V→F is designed for high speed and wide dynamic range at the expense of linearity and thermal stability. The circuit’s output switches a charge pump whose output, integrated to DC, is compared to the input voltage The DC amplifier forces V→F operating frequency to be a direct function of input voltage.”

Earlier in “Designs for…” William had presented several terrific VFC designs embodying Figure 1’s concept, that utilized a variety of different charge pumps. Two of these were diode types. More examples of Williams VFC designs incorporating diode pumps are detailed in his fascinating (and entertaining!) narrative of his creative design process: “The Zoo Circuit” (Chapter 18).

The success of these and other diode-pump equipped designs proves the utility of diodes in precision applications. However, an inherent challenge in working diode pumps into VFCs is accommodation of the inconvenient fact that no (real) diode is ideal. Diodes incur non-linear and temperature-dependent voltage drop, shunt capacitance, reverse recovery charge, and other “charming” idiosyncrasies. Inspection of any good VFC with a diode pump (including Williams’s excellent designs) will reveal a significant fraction of circuitry and part count dedicated to mitigating these quirks. Figure 2 sketches where some of these errors arise and their effects on pump accuracy.

Figure 2 The realities of a diode pump where errors can arise such as non-linear and temperature-dependent voltage drop, shunt capacitance, reverse recovery charge, and more.

 If the diodes in Figure 2’s pump were perfect, then each Vpp cycle of the input frequency would output a dollop of charge Q = -VC, and we’d therefore have Vout = FVCR. But since they’re not, forward voltages (Vd), shunt capacitances (Cs), etc. subtract from the net charge pumped leaving Q = – (VC – 2Vd(C + Cs)) making Vout = F(VC – 2Vd(C + Cs))R.

 Traditional circuit tricks for (at least partially) canceling these errors and nulling out (most) of the tempco they introduce (e.g., 2mV/oC for each Vd) include adding strings of diodes in series with VFC voltage references and calibration trims in input networks. Although they can be made to work, fine tuning these remedies in a given design can be complex and one of it is particularly elegant or easy.

Figure 3 shows an approach that’s entirely different from reference tweaking: “Take-Back-Half”, or TBH!

Figure 3 TBH adds a half-amplitude reverse-polarity pump that subtracts error terms.

 TBH adds a new opposite-polarity pump in parallel with the usual diode pair, driven by a 1:2 ratio capacitive voltage divider with the same total capacitance. The result is to generate opposing charge packets that have half the nominal signal amplitude but equal error signal amplitude. Consequently, when the charges are summed, half the desired signal is “taken back” from the net pump output, but all the error goes away.

This leaves only the original, ideal-diode-case output:  Q = -VC and Vout = FVCR.

This verbiage might sound garbled and confusing (I know) but the analog algebra is simple and (I hope) clear. Please see Figure 3.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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• Temperature controller has “take-back-half” convergence algorithm
• Take-back-half thermostat uses ∆Vbe transistor sensor
• Voltage inverter design idea transmogrifies into a 1MHz VFC
• Inexpensive VFC features good linearity and dynamic range
• Single supply 200kHz VFC with bipolar differential inputs

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• Improves PCIe design productivity using a smarter and streamlined workflow with simulation-driven virtual compliance test solutions
• Supports design exploration and report generation that speeds chiplet signal integrity analysis and UCIe compliance verification to increase designer productivity and time-to-market

Keysight Technologies, Inc. introduces System Designer for PCIe, a new product in the Advanced Design System (ADS) product suite that supports simulation workflows based on industry standards for high-speed, high-frequency digital designs. System Designer for PCIe is an intelligent design environment for modeling and simulating the latest Peripheral Component Interconnect Express (PCIe) Gen5 and Gen6 systems. Keysight is also improving its electronic design automation (EDA) platform by adding new features to the existing Chiplet PHY Designer tool to estimate chiplet die-to-die link margin performance and Voltage Transfer Function (VTF) compliance measurement.

PCIe is a versatile and essential interface standard across a wide range of electronics industry segments due to its high-speed data transfer capabilities, scalability, and adaptability. Adoption spans from everyday consumer electronics to specialized applications in high-performance computing and critical infrastructure systems.

Complex PCIe designs support multi-link and multi-lane systems that involve a complex analysis setup between RootComplex and End-Point, sometimes incorporating mid-channel repeaters. Designers spend an inordinate amount of time preparing simulations that are prone to mistakes. Simulations often lack vendor-specific algorithmic modeling interface (AMI) simulation models, which are required early in the design cycle for design space exploration. Designers also need assurance that their prototype design will pass compliance testing before hardware fabrication.

• The System Designer for PCIe automates the setup for multi-link, multi-lane, and multi-level (PAM4) PCIe systems using a smart design environment. It simplifies simulation setup and reduces time-to-first-insight.
• The PCIe AMI modeler, which supports NRZ and PAM4 modulations, facilitates quick AMI model generation needed for PCIe system analysis. The AMI Model Builder gives designers a wizard-driven AMI model generation workflow to rapidly create models for both transmitters (Tx) and receivers (Rx).
• Streamlined, simulation-driven virtual compliance testing enables designers to ensure design quality. The integrated, simulation-driven PCIe compliance test workflow reduces design costs by minimizing design iterations and shortening time-to-market.

• Chiplet PHY Designer is the EDA industry’s first simulation solution for Universal Chiplet Interconnect Express (UCIe) standards, enabling predictions of die-to-die link margin, VTF for channel compliance analysis, and forwarded clock capability. Chiplet PHY Designer includes new design exploration and report generation features that accelerate signal integrity analysis and compliance verification to improve designer productivity and time-to-market.

Hee-Soo Lee, Director of High-Speed Digital segment, Keysight EDA, said, “We continue to expand our standards-driven workflow approach to support our customers. Our high-speed digital product portfolio is leading the EDA industry with the most accurate and advanced simulation software for signal integrity analysis and compliance test validation. Digital standards such as PCIe and UCIe are critical to the performance of electronic systems. Designers using our PCIe and UCIe simulation solutions in their workflows can shift left their development cycle to save significant time and cost.”

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Gautam Solar, a renowned name in India’s solar panel manufacturing sector, has taken a notable move forward in addressing the challenges posed by extreme weather conditions. During a press conference held at Sayaji Hotel in Indore, the company launched a comprehensive whitepaper focusing on the ramifications of the 2024 Indian Heat Wave on the performance of a solar power plant. This whitepaper also sheds light on the need for advanced technologies to maintain optimal solar power generation in high-temperature environments.

The whitepaper, titled “Enhancing Power Generation and CUF of Solar Power Plants Amid High Temperatures: Strategies for the 2024 Indian Heat Wave” plumbs deep into the detrimental effects of the 2024 Indian Heat Wave, which has severely impacted human health, caused hundreds of deaths, and negatively affected the performance of solar panels.

These adverse conditions have resulted in decreased power generation and lower CUF of solar power plants. Gautam Solar’s whitepaper addresses these issues by emphasizing the use of high-efficiency N-type Tunnel Oxide Passivated Contact (TOPCon) and Monocrystalline Passivated Emitter and Rear Contact (PERC) Solar Panels, which are designed to perform well even under elevated temperatures.

“At Gautam Solar, we are committed to pushing the boundaries of solar technology to ensure reliable and efficient power generation, even in the most challenging conditions. Our latest whitepaper elaborates our dedication to innovation and embracing the latest technology to address the impact of extreme heat on solar power systems,” said Mr. Gautam Mohanka, CEO of Gautam Solar.

Factors affecting Solar Panel Performance: An exploration of the various environmental factors that influence the power generation from a solar panel, including irradiance, ambient temperature, humidity etc.

Solar Panel Testing: Section dealing with testing of various temperature-related parameters which affect the performance of a solar panel, including measurement of Temperature Coefficients, Nominal Operating Cell Temperature (NOCT) and Performance at Standard Test Conditions (STC) and NOCT.

Mono PERC and N-Type TOPCon Solar Panels: Emphasis on the technical specifications of Gautam Solar’s high-efficiency Mono PERC and N-type TOPCon panels, which make them ideal for use in hot climate conditions. Their low temperature coefficients, high bifaciality factor and reduced degradation rates ensures good LCOE performance and makes them highly efficient in high-temperature areas.

System Design, Installation, Monitoring and Maintenance: Focus on ensuring optimal tilt angle and orientation for installation to ensure improved airflow and cooling. Further, implementation of ventilation and cooling methods is discussed. Lastly, usage of advanced monitoring systems for detecting temperature-related issues and regular maintenance to address heat-induced damages is covered.

The whitepaper further explores future work, emphasizing the need for continued research and development in heat-resilient materials, advanced cooling techniques, and adaptive system designs.

Mr. Gautam Mohanka further said, “The 2024 Indian Heat Wave demands the critical need to address high-temperature challenges in solar power plants. By leveraging advanced technologies like N-type TOPCon and Mono PERC solar panels, and implementing strategic design, installation, and maintenance practices, Gautam Solar aims to ensure optimal performance and reliability of solar power systems even in extreme heat conditions.”

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Ideal for next-generation smartphones, game consoles, and other consumer electronics applications

Littelfuse, Inc., an industrial technology manufacturing company empowering a sustainable, connected, and safer world, announced the extension of its ITV2718 surface-mountable Li-ion battery protector series. These fuses safeguard Li-ion battery packs against overcurrent and overcharging (overvoltage) conditions—even when fast charging.

The latest addition, the ITV2718, provides a five-amp, three-terminal fuse in a 2.7 x 1.8 mm footprint. The innovative design utilizes an embedded fuse and heater element combination to respond quickly, interrupting the battery pack’s charging or discharging circuit before overcharging or overheating conditions occur.

• Game consoles
• E-call
• Portable routers
• Portable modems
• Smartphones
• Notebooks and tablets

“By extending our ITV line of li-ion battery pack protection fuses even further to include these new five-amp-rated devices, Littelfuse is providing electronics engineers even more options for their next-gen consumer electronics designs,” said Stephen Li, Global Product Manager at Littelfuse. “Continuing to expand our portfolio of surface-mountable, three-terminal battery pack protectors enables us to provide these product development teams with even greater, more innovative solutions in battery protection.”

• Prevents overcurrent and overcharging battery pack damage via fast response time and low internal resistance.
• Surface-mount design simplifies automated printed circuit board (PCB) assembly.
• Meets industry safety requirements via UL and TUV certifications for faster compliance approval.
• Halogen-free and RoHS compliant environmentally friendly components.

The embedded three-terminal fuse cuts off the circuit immediately when an overcurrent condition occurs. The heater element, which is embedded directly under the fuse element, generates enough heat to blow the fuse once the IC or FET detects overcharging.

The ITV2718 is available in tape and reel format in quantities of 4,000. Sample requests are accepted through authorized Littelfuse distributors worldwide. For a listing of Littelfuse distributors, please visit Littelfuse.com.

Additional information is available on the ITV2718 Battery Protector product page. For technical questions, please contact:

• Stephen Li, Global Product Manager, sli2@littelfuse.com
• Amanda Cheng, Assistant Product Manager, acheng2@Littelfuse.com
• Liang Wu, Product Engineer, lwu3@Littelfuse.com

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UpNano co-developed a revolutionary manufacturing process for fused silica parts in the mm-range using 2PP technology.

UpNano GmbH (Vienna, Austria) has co-developed a novel manufacturing process for 3D–printed fused quartz objects. This innovative technology enables the production of high-precision shaped parts in the mm and cm-range. The process is based on Glassomer GmbH’s (Freiburg, Germany) innovation and has been modified for two-photon polymerization (2PP) 3D-printing using UpNano’s NanoOne high-resolution printing system. These are the highest performance 2PP 3D-printers on the market, capable of printing over 15 orders of magnitude.

Manufacturing minuscule and complex 3D objects in glass is a challenging process. This is even more the case, if the required material is to be high-quality fused silica (SiO₂) glass, which has an exceptionally high melting point. The only possible methods that can be used are based on non-commercially available equipment and include melting glass fibers using laser beams or fused deposition modeling to produce soda lime glass. These methods often result in final products with rough surfaces that are undesirable. Now, UpNano and Glassomer have developed a rapid 3D printing process to produce smooth fused silica parts in the mm and cm range with features in the μm range.

THREE STEPS AHEAD…
“It’s a three-step process”, explains Markus Lunzer, team lead of Materials & Application at UpNano. “The first step is to design and print the desired structure using all the advantages 2PP 3D-printing offers. The second step is to remove organic binder material followed by a high temperature sintering process, the third step.” At the core of this is a newly developed nanocomposite “UpQuartz”. In addition to SiO2 nanoparticles, it contains a specially designed polymer matrix that allows the composite to be 2PP 3D–printed in the first place. The printing process produces a “green part” that already has the shape of the final and desired structure. To obtain the fused silica product in the end, the polymer matrix must be removed. Heating the green part to 600°C effectively removes the polymer matrix, leaving behind the “brown part”. This is all SiO2 nanoparticles in the shape of the final product. The structure is sintered and fused after exposure to 1,300°C. During the post-processing, the object undergoes isotropic shrinkage of approximately 30%. This can easily be compensated for by an appropriate upscale of the green part using UpNano’s software.

“This innovative production process we developed”, says Markus Lunzer, “is ideally suited for larger 3D–printed glass parts that require high-resolution and high-precision, in the fields of engineering, and chemical, medical or research applications.” Fused silica offers superior optical properties, along with biocompatibility as well as high chemical inertness and exceptional heat resistance, making it an ideal material for a vast range of applications. This new development marks a significant advancement in the potential of 2PP 3D printing, following UpNano’s recent success in advancing the material testing of 2PP 3D–printed parts using UpNano printers and resins for macroscopic test specimens. In addition, the company’s printers have recently been used to achieve a significant milestone in 2PP 3D-printing by producing holistic embedded microfluidic chips as well as tungsten and platinum microstructures with (sub-)μm resolution.

The production of fused silica objects by 2PP 3D printing was a joint development between UpNano and Glassomer. The German company has previously enabled the production of fused silica objects by employing technologies such as soft lithography, injection molding, as well as conventional 3D-printing. Now, the joint material development from UpNano and Glassomer also allows the use of high-precision 2PP 3D-printing to produce fused silica objects.

…WITH INNOVATION CAPITAL
This series of developments exemplifies UpNano’s innovation capital in the highly competitive 2PP 3D-printer market, complemented by the continued and growing commercial success of the NanoOne printer range. In fact, sales in 2023 were up 57% on the previous year and customers are now served on five continents. All NanoOne printers are equipped with patented adaptive resolution technology, which allows the laser beam to be expanded by a factor of 10 for any given objective. A recent software update has enabled seamless stitching, and given all the available modules, the NanoOne range of printers now is considered the most versatile and fastest 2PP 3D-printer on the market. “The speed, resolution, and versatility of our printers make them powerful tools for the mass production of highly precise parts. Our ever-expanding range of materials extends the range of applications. In due course, we will also expand the range of services we offer”, adds Bernhard Küenburg, UpNano´s CEO.

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ASMPT, the market and innovation leader in SMT manufacturing technology, has added two new features to its proven DEK printing platforms that automate solder paste transfers and simplify squeegee changes.

ASMPT covers almost the entire SMT manufacturing process with its extensive product portfolio and is continuously working to further automate and simplify the various workflows. “Solder paste printing, which is already the most error-prone process in SMT production, still has many steps that must be done by hand,” explains Rick Goldsmith, Director Product Management at ASMPT. “Finding suitable people for these activities is becoming increasingly difficult, which is why our customers are asking for solutions that reduce personnel and material costs as well as error rates.”

When the printer setup needs to be changed, the solder paste that remains on the old stencil needs to be transferred to the new one. “Until now, this was done manually with a spatula,” explains Goldsmith. “In most cases, some of the paste remained on the old stencil and was not fully transferred to the new one. In addition, there was always the risk that the paste would get contaminated or wind up in the wrong place, leading to short circuits and malfunctions.”

The new paste transfer unit for the DEK TQ simplifies this process. The paste gets transferred automatically during each stencil change, provided the process parameters permit this. To do this, the squeegee pushes the paste to a transfer unit, from which it gets applied to the new stencil. Next, the system uses the understencil cleaning system to clean off any paste residue.

“This fully automatic paste transfer relieves the already scarce operators,” says Goldsmith. “It works faster, more precisely and more efficiently than would be possible by hand. With the manual process, up to 10 percent of the paste remains on the stencil. Our automated paste transfer system reduces this to 5 percent. This will represent a significant cost saving in solder paste, reducing manufacturing cost per PCB.” The new paste transfer system can be easily installed on all DEK TQ-series solder paste printers.

ASMPT has also improved the squeegee changeover process on its solder paste printers. “Previously, the squeegee was affixed with two thumbscrews,” explains Goldsmith. “To change the squeegee, the operator had to loosen and then tighten them again – a time-consuming process that often caused problems, for example, when someone tightened the thumbscrews too firmly and another operator was unable to loosen them. The time factor was also significant, because 20 changeovers over a 24-hour period are not uncommon.”

A new holder makes these changeovers much easier because the squeegee is automatically unlocked when it is removed out of the machine. It can then be switched out in a single step before the bracket locks automatically as the squeegee is retracted. This reduces the changeover time by up to 50 percent. In addition, a mechanical coding system prevents the incorrect insertion of squeegees. Quick Change Squeegee can be retrofitted in a few hours and is available for both the DEK TQ and the NeoHorizon platforms.

“Competition is getting tougher all the time in SMT manufacturing,” says Goldsmith. “To be successful in this field, you must continuously automate and streamline your operations. At ASMPT, we understand the challenges SMT manufacturers face and are able to offer our customers interesting solutions that provide them with tangible competitive advantages.”

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The University of Aalborg, Denmark, has been honored for advancements in Harbor Safety Technology through a collaborative project with Milestone Systems. Specifically, video technology and synthetic datasets deployed in a Danish harbor were recently awarded the prestigious Danish Spar Nord Foundation Research Award for research into detecting fatal accidents in harbors using Artificial Intelligence (AI)-trained models for thermal cameras.

Milestone Systems, a leading provider of video technology, announced that the award-winning research project furthers the AI capabilities of thermal cameras and Milestone’s video technology software to monitor and assess unusual behavior and enhance safety in harbors around the world.

Every year 236,000 people drown around the world. In Denmark, the harbors have witnessed numerous drowning incidents over the years, with 1,647 lives lost between 2001 and 2015. A quarter of these tragedies occurred in the harbors themselves. Identifying a clear need to prevent such accidents, a research team at The University of Aalborg leveraged AI combined with video technology to enhance safety in one of Denmark’s busiest ports, Aalborg Harbor. In doing so, they created the largest outdoor thermal dataset for video analytics, covering a nine-month period.

The action of people falling into a harbor is a specific activity that cannot be easily, or ethically, replicated in the real world. Volunteers cannot be asked to fall into the water for safety reasons. Using a combination of a test-dummy filled with warm water detectable by thermal cameras and the largest published collection of annotated thermal images, AI models were trained to promptly detect and alert rescue teams if a person fell into the harbor.

The research team created an advanced synthetic dataset that could effectively train the AI models in the sudden, involuntary movements involved in falling. The training data was expanded to include wheelchair users, skaters, and bicycle riders, to provide as many scenarios of different people falling as possible for the AI model.

“By knowing the normal behavior on the waterfront, the model can detect abnormal events such as a person falling off the dock and immediately trigger an alarm. This way, rescue personnel can be called out quickly – even in cases where the accident occurs without witnesses,” explained lead researcher and Ph.D. student, Neelu Madan, The University of Aalborg.

As well as saving lives, Neelu Madan’s award-winning research demonstrates the power of synthetic data used to train AI models in scenarios that are difficult or unsafe to replicate in the real world. According to Neelu, the same model has applications in other situations. For example, it could be used by manufacturing companies to improve production processes.

“During manufacturing, for instance, it is crucial that automated processes proceed as they should. If not, the final product may end up with undetected errors that can be expensive in many ways, not least financially,” she stated.

Combining AI and video technology is making harbors safer and redefining safety standards across the transportation sector – ultimately saving countless lives in years to come as it is adopted on a global scale. The research which is based on a partnership between The University of Aalborg and Milestone Systems has demonstrated the possibilities of combining video technology software and AI to benefit the broader society.

“We are incredibly proud of Neelu and excited about the potential application of her work. The development of the thermal dataset by The University of Aalborg and Milestone Systems at Aalborg Harbor represents a groundbreaking step forward in video technology, providing the community with the largest annotated thermal dataset,” said Rahul Yadav, Chief Technology Officer, Milestone Systems.

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Finding appropriate methods of cooling electronics allows engineers, designers and other professionals to prioritize sustainability by finding solutions that will make the products last longer and become more energy efficient.

Passive techniques are popular because they are usually less expensive and more reliable than active ones because there are no fans or other moving parts to break. What have researchers explored, and how can their findings improve future electronics designs?

Applying hot spot reducing methods

Graphene is a material known for being extraordinarily strong yet lightweight. Those studying it have also learned it can conduct and dissipate heat efficiently, leading engineers to want to learn more about its capabilities as a passive cooling mechanism in electronics.

One example associated with a European Union-funded project comes from Swedish startup Tenutec, which uses graphene as additives or multilayered films for passive cooling in electronics. The company stands out from others with its sustainable manufacturing method. It enables graphene production with a carbon footprint of only 0.85 kilograms of CO2 equivalents per kilogram. That is several hundred times less carbon-intensive than other well-established methods.

Figure 1 The use of graphene as additives or multilayered films has significant merits in passive cooling. Source: Tenutec

Additionally, its technique enables dispersion of graphene into one to three layers without harmful chemicals. Because the venture’s passive cooling methods eliminate hot spots in electronics, they also improve sustainability by lengthening products’ life spans.

This passive cooling work began during research at Sweden’s Chalmers University of Technology. Researchers developed and improved their graphene production method there, eventually realizing that the current market conditions and consumer demands made the technique marketable.

Regardless of the precise innovations applied, many electronics manufacturers want compact and effective solutions with the accompanying data to prove their worth. Another hot spot-eliminating technology can dissipate heat at levels of 1,000 watts per square centimeter, making it a good solution for devices’ power components.

Whether professionals use graphene sheets or alternatives to keep their devices at the right temperature, potential users will want assurances of effectiveness.

Improving performance of metal-organic frameworks

Numerous improvements in passive cooling options for electronics involve metal-organic frameworks (MOFs)—porous materials that pull water vapor from the air. However, they typically have low thermal conductivity. One research team sought to improve that characteristic by using a water adsorption process to control interfacial heat transfers from contacted surfaces to MOFs.

Figure 2 Metal-organic frameworks (MOFs) are porous materials that pull water vapor from the air. Source: IntechOpen

This group applied simulations and comprehensive measurements during their approach to determine its effectiveness. The results indicated that the water adsorption method made the interfacial thermal conductance approximately 7.1 times better than the MOFs performed without them.

The researchers also concluded that adsorbed water molecules within the MOFs formed dense channels, creating thermal pathways that moved heat away from the hot surfaces. They determined this cooling innovation created a sustainable way to regulate temperatures in electronics and other critical devices while simultaneously expanding possibilities that use MOFs for passive cooling.

Supporting sustainability while keeping electronics cool

Even as consumers use electronics on daily basis, many are increasingly concerned about the waste generated when those products stop working or get discarded. Similarly, they want manufacturers to offer solutions that work well while reducing environmental burdens.

Passive cooling technologies are central to these demands because electronics must exhibit adequate thermal management capabilities. Overheating can shorten their life spans and endanger users. However, when strategies meet sustainability needs while maintaining effectiveness, consumers and designers reap the benefits.

Ellie Gabel is a freelance writer as well as associate editor at Revolutionized.

Related Content

• Graphene composite beats copper for cooling chip
• European Data Center Cooling Startups Gain Ground
• Quickly estimate an electronic system’s cooling requirements
• Dutch Liquid Cooling Startup ‘Turbocharges’ Gigabyte Servers
• Ultra-compact computer systems rely on passive cooling techniques

The post How passive cooling advances electronics sustainability appeared first on EDN.

Semiconductors are the essential component fueling the growth of industries such as automotive, renewable energy, communications, information technology, defense, and consumer electronics. The rise of their importance began in the late 1950s when Jack Kirby and Robert Noyce invented integrated circuits (IC), which built electronic components and circuits on a common semiconductor base. ICs quickly replaced vacuum tube-based electronic equipment because they were more power efficient, saved space, and more reliable.

Over the past six decades, ICs have advanced significantly and are used in many industries as they are critical components in numerous products and processes. ICs can be multiple discrete components packaged together, such as digital logic circuits, microcontrollers, microprocessors, digital memory storage, analog circuits and amplifiers, radio frequency (RF) / microwave (MW) analog components and circuits, and integrated power circuits. This article focuses on using waveform generators to test various types of ICs.

IC design and testing are complex processes involving precision and expertise to meet required specifications. Engineers engage in iterations, optimizations, and validations to ensure the final IC achieves the desired performance and reliability. In Figure 1, the process begins with software modeling and simulation based on IC specifications. Subsequently, the design is etched onto a photomask and transferred to a silicon wafer during the wafer foundry stage. After wafer testing, the ICs are packaged and undergo functional testing to ensure they function correctly.

Figure 1 The IC design and test process flow including IC design and simulation, wafer processing, parametric testing, lead frame/wire bonding, package testing, and ending with functional test. Source: Keysight

During the design or front-end IC manufacturing stage, the ICs tend to be tested at the wafer level. Testing ICs at the upstream wafer-level process can be challenging, especially when using wafer-probing tools. However, it is necessary because the packaging process is costly and complex. Figure 2 shows wafer probing and testing in progress.

Figure 2 Wafer-level IC probing and testing where basic functional verifications can be performed such as catastrophic shorting, leakage, power supply, and general input / output conditions. Source: Keysight

At the wafer level, you can perform tests for basic function verifications such as catastrophic shorting, leakage, power supply, and general input / output conditions. Signal sources can come from programmable DC power supplies, source and measure units, and general-purpose waveform generators.

During the IC design stage, test engineers can perform noise, DC parametric, and S-parameter characterization work at wafer-level probing tests. This process drastically reduces the time to the first measurement and provides accurate and repeatable device and component characterization.

After the ICs are placed on lead frames, wire-bonded to their respective leads and encapsulated, they are in their final physical form. Tests are conducted to ensure that the packaged ICs meet packaging expectations, such as no short circuits, open or weak connections, proper electrical isolation between internal circuits, and more.

Waveform generators provide clean signals and controlled frequency and amplitude noise levels for signal integrity and low-frequency noise tests. Figure 3 shows how waveform generators can provide controlled simulated signals into ICs for an oscilloscope to test signal integrity.

Figure 3 The eye diagram of an IC signal integrity test where waveform generators can provide clean signals and controlled frequency and amplitude noise levels. Source: Keysight

Post-packaging functional testing, also known as end-of-line testing, is often complex and tedious. This process is the last testing stage, during which the ICs are extensively tested to ensure they meet specified performance and quality standards before they are shipped to customers.

Waveform generators generate complex variable patterns, real-world signals, and even extreme use-case signals to ensure that all ICs shipped meet the required performance specifications and functionality. Modern waveform generators are versatile in generating all kinds of signals, such as digital, analog, complex modulated, low to high frequency, burst, synchronized, and arbitrary waveform signals for all IC applications.

Waveform generators on the market have a wide range of specifications. Testing and characterizing ICs requires stringent specifications. IC design engineers need a source that produces a clean, low-distortion, stable, and reliable signal. The signal generated should not vary regardless of frequency or sample rate. Furthermore, certain waveform generator specifications for IC testing are important.

A clean signal source provides true and unadulterated signals without noise or interference from other foreign signals. The signals are measurable by the purity of a signal void of harmonic distortions and jitter. A clean and stable signal is necessary when testing ICs because engineers want:

• The best product specification: ICs require precise and accurate signals to characterize and validate their functions and performances. The more errors introduced from the signal source, the more degraded the product specification becomes due to measurement uncertainties.
• To avoid false test results: A stable signal source creates a consistent test process. Consequently, the test results can accurately characterize the behavior of the ICs. If the signal source is unstable, problems such as false test results affect downstream tests. Shipping the incorrectly characterized product to customers is the worst-case scenario.
• Repeatable and reliable performance: Clean signals will also provide optimized repeatability test conditions to gauge the true performance of ICs. They will not have unwanted harmonics and noise, rendering test results inaccurate. Furthermore, a test can be made more reliable by replacing a real-world signal with a signal created by a waveform generator.

Besides having clean signals to characterize the performance of IC devices, adding noise to test signals simulates real-world noisy transmission, crosstalk, and EMI. Instead of getting the best product performance specifications, adding noise stresses the IC under test and determines the robustness of the products.

Suitable waveform generators can produce variable noise bandwidth to control the frequency content of the test signal. Figure 4 illustrates that this approach enables controlled stress testing of the ICs under test.

Figure 4 Adding controlled noise into a test signal (top image) results in a noisy ECG signal (bottom image). Source: Keysight

Many applications require mixed-signal ICs, which are essentially ICs with digital and analog circuits built-in and packaged together. Applications that use mixed-signal ICs include analog-to-digital converters, digital-to-analog converters, power management circuits, microcontroller circuits, and physical parameter sensing measurements such as temperature, humidity, and pressure. Waveform generators can simulate both digital and analog signals to test mixed-signal ICs.

Modern waveform generators can generate arbitrary waveforms to simulate real IC test applications. These generators usually come with software applications that create arbitrary waveforms.

The most direct method for importing signals is digitizing a real-world test signal using an oscilloscope, saving it in a format that is readable with your software application, digitally manipulating or conditioning the test signal, and then transferring it to a waveform generator to regenerate the signal.

Another common method is to use waveform builder software to generate custom arbitrary waveforms and combining them into the desired simulated test signal. Some IC design engineers may want to generate the waveforms directly in MATLAB or Python programming and transfer those waveforms to the waveform generators. For example, Figure 5 shows how MATLAB understands the plotting of a complex waveform. The waveform is a simulation of a section of an electrocardiograph (ECG) heart signal showing part of the PQRST points. In fact, this waveform shows only the RST points for the purpose of creating a T-wave rejection test waveform. MATLAB can model waveforms using math equations and translate all these points into a complex ECG test signal.

Figure 5 Using math equations, assembling into a simulated cardio ECG test signal in MATLAB. Source: Keysight

Figure 6 shows the output of a cardio ECG test signal generated from MATLAB. The MATLAB software application offers options to send waveform points as a binary block to an arbitrary waveform function generator. The reason for sending a waveform as binary data rather than ASCII data is simple—the binary data is much smaller than the equivalent ASCII data.

Figure 6 MATLAB can transfer the above-simulated cardio ECG test signal into a waveform generator. Source: Keysight

These methods enable engineers to create the desired test signals for cataloging and storing in digital waveform libraries. This approach enables consistent and organized testing for many types of IC test applications.

Most modern waveform generators can play various segments of waveforms in sequence. Design engineers can build a playlist of test sequences with waveforms of incremental changes or good or bad signals to test the IC responses. Depending on your waveform generator’s capabilities, you can combine individual arbitrary waveform segments into user-defined lists or sequences to form longer, more complex waveforms.

Waveform generators are versatile test instruments essential throughout IC design and manufacturing processes. They can generate all kinds of signals, such as digital, analog, complex modulated, low to high frequency, burst, synchronized, and arbitrary waveform signals, for many types of IC applications.

Designers can take advantage of the powerful capabilities of waveform generators to create clean and stable signals as well as to control IC stress testing by adding incremental noise content to the test signals. Waveform generators can also generate all kinds of arbitrary waveforms to simulate real IC test applications, this is critical as ICs are getting smaller and integrate more complex functions.

Bernard Ang has been with Keysight Technologies (previously Hewlett Packard and Agilent Technologies) for more than 30 years. Bernard held roles in manufacturing test engineering, product engineering, product line management, product development management, product support management, and product marketing. He is currently a product marketer focusing on data acquisition systems, digital multimeters, and education product solutions. Bernard received his Bachelor of Electrical Engineering from Southern Illinois University, Carbondale, Illinois. 

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Company will be primary provider of fully optimized power system solution based on onsemi’s latest generation EliteSiC M3e platform

• onsemi and Volkswagen Group sign multi-year deal to supply solution for vehicle lineup across several brands
• onsemi will provide a full stack of silicon carbide technologies as part of an integrated module solution that can scale across all power platforms
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According to the wisdom of French philosopher Jean-Baptiste Alphonse Karr, “Plus ça change, plus c’est la même chose,” or “The more things change, the more they stay the same.” This adage holds significant relevance in the fast-paced world of the semiconductor industry. Currently, the industry is undergoing a profound technological shift fueled by diverse applications that mandate intricate custom chip designs.

Ground-breaking technologies such as artificial intelligence (AI), autonomous vehicles, edge processing and chiplets are triggering an avalanche of advancements in the semiconductor market. Pioneering technologies are paving the way for high-growth markets, maintaining a competitive edge for products and driving the demand for increasingly sophisticated systems-on-chips (SoCs) to power burgeoning applications.

As a result of design complexity and market competition, innovative chip development strategies have become essential for expedited market entry and revenue growth. Tapping into these technological advances is a strategic imperative to secure market leadership.

The established hybrid design landscape

Over the past two decades, OEMs, Tier 1 suppliers and system designers have embraced a hybrid chip design model, predominantly operating independently. These companies frequently resort to customer-owned tooling (COT) for chip design, subsequently engaging with back-end services companies and wafer production management teams.

The COT model necessitates the recruitment of specialized semiconductor engineers from various disciplines for SoC development—a challenging feat due to the scarcity and steep cost of engineers. To address this need, companies often outsource talent to help manage temporary workload peaks and meet specific skillset demands. However, this workaround may not lead to forming a permanent, skilled team.

Large enterprises and startup companies alike must pay closer attention to the severe financial implications of design errors, which can sabotage budgets and delay market entry. In a recent study, a leading EDA firm reveals that over 60% of all first-time designs require a silicon re-spin. With millions of dollars of NRE on the line each time, plus the cost of delayed time to market, the rising complexity in chip design significantly amplifies the risk of errors, making any mistake potentially career-ending.

Figure 1 A 2020 functional verification study conducted by Siemens EDA and Wilson Research Group shows only 32% of 2020’s designs claimed first-silicon success.

Against this backdrop, the tech landscape continues to experience growth from venture capital-backed startups, particularly in the AI realm. These agile companies often utilize the COT model but face similar hurdles in designing distinctive, complex chips for their products. The technical expertise required to create sophisticated SoCs often exceeds their core competencies.

This underscores the need for experienced partners’ guidance throughout the chip design journey. Also, they frequently cannot source wafers directly from the industry’s leading foundry, TSMC, and instead are routed to a Value Chain Alliance (VCA) partner for mask creation and wafer production management.

These trends are driving a resurgence of ASIC design companies that now focus on “design and supply” services, offering a broad spectrum of technologies for customers to choose from. These firms possess the technical skills to guide customers in making informed selections of third-party IP and comprehend chiplet interconnect requirements, sophisticated SoC power management, 3D packaging, and more.

In short, this minimizes risk with new chip implementations and corresponding financial impacts. So, a new generation of ASIC companies with broad experience and stable engineering teams is emerging, capable of providing solid technology recommendations.

The imperative for a revamped model

Companies can preempt potential setbacks by collaborating with the new generation of ASIC design and supply firms that can manage the entire silicon development process. This necessity is spurring a reevaluation of chip design strategies. The quest for unique differentiation and shorter development cycles is moving companies toward a collaborative relationship with their ASIC design partners.

This shift signals the demand for a new paradigm where companies are seeking alternatives capable of supporting the complete chip ecosystem, from inception to delivery. Adopting an integrated ASIC design and supply model offers significant advantages over traditional ASIC houses and reduces the investment associated with COT models.

An integrated ASIC design and supply model involves cross-functional teams collaborating closely with customers to define the entire semiconductor development and manufacturing process, including packaging, final testing and product lifecycle management.

Today’s SoCs are intricate, multi-billion-transistor devices custom-built for specific applications. The cost of developing such high-end chips can easily exceed $50 million, with the photomask set alone at advanced process nodes ranging from $10 million to $20 million. A collaboration with a technologically advanced, single-source ASIC design house can expedite chip development and help ensure first-time silicon success.

Figure 2 A single-source ASIC design house can expedite chip development and help ensure first-time silicon success. Source: Sondrel

Rich Wawrzyniak, principal analyst for The SHD Group, emphasizes the growing importance of ASIC-class services by stating, “In today’s complex technological landscape, ASIC-class services have become an essential part of the equation for handling advanced semiconductor design implementations.”

In the face of rapidly evolving technologies and the pressure to accelerate time to market, partnering with a single-source ASIC design and supply company appears increasingly beneficial. With its specialization in managing the entire chip development process, such a company can help chip designers architect their future and secure a competitive advantage.

Ian Walsh, Sondrel’s regional VP for America, is based in the company’s U.S. office in Santa Clara, California.

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Disclosure of Transactions in Own Shares – Period from Jul 15, 2024 to Jul 19, 2024

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announces full details of its common share repurchase program (the “Program”) disclosed via a press release dated June 21, 2024. The Program was approved by a shareholder resolution dated May 22, 2024 and by the supervisory board.

STMicroelectronics N.V. (registered with the trade register under number 33194537) (LEI: 213800Z8NOHIKRI42W10) announces the repurchase (by a broker acting for the Company) on the regulated market of Euronext Paris, in the period between Jul 15, 2024 to Jul 19, 2024 (the “Period”), of 254,850 ordinary shares (equal to 0.03% of its issued share capital) at the weighted average purchase price per share of EUR 38.2047 and for an overall price of EUR 9,736,472.80.

The purpose of these transactions under article 5(2) of Regulation (EU) 596/2014 (the Market Abuse Regulation) was to meet obligations arising from share option programmes, or other allocations of shares, to employees or to members of the administrative, management or supervisory bodies of the issuer or of an associate company.

The shares may be held in treasury prior to being used for such purpose and, to the extent that they are not ultimately needed for such purpose, they may be used for any other lawful purpose under article 5(2) of the Market Abuse Regulation.

Below is a summary of the repurchase transactions made in the course of the Period in relation to the ordinary shares of STMicroelectronics (ISIN: NL0000226223), in detailed form. 

Transactions in Period

Following the share buybacks detailed above, the Company holds in total 8,767,667 treasury shares, which represents approximately 1.0% of the Company’s issued share capital.

In accordance with Article 5(1)(b) of the Market Abuse Regulation and Article 2(3) of Commission Delegated Regulation (EU) 2016/1052, a full breakdown of the individual trades in the Program are disclosed on the ST website (https://investors.st.com/stock-and-bond-information/share-buyback).

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