ELE Times

Courtesy: Arrow Electronics

Artificial Intelligence has rapidly become an innovative driver across industries, enabling everything from autonomous vehicle development to real-time healthcare diagnostics. However, as AI models grow in both complexity and scale, power and thermal management concerns are also rising. Companies must meet and overcome these challenges to help ensure sustainable and efficient AI operations.

Why Power and Thermal Management Matter in AI

AI systems are, at their core, computationally intensive and require large amounts of processing power to train and deploy models effectively. This intense compute power results in increasing amounts of energy consumption and heat. Without addressing these issues, organizations are at risk of:

1. System Overheating: Excessive heat can degrade hardware performance, cause unexpected failures, and shorten the lifespan of critical infrastructure.
2. Operational Inefficiencies: Ineffective cooling strategies lead to higher energy costs, increased maintenance needs, and reduced system reliability.
3. Environmental Impact: Escalating energy consumption increases carbon footprints, counteracting sustainability goals and regulatory requirements.

The Scope of Power and Thermal Challenges

While AI is fundamentally a compute-heavy task, recent trends exacerbate heat and thermal concerns for artificial intelligence systems. Some of these trends include:

• Growing Compute Density: As AI models become larger and more complex, data centers must meet rack densities exceeding 50kW—a significant jump from traditional capacities.
• Edge Deployments: Deploying AI at the edge requires compact, energy-efficient systems that can handle extreme environmental conditions while still performing at high levels.
• Diverse Workloads: AI includes applications such as computer vision, NLP, and generative models, each with its own unique performance and cooling needs.

These challenges require a combination of advanced technologies and strategic planning to maintain performance and sustainability.

Strategies for Addressing Thermal Challenges

Liquid Cooling

While liquid cooling is not a new concept, it has seen rapid growth and adoption to combat heat and thermal issues in AI systems, especially at the edge. Unlike traditional air-based systems, liquid cooling directly removes heat from critical components, offering:

• Improved Efficiency: Direct-to-chip cooling systems enhance heat dissipation, allowing servers to handle workloads exceeding 50kW per rack without compromising reliability.
• Scalability: Liquid cooling is suitable for data centers, edge deployments, and hybrid environments and supports the growing compute density required for AI applications.
• Sustainability: Reduced reliance on energy-intensive air-cooling systems contributes to lower carbon emissions and aligns with environmental regulations.

Arrow’s Intelligent Solutions business works with leading vendors and leverages advanced liquid cooling technologies, such as rear-door heat exchangers and immersion cooling, to provide tailored solutions that address the specific needs of OEMs and ISVs. These solutions enhance system stability, extend lifespan, and significantly lower energy consumption.

Innovations in Passive Cooling

In addition to active cooling systems, advancements in passive cooling techniques, such as optimized airflow management and heat pipe technology, are becoming increasingly relevant. Heat pipe cooling, in particular, offers numerous advantages for AI systems, including exceptional thermal efficiency, uniform heat distribution across the system, minimal maintenance needs, a lightweight design, and effective cooling for high-density computing components.

The Role of Right-Sized Computing

As seen in Ampere’s innovative GPU-free AI inference solutions, right-sized computing aligns hardware capabilities with workload requirements. This approach minimizes energy waste and reduces costs and operational complexity. Ampere’s cloud-native processors, for instance, deliver:

• Enhanced Efficiency: Up to 6.4x greater AI inference performance compared to traditional systems.
• Lower Power Consumption: Optimized for sustainability, these processors allow organizations to achieve more with less energy.
• Broad Application Support: Ampere’s solutions excel across diverse AI workloads from computer vision to natural language processing.

Integrating Ampere’s technology with Arrow’s thermal management expertise helps ensure that customers receive end-to-end solutions optimized for performance, cost, and sustainability.

Holistic Approaches to AI Deployment

In addition to hardware choice and usage strategies, more comprehensive approaches to AI deployment can help mitigate concerns over these systems’ significant energy usage and heat generation and their general sustainability.

Predictive Maintenance

Predictive maintenance tools can monitor system performance, identify potential thermal issues before they escalate, and reduce downtime. Our engineering team can help develop comprehensive maintenance frameworks that leverage machine learning for operational continuity.

Energy-Efficient Architectures

Transitioning to energy-efficient architectures, such as those based on ARM or custom-designed accelerators, can significantly reduce power consumption. Our ecosystem of cutting-edge suppliers enables OEMs to access these transformative technologies.

Lifecycle Management

Lifecycle management is critical for achieving sustainable AI deployments. Strategies such as hardware recycling, second-life battery integration, and modular system upgrades can extend the usability of AI infrastructure while minimizing waste.

Moving Towards Sustainable AI Deployment

Beyond addressing immediate thermal and power challenges, OEMs must focus on long-term sustainability. Strategies include:

• Integrated Design Approaches: Collaborating across hardware, software, and cooling technology providers to create cohesive systems that meet evolving demands.
• Regulatory Compliance: Adhering to emerging global standards for energy efficiency and environmental responsibility.
• Customer Education: Empowering end-users with tools and knowledge to optimize their AI deployments sustainably.

Arrow is at the forefront of these efforts, providing OEMs with the tools and expertise to navigate the complexities of power and thermal management in AI. By leveraging our network of robust technology collaborations, engineering expertise, and a commitment to innovation, Arrow’s Intelligent Solutions business helps organizations stay ahead in the race for sustainable AI solutions.

Conclusion

The demands of AI are pushing the boundaries of power and thermal management, but solutions like liquid cooling, passive cooling innovations, and right-sized computing are paving the way for a more sustainable future.

In collaboration with cutting-edge technology providers, Arrow helps you build a comprehensive strategy that balances performance, cost, and environmental responsibility. With these tactics, organizations can deploy their AI solutions in an efficient, reliable, and scalable way.

The post Power and Thermal Management Concerns in AI: Challenges and Solutions appeared first on ELE Times.

Infineon Technologies AG bolsters its global and regional market leadership positions in automotive semiconductors, including its very strong position in microcontrollers. According to the latest market research from TechInsights , Infineon achieved a market share of 13.5 percent in the global automotive semiconductor market in 2024. In Europe, the company climbed to the top spot with a 14.1 percent market share, up from second in 2023.

Infineon also strengthened its presence in North America to the second largest market participant with a 10.4 percent share, rising from last year’s number three position. The global market share in microcontrollers rose again, to 32.0 percent, increasing the lead over the second-placed competitor by 2.7 percentage points.

Furthermore, Infineon maintained its leading market positions in the largest market for automotive semiconductors, China, with a 13.9 percent market share as well as in South Korea with a 17.7 percent market share. In Japan, the company confirmed its strong second place with a share of 13.2 percent. In total, the global automotive semiconductor market accounted for US$ 68.4 billion in 2024 – a slight decline of 1.2 percent compared to US$ 69.2 billion in 2023.

“We are the global number one in automotive semiconductors for the fifth consecutive year and we are equally successful across the world. For the first time in our history, Infineon is among the top two automotive semiconductor companies in every region,” said Peter Schaefer, Executive Vice President and Chief Sales Officer Automotive at Infineon. “This global success is a token of our strong product portfolio, outstanding customer support and our dedication to the specific needs of our customers.”

Infineon’s semiconductors are essential in driving the digitalization and decarbonization of vehicles to make them clean, safe and smart. They serve all major automotive applications such as driver assistance and safety systems, powertrain and battery management as well as comfort and infotainment features. A key focus is to support the evolution of electrical/electronic vehicle architectures towards more centralized zonal designs as the basis for software-defined vehicles. This requires state-of-the-art connectivity and data security, smart power distribution and real-time computing power.

“It is the fifth time in a row that the ‘TechInsights Automotive Semiconductor Vendor Market Share Ranking’ confirms the Infineon lead, with microcontrollers largely contributing to this success,” said Asif Anwar, Executive Director of Automotive End Market Research at TechInsights. “Semiconductors for advanced driver assistance systems, especially SoCs and memories, were among the best performing product categories. Infineon did exceptionally well in microcontrollers used in advanced driver assistance systems and many other applications. With an increase of 3.6 percentage points to a 32.0 percent market share, Infineon has held up well in the automotive microcontroller market, which decreased by 8.2 percent year-over-year.” TechInsights, “2024 Automotive Semiconductor Vendor Market Share”, March 2025.

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Author : Saleem Ahmed, Officiating Head, ESSCI

India is undergoing a significant transformation in its transportation sector, with electric vehicles at the forefront of this revolution. The government’s proactive initiatives, such as the Faster Adoption and Manufacturing of Electric Vehicles scheme and the Production Linked Incentive program for Advanced Chemistry Cell battery manufacturing, underscore a strong commitment to sustainable mobility. These efforts aim to achieve a 30% EV market share by 2030, a goal that necessitates a highly skilled workforce proficient in battery technology and e-mobility systems.

ESSCI’s Targeted Training Programs for E-Mobility

To address the burgeoning demand for skilled professionals in the EV sector, the Electronics Sector Skills Council of India has developed specialized training programs. These programs are meticulously designed to equip learners with industry-relevant expertise, preparing them for roles in manufacturing, design, and maintenance within the e-mobility ecosystem.
One of ESSCI’s flagship qualifications is the Battery System Assembly Operator (ELE/Q6604) program.

This course focuses on training individuals in the precise assembly of battery packs, emphasizing a comprehensive understanding of battery construction, adherence to safety protocols, and stringent quality control measures. Given that battery packs constitute a significant portion of an EV’s total cost, their proper assembly is crucial for both performance and affordability.For those inclined towards innovation and design, the Battery System Design Engineer (ELE/Q6701) qualification offers a robust foundation in battery architecture, chemistry, and optimization techniques.

Participants are trained to develop high-performance energy storage systems that enhance efficiency, extend battery lifespan, and minimize environmental impact. As India progresses towards advanced battery technologies, expertise in battery design becomes indispensable for realizing the nation’s e-mobility objectives.

Equally vital to the EV ecosystem is the Battery System Repair Technician (ELE/Q7001) program. This course concentrates on diagnosing, troubleshooting, and repairing battery systems. As battery degradation over time can affect vehicle performance and range, skilled repair technicians are essential to sustaining India’s EV adoption. The program ensures that professionals are proficient in battery diagnostics, cell balancing, thermal management, and safety protocols—skills that are increasingly in demand as India’s EV repair and servicing sector expands.

Collaborations and Industry Integration

To enhance practical learning, ESSCI collaborates with industry leaders and academic institutions, ensuring that its training programs align with the latest technological advancements and market demands. A notable initiative is ESSCI’s partnership with ABB India, which led to the establishment of a Smart Electrician Training Centre in Faridabad, Haryana. This center provides hands-on training in modern electrical systems, smart grid technologies, and EV charging infrastructure, equipping technicians with real-world expertise.

Additionally, ESSCI actively engages with automotive manufacturers, battery producers, and energy storage companies to integrate their insights into curriculum development. Collaborations with companies involved in lithium-ion battery manufacturing, battery recycling, and charging infrastructure development ensure that the training programs remain pertinent to industry needs. These partnerships also facilitate job placements for trainees, bridging the gap between skill acquisition and employment.

Rising Demand for E-Mobility Professionals in India

The Indian EV market is experiencing exponential growth, with projections estimating a Compound Annual Growth Rate of 49% from 2022 to 2030.This surge is driven by supportive government policies, increasing environmental awareness, and technological advancements. The adoption of EVs is anticipated to generate approximately 5 million direct and indirect jobs in India by 2030, with a significant portion of these roles emerging in battery technology, EV servicing, and charging infrastructure.

Furthermore, the lithium-ion battery market in India is expected to reach substantial capacity by 2030, propelled by the escalating demand from the EV sector. This trend underscores the urgent need for skilled professionals capable of developing, maintaining, and optimizing battery systems for electric vehicles, energy storage solutions, and grid stabilization.

The Road Ahead: Preparing India’s Workforce for the E-Mobility Revolution

ESSCI’s emphasis on future-ready skill development is instrumental in India’s journey toward sustainable mobility. By aligning its training programs with evolving industry trends, ESSCI addresses the immediate demand for skilled professionals and prepares the next generation for long-term career opportunities in e-mobility and battery technology.

With continued government support, industry collaborations, and advancements in battery research, India is well-positioned to become a global leader in electric mobility. However, achieving this vision requires a robust skilling ecosystem that empowers individuals with the expertise needed to drive innovation and ensure the reliability of EV technology.

Through its specialized training initiatives, ESSCI is effectively bridging the skill gap, enhancing employability, and contributing to India’s clean energy goals. As the demand for battery engineers, EV service technicians, and energy storage specialists continues to rise, ESSCI’s programs will remain integral to shaping the future of e-mobility in India.

The post Empowering the Next Generation: ESSCI’s Role in Promoting E-Mobility and Battery Technology Skills appeared first on ELE Times.

Nuvoton Technology’s NuMicro MA35D1 is a high-performance, dual-core Arm Cortex-A35 microprocessor capable of running both RTOS and Linux simultaneously. In the latest application demonstration, it delivers instant boot-up within one second, real-time control, and versatile application support by leveraging the strengths of both operating systems.

Linux excels in networking, multimedia, and multitasking, offering rich software tools and broad hardware compatibility that simplifies integration, while RTOS ensures stable and predictable response times for real-time industrial control scenarios. To meet diverse application demands, the MA35D1 maximizes performance and efficiency, making it an ideal solution for industrial automation, AIoT applications, smart buildings, home appliances.

Key Features

• Dual-OS Support: Runs RTOS and Linux simultaneously for optimal performance in real-time applications.
• Instant Boot-Up: Instantly operational within 1 second for mission-critical applications.
• Immediate Data Processing: Rapid sensor data acquisition and LCD display updates.
• Enhanced UI Experience: Powered by Qt for MCUs, the UI provides high-quality and smooth user interface experience.
• Networking Features: Smart devices can connect to the built-in MA35D1 web server for real-time monitoring and remote control.

Technical Specifications

• Processor: Dual-core 64-bit Cortex-A35, 800 MHz and Cortex-M4
• Memory: Multi-chip package (MCP) DDR SDRAM up to 512 MB
• Security Features: Integrated Nuvoton Trusted Secure Island (TSI) to enhance system security
• Multimedia: JPEG/H.264 decoder, TFT-LCD resolution up to 1080p
• Connectivity: 2 sets of Gigabit Ethernet, high-speed USB, SDIO 3.0, 4 sets of CAN FD, and 16 sets of UART

The post Nuvoton NuMicro MA35D1 Microprocessor Dual-OS Solution: Revolutionizing Industrial Automation and AIoT Applications appeared first on ELE Times.

Courtesy: Keysight

6G aims to connect the physical, digital, and human worlds through emerging technology focusing on new spectrum utilization, artificial intelligence integration into networks and devices, digital twins, and new network architectures. These elements enhance network programmability and automation across various 6G use cases.

While the commercial deployment of 6G seems quite far away, the research needs for 6G are already here, including growing efforts around the spectrum. New frequency ranges are needed to satisfy the bandwidth needs of the ever-growing throughput requirements. Frequency range 3, or FR3, is one of the new spectrum ranges where 6G is evolving. There were only two frequency ranges for 5G: FR1 and FR2. FR3 is between FR1, often referred to as sub-6 GHz, and FR2, the so-called millimeter-wave range, between 7 and 24 GHz.

6G Requirements : A Drive Towards Deterministic Channel Models

4G and 5G addressed radio channel modeling requirements using geometry-based stochastic channel models (GSCMs) for simulating and testing massive multiple-input and multiple-output (mMIMO) systems. However, 6G use cases and technologies are generating new requirements for radio channel modeling because of:

• Near-field (NF) and short-range communications using smaller cells.
• The need for accurate location-based services.
• Smart environments with multiple radio access technologies.
• Propagation challenges at sub-terahertz (THz) frequencies.
• Flexible adaptation and enhanced environmental awareness.
• Integrated sensing and communication (ISAC) and extreme MIMO (xMIMO).

6G FR3 Radio Channel Modeling

Antenna arrays with substantial apertures are under investigation in the 6G FR3 band for MIMO technologies, including MIMO, mMIMO, and xMIMO. xMIMO antenna arrays support narrow pencil beams and more MIMO layers than conventional mMIMO. Figure 1 shows an example of extreme hybrid beamforming, FR3 upper mid-band base station. As a result, the design and validation of xMIMO wireless systems necessitate accurate intra- and inter-cluster angular characteristics from the channel model.

Figure 1. An example of extreme hybrid beamforming, FR3 upper mid-band base station

Ensuring that the channel model accurately captures the intra- and inter-cluster angular characteristics is essential when conducting system simulations or testing the actual performance of xMIMO base stations in RAN and Open RAN configurations. In addition, dynamic channel models are necessary for evaluating beam management and precoding adaptation over user equipment movement. These channel models consider transitions between line-of-sight / non-line-of-sight and blockage conditions.

However, the current 3GPP GSCM channel models lack the accuracy needed to develop extreme beamforming algorithms with highly directive pencil beams. To address that, a new 3GPP RP-234018 Release 19 technical study item on channel modeling enhancements for 7 to 24 GHz for New Radio (NR) was initiated.

To test the upper mid-band for FR3, test engineers need:

• Phase and time coherent multichannel emulation.
• Semi-deterministic and/or deterministic channel models.
• Accurately calibrated equipment for phase and amplitude measurements.
• Comprehensive measurement and analysis tools.

6G FR3 System Testing

6G FR3 system testing requires phase and time-coherent multichannel emulation using semi-deterministic and deterministic channel models. From the physical layer (PHY) to the application layer, key performance metrics for 6G FR3 testing include:

• Beam weight estimation and pointing metrics.
• Beam shape and gain.
• Sidelobe levels.

Figure 2. The three main channel modeling approaches necessary in 5G-Advanced and 6G system simulations, design, and product development and testing.

With a robust channel emulation solution, test engineers can reproduce a diverse propagation environment and emulate hardware impairments like phase noise and interference. They will need:

• Channel emulation capabilities to create realistic and highly accurate 6G FR3 environment models.
• Signal generation capabilities to provide the necessary 6G transmit waveform to the channel emulator.
• Performance metrics, including beamforming gain, beam width, and sidelobe levels.
• Software tools to perform phase and time-coherent multichannel emulation and create geometry-based stochastic channel models.
• Testing environment to reproduce propagation environments and ensure comprehensive testing.

The Keysight 6G FR3 system test solution

Keysight 6G FR3 system test solution includes a channel emulator, channel emulation software, and an MXG signal generator.This solution creates realistic and highly accurate stochastic and deterministic models for mimicking 6G FR3 components and systems. The MXG signal generator provides the signal input to the FR3-capable channel emulator. The channel emulator also supports ISAC for detecting and tracking objects.

Figure 3. The Keysight 6G FR3 system test solution The Bottom Line

Precise channel emulation is crucial for 6G FR3. Accurate channel models are needed to support advanced 6G features and allow for realistic testing of 6G technologies, such as mMIMO and beamforming, under various conditions to understand how these technologies will perform in real-world scenarios. Additionally, it supports advanced use cases like ISAC, which require detailed knowledge of the channel characteristics to function effectively.

Be prepared for 6G and the challenges it brings onboard and accelerate your 6G prototyping before releasing standards using Keysight solutions for channel modeling and emulation for FR3 MIMO, mMIMO, xMIMO, and ISAC.

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Courtesy: Nvidia

As quantum computers continue to develop, they will integrate with AI supercomputers to form accelerated quantum supercomputers capable of solving some of the world’s hardest problems.

Integrating quantum processing units into AI supercomputers is key for developing new applications, helping unlock breakthroughs critical to running future quantum hardware and enabling developments in quantum error correction and device control.

The NVIDIA Accelerated Quantum Research Center, or NVAQC, announced today at the NVIDIA GTC global AI conference, is where these developments will happen. With an NVIDIA GB200 NVL72 system and the NVIDIA Quantum-2 InfiniBand networking platform, the facility will house a supercomputer with 576 NVIDIA Blackwell GPUs dedicated to quantum computing research. “The NVAQC draws on much-needed and long-sought-after tools for scaling quantum computing to next-generation devices,” said Tim Costa, senior director of computer-aided engineering, quantum and CUDA-X at NVIDIA. “The center will be a place for large-scale simulations of quantum algorithms and hardware, tight integration of quantum processors, and both training and deployment of AI models for quantum.”

The NVAQC will host a GB200 NVL72 system.

Quantum computing innovators like Quantinuum, QuEra and Quantum Machines, along with academic partners from the Harvard Quantum Initiative and the Engineering Quantum Systems group at the MIT Center for Quantum Engineering, will work on projects with NVIDIA at the center to explore how AI supercomputing can accelerate the path toward quantum computing.

“The NVAQC is a powerful tool that will be instrumental in ushering in the next generation of research across the entire quantum ecosystem,” said William Oliver, professor of electrical engineering and computer science, and of physics, leader of the EQuS group and director of the MIT Center for Quantum Engineering. “NVIDIA is a critical partner for realizing useful quantum computing.”

There are several key quantum computing challenges where the NVAQC is already set to have a dramatic impact.

Protecting Qubits With AI Supercomputing

Qubit interactions are a double-edged sword. While qubits must interact with their surroundings to be controlled and measured, these same interactions are also a source of noise — unwanted disturbances that affect the accuracy of quantum calculations. Quantum algorithms can only work if the resulting noise is kept in check.

Quantum error correction provides a solution, encoding noiseless, logical qubits within many noisy, physical qubits. By processing the outputs from repeated measurements on these noisy qubits, it’s possible to identify, track and correct qubit errors — all without destroying the delicate quantum information needed by a computation.

The process of figuring out where errors occurred and what corrections to apply is called decoding. Decoding is an extremely difficult task that must be performed by a conventional computer within a narrow time frame to prevent noise from snowballing out of control.

A key goal of the NVAQC will be exploring how AI supercomputing can accelerate decoding. Studying how to collocate quantum hardware within the center will allow the development of low-latency, parallelized and AI-enhanced decoders, running on NVIDIA GB200 Grace Blackwell Superchips.The NVAQC will also tackle other challenges in quantum error correction. QuEra will work with NVIDIA to accelerate its search for new, improved quantum error correction codes, assessing the performance of candidate codes through demanding simulations of complex quantum circuits.

“The NVAQC will be an essential tool for discovering, testing and refining new quantum error correction codes and decoders capable of bringing the whole industry closer to useful quantum computing,” said Mikhail Lukin, Joshua and Beth Friedman University Professor at Harvard and a codirector of the Harvard Quantum Initiative.

Developing Applications for Accelerated Quantum Supercomputers

The majority of useful quantum algorithms draw equally from classical and quantum computing resources, ultimately requiring an accelerated quantum supercomputer that unifies both kinds of hardware.

For example, the output of classical supercomputers is often needed to prime quantum computations. The NVAQC provides the heterogeneous compute infrastructure needed for research on developing and improving such hybrid algorithms.

Accelerated quantum supercomputers will connect quantum and classical processors to execute hybrid algorithms.

New AI-based compilation techniques will also be explored at the NVAQC, with the potential to accelerate the runtime of all quantum algorithms, including through work with Quantinuum. Quantinuum will build on its previous integration work with NVIDIA, offering its hardware and emulators through the NVIDIA CUDA-Q platform. Users of CUDA-Q are currently offered access to Quantinuum’s System H1 QPU hardware and emulator for 90 days.

“We’re excited to collaborate with NVIDIA at this center,” said Rajeeb Hazra, president and CEO of Quantinuum. “By combining Quantinuum’s powerful quantum systems with NVIDIA’s cutting-edge accelerated computing, we’re pushing the boundaries of hybrid quantum-classical computing and unlocking exciting new possibilities.”

QPU Integration

Integrating quantum hardware with AI supercomputing is one of the major remaining hurdles on the path to running useful quantum hardware.

The requirements of such an integration can be extremely demanding. The decoding required by quantum error correction can only function if data from millions of qubits can be sent between quantum and classical hardware at ultralow latencies.

Quantum Machines will work with NVIDIA at the NVAQC to develop and hone new controller technologies supporting rapid, high-bandwidth interfaces between quantum processors and GB200 superchips.

“We’re excited to see NVIDIA’s growing commitment to accelerating the realization of useful quantum computers, providing researchers with the most advanced infrastructure to push the boundaries of quantum-classical computing,” said Itamar Sivan, CEO of Quantum Machines.

The NVIDIA DGX Quantum system comprises an NVIDIA GH200 superchip and Quantum Machines’ OPX1000 control system.

Key to integrating quantum and classical hardware is a platform that lets researchers and developers quickly shift context between these two disparate computing paradigms within a single application. The NVIDIA CUDA-Q platform will be the entry point for researchers to harness the NVAQC’s quantum-classical integration.

Building on tools like NVIDIA DGX Quantum — a reference architecture for integrating quantum and classical hardware — and CUDA-Q, the NVAQC is set to be an epicenter for next-generation developments in quantum computing, seeding the evolution of qubits into impactful quantum computers.

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Author: STMicroelectronics

ST has been serving customers in the automotive market for over 30 years and provides them with a range of products and solutions covering most applications in a typical vehicle. As the market has evolved, so has ST’s offering, a key part of which is automotive microcontrollers (MCUs).

ST pioneered embedded non-volatile memory (eNVM) with ST10 and then introduced automotive microcontrollers with its SPC5 range based on PowerPC architecture, shipping more than one billion MCUs in automotive. Cost-effective automotive controllers from the STM8 family complemented this offer.

ST’s Stellar Family

ST’s latest generation of automotive microcontrollers is the Stellar family, which is the industry’s first Arm®-based portfolio that spans the entire automotive MCU spectrum, from low-end to high-end solutions. These advanced microcontrollers reduce complexity, ensure safety and security, and deliver optimal performance and efficiency of next-gen vehicle architectures and features. Customers can benefit from shorter development times and focus on bringing innovation and differentiation for their software-defined vehicles (SDVs) in this highly competitive market. For these reasons Stellar products are gaining momentum, particularly among our customers in Asia and Europe.

Stellar is the industry’s first family of emerging technologies after eFlash, representing the most mature and smallest memory cell automotive grade solution on the market. The Stellar family is optimized for electrification, including X-in-1 vehicle motion control computing, new vehicle architectures, zonal and domains, and safety MCUs for safety-critical subsystems, such as ADAS.

It fully supports automotive transformation by integrating multiple functions safely into a single device and allowing the continuous integration of new features in vehicles. This is made possible with key technologies, including a right choice of core technology, virtualization, Ethernet support and ground-breaking memory technology embedded in the automotive MCUs–a game changer for customers faces challenges with application memory sizing.

Stellar MCUs are based on Arm® Cortex®-R52+ technology. This high-performance processor delivers real-time virtualization support for time-critical secure and safety systems. It can run multiple applications simultaneously with freedom from interference. And thanks to fully programmable auxiliary cores it is possible to accelerate specific functions, such as routing, low power management, digital filtering while offloading the main cores.

“As the driver experience continues to evolve in the age of AI and software-defined vehicles, advancing automotive functional safety, flexibility and real-time performance capabilities is essential,” said Dipti Vachani, senior vice president and general manager, Automotive Line of Business, Arm. “Built on Arm, the Stellar microcontroller family taps into the Arm compute platform’s advanced safety and real-time features, as well as the broad Arm software ecosystem. This enables car manufacturers to comply with strict safety regulations while implementing innovative features that keep them at the forefront of the automotive industry.”

Stellar MCUs enable the introduction of ethernet capabilities in vehicles and is the first ST MCU embedding an Ethernet switch. Thanks to Ethernet, data exchange is more efficient, and flexible, supporting the needed gigabit throughput, with a higher level of security. By supporting various in-vehicle communication topologies, such as Ethernet ring, automotive MCUs fulfill the promise of halving the length of the cross-car wiring cables and manufacturing costs.

Phase Change Memory is set to redefine what is possible in vehicle software

Stellar MCUs, with the embedded Phase Change Memory (PCM) technology and its flexibility, transform the process of Over-the-Air (OTA) updates. In the automotive industry, OTA updates are crucial for adding new features and safety or security patches without physical intervention. However, this flexibility often requires careful consideration of future memory needs, which can lead to increased costs and complex planning.

ST’s PCM innovation is no ordinary memory. Not only is it the industry’s smallest memory cell for automotive MCU, but it is pioneering a transformative breakthrough in automotive and set to redefine what is possible in vehicle software. Thanks to ST’s innovative PCM technology, memory capabilities are reaching a new level of sophistication. This is not just about memory performance. It is a forward-thinking solution that brings adaptability and lasting value to the automotive landscape enabling the final developers to continuously improve and upgrade functions.

As vehicles become increasingly software-defined, the ability to introduce new features and enhancements is essential. PCM’s groundbreaking technology will support the shift toward more adaptable, future-focused vehicles, giving automakers new ways to refine experiences as vehicles continue to advance.

Additionally, PCM delivers the ability to support uninterrupted OTA updates. PCM securely stores updates without impacting the vehicle’s current operations. Thanks to concurrent read and write capabilities, the new software download does not interfere with the application code already running on the MCU, ensuring continuous performance during the update process.

Stellar P, designed for the integration of multiple functions, and Stellar G, for the realization of Software-Defined Vehicles (SDV) zonal controllers, are two series leveraging ST’s internally developed eNVM. They are built on 28nm FD-SOI technology, allowing them to achieve maximum frequency with lower power consumption and enhanced radiation immunity. Stellar is the first 28nm product certified for functional safety and will enter production by the end of this year.

The Stellar family also enables the X-in-1 growing trend toward more affordable electromobility, with the decisive switch from fossil to electrically powered vehicles. X-in-1 powertrain solutions combine multiple components into a single ECU, allowing manufacturers to create efficient, compact, and cost-effective performing vehicles.

Stellar offers scalable X-in-1 implementation, accommodating a growing number of ECUs from low to high integration levels. This solution supports increasingly complex X-in-1 systems by providing enhanced availability of cores, analog components, and I/O capabilities.

“As a global leader in lithium-ion batteries, Sunwoda provides stable and reliable electronic system solutions for automotive suppliers worldwide. Our new collaboration with STMicroelectronics focuses on developing solutions using ST’s advanced Stellar microcontrollers and proprietary production processes, which primarily include battery management systems, and VDC/Zonal and body control functions. Together, we aim to provide intelligent solutions that enhance the next generation of energy vehicles in China and globally,” said Wang Mingwang, founder, Sunwoda.

STM32 microcontrollers to enter automotive

As part of the expanded roadmap for automotive MCUs, ST will introduce its market-leading general-purpose STM32 microcontroller platform to the automotive sector. The STM32 platform is well recognized for its cost optimization, simplicity, and reliability. Augmented with automotive grade quality and safety, STM32A will achieve up to ASIL B standards. This platform will be designed to handle edge actuation, from the simplest functions to more sophisticated single tasks, all at optimized costs. It will be particularly well-suited for applications like motor control in vehicle systems, including windows, mirrors, and roofs.

Best of industrial and automotive worlds: towards converged future

Over time, the convergence of the industrial and automotive hardware and software platforms will combine the best of both worlds. Automotive brings strong security expertise and industrial is built on strong Internet of Things and artificial intelligence solutions. The converged future will share hardware technologies, cores, and a common ecosystem of tools and software support. Such convergence will enable customers to seamlessly transition between solutions, offering simplification and full scalability to innovate faster.

Edge AI technology is one example where we see what is being adopted now in industrial applications benefiting automotive in the future. Neural accelerator technology and the associated tools that enable developers to easily implement AI in their applications, whatever their level of data science expertise, will enhance automotive systems in the future. ST has spent approximately 10 years investing in the development of microcontrollers, smart sensors, and AI software tools to meet the needs of our customers and harness the power of edge AI.

While AI adoption in automotive—beyond autonomous driving—is still in its initial stages, there are emerging trends of promising use cases for system optimization, energy efficiency, and problem-solving. For example, virtual sensors can measure rotor temperatures, and predictive maintenance can ensure vehicle reliability. As the number of sensors in vehicles heavily increases, AI will play a key role in virtualizing many of them, further enhancing automotive performance. Security is another area where we see the convergence of industrial and automotive bringing significant benefits.

This future will be based on the most advanced and more efficient 18nm process technologies. ST’s advanced technology portfolio for automotive MCUs spans from 40 to 28 to 18nm, selected to optimize product performance and cost.

The benefits of the IDM model for our customers

As an integrated device manufacturer (IDM), ST develops fundamental semiconductor process technologies, creates core intellectual property (IP), designs products using these technologies and IP, and manufactures, tests and packages them using owned facilities or through partnerships. This brings several benefits for our customers:

• Processes designed and refined to meet the applications needs of our customers in various markets.
• IP blocks optimized for specific functions and systems, owned by ST.
• Manufacturing processes are optimized for key performance and yield through the tight teamwork between process, product, and operational teams.
• Control of manufacturing capacity and creation of flexible, reliable supply chains.

This is particularly important for our automotive customers.

An example of these benefits is the combination of FD-SOI and PCM technologies that ST has developed for its Stellar microcontrollers. ST was one of the key innovators in both technologies, working with partners to bring them to market. ST’s ability to master the technology and tailor it to automotive applications has resulted in products with unique benefits. ST’s implementation of PCM technology has allowed the creation of the smallest physical memory cell in the industry delivering 2x the memory density of alternatives.

Thanks to the high-energy efficiency, high reliability, and radiation immunity of this memory technology, ICs designed in FD-SOI with embedded PCM meet the most stringent requirements of automotive applications. ST’s PCM technology achieves automotive requirements for AEC-Q100 Grade 0 with an operating temperature up to +165°C. The patented technology supports high-temperature data retention, including during solder reflow, so firmware can be uploaded before soldering.

Ecosystem plays a key role for transformation

An extensive partner ecosystem from developer tools to specific libraries for safety, security, and data exchange and distribution, augmenting ST’s portfolio capabilities further complements this leading technology. This will also provide the necessary simplification, aiding our customers in their transformation journey towards software-defined vehicles.

“STMicroelectronics and Green Hills Software are working closely together to deliver innovative integrated hardware and software solutions that address the growing challenges automotive OEMs and Tier 1s face in next generation vehicle zonal architectures.” said Dan O’Dowd, Founder and CEO at Green Hills Software. “Green Hills production-proven safety-certified RTOS and tools, coupled with ST’s Stellar SR6’s unique communication IP, deliver advanced fault tolerant zonal networking that enables significant per-vehicle cost savings while reducing time-to-market.”

“With MICROSAR Classic, we enable our customers with safe and secure basic software for ECUs for a wide range of use cases. Thanks to many years of close cooperation with ST, the corresponding support for the new Stellar MCUs is already available,” says Jochen Rein, Director of the Product Line Embedded Software and Systems at Vector. “By integrating Stellar’s advanced hardware with Vector’s robust software, customers get the highest level of safety and reliability for both ADAS applications and to successfully manage the transition to Software-Defined Vehicles.”

“iSOFT is a leading developer of automotive operating systems in China and the premium partner of AUTOSAR for China’s infrastructure software. Since the introduction of its collaboration with ST in 2016, iSOFT has become ST MCAL agent in China. This includes multiple microcontrollers such as SPC58/SPC56/STM8A, and the companies will also engage in a deeper strategic cooperation on the newly introduced Stellar family that will support EasyXMen Open Source Operating System in the future.” Luo Tong, Vice President, iSOFT

“Neusoft Reach’s software platform, NeuSAR, leads the mass production of China’s full-stack “AUTOSAR +Middleware,” widely used in next-gen ADAS, chassis, power, and body control systems. Neusoft Reach provides complete solutions based on ST’s SPC5 and Stellar E series automotive MCU, including application/basic software, bootloader, refresh, and simulation, which will be complemented with the new gen of Stellar P and G series. Both companies will work together to create a higher level of automotive-grade software and hardware integrated solutions to help OEMs and tier 1s to bring efficient, personalized, and differentiated functions and accelerate SDV innovation.” Jipeng Wang, Director, NeuSAR CP Products BU, Neusoft Reach

Conclusion

By building on common foundations across product dimensions and focusing on robust automotive quality, ST serves a wide market with a comprehensive product range that is both “broad”—spanning from as low as 128 KB to 64 MB memory, single to multicore computation with virtualization—and “deep,” with each series tailored for specific functions: Stellar P and G series focus on integration, and STM32A will be optimized for value, targeting single-core applications that prioritize efficiency and simplicity.

ST’s expanded automotive microcontrollers roadmap focuses on helping its customers to reduce complexity, improve efficiency, while ensuring the highest security and safety standards for next-gen cars. It addresses electrification, personalization, automation, and connectivity.

The post ST’s Automotive MCU technology for next-generation vehicles appeared first on ELE Times.

As the Trump administration proposes the introduction of “reciprocal tariffs”—taxing imports at the same rate foreign governments impose on U.S. goods—the global electronics and semiconductor industry is bracing for ripple effects that could redefine supply chains, trade routes, and strategic investments. With India emerging as a serious contender in global electronics manufacturing, these policy shifts could present both opportunities and challenges for the country’s growing semiconductor ambitions.

Global Supply Chains in Flux

The electronics and semiconductor sectors are among the most intricately connected global industries. From chip design in the U.S. and Taiwan, to wafer fabrication in South Korea and China, to final assembly in India and Vietnam—every component in a finished product typically crosses multiple borders. A tariff war threatens to disrupt these finely tuned global supply chains.

This risk was underscored recently when President Donald Trump announced a staggering 104% tariff on Chinese electric vehicles, shaking global markets. Reacting to the tariff hike, Tata-owned Jaguar Land Rover halted its shipments to the U.S. for a month in response to a separate 25% import tariff, citing sudden cost pressures and logistical uncertainty. These developments signal a volatile phase for companies relying heavily on cross-border operations.

For India, which imports up to 88% of its semiconductor requirements, disruptions in sourcing from East Asian hubs could cause short-term volatility in the availability and pricing of key components. Additionally, higher tariffs could push up input costs for Indian manufacturers exporting to the U.S., making pricing less competitive.

A Tailwind for ‘Make in India’?

However, there’s a silver lining. As geopolitical tensions rise and multinationals seek “China Plus One” strategies, India is increasingly viewed as a viable alternative. The Indian government’s push under the Production Linked Incentive (PLI) scheme, coupled with new semiconductor fabrication plans and robust demand for electronics, places the country in a favorable position to absorb diverted investments.

This shift is already underway. Apple and Samsung are reportedly accelerating plans to shift manufacturing to India, partly to hedge against Trump’s rising tariffs on Chinese goods. Apple, for instance, has already begun iPhone production at Foxconn’s Tamil Nadu facility, with plans to ramp up output in 2025. These strategic realignments bolster India’s role in the global value chain.

If reciprocal tariffs deter trade between the U.S. and China, Indian manufacturers may gain a competitive edge—particularly in segments like PCB assembly, mobile manufacturing, and back-end chip packaging. This could catalyze India’s ambition to become a $300 billion electronics manufacturing hub by 2026.

Impact on Competitiveness

Over 80% of the U.S. semiconductor industry’s production is destined for international markets, making it highly dependent on global exports. Imposing higher tariffs may weaken its global competitiveness, particularly if retaliatory measures by other countries kick in. On the flip side, Chinese manufacturers could double down on building self-reliant supply chains, while Indian firms may find new export opportunities if trade patterns realign.

Yet, uncertainties remain. India’s electronics industry still depends significantly on imports of chips and sub-components. Tariff-induced disruptions could lead to cost escalations, affecting price-sensitive consumer markets both in India and abroad.

Export Pressures & Strategic Realignment

With India expanding its export capabilities in smartphones, consumer electronics, and electric vehicle components, increased trade barriers may force a rethinking of pricing strategies. Electronics brands exporting to the U.S. could face squeezed margins or may need to reroute operations to avoid tariffs.

To stay competitive, global electronics firms may explore shifting part of their production from China to tariff-neutral zones such as India, Mexico, or Southeast Asia. This trend, already underway post-COVID-19, may accelerate under tariff-driven pressure.

Policy Implications for India

India must walk a fine line. While these global shifts could open up new export windows, there’s also a risk of becoming collateral damage in a broader trade conflict. To safeguard domestic manufacturers and leverage emerging opportunities, the Indian government should consider:

• Negotiating strategic trade agreements with the U.S., EU, and ASEAN nations.
• Providing greater ease-of-doing-business incentives for relocating manufacturers.
• Accelerating semiconductor ecosystem development to reduce import dependencies.
• Offer temporary tariff shelters or rebates for affected MSMEs in electronics exports.

Conclusion: A Defining Moment

The Trump administration’s proposed tariffs may well be a turning point for the global semiconductor and electronics industry. For India, this could serve as both a test and an opportunity—to deepen its electronics manufacturing base, attract foreign investments, and reposition itself as a trusted global partner in a rapidly changing trade environment. Strategic foresight, nimble policy responses, and continued innovation will be key to navigating the challenges ahead.

The post Trump’s Tariff Surge Rattles Global Electronics Industry: Can India Rise Amid Disruption? appeared first on ELE Times.

Courtesy: Synopsys

We’re excited to announce Virtualizer Native Execution for Arm-based machines. This groundbreaking virtual prototyping technology will transform how software is developed for edge devices and applications — particularly in the automotive, HPC, IoT, and mobile industries.

Virtualizer Native Execution enables a paradigm shift in edge-focused software development via improved:

• Simulation performance. Virtualizer Native Execution significantly boosts the performance of virtual prototypes — speeding up software development, debugging, and testing.
• Development productivity. Virtualizer Native Execution leverages cloud-native approaches to enhance productivity, reduce toolchain silos, and make modern development workflows more accessible for embedded software engineers.

Extending the industry-leading virtual prototyping solution to the Arm ecosystem

The market-leading virtual prototyping solution with the largest library of models and IP,Virtualizer enables developers to work with virtual prototypes of target hardware instead of physical setups that are location-dependent and difficult to scale.

Virtualizer Native Execution extends the complete Virtualizer tool suite to the Arm ecosystem, allowing virtual prototypes to be built, executed, and tested directly on Arm-based machines. And because it can be leveraged across development and computing environments — on-premises, in the cloud, and at the edge — it eliminates toolchain and workflow silos and helps increase development flexibility and agility.

Virtualizer Native Execution significantly boosts development speed and efficiency via:

• Native execution. Instead of simulating the target hardware’s CPU on an Instruction Set Simulator (ISS), Virtualizer Native Execution enables virtual prototypes to be executed directly on the host CPU. This significantly reduces boot times (from 20 minutes to tens of seconds for a typical Android boot).
• Scalability. Modern Arm host machines offer more than 96 cores, and Virtualizer Native Execution can directly map each core of the virtual system-on-chip (SoC) to a physical core to greatly accelerate prototype performance.

Supporting the increased adoption and development of Arm-based systems

Arm-based CPUs have long dominated the mobile market, and in recent years they’ve been increasingly used for automotive, IoT, consumer, and other edge-based applications. Those in the cloud and HPC markets have also embraced Arm CPUs and IP, which provide an alternative to traditional x86-based solutions and deliver exceptional performance, power, and cost benefits.

This widespread adoption is leading to greater alignment and uniformity of the CPUs and toolsets being used across on-premises, cloud, and edge environments. Often referred to as Instruction Set Architecture (ISA) parity, this uniformity provides new opportunities to streamline development efficiency and flexibility.

Virtualizer Native Execution supports the increased adoption and development of Arm-based solutions and takes advantage of ISA parity to supercharge software development and edge innovation.

Combining virtual prototyping with hardware-assisted verification (HAV)

Virtualizer Native Execution also supports hybrid emulation, which combines the unique strengths of virtual prototyping and hardware-assisted verification (HAV). Tightly integrated with Synopsys HAV solutions, Virtualizer Native Execution supports hybrid setups where the CPU subsystem is virtualized and the rest of the device under test (DUT) is emulated. And because it eliminates ISS overhead and runs natively on the host CPU, Virtualizer Native Execution is able to keep up with the fastest emulation systems (including the new ZeBu-200).The speed and scalability of Virtualizer Native Execution also enable new emulation use cases, like application-driven performance and power validation.

Taking embedded software development to the cloud

Developing embedded software for edge devices has long been a fragmented process involving complicated lab setups, delicate test boards and cables, and disparate toolsets. Not only has this hindered efficiency and scalability, but it has prevented the adoption of modern, agile development processes.

With Virtualizer Native Execution, developers can:

• Build and scale CI/CD pipelines in the cloud.
• Take advantage of higher performance and throughput as well as faster boot times.
• Replicate and align virtual prototypes across development and operating environments — on-premises, in the cloud, and at the edge.

Virtualizer Native Execution for Arm marks a significant leap forward in edge-focused software development. With better performance and scalability, native execution on Arm-based machines, and cloud-to-edge parity, developers can supercharge their virtual prototyping workflows.

The post Transforming Edge Software Development with Arm-based Virtual Prototyping appeared first on ELE Times.

Courtesy: Renesas

High-performance AI data centers are reshaping semiconductor design and investment trajectories like no technology we’ve seen. As recently as 2022, spending on AI infrastructure was in the vicinity of $15 billion. This year, expenditures could easily top $60 billion. Yes, that sucking sound you hear is the oxygen being pulled from every investment plan and breathed into data centers.

We are clearly operating in an era of unprecedented artificial intelligence capital outlays – notwithstanding the potential impact of newcomers like DeepSeek. But while high-performance computing processors from Nvidia, AMD, and others are busy stealing the limelight, the high-bandwidth memory that stores training and inference models is having its day too – with 2024 DRAM revenue setting a record of nearly $116 billion.

Data center servers are driving a continuous increase in CPU core count, which requires more memory capacity to make higher-bandwidth data available to each processor core. But the laws of physics are quickly catching up. A CPU signal can only go so fast and far. That’s where memory interface devices such as register-clock drivers and data buffers come into play. By allowing the clock, command, address, and data signals to be re-driven with much-improved signal integrity, these interfaces enable the entire memory subsystem to scale in speed and capacity.

Today, RCD empowers registered DIMMs (RDIMMs) to operate up to 8 Giga Transfers per Second (GT/s). Most data center servers use RDIMMs, although some HPC systems need even greater memory subsystem performance.

Memory Interfaces Further Accelerate DRAM and Processor Performance

Notable for the vital role it plays in data center server systems, DRAM architecture hasn’t actually changed dramatically over the past three decades. Increases in density, speed, and power efficiency can be attributed largely to deep-submicron semiconductor scaling, while new 2.5D and 3D stacked DRAM packaging allows for higher-capacity DIMM modules.

As explained above, advances in memory interface technology – beginning with synchronous DRAM and carrying across multiple generations of double data rate DRAM – have played an outsized role in helping the interface keep pace with processor speeds.

Multi-rank DIMMs (MRDIMMs) are an innovative technology designed for AI and HPC data center applications. Made possible through a partnership between Renesas, Intel, and memory suppliers, MRDIMMs allow the memory subsystem to scale to much higher bandwidths compared to RDIMMs on corresponding server systems. Specifically, MRDIMMs double the data transfer speeds of the host interface by enabling two ranks of memory to fetch data simultaneously, which yields a six percent to 33 percent improvement in memory bandwidth.

Renesas DRAM Interfaces Help Close the Processor-to-Memory Performance Gap

Late last year, Renesas released the first complete memory interface chipset solution for second-generation DDR5 MRDIMMs. With an operating speed of 12.8GT/s, this represented a huge improvement in terms of how fast we can drive the interface compared to the 8.0GT/s maximum for a standard DIMM.

How did we get there? Through a combination of highly orchestrated component technologies. Since its inception at Integrated Device Technology, before it was acquired by Renesas, we’ve been on a mission to solve one problem confounding memory performance: signal integrity.

As the speed gap between DRAM and the CPU began to grow, the physical loading of the DRAM was becoming a problem for system architects. We saw an opportunity to address the challenge through our analog and mixed-signal design competency. The first in line was an RCD we used to intercept and redrive the clock signal and command address between the DRAM and processor. Subsequently, we developed a line of fully buffered DIMMs, which encapsulated all types of signals on the system memory interface, including clocks, command addresses, and data.

Fast forward, and our newest DDR5 memory interfaces include second-generation RCDs and data buffers for MRDIMMs in addition to a power management IC (PMIC), making us the only company to offer a complete chipset solution for the next-generation of RDIMMs and MRDIMMs. In addition, Renesas has made a significant contribution in helping power efficiency by evangelizing a concept called “voltage regulation on DIMM.” Voltage regulation circuitry now sits directly on the DIMM, as opposed to the motherboard, which allows for a more efficient, distributed power model. This is done using PMICs that locally generate and regulate all the necessary voltages needed by various DIMM components.

Leveraging the Electronics Design Ecosystem for the Future

Renesas has amassed a vast base of in-house expertise by collaborating with a large design ecosystem of leading CPU and memory providers, hyperscale data center customers, and standards bodies like JEDEC. That gives us the freedom to remove the bottlenecks that stand in the way of our ability to continue increasing DIMM speeds and capacity by determining how many DRAM components can be populated and how fast they can run.

It also opens opportunities to leverage technologies developed for AI data centers and redirect them to emerging use cases. That’s true for the higher processing and memory bandwidth requirements influencing designs at the edge of industrial network controls, where data must be captured and turned into actionable insights. And, it applies to the surging data volumes required by automotive safety and autonomous driving applications, which are quickly turning our vehicles into servers on wheels.

The post High-Speed Data Centers Owe a Debt of Gratitude to DRAM Memory Interfaces appeared first on ELE Times.

Courtesy : Bosch

The moon — an environment full of extremes that can push even the most advanced technologies to their limits. Abrasive dust blocks sensitive sensors, temperatures as low as -150°C challenge conventional electronics, and the complete absence of GPS makes precise navigation nearly impossible. Such conditions demand innovative solutions tailored to the unique requirements of this extraordinary environment.

Bosch brings its technological expertise to a visionary project funded by NASA’s Tipping Point program with $5.8 million. In collaboration with Astrobotic, WiBotic, the University of Washington, and NASA’s Glenn Research Center, the project unites contributions from leading innovators. CubeRover(TM), developed by Astrobotic, is the mission’s lightweight and modular exploration vehicle. WiBotic contributes wireless charging technology, enabling efficient energy transfer under lunar conditions. Bosch focuses on autonomous docking, providing critical systems that ensure the CubeRover(TM) can navigate and connect reliably in this extreme environment. The University of Washington and NASA Glenn Research Center contribute by offering performance characterization and testing of the wireless charging system.

Together, these efforts promise to revolutionize space exploration while paving the way for future innovations in autonomous systems development.

The minds behind the mission — Vivek Jain and his team

One of them is Vivek Jain, a lead expert at Bosch Research. Astrobotic serves as the principal investigator for this project, working closely with Bosch, which contributes its expertise in sensing, software, and autonomous docking for wireless power transmission.

Together, the partners are developing technologies that enable the rovers to navigate the moon with precision — without GPS. To achieve this, Bosch relies on a combination of camera data, Wi-Fi fingerprinting and sensor fusion. These approaches ensure that the rovers operate reliably even under extreme conditions such as intense light or presence of sticky lunar dust. With these innovative solutions, Bosch plays a crucial role in advancing the development of autonomous systems designed for the moon’s demanding environment.

Vivek Jain, Head of the Wireless Connectivity and Sensing group at Bosch Research, Sunnyvale, USA CubeRover(TM) — small, lightweight, and efficient

CubeRover(TM) is the centerpiece of the lunar mission, designed specifically for operation on the moon’s surface. A modular, ultra-lightweight, and compact rover, its smallest form factor weighs less than 5 pounds and is roughly the size of a shoebox. These characteristics enable the simultaneous transport of multiple rovers on a central platform (lander), which lands on the lunar surface and serves as a base station for power and navigation.

This makes missions not only more flexible but also more cost-effective, as multiple rovers can be deployed with a single launch. In addition to its compact size, CubeRover(TM) impresses with its versatility. It can carry scientific instruments such as cameras or spectrometers, opening up new approaches to lunar exploration. With its innovative technology and ability to operate reliably even in extreme environments, it represents a turning point in the exploration of new worlds.

Reaching the destination without GPS — the challenges of navigating the moon

How Bosch develops creative solutions for navigation.

Orientation with visual markers and sensor fusion

How do you navigate on the moon, where GPS is not an option? Bosch has the answer with innovative technologies that guide the CubeRover(TM) safely through the extreme conditions of the lunar surface. The lander, a platform on the moon’s surface, serves as a central base station for the CubeRover(TM), providing energy and orientation. Special visual markers, known as AprilTags, are attached to the lander and function like QR codes. These markers are detected by the CubeRover(TM)’s camera, enabling it to accurately calculate its position and navigate securely.

In addition, the CubeRover(TM) employs sensor fusion, combining camera data with information from motion sensors and wheel speed sensors. This technology ensures stability even on uneven or slippery surfaces — performing reliably amidst dust, intense light, or wheel slips.

Wi-Fi fingerprinting as a backup solution

In addition to visual markers, Bosch uses Wi-Fi fingerprinting to ensure the CubeRover(TM)’s navigation. The lander, the central platform on the lunar surface, emits Wi-Fi signals that the rover receives. Based on the signal strength and characteristics, the CubeRover(TM) determines its position and creates a map of the surroundings.

This method acts as a backup when visual markers are obscured by dust or shadows, ensuring the CubeRover(TM) remains navigable even under challenging conditions. By combining visual markers, sensor fusion, and Wi-Fi fingerprinting, Bosch enables precise navigation – entirely without GPS.

Wireless charging

The small rover presents unique challenges for energy supply. Being too small for large solar panels, the CubeRover(TM) employs an innovative solution: wireless charging. The lander collects solar energy and transfers it wirelessly to the rover.

An additional benefit of this technology is the heat generated during the charging process. This heat is used to protect the rover from the extreme temperatures of the lunar night. Intelligent charging algorithms ensure that the rover aligns its position optimally for efficient energy transfer.

The post Mission Moon — how CubeRover makes autonomous docking for space possible appeared first on ELE Times.

In an exclusive conversation with Rashi Bajpai of ELE Times, Pankaj Singh, Head of Data Center & Telecom Business Solutions at Delta Electronics India, delves into the company’s groundbreaking strides in energy-efficient ICT infrastructure.

Pankaj Singh- Head of Data Center & Telecom Business Solutions at Delta Electronics India

Highlighting innovations tailored for India’s unique needs and global scalability, he discusses Delta’s pivotal role in shaping sustainable, high-performance telecom and data center ecosystems aligned with the Digital India vision.

 

 

 

 

Here is the excerpt:

ELE Times: Delta Electronics has long been a leader in energy-efficient ICT solutions. Could you elaborate on the latest innovations in your telecom and data center products that optimize energy consumption without compromising on performance?

Mr. Pankaj Singh: Delta continues to innovate in the ICT sector by developing high-efficiency power and cooling solutions that optimize energy consumption while maintaining superior performance. Our telecom and data center solutions incorporate 97% efficiency rectifiers, modular UPS systems exceeding 97% efficiency, and AI-driven thermal management that dynamically adjusts cooling based on real-time data, significantly improving Power Usage Effectiveness (PUE). Additionally, our hybrid power systems seamlessly integrate renewable energy sources, reducing reliance on conventional power grids. These innovations help businesses enhance operational efficiency while reducing carbon footprints and energy costs, reinforcing Delta’s commitment to sustainability and technological advancement.

ELE Times: As a company committed to both local and global markets, how does Delta ensure that its telecom and data center products are specifically tailored to meet India’s unique requirements while also being scalable for international use?

Mr. Pankaj Singh: Delta adopts a localization-with-scalability approach to develop telecom and data center solutions that address India’s unique challenges while remaining adaptable for global markets. Last year, we inaugurated our global R&D Center in India with the vision of “Design in India, for the World.” Our India-based R&D team develops products tailored to the country’s diverse climatic conditions, including extreme temperatures and humidity, while ensuring power reliability through high-efficiency rectifiers and advanced battery storage solutions. Our grid-resilient hybrid power systems enable seamless connectivity even in remote areas with unstable power supply. Additionally, Delta ensures compliance with Indian (BIS, TEC) and global (UL, CE, IEC) standards, making our products viable for both domestic and international markets. By integrating modular and scalable architectures, we deliver future-ready ICT solutions that evolve with business needs while maintaining high efficiency and reliability.

ELE Times: With the ambitious goal of powering 5 lakh telecom towers across India, how are Delta’s cutting-edge solutions addressing the increasing demand for reliable connectivity, and how does energy efficiency factor into this large-scale initiative?

Mr. Pankaj Singh: Delta is committed to supporting India’s telecom expansion by delivering energy-efficient and reliable power solutions for 5 lakh telecom towers across the country. Our advanced high-efficiency rectifiers, lithium-ion battery energy storage solutions, and hybrid power systems ensure uninterrupted connectivity, even in regions with unstable grid power. By integrating renewable energy sources such as solar and wind with intelligent power management systems, we help telecom operators reduce operational costs and carbon footprints. Additionally, our comprehensive telecom customer service ensures 24/7 technical support, proactive maintenance, and remote monitoring capabilities, enabling seamless network operations. With a strong focus on energy efficiency, grid resilience, and smart automation, Delta empowers telecom providers to enhance network uptime while meeting sustainability goals.

ELE Times: At ELECRAMA 2025, Delta introduced several new products designed to support India’s Digital India vision. Could you highlight the key technical features of these products and explain how they will contribute to the enhancement of India’s digital infrastructure?

Mr. Pankaj Singh: At ELECRAMA 2025, Delta unveiled a range of next-generation power and ICT solutions aimed at strengthening India’s digital infrastructure. Our new high-density UPS systems offer industry-leading >97% efficiency, ensuring maximum power protection for critical IT applications. We also introduced prefabricated modular data centers, which provide a plug-and-play, scalable approach to IT infrastructure expansion, allowing rapid deployment with optimized energy consumption. Our 5G-ready telecom power systems integrate solar energy, lithium-ion storage, and AI-based thermal management, reducing energy costs while enhancing network reliability. These solutions are set to support India’s Digital India vision by providing efficient, scalable, and sustainable infrastructure for the country’s growing data needs.

ELE Times: Sustainability is a key focus for Delta. How do your product development strategies balance the need for technological innovation with the imperative for environmental sustainability, particularly in the context of energy-efficient data centers and telecom networks?

Mr. Pankaj Singh: Sustainability is at the core of Delta’s product development strategy, ensuring that every innovation balances technological advancement with environmental responsibility. Our data center and telecom solutions are designed to minimize energy consumption by incorporating high-efficiency power conversion, intelligent thermal management, and renewable energy integration. We use recyclable materials, lead-free components, and eco-friendly manufacturing processes to reduce environmental impact. Additionally, our solar-powered energy solutions and AI-driven cooling systems significantly cut carbon emissions and operational costs. By prioritizing energy efficiency, sustainable materials, and intelligent automation, Delta is driving the ICT industry toward a greener, more sustainable future without compromising on performance or scalability.

ELE Times: The telecom and data center industries are evolving at an unprecedented pace. What are the most significant challenges Delta faces in designing solutions for this rapidly changing environment, and how do your latest technologies address these challenges to ensure long-term scalability and efficiency?

Mr. Pankaj Singh: The telecom and data center industries are evolving rapidly, driven by increasing data demand, emerging technologies like 5G and AI, and the need for energy-efficient infrastructure. Delta faces several key challenges in designing solutions that ensure long-term scalability and efficiency.

One major challenge is scalability, as networks and data centers must accommodate exponential growth in bandwidth, processing power, and storage. Delta addresses this by implementing modular and cloud-native architectures, allowing seamless expansion while maintaining cost efficiency. Another challenge is energy consumption, as data centers are among the largest consumers of electricity. Delta integrates high-efficiency power solutions, intelligent cooling systems, and renewable energy integration to minimize energy use and reduce environmental impact.

Delta’s latest technologies also focus on 5G, edge computing, and AI-driven network management, enabling faster connectivity, real-time data processing, and reduced latency. By integrating automation, energy efficiency, and scalable architectures, Delta ensures its telecom and data center solutions remain future-ready, adaptable, and optimized for performance in a rapidly evolving digital landscape.

The post Delta Electronics Fuels India’s Digital Ambitions with Scalable, Sustainable ICT Solutions appeared first on ELE Times.

Courtesy: ANALOG DEVICES

ISO 10218, third edition, was released at the start of 2025. This standard covers industrial robot safety. Typically, this means fixed industrial robots, including what are known as cobots. A HAS consultant assessed the standard, which will hopefully be published shortly in the OJEU (official journal of the European Union) giving a presumption of conformity with all relevant machinery directive clauses.

Note – ISO TC 299 WG 3: avoid using the word cobot, as there is no such thing. The assertion is that the application is collaborative and not the robot. Any robot can work in a collaborative application with the right external equipment, e.g., a laser scanner or 3D TOF may allow implementation

Figure 1: Two parts of the new industrial robot safety standard

I think I started on this committee in 2018, and Ireland hosted a meeting on the committee in 2019, but I believe WG3 was already working on this revision well before that time. The convenor was Roberta Nelson Shea of Universal Robots, which meant we had much experience right there, but there was a lot. I mean a lot, of experience in both the application and design of robots within the group. It also included health and safety professionals, independent assessors, and a human factors expert. It was a well-attended group, with over 50 in some cases, leading to restrictions on how many from each country were allowed to attend. Countries with big teams attending included Canada, Japan, Korea, Sweden, Germany, the USA, the UK, Ireland, Denmark, and Italy…. I must admit, I’m a robot safety expert who has never used a robot. My other major functional safety contributor is on the IEC 61508 committee, where I lead the semiconductor group, including the new IEC 61508-2-1. Therefore, once we strayed into the use of robots, as opposed to their design, I was out of my depth. For this reason, I am sure that the highlights I have chosen below from the new version would be very different from those chosen by someone with a different background.

Figure 2: Excerpt from the Irish papers dated November 2019

My highlights are:

• Removal of mandatory redundancy requirements
• New security guidance
• New comms requirements

Removal of Mandatory Redundancy Requirements

Let’s start with the mandatory redundancy requirements. The older 2011 version required a default SIL 2 with HFT=1 or PL d CAT 3 safety function. This offended me on several levels, including:

• With complex technology, systematic failure modes are more of a concern than random hardware failures
• HFT= 1 and CAT 3 are not even the same thing (CAT 3 allows the impact of diagnostics in achieving single fault tolerance to be considered, HFT does not)
• Modern technology based on semiconductors can be far more reliable than older mechanical technology and with higher diagnostic rates and lower diagnostic test intervals

Figure 3: Graphic showing the 4.43e-7/h portion of the SIL 2,PL d range

Even after many years of debate (yes years and I am not exaggerating) the following was agreed. If you weren’t involved, the number of 4.43e-7/h might seem random. Both PL d and SIL 2 require a failure rate in the range 1e-6/h to 1e-7/h, so it’s just below the midpoint of the range. It’s in the better half, indicating lower-than-average risk. But if lower-than-average was all we required, we could have used 5.0e-7/h. Shown another way, it can be compared to what is traditionally achieved with a CAT 3 architecture. The graphic above also shows it exceeds what is generally considered possible with a CAT 2 (non-redundant) architecture. However, the best way to show it is by highlighting it using ISO 13849-1:2015 Annex K. To get to this number with a CAT 2 architecture (single channel with diagnostics) you need an MTTFd (mean time to failure dangerous) of 62 years and a DC of 90%. It also shows that previously with your CAT 3 architecture a DC of 60% would have been acceptable but that would deliver a much worse PFHd unless you got your MTTFd to at least 43 years and that with CAT 3 and a DC of 90% you can easily reach down into PL e type performance.

It’s good to write this down while I still remember the reasoning. These changes will make it easier to adopt new technologies into robots but reduce the robot cost and increase the robot’s capabilities, which hopefully will all contribute to a higher adoption of robots. Such new technologies might include 3D TOF and novel encoders.

New Security Guidance

Figure 4: 4.43e-7/h shown in comparison to the traditional CAT 3 architecture

My next highlight is the new cyber security guidance. It’s always controversial whether safety standards should include anything on cyber security or whether the two disciplines should remain separate. However, it is good that we added something as the new EU machinery regulation (replacing the old machinery directive) places more emphasis on cyber security than the old machinery regulation. We also now have the CRA . I would have liked to add more emphasis on IEC 62443 compliance, but what we got is good. A cyber security risk assessment is now required, and IEC TS 63074:2023 is called out, which then defers to IEC 62443. I spoke on cyber security for robots at last year’s international robot safety conference in Cincinnati. Unfortunately, the presentations from this excellent conference are not available on the web.

New Comms Requirements

Lastly, in a world with more and more requirements for always being connected, data is the new oil; it is good that the standard now includes requirements for industrial communications. There was nothing in the old version on safety data to be transmitted over a network. Previously, the best guidance would have been in IEC 61508-2010 7.4.11, which mentions a white channel design with no further details and defers to either IEC 61784-3 or IEC 62280/EN 50519 for the black channel designs. The new version of ISO 10218 concentrates on the more common black channel approach and, despite being short, shows how the black channel requirements can be tailored differently for the internal robot network (controller to the various axes) and the external robot network, e.g., controller to a PLC.

This is an area I continue to work on; we are revamping IEC 61508-2 7.4.11 with more details on the white channel in particular, which I think might be especially relevant for robot internal networks since it is more suitable in my view for hard real-time requirements. I have also, for my sins, been appointed as the liaison between IEC TC 65 SC65A(system) and SC 65C.  The black channel will continue to be the most important for the controller to the PLC network, and the 1km range offered by 10BASE-TIL and even Ethernet APL / 2-WISEcould be important here.

Other information I like in the new version includes:

• The long list of safety functions in Annex C
• The allowances for small robots in 5.1.17 (<10kg, <250mm/s, <50N)
• The nice figure in Annex B shows maximum, restricted, operating, and safe-guarded spaces

ISO TC 299 WG 3 is continuing to work on ISO 20218-3, which will give more guidance on the limited information on cyber security within ISO 10218. I don’t know whether ISO 10218 already needs a refresh to allow for machinery regulation.

The post The Revised Industrial Robot Safety Standard appeared first on ELE Times.

Courtesy : Microchip

As EEPROM devices shrink, board space can be freed for exciting uses. However, smaller EEPROM means smaller cell sizes. This in turn means thinner cell oxide layers. These can wear out more easily, raising reliability concerns. Many manufacturers defend against cell wear out with Error Correcting Codes which detect and correct errors. This solution is usually hidden, with no way of knowing whether it’s there or if it was invoked. Thus, ECC should be seen as a safety feature, not a sole reliability solution. That’s why Microchip Technology, with over 30 years of EEPROM experience, has developed a new family of EEPROM with Error Correction Status. ECS alerts users when error correction occurs, indicating that a memory block should be retired. This feature takes error correction one step further, acting as a powerful reliability multiplier for stand-alone EEPROM, and providing transparency and control designers can enjoy.

Error Correction

As mentioned, most new EEPROMs include Error Correcting Codes, typically designed to correct single-bit errors for each specified number of bytes. There are multiple types of ECC used, the most common being Hamming codes. ECC adds parity bits calculated from stored data. When data is read back, the parity bits are recalculated from stored data and compared to the parity bits stored in memory. Discrepancies indicate errors, and the pattern of the discrepancy allows the system to pinpoint and correct single-bit errors, restoring the data and allowing the memory block to continue to be used. However, many EEPROMs don’t indicate when corrections occur, leaving you unaware of deteriorating blocks. ECC then can only be used as a safety feature, giving the application a marginal endurance extension so it may last a bit longer without corrupted data. If you need to know if a block is truly worn out, you can add manual checks to verify memory after each write, but this is resource intensive. Error Correction Status on the other hand solves this challenge because it automatically flags you when a block becomes worn-out, enhancing reliability without needing to invest a large amount of resources.

System Considerations

The advantage of ECS shines the most within wear-leveling routines. How does wear-leveling work? Let’s begin with system design considerations and explain how wear leveling works, then we will show how to use ECS to enhance a wear-leveling routine.

Regardless of whether your EEPROM has ECC or not, it’s crucial to consider its endurance, typically rated at 100,000 cycles for MCU-embedded EEPROM and 1 million cycles for standalone EEPROM at room temperature. Designers must account for this by estimating the number of write cycles over the typical lifetime of the application to determine what size of an EEPROM they need and how to allocate data within the memory.

For instance, consider an industrial power distribution system in a building with four sensors, one for each machine that workers can use when needed. Each sensor generates a data packet per usage session, recording things like energy consumption, session duration and timestamps. Data is stored in the EEPROM until a central server requests a data pull. The system is designed to pull data frequently enough to avoid overwriting existing data within each packet. Assuming a 12-year application lifespan and an average of 400 daily packets per sensor, the total cycles per sensor will reach 1.752 million, greatly surpassing the typical EEPROM endurance rating. To address this, you can create a software routine to spread wear out across the additional blocks (assuming you have excess space). This is called wear-leveling.

Wear-Leveling: Dynamic and Static

To implement wear-leveling, you can purchase an EEPROM twice as large, allowing you to allocate 2 blocks per sensor, providing up to 2 million cycles per sensor. This offers a buffer of additional cycles if needed (an extra 248 thousand cycles per sensor).

You will then need some way to know where to write new data to spread the wear. While you could write each block to its 1-million-cycle-limit before proceeding to the next, this approach may lead to premature wear if some sensors generate more data than others. If you spread the wear evenly across the EEPROM, the overall application will last longer. Figure 1 illustrates the example explained above, with four meters sending data packets (in purple) back to the MCU across the communication bus. The data is stored in blocks within the EEPROM. Each block has a counter in the top left indicating the number of erase-write cycles it has experienced.

Figure 1

There are two types of wear-leveling: dynamic and static. Dynamic wear-leveling is simpler, spreading wear over frequently changing memory blocks but can result in uneven wear. Uneven wear caused by this type of wear-leveling is illustrated in Figure 2. The other type: static wear-leveling, spreads wear across the entire EEPROM, extending the life of the entire memory. Static wear-leveling requires more CPU overhead; however, it will produce the highest endurance for the life of the application.

Figure 2

Wear-leveling involves monitoring each memory block’s write cycles and allocation status, which itself can cause wear in non-volatile memory. To deal with this, one option is to store this information in your MCU’s RAM, which doesn’t wear out. Since RAM loses data on power loss, you may consider designing a circuit to detect power loss early, allowing time to transfer current register states to NVM.

Implement Wear-Leveling in Software

In general, a software approach to wear-leveling is to create an algorithm which directs writes to the block with the fewest previous number of writes to spread wear. In static wear-leveling specifically, data is stored in the least-used location not currently allocated for anything else, and data will be swapped to new locations if the cycle difference between blocks is too large. Each block’s write cycles are tracked with a counter, and blocks are retired when they reach their maximum endurance rating.

Wear-leveling effectively reduces wear and improves reliability, allowing each block to reach its maximum specified endurance (Figure 3). However, endurance specifications are only rough indicators of the physical life of the block and don’t include early failures. Also, many blocks will last much longer in the real-world than their endurance ratings allow for. To ensure even higher reliability, additional checks are needed. One method is to read back and compare the block just written to the original data, which requires bus time, CPU overhead and additional RAM. This readback should occur for every write, especially as the number of writes approaches the endurance limit, to detect cell wear-out failures. Without readbacks, wear-out and data corruption may go undetected. The following software flowchart illustrates an example of static wear-leveling, including the readback and comparison necessary to ensure high-reliability. This implementation has the disadvantage of spending significant system resources on reliability.

Figure 3

Using Error Correction Status with Wear-Leveling

Error Correction Status enables a new data-driven approach to wear-leveling and significantly enhanced reliability without the need for full data readbacks.

ECS indicates when a single-bit error has been detected and corrected. This allows you to check a status register to see if ECC was invoked, reducing the need for full memory block readbacks (Figure 4). When an error is detected, the block can be retired, providing data-based feedback on memory wear-out instead of relying on a blind counter. This eliminates the need to carefully estimate memory lifespan and is beneficial for systems that experience vast shifts in their environments over their life, like dramatic temperature and voltage variations which are common in the manufacturing, automotive and utilities industries. This approach allows you to extend memory cell life beyond the datasheet endurance specification all the way to true failure, potentially allowing you to use the device much longer than before.

Figure 4

This data-driven approach to wear-leveling is more reliable than classic wear-leveling because it uses actual data instead of arbitrary counts—if one block lasts longer than another, you can continue using that block until cell wear out. It also reduces bus time, CPU overhead and required RAM, which in turn lowers power consumption and improves system performance. Your software flow can now be updated to accommodate this new status indicator (Figure 5).

Figure 5

As illustrated in the flowchart, using an ECS bit simplifies the software flow by eliminating the need to read back data, store it in RAM and perform comparisons, freeing resources to create conceptually simpler software. Although a data readback is still required to evaluate the status bit, the data can be ignored, reducing RAM and CPU overhead. The frequency of status bit checks depends on block size and the smallest file size the software handles.

The following devices offer ECS and are currently released and available for order:

• I2C EEPROMs: 24CSM01 (1 Mbit), 24CS512 (512 Kbit), 24CS256 (256 Kbit)
• SPI EEPROMs: 25CSM04 (4 Mbit), 25CS640 (64 Kbit), 25CS320 (32Kbit)

The overall benefit of ECS is significant and will allow you to see cell health in a way you could not before. Some of the advantages are:

• Maximize EEPROM block lifespan by running cells to failure
• Option to remove full block reads to check for data corruption, freeing up time on the communication bus
• If wear-leveling is not necessary or too burdensome to the application, the ECS bit serves as a quick check of memory health, facilitating the extension of EEPROM block lifespan and helping to avoid tracking write cycles

Reliability Improvements with ECS

Implementing error correction with a status indicator revolutionizes reliability and extends device life, especially within wear-leveling schemes. This advancement is a game-changer for automotive, medical and other safety-critical applications, offering unparalleled reliability. Designers striving for excellence will find this approach indispensable in creating top-tier systems that stand the test of time. Remember, using our new CS EEPROM will allow you to take hold of your reliability destiny. For more information, be sure to check out our CS family of EEPROM products.

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Courtesy : LAM RESEARCH

Gate-induced drain leakage (GIDL) presents a major challenge in scaling DRAM technology.

DRAM serves as the backbone of modern computing, enabling devices ranging from smartphones to high-performance servers. As the demand accelerates for higher density and lower power consumption in memory devices, innovation in reducing DRAM leakage currents and enhancing performance becomes essential. One significant challenge in scaling DRAM technology is GIDL, a primary source of standby charge loss. This article explores how a DWMG structure in DRAM buried word-line (BWL) can mitigate GIDL. By leveraging a full-scale process integration model that supports electrical analysis, we demonstrate how this approach reduces leakage current while maintaining robust device performance.

The Challenge of GIDL in Modern DRAM

GIDL is primarily caused by band-to-band tunneling (BTBT) at the drain junction under high electric field conditions. This phenomenon not only increases off-state leakage currents but also degrades memory state retention time in DRAM cells, particularly as feature sizes shrink below 20 nm.1

Factors such as thinner gate oxides and higher doping concentrations exacerbate GIDL, creating a synergistic effect that makes it a critical problem in designing low-power, high-density DRAM.2

Figure 1: (a) Gain-induced drain leakage during pre-charge mode in DRAMs and (b) the mechanism of trap-assisted band-to-band tunneling3

The Solution

The introduction of a dual work-function metal gate structure provides a compelling solution to this challenge. By segmenting the buried word-line gate into regions with distinct work functions, the electric field along the channel is precisely controlled. Examples of some dual work-function metal gate structures are shown in Figure 2.

This structure suppresses BTBT generation, thereby reducing GIDL without compromising drive current or threshold voltage (Vt). As a result, this design is well-suited for advanced DRAM nodes.4,5

Figure 2: (Left to right) U.S. 9,543,433 B2 Samsung Patent,4 U.S. 9,543,433 B2 Micron Patent,5 and U.S. patent 9,276,114 TSMC patent.6

DWMG Alignment with Industry Trends

The DWMG approach aligns with broader semiconductor trends emphasizing advanced gate designs and channel engineering. Our study applies this innovation to DRAM technology, addressing GIDL challenges while preserving key performance metrics. Similar methods have been successfully implemented in FinFETs6 and tunnel FETs7 to reduce leakage and improve subthreshold slopes.

Leveraging Process Integration Modeling for Insights

Our process integration modeling platform (SEMulator3D) with built-in electrical analysis capabilities played a pivotal role in evaluating the DWMG design. This tool allowed us to:

1. Simulate the full process flow of a DRAM cell array, from active area formation to capacitor integration (Figure 3a).
2. Focus on the BWL transistor by extracting and refining a specific transistor for electrical characterization (Figure 3b–d).
3. Analyze the interactions between process parameters—such as gate work-function, oxide thickness, and doping profiles—and their impact on electrical performance.

This simulation framework provided a holistic view of integration challenges and revealed the effectiveness of DWMG in reducing current leakage.

Figure 3: The full process integration of a DRAM cell array: (a) The whole structure up to the capacitor top TiN deposition, (b) a top-down view to define the desired cross-section, (c) a zoomed view of the cell BWL transistors from which a target transistor is cropped, and (d) an electrical simulation structure of a cropped BWL transistor with the doping profile.

DWMG Design and Simulation Results

The DWMG structure is realized by splitting the gate into upper and lower regions with distinct work functions in the upper region’s metal gate of 3.5eV, 4.1eV, and 4.7eV (Figure 4). The device simulation considers the models of doping/field-dependent mobility, Shockley-Read-Hall (SRH) generation/recombination, and trap-assisted band-to-band tunneling effects.

The drift-diffusion equation is solved to obtain Idrain vs. Vgate curves, both in the linear and saturation regimes. The substrate current is measured (virtually) to determine the GIDL leakage amount.

Figure 4: A cross-section of the device simulation structure and metal gate work-function split conditions

Key results include the following:

1. Leakage reduction (Figure 5): The low and high work-function regions, in the upper gate and lower gate, respectively, create a more relaxed electric field distribution than the same work-function without the DWMG, which suppresses BTBT at the drain junction and in turn reduces leakage current.

Figure 5: Electric field and BTBT rate at the gate-drain overlap region (left) and a 2D field view of BTBT rate at Vg=-2.5V and Vd=+1.5V bias conditions (right).

2. Preserved device performance (Figure 6): Despite the GIDL reduction (I_subtrate), critical IV characteristics in both linear (Idlin_Vg) and saturation (Idsat_Vg) regimes remain intact when using the DWMG, ensuring reliable operation during read and write cycles.

Figure 6: Id vs. Vg in linear regime @Vd=0.1V (left), Id vs. Vg in saturation regime @ Vd=1.5V (middle), and Isub vs. Vg @Vd=1.5V (right).

3. Process dependency (Figure 7): Gate oxide thickness and doping concentration significantly influence performance. For instance, thinner oxides improve field control but increase BTBT risk due to the reduced barrier width. Similarly, higher doping improves modulation capabilities but exacerbates BTBT by increasing the electric field intensity, which accelerates tunneling processes.

Figure 7: Isub and max BTBT rate vs. gate oxide thickness (left) and Isub and max BTBT rate vs. source/drain doping (right).

Advantages of Combining Device Electrical Analysis with Process Integration Modeling   

Performing device electrical analysis during process integration modeling can enable the following types of advanced analyses that identify design-technology trade-offs:

• Electrical pathfinding: This type of analysis can be used to rapidly explore combinations of gate work-functions, oxide thicknesses, and doping profiles to pinpoint optimal designs. This approach has the potential to minimize the cost and time of physical experiments while reducing risks associated with late-stage failures.
• Variability analysis: Statistical simulations can identify the impact of process variations—such as gate oxide non-uniformity and doping fluctuations—on GIDL and IV characteristics. This type of analysis highlights critical design margins and has the potential to provide feedback on process optimization (such as active area formation) from very early process development stages.

The Future of DWMG and DRAM

The dual work-function metal gate (DWMG) is a robust, scalable solution for mitigating GIDL in DRAM technology. By optimizing the electric field distribution, this design effectively reduces leakage currents while maintaining critical IV performance. Process integration modeling combined with electrical analysis capabilities is instrumental in demonstrating the ability to reduce leakage current using DWMG, offering a comprehensive framework for addressing design and integration challenges.

Future research efforts could include:

• Integrating DWMG designs with high-k dielectrics or advanced junction engineering to further enhance leakage control.
• Assessing the impact of scaling trends, such as smaller metal pitches and EUV lithography, on DWMG performance.
• Developing predictive models for variability in advanced DRAM nodes.

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Courtesy : Infineon

As electric vehicles continue to gain traction in the agricultural, commercial, and construction sectors, the demand for efficient and reliable power systems grows. High-voltage traction systems ensure these vehicles operate effectively under heavy loads and demanding conditions such as 60,000 hours of operation time, up to 1.5 million km as well as low FIT rates. Infineon’s  EconoDUAL(TM) 250kw Power Kit ,is a prime example that meets the evolving needs of Inverter systems in commercial and agricultural vehicles.

This 250kW three-phase inverter power kit is designed for eCAVs with 800V battery ,addressing the increasing demand for reliable and efficient solutions. It provides a consistent platform for developers working on eCAVs, offering numerous benefits, including a fast time to market via its system solution, and a flexible design with scalable module currents up to 900 A nominal and an easy migration path towards higher voltage class and SiC technology.

Key features

• High-Power Output:  specifically designed for 800 V traction–inverter system in eCAVs.
• Accurate current measurement: It integrates our XENSIV TLE4973 Hall coreless current sensors in a compact and easy-to-mount Swoboda universal current sensor module.
• Custom Design Elements: The kit includes specially designed DC-link capacitors and a liquid-cooling system to maintain performance in challenging operating conditions.
• Component Integration: It features three FF900R12ME7 EconoDUAL(TM)3 IGBT7 power modules and 1ED3321MC12N EiceDRIVER  gate drivers, ensuring compatibility and ease of assembly.

The EconoDUAL(TM) Power Kit includes three industrial grading EconoDUAL(TM) 3 IGBT7 modules capable of handling high currents efficiently, as well as gate drivers mounted on gate drive boards with booster stages that ensure reliable operation in demanding applications. Additionally, this kit is equipped with an integrated cooling system, which prevents overheating and ensures thermal stability, and is optimized for 800 V systems, with all components, including busbars and capacitors, specifically tailored for high-voltage operation.

Application Development in commercial and agricultural vehicles 

The EconoDUAL(TM) Power Kit provides essential tools for addressing the challenges of designing and developing eCAVs. It is particularly suitable for light and medium-duty vehicles such as eBuses and medium-duty eTrucks, while also being applicable to other vehicle types like construction equipment and agricultural vehicles. Its integrated design and advanced components help streamline prototyping and development processes. Additionally, our 32-bit AURIX microcontrollers can be used to enhance the overall system design and ensure functional safety up to the highest ASIL D level. AURIX microcontrollers also offer integrated DS-ADC (delta sigma ADC) to enable a digital calculation of resolver positioning, eventually to replace external resolver IC e.g. Tamagawa, and reduce system complexity.

The microcontroller selection tree can be found below:

 

XENSIV TLE4973 current sensors, is based on TLE4973 core-less technology. It is highly accurate over temperature and lifetime due to high linearity, stray-field robustness and lack of hysteresis. There is also no need for magnetic concentrator nor a shield, achieving space optimization and design flexibility.

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Courtesy : Broadcom

Broadcom’s portfolio of automotive Ethernet switches are built not only for today’s automotive network, they’re scalable for the network of the future.

Automakers have used Broadcom’s standard automotive switches for more than a decade to route data between various sensors, processing units, and actuators within the vehicle. As automakers transition from domain-based to zonal architectures, pre-planning allows the architectures to scale to newer features and benefits.Software-defined vehicles, or SDVs, have the connectivity and processing power to secure, monitor, upgrade, and update vehicle capabilities. The software for different computing functions, such as driver assist, infotainment, body control, and instrumentation, can all be distributed across different boards and processors. Sensor data can flow to multiple zones/boards versus being directly connected. It is the scalability of Ethernet hardware that allows an SDV to be improved after purchase. So, what features should you look for in a switch to support SDVs?

Network Scalability for SDVs

The first item to examine is the type of system on chip, or SoC, that is being used for compute processing in your architecture. New classes of automotive SoCs allow application processing, real-time processing, AI compute, and safety functionality in a single device. Zonal and central compute electronic control units (ECUs) can take advantage of these scalable SoCs. These SoCs have multiple multi-gigabit interfaces to the network to gather and transmit all the data they need to process. For example, AI models for autonomous drive systems can be updated to improve camera recognition and safety. As new software features are added, the amount of data sent over these SoC interfaces will increase. Just as the SoCs are optimized and designed to scale over time to handle larger compute and network needs, the Ethernet network must be designed from the start to support future needs. The automotive Ethernet switch must support multiple connections to the SoCs at the maximum line rate needed. The switch should also be able to support the scalability of each interface from 1Gbps to 10Gbps. If the SoC supports PCIe interfaces with virtualization, then the switch needs to support virtualization as well.

As the software feature workloads get distributed between compute devices, there will be a need for network performance optimizations and time-sensitive provisioning. SDVs will collect data across the network for data analytics and health monitoring. The Ethernet switches will use their packet filters to monitor specific traffic flows at line rate. Captured motor efficiency data, Ethernet network health, and autonomous drive data for AI model improvement can all traverse the Ethernet backbone to the car’s cloud connection. Dynamic configuration of the automotive Ethernet switches allows the automaker to scale the needed resources efficiently over time. Automotive Ethernet switches need to have the bandwidth scalability and timing control to handle future network needs.

As port count requirements for an ECU increase, the automotive Ethernet switch chip must be able to handle all the ports with a single die. A switch chip that uses more than one smaller switch die in a single package can cause numerous issues. The stacking or cascading switch cores have higher latency as the Ethernet packets must be stored and forwarded through each switch die. The high-speed interface between these embedded dies becomes a bottleneck for traffic that must flow from a port on one die to the port on the other die. Time synchronization becomes trickier as multiple gPTP protocol stacks are run inside the single package. Scalability is a key feature enabled effectively with a monolithic die based switch.

As mentioned in our blog,”Securing software-defined vehicles with zonal E/E architectures,” protecting SDVs using zonal electrical/electronic architectures is critically important. The SDV architecture requires a multilayer security approach. The switches need to boot authenticated images securely, and they must allow only authenticated images to be loaded during over-the-air updates. Since software-based protection is challenging at faster Ethernet speeds, MACsec packet authentication and encryption allows line-rate protection in hardware at speeds up to 10 Gbps. In addition, both DOS protection and packet filtering are needed in hardware. Additional levels of protection can be taken in hardware that are unique to an automotive network architecture. An automotive network is fixed, unlike an SMB or enterprise Ethernet network. A port on the switch connected to a RADAR will always be connected to that RADAR in every car. If the unique address of the RADAR on an Ethernet packet is ever seen ingressing on another port, then it is known that someone is spoofing that address, and the port should be quarantined. The same can be said if a second address is seen on the RADAR port, as there should only be one device connected to that port. The security features should be implemented by dedicated hardware in the switch with software running on the internal processor subsystem handling any exceptions. This enables all of the security functionality at line rate and makes the intrusion detection and prevention software clients to be efficient and effective.

50G Auto Ethernet Switch Portfolio Expansion

In 2022, Broadcom unveiled the 50G automotive Ethernet switch product family to meet automakers’ needs and enable the future of SDVs. To drive mass adoption of SDVs, Broadcom is expanding the product family with a new cost-optimized 11-port version, the BCM89581MT. This device is a single die, lower-power, smaller-port count, 50G automotive Ethernet switch. To provide scalable flow of traffic, the BCM89581MT has multiple interfaces capable of 10Gbps connections to the latest SoCs and multi-gigabit automotive Ethernet PHYs. The high-speed interfaces can be 2.5G SGMII, USXGMII, PCIe Gen 4 single lane or XFI. This addition to Broadcom’s automotive Ethernet switch portfolio will allow for smaller port count central compute or zonal ECUs to fit into the SDV architecture. Broadcom’s automotive SDK can be seamlessly ported across the different family members.

Conclusion

The BCM89581MT enables original equipment manufacturers (OEMs) to realize the full network potential for smaller cost-optimized ECUs. With advanced security, scalable connections to SoCs, advanced time-synchronized networking features, and a full-feature SDK, the BCM89581MT easily allows the OEM to take advantage of the SDV features they need. Broadcom will showcase its expanded portfolio of 50G automotive Ethernet switches, including the new BCM89581MT, at the 2025 Automotive Ethernet Congress in Munich from February 18th-20th. Stop by our booth to learn more about our latest offerings and how our expanded portfolio of automotive Ethernet switch chips enable next-generation software-defined vehicles.

The post Broadcom drives mass adoption of software-defined vehicles with expanded Ethernet switch portfolio appeared first on ELE Times.

Courtesy : Onsemi

One secret behind the success of modern industrial automation is the power of 3D vision. Traditional 2D sensors can only provide flat images, creating limitations in their effectiveness in applications like device inspection. They can read a barcode which may contain the items’ dimensions but cannot independently gauge true shape and size, or any potential dents, defects or irregularities. In addition, 2D readings are at the mercy of lighting conditions, which may obfuscate or distort important areas of interest.

A breakthrough to these constraints can be done with depth sensing, processing the Z-axis in 3D, much like human vision. Now, depth cameras can tell the fullness of an object, perform precise inspections on devices, and even detect subtle facial features for applications such as access control. Thanks to these capabilities, 3D vision is a game-changer across industries – from defense and aerospace to medical, automotive and micro-technology. Whether it’s obstacle detection, facial recognition, self-driving or robotic assistants, depth sensing is the key to modern industrial automation.

Depth sensing, however of type, relies on active or passive visual protectionism. Depth sensing based on passive componentular requires highly calilytic stereo sensors and parallax, very similar to the human eye. Active sensing uses an emitted light beam towards their targets and uses the reflected energy to determine depth. This requires an energy emitter, but offers advantages like penetrating clouds/smoke, 24/7 operation and more deterministic operation.

There are several active directional techniques: direct time-of-flight (dToF), indirect time-of-flight (iToF), structured light and active stereo. Indirect time-offlight uses phase shift between the transmitted and received signals to calculate distance – it’s very accurate and the understanding hardware is simple.

In this blog you will learn about onsemi’s latest family addition, Hyperlux ID has made significant advances in iToF technology and these advances can be utilized to improve depth sensing in current industrial and commercial applications.

Existing iToF Technology Constraints Reduce Widespread Adoption

iToF sensing lies at the heart of many applications. One such popular application is face recognition as seen on various smartphones. However, this access control feature can only function at close range. Other applications that use iToF include machine vision (MV), robotics, augmented reality/virtual reality (AR/VR), biometrics and patient monitoring. Currently these applications are restricted to innulin use at close range (< 5m) with stationary objects that do not require high resolution. Several challenges restrict the potential scope of iToF technology. Among these are motion, the overhead and complexity of the hardware and data processing architecture and the need for meticulous calibration.

These significant hurdles either force engineers to implement complex 3D and expensive solutions to obtain depth, or simply to not acquire depth information at all. With remarkable innovations, onsemi introduces the Hyperlux ID family.

Hyperlux ID family that enables the benefits of iToF without previously noted restrictions. Hyperlux ID’s iToF implementation can now enable a more widespread adoption of this important technology.

Detailing the Hyperlux ID Advances

Onsemi’s Hyperlux ID sensing family initially consists of two 1.2 megapixels (MP) iToF products, the AF0130 and AF0131. This family provides advanced sensor performance and development in four critical areas:

1. Receiving reliable depth information with moving objects

Achieving optimal resolution/depth distance with high accuracy

3. Reducing cost and size
4. Decreasing calibration time

Each of the aforementioned areas and improvements are further detailed.

Momentum Motion Artifacts

To enable more widespread adoption, iToF sensors need to function well with moving objects, so they can produce accurate results without motion. As mentioned, iToF sensing on light reflections using four or more different phases to calculate depth. Nearly all existing iToF sensing solutions in the marketplace do not capture and process these phases simultaneously provide which issues with moving objects. Designed with a unique proprietary integration and readout structure, the Hyperlux ID depth sensor uses global shutter with on-chip storage and real-time processing to enable fast-moving object capture applications such as conveyor belt operation, robot arms, surveillance, collision collision, attachment detection and more.

iToF Applications in Warehouse Increased Resolution = Higher Accuracy and Expanded Depth

Most iToF sensors on the market today have only VGA resolution, which hinders their accuracy, and in turn, limits their applications. One reason VGA is more prevalent is due to the complex phase capture and data intensive processing mentioned prior. In contrast, the Hyperlux ID sensors are designed with 1.2 MP resolution (1280×960) using a high performance 3.5 μm back-side (BSI) pixel. As a product of its increased resolution over VGA, the Hyperlux ID sensor offers the additional critical advantage of expanded range depth. , at closer distances high-precision accuracy is provided and wider-angle optics can be used.

With higher resolution, the Hyperlux ID sensors also deliver improved quantum efficiency and reduced depth jitter. Taken together, these enhancements mean new applications for iToF sensors where high resolution and expanded depth are paramount, such as gesture recognition, quality control/inspection and access control.

Existing iToF solutions (left) vs onsemi’s new advanced Hyperlux ID iToF (right) Longer Range

As a product of increased resolution, the Hyperlux ID depth sensor can measure depth over a much greater range compared to other iToF sensors currently available. While current iToF offerings have an indoor range of less than 10 meters, the Hyperlux ID iToF sensor family can reach up to 30 meters. The usage of a high-performance global shutter pixel enables a full sensor array to closely align to active infrared lighting, which in turn limits noise provides from other infrared sources which are common indoor lights and most challenging of all – the sun.

Easier Calibration and Development

Accurately record and calculating phase differences in iToF sensors require precise calibration, an extremely time-consuming process. To ease this, we have developed a proprietary method that makes Hyperlux ID sensors easier to calibrate and thus faster to set up.

To aid in development, onsemi has constructed an easy-to-use development kit that includes a baseboard, a head sensorboard and a laser board. The kit can be used both indoors and outdoors with a range of 0.5 – 30 meters. It can produce depth maps, 3D point clouds, phase-out and depth-out data from an image.

Activated, by using spread-spectrum techniques many iToF (and other infrared-enabled devices) sensors can be used in the same system without worrying of other interference devices.

onsemi’s iToF Sensors Do More for Less

iToF sensors are excellent at making accurate 3D depth measurements, which have won them a solid place in industrial and commercial applications. With remarkable improvements in performance and design simplification, onsemi’s Hyperlux ID depth sensors open a new world of applications for iToF sensing depth.

Compared to iToF sensors on the market today, Hyperlux ID depth sensors work more effectively with objects in motion, outdoors and at greater distances. In addition, due to their novel design, Hyperlux ID depth sensors are more cost-effective, take up less board real estate and are easier to work with.

The Hyperlux ID family of depth sensors consists of two products: the AF0130 and AF0131. The AF0130 includes built-in depth processing while the AF0131 does not, for customers who prefer to use their own original algorithms.

The post Acquire the Current Challenges of Indirect Time-of-Flight (iToF) Technology with Technological Advancements appeared first on ELE Times.

Three new modems, purpose-built for IoT, bring an industry-first iSIM, cloud services and connectivity on NB-IoT and Cat 1bis networks for ubiquitous coverage.

The industrial Internet of Things (IIoT) is rapidly transforming industries, enabling businesses to achieve greater efficiency, productivity and visibility. However, deploying successful IIoT applications requires reliable connectivity, accurate positioning and cost-effective solutions. Three new modems from Qualcomm Technologies are purpose-built to address far-ranging use cases across industrial applications through an industry-first integrated SIM (iSIM), and LTE connectivity on Narrowband IoT (NB-IoT) and Cat 1bis networks, for coverage even in challenging signal environments.

The Qualcomm E41 4G Modem-RF

The Qualcomm E41 4G Modem-RF evolves IoT device capabilities by bringing integrated connectivity through an industry-first GSMA pre-certified iSIM. It offers device manufacturers the ability to simplify the device manufacturing process by reducing the need for additional parts and multiple models of the same device, helping accelerate the time to market of commercial devices, since those devices can be remotely provisioned to the desired network once manufactured through integrated connectivity capabilities. The E41 4G Modem-RF is also purpose-built for use with the Qualcomm Aware Platform so enterprises, OEMs, ODMs and developers can easily build, deploy and scale cloud-connected devices that can be tailored to solve various industrial challenges across businesses, through value-added, cloud-based services.

The Qualcomm E51 4G Modem-RF and Qualcomm E52 4G Modem-RF

Continuing the mission of advancing cellular connectivity for everyone and across every device, Qualcomm is proudly introducing a new generation of modem solutions for IoT, optimized for use on NB-IoT and Cat 1bis networks. Both the Qualcomm E51 4G Modem-RF and the Qualcomm E52 4G Modem-RF feature a highly integrated design that allows for power and cost optimizations for device manufacturers. These two low-power solutions contain an integrated power management unit, support for RF communications, and a rich array of peripherals.

The former of these two solutions also removes the need for dedicated GPS hardware through cloud-based GPS positioning services, further helping device manufacturers save on device costs, while reducing positioning error in open sky and dense urban environments. Regardless of which modem ODMs and OEMs choose, they can rest assured they can utilize low-power connectivity and intelligent power management capabilities, and NB-IoT or Cat 1bis connectivity, making these modems ideal for ultra-low power connectivity across a range of IoT devices including smart meters, smart city devices, intelligent parking solutions, healthcare devices, wearable devices, IP cameras, point-of-sale terminals and more.

Integrated global connectivity

The Qualcomm E41 4G Modem-RF and Qualcomm E52 4G Modem-RF are both Cat 1bis solutions that represent advancements in IIoT connectivity, including a breakthrough on the former of these modems, which features an industry-first, GSMA pre-certified iSIM solution that can be programmed during manufacturing or remotely via a SIM provisioning service. This will enable devices to more readily connect to a variety of cellular networks across the globe, thereby making it easier than ever for ODMs, OEMs, MNOs and MVNOs to integrate connectivity on devices across networks.

The potential applications for the E41 4G Modem-RF span across a variety of IoT devices, including smart meters that are placed in remote areas that have historically required frequent battery replacements or manual readings. Now, those meters can operate more efficiently by using integrated connectivity and remote management to send readings proactively over the air, and alert remote decision-makers when maintenance is needed.

Positioning in any environment

IoT devices are deployed in a variety of environments, including where location technologies have traditionally been challenged, such as indoor areas like warehouses and retail stores. The E41 4G Modem-RF uses several positioning techniques to address the needs of industrial IoT applications, including in these difficult signal environments, using ambient signals from existing Wi-Fi access points and cellular towers. Positioning can be achieved either directly through the modem, or through Qualcomm Aware Positioning Services, which adds cloud-based positioning services and available GNSS assistance, when paired with the all-new optional dual-band GNSS receiver, the Qualcomm QCG110. This is an ideal solution for positioning devices in open-sky environments that require precise positioning, using multiple constellations, in a power-conscious way.

With its variety of positioning technologies, the E41 4G Modem-RF provides a robust solution for IIoT applications including asset tracking and fleet management, energy and utilities, retail and mobile network operators, powering continuous asset visibility, monitoring and management capabilities even in the most challenging conditions.

Cost-conscious design

All three new modems will help device manufacturers simplify the development process and reduce the time and costs to develop devices through a highly integrated design architecture. Because the E41 4G Modem-RF incorporates iSIM technology directly into the hardware design, it reduces the total cost of assembling a device, since the cost of SIM card is included in the modem. OEMs are able to develop a single device model that can be remotely programmed to work in different regions around the globe and transform the traditional manufacturing model where it’s been necessary to build multiple models of the same device, each using a different SIM, to work with different connectivity providers across regions. By utilizing the E41 4G Modem-RF’s compact design, businesses can unlock the full potential of IIoT without compromising on quality or performance, and reduce design complexity.

Powering a variety of industrial uses

The capabilities of all three modems unlock a wide variety of possibilities across smart wearables in warehousing, industrial handheld devices in retail, smart metering in energy and utilities, guidance for autonomous robots across retail, warehouses and more.

In the energy and utilities sector, example uses for all three of these modems include:

• Improved operational efficiency and energy distribution on a localized grid level with reduced costs through less manual intervention.
• Long-lasting asset control capabilities for vital infrastructure, such as electric meters, through precise data collection and remote management capabilities.
• High temperature support allows devices to be deployed and used in harsh environments that are typical of energy and utilities space.
• IP cameras, wearable devices, smart meters and industrial handheld devices.

In the retail sector, examples of solutions the E41 4G Modem-RF can power include:

• Real-time inventory management and security-focused payment processing to point-of-sale systems and industrial handheld devices.
• On-device AI capabilities and advanced security surveillance functionality on IP cameras with real-time alerts and remote monitoring capabilities.

For autonomous robots in manufacturing, logistics and retail applications, the E41 4G Modem-RF provides:

• Precise positioning and connectivity, delivering efficient navigation and automation.
• Low-latency and security-focused processing for enhanced reliability during use.

At its core, the integrated and compact design of these three modems supports a wide range of IoT applications that demand both precise, low-power positioning and seamless connectivity, within a single, versatile design that can be selected depending on the target application, empowering businesses across multiple industries to achieve growth and seize new opportunities.

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Future-proof quality assurance for power electronics through sintering paste inspection with multi-line SPI

Higher operating temperatures, thinner interconnection layers, 10 times the longevity – the advantages of sintering pastes over solder pastes have long been recognized in the field of power electronics. Not least for this reason, sintering pastes are preferred in system-critical technologies such as “green energy” and e-mobility. Here, for example, IGBTs have become the central component in converters for all types of electric drives: wind turbines, solar power generation, battery charging – hardly any future technology would be conceivable without the “all-rounder” sintering paste. However, sintering is more prone to errors than soldering paste printing. Furthermore, defects are more difficult to detect and rectify – critical failures in the field are the result. To avoid this, GÖPEL electronic has now added an inspection system specifically for sintering paste to its Multi Line platform.

The Multi Line SPI is a cost-effective 3D inline system for automated inspection of sintering paste. Based on the Multi Line platform, it is a customized solution for small and medium-sized companies with high quality standards; it can also be used for solder pastes. The telecentric 3D camera module is used to inspect solder and sinter paste without shadows for shape, area, coplanarity, height, bridges, volume and X/Y offset. Equipped with two digital fringe projectors for shadow-free 3D image capturing, it has a resolution of 15µm/pixel, a height measurement accuracy of 1µm and a height resolution of 0.2 µm. This means that measurement values can be obtained precisely and repeatedly.

Generation of an inspection program for sinter paste inspection takes only a few minutes: CAD data or a reference layout is sufficient. Users who already use GÖPEL electronic software for programming SMD, THT or CCI systems can learn the additional sinter paste functions with little training. In addition, the data import, verification and statistics software are identical to the other inspection systems from GÖPEL electronic. This is where the platform concept of the Multi Line series really pays off: the uniform, powerful operating and evaluation software across all devices reduces training and programming effort, enabling flexible and optimized staff deployment planning.

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