ELE Times

Rohde & Schwarz presents the new R&S UDS digital multimeter series. The compact instruments can display three measurements simultaneously and offer versatile measurement functions and various interfaces for remote control. Models are available with a digit resolution of 5 ½ as well as 6 ½, the latter providing a basic DC accuracy of 0.0075 percent. The R&S UDS series replaces the established R&S HMC8012 digital multimeter, offering more accuracy and an updated intuitive user interface for smooth and efficient testing.

The new R&S UDS digital multimeters from Rohde & Schwarz offer a versatile range of testing capabilities, making them ideal for troubleshooting, component testing, and system validation applications, as well as for teaching labs in education. Additionally, they are well-suited for production environments, where reliability and accuracy are paramount. With voltage ranges extending up to 1000 V DC and 750 V AC and a current capacity of 10 A, these multimeters provide a comprehensive solution for a wide range of measurement tasks. They come with an easy-to-use interface and a 3.5” OVGA color display for excellent readability. The large screen can simultaneously display up to three measurement values, streamlining test workflows and enhancing productivity.

Advanced Measurement Capabilities

In addition to twelve standard measurement functions, the multimeters feature built-in statistical and mathematical functions, making them suitable for a wide range of applications, including two-wire and four-wire measurements, as well as limit testing.

For remote control, the new multimeters offer a variety of interfaces, including USB, IEEE-488 (GPIB) for SCPI-based commands, and LAN (Ethernet). This enables seamless integration of the R&S UDS digital multimeter into any test setup or production line, providing unparalleled flexibility and convenience.

As the well-established R&S HMC8012 digital multimeter is being phased out, the new R&S UDS series will take its place.

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Quectel Wireless Solutions, a global IoT solutions provider, has launched the Quectel KCM0A5S, a high-performance Wi-SUN module designed for smart applications such as street lighting, precision agriculture, industrial IoT, smart meters and smart cities. Based on Silicon Labs EFR32FG25, a sub-GHz low power wireless System on Chip, and featuring an ARM Cortex-M33 processor with a frequency of up to 97.5MHz, the module includes built-in 256KB RAM and 2MB Flash memory, ensuring efficient performance.

The Quectel KCM0A5S supports the Wi-SUN Field Area Network (FAN) 1.1 protocol and operates across the 470–928 MHz frequency range. The module utilizes IPv6-based wireless mesh networking technology, intrinsic to the Wi-SUN communication standard, to deliver long-range transmission, stable network connectivity and reliable data transmission. Furthermore, the KCM0A5S offers flexible deployment capabilities, supporting both router and leaf node configurations in standalone SoC mode, as well as acting as a border router when paired with a Linux host in RCP (Radio Co-Processor) mode. This versatility makes it an ideal solution for a wide range of mesh networking applications in smart city, utility, and industrial IoT deployments. In addition, the KCM0A5S features strong anti-interference capabilities and delivers excellent signal penetration which is of specific value for use cases in hard-to-reach locations. With a minimum of ten years product lifecycle and cross-version compatibility, the solution ensures long-term interoperability within Wi-SUN FAN networks.

We’re delighted to launch the Quectel KCM0A5S Wi-SUN module,” said Delbert Sun, Vice General Manager, Product Department, Quectel Wireless Solutions. “Wi-SUN is a versatile LPWA connectivity technology that is applicable globally to a wide range of use cases. Its security, scalability and robustness provide compelling advantages to developers and device designers and the KCM0A5S adds to this with its ultra-compact form factor, high speed bandwidth and low latency. We look forward to helping customers to build a smarter world with the KCM0A5S as they bring the latest Wi-SUN enabled devices to market.

Flexibility for developers and designers is assured thanks to the KCM0A5S’s ultra-compact LCC form factor. Dimensions of 28.0mm x 22.0mm x 3.15mm enable the size and cost of end products to be optimized, allowing for maximized design options. The module is also ideal for industrial-grade use cases with an operating temperature range of -40 °C to +85 °C. The module is available in variants that support a peak transmit power of 30 dBm—currently permitted in select regions such as North America, Latin Ameria and some APAC countries —and offers both OFDM and FSK modulation schemes, subject to regional regulatory allowances.

Wi-SUN has been gaining traction for connecting IoT devices as a low power wide area (LPWA) connectivity solution because of its blend of scalability, security, interoperability and performance. It offers high speed bandwidth at up to 2.4Mbp with OFDM modulation. The technology is easily expandable and can support thousands of nodes. WI-SUN’s self-forming and self-healing mesh eliminates single point of failure networks and simplifies deployment.

The combination of wide coverage, long distance of several kilometers and the ability to serve urban scenarios, covered by multi-hop mode is seeing Wi-SUN adopted for smart metering and smart city applications. For example, a control management system for street lighting, utilities and parking has been deployed in London that utilizes 15,000 Wi-SUN devices and 12 Wi-SUN border routers to enable real-time remote management and provide a future-proof system that can scale up as the city transitions to new infrastructure.

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Rohde & Schwarz is set to revolutionize the field of signal and spectrum analysis with the launch of the FSWX signal and spectrum analyzer, an innovative instrument designed to overcome the limitations of current measurement methods.

Rohde & Schwarz introduced the brand-new FSWX signal and spectrum analyzer, the first multichannel signal and spectrum analyzer with multiple input ports, unlocking new possibilities in signal analysis. It is also the first instrument of its kind with a cutting-edge internal multi-path architecture enabling a novel cross-correlation feature. Combined with its low phase noise for high signal purity, its spurious-free dynamic range and its outstanding residual EVM, the FSWX delivers an RF performance like no other signal and spectrum analyzer in the market.

The instrument’s wide internal bandwidth of 8 GHz allows for comprehensive analysis even of complex waveforms and modulation schemes. Combined with a high measurement speed and analysis tools tailored to the user’s needs, the FSWX brings new levels of performance and precision to signal analysis for modern RF applications – from active RF components testing to state-of-the-art automotive radar testing to complex airborne radar scenarios and satellite test in A&D applications to the latest test challenges in WLAN and cellular technologies like 5G and beyond.

Michael Fischlein, Vice President Spectrum & Network Analyzers, EMC & Antenna Test at Rohde & Schwarz, is thrilled to introduce the new FSWX: “Our team has truly re-imagined signal and spectrum analysis technology with our new FSWX. They have come up with an innovative architecture and design to empower our customers to tackle complex measurement scenarios in the evolving landscape of wireless communications and radar technology that were previously unattainable. In other words, the FSWX makes measuring the impossible, possible.” The instrument’s innovative design features include multiple input ports, cross-correlation capabilities, advanced filter banks and broadband ADCs.

Multiple input ports

The multichannel FSWX offers the ability to measure multiple signal sources simultaneously, regardless of whether they operate at the same or different frequencies. With synchronous input ports, each featuring 4 GHz analysis bandwidth, users can seamlessly analyze the interactions between diverse signals. This opens up a multitude of new measurement scenarios, for instance, phase-coherent measurements of antenna arrays used in beamforming for wireless communications as well as in airborne and automotive radar sensors.

Multi-path architecture and cross-correlation

Its advanced internal multi-path architecture allows for the cross-correlation mode, a novel feature of the FSWX. A single signal input is internally split into two independent signal paths, each equipped with its own local oscillator and ADC. With this innovative design, advanced cross-correlation algorithms can be applied in the digital backend, effectively removing the inherent noise of the measurement instrument. This feature reveals spurs not easily seen without cross-correlation. It is especially helpful when, for instance, measuring Error Vector Magnitude (EVM), a critical factor in mobile communications. The added wideband noise of traditional signal and spectrum analyzers limits the accuracy and dynamic of EVM measurements. With the cross-correlation feature, however, the FSWX provides an unobstructed view of the DUT for precise EVM analysis.

The internal multi-path architecture also offers advanced triggering options. For example, users can apply an IF or RF power trigger at distinct frequencies, as the multi-path design allows for independent frequency settings for each receive path behind the splitter. This way, the FSWX can easily reveal effects between two RF signals.

Advanced filter banks and broadband ADCs

Traditionally, for preselection in the microwave range, spectrum analyzers rely on YIG filters. Since they are known for their challenging frequency response, YIG filters need to be bypassed for wideband signal analysis. The FSWX, however, employs broadband ADCs in conjunction with filter banks that span the entire operating frequency range, allowing for pre-selected signal analysis while eliminating the need for YIG filters. The filter banks provide high precision, optimizing instrument settings for specific applications and significantly reducing the risk of unwanted signal images contaminating results. For users requiring narrowband applications, a YIG filter can still be added optionally.

Innovative firmware applications

The FSWX also provides innovative firmware applications such as the CrossACT (Cross Application Control and Triggering) firmware feature. It synchronizes various measurements across different input channels, allowing for simultaneous analysis with multiple tools. This capability simplifies comparisons, such as determining whether the higher harmonics of a radar signal directly impact the EVM performance of a 5G signal.

The Linux-based operating system of the FSWX provides a high level of security and long-term support, essential features for users in security-sensitive environments. This robust operating system ensures reliability and stability, making the FSWX an ideal choice for demanding applications.

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Author: Mr. Saleem Ahmed, Officiating Head, ESSCI

In the next ten years, India will witness a tectonic shift in its technological landscape, one that will decisively shape the nation’s economic destiny and global standing. At the heart of this transformation lies the semiconductor industry, often referred to as the “new oil” in the global economy. For Indian engineers, the semiconductor revolution isn’t just a story of factories and chips—it’s a gateway to high-value, future-ready careers that promise innovation, growth, and national impact.

With multiple large-scale semiconductor fabrication and assembly projects underway, and policy support at an all-time high, semiconductor jobs are rapidly becoming the next big thing for engineering talent in India. And at the forefront of this workforce transformation stands the Electronics Sector Skills Council of India (ESSCI)—tasked with equipping the Indian workforce for this high-tech future.

A Nation on the Verge of a Chip Revolution

India’s dependence on imported chips—used in everything from mobile phones to fighter jets—has long been a strategic vulnerability. But that reality is now changing. Recently Union Cabinet’s approved  approved a new semiconductor plant in Uttar Pradesh’s Jewar to be jointly set up by HCL Group and Foxconn. The newly approved facility will come up at an investment of Rs 3,700 crore.

This is the sixth unit approved under the India Semiconductor Mission, with five semiconductor facilities in advanced stages of construction. Three of these units—by Micron Technologies, Kaynes Technologies and a combination of CG Power-Renesas Electronics and Star Microelectronics—are based in Sanand, Gujarat. The Tata Group is building one semiconductor facility in Dholera, Gujarat and another in Assam.

These developments are backed by the Government of India’s India Semiconductor Mission (ISM), a ₹76,000 crore policy initiative that provides incentives for design, manufacturing, and packaging of semiconductor chips.

This growing ecosystem will need a massive talent pool—and that’s where India’s engineers come in.

Why Semiconductors Are a Game-Changer for Engineers

Semiconductors power almost every modern device—from smartphones and laptops to electric vehicles, smart appliances, 5G infrastructure, defense systems, and even satellites. As the world shifts toward AI, IoT, and smart mobility, the demand for chips is set to explode. According to recent estimates, India’s semiconductor market will triple in size—from US$22.7 billion in 2019 to over US$80 billion by 2028.

This explosion is not just about demand—it’s about job creation.

According to ESSCI’s analysis, the semiconductor industry is set to witness a dramatic rise in employment demand. The sector, which is projected to employ 1.70 lakh individuals by 2025, is expected to rise to 1.87 lakh in 2026, and add a total of 1.03 lakh new jobs by 2030. This includes roles in chip design, fabrication, testing, quality control, equipment maintenance, and advanced manufacturing processes.

The rapid expansion of this sector has created an urgent need for a highly skilled workforce. ESSCI is committed to bridging the skill gap through targeted training programs, collaborating with industry and academia to equip young professionals with expertise in chip design, fabrication, and advanced packaging. These initiatives will empower the next generation to drive India’s semiconductor revolution.

Such roles are not only high-paying but also globally portable, offering Indian engineers access to both domestic and international job markets.

The Many Doors Semiconductor Jobs Open

The semiconductor industry is uniquely interdisciplinary, requiring expertise in electronics, mechanical, chemical, computer science, materials engineering, and more. Here’s a breakdown of the top career tracks Indian engineers can pursue:

1. Design Engineers

Design engineers work on creating the architecture and layout of chips. They use Electronic Design Automation (EDA) tools to ensure chips are efficient, reliable, and ready for fabrication.

2. Process Engineers

These engineers fine-tune the manufacturing process, often working in cleanroom environments. They handle wafer processing, lithography, etching, doping, and deposition.

3. Packaging and Testing Experts

Once chips are fabricated, they need to be tested, assembled, and packaged. Engineers in this field ensure performance and durability under various operating conditions.

4. R&D Scientists

Research roles offer cutting-edge work in developing new semiconductor materials like gallium nitride or silicon carbide, and technologies like FinFET or EUV lithography.

5. Equipment and Maintenance Technicians

Fabrication units run on precision equipment that needs constant monitoring and maintenance—critical work for mechanical and electronics engineers.

6. Quality and Safety Officers

Given the strict standards in chip manufacturing, QA engineers ensure compliance, while safety experts handle protocols in chemical and electrical hazards.

Enter ESSCI: Building the Backbone of India’s Semiconductor Workforce

With this exponential growth comes the challenge of creating a skilled and job-ready workforce. The Electronics Sector Skills Council of India (ESSCI), under the aegis of the Ministry of Skill Development and Entrepreneurship, plays a crucial role in bridging this gap.

ESSCI has already developed 25 NSQF-aligned qualifications for semiconductor design, packaging, and manufacturing. These qualifications are designed to cater to:

• Engineering graduates seeking specialization
• Diploma and ITI students entering the job market
• Working professionals seeking upskilling or domain switch

ESSCI offers focused a range of qualifications covering the complete value chain of the semiconductor industry. Short Term courses such as VLSI Design Engineer, concentrating on designing SOC-module functions using software, Embedded Full Stack Engineer, IoT Hardware Analyst are some of the top courses offered for pursuing engineering graduates to gain the knowledge of EDA Tools and system design. ESSCI also provides qualifications for Wafer Back Grinding Engineer and Wafer Dicing Engineer, specialising in wafer manufacturing tasks which can be taught to ITI / Diploma students. ESSCI also has foundation / upskilling courses in the field of Nano Science & Advance Nano Science which is also in great demand. Also, there are some basic courses on the Industrial Safety – Electrical & Hazchem which are very crucial & important for the industrial safety requirements.

Career Opportunities in Semiconductor Technology:

As the semiconductor industry evolves in response to these mega trends, it creates exciting career opportunities for professionals across the value chain – designing, fabrication and packaging. From semiconductor design and manufacturing to research and development, there is a growing demand for skilled professionals who can innovate and drive technological advancements in the industry.

The sector is expected to see more than 800,000 to 1 million job openings over the next five years, says staffing company Randstad. The government recently approved $15 billion worth of investments into the sector including from the Tata group. India’s burgeoning semiconductor sector is facing a surge in demand for talent, fuelled by new investments and the government’s ambitious plan to transform the country into a chip manufacturing hub.

1. Semiconductor Design Engineer:Semiconductor design engineers play a crucial role in developing the architecture and circuitry of semiconductor chips. They utilize tools like Electronic Design Automation (EDA) software and simulation tools to design and optimize chip layouts for performance, power efficiency, and manufacturability.
2. Process Engineer:Process engineers are responsible for developing and optimizing semiconductor manufacturing processes. They work closely with equipment vendors and manufacturing teams to ensure the smooth operation of semiconductor fabrication facilities, improve yield rates, and reduce production costs.
3. Research Scientist:Research scientists in the semiconductor industry focus on exploring new materials, devices, and technologies to push the boundaries of semiconductor innovation. They conduct experiments, analyze data, and collaborate with cross-functional teams to develop next-generation semiconductor solutions.
4. Material Engineers:Material engineers in the semiconductor industry are pivotal in researching, selecting, and optimizing the materials used in semiconductor device fabrication. Their expertise spans a wide range of materials, including silicon, gallium arsenide, and various compound semiconductors. Material engineers work closely with semiconductor design teams to ensure that the chosen materials meet the performance requirements of the intended applications while also considering factors such as cost, scalability, and reliability. Additionally, they play a crucial role in developing new materials and processes to push the boundaries of semiconductor technology, enabling advancements in areas such as miniaturization, power efficiency, and functionality.
5. Product Marketing Manager:Product marketing managers play a vital role in bringing semiconductor products to market. They conduct market research, develop marketing strategies, and collaborate with sales teams to promote semiconductor products and drive revenue growth.
6. Quality Assurance Engineer:Quality assurance engineers ensure that semiconductor products meet the highest standards of quality and reliability. They develop and implement test plans, conduct performance testing, and analyze data to identify and address any issues or defects in semiconductor products.
7. Packaging experts:Packaging experts in the semiconductor industry are instrumental in developing and implementing packaging solutions that safeguard semiconductor chips. Their role entails meticulous selection of packaging materials, designing efficient packaging structures to ensure protection against environmental factors and mechanical stresses, and optimizing designs for thermal management and electrical performance. They collaborate closely with design and manufacturing teams to ensure that packaging solutions meet stringent industry standards while balancing factors such as cost-effectiveness and manufacturability.
8. Clean room specialists:They play a pivotal role in maintaining the pristine conditions necessary for semiconductor fabrication processes. They are responsible for meticulously managing and monitoring cleanroom environments to prevent contamination that could compromise the quality and reliability of semiconductor devices. Clean room specialists enforce strict cleanliness protocols, perform regular inspections, and oversee cleaning procedures to ensure compliance with industry standards and regulations. Their expertise ensures that semiconductor manufacturing facilities operate in controlled environments conducive to high-quality production.
9. Machine maintenance technicians:They are essential for sustaining the operational efficiency and reliability of semiconductor manufacturing equipment. Their responsibilities include conducting routine maintenance tasks, performing diagnostics, troubleshooting equipment issues, and executing repairs as needed to minimize downtime and optimize production throughput. Machine maintenance technicians also play a crucial role in implementing preventive maintenance schedules, identifying opportunities for equipment upgrades or optimizations, and ensuring compliance with safety regulations and operational standards. Their expertise contributes to the overall efficiency and longevity of semiconductor manufacturing operations.
10. Safety protocol checkers:These people are integral to maintaining a safe and secure work environment within semiconductor manufacturing facilities. They are responsible for enforcing safety regulations, conducting regular inspections to identify potential hazards, and implementing corrective measures to mitigate risks and prevent accidents. Safety protocol checkers also play a vital role in developing and implementing safety training programs, conducting safety audits, and promoting a culture of safety awareness among employees. Their diligence and vigilance help to safeguard the well-being of personnel, protect semiconductor manufacturing equipment, and maintain the integrity of semiconductor processes.

Career Opportunities Across the Ecosystem

• Global Semiconductor Giants: Intel, Micron, AMD, Qualcomm, NXP
• Indian Startups & Design Houses: Saankhya Labs, Steradian Semiconductors, Signalchip
• Manufacturing Units: Tata Group, Vedanta-Foxconn, ISMC
• Government & Defense: DRDO, ISRO, SCL (Semiconductor Lab)
• Academia & R&D: IITs, IIITs, National Labs

India’s Policy Ecosystem: Creating the Right Conditions

India’s semiconductor journey isn’t just market-driven—it’s backed by clear, consistent policy action:

• Production Linked Incentive (PLI) Scheme to support manufacturers.
• Design Linked Incentive (DLI) Scheme for fabless startups and institutions.
• Modernization of the Semiconductor Laboratory (SCL) in Mohali into a full-fledged fab.
• State-level incentives, like Odisha’s offer of 25% subsidy on capex for fabs and 20% for fabless companies.

Moreover, global giants like Applied Materials, Lam Research, and Samsung Semiconductor India Research (SSIR) are expanding operations in India—indicating long-term confidence in India’s talent and policy framework.

A Strategic Moment for Indian Youth

The rise of India’s semiconductor sector presents a rare, perhaps once-in-a-generation, opportunity. Engineers who upskill today can become:

• The designers of India’s next chip
• The technicians behind India’s first fab line
• The entrepreneurs launching fabless startups
• The leaders driving India’s tech sovereignty

At a time when countries are scrambling to secure chip supply chains, India is carving a unique place for itself—not just as a consumer but as a creator. But this vision hinges on talent.

That’s why engineers—especially young graduates and final-year students—must look seriously at semiconductors. With government support, ESSCI’s training programs, and private sector momentum, the time to act is now.

Conclusion: From Potential to Powerhouse

India is no longer at the sidelines of the global chip race. With strong policy, infrastructure investment, and a strategic location, it is emerging as a serious contender. But no chip factory can run without engineers. The success of India’s semiconductor mission will ultimately depend on its people—its skilled, driven, and future-ready engineers.

The post Why Semiconductor Jobs Are the Next Big Thing for Indian Engineers appeared first on ELE Times.

Anritsu expands its signal generator product line with the introduction of the EcoSyn Lite Microwave Synthesizer Module that delivers outstanding phase noise, ultra-fast switching speed and compact size. EcoSyn Lite compliments Anritsu’s high performance RubidiumTM bench top signal generators to address a wide range of signal generator applications.

EcoSyn Lite covers 10 MHz to 20 GHz frequency range and delivers +18 dBm output power. Housed in a portable, compact 4 inch x 4 inch x 0.8 inch form factor ideal for use in space constrained applications which require instrumentation grade CW signal source.

Instrument Class Phase Noise in Module Form Factor

EcoSyn Lite features best in class phase noise performance of -126 dBc/Hz (typical) at 10 GHz and 10 kHz offset, that compares favorably with some of the bench top signal generators in the market today. With its robust output power of up to +18 dBm it is ideal as LO for up/down converters in RF/Microwave transceivers. These transceivers increasingly use complex and high order modulation signals which require LOs with low phase noise for up/down conversion. EcoSyn Lite’s superior non-harmonic spurious of -60 dBc delivers very low jitter and can be used as a clock source for Gbit ADC/DAC testing and in high-speed optical systems.

Ultra-fast Frequency Switching Speed

EcoSyn Lite has ultra-fast frequency switching time of less than 50 µs in Triggered list mode. In ATE (Automatic Test Equipment) application, fast frequency switching speed saves testing time. Shorter test times translate to higher test throughput thus achieving less test cost. Ultra-fast switching time and small form factor makes EcoSyn Lite ideal in ATE rack applications.

Switching speed can also be critical in radar cross section (RCS) measurements necessary to establish radar signatures for known targets, such as aircraft, ships, and missiles. These signatures are created through measurements at thousands of frequencies. Because of the total numbers of measurements that must be made, EcoSyn’s ultra fast switching time can save considerable measurement time. Testing an antenna also requires large amounts of data at multiple frequencies. EcoSyn Lite’s ultra-fast switching speed can save a lot of testing time.

Efficient, compact and Easy to Automate

EcoSyn Lite synthesizer modules are housed in portable, compact 4 in x 4 in x 0.8 in form factor which enables them to be used in space constrained applications which require instrumentation grade CW signal source. It supports USB and SPI interfaces for remote control and is powered using a +12 VDC source.

EcoSyn Lite supports standard SCPI and QuickSyn native commands which make developing scripts to remotely control and automate very easy and user friendly.

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The Central government has introduced major reforms to Special Economic Zone (SEZ) Rules to push India’s aspirations in semiconductor and electronics manufacturing, with the aim of drawing global investments and minimizing procedural bottlenecks for high-tech sectors. The Ministry of Commerce & Industry said that these measures are going to change India’s industrial policy scenario where SEZs shall henceforth be more accessible and investment-friendly.

Major Policy Changes to SEZ Norms

Amendment on Rule 5 of the SEZ Rules, 2006, is among the landmark reforms, which includes the minimum land size to be established for a semiconductor or electronic component-specific SEZ being curtailed from 50 hectares to just 10. This is expected to benefit the smaller yet highly potential players and thus fast-track building advanced manufacturing hubs.

Another important change is Rule 7, which gives more latitude in acquiring and using land. There will no longer be an encumbrance-free clause attached to mortgaging or leasing land to federal or state government agencies. This will ease a significant regulatory hurdle faced by developers and investors.

In Rule 53, a new method to compute Net Foreign Exchange (NFE) has been introduced so as to include goods being received or supplied free of cost, if such valuation is carried out as per the customs valuation norms. This will align India’s SEZ policy with global best practices and allow easier trade reporting by SEZ units.

On the other hand, Rule 18 has been amended to enable the sale of goods from SEZs into the Domestic Tariff Area (DTA) on payment of the applicable duties. This upgrade will offer enhanced flexibility to the SEZ manufacturers, as well as improve viability of commercial operations by extending market access across the country.

Focus on Capital-Intensive, Long-Gestation Sectors

These strategic reforms notified by the Department of Commerce on June 3, 2025, will be targeted toward industries with higher capital investment needs and long development time frames-such as semiconductor fabrication and advanced electronics.

By minimizing the compliance cover and raising operational flexibility, the government would like to induce global majors and homegrown innovators to invest in the evolving high-tech landscape in India.

The policy shift would also aid job creation, particularly in areas, that are highly skilled. Amongst the jobs created would be those requiring skills in chip design, fabrication engineering and electronics system manufacturing.

Early Gains: Two Major SEZ Projects Approved

In a speedy follow-up to the announcement, the Board of Approval for SEZs has cleared two proposals of major import intended to create the desired impact of the reform:

• Micron Semiconductor Technology India Pvt Ltd would construct a semiconductor LRD of SEZ at Sanand, Gujarat, 37.64 hectares in extent, with an investment commitment of ₹13,000 crore. This unit would become one of the biggest nodes in the Indian-chip making landscape.
• The Hubballi Durable Goods Cluster Pvt Ltd, promoted by Aequs Group, would set up an electronics components SEZ at Dharwad, Karnataka, spread over an area of 11.55 hectares, with an investment of about ₹100 crore.

Such approvals speak of the desire of the government to swiftly translate the policy into action and brand India as reliable partner in the global semiconductor value chain.

Strengthening India’s Global Competitiveness

Due to the soaring worldwide demand for semiconductors and electronics as digital transformation and geopolitical realignments take place, India positions itself, almost by way of strategy, as an option for manufacturing. The new SEZ framework enhances ease of doing business and gives credence to India’s claim to become a self-reliant, technology-driven economy.

These are the steps towards building a strong semiconductor ecosystem, one offering innovativeness, resilience and global relevance.

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Pick and Place Friendly Lead Bending Option Allows Devices to Be Used as SMD Components to Reduce Assembly Costs

Vishay Intertechnology, Inc. announced that its AC03-CS series of axial cemented, leaded wirewound safety resistors is now available with a pick and place friendly lead bending option, the WSZ lead form, which allows the devices to be used as surface-mount components to reduce assembly time and lower costs.

Vishay Draloric AC03-CS series resistors act as inrush current limiting resistors during normal operation and serve as pre-charge, discharge, and snubber resistors. The devices are designed to ensure safe and silent fusing in automotive electronics, energy meters, and power supplies for industrial drives and consumer appliances when high DC voltage overload or accidental AC mains voltage of 120 VRMS / 240 VRMS is applied.

For challenging operating conditions, the devices operate over a wide temperature range from -40 °C to +200 °C and feature a robust, non-flammable silicone cement coating that conforms to UL 94 V-0. This coating allows the resistors to safeguard the PCB and other components by minimizing the risk of fire due to extreme electrical overloads, without the need for additional fuses in series.

The AEC-Q200 qualified AC03-CS series features a high surge voltage capability up to 4 kV (1.2/50 µs pulse per IEC 61000-4-5) and a power rating of 3 W at an ambient temperature of 40 °C. The devices offer resistance from 1 Ω to 100 Ω, resistance tolerance of ± 5 %, and temperature coefficient (TCR) of ± 200 ppm/K. RoHS-compliant, halogen-free, and Vishay Green, the resistors feature tin-plated terminations for compatibility with lead (Pb)-free and lead (Pb)-containing soldering processes.

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New MCUs Are Ideal for Portable Devices such as Data Loggers and Charge Cases

Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, introduced the RA2L2 microcontroller (MCU) group with ultra-low power consumption and the industry’s first support for the new UCB-C Revision 2.4 standard. Based on a 48-MHz Arm Cortex M23 processor, the new MCUs offer a rich feature set that makes them ideal for portable devices and PC peripherals such as gaming mice and keyboards.

The new USB Type-C Cable and Connector Specification Release 2.4 has reduced voltage detection thresholds (0.613V for 1.5A source, and 1.165V for 3.0A source). The RA2L2 MCUs are the industry’s first MCUs to support these new levels.

The RA2L2 MCUs employ proprietary low-power technology that delivers 87.5 µA/MHz active mode and software standby current of just 250nA. They also offer an independent operating clock for the low-power UART, which can be used to wake up the system when receiving data from Wi-Fi and/or Bluetooth LE modules. Along with the USB-C support, this combination of features makes the RA2L2 the premier solution available for portable devices such as USB data loggers, charge cases, barcode readers and other products.

In addition to USB-C with CC detection up to 15W (5V/3A) and USB FS support, the new MCUs offer LP UART, I3C, and CAN interfaces, giving designers the ability to reduce component count, saving cost, board-space and power consumption.

The RA2L2 MCUs are supported by Renesas’ Flexible Software Package (FSP). The FSP enables faster application development by providing all the infrastructure software needed, including multiple RTOS, BSP, peripheral drivers, middleware, connectivity, and networking as well as reference software to build complex AI, motor control and cloud solutions. It allows customers to integrate their own legacy code and choice of RTOS with FSP, thus providing full flexibility in application development. The FSP eases migration of existing IP to and from other RA devices.

“The RA2L2 Group MCUs are our first to realize full-speed USB along with USB-Type C connector support. They also ensure system costs remain low by reducing external components, and they offer the same low-power characteristics as our popular RA2L1 devices,” said Daryl Khoo, Vice President of Embedded Processing Marketing Division at Renesas. “These new devices demonstrate our commitment and ability to quickly deliver the solutions our customers require.”

Key Features of the RA2L2 MCUs

• Core: 48 MHz Arm Cortex-M23
• Memory: 128-64 KB Flash, 16 KB SRAM, 4 KB Dataflash
• Peripherals: USB-C, USB-FS, CAN, Low Power UART, SCI, SPI, I3C, I2S, 12-bit ADC (17-channel), Low Power Timer, Real-Time Clock, High-Speed On-chip Oscillator (HOCO), Temp Sensor
• Packages: 32-, 48- and 64-pin LQFP; 32- and 48-pin QFN
• Security: Unique ID, TRNG
• Wide Ambient Temperature Range: Ta = -40°C to 125°C
• Operating Voltage: 1.6V – 5.5V; USB Operating Voltage: 3.0V to 3.6V

Winning Combinations

Renesas has combined the new RA2L2 MCUs with numerous compatible devices from its portfolio to offer a wide array of Winning Combinations, including USB Data Logger, Electronic Toll with GNSS, Gaming Keyboard and Gaming Mouse. These designs are technically vetted system architectures from mutually compatible devices that work together seamlessly to bring an optimized, low-risk design for faster time to market. Renesas offers more than 400 Winning Combinations with a wide range of products from the Renesas portfolio to enable customers to speed up the design process and bring their products to market more quickly.

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Infineon Technologies AG is launching the XENSIV TLE4802SC16-S0000, an inductive sensor designed to enhance performance in automotive chassis applications. The sensor enables high-precision torque and angle measurements with robust stray field robustness, supporting digital output via SENT or SPC protocols. It achieves highly accurate sensing without needing additional shielding. Tailored for use in electric power steering systems, including torque and steering angle sensors, as well as pedal and suspension applications, the sensor offers both flexibility and reliability.

The XENSIV TLE4802SC16-S0000 combines a coil system driver, signal conditioning circuits, and a digital signal processor (DSP) in a single package. The sensor includes overvoltage and reverse polarity protection and comes in a RoHS-compliant and halogen-free surface-mounted TSSOP-16 package. It is qualified to AECQ100, Grade 0, for operation across a wide temperature range from -40°C to 150°C. Furthermore, the sensor is fully compliant with ISO 26262, making it ideal for safety-critical systems. A built-in cybersecurity function protects the system communications against man-in-the-middle attacks. The TLE4802SC16-S0000 is the first in a new family of inductive sensors, with further variants planned for release.

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Anritsu Company will exhibit cutting-edge high-speed signal integrity solutions at the PCI-SIG Developers Conference from June 11-12 in Santa Clara, CA. Anritsu will present PCI-Express  6.0 and 7.0 live demonstrations of the industry-leading MP1900A BERT in collaboration with Synopsys, Teledyne LeCroy, CIG, and Tektronix.

Live Demonstrations

World’s First PCI-Express 6.0 Link Training over Optics

Anritsu is joining forces with Synopsys, Tektronix, and CIG to demonstrate the world’s first PCIe 6.0 optical connection link training using the Anritsu MP1900A BERT, Synopsys PCIe 6.x PHY and Controller IP, Tektronix DPO70000 Real Time Oscilloscope, and CIG OSFP LPO optical module.

PCIe over optical links provides higher bandwidth, covers longer distances, and is more energy-efficient, effectively addressing key bottlenecks for AI workloads in data centers.

This joint demonstration highlights Anritsu’s leadership in next-generation optical PCIe.

PCI-Express 7.0 Differential Skew Evaluation

In collaboration with Teledyne LeCroy, Anritsu will present a solution for evaluating the effect of differential skew in PCIe 7.0.

PCIe 7.0 uses PAM4 signaling, which reduces eye height by more than three times compared to NRZ. Combined with the speed increase from 32.0 Gbaud in PCIe 6.0 to 64.0 Gbaud, this results in a smaller unit interval (UI) that is significantly more sensitive to skew.

In high-speed environments, signals traversing an ISI channel may exhibit a dip in the fundamental frequency due to skew. While most BERTs lack built-in skew evaluation functions, Anritsu addresses this by using two MP1900A MU196020A PAM4 PPG units with the Channel Sync function to inject P-N skew and Teledyne LeCroy’s WaveMaster 8650HD 65 GHz oscilloscope for advanced analysis.

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Infineon Technologies AG announced a collaboration with Typhoon HIL, a leading provider of Hardware-in-the-Loop (HIL) simulation solutions, to provide automotive engineering teams with a fully-integrated, real-time development and test environment for key elements of xEV powertrain systems. Customers working with Infineon’s AURIX TC3x/TC4x automotive microcontrollers (MCUs) can now use a complete HIL simulation and test solution using Typhoon’s HIL simulator for ultra-high-fidelity motor drive, on-board charger, BMS, and power electronics emulation, which provides a plug-and-play interface via the Infineon TriBoard Interface Card.

“Developers of xEV components including motor drives, battery management systems, on-board chargers, and DC-DC converters increasingly rely on Controller Hardware-in-the-Loop (C-HIL), on top of Software-in-the-Loop (SIL) and simulation-based approaches, to quickly achieve results and more rapidly iterate in both prototyping and test cycles,” said Christopher Thibeault, Director of Partner & Ecosystem Management Automotive Americas, Infineon Technologies. “With Typhoon’s proven real-time HIL platform, our AURIX customers can access a design and test environment that will help bring their automotive solutions based on dependable electronics to market faster.”

The solution offered by Infineon and Typhoon HIL includes any of several Typhoon HIL Simulators for real-time digital testing, a suite of testbed hardware and software tools, and the Infineon TriBoard Interface Card, which supports Infineon AURIX TC3xx and TC4xx evaluation boards and plugs directly into a single row of DIN41612 connectors on the front panel of the HIL Simulator. The solution streamlines validation workflows, expedites design and testing processes, and reduces development costs and complexity for customers. Typhoon HIL also offers an “Automotive Communication Extender” product for its HIL Simulator solution based on an AURIX TC3xx processor, which will provide an enhanced  communication interface that allows customers to connect to a larger number of heterogenous ECUs under test via CAN, CAN FD, LIN, and SPI protocols.

“We are excited to partner with a leader in the automotive integrated circuits market, to provide MCU developers with a platform for development and testing of AURIX-based controllers before hardware design is completed,” said Petar Gartner, Director of HIL Solutions, Typhoon HIL. “Our joint customers gain a competitive edge by accelerating their design and test operations while reducing costs, which ultimately translates to market advantage.  We look forward to this ongoing collaboration with Infineon.”

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Devices Offer Industry-Leading 150 kV/μs CMTI, 400 kHz Bandwidth, and Low Minimum Gain Error of ± 0.3 %

Vishay Intertechnology, Inc. announced the release of its latest isolation amplifiers, the VIA0050DD, VIA0250DD, and VIA2000SD. These new devices offer enhanced performance for a wide range of industrial, automotive, and medical applications, where high precision, reliability, and compact size are critical.

The VIA series of isolation amplifiers are designed to deliver exceptional thermal stability and precise measurement capabilities. With a typical common-mode transient immunity (CMTI) of 150 kV/μs, these amplifiers provide robust performance even in harsh environments, such as heavy-duty motor applications. The low typical gain error of ± 0.05 % and minimal gain drift of 15 ppm/°C typical ensure calibration-free, precise measurements over time and temperature. Additionally, these devices offer a high bandwidth of 400 kHz, enabling faster measurements compared to traditional opto-based isolation amplifiers.

Each amplifier in this series also features low offset error and drift, reinforced isolation, and inbuilt diagnostics for simplified precision current and voltage measurements. The inbuilt common mode voltage detection prevents failures in current and voltage measurement applications, making these amplifiers particularly suited for demanding applications where reliability is paramount. This series is designed to be compatible with Vishay’s WSBE low TCR, high power shunts, ensuring superior performance across a wide temperature range from -40°C to +125°C.

The VIA0050DD is a capacitive isolation amplifier optimized for environments where space is at a premium and low power consumption is essential. It features a high common-mode transient immunity (CMTI) of 100 kV/μs minimum, ensuring reliable performance even in noisy environments. Its low differential input voltage of ± 50 mV makes it ideal for precision isolated current measurements in space-constrained applications, such as power inverters, battery energy storage systems, motor phase current sensing, and industrial motor controls. Similarly, with its wide differential input voltage of ± 250 mV, the VIA0250DD allows for isolated current as well as voltage measurements.

The VIA2000SD offers the highest signal-to-noise ratio (SNR) and bandwidth among the three models, making it the best choice for high-fidelity signal transmission in complex environments. Its linear differential input voltage in the range of 0.02 V to 2 V allows for precise isolated voltage measurements for applications such as bus voltage monitoring and uninterruptible power supplies (UPS).

The VIA series isolation amplifiers are designed to provide reliable, accurate performance across a variety of applications, including bus voltage monitoring, AC motor controls, power and solar inverters, and UPS. These amplifiers ensure accurate measurements across high voltage potential dividers and precision shunts, provide ease in monitoring of industrial motor drives, deliver robust performance in renewable energy systems, and maintain signal integrity in critical power systems.

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Mouser Electronics, Inc. announced that it has been named 2024 Distributor of the Year by Bulgin, a leading manufacturer of environmentally sealed connectors and components for various industries, including automotive, industrial, medical and more. Representatives for Bulgin cited Mouser’s strategic support of new product launches and customer growth in 2024.

“Mouser is a valued partner, and we congratulate the Mouser team on this well-deserved award, which celebrates Mouser’s customer service, effective communication, and commitment to meeting our business needs and goals,” said Eric Smith, Vice President of Global Distribution Channel with Bulgin. “Mouser played a key role in contributing to our overall success in 2024, and we look forward to continuing the momentum in 2025 and beyond.”

“We’d like to thank Bulgin for this great honor. This award recognizes our continued efforts to be the industry’s New Product Introduction (NPI) leader, with the latest products from forward-thinking companies like Bulgin,” said Krystal Jackson, Vice President of Supplier Management at Mouser. “We have an outstanding business relationship with Bulgin and anticipate great success together in the future.”

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Vehicle-to-Everything (V2X) communication systems and lightning-fast 5G networks are merging to usher in a new era of global mobility. We are getting closer to the promise of safer roads, autonomous driving, and intelligent traffic ecosystems as a result of this convergence, which is changing how cars interact with their surroundings. Tech pioneers like Jio, Alepo, and Keysight Technologies are at the forefront of this change, facilitating V2X implementation across many infrastructures and regions.

V2X: What Is It?

The term “vehicle-to-everything” (V2X) refers to a broad category of technologies that allow automobiles to interact with their surroundings. Networks (V2N), pedestrians (V2P), infrastructure (V2I), other vehicles (V2V), and connected devices (V2D) are all included in this. Every mode has special features that improve driver ease, traffic efficiency, and road safety.

Thanks to vehicle-to-vehicle (v2v) communication, cars can exchange vital information, including direction, speed, and braking condition. This makes collision avoidance systems and early alerts easier, especially in low-visibility situations. Vehicle-to-infrastructure (V2I) enables automobiles to communicate with traffic lights, smart city systems, and road signs. By alerting drivers about impending risks or real-time signal changes, it facilitates traffic planning.

A proactive, as opposed to reactive, transportation system is made possible by the network of intelligent contacts created by this variety of communication channels. An environment where traffic flows are optimized, accidents are reduced, and cars can operate with more autonomy is the end outcome.

The Impact of Jio on India’s V2X Market Dependency

One of India’s top telecom companies, Jio, is actively constructing a strong 5G infrastructure to support V2X in the nation going forward. Jio’s V2X platform aims to create a digital transportation environment in which cars are intelligent, networked machines that can make decisions in real time.

Jio claims that their 5G-based V2X solutions are designed to make important applications like smart traffic control, cooperative collision avoidance, and autonomous driving possible. These uses make extensive use of 5G’s ultra-low latency and high bandwidth characteristics, which enable almost immediate device-to-device communication.

Road safety is still a major concern in India, where Jio’s effort has the potential to be revolutionary. Roadside unit (RSU) deployment and network slicing for V2X services allow the platform to serve latency-sensitive applications, such as danger detection and emergency vehicle prioritising. Additionally, Jio’s efforts are in line with India’s larger goal of developing intelligent transportation systems under the framework of Digital India.

Alepo’s 5G Core: An Expandable C-V2X Backbone

Alepo’s 5G Converged Core platform introduces software-defined intelligence to the V2X space, while Jio’s focus is on connectivity and infrastructure. Alepo’s basic product is capable of managing V2X-specific subscriptions, Quality of Service (QoS) policies, and session orchestration. It also supports the cellular V2X (C-V2X) standard.

Alepo’s platform stands out by enabling two distinct C-V2X communication pathways—PC5 for direct communication and Uu for network-assisted transmission. Direct communication, which allows peer-to-peer transmission between vehicles without requiring a cellular network, usually operates in the 5.9 GHz ITS frequency. In scenarios where milliseconds count, such as platooning or high-speed highway synchronisation, this is crucial.

On the other hand, network-based communication links cars to cloud services and other organisations by leveraging the cellular infrastructure that is already in place. Alepo’s 5G core skillfully strikes a balance between these modes to guarantee uninterrupted connection in any setting.

Alepo’s system’s user equipment (UE) classification is another essential component. Vehicles and pedestrians are distinguished by the system as distinct UE kinds, each with its own QoS characteristics. This makes it possible to handle data requirements and mobility patterns in a tailored way, guaranteeing that a pedestrian warning is handled differently from a vehicle coordination signal. For a sophisticated V2X ecosystem to be supported at scale, this degree of granularity is essential.

The Testing and Validation Ecosystem of Keysight

Thorough validation is essential to the efficacy of V2X systems, and Keysight Technologies is essential in this regard. Testing for compliance and interoperability must change to keep up with the complexity of V2X devices. This need is met by Keysight’s SA8700A C-V2X Test Solution, which supports both protocol and RF testing according to 3GPP Release 14 guidelines.

Manufacturers and developers may validate their V2X devices in controlled laboratory settings thanks to this service. End-to-end simulation of real-world situations, including lane-change assistance, junction collision warnings, and emergency braking alerts, is supported. Keysight’s technologies guarantee that devices not only function but also function under stress, thanks to their comprehensive diagnostic feedback and latency measurements.

Furthermore, Keysight provides the WaveBee V2X Test and Emulation package, which is intended to replicate actual driving situations on test roads and tracks. From early development to field testing after deployment, these solutions provide ongoing validation across the product lifecycle. These testing platforms guarantee user safety, performance, and compliance as international laws tighten and safety-critical applications gain traction.

Obstacles in the Way of V2X Maturity

While the promise of V2X is vast, its full-scale deployment is hindered by several critical hurdles. Standardisation is a significant obstacle. The global automotive landscape is fragmented, with regional preferences varying between technologies like DSRC and C-V2X. To guarantee smooth communication between automobiles made by various manufacturers, these standards must be harmonised.

Privacy and security are important issues to consider. As cars are becoming data nodes, it is important to ensure private data is protected from abuse or leakage. V2X networks need to implement secure authentication methods, end-to-end encryption, and anomaly detection methods to maintain resilience and trust.

Investment in infrastructure is another issue. It is critical to densify roadside units, edge servers, and network slicing in order for V2X systems to provide the best experience. Governments and municipalities need to engage in making smart mobility infrastructure happen and, while telecom has its role through networks and infrastructure developments, the effort must come from all parties. 

Conclusion: It’s Closer Than You Think

Right now, in the transportation space, parts of the ecosystem are finally being redesigned through the fusion of 5G and a new V2X communication standard. At the junction of connectivity with safer cars, smarter roads, and seamless transportation, companies like Jio, Alepo, and Keysight have already begun shaping that future.

As infrastructure continues to grow, and standardization becomes more advanced, V2X will go from a specialized innovation to an essential part of urban mobility. This technology could change everything from increasing safety by lowering traffic deaths to building networks of autonomous vehicles. The time has come for urban planners, politicians, telecom, and automotive industry players to partner up and together invest in V2X.

 

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Reflex Drive, a deep tech startup from India has selected power devices from Infineon Technologies AG for its next-generation motor control solutions for unmanned aerial vehicles (UAVs). By integrating Infineon’s OptiMOS 80 V and 100 V, Reflex Drive’s electric speed controllers (ESCs) achieve improved thermal management and higher efficiency, enabling high power density in a compact footprint. Additionally, the use of Infineon’s MOTIX IMD701 controller solution which combines the XMC1404 microcontroller with the MOTIX 6EDL7141 3-phase gate driver IC delivers compact, precise, and reliable motor control. This enables improved performance, greater reliability, and longer flight times for UAVs.

“Our partnership with Reflex Drive is an important contribution to our market launch strategy and presence in India,” says Nenad Belancic, Global Application Manager Robotics and Drones at Infineon. “Our partner has proven its expertise with numerous customers who have obtained aviation certifications. In addition, the company has presented its innovative technologies enabled by Infineon systems at important international industry events.”

“Our collaboration with Infineon has led to significant advances in UAV electronics,” says Amrit Singh, Founder of Reflex Drive. “We believe drones have the potential to transform industries, from agriculture to logistics, and with Infineon’s devices, we can help drive this transformation at the forefront.”

Reflex Drives’s ESCs with field-oriented control (FOC) offer improved motor efficiency and precise control, while its high-performance BLDC motors are designed for optimized flight control and enable predictive maintenance of drive systems. Weighing only 180 g and with a compact volume of 120 cm³, the ESCs can deliver continuous power output of 3.8 kW (12S/48 V, 80 A continuous). Due to their lightweight design, robust power output, and consistent FOC control – even under demanding weather conditions – make them ideal for motors in the thrust range from 15 to 20 kg. Therefore, they are particularly suitable for drone applications in the fields of agricultural spraying technology, seed dispersal, small-scale logistics, and goods transport.

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NoFilter GPT is a cutting-edge conversational AI built to deliver unfiltered, bold, and authentic interactions. It offers different modes for different tasks: Raw Mode delivers candid, no-nonsense dialogue; Insight Mode explores complex topics with sharp analysis; and Reality Check Mode debunks misinformation with brutally honest takes. NoFilter GPT is designed for users who value clarity, directness and intellectual integrity in real-time conversations.

Network Traffic Analysis

The ATI team in Keysight has analyzed the network traffic of NoFilter GPT and found some interesting insights that can help researchers optimize performance and enhance security. This analysis was conducted using HAR captures from a web session. NoFilter GPT operates with standard web protocols and relies on secure TLS encryption for communication.

Overall Analysis

We have performed extensive user interactions with the NoFilter GPT web application. The captured traffic was completely TLS encrypted. We have further analyzed the traffic based on host names.

Figure 1: Request-Response count per host

In the figure above we can observe the majority of request-response interactions were observed with nofiltergpt.com, handling core AI functions like chat and image generation. Additionally, NoFilterGPT related host, chat.nofiltergpt.com manage AI chat, image generation, and token-based request authentication, while other external hosts primarily serve static assets and analytics.

Figure 2: Cumulative payload per host

The diagram above shows that the host chat.nofiltergpt.com has the maximum cumulative payload followed by nofiltergpt.com. The rest of the hosts are creating smaller network footprints.

Analyzing Endpoints

By examining the HAR file, we gain a detailed view of the HTTP requests and responses between the client and NoFilter GPT’s servers. This analysis focuses on critical endpoints and their roles in the platform’s functionality.

Chat Completion

Endpoint: https://chat.nofiltergpt.com/run/nofilterai/controller5?identifier…

• Method: POST
• Purpose: This is the actual request that sends user input to the chat model and receives a response.
• Request Headers:
• Content-Type: application/json
• Accept: */* (Accepts any response type, indicating a flexible API for logging events.)
• Origin: https://nofiltergpt.com (Ensures requests originate from NoFilterGPT’s platform)
• Request Payload: Base64-encoded JSON containing user message, system prompt, temperature, etc.
• Response Status: 200 OK (successful session creation)

This triggers a response from the model.

• Method: OPTIONS
• Purpose: This is a CORS ( Cross-Origin Resource Sharing ) preflight request automatically sent by the browser before the POST request.
• Request Payload: None

The server responds with headers indicating what methods and origins are allowed, enabling the browser to safely send the POST.

Image Generation

• Endpoint: https://chat.nofiltergpt.com/media/generate2.php

• Method: POST
• Purpose: Sends an image generation prompt to the server.
• Request Headers:
• Content-Type: application/json
• Accept: */* (Accepts any response type, indicating a flexible API for logging events.)
• Request Payload: JSON with token, prompt, width, height, steps, sampler, etc.
• Response Status: 200 OK (successful session creation)

This generates and returns an image based on the prompt and settings.

• Method: OPTIONS
• Purpose: Browser-initiated CORS preflight checks to see if the server will accept the POST request
• Request Payload: None

Gets permission from the server to proceed with the actual POST request.

NOTE: While NoFilterGPT can be useful it is a prohibited tool by many companies and government entities. Policy and technical systems must be in place to prevent usage, and it is vital to confirm this via test using BreakingPoint. These tests help validate the security measures and help organizations prevent accidental or malicious use of the platform.

NoFilterGPT Traffic Simulation in Keysight ATI

At Keysight Technologies Application and Threat Intelligence (ATI), since we always try to deliver the hot trending application, we have published the NoFilter GPT application in ATI-2025-05 which simulates the HAR collected from the NoFilter GPT web application as of March 2025 including different user actions like performing text-based queries, uploading multimedia files, using the generate image feature to create custom visuals and refining search results. Here all the HTTP transactions are replayed in HTTP/2 over TLS1.3.

Figure 3: NoFilterGPT Mar25 HAR Replay HTTP/2 over TLS1.3 Superflow in BPS

The NoFilterGPT application and its 4 new Superflows as shown below:

Figure 4: NoFilterGPT App and its Superflows in BPS

Leverage Subscription Service to Stay Ahead of Attacks

Keysight’s Application and Threat Intelligence subscription provides daily malware and bi-weekly updates of the latest application protocols and vulnerabilities for use with Keysight test platforms. The ATI Research Centre continuously monitors threats as they appear in the wild. Customers of BreakingPoint now have access to attack campaigns for different advanced persistent threats, allowing BreakingPoint Customers to test their currently deployed security control’s ability to detect or block such attacks.

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Motivation

3D reconstruction is a long-standing problem in computer vision, with applications in robotics, VR and multimedia. It is a notorious problem since it requires lifting 2D images to 3D space in a dense, accurate manner.

Gaussian splatting (GS) [1] represents 3D scenes using volumetric splats, which can capture detailed geometry and appearance information. It has become quite popular due to their relatively fast training, inference speeds and high quality reconstruction.

GS-based reconstructions generally consist of millions of Gaussians, which makes them hard to use on computationally constrained devices such as smartphones. Our goal is to improve storage and computational inefficiency of GS methods. Hence, we propose Trick-GS, a set of optimizations that enhance the efficiency of Gaussian Splatting without significantly compromising rendering quality.

Background

GS is a method for representing 3D scenes using volumetric splats, which can capture detailed geometry and appearance information. It has become quite popular due to their relatively fast training, inference speeds and high quality reconstruction.

GS reconstructs a scene by fitting a collection of 3D Gaussian primitives, which can be efficiently rendered in a differentiable volume splatting rasterizer by extending EWA volume splatting [2]. A scene represented with 3DGS typically consists of hundreds of thousands to millions of Gaussians, where each 3D Gaussian primitive consists of 59 parameters. The technique includes rasterizing Gaussians from 3D to 2D and optimizing the Gaussian parameters where a 3D covariance matrix of Gaussians are later parameterized using a scaling matrix and a rotation matrix. Each Gaussian primitive also has an opacity (α ∈ [0, 1]), a diffused color and a set of spherical harmonics (SH) coefficients, typically consisting of 3-bands, to represent view-dependent colors. Color C of each pixel in the image plane is later determined by Gaussians contributing to that pixel with blending the colors in a sorted order.

GS initializes the scene and its Gaussians with point clouds from SfM based methods such as Colmap. Later Gaussians are optimized and the scene structure is changed by removing, keeping or adding Gaussians to the scene based on gradients of Gaussians in the optimization stage. GS greedily adds Gaussians to the scene and this makes the approach in efficient in terms of storage and computation time during training.

Tricks for Learning Efficient 3DGS Representations

We adopt several strategies that can overcome the inefficiency of representing the scenes with millions of Gaussians. Our adopted strategies mutually work in harmony and improve the efficiency in different aspects. We mainly categorize our adopted strategies in four groups:

a) Pruning Gaussians; tackling the number of Gaussians by pruning.

b) SH masking; learning to mask less useful Gaussian parameters with SH masking to lower the storage requirements.

c) Progressive training strategies; changing the input representation by progressive training strategies.

d) Accelerated implementation; the optimization in terms of implementation.

a) Pruning Gaussians:

a.1) Volume Masking
Gaussians with low scale tend to have minimal impact on the overall quality, therefore we adopt a strategy that learns to mask and remove such Gaussians. N binary masks, M ∈ {0, 1}N , are learned for N Gaussians and applied on its opacity, α ∈ [0, 1]N , and non-negative scale attributes, s by introducing a mask parameter, m ∈ RN. The learned masks are then thresholded to generate hard masks M;

These Gaussians are pruned at densification stage using these masks and are also pruned at every km iteration after densification stage.

a.2) Significance of Gaussians
Significance score calculation aims to find Gaussians that have no impact or little overall impact. We adopt a strategy where the impact of a Gaussian is determined by considering how often it is hit by a ray. More concretely, the so called significance score GSj is calculated with 1(G(Xj ), ri) where 1(·) is the indicator function, ri is ray i for every ray in the training set and Xj is the times Gaussian j hit ri.

where j is the Gaussian index, i is the pixel, γ(Σj ) is the Gaussian’s volume, M, H, and W represents the number of training views, image height, and width, respectively. Since it is a costly operation, we apply this pruning ksg times during training with a decay factor considering the percentile removed in the previous round.

b) Spherical Harmonic (SH) Masking

SHs are used to represent view dependent color for a Gaussian, however, one can appreciate that not all Gaussians will have the same levels of varying colors depending on the scene, which provides a further pruning opportunity. We adopt a strategy where SH bands are pruned based on a mask learned during training, and unnecessary bands are removed after the training is complete. Specifically, each Gaussian learns a mask per SH band. SH masks are calculated as in the following equation and SH values for the ith Gaussian for the corresponding SH band, l, is set to zero if its hard mask, Mshi(l), value is zero and unchanged otherwise.

where mli ∈ (0, 1), Mlsh ∈ {0, 1}. Finally, each masked view dependent color is defined as ĉi(l) = Mshi(l)ci(l) where ci(l) ∈ R(2l+1)×3. Masking loss for each degree of SH is weighted by its number of coefficients, since the number of SH coefficients vary per SH band.

c) Progressive training strategies

Progressive training of Gaussians refers to starting from a coarser, less detailed image representation and gradually changing the representation back to the original image. These strategies work as a regularization scheme.

c.1) By blurring
Gaussian blurring is used to change the level of details in an image similar. Kernel size is progressively lowered at every kb iteration based on a decay factor. This strategy helps to remove floating artifacts from the sub-optimal initialization of Gaussians and serves as a regularization to converge to a better local minima. It also significantly impacts the training time since a coarser scene representation requires less number of Gaussians to represent the scene.

c.2) By resolution
Progressive training by resolution. Another strategy to mitigate the over-fitting on training data is to start with smaller images and progressively increase the image resolution during training to help learning a broader global information. This approach specifically helps to learn finer grained details for pixels behind the foreground objects.

c.3) By scales of Gaussians
Another strategy is to focus on low-frequency details during the early stages of the training by controlling the low-pass filter in the rasterization stage. Some Gaussians might become smaller than a single pixel if each 3D Gaussian is projected into 2D, which results in artefacts. Therefore, the covariance matrix of each Gaussian is added by a small value to the diagonal element to constraint the scale of each Gaussian. We progressively change scale for each Gaussian during the optimization similar to ensure the minimum area that each Gaussian covers in the screen space. Using a larger scale in the beginning of the optimization enables Gaussians receive gradients from a wider area and therefore the coarse structure of the scene is learned efficiently.

d) Accelerated Implementation

We adopt a strategy that is more focused on the training time efficiency. We follow on separating higher SH bands from the 0th band within the rasterization, thus lower the number of updates for the higher SH bands than the diffused colors. SH bands (45 dims) cover a large proportion of these updates, where they are only used to represent view-dependent color variations. By modifying the rasterizer to split SH bands from the diffused color, we update higher SH bands every 16 iterations whereas diffused colors are updated at every iteration.

GS uses photometric and structural losses for optimization where structural loss calculation is costly. SSIM loss calculation with optimized CUDA kernels. SSIM is configured to use 11×11 Gaussian kernel convolutions by standard, where as an optimized version is obtained by replacing the larger 2D kernel with two smaller 1D Gaussian kernels. Applying less number of updates for higher SH bands and optimizing the SSIM loss calculation have a negligible impact on the accuracy, while it significantly helps to speed-up the training time as shown by our experiments.

Experimental Results

We follow the setup on real-world scenes. 15 scenes from bounded and unbounded indoor/outdoor scenarios; nine from Mip-NeRF 360, two (truck and train) from Tanks&Temples and two (DrJohnson and Playroom) from Deep Blending datasets are used. SfM points and camera poses are used as provided by the authors [1] and every 8th image in each dataset is used for testing. Models are trained for 30K iterations and PSNR, SSIM and LPIPS are used for evaluation. We save the Gaussian parameters in 16-bit precision to save extra disk space as we do not observe any accuracy drop compared to 32-bit precision.

Performance Evaluation

Our most efficient model Trick-GS-small improves over the vanilla 3DGS by compressing the model size drastically, 23×, improving the training time and FPS by 1.7× and 2×, respectively on three datasets. However, this results in slight loss of accuracy, and therefore we use late densification and progressive scale-based training with our most accurate model Trick-GS, which is still more efficient than others while not sacrificing on the accuracy.

Table 1. Quantitative evaluation on MipNeRF 360 and Tanks&Temples datasets. Results with marked ’∗’ method names are taken from the corresponding papers. Results between the double horizontal lines are from retraining the models on our system. We color the results with 1st, 2nd and 3rd rankings in the order of solid to transparent colored cells for each column. Trick-GS can reconstruct scenes with much lower training time and disk space requirements while not sacrificing on the accuracy.

Trick-GS improves PSNR by 0.2dB on average while losing 50% on the storage space and 15% on the training time compared to Trick-GS-small. The reduction on the efficiency with Trick-GS is because of the use of progressive scale-based training and late densification that compensates for the loss from pruning of false positive Gaussians. We tested an existing post-processing step, which helps to further reduce model size as low as 6MB and 12MB respectively for Trick-GS-small and Trick-GS over MipNeRF 360 dataset. The post-processing does not heavily impact the training time but the accuracy drop on PSNR metric is 0.33dB which is undesirable for our method. Thanks to our trick choices, Trick-GS learns models as low as 10MB for some outdoor scenes while keeping the training time around 10mins for most scenes.

Figure 1. Number of Gaussians (#G) during training (on MipNeRF 360 – bicycle scene) for all methods, number of masked Gaussians (#Masked-G) and number of Gaussians with a masked SH band for our method. Our method performs a balanced reconstruction in terms of training efficiency by not letting the number of Gaussians increase drastically as other methods during training, which is a desirable property for end devices with low memory.

Learning to mask SH bands helps our approach to lower the storage space requirements. Trick-GS lowers the storage requirements for each scene over three datasets even though it might result in more Gaussians than Mini-Splatting for some scenes. Our method improves some accuracy metrics over 3DGS while the accuracy changes are negligible. Advantage of our method is the requirement of 23× less storage and 1.7× less training time compared to 3DGS. Our approach achieves this performance without increasing the maximum number of Gaussians as high as the compared methods. Fig. 1 shows the change in number of Gaussians during training and an analysis on the number of pruned Gaussians based on the learned masks. Trick-GS achieves comparable accuracy level while using 4.5× less Gaussians compared to Mini-Splatting and 2× less Gaussians compared to Compact-GS, which is important for the maximum GPU consumption on end devices. Fig. 2 shows the qualitative impact of our progressive training strategies. Trick-GS obtains structurally more consistent reconstructions of tree branches thanks to the progressive training.

Figure 2. Impact of progressive training strategies on challenging background reconstructions. We empirically found that progressive training strategies as downsampling, adding Gaussian noise and changing the scale of learned Gaussians have a significant impact on the background objects with holes such as tree branches.

Ablation Study

We evaluate the contribution of tricks in Tab. 2 on MipNeRF360 – bicycle scene. Our tricks mutually benefits from each other to enable on-device learning. While Gaussian blurring helps to prune almost half of the Gaussians compared to 3DGS with a negligible accuracy loss, downsampling the image resolution helps to focus on the details by the progressive training and hence their mixture model lowers the training time and the Gaussian count by half. Significance score based pruning strategy improves the storage space the most among other tricks while masking Gaussians strategy results in lower number of Gaussians at its peak and at the end of learning. Enabling progressive Gaussian scale based training also helps to improve the accuracy thanks to having higher number of Gaussians with the introduced split strategy.

Table 2. Ablation study on tricks adopted by our approach using‘bicycle’ scene. Our tricks are abbreviated as BL: progressive Gaussian blurring, DS: progressive downsampling, SG: significance pruning, GM: Gaussian masking, SHM: SH masking, AT: accelerated training, DE: late densification, SC: progressive scaling. Our full model Trick-GS uses all the tricks while Trick-GS-small uses all but DE and SC.

Summary and Future Directions

We have proposed a mixture of strategies adopted from the literature to obtain compact 3DGS representations. We have carefully designed and chosen strategies from the literature and showed competitive experimental results. Our approach reduces the training time for 3DGS by 1.7×, the storage requirement by 23×, increases the FPS by 2× while keeping the quality competitive with the baselines. The advantage of our method is being easily tunable w.r.t. the application/device needs and it further can be improved with a post-processing stage from the literature e.g. codebook learning, huffman encoding. We believe a dynamic and compact learning system is needed based on device requirements and therefore leave automatizing such systems for future work.

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Courtesy: Synopsys

Recent advancements in machine learning have resulted in improvements in artificial intelligence (AI), including image recognition, autonomous driving, and generative AI. These advances are primarily due to the ability to train large models on increasingly complex datasets, enabling better learning and generalization as well as the creation of larger models. As datasets and model sizes grow, there is a requirement for more powerful and optimized computing clusters to support the next generation of AI.

With more than 25 years of experience in delivering field-proven silicon IP solutions, we are thrilled to partner with NVIDIA and the NVIDIA NVLink ecosystem to enable and accelerate the creation of custom AI silicon. This strategic collaboration will leverage Synopsys’ expertise in silicon IPs to assist in the development of bespoke AI silicon, forming the foundation for advanced compute clusters aimed at delivering the next generation of transformative AI experiences.

Compute challenges with larger datasets and increasingly large AI models

Training trillion-parameter-plus models on large datasets necessitates substantial computational resources, including specialized accelerators such as Graphics Processing Units (GPUs) and Tensor Processing Units (TPUs). AI computing clusters incorporate three essential functions:

1. Compute — implemented using processors and dedicated accelerators.
2. Memory — implemented as High Bandwidth Memory (HBM) or Double Data Rate (DDR) with virtual memory across the cluster for memory semantics.
3. Storage — implemented as Solid State Drives (SSDs) that efficiently transfer data from storage to processors and accelerators via Peripheral Component Interconnect Express (PCIe)-based Network Interface Cards (NICs).

Retimers and switches constitute the fabric that connects accelerators and processors. To enhance the computational capabilities of the cluster, it is necessary to increase capacity and bandwidth across all functions and interconnects.

Developing increasingly sophisticated, multi-trillion-parameter models requires the entire cluster to be connected over a scale-up and scale-out network so it can function as a unified computer.

Figure 1: A representative compute cluster with scale-up and scale-out network.

Standards-based IPs for truly interoperable compute clusters

The successful deployment of next-generation computing clusters relies on silicon-verified interconnects that utilize advanced process node technology and guarantee interoperability. Standardized interconnects enable an interoperable, multi-vendor implementation of a cluster.

PCIe is an established standard for processor-to-accelerator interfaces, ensuring interoperability among processors, NICs, retimers, and switches. Since 1992, the PCI-SIG has been defining Peripheral Component Interconnect (PCI) solutions, with PCIe now in its seventh generation. The extensive history and widespread deployment of PCIe ensure that IP solutions benefit from the silicon learning of previous generations. Furthermore, the entire ecosystem developing processors, retimers, switches, NICs, and SSDs possesses significant deployment experience with PCIe technology. Our complete IP solution for PCIe 7.0 is built upon our experience with more than 3,000 PCIe designs, launched in June 2024 with endorsements from ecosystem partners such as Intel, Rivos, Xconn, Microchip, Enfabrica, and Kandou.

When deploying trained models in the cloud, hyperscalers aim to continue utilizing their software on custom processors that interface with various types of accelerators. For NVIDIA AI factories, NVLink Fusion provides another method for connecting processors to GPUs.

 

Figure 2: Components and interconnects of a next-generation compute cluster.

Accelerators can be connected in various configurations, affecting the efficiency of compute clusters. Scale-up requires memory semantics for a virtual memory pool across the cluster, while scale-out involves connecting tens-of-thousands to hundreds-of-thousands of GPUs with layers of switching and congestion management. Unlike scale-up, scale-out is more latency-tolerant and designed for bandwidth oversubscription to suit AI model data parallelism. In December 2024, we launched our Ultra Accelerator Link (UALink) and Ultra Ethernet solution to connect accelerators efficiently. The solution, which was publicly supported with quotes from AMD, Juniper and Tenstorrent, is based on silicon-proven 224G PHY and more than 2,000 Ethernet designs.

Trillion-parameter models demand extensive memory storage and high data rates for low latency access, necessitating increased memory bandwidth and total capacity. HBM provides both substantial capacity and high bandwidth. Our HBM4 IP represents the sixth generation of HBM technology, offering pin bandwidths up to 12 Gbps, which results in an overall interface bandwidth exceeding 3 TBps.

Co-packaged multi-die aggregation not only enhances compute throughput by overcoming the limitations of advanced fabrication processes but also facilitates the integration of optical interconnects through emerging Co-Packaged Optical (CPO) technologies. Since 2022, we have been developing linear electro-optical (EO) interfaces to create energy-efficient EO links. The Universal Chiplet Interconnect Express (UCIe) standard has provided a well-defined path for multi-vendor interoperability. In collaboration with Intel in 2023, we successfully demonstrated the first UCIe-connected, chiplet-based test chip.

Multi-die integration poses challenges for heat dissipation, potentially impacting temperature-sensitive photonic components or causing thermal runaway. Our comprehensive multi-die solution, including Die-to-Die IP, HBM IP, and 3DIC Compiler for system-in-package integration, provides a reliable and robust multi-die implementation.

Adopting well-established and extensively validated IP solutions across critical interconnects – from processor-accelerator interfaces to advanced multi-die architectures and HBM – mitigates the risks associated with custom design and integration. Pre-verified IPs streamline the design and verification process, accelerate timelines, and ultimately pave the way for successful first-pass silicon, enabling the rapid deployment of innovative and interoperable compute clusters.

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Courtesy: Lattice Semiconductors

Imagine a robot navigating a crowded factory floor, rerouting itself in real-time around equipment, humans, and unexpected obstacles — all while maintaining motion control and system stability. This isn’t a distant vision; this is the reality engineered by Agiliad in partnership with Lattice Semiconductor.

In a market full of autonomous mobile robots (AMRs) that rely on generic control stacks and prebuilt kits, this AMR stands out as a deep-tech system, purpose-built for intelligent indoor mobility. Unlike conventional AMRs that often trade performance for modularity or ease of deployment, this robot integrates a custom motion control framework based on Lattice’s Certus-NX FPGA, along with a ROS2-based advanced SLAM (Simultaneous Localization and Mapping), sensor fusion, and navigation stack running on NVIDIA Jetson Orin— all tightly orchestrated for low-latency, high-reliability operation.

This next-generation AMR is more than just mobile — it’s aware, adaptable, and engineered for deterministic control in real-world conditions. Designed for use in industrial settings, research labs, and beyond, the robot brings together embedded intelligence, energy efficiency, and full-stack integration to set a new benchmark for autonomous systems.

Key Features of the Robot: The Intelligence Behind the Robot

Advanced Localization & Mapping: RTAB-Map SLAM, a robust loop-closure-enabled algorithm, leverages both 3D lidar and camera feeds for consistent mapping even in environments with visual and spatial ambiguities.

• 3D Obstacle Detection & Avoidance: Using a combination of 3D voxel layers and spatio-temporal layers, the robot dynamically detects and navigates around static and moving objects — maintaining safe clearance while recalculating routes on the fly.
• Path Planning: The navigation stack uses the SMAC (Search-Based Motion Planning) planner for global routing and MPPI (Model Predictive Path Integral) for locally optimized trajectories, allowing real-time adaptation to dynamic environmental changes.
• Precision Motion Control via FPGA: BLDC motors are governed by Lattice Certus-NX FPGAs executing custom PI (proportional integral) control loops in hardware, ensuring smooth acceleration, braking, and turning — critical for safety in confined spaces.

Sensor Fusion for Environmental Awareness :
Lidar and stereo camera data is processed on the Lattice Avant-E FPGA and fused with point cloud information to detect and differentiate humans and objects, providing real-time environmental awareness for safe and adaptive navigation.

System Architecture Breakdown Diagram

The AMR’s architecture is a layered, modular system built for reliability, scalability, and low power consumption. Jetson handles ROS2 algorithms, while the Lattice FPGAs manage motion control.

• Robot Geometry and Integration with ROS2 : The robot’s geometry and joints are defined in a URDF model derived from mechanical CAD files. The Robot State Publisher node in ROS2 uses this URDF to publish robot structure and transform data across the ROS2 network.
• Lattice Avant-E FPGA Based Sensor Fusion : Sensor data from lidar and stereo vision cameras is transmitted to the Avant-E FPGA over UDP. Avant-E employs OpenCV for real-time image identification and classification, fusing visual data with point cloud information to accurately detect and differentiate humans from other objects in the environment. This fused data — including human-specific classification and distance metrics — is then transmitted to the ROS2 framework running on NVIDIA Jetson. This high-fidelity sensor fusion layer ensures enhanced situational awareness, enabling the robot to make informed navigation decisions in complex, dynamic settings.
• SLAM & Localization: Lidar provides a 3D point cloud of the environment, while the camera supplies raw image data. An RTAB-Map (Real-Time Appearance-Based Mapping) processes this information to create a 3D occupancy grid. Odometry is derived using an iterative closest point (ICP) algorithm, with loop closure performed using image data. This enables continuous optimization of the robot’s position, even in repetitive or cluttered spaces.
• Navigation: Navigation generates cost maps by inflating areas around obstacles. These cost gradients guide planners to generate low-risk paths. SMAC provides long-range planning, while MPPI evaluates multiple trajectory options and selects the safest path.
• ROS2 Control and Differential Drive Kinematics: ROS2 computes a command velocity (linear and angular) which is translated into individual wheel velocities using differential drive kinematics.
• Hardware Interface: This layer ensures integration between ROS2 and the robot’s hardware. Serial communication (UART) between Jetson and Certus-NX transmits motor velocity commands in real-time.
• Lattice Certus-NX FPGA-Based Motion Control: Lattice’s Certus-NX FPGA executes real-time motor control algorithms with high reliability and minimal latency, enabling deterministic performance, efficient power use, and improved safety under industrial loads:

PI Control Loops for velocity and torque regulation, using encoder feedback to ensure performance regardless of frictional surface conditions.

Commutation Sequencer that uses hall sensor feedback to control 3-phase BLDC motor excitation.

 

How It All Works Together: A Decision-Making Snapshot

The robot’s intelligence simulates a real-time decision-making loop:

Where am I?

The robot localizes using RTAB-Map SLAM with loop closure, updating its position based on visual and spatial cues.

Where should I go?
A user-defined goal (set via touchscreen or remote interface) is passed to the global planner, which calculates a safe, efficient route using SMAC.

How do I get there?
The MPPI planner simulates and evaluates dozens of trajectories in real-time, using critic-based scoring to dynamically adapt to the robot’s surroundings.

What if something blocks the path?
Sensor data updates the obstacle map, triggering real-time replanning. If no safe path is found, recovery behaviors are activated via behavior servers.

Component / Design Element	Rationale
Differential Drive	Simpler control logic and reduced energy usage compared to omni-wheels
Lidar Placement (Center)	Avoids blind spots; improves loop closure and mapping accuracy
Maxon BLDC Motors	High torque (>4.5 Nm) for payload handling and smooth mobility
Certus-NX FPGA Motion Control	Enables deterministic control with low CPU overhead
Camera Integration	Improves visual SLAM and scene understanding
Convex Caster Wheels	Reduces ground friction, enhances turning in confined areas
Cooling Architecture	Fans and vents maintain safe operating temperatures
Jetson as CPU	Provides headroom for future GPU-based algorithm integration

Lattice FPGA Technology
Lattice’s Certus-NX and Avant-E FPGAs deliver complementary capabilities that are critical for autonomous robotic systems:

• Low Power Consumption : Extends battery life in mobile systems
• Real-Time Performance: Delivers responsive control loops and fast data handling
• Flexible Architecture : Supports custom control logic and sensor interfaces

Combined with NVIDIA Jetson Orin and embedded vision tools, the result is a scalable and adaptable robotic platform.

Looking Ahead: Enabling the Future of Robotics
Agiliad’s engineering model emphasizes deep system-level thinking, rapid prototyping, and cross-domain integration, delivering a fully operational system within a compressed development timeline by leveraging low power Lattice FPGAs. This reflects Agiliad’s deep expertise in full-stack design and multidisciplinary integration across mechanical, electrical, embedded, and software.

The post Redefining Robotics: High-Precision Autonomous Mobile Robots appeared first on ELE Times.

India is going to make their very first indigenous chip by the end of 2025, making a very important step towards technological advancements for this nation. Announcing this, Union Minister of Electronics and IT, Ashwini Vaishnaw, said that the chip employing 28-90nm technology is slated for rollout this year. This is envisaged as part of a larger plan for India to promote semiconductor manufacturing in the country and cut down on import dependency.

The first chip would be manufactured at Tata Electronics’ unit at Jagiroad in Assam, with an investment of 27,000 crore. The facility, coming up under the aegis of the India Semiconductor Mission, is a huge investment into the northeast and shall create many job opportunities. The government has also approved setting up the sixth fab in Uttar Pradesh through a JV of HCL and Foxconn, further deepening the semiconductor ecosystem in the country.

Minister Vaishnaw stated that the 28-90nm chips are used in various sectors such as automotive, telecommunications, power and railways. India, therefore, intends to focus on this segment that accounts for roughly 60 percent of the global semiconductor market so that it can position itself as a major market player.

Apart from manufacturing, the government is putting a greater emphasis on developing indigenous IP and design skills. Work is progressing towards the development of 25 chips with indigenous IP-aimed at improving cyber security. 13 projects are being pursued under the aegis of the Centre for Development of Advanced Computing (C-DAC), Bengaluru, thereby giving concrete expression to self-reliance and innovation.

Building an indigenous fab aligns with the objectives laid down in India’s “Digital India” concept, which works towards prompting India as a global nucleus for electronics manufacturing. India’s entry into the semiconductor industry is anticipated to have a significant impact on the economy both domestically and globally, given the continuous disruptions in the supply chain and in the rapidly evolving technological landscape.

Conclusion:

This initiative is directly in keeping with the “Digital India” vision to transform the country into a gobal hub for electronics manufacturing. With supply chain issues and technological shifts currently gripping the world, practically entering semiconductor production would certainly having far-reaching implications for the Indian economy as well as on the global level.

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