ELE Times

India is now helping Sri Lanka set up an artificial intelligence laboratory for its Army, making cutting-edge digital technologies a key focus of defence ties. The plan was rolled out by Defence Minister Rajnath Sing during his Colombo visit, during which three other pacts related to defence were signed between the two sides. The laboratory’s functions haven’t been specified yet, but this could include analysis of military data, support for surveillance tasks, logistics and resource management, and quicker planning-all critical elements for operations, officials indicated. The move indicates a trend towards leveraging AI as it has become easier for armies to gain a better grasp of the situations and make effective use of intelligence, data collected through sensors or surveillance equipment.

The agreements also include modernization of the L-70 air-defence guns utilized by the Sri Lanka Air Force and cooperation between the National Cadets Corps and the National Defence Colleges of both countries. Furthermore, India also provided spares for the Mk-II radar, some naval parts, and inflatable targets for training purposes. It indicates the extension of India’s regional defence partnership from traditional hardware and training to AI, digital infrastructure, and know-how exchange. Also, it may offer some new space for India’s defence-electronics firms specializing in sensors, secure communication systems, analytic software, and command and control.

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India’s premier video security brand PRAMA showcased advanced security products and smart security solutions for the MSME sector at the first edition of Bharatiya Vyapar Mahotsav (BVM) from August 12-15, 2026 at Bharat Mandapam, New Delhi. At the exhibition, traders, MSMEs, manufacturers, innovators, businesses and other industry stakeholders came together to showcase their products, services, and solutions. The inaugural event was attended by Union Minister for Commerce & Industry Piyush Goyal, Minister of State for Commerce and Industry Jitin Prasada and former Union Minister Smriti Irani along with leaders and representatives from Confederation of All India Traders (CAIT), Swadeshi Jagran Manch and other organisations.

PRAMA management representative said, “The Bharatiya Vyapar Mahostav is a great platform for Pan India Trade bodies and entrepreneurs of MSME sector. The Indian security market is poised for a new growth phase due to the exponential growth of Micro, Small and Medium Enterprises (MSME) sector. MSME sector is the backbone of India’s economy. We are glad to serve the needs of India’s Medium and Small enterprises. We find Bharatiya Vyapar Mahotsav (BVM) event, a highly valuable exhibition platform to connect with the key stakeholders and ecosystem partners. We showcased the latest products and solutions in this expo. We appreciate CAIT’s proactive role in organizing Bharatiya Vyapar Mahotsav event to spur innovation and engagement with key industry stakeholders.”

He further elaborated, “PRAMA, being India’s premier indigenous security brand holds, great significance. The spectacular growth that India security industry has achieved, PRAMA’s evolution as a leading security brand is the manifestation of Indian spirit and ingenuity. We are taking indigenous manufacturing to the next level. We are here to offer best-in-class products with cutting edge technologies that can deliver solutions as per the MSME Sector’s evolving requirements as per the business cases and application scenarios.”

The elaborately designed spacious PRAMA booth was center of attraction for the trade and industry specific visitors. PRAMA booth showcased the latest products and MSME sector’s solutions, including Ai technology, Interactive Display Panel, Perimeter and Defence Solution, Ranginview IP Series with Built-in MiC, Safe City Solution, Transportation Solution, Mobile enforcement Solution, Networking and Transmission and many more.

PRAMA booth displayed the latest video security products, including Ai Solution. PRAMA’s AiSense technology, powered by advanced AI Algorithms, takes surveillance to the next level. This technology intelligently distinguishes people and vehicles from other moving objects, reducing false alarm caused by animals or environmental factors. With AiSense Technology one can focus on the real threats, optimize resources and build on an intelligent security system. The AI Sense Technology can be very helpful in the various application scenarios in the retail segment for the MSME sector.

PRAMA’s Interactive Display Panel (IDP) was displayed at the booth, it is an all-in-one large display panel which integrates features of a computer, whiteboard, and projector, all in one device, making it a versatile tool for education, corporate training and business video conferencing scenarios. It is a great communication and training tool for the MSME sector.

PRAMA’s booth showcased Safe City Solution, which provides sound, stable and reliable public security. It features a suite of advanced technologies and security subsystems to safeguard industries, centralise operations, and integrate security platforms. These integrated technologies enable rapid and effective responses to security needs and events.

Bharatiya Vyapar Mahotsav (BVM) 2026 is India’s largest Make-In-India multi-sectoral trade expo, designed to bring together India’s diverse business ecosystem under one roof, connecting traders, MSMEs, manufacturers, industry leaders, institutions, and policymakers from across the country. The mega event was organized by Confederation of All India Traders (CAIT) & ITPO.

The Bharatiya Vyapar Mahotsav (BVM), 2026 was a four day event, which was successfully concluded. The event helped to create awareness about the latest innovations and products in the myriad trade segments. The discussions and deliberations were done with various key stakeholders on the core trade and MSME issues. The event was attended by the key trade and business professionals, Government officials and key stakeholders from the Trade and MSME sectors.

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GSAS Micro Systems inaugurated its new manufacturing and expanded R&D facility in Doddaballapur, Bengaluru Rural, marking a significant step in the company’s journey from embedded engineering and technology integration toward a stronger in-house product development and manufacturing footprint in Karnataka.

Located in the Doddaballapur 3rd Phase Industrial Area, the new facility brings GSAS’s product development, engineering, manufacturing and project activities together under one roof. It will serve as a working hub for hardware manufacturing, assembly, integration, quality testing, R&D and new-product development.

The expansion comes as Karnataka continues to strengthen its electronics and semiconductor ecosystem, building on its established capabilities in electronic design and semiconductor R&D. According to the Karnataka Digital Economy Mission (KDEM), the state contributes 10% of India’s electronics output and nearly 40% of the country’s electronic design output. Karnataka also accounts for more than 22% of India’s electronics exports and hosts more than 100 fabless semiconductor design companies.

For GSAS, the Doddaballapur facility is both a business milestone and the culmination of a much older ambition. The company’s founder has carried the vision of building a dedicated electronics manufacturing base since the 1990s. Bringing that ambition to life in Karnataka gives the company a permanent home for developing and building more of its own products while expanding the engineering infrastructure available for customer-specific programmes.

“This is a deeply personal milestone for me. I have wanted to build a dedicated electronics manufacturing home since the 1990s. Karnataka gave our generation of electronics entrepreneurs the engineering talent, industry networks and ecosystem to build companies here. With this facility, we now have a place where our team can take more ideas from engineering and R&D into real products and manufacturing. For us, this is not the end of a dream; it is the foundation for what GSAS wants to build next.” said Satya Gopalam, Chairman and Managing Director , GSAS Micro Systems.

“Our engineering work has been moving deeper into the FPGA space, with vision AI and edge AI projects, board bring-up support for automotive programmes, and PCBA test automation. This new 12,000 square foot facility gives that work a manufacturing home: we will build the new Genesis series here, essentially embedded development kits and FPGA development kits, manufactured and assembled on site, alongside test automation and integration work for the automotive, aerospace and satellite space. We have been working towards this for the last few years, and I am proud to see it finally established. If you are curious, reach out; we are happy to give you a tour of the facility.” said Anvesh Gopalam, Executive Director , GSAS Micro Systems.

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Col Sandeep Rao (Retd) is a veteran Indian Army Artillery officer with more than two decades of military service. His career includes experience in combat operations, counter-terrorism and high-altitude operations along the Line of Control. An alumnus of the National Defence Academy and Don Bosco High School, Matunga, Mumbai, he brings military leadership and field experience to his role as Advisor at Tirupati Forge.

Within India’s defence acquisition framework, Col Rao served as programme coordinator for the country’s first indigenously designed and developed 155 mm advanced artillery gun system, managing requirement formulation, trials, and execution. His domain expertise includes artillery platforms, counter-UAS systems, defence robotics, ammunition manufacturing, and Defence Acquisition Procedure (DAP 2020) implementation.

Following his military service, Col Rao acts as a strategic advisor to defence manufacturers, technology enterprises, and investment platforms. He guides companies on market positioning, technology transfer, and institutional procurement pathways while advising defence-tech start-ups on investor readiness and government acquisition. As a technology scout and strategy consultant, he collaborates across the Ministry of Defence, DRDO, and industry channels to bridge operational military requirements with commercial delivery and advance defence indigenisation.

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Microchip Technology and Marelli have announced a new display connectivity solution that uses ASA Motion Link (ASA-ML), an open standard for automotive video connectivity. The solution enables graphics and video generated by a vehicle’s central computer to be streamed directly to in-vehicle displays. The demonstrator can help automakers simplify display architectures, optimise system costs and increase sourcing flexibility as they move toward software-defined vehicles (SDVs).

ASA Motion Link is an open standard for automotive video connectivity and SerDes (serializer-deserializer) communication, defined by the Automotive SerDes Alliance (ASA), a global consortium of vehicle makers, Tier 1 suppliers and semiconductor companies. By enabling secure, high-speed video and graphics transmission across products from multiple technology providers, the standard supports greater compatibility across the automotive ecosystem and provides a scalable alternative to proprietary video transmission technologies. As a founding member of ASA, Microchip is advancing the automotive industry’s transition from proprietary connectivity technologies to open, interoperable standards, and has demonstrated broad interoperability with its camera solutions and is now extending those solutions to enable display connectivity.

As vehicle architectures evolve toward centralized computing and software-defined vehicles (SDVs), vehicle makers are looking for connectivity solutions that can support growing performance demands while reducing complexity, controlling costs and enabling scalable vehicle electronics architectures. In the joint demonstrator solution, graphics and video content generated by the vehicle’s central computer is processed and transmitted through Microchip’s VS7000 ASA-ML chipset over a high-speed standardized link.

Marelli pioneers the display-side integration of the technology by enabling the configuration and optimization of the ASA ML deserializer to decode standardized video streams directly at the display. This ensures accurate reception, synchronization and delivery of centrally generated content, including camera feeds, navigation maps, infotainment graphics and vehicle control interfaces, while enabling simplified display-side electronic architectures.

“The transition to software-defined vehicles is driving demand for more open, flexible and scalable electronic architectures,” said Kelei Shen, president of Marelli’s electronics business. “As an integrator within the automotive ecosystem, Marelli brings together best-in-class technologies from multiple partners to deliver complete solutions for vehicle makers. This collaboration highlights how open standards can accelerate innovation while providing interoperability needed for the next generation of vehicle architectures.”

“Open standards play a critical role in accelerating innovation by reducing dependency on proprietary technologies,” said Kevin So, vice president of Microchip’s communications business unit. “Our collaboration with Marelli demonstrates how ASA Motion Link provides automotive manufacturers with a secure, interoperable and scalable connectivity solution that simplifies integration across the ecosystem.”

Technology Highlights

• Open interoperability enabling seamless connectivity between cockpit systems and displays from multiple technology providers.
• Greater supplier flexibility thanks to open protocol specifications supported across the automotive ecosystem.
• Integrated security with link-layer authentication and encryption embedded in the communication channel.
• Robust data transmission with lossless communication and high immunity to electromagnetic noise.
• Scalable performance supporting data rates up to 16 Gbps to address a range of display requirements.
• Optimized efficiency enabled by embedded Time Division Duplex (TDD) functionality and simplified Forward Error Correction (FEC), contributing to lower power consumption.
• Path to increasingly Ethernet-centric vehicle architectures.

The collaboration demonstrates how open-standard connectivity supports in-vehicle networking and electronics by enabling secure communication between centralized computing systems and displays. It also reflects Marelli’s broader commitment to adopting open standards that help simplify development, optimize system costs, and promote a more open automotive ecosystem.

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London is set to be the venue for European Microwave Week (EuMW) 2026, bringing together professionals working across RF, microwave, wireless and radar engineering.

In relation to this the European Microwave Exhibition is being held in Excel London, the event scheduled to take place between October 6 and 8, 2026. Within Booth B10, Rohde & Schwarz will present a range of their most recent test and measurement solutions, aimed at RF & Microwave component, wireless, radar & satellite system developers and will enable them to respond to demands in areas such as EW (electronic warfare) and EMSO (electromagnetic spectrum operations) with more challenging frequency environments.

Markus Lörner, Application Segment Manager RF & Microwave Components at Rohde & Schwarz, says: “Our EuMW 2026 motto, ‘Progress needs proof,’ reflects what many engineers are facing today: when DUTs push beyond the limits of conventional methods, innovation slows down. At the show, we will demonstrate how our advanced test solutions support customers across RF and microwave components, satellite and radar systems, phased-array antennas and emerging 6G sensing applications. As R&D moves toward higher frequencies, more integrated designs and increasingly demanding spectrum environments, precise and reliable measurement becomes a key enabler of progress.”

A highlight at the Rohde & Schwarz booth is the FSWX signal and spectrum analyser, displayed in a radar and electronic warfare (EW) test scenario within the context of electromagnetic spectrum operations (EMSO), focused on DRFM-based jammers. In this setup, an R&S SMW200A vector signal generator simulates radar signals, while the FSWX uses its multi channel architecture to analyse jammer input and output signals simultaneously for a comprehensive assessment of deceptive signal behaviour. The new, fully integrated R&S FSWX-KM700 pulse analysis option measures both channels in parallel and provides detailed insight into pulsed radar parameters, differences between the channels and the parameter trends over time.

In a second demonstration, Rohde & Schwarz will show how its high-frequency test capabilities can be extended into the E-band and beyond, up to 110 GHz, to characterise challenging high-frequency components. The demonstration combines the fully calibrated R&S FE110ST external frontend with the R&S SFI100A wideband IF vector signal generator, enabling wideband signal generation and testing for demanding high-frequency applications. The setup can support the testing of satellite components for new payload and link-generation applications, while helping engineers accurately characterise the RF behaviour of the device under test (DUT).

Rohde & Schwarz will also showcase the enhanced R&S FSWP phase noise analyser and VCO tester platform for advanced component characterization. With support for residual and absolute phase noise measurements up to 56 GHz and further improved internal reference, R&S FSWP-B62, the solution offers high flexibility for testing synthesizers, OCXOs, DROs, VCOs and two-port components such as amplifiers. New options for integrating external signal sources as local oscillators can dramatically accelerate measurements, in some cases by up to a factor of 1,000, making the R&S FSWP well suited for the development of low-noise signal sources for radar, satellite, base station and high-speed digital applications.

Rohde & Schwarz will also present the new R&S SAM200 system amplifier for high-power test applications in the Ka- and V band up to 53 GHz. In radar, satellite link and backhaul applications, RF frontends must deliver higher power levels so signals can travel farther and cover larger distances. Designed to support validation of these components, the amplifier extends test setups with higher signal power while maintaining precise and reliable level control. At EuMW, Rohde & Schwarz will showcase the R&S SAM200 in two demonstrations: one characterizing a high-power Ka-band amplifier with the R&S ZNA vector network analyser in a fully integrated and calibrated test setup, and another highlighting the amplifier’s linearity in a wideband modulated test scenario with the R&S SMW200A vector signal generator and the FSW signal and spectrum analyser.

At EuMW, Rohde & Schwarz will also highlight the R&S ZNB3000 vector network analyzer for measurement applications in satellite communications, Earth observation and radio astronomy. Its wide dynamic range and low trace noise provide the sensitivity required for demanding antenna characterization and radar measurements. For higher-frequency applications, optional millimeter wave converters extend coverage up to 330 GHz, including bands used by microwave and millimeter wave radiometers. Together, these capabilities make the R&S ZNB3000 a versatile and cost-effective solution for a broad range of measurement needs in the satellite and space sectors.

With the AREG800A radar target generator, Rohde & Schwarz will showcase new test capabilities addressing use cases like 6G integrated sensing and communication (ISAC). As 6G networks evolve beyond data connectivity toward environmental awareness, ISAC is emerging as a key technology for detecting and classifying objects using mobile infrastructure. In addition to emulating distance, speed and radar cross section (RCS), the solution can also generate micro-Doppler signatures, enabling more realistic test scenarios for applications such as drone detection and supporting the development of advanced sensing capabilities.

Visitors will find Rohde & Schwarz at booth B10 at Excel London from October 6 to 8, 2026, where they can learn how next-generation test solutions support engineers from component characterization to system-level validation across radar, satellite, wireless and aerospace and defense applications. In addition, experts from the company will contribute to the EuMW 2026 with presentations and workshops as part of the European Microwave Conference (EuMC) as well as the European Radar Conference (EuRAD).

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Infineon Technologies and SolarEdge Technologies, have expanded their existing collaboration to include Solid-State Circuit Breaker (SSCB) technology for high-voltage DC distribution in AI and hyperscale data centres. The collaboration addresses a key challenge in adopting 800 VDC architectures: achieving selective protection while maintaining high efficiency requires extremely fast fault isolation.

Expanding the partnership into solid-state protection addresses an important gap in the distribution layer between the Solid State Transformer (SST) and the compute rack, further advancing the end-to-end grid-to-rack concept. SolarEdge is leading the design of the Solid-State Circuit Breaker (SSCB) solution, while Infineon contributes its silicon carbide (SiC) JFET technology as a core component of the protection switch.

Rapidly increasing AI compute density is pushing the data-centre industry toward higher-voltage DC distribution architectures. In this environment, solid-state circuit breakers (SSCBs) address the need for fast and selective fault protection. Unlike AC systems, DC systems do not have a natural current zero, making fault interruption more challenging and potentially resulting in arcing when conventional mechanical breakers are used.

SSCBs overcome this limitation by using power semiconductors to interrupt fault currents in the microsecond regime, without mechanical contacts and the associated arcing. Infineon’s CoolSiC JFET technology combines low conduction losses, fast turn off capability and high robustness, making it suitable for solid-state protection applications. These characteristics can help protect high-value compute hardware from fault-related damage while supporting compact and power-dense DC distribution architectures.

The collaboration builds directly on SolarEdge’s SST platform with Infineon SiC components, first announced in November 2025. The SST is designed to enable direct medium-voltage (13.8-34.5 kV) to 800-1500 VDC conversion at over 99 percent efficiency, collapsing multiple conversion stages into a single solution while reducing physical footprint.

“High-density AI infrastructure at 800 VDC demands uncompromising efficiency and protection”, said Shuki Nir, Chief Executive Officer of SolarEdge. “Solid-state protection will enable operators to achieve both, delivering ultra-fast and dependable fault isolation without sacrificing conversion performance. Infineon’s silicon carbide technology is what makes it practical at scale.”

“Today’s data infrastructures have become more vulnerable to electrical faults, thereby driving the demand for smarter, faster and more robust power distribution systems,” said Andreas Weisl, Executive Vice President and Chief Sales Officer of Industrial & Infrastructure at Infineon. “By combining our advanced silicon carbide JFET technology with SolarEdge’s expertise in final power distribution, we are addressing these demands to ensure fast, safe and reliable operations in AI data centers.”

Building on more than 15 years of leadership in DC-coupled power electronics, SolarEdge is developing an 800 VDC powertrain for AI factories, a DC-native chain that carries power from the medium-voltage grid connection through conversion, distribution and protection to the compute rack. Infineon’s broad portfolio of silicon, silicon carbide and gallium nitride solutions provides that foundation, supporting the decarbonisation of AI infrastructure through lower losses, reduced environmental impact, and improved total cost of ownership.

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This year, the emphasis of Electronica, Bengaluru, is on a presentation of new inspection systems. Making its presence felt, GOPEL electronic will present an array of new products at the exhibition. The Multi Line AXI X-ray inspection platform marks a new generation of inspection systems for electronic assemblies that brings a new dimension of quality to electronics manufacturing.

Multi Line AXI combines advanced technological innovations with flexible application options and multifunction capabilities, while also offering simple and rapid adaptability to inspection tasks. This innovative AXI marks a new benchmark in X-ray inspection while supporting manufacturers in maintaining consistent quality in electronics production.

The all-purpose Multi Line is ready for all inspection tasks throughout the entire manufacturing process which includes SPI (Solder Paste Inspection), SMD (Surface-Mount Device) and THT (Through-Hole Technology) processes. Due to the modularity of the Multi Line platform, camera modules can be configured according to specific requirements and are available for other process applications through rearrangement, if ever required.

Fast test program generation, bilateral inspection and the use of a common operating platform are characteristics of devices from the Multi Line AOI platform, which ensure high quality of production at high-mix/low volume production, prototyping, and small batch sizes. The Vario Line systems combine high-speed inspection with high defect-detection performance, setting new standards in precision and efficiency through intelligent 2D/3D inspection and variable 360-degree inspection in 1-degree increments.

In the field of electrical testing and programming, GOPEL electronic’s in-system programming and boundary scan products will take centre stage: For example, the FlashFOX universal programmer supports the dynamic transfer of programming data—the programmer always retrieves the latest content to be programmed from the central server. In addition to the 8-channel version, the new FlashFOX 2 can also implement complex power supply configurations for the microcontrollers or flash devices to be programmed, thanks to four integrated independent power supplies.

The turnkey BARCUDA tester is a complete solution for testing and programming PCBAs. The stand-alone unit utilises the proven technologies of GOPEL Electronics’s Embedded JTAG Solutions, but can also be expanded to meet the functional test requirements of electronics manufacturing. The BARCUDA JTAG production tester tests and programs PCBAs with or without JTAG/boundary scan without the need for time-consuming configuration of a specialized in-house test system.

The JULIET unlimited JTAG tester is a professional, flexible JTAG/boundary scan tester that combines the entire system electronics and DUT adaptation into a single, complete unit. A total of six different models cover all production applications from simple test execution to a complete repair station with graphical fault visualisation making the system ideal for rapid prototyping and low-volume production runs.

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​Arrow Electronics has made global remote access available to customers through its Digital Test Drive platform for evaluating NXP Semiconductors’ Ara240 discrete neural processing unit (DNPU). This gives engineers early access to run, test, or evaluate real-world performance for advanced AI models and technologies for computer vision, generative AI & multimodal systems before purchasing.

This trend comes as AI is being more heavily deployed in industrial, robotics, and intelligent vision applications, and developers now look forward to implementing more advanced AI applications close to the generation of data. Operating AI locally at the edge brings advantages such as limited latency, enhanced data privacy, and restricted reliance on cloud-hosted computation, as for those with real-time requirements.

To enable customers to discover and examine this functionality. Arrow has also included NXP’s Ara240 solutions on its Digital Test Drive, a digital test platform offered by Arrow on the web. Arrow’s Digital Test Drive, a ‘digital test platform,’ is a remote hardware test and development platform hosted in the cloud. It allows users to test real hardware, remote devices without actually owning and having a target device on their desk.

Engineers can test live systems with NXP i.MX applications processor and the Ara240 DNPU over remote systems that let engineers explore real world AI applications like computer vision, LMM inference and vision language AI without having to rely on specifications or benchmarks. From these systems, engineers can better test their intended use case for their particular project before investing hardware money and system architecture.

“Developers need practical ways to understand how advanced AI technologies will perform in real applications,” said Justin Mortimer, senior director, product marketing, Secure Connected Edge, NXP Semiconductors. “By providing access to NXP’s Ara240 DNPUs through Digital Test Drive, Arrow enables engineering teams to evaluate real-world edge AI performance faster and make informed design decisions.”

“At Arrow, we are committed to helping customers accelerate their AI journey by removing barriers between innovation and deployment,” said Shelby Schnurrenberger, vice president of supplier management, global semiconductor, Arrow Electronics. “By integrating NXP’s Ara240 AI accelerator into our Digital Test Drive platform, engineers can evaluate advanced edge AI workloads immediately, gaining hands-on experience with the technology before making hardware investments.”​

​“Together with NXP, we are enabling customers to move faster from concept to production and unlock new opportunities in intelligent edge applications. Digital Test Drive extends global access to NXP’s AI portfolio, allowing engineers to validate performance, explore use cases, and shorten development cycles from anywhere in the world. This collaboration reinforces our shared commitment to making edge AI more accessible, scalable, and practical for customers across industrial, robotics, machine vision, and emerging intelligent systems.” Schnurrenberger stated.

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ST is introducing an initiative to provide Rust drivers for many of our sensors, opening a new avenue for those looking to adopt this programming language in their embedded systems development. Obviously, we will continue to ship and maintain our C-based ecosystem.

However, we are also aware of the growing popularity of the Rust programming language, the benefits it offers for many projects, and that building a robust, platform-agnostic alternative in another programming language takes significant time and investment. It’s for those reasons that we have started porting drivers piecemeal and are now advertising our presence on crates.io and showcasing projects like Embassy STM32, which provides a hardware abstraction layer in Rust for our MCUs.

One of the most popular aspects of Rust is its inherent code safety compared to other languages, including C and C++. In essence, that means the Rust compiler will forbid certain operations that could jeopardise memory safety. Being memory-safe means that the Rust compiler will block any memory access if it hasn’t been explicitly allocated or has already been deallocated. This is a significant departure from C and C++, where developers have much more freedom in memory management. However, it also means that bad code can lead to issues such as buffer overflows, memory leaks, and “use-after-free” or dangling pointers. All of these can result in data corruption or even security vulnerabilities.

The reason Rust is safer is that it implements Resource acquisition is initialisation (RAII), a technique that automatically and immediately allocates resources when an object is created and releases them when the object is deleted. The compiler allocates these resources to an owner and can then transfer ownership or allow another owner to borrow it if needed. As a result, Rust handles resource management and does not need a garbage collector to manage memory allocations, unlike C++, another language that implements RAII but still requires developers to manage memory themselves. In practice, the absence of a garbage collector reduces overhead, but it also makes Rust code much less lenient.

While this blog post can’t begin to scratch the surface of all the ways Rust differs from C and C++ (we won’t even go into type safety), the point above illustrates an important reason why developers are moving to Rust and why ST has already tried to provide alternatives to its sensor drivers. The Rust learning curve is high. Writing safe code that compiles is challenging because there are so many guardrails to ensure code safety. However, it also means that once the code compiles, developers have far greater assurance of safety and security. And for developers new to Rust, having open-source drivers like the ones ST provides means they can study our implementations and learn from our experience.

Another reason developers are adopting Rust for their embedded projects is the way it handles interfaces and bus operations. Unlike C, which traditionally uses a pointer-based bus abstraction, Rust uses “Traits”, which define interfaces as types and then provide a flexible abstraction over them. Through ecosystem standards such as embedded-HAL, interfaces for buses like I2C and SPI can be implemented consistently across platforms, helping developers gain expertise. In fact, our code already uses APIs aligned with our original C drivers to ease the learning curve, and we adopted consistent naming to smooth the transition to our Rust alternative.

One misconception we often encounter is that Rust is inherently “faster” than C or C++. The truth is far more nuanced. Depending on the application, Rust may be slower than, on par with, or faster than C. However, in many instances, Rust forces teams to rewrite their application, which naturally leads to refactoring, dropping legacy code, or creating new, optimised processes. The absence of a garbage collector in Rust, or its modern compiler enhancements, certainly helps, but embedded system developers should not rush in thinking it will magically provide significant runtime improvements. However, it will offer significantly safer, often more flexible code, which is why we are providing Rust alternatives for our C sensor drivers.

The discussions in our GitHub repository for this project show a thriving community, which is an important factor for many developers. It’s not just key industry players like Meta, Google, or Microsoft that have publicly pledged to adopt the new programming language. Many smaller teams are investing in the new language because acquiring fluency takes time, and falling behind could lead to significant technical debt that would benefit a competitor. We know that adoption is still in the early phase. This is why we are providing Rust sensor drivers now. ST wants to support those who want to be first in this transition, which seems to be shaping the future of embedded systems development.

The best way to get started is to install Rust using rustup, then, as developers build their project, grab one of our packages on Crates. Our GitHub Page also walks users through the download and integration process. We offer examples in Cargo to help teams get results faster. And while the drivers themselves allow engineers to be MCU-agnostic, the examples we use are written for STM32 microcontrollers and primarily use the NUCLEO-F401RE development board. Current Rust drivers focus on I2C and SPI interfaces, as these are by far the most commonly used, but additional support, including I3C, is underway, and we will update this blog post as we release major updates.

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In a significant addition to India’s growing portfolio of home-grown enterprise intellectual property, Novac Technology Solutions, a distinguished leader in technology and AI solutions, has secured an Indian patent for its proprietary innovation, “System and Method for Managing a Project by Integrating Set of Modules” (Patent No. 595218). Designed and developed in India, the platform addresses one of the software industry’s most persistent challenges: fragmented project execution, highlighting the country’s growing role in creating globally relevant enterprise technologies through indigenous engineering and innovation.

Granted by the Indian Patent Office under the Controller General of Patents, Designs and Trade Marks (CGPDTM), the patent provides protection for Novac’s patented invention to enterprise software delivery. The innovation brings together every critical stage of the software development lifecycle, including project estimation, scheduling, project reviews, testing, defect tracking and maintenance, into a unified platform that enables organisations to manage software projects through a connected ecosystem rather than disconnected tools and workflows.

As software development becomes increasingly complex, organisations often rely on multiple tools to manage project estimation, planning, scheduling, testing and maintenance. While each serves a specific purpose, disconnected systems often result in fragmented workflows, manual coordination, inconsistent tracking and limited visibility across teams. Novac’s patented innovation addresses this challenge by integrating the key stages of software project management into a single integrated platform, enabling integrated information flow, stronger collaboration and a unified view of project execution.

A key differentiator of the patented platform is its dynamic scheduling and task-dependency management capability, which automatically updates interconnected tasks whenever changes are made to lower-level activities. This reduces manual intervention, improves planning accuracy and helps organisations improve resource utilisation while adapting to changing project requirements. The platform also integrates testing, defect management and project reviews, providing end-to-end traceability, better governance and timely insights that enable better-informed decision-making throughout the software delivery lifecycle.

Speaking about the patent, Mr. N.S Nanda Kishore, Managing Director & CEO, Novac Technology Solutions said, “Software engineering is becoming increasingly interconnected, yet many organisations continue to manage complex projects through disconnected systems and fragmented workflows. The future of enterprise software delivery lies in creating intelligent ecosystems that connect every stage of the development lifecycle, enabling greater visibility, seamless collaboration and informed decision-making. This patented solution reflects Novac’s continued commitment to engineering innovation by bringing an integrated approach to software project management.”

The patent marks an important milestone in Novac’s innovation journey and further strengthens its intellectual property portfolio. More broadly, it reflects the evolution of India’s technology ecosystem, where companies are increasingly creating proprietary enterprise technologies alongside delivering world-class technology services. As organisations worldwide continue to modernise software engineering and digital operations, innovations developed in India are playing an increasingly important role in shaping the future of enterprise technology.

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Critical Manufacturing, the Industrial Operations Platform company that unites execution, connectivity, analytics and trusted AI, will exhibit at SEMICON India from September 17–19, demonstrating how semiconductor manufacturers can establish connected, data-driven operations that support intelligent production.

Exhibiting in collaboration with ASMPT, Critical Manufacturing will bring its vision of the factory of the future to life, showing how manufacturers can transform operational complexity into actionable intelligence through a unified platform.

India is moving from semiconductor ambition towards ecosystem development, with investment spanning fabrication, compound semiconductors, assembly and testing, advanced packaging and chip design. As new manufacturing capacity is established, companies will need to build digital production foundations that can support quality, traceability and coordination from the outset.

At SEMICON India, Critical Manufacturing will demonstrate how its Industrial Operations Platform extends beyond traditional Manufacturing Execution Systems (MES). MES acts as the execution core within a broader platform that continuously connects production data, analytics and AI, enabling a closed-loop system where insights are generated and acted upon in real time.

For manufacturers developing new semiconductor operations, decisions made at an early stage can shape production performance for years to come. Establishing consistent processes, data structures and traceability from the beginning helps prevent fragmented systems from developing as facilities, product portfolios and production volumes grow.

The platform captures data at source, structures it across equipment, systems and sites, and provides the operational context needed to support informed decisions. This gives manufacturers a foundation that can scale with their operations while maintaining control over quality and production processes.

Visitors will be invited to “step into the factory of the future” through live demonstrations showing how machines, processes and data can be connected across the shopfloor.

The demonstration will highlight how real-time information flows between equipment and manufacturing systems, helping teams understand relationships between process conditions and production outcomes. This supports a shift from reacting to problems towards anticipating and addressing issues before they affect quality, output or delivery.

Together, these capabilities reflect the industry’s transition from digital transformation to intelligence-driven operations. By incorporating connectivity and manufacturing intelligence from the beginning, manufacturers can support continuous learning and improvement while avoiding isolated systems that later become difficult and costly to integrate.

“India has an important opportunity to build modern semiconductor operations without being constrained by the fragmented legacy systems found in many established manufacturing environments,” said Weng Keong Lan, Managing Director of Critical Manufacturing Malaysia, responsible for India’s Go-to-Market. “As new facilities and capabilities are developed, manufacturers can put the right execution, connectivity and data foundations in place from the outset rather than attempting to integrate them later.”

A key feature of the demonstration will be Critical Manufacturing’s AI Copilots, embedded directly within the MES environment. The copilots enable users to interact with manufacturing data using natural language and generate dashboards, charts and insights without complex queries or specialist expertise.

By making production information easier to access and interpret, AI Copilots can help engineers, operators and decision makers investigate changing conditions, identify trends and respond with greater confidence.

The joint presence with ASMPT reinforces the importance of considering manufacturing equipment and software as part of one coordinated production environment. Closely connected equipment and software ecosystems can provide greater coordination, control and performance across the production lifecycle.

Lan added, “At SEMICON India, we will demonstrate how a unified Industrial Operations Platform can help manufacturers standardise processes, establish end-to-end traceability and maintain control as production scales. Building these capabilities early will be essential if India’s growing semiconductor ecosystem is to translate investment into reliable, high-quality manufacturing.”

Visitors to SEMICON India 2026 can experience live demonstrations at the ASMPT booth 1346, where Critical Manufacturing experts will showcase how the Industrial Operations Platform supports connected and intelligent semiconductor manufacturing.

Attendees are invited to explore how the platform can help manufacturers establish scalable operations, maintain production traceability and manage increasing complexity as facilities and output grow.

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The demand for low-voltage clock drivers continues to grow with the rapid adoption of advanced FinFET process nodes used in high-performance FPGAs, SoCs, AI accelerators and next-generation CPUs. Printed circuit board designers face increasing challenges due to the limited availability of standard 1.2V LVCMOS clock buffers and level-translating buffers capable of converting higher-voltage clock signals to the lower-voltage levels required by these advanced devices. Conventional approaches that rely on discrete components and voltage-divider techniques can compromise signal integrity and clock duty cycle accuracy while increasing board complexity and component count.

Microchip Technology has introduced the SY757xx family, a comprehensive portfolio of 1.2V-output LVCMOS clock buffers, designed to address these challenges. The new devices simplify system design by eliminating the need for traditional discrete component implementations while delivering ultra-low additive jitter performance. To provide flexibility for supporting legacy board power supplies and different clock-source voltage levels, the devices support a broad range of supply voltage (VDD) and a wide operating frequency range. The SY757xx family enables ultra-low additive jitter clock distribution while maintaining the high clock resolution and signal integrity required for today’s high-speed FPGA, SoC and CPU platforms.

“Our SY757xx family of clock buffers helps customers overcome the growing clock distribution challenges associated with next generation high-performance FPGA, SoC and CPU platforms,” said Maamoun Abou Seido, appointed vice president of Microchip’s timing and communications business unit. “By combining ultra-low additive jitter performance with broad VDD and wide frequency support in a single-chip solution, the SY757xx devices simplify board design, reduce component count and help customers maintain the signal integrity and timing accuracy required in today’s high-performance computing applications.”

Microchip’s SY757xx family strengthens the clock buffer’s role as a critically important SoC and FPGA interface for clock distribution and clock fanout functionality in application platforms where signal integrity is paramount. These platforms demand high-speed parallel processing, hardware reconfigurability, low latency and efficient real-time computing. These capabilities are required for applications ranging from embedded vision and video processing to AI/ML acceleration, industrial control and IoT, networking and communications, and signal processing and embedded systems.

Launching three products in production and eight that are sampling in limited volumes, the family spans a wide array of configurations in three space-saving packaging options. The devices protect against clock distortion across a 0 Hz to 250 MHz frequency spectrum while also offering a broad range of power supply input and output options across the 1.2V to 3.3V voltage-translation input range. This includes a single-chip option that reliably interconnects 3.3V components to FPGAs and SoCs with a 1.2V clock signal requirement. Additive jitter is as low as 26 femtoseconds (fs).

Compared to traditional discrete component solutions for these FPGA and SoC applications, the Microchip buffers simplify design and reduce bill-of-materials costs while helping to optimize AC coupling and biasing and maintain signal integrity. Voltage dividers using discrete components may not provide adequate design margin and can degrade signal integrity by causing duty-cycle distortion.

Microchip clock buffers complement the company’s comprehensive range of flash-based FPGAs and SoC FPGAs spanning ultra low density to mid-range density devices. These and other Microchip products that range from microcontrollers and analog components to power management, timing, connectivity and memory devices are pre-engineered and validated to enable a simplified, lower-risk and more holistic approach to system design.

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India is one of the favourite destinations for international tourists, but security concerns often curtail the opportunities and growth prospects. The Indian tourism sector needs to tap this opportunity by sprucing up its act with adequate security measures and adoption of the latest security technologies to assure the large pool of tourists travelling to India’s popular tourist destinations.

When planning a security strategy for the tourism sector, one needs to understand the key challenges and threats that exist in India’s vast tourism sector. The Indian tourism sector includes popular tourist destinations, national monuments and cultural heritage sites. Religious tourism offers diverse options for tourists; there are many world-famous places of worship in India that attract millions of visitors from around the world. India offers a wealth of opportunities for religious tourism, attracting millions of pilgrims and spiritual seekers from around the world.

Tourism in India faces several security challenges that can impact both domestic and international travelers. Here are some of the key issues:

Safety and Security: Concerns about the safety of tourists, especially women, have been prominent. Incidents of theft, harassment, and even violence have been reported, which can deter potential visitors.

Infrastructure: Inadequate infrastructure, including poor transportation and healthcare facilities, can pose risks to tourists. This includes issues like unsafe roads and lack of emergency medical services.

Environmental Degradation: Overcrowding and lack of proper waste management at popular tourist spots can lead to environmental degradation, which not only affects the natural beauty but also poses health risks.

Regulatory Challenges: The tourism sector often faces regulatory hurdles, including complex visa processes and inconsistent enforcement of safety regulations.

Human Resources: There is a shortage of skilled manpower in the tourism and hospitality sectors, which can affect the quality of services and safety measures available to tourists.

Security & Safety Awareness: Insufficient media promotion about tourism security and safety awareness protocols and guidelines lead to uncertainity and misinformation among tourists.

Addressing these challenges requires coordinated efforts from the government, private sector, and local communities to ensure a safe and enjoyable experience for all tourists.

Advanced video security solutions can significantly enhance the safety and security of tourists in several ways:

Video Security and Monitoring: High-definition cameras installed at key tourist spots, hotels, and public transport hubs can monitor activity in real time. This helps quickly identify and respond to any suspicious behaviour or incidents.

Crime Deterrence: The presence of visible security cameras can deter potential criminals. Knowing they are being watched reduces the likelihood of theft, vandalism, and other crimes.

Incident Response: In the event of an incident, video footage can provide crucial evidence to law enforcement agencies. This helps in the swift resolution of cases and enhances the overall sense of security.

Crowd Management: Video analytics can help manage large crowds at popular tourist destinations. By analysing foot traffic patterns, authorities can prevent overcrowding and ensure smooth movement of people, reducing the risk of accidents.

Emergency Situations: In emergencies, such as natural disasters or terrorist attacks, video security can provide real-time information to emergency responders, helping them to coordinate their efforts more effectively.

Enhanced Visitor Experience: By ensuring a safe environment, video security solutions can enhance the overall visitor experience. Tourists are more likely to enjoy their stay and recommend the destination to others if they feel secure. Implementing these solutions requires collaboration among local authorities, private-sector stakeholders, and technology providers to create a comprehensive security network that prioritises the safety and well-being of tourists. Places of worship face several unique security challenges, balancing the need to be open and welcoming with the necessity of ensuring safety. Here are some of the key challenges:

Open Access: Places of worship are designed to be open and accessible to everyone, which can make it difficult to control who enters and exits the premises.

Vandalism and Theft: These locations can be targets for vandalism and theft, especially if they house valuable artefacts or donations.

Violence and Terrorism: Unfortunately, places of worship can be targets for violent attacks, including hate crimes and terrorism. Ensuring the safety of congregants during services and events is a significant concern.

Cybersecurity: With the increasing use of digital systems for managing operations and communications, places of worship are also vulnerable to cyberattacks. This includes threats like ransomware, data breaches, and online harassment.

Emergency Preparedness: Many places of worship may lack comprehensive emergency response plans. This includes preparedness for natural disasters, medical emergencies, and other unexpected incidents.

Addressing these challenges requires a holistic approach that includes physical security measures, community engagement, and emergency preparedness planning. Collaboration with local law enforcement and security experts can also enhance the safety and security of these important community spaces.

Securing Places of Worship: Installing video security cameras and security systems can significantly enhance safety and provide peace of mind for devotees. By implementing these measures, places of worship can create a secure environment that allows congregants to focus on their spiritual activities without safety concerns.

Protecting Cultural Heritage Sites: It requires a combination of advanced security systems and thoughtful planning to preserve their historical and aesthetic value. By combining advanced security measures, cultural heritage sites can be effectively protected while maintaining their historical integrity and ensuring a safe and enjoyable experience for visitors.

PRAMA offers advanced Security  Solutions for Tourism, Cultural Heritage Sites and Religious Places. PRAMA offers a range of specialised security solutions tailored for tourism, cultural heritage sites, and religious places.

Here are some of the  key offerings for the tourism sector:

Smart Video Security Systems: These include advanced CCTV cameras with AI capabilities for real-time monitoring and threat detection. The systems are designed to ensure the safety of tourists and protect valuable cultural assets.

Integrated Remote Monitoring Intrusion Solutions (IRMIS): This solution enables centralised monitoring across multiple sites, providing a comprehensive security overview and rapid response capabilities.

AI Sense Solutions: Utilising artificial intelligence, these solutions enhance security by identifying potential threats and unusual activity, enabling proactive measures.

Advanced Traffic Management Systems (ATMS): These systems help manage and monitor traffic around tourist sites and religious places, ensuring smooth and secure access for visitors.

Specialised Temple Solutions: Tailored for religious places, these solutions include high-definition cameras and access control systems to manage large crowds and ensure devotees’ safety. PRAMA India’s solutions are designed to provide robust security while maintaining the sanctity and accessibility of cultural and religious sites.

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Murata Manufacturing Co., Ltd. has expanded the line-up of its automotive-grade metal power inductors in the DFE2MCPH_JL series by adding nine new inductance values. This expanded line-up enables broader support for the diverse circuit design requirements of automotive power circuits used in advanced driver assistance systems (ADAS), in-vehicle infotainment (IVI), and other automotive electronic equipment. Mass production has already begun.

In recent years, the increasing performance and functionality of ADAS and IVI systems have driven demand for automotive power circuits that are smaller, more efficient, and lower in power loss. At the same time, increasingly diverse power supply requirements across different applications have created the need for a wider range of inductance values, allowing designers to select the most suitable inductor for each power circuit.

To address these market requirements, Murata has added nine new inductance options to the DFE2MCPH_JL series. Despite their compact 0806-inch (2.0 × 1.6 mm) package, the new inductors achieve low DC resistance, high current capability, and 40 V withstand voltage. They are also compliant with the AEC-Q200 automotive qualification standard, making them well suited for power circuits used in increasingly sophisticated automotive electronics, including ADAS and IVI systems. By expanding the available inductance range, Murata enables designers to select the optimum inductance value according to application and power supply requirements, thereby improving design flexibility for automotive power circuits.

Murata will continue expanding its line-up of automotive-grade power inductors to meet evolving market needs and contribute to further advances in vehicle performance, functionality, and electrification.

≪DFE2MCPH_JL Seres Specifications≫

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Power designs now face the same demands at the same time: higher efficiency, smaller size, lower cost, and more power from the same space. For years, silicon has supported these designs. However, in a growing number of applications, it is close to its practical limits, and further optimisation increases losses and heat.

For this reason, gallium nitride (GaN) power transistors are receiving significant attention. ST has added a new 700 V and 100 V PowerGaN family to its portfolio and brings these advantages to mainstream power conversion. This article explains what the technology offers power designs and why it matters now.

Gallium nitride is a wide-bandgap semiconductor and, in a power converter, its main advantage is speed. Gallium nitride (GaN) power transistors, also called gallium nitride high electron mobility transistors (GaN HEMTs), switch much faster than silicon devices and lose less energy each time they turn on and off. Two effects follow from this behaviour. Less energy is wasted as heat, and the converter can operate at a higher switching frequency without losses increasing as they do with silicon.

Almost every benefit of GaN results from these two effects. Until recently, the technology appeared mainly in specialised, high-end products where the cost was justified. With a broad 700 V to 100 V family now in production, GaN has become a practical choice for everyday power conversion across a wide range of designs.

The clearest benefit is efficiency. Because GaN has low conduction and switching losses, more of the input power reaches the load, and less of the power turns into heat. In ST reference designs, PowerGaN has achieved power-supply efficiency of up to 98.6%. Higher efficiency affects the entire design: lower operating costs, less energy consumption over the product life cycle, and lower demand on the cooling system.

For equipment that operates continuously, such as power supplies, lighting, and energy systems, even a small efficiency gain accumulates over thousands of operating hours. Efficiency is usually the first reason that a design team considers GaN, and it leads directly to the next two benefits.

The second benefit is size. A higher switching frequency allows the bulky magnetic components and filters in a converter to shrink, and the rest of the design shrinks with them. That creates two options for a design team: deliver the same power in a smaller, lighter product, or fit more power into an existing enclosure.

Gallium nitride (GaN)-based designs have reached an average size reduction of around 50%, compared with earlier silicon equivalents, at power densities above 100 watts per cubic inch. For products with tight space and weight constraints, such as compact adapters, chargers, and on-board systems, that extra headroom can determine whether a design fits at all. Increased power density is where the move to GaN becomes visible in the finished product.

The third pillar is lower system cost. It results as much from the design around the transistor as from the device itself. A gallium nitride (GaN)-based converter uses smaller passive components and fewer passive components and often requires little or no heat sink. As a result, the overall system cost decreases, and the design is simpler.

Cooler operation also improves reliability and life cycle, which means that the system tends to last longer and requires less servicing. Lower energy consumption over the product life cycle adds to the savings. Together, these effects reduce the cost of building and operating the system, and they are a large part of why GaN deserves its place in a design.

These benefits are not tied to a single product type. The same value higher efficiency, greater density, and lower total cost) extends across a broad range of designs, including AC-DC and DC-DC power supplies, USB Type-C adapters and chargers, LED lighting, motor control, AI servers, robotics, industrial systems, and advanced consumer applications such as home appliances, as well as power and energy systems such as solar and storage. The same value also supports the growing power demands of computing and electrification.

Across these areas, priorities differ, but the same three advantages apply. A choice of package options allows a design team to match the device to the power level and board layout of each application. Because the 700 V & 100V PowerGaN family is already in production and available, these benefits can already be built into designs today.

Adopting a new switching technology is a decision about support as much as about the device itself. Alongside the 700 V and 100 V family, ST brings decades of power semiconductor experience, a broad product portfolio, a reliable supply chain, and strong technical support. For a team that works with GaN for the first time, that combination reduces the risk of the transition and shortens the path from an idea to a working design. It is part of what makes the value of PowerGaN practical rather than theoretical.

GaN power transistors provide higher efficiency, greater power density, and lower system cost for power conversion. The new 700 V and 100 V PowerGaN family makes these benefits available to mainstream designs. For a design team that is considering the move to GaN, the technology has reached the point at which its advantages are practical today rather than promised for tomorrow.

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Aheesa Digital Innovations, a DLI-scheme backed fabless semiconductor company headquartered in Chennai, has signed a Memorandum of Understanding (MoU) with Optilink Networks Pvt. Ltd., onboarding the company as its packaging partner for VIHAAN-I, Aheesa’s indigenous RISC-V broadband networking System-on-Chip (SoC). The partnership marks another step towards commercialising VIHAAN-I, strengthening the pathway from indigenous chip design and silicon validation to packaging, distribution and market deployment.

The partnership brings together two complementary parts of the broadband technology ecosystem. Optilink has supported the VIHAAN-I journey through testing, validation and engineering support, with its in-house capabilities across product design, firmware development and hardware integration. Under the MoU, Optilink will support end-to-end product development from prototyping to packaging, while the companies work towards developing, qualifying and commercialising ONT/CPE products based on the VIHAAN-I chipset. The collaboration is aimed at delivering solutions that are cost-efficient and comply with Indian and global standards, while accelerating commercialisation through Optilink’s engineering and manufacturing expertise.

This further advances Aheesa’s ambition to establish itself as a semiconductor design house with a portfolio of Indian-designed chips serving both domestic and global markets. With design, silicon validation, packaging and distribution capabilities progressively coming together, Aheesa is now leaping towards commercial deployment in early 2027.

The partnership comes in a landmark year for Aheesa. VIHAAN-I achieved tape-out on Republic Day 2026, followed by Aheesa securing investment from the Tamil Nadu Infrastructure Fund Management Corporation (TNIFMC) through the Tamil Nadu Emerging Sector Seed Fund. On this Independence Day, the chip achieved first-pass silicon success on its very first attempt.

Commenting on the partnership, Sridharan Mani, Founder and CEO, Aheesa Digital Innovations, said, “Building a chip is only half the journey as the real test is turning that silicon into a product people can use. No semiconductor ecosystem thrives on the strength of one player alone; it takes multiple partners, each doing their part, to carry a design to the consumer and make this sector succeed. With Optilink joining us for packaging, VIHAAN-I takes a step closer to that reality. We have spent years estabilishing that world-class semiconductor design can happen in India. Now with Optilink, we’re building the pathway to take it from systems to scale.”

Devchand Haria, Managing Director, Optilink Networks Pvt. Ltd said, “At Optilink, we’ve spent close to two decades building the networking hardware that connects Indian homes from fiber access to broadband CPE. Partnering with Aheesa for VIHAAN-I lets us bring that same experience to an Indian-designed chip, taking it from silicon to the products that will actually sit in Indian households. This is exactly the kind of collaboration our sector needs, that is Indian design and Indian manufacturing expertise working together to put homegrown silicon inside the devices people use every day.”

Founded in 2005 and headquartered in Mumbai, Optilink Networks Pvt. Ltd. is an Indian Original Equipment Manufacturer (OEM) that designs, manufactures and distributes IP-based networking hardware, Fiber-to-the-Home (FTTH) solutions and IP Television (IPTV) technologies. Serving ISPs, telecom operators, cable and MSO networks, enterprises and government customers, Optilink has built a strong B2B presence through its channel partners, distributors and system integrators across India.

Aheesa’s work spans indigenous semiconductor and networking technologies across telecom, broadband, cybersecurity and edge computing. This partnership now reflects the wider momentum in India’s semiconductor design ecosystem, now scaling under Semicon 2.0 — the ₹1,27,500 crore programme approved in July 2026 to build a globally competitive supply chain across chip design, manufacturing, packaging and materials. As indigenous designs move from validation towards commercial adoption, it is partnerships like this, pairing Indian chip design with the reach to deploy it, that will help define how homegrown silicon scales.

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Infineon Technologies AG introduces the TDA235E5 and TDA235E0, a dual-phase smart power stage family designed to meet the rapidly growing power density requirements of next-generation AI accelerators and vertical power delivery modules. Integrating Infineon’s OptiMOS 6 MOSFETs and a dual-phase driver IC in a compact 6 x 6 x 0.8 mm³ package, the new family delivers benchmark power density exceeding 2 A/mm², setting a new reference point for power stage performance in high current AI processor applications. As hyperscalers and datacenter operators continue to scale AI infrastructure, the demand for power delivery solutions that combine higher current capability with shrinking physical footprints is becoming a critical bottleneck.

“Infineon customers are designing AI systems that will define the next decade of computing infrastructure,” said Rakesh Renganathan, Vice President Power ICs at Infineon. “The TDA235E5 and TDA235E0 power stages give designers the power density, thermal performance, and design flexibility to move faster and build with confidence, backed by Infineon’s full AI server power delivery ecosystem.”

The two devices support up to 300 A peak current and 120 A total design current (TDC), making them well suited for next generation AI xPU accelerators as well as conventional server CPUs in datacenter environments. Both lateral and vertical power delivery configurations are supported, providing the design flexibility required as the industry transitions toward vertical power module architectures in advanced AI processor packages. Superior thermal impedance from junction to top side enables efficient liquid cooling integration, a characteristic that is increasingly important as power levels per processor socket continue to rise and traditional air-cooled thermal budgets are exhausted. Combined with Infineon’s digital multiphase controllers, the power stages support flexible, scalable multi-rail architectures that reduce time to deployment in fast-evolving AI server platforms.

The TDA235E5 and TDA235E0 integrate into Infineon’s end-to-end AI server power delivery ecosystem, spanning the full power chain from grid interface to processor core rails. By combining the complementary strengths of silicon, silicon carbide, and gallium nitride, Infineon provides datacenter customers with a proven, scalable path to the highest efficiency, robustness, and power density available for AI-optimized infrastructure. The datacenter power delivery market is one of the semiconductor industry’s fastest-growing demand segments, driving Infineon’s continued product investment to serve this opportunity at the component level where power density requirements are most critical. 

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Synopsys, COEP Technological University and CADFEM India have setup the “Ansys Digital Twin & Multiphysics Lab” on the COEP campus, Pune to support advanced engineering education, research, and strengthen the industry-academia partnerships. This program holds huge significance in an ecosystem for automotive and electrical vehicle industry which utilizes the technologies for vehicle system’s product development and validation processes.

The laboratory was established as a part of Memorandum of Understanding (MoU) signed during the 2026 Symposium. It will provide students, researchers, and faculty members access to Ansys digital-twin technologies and advanced high-end multiphysics simulation tool that have been acquired by Synopsis. The lab will host industry training and certification, technical seminars and research.

Multiphysics simulation has a potential role in analysis of different physics domains in development process of the vehicle or component within EV industry. Engineers are able to investigate on battery thermals, electric motor efficiencies, power electronics functionality, structural strength, electromagnetic phenomenon and thermal management by simulation work-flows prior build physical prototype. Digital-twin methodology can create bridge between physics-based models and actual data taken from sensors and operation data so to monitor and predict system behaviours.

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​India’s rapidly growing EV industry faces a capability gap in developing and producing high-technology components that can meet modern technology demands because about 80% of component manufacturers are small businesses built for traditional mechanical parts rather than advanced electronics and software. The capability gap involves areas such as batteries, power electronics, embedded software, advanced electronics, and system integration.

India is shifting more towards electric vehicles as its automotive supply chain expands. Original Equipment Manufacturer (OEM) sourcing of auto-components is expected to increase by 16% to 6.6 lakh crore by FY26 against components’ exports valued at around 2.1 lakh crore. However, import charges rise at a greater rate, with China covering about 36% of all the auto component imports India uses.

The capability challenge is particularly significant for small and medium-scale enterprises (MSMEs), which constitute almost 80% of Indian auto-parts producers. Though electronics, embedded software, advanced engineering, and system integration are key factors for competitiveness, a lesser than half the small and medium scale enterprises lack the capabilities required to develop and manufacture components as per the modern industry demands. Embedded software capability is estimated to be found in only 10% of domestic suppliers, whereas system integration, and product-development capabilities are around 14%.

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