Новини світу мікро- та наноелектроніки

During a visit to Newport Wafer Fab in South Wales — the UK’s largest semiconductor facility — a day after giving her Spring Statement (promising a “new era of security and national renewal” to kickstart economic growth, protect working people and keep Britain safe), the UK Government’s Chancellor of the Exchequer Rachel Reeves has welcomed the intention of discrete semiconductor and passive electronic component maker Vishay Intertechnology Inc of Malvern, PA, USA to invest £250m in boosting production at its subsidiary Vishay Newport Ltd as part of plans to develop large-scale compound semiconductor manufacturing in the UK, specifically of silicon carbide devices...

In this look at transmission line theory, we will assume an RG-58 type of coaxial cable which has a characteristic impedance of 50 Ω. Where we let C stand for the capacitance per unit length, 30 pF per foot in this case, the characteristic impedance Zo = sqrt(L/C) where L is the inductance per unit length. This gives L = Zo²×C = 75 nH per foot.

We make a very simplistic MultiSim SPICE model of the transmission line being driven by a 50-Ω source impedance of the left in the Figure 1 with a load resistance whose value we are going to set to several different values, to 10,000 Ω, to 50 Ω, and then to 5 Ω while we examine the effects of each as a study of time domain reflectometry (TDR).

Figure 1 TDR result from a MultiSim SPICE model of a transmission line driven by a 50-Ω source impedance (R1) and where load resistance, R2, is set 10,000 Ω.

In Figure 1, using a square wave signal source, we see the signal takes 16.5 ns to make its way down the transmission line to arrive at R2. During that time, the signal input end at V1 and R1 presents an input impedance of 50 Ω, the cable’s characteristic impedance Zo.

Since the R2 value does not match Zo, energy transfer into R2 is incomplete and some of the arriving energy gets reflected back toward the left again. When that reflection reaches R1 in another 16.5 ns—a total transit time of 33 ns—the impedance presented to the V1 and R1 pair jumps up and we see the input voltage at the left end of the transmission line jump up too.

The propagation velocity and the velocity factor of the transmission line are calculable from the transit times are nearly two-thirds the speed of light in free space, just as in the published data for this cable.

In Figure 2, when we have R2 at 50 Ω, there is a match to Zo and no energy gets reflected back again. When we have R2 at only 5 Ω, we have a mismatch to Zo again and a reflection back toward the left, but the impedance at the left end drops instead of rising.

Figure 2 TDR Results for load R2 = 50 Ω, showing a match with no energy reflected back, and for R2 = 5 Ω showing a mismatch and energy reflected back.

Of course, this SPICE model is very crude in that each LC pair represents one foot of cable length. A more finely grained model with many more LC pairs per unit length would yield better waveform results than we’ve shown here.

For the sake of illustrating these principles though, I beg your forgiveness.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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• Measure propagation delays using time-domain reflectometry

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After an internal and external search by its board of directors, Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has appointed Robert Feurle as CEO, effective 1 May. He succeeds Thomas Werner, who is serving as interim executive chairman and will return as chairman of the board following the transition...

Compound Semiconductor Applications (CSA) Catapult is part of a consortium that is one of the winners of the Quantum Missions pilot competition, securing a share of £12m of funding from government agency Innovate UK. The collaboration brings together Vector Photonics Ltd (spun off from Scotland’s University of Glasgow in 2020), Sheffield University spin-off Phlux Technology —which designs and manufactures 1550nm avalanche photodiode (APD) infrared sensors — and the University of Bristol, alongside the Catapult’s expertise...

Superjunction Device Enables High Power Ratings and Density While Lowering Conduction and Switching Losses to Increase Efficiency

Vishay Intertechnology, Inc. introduced a new Gen 4.5 650 V E Series power MOSFET that delivers high efficiency and power density for telecom, industrial, and computing applications. Compared to previous-generation devices, the Vishay Siliconix n-channel slashes on-resistance by 48.2 % while offering a 65.4 % lower resistance times gate charge, a key figure of merit (FOM) for 650 V MOSFETs used in power conversion applications.

Vishay offers a broad line of MOSFET technologies that support all stages of the power conversion process, from high voltage inputs to the low voltage outputs required to power the latest high tech equipment. With the SiHK050N65E and other devices in the Gen 4.5 650 V E Series family, the company is addressing the need for efficiency and power density improvements in two of the first stages of the power system architecture — power factor correction (PFC) and subsequent DC/DC converter blocks. Typical applications will include servers, edge computing, and super computers; UPS; high intensity discharge (HID) lamps and fluorescent ballast lighting; telecom SMPS; solar inverters; welding equipment; induction heating; motor drives; and battery chargers.Built on Vishay’s latest energy-efficient E Series superjunction technology, the SiHK050N65E’s low typical on-resistance of 0.048 Ω at 10 V results in a higher power rating for applications > 6 kW. With 50 V of additional breakdown voltage, the 650 V device addresses 200 VAC to 277 VAC input voltages and the Open Compute Project’s Open Rack V3 (ORV3) standards. In addition, the MOSFET offers ultra low gate charge down to 78 nC. The resulting FOM of 3.74 Ω*nC translates into reduced conduction and switching losses to save energy and increase efficiency. This allows the device to address the specific titanium efficiency requirements in server power supplies or reach 96 % peak efficiency.

The post Vishay Intertechnology Gen 4.5 650 V E Series Power MOSFET Delivers Industry’s Lowest RDS(ON)*Qg and RDS(ON)*Co(er) FOMs appeared first on ELE Times.

New hardware integrates closely with convenient, graphical development environment

Developing context-aware applications with MEMS sensors is faster, more powerful, and more flexible with ST’s latest-generation sensor evaluation board, the STEVAL-MKI109D. Now upgraded with an STM32H5 microcontroller, USB-C connector, and extra digital interfaces including I3C for flexible communication, the new board lets users quickly evaluate sensors and confidently handle demanding projects.

Engineers unveiled the STEVAL-MKI109D during a live tech lab, showing how to simply plug in a sensor module, connect a PC, and start analyzing data in ST MEMS Studio. Using this all-in-one graphical environment, developers can visualize the sensor output, quickly fine-tune settings, configure features, and exercise the AI capabilities of ST sensors with a machine-learning core (MLC) and intelligent sensor processing unit (ISPU) inside. The tool provides advanced functions including power monitoring and supply voltage management that help optimize energy consumption and debugging.

ST’s MEMS portfolio contains inertial sensors, pressure sensors, biosensors, and digital and analog microphones offering many choices of speed, accuracy, full-scale range, and package style in industrial, consumer, and automotive grades. Extremely compact and robust, they are suited to diverse applications including consumer products, smartphones, wearables, smart-home devices, industrial sensing, safety equipment, healthcare, environmental monitoring, and many more. Automotive-grade devices target applications including navigation support, advanced driver assistance, and automated driving.

An evaluation module is available for each sensor type, mounted on a convenient DIL24 card with headers, ready to connect to the STEVAL-MKI109D board. Additional plug-and-play accessories are available, including biosensor electrodes and remote-sensing extension cables to quickly evaluate sensors when building proof-of-concept models and developing prototypes.

The STM32H5 MCU at the heart of the new board has the latest high-performing and efficient Arm Cortex-M33 core with extensive peripherals that enable faster, more convenient development. Customers’ sensor projects can target any of the over 1400 microcontrollers and microprocessors in the STM32 family. The MLC, finite-state machine (FSM), and ISPU embedded in select MEMS devices help optimize application performance and power consumption for superior functionality, responsiveness, and battery runtime.

The STEVAL-MKI109D board is available from distributors and the eSTore, from $105. ST MEMS Studio is ready to download now at www.st.com/mems-studio and is supported with automatic upgrades to ensure users always have the latest software and firmware.

For further information please visit: www.st.com/mems-studio

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The robust, low-power solutions from Microchip Technology meet stringent automotive standards for reliability in harsh conditions

Microchip Technology’s PolarFire System on Chip (SoC) FPGAs have earned the Automotive Electronics Council (AEC)-Q100 qualification. The AEC-Q standards are a guideline for integrated circuits, using stress tests to measure the reliability of electronic components in vehicles. AEC-Q100 qualified devices have gone through rigorous testing to demonstrate they can withstand extreme conditions in automotive applications.

The PolarFire SoC FPGA has been qualified for automotive Grade 1 temperatures, -40°C to 125°C. PolarFire SoC FPGAs feature an embedded 64-bit, quad-core RISC-V architecture capable of running Linux and real-time operating systems (RTOS), with mid-range density programmable logic of up to 500K logic elements (LE). The SoC FPGA is designed for complex applications that demand low-power, high-performance, exceptional reliability and an extended operating temperature range. Devices with the same density and package have scalable assurance and share pin-package compatibility across temperature grades, making it appropriate for automotive use as well as aerospace and military applications.

The SoC FPGAs incorporate embedded security and safety features to protect physical, device, design and data integrity. The SoCs are designed with single event upset (SEU) immunity, which enhances reliability and helps mitigate the risk of data corruption and system failures in demanding environments.

“Achieving the AEC-Q100 qualification for our PolarFire SoC FPGAs validates that our technology can perform under the most challenging conditions and underscores our commitment to delivering robust solutions to meet the stringent demands of the automotive industry,” said Bruce Weyer, Corporate Vice President of Microchip’s FPGA business unit. “Our low-power design and RISC-V cores empower automotive engineers to create advanced, reliable and energy-efficient solutions for next-generation automotive systems.”

PolarFire FPGAs and SoCs deliver power and thermal efficiency, eliminating the need for active cooling while ensuring high integration, defense-grade security and reliability. With high levels of scalability, they maintain performance across varying temperature conditions and meet stringent demands of mission-critical environments.

Development Tools

PolarFire SoCs are supported by Microchip’s Libero SoC Design Suite, SmartHLS, VectorBlox and Microchip’s Mi-V ecosystem of partner platforms for rapid RISC-V application development.  Additionally, a wide variety of Microchip and partner intellectual property (IP) cores are available to accelerate time-to-market. Libero SoC Design Suite is TÜV Rheinland-certified for functional safety, meeting ISO 26262 ASIL D standards for automotive applications. Compatible development boards are also available.

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The Evolving Ecosystem of Mobile Manufacturing in India

The Indian mobile manufacturing landscape represents a remarkable narrative of technological transformation, economic strategy, and industrial innovation. What was once a predominantly import-driven market has metamorphosed into a robust domestic production powerhouse, driven by a confluence of governmental initiatives, technological investments, and strategic corporate vision.

Xiaomi India: A Manufacturing Paradigm Shift

Xiaomi’s journey in India epitomizes the potential of localized manufacturing. Their production facilities in Chennai and Noida are not merely assembly lines but sophisticated technological ecosystems that represent the cutting edge of mobile manufacturing. The company has systematically invested in creating a comprehensive manufacturing infrastructure that goes beyond simple assembly.

The technological sophistication of Xiaomi’s manufacturing approach is evident in their deployment of advanced Surface Mount Technology (SMT) lines. These highly automated production systems enable precision component placement, ensuring consistent quality and minimizing human error. Robotic assembly processes have been integrated to enhance production efficiency, allowing for rapid scaling and maintaining stringent quality standards.

Moreover, Xiaomi’s local sourcing strategy has been instrumental in creating a robust domestic supply chain. By strategically partnering with local component manufacturers and investing in local ecosystem development, they have not just reduced production costs but also contributed to developing India’s electronics manufacturing capabilities.

Samsung: A Global Manufacturing Powerhouse in India

Samsung’s manufacturing complex in Noida represents more than just a production facility – it is a testament to advanced manufacturing capabilities. The facility stands as one of the world’s largest mobile phone factories, embodying cutting-edge technological integration and precision engineering.

The company’s approach transcends traditional manufacturing paradigms. Advanced Printed Circuit Board (PCB) manufacturing techniques, coupled with comprehensive quality assurance protocols, ensure that every device meets global standards. Their laboratories represent technological sanctuaries where each component undergoes rigorous testing, examining everything from thermal performance to electromagnetic compatibility.

Samsung’s integrated design and production workflows demonstrate a holistic approach to mobile manufacturing. By seamlessly connecting research, design, and production departments, they create an ecosystem that rapidly translates technological innovations into market-ready products.

Emerging Players: Realme and the New Manufacturing Paradigm

Realme represents the new generation of mobile manufacturers – agile, technology-driven, and deeply committed to localization. Their manufacturing facilities in Greater Noida are not just production centers but innovation laboratories that embrace modern manufacturing philosophies.

Lean manufacturing principles guide their production strategy, allowing for maximum efficiency and minimal waste. Modular production designs enable rapid prototyping and quick adaptation to market demands. This approach allows Realme to maintain a competitive edge in a rapidly evolving market, responding swiftly to technological trends and consumer preferences.

Oppo and Vivo: Synchronized Manufacturing Excellence

The sister companies Oppo and Vivo have developed a synchronized manufacturing ecosystem that exemplifies technological sophistication. Their facilities in Greater Noida and Noida are equipped with state-of-the-art automated optical inspection systems, ensuring that every device meets exacting quality standards.

Their manufacturing approach integrates advanced thermal and durability testing, recognizing that modern smartphones must withstand diverse environmental conditions. Comprehensive supply chain integration ensures that each component is not just sourced but meticulously validated.

Apple’s Strategic Manufacturing Presence

Though not an Indian company, Apple’s manufacturing strategy through Foxconn and Wistron represents a significant milestone in India’s mobile manufacturing journey. The facilities in Chennai and Bengaluru showcase precision engineering workflows that align with global high-end smartphone production standards.

Technological Horizons and Future Trajectories

The Indian mobile manufacturing ecosystem is poised at an exciting technological frontier. Emerging trends point towards deeper 5G component localization, advanced semiconductor integration, and AI-driven manufacturing optimization. Sustainability is becoming a critical consideration, with manufacturers exploring eco-friendly production technologies.

Government’s Transformative Role

The Production Linked Incentive (PLI) scheme has been the catalyst that transformed potential into reality. By creating a supportive policy environment, the government has not just attracted investments but fundamentally reshaped India’s technological manufacturing landscape.

Conclusion: A Global Manufacturing Destination

India’s mobile manufacturing journey is a narrative of technological ambition, strategic vision, and relentless innovation. From being a consumer market to emerging as a global manufacturing hub, the transformation is profound and promising.

The road ahead is illuminated by continuous technological advancement, strategic investments, and an unwavering commitment to excellence.

The post From Assembly to Innovation: India’s Transformative Mobile Manufacturing Revolution appeared first on ELE Times.

Spectrik of Eindhoven, The Netherlands is taking further steps in developing photonic gas sensors for agricultural applications by partnering with Eindhoven-based VTEC Lasers and Sensors B.V...

As part of its ongoing initiatives to optimize its manufacturing footprint, materials, networking and laser technology firm Coherent Corp of Saxonburg, PA, USA is to sell its epitaxial fabrication facility in Champaign, Illinois...

Materials, networking and laser technology firm Coherent Corp of Saxonburg, PA, USA has launched its 2x400G-FR4 Lite optical transceiver, a silicon photonics-based module optimized for AI-driven data centers and high-speed Ethernet networks. Designed for high volume deployments, the transceiver delivers 500m reach while significantly reducing power consumption. It complements the firm’s existing 800G-DR8 transceiver (also built with silicon photonics technology) with a wavelength-multiplexed variant that is more fiber-efficient than the DR8...

Materials, networking and laser technology firm Coherent Corp of Saxonburg, PA, USA has launched its 793nm pump laser diode, setting what is said to be a new industry standard with 28W of power and 97% polarization purity. The product offers what is claimed to be unmatched performance and cost efficiency, unlocking new possibilities for applications in the rapidly growing thulium fiber laser market...

Bridgelux Inc of Fremont, CA, USA (a vertically integrated developer and manufacturer of solid-state light sources for lighting applications) has expanded its chip-on-board (COB) product line by launching two inaugural DriveLux series of light engine products. By seamlessly integrating COB technology with an advanced driver, DriveLux is compact, with a replaceable design, what is claimed to be exceptional CRI90 efficacy, and versatile mounting options for large, selectable optical lenses in various sizes and beam angles...

Multi-national industrial and energy company METLEN Energy & Metals S.A. of Athens, Greece — which operates the only vertically integrated bauxite, alumina and primary aluminium production unit in the European Union (EU) with privately owned port facilities — says that its flagship investment in gallium production at the historic Aluminium of Greece industrial unit has been officially recognized as a Strategic Project by the European Commission under the Critical Raw Materials Act (CRMA)...

submitted by /u/DifficultyWhich7483 [link] [comments]

PCIe, the most successful interconnect technology for more than 25 years, is entering a new phase of complexity with the adoption of PCIe 6.0, which is now largely driving artificial intelligence (AI) workloads. Gary Hilson talks to senior managers at Broadcom and Astera Labs to understand issues related to PCIe 6.0 system design, interoperability and performance testing. These issues are critical in PCIe 6.0 deployment in advanced AI data centers.

Read the full story at EDN’s sister publication, EE Times.

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• PCIe 7.0 To Double Data Rate – Again
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• Advanced workloads drive PCIe 6.0 adoption
• AI Data Centers Need Huge Power-Backup Systems
• Solving PCIe Latency with Retimers and Elastic Buffers

The post A closer look at PCIe 6.0 interoperability, performance testing appeared first on EDN.

Skorpios Technologies Inc of Albuquerque, NM, USA (which provides integrated silicon photonics products and silicon nanostructures based on its proprietary Tru-SiPh wafer-scale heterogeneous integration platform) has appointed Gunter Reiss as chief revenue officer to accelerate global expansion across AI infrastructure, hyperscalers, optical networking, quantum computing, LiDAR, aerospace, and advanced foundry services...

LM317 fans will recognize Figure 1 as the traditional LM317 constant current source topology. It closely regulates Iout = Vadj/Rs by forcing the OUTPUT pin to be Vadj = 1.25 V positive relative to the ADJ pin. Thus, Iout = Vadj/Rs to a very good approximation. Master chip chef Bob Pease cooked it up to be so!

Figure 1 Classic LM317 constant current source,
Iout = Vadj/Rs + Iadj ≃ Vadj/Rs = 1.25/Rs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In usual practice, Iout >> Iadj, the latter being specified at 50 µA typical, 100 µA max. This simplifies the math by making the Iadj bias current safely ignorable without letting accuracy take a hit. It’s worked great for 50 years but it has an obvious downside. the way you program Iout is by changing Rs.

Figure 2 shows a new(er) topology with a different (more agile) method for making Iout programmable.

Figure 2 A novel LM317 topology enables control of amps of Iout with just milliamps of Ic,
Iout = (Vadj – (Ic – Iadj)Rc)/Rs – Ic + Iadj ≃ (Vadj – (Ic – Iadj)Rc)/Rs. 

Typically, Rc > 100Rs, making Figure 2 able to control up to 1.5 A of Iout with just milliamps of Ic. Of course, now it may no longer be good enough to just ignore Iadj. 

Figure 3 shows the idea fleshed out into a complete PWM controlled 15 V, 1 A, grounded-load current source that includes Iadj compensation. Here’s how it works.

Figure 3 The 1-A, 15-V, PWM-programmed grounded-load current source with a novel LM317 topology. The asterisked resistors are 1% or better and Rs = 1.25 Ω.

The 5-Vpp PWM input has a frequency (Fpwm) assumed to be 10 kHz or thereabouts. If it doesn’t, scale C1 appropriately with:

C1 = 22µF*10kHz/Fpwm

The resulting PWM switching of Q2 creates a variable resistance averaged by C1 to Rc(1 + 1/Df) where Df = the 0 to 1 PWM duty factor.  Thus a (0 to 2.5v)/2Rc = 3.11 mA Ic current = 2.5v/Rc(1 + 1/Df) flows into Z1’s summing point.

Z1 servos the V1 gate drive of Q1 to hold its source at an accurate 2.5-V reference for the PWM conversion and to level shift Ic to track U1’s ADJ pin. Also summed with Ic is Iadj bias compensation (2.5v/51k = 50µA) provided by R1.

The unsightly stack of six 1N4001’s is needed to provide bias for Q1 to work into. I freely admit that it’s not very pretty. Hopefully the novelty of Figure 2 makes up for it! 

Note that accuracy and linearity mostly depend only on the match of the Rc resistors and the precision of the Z1 and U1 internal references. It’s a happy coincidence that the 2:1 ratio of the TL431’s 2.5-V versus the LM317’s 1.25 V permits the convenient use of three identical Rc resistors.

If Rs = 1.25 Ω, then Iout(max) = 1 A and Iout versus Df is as plotted in Figure 4.

Figure 4 Iout versus Df where Df (x-axis) is the PWM duty factor and Iout (y-axis) is Vadj/1.25 = 1 A full-scale = 1 – 2/(1 + 1/Df).

 Df versus Iout is plotted in Figure 5.

Figure 5 Df versus Iout where Iout (x-axis) is 1 A full-scale and Df (y-axis) = 1/(2/(1 – Iout) – 1).

Note that U1 might be called upon to dissipate as much as:

• 20 W if Rs = 1.25 Ω and Iout(max) = 1 A
• 30 W if Rs = 0.83 Ω and Iout(max) = 1.5A

Moral of the story: don’t be skimpy on the heatsink! Also note that Rs should be rated for a wattage of at least 1.252/Rs.

Then there’s the consideration of power up/down transients. When the system is first switched on and C1 is sitting discharged, and the controller will have about 4 to 8 milliseconds to initialize the PWM logic to 1.0 before C1 can charge enough to allow U1 to come on and start sourcing current. Don’t forget this detail during software development! On power-down, Q3 kicks in when +5 V drops below ~2 V. This saturates Q1 and forces Iout to zero to protect the load as well as discharging C1 in preparation for the next power-up.

In closing, thanks go (again) to savvy reader Ashutosh for his suggestion that the Figure 2 topology might deserve a focused DI of its own, and (likewise again) to editor Aalyia for the fertile DI environment she has created that makes this kind of teamwork, well, workable!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• 1 A, 20 V PWM DAC current source with tracking preregulator
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• LM317 smooths but doesn’t regulate
• PWM power DAC incorporates an LM317
• Power Zener using the LM317
• Use an LM317 as 0 to 3V adjustable regulator

The post PWM-programmed LM317 constant current source appeared first on EDN.

Firmware is open source though. A small (52x30) PCB to forward USB HID reports over BLE. Plus additional buttons and a rotary encoder. submitted by /u/No_Pilot_1974 [link] [comments]

submitted by /u/1Davide [link] [comments]