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Automotive chips improve ADAS reliability
TI has expanded its automotive portfolio with a high-speed lidar laser driver, BAW-based clocks, and a mmWave radar sensor. These devices support the development of adaptable ADAS for safer, more automated driving.
The LMH13000 is claimed to be the first laser driver with an ultra-fast 800-ps rise time, enabling up to 30% longer distance measurements than discrete implementations and enhancing real-time decision making. It integrates LVDS, CMOS, and TTL control signals, eliminating the need for large capacitors or additional external circuitry. The device delivers up to 5 A of adjustable output current with just 2% variation across an ambient temperature range of -40°C to +125°C.
By leveraging bulk acoustic wave (BAW) technology, the CDC6C-Q1 oscillator and the LMK3H0102-Q1 and LMK3C0105-Q1 clock generators provide 100× greater reliability than quartz-based clocks, with a failure-in-time (FIT) rate as low as 0.3. These devices improve clocking precision in next-generation vehicle subsystems.
TI’s AWR2944P front and corner radar sensor builds on the AWR2944 platform, offering a higher signal-to-noise ratio, enhanced compute performance, expanded memory, and an integrated radar hardware accelerator. The accelerator enables the system’s MCU and DSP to perform machine learning tasks for edge AI applications.
Preproduction quantities of the LMH13000, CDC6C-Q1, LMK3H0102-Q1, LMK3C0105-Q1, and AWR2944P are available now on TI.com. Additional output current options and an automotive-qualified version of the LMH13000 are expected in 2026.
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PMIC fine-tunes power for MPUs and FPGAs
Designed for high-end MPU and FPGA systems, the Microchip MCP16701 PMIC integrates eight 1.5-A buck converters that can be paralleled and are duty cycle-capable. It also includes four 300-mA LDO regulators and a controller to drive external MOSFETs.
The MCP16701 enables dynamic VOUT adjustment across all converters, from 0.6 V to 1.6 V in 12.5-mV steps and from 1.6 V to 3.8 V in 25-mV steps. This flexibility allows precise power tuning for specific requirements in industrial computing, data servers, and edge AI, enhancing overall system efficiency.
Housed in a compact 8×8-mm VQFN package, the PMIC reduces board area by 48% and lowers component count to less than 60% compared to discrete designs. It supports Microchip’s PIC64-GX MPU and PolarFire FPGAs with a configurable feature set and operates from -40°C to +105°C. An I2C interface facilitates communication with other system components.
The MCP16701 costs $3 each in lots of 10,000 units.
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PXI testbench strengthens chip security testing
The DS1050A Embedded Security Testbench from Keysight is a scalable PXI-based platform for advanced side-channel analysis (SCA) and fault injection (FI) testing. Designed for modern chips and embedded devices, it builds on the Device Vulnerability Analysis product line, offering up to 10× higher test effectiveness to help identify and mitigate hardware-level security threats.
This modular platform combines three core components—the M9046A PXIe chassis, M9038A PXIe embedded controller, and Inspector software. It integrates key tools, including oscilloscopes, interface equipment, amplifiers, and trigger generators, into a single chassis, reducing cabling and improving inter-module communication speed.
The 18-slot M9046A PXIe chassis delivers up to 1675 W of power and supports 85 W of cooling per slot, accommodating both Keysight and third-party test modules. Powered by an Intel Core i7-9850HE processor, the M9038A embedded controller provides the computing performance required for complex tests. Inspector software simulates diverse fault conditions, supports data acquisition, and enables advanced cryptanalysis across embedded devices, chips, and smart cards.
For more information on the DS1050A Embedded Security Testbench, or to request a price quote, click the product page link below.
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Sensor brings cinematic HDR video to smartphones
Omnivision’s OV50X CMOS image sensor delivers movie-grade video capture with ultra-high dynamic range (HDR) for premium smartphones. Based on the company’s TheiaCel and dual conversion gain (DCG) technologies, the color sensor achieves single-exposure HDR approaching 110 dB—reportedly the highest available in smartphones.
The OV50X is a 50-Mpixel sensor with a 1.6-µm pixel pitch and an 8192×6144 active array in a 1-in. optical format. It supports 4-cell binning, providing 12.5-Mpixel output at up to 180 frames/s, or 60 frames/s with three-exposure HDR. The sensor also enables 8K video with dual analog gain HDR and on-sensor crop-zoom capability.
TheiaCel employs lateral overflow integration capacitor (LOFIC) technology in combination with Omnivision’s proprietary DCG HDR to capture high-quality images and video in difficult lighting conditions. Quad phase detection (QPD) with 100% sensor coverage enables fast, precise autofocus across the entire frame—even in low light.
The OV50X image sensor is currently sampling, with mass production slated for Q3 2025.
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GaN transistors integrate Schottky diode
Medium-voltage CoolGaN G5 transistors from Infineon include a built-in Schottky diode to minimize dead-time losses and enhance system efficiency. The integrated diode also streamlines power stage design and helps reduce BOM cost.
In hard-switching designs, GaN devices can suffer from higher power losses due to body diode behavior, especially with long controller dead times. CoolGaN G5 transistors address this by integrating a Schottky diode, improving efficiency across applications such as telecom IBCs, DC/DC converters, USB-C chargers, power supplies, and motor drives.
GaN transistor reverse conduction voltage (VRC) depends on the threshold voltage (VTH) and OFF-state gate bias (VGS), as there is no body diode. Since VTH is typically higher than the turn-on voltage of silicon diodes, reverse conduction losses increase in third-quadrant operation. The CoolGaN transistor reduces these losses, improves compatibility with high-side gate drivers, and allows broader controller compatibility due to relaxed dead-time.
The first device in the CoolGaN G5 series with an integrated Schottky diode is a 100-V, 1.5-mΩ transistor in a 3×5-mm PQFN package. Engineering samples and a target datasheet are available upon request.
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Shoot-through
This phenomenon has nothing to do with “Gunsmoke” or with “Have Gun, Will Travel”. (Do you remember those old TV shows?) The phrase “shoot- through” describes unwanted and possibly destructive pulses of current flowing through power semiconductors in certain power supply designs.
In half-bridge and full-bridge power inverters, we have one pair (half-bridge) or two pairs (full-bridge) of power switching devices connected in series from a rail voltage to a rail voltage return. Those devices could be power MOSFETs, IGBTs, or whatever but the requirement in each case is the same. That requirement is that the two devices in each pair turn on and off in alternate fashion. If the upper one is on, the lower one is off. If the upper one is off, the lower one is on.
The circuit board seen in Figure 1 was one such design based on a full-bridge power inverter, and it had a shoot- through issue.
Figure 1 A full-bridge circuit board with a shoot-through issue and the test arrangement used to assess it.
A super simplified SPICE simulation shows conceptually what was going amiss with that circuit board, Figure 2.
Figure 2 A SPICE simulation that conceptually walks through the shoot-through problem occurring on the circuit in Figure 1.
S1 represents the board’s Q1 and Q2 upper switches and S2 represents the board’s Q4 and Q3 lower switches. At each switching transition, there was a brief moment when one switch had not quite turned off by the time its corresponding switch had turned on. With both switching devices on at the same time, however brief that “same” time was, there would be a pulse of current flowing from the board’s rail through the two switches an into the board’s rail return. That current pulse would be of essentially unlimited magnitude and the two switching devices could and would suffer damage.
Electromagnetic interference issues arose as well, but that’s a separate discussion.
Old hands will undoubtedly recognize the following, but let’s take a look at the remedy shown in Figure 3.
Figure 3 Shoot-through problem solved by introducing two diodes to speed up the switchs’ turn-off times.
The capacitors C1 and C2 represent the input gate capacitances of the power MOSFETs that served as the switches. The shoot-through issue would arise when one of those capacitances was not fully discharged before the other capacitance got raised to its own full charge. Adding two diodes sped up the capacitance discharge times so that essentially full discharge was achieved for each FET before the other one could turn on.
Having thus prevented simultaneous turn-ons, the troublesome current pulses on that circuit board were eliminated.
John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).
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Addressing hardware failures and silent data corruption in AI chips
Meta trained one of its AI models, called Llama 3, in 2024 and published the results in a widely covered paper. During a 54-day period of pre-training, Llama 3 experienced 466 job interruptions, 419 of which were unexpected. Upon further investigation, Meta learned 78% of those hiccups were caused by hardware issues such as GPU and host component failures.
Hardware issues like these don’t just cause job interruptions. They can also lead to silent data corruption (SDC), causing unwanted data loss or inaccuracies that often go undetected for extended periods.
While Meta’s pre-training interruptions were unexpected, they shouldn’t be entirely surprising. AI models like Llama 3 have massive processing demands that require colossal computing clusters. For training alone, AI workloads can require hundreds of thousands of nodes and associated GPUs working in unison for weeks or months at a time.
The intensity and scale of AI processing and switching create a tremendous amount of heat, voltage fluctuations and noise, all of which place unprecedented stress on computational hardware. The GPUs and underlying silicon can degrade more rapidly than they would under normal (or what used to be normal) conditions. Performance and reliability wane accordingly.
This is especially true for sub-5 nm process technologies, where silicon degradation and faulty behavior are observed upon manufacturing and in the field.
But what can be done about it? How can unanticipated interruptions and SDC be mitigated? And how can chip design teams ensure optimal performance and reliability as the industry pushes forward with newer, bigger AI workloads that demand even more processing capacity and scale?
Ensuring silicon reliability, availability and serviceability (RAS)
Certain AI players like Meta have established monitoring and diagnostics capabilities to improve the availability and reliability of their computing environments. But with processing demands, hardware failures and SDC issues on the rise, there is a distinct need for test and telemetry capabilities at deeper levels—all the way down to the silicon and multi-die packages within each XPU/GPU as well as the interconnects that bring them together.
The key is silicon lifecycle management (SLM) solutions that help ensure end-to-end RAS, from design and manufacturing to bring-up and in-field operation.
With better visibility, monitoring, and diagnostics at the silicon level, design teams can:
- Gain telemetry-based insights into why chips are failing or why SDC is occurring.
- Identify voltage or timing degradation, overheating, and mechanical failures in silicon components, multi-die packages, and high-speed interconnects.
- Conduct more precise thermal and power characterization for AI workloads.
- Detect, characterize, and resolve radiation, voltage noise, and mechanism failures that can lead to undetected bit flips and SDC.
- Improve silicon yield, quality, and in-field RAS.
- Implement reliability-focused techniques—like triple modular redundancy and dual core lock step—during the register-transfer level (RTL) design phase to mitigate SDC.
- Establish an accurate pre-silicon aging simulation methodology to detect sensitive or vulnerable circuits and replace them with aging-resilient circuits.
- Improve outlier detection on reliability models, which helps minimize in-field SDC.
Silicon lifecycle management (SLM) solutions help ensure end-to-end reliability, availability, and serviceability. Source: Synopsys
An SML design example
SLM IP and analytics solutions help improve silicon health and provide operational metrics at each phase of the system lifecycle. This includes environmental monitoring for understanding and optimizing silicon performance based on the operating environment of the device; structural monitoring to identify performance variations from design to in-field operation; and functional monitoring to track the health and anomalies of critical device functions.
Below are the key features and capabilities that SLM IP provides:
- Process, voltage and temperature monitors
- Help ensure optimal operation while maximizing performance, power, and reliability.
- Highly accurate and distributed monitoring throughout the die, enabling thermal management via frequency throttling.
- Path margin monitors
- Measure timing margin of 1000+ synthetic and functional paths (in-test and in-field).
- Enable silicon performance optimization based on actual margins.
- Automated path selection, IP insertion, and scan generation.
- Clock and delay monitors
- Measure the delay between the edges of one or more signals.
- Check the quality of the clock duty cycle.
- Measure memory read access time tracking with built-in self-test (BIST).
- Characterize digital delay lines.
- UCIe monitor, test and repair
- Monitor signal integrity of die-to-die UCIe lane(s).
- Generate algorithmic BIST patterns to detect interconnect fault types, including lane-to-lane crosstalk.
- Perform cumulative lane repair with redundancy allocation (upon manufacturing and in-field).
- High-speed access and test
- Enable testing over functional interfaces (PCIe, USB and SPI).
- For in-field operation as well as wafer sort, final test, and system-level test.
- Can be used in conjunction with automated test equipment.
- Help conduct in-field remote diagnoses and lower-cost test via reduced pin count.
- HBM external test and repair
- Comprehensive, silicon-proven DRAM stack test, repair and diagnostics engine.
- Support third-party HBM DRAM stack providers.
- Provide high-performance die to die interconnect test and repair support.
- Operate in conjunction with HBM PHY and support a range of HBM protocols and configurations.
- SLM hierarchical subsystem
- Automated hierarchical SLM and test manageability solution for system-on-chips (SoCs).
- Automated integration and access of all IP/cores with in-system scheduling.
- Pre-validated, ready ATE patterns with pattern porting.
Silicon test and telemetry in the age of AI
With the scale and processing demands of AI devices and workloads on the rise, system reliability, silicon health and SDC issues are becoming more widespread. While there is no single solution or antidote for avoiding these issues, deeper and more comprehensive test, repair, and telemetry—at the silicon level—can help mitigate them. The ability to detect or predict in-field chip degradation is particularly valuable, enabling corrective action before sudden or catastrophic system failures occur.
Delivering end-to-end visibility through RAS, silicon test, repair, and telemetry will be increasingly important as we move toward the age of AI.
Shankar Krishnamoorthy is chief product development officer at Synopsys.
Krishna Adusumalli is R&D engineer at Synopsys.
Jyotika Athavale is architecture engineering director at Synopsys.
Yervant Zorian is chief architect at Synopsys.
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The post Addressing hardware failures and silent data corruption in AI chips appeared first on EDN.
Vishay Intertechnology 600 V Standard and 60 V to 200 V TMBS Rectifiers Deliver High Current Ratings to 9 A in DFN33A Package
Featuring Low 0.88 mm Profile and Wettable Flanks, Space-Saving Devices Provide Improved Thermal Performance and Efficiency
Vishay Intertechnology, Inc. introduced 27 standard and Trench MOS Barrier Schottky (TMBS) surface-mount rectifiers in the low profile DFN33A package with wettable flanks. Providing space-saving, high efficiency solutions for commercial, industrial, telecom, and automotive applications, the standard devices are the industry’s first in this package size and provide current ratings up to 6 A, while the TMBS devices deliver industry-best current ratings up to 9 A. Offering a wide range of voltage options from 60 V to 200 V for TMBS and up to 600 V for standard rectifiers, the devices are available in Automotive Grade, AEC-Q101 qualified versions.
The latest package in Vishay’s Power DFN family, the DFN33A features a compact 3.3 mm by 3.3 mm footprint and an extremely low typical height of 0.88 mm, allowing the Vishay General Semiconductor rectifiers released today to make more efficient use of PCB space. Compared to the conventional SMB (DO-214AA) and eSMP series SMPA (DO-220AA), the package’s size is 44 % and 20 % smaller, respectively. In addition, the device’s low profile is 2.6x thinner than the SMB (DO-214AA) and SMC, and 7 % thinner than the SMPA (DO-220AA). At the same time, the rectifiers’ optimized copper mass design and advanced die placement technology allow for superior thermal performance that enables operation at higher current ratings.
The devices are intended for low voltage, high frequency inverters, DC/DC converters, freewheeling diodes, and polarity and rail to rail protection in hot swap circuits for baseband antennas and power over Ethernet (PoE) for switches, routers, and optical network equipment. For these applications, the rectifiers offer high temperature operation up to +175 °C, while their exceptionally low forward voltage drop and low leakage current enhance design efficiency. The wettable flanks of their DFN33A package allow for automatic optical inspection, eliminating the need for an X-ray inspection.
Ideal for automated placement, the rectifiers offer an MSL moisture sensitivity level of 1, per J-STD-020, LF maximum peak of 260 °C. The devices are RoHS-compliant and halogen-free, and their matte tin-plated leads meet the JESD 201 class 2 whisker test.
The post Vishay Intertechnology 600 V Standard and 60 V to 200 V TMBS Rectifiers Deliver High Current Ratings to 9 A in DFN33A Package appeared first on ELE Times.
I think my cap is bad.
 | submitted by /u/knw_a-z_0-9_a-z [link] [comments] |
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3D printed digital night vision
 | This was a project that I worked on a couple months ago that was really fun and cool, I followed it on YouTube if you look up adhd engineer. (Black was the first version) [link] [comments] |
FINALLY! I made this 555 Timer using a Nor IC and an Op-Amp(used as comparators)
 | submitted by /u/White_Septendecim [link] [comments] |
Photo tachometer sensor accommodates ambient light
Tachometry, the measurement of the speed of spin of rotating objects, is a common application. Some of those objects, however, have quirky aspects that make them extra interesting, even scary. One such category includes outdoor noncontact sensing of large, fast, and potentially hazardous objects like windmills, waterwheels, and aircraft propellers. The tachometer peripheral illustrated in Figure 1 implements optical sensing using available ambient light that provides a logic-level signal to a microcontroller digital input and is easily adaptable to different light levels and mechanical contexts.
Figure 1 Logarithmic contrast detection accommodates several decades of variability in available illumination.
Wow the engineering world with your unique design: Design Ideas Submission Guide
Safe sensing of large rotating objects is best done from a safe (large) distance and passive available-light optical methods are the obvious solution. Unless elaborate lens systems are used in front of the detector, the optical signal is apt to have a relatively low-amplitude due to the tendency of the rotating object (propeller blade, etc.) to fill only a small fraction of the field of view of simple detectors. This tachometer (Figure 1) makes do with an uncomplicated detector (phototransistor Q1 with a simple light shield) by following the detector with a high-gain, AC coupled, logarithmic, threshold detector.
Q1’s photocurrent produces a signal across Q2 and Q3 that varies by ~500 µV pp for every 1% change in incident light intensity that’s roughly (e.g. neglecting various tempcos) given by:
V ~ 0.12 log10(Iq1/Io)
Io ~ 10 fA
This approximate log relationship works over a range of nanoamps to milliamps of photocurrent and is therefore able to provide reliable circuit operation despite several orders of magnitude variation in available light intensity. A1 and the surrounding discrete components comprise high gain (80 dB) amplification that presents a 5-Vpp square-wave to the attached microcontroller DIO pin.
Programming of the I/O pin internal logic for pulse counting allows a simple software routine to divide the accumulated count by the associated time interval and by the number of counted optical features of the rotating object (e.g., number of blades on the propeller) to produce an accurate RPM reading.
Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.
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