Новини світу мікро- та наноелектроніки

Tokyo-based automated semiconductor test & measurement equipment maker Advantest Corp has unveiled the Wave Scale RF20ex instrument for the V93000 EXA Scale platform, enabling customers to test virtually any type of radio frequency (RF) device using a single instrument...

As we near the end of the year, two CEOs at prominent semiconductor firms are leaving, and in both cases, the chairmen of the board are replacing them as interim CEOs. What’s common in both companies is the quest for a turnaround in the rapidly evolving semiconductor market.

First, Ganesh Moorthy, president and CEO, is leaving Microchip, and chairman Steve Sanghi is taking back the charge of the top job at the Chandler, Arizona-based semiconductor firm. While the announcement states that Moorthy is retiring after his nearly three-year stint at the corner office, the fact that Sanghi is back at the helm immediately doesn’t exactly signal a smooth transition.

Figure 1 Before joining Microchip, Moorthy was CEO of Cybercilium, the company he co-founded in Tempe, Arizona.

Sanghi, who will remain chairman, is taking charge as interim president and CEO. Moorthy joined Microchip as VP of advanced microcontrollers and automotive division in 2001, and he was appointed chief operating officer before being elevated to the CEO job in 2021. He had served at Intel for 19 years before his stints at Cybercilium and Microchip.

Microchip has been confronting an inventory stock and sales slump for some time, and its shares are down 28% in 2024. Sanghi’s statement on taking the charge as CEO clearly points toward an aim to return to growth in revenue and profitability.

Then there is the news about Wolfspeed’s CEO change, and it’s more startling and less subtle. The Wolfspeed board has ousted CEO Gregg Lowe without cause, and like Microchip, chairman of the board Thomas Werner is taking over as interim CEO before Wolfspeed finds Lowe’s replacement.

Lowe, who spearheaded Freescale’s sale to NXP in 2015 as CEO, took the helm of Cree in 2017 and transformed it from an LED lighting company to a silicon carbide (SiC) IDM. During this transformation under Lowe, the company acquired a new name: Wolfspeed. Also, during this time, Infineon made a failed attempt to acquire Wolfspeed.

However, the Durham, North Carolina-based chipmaker seems to have failed to translate its enviable position as a pure-play SiC company in this high-growth market, and that probably sums up Lowe’s ouster. It’s apparent from Werner’s statement announcing this CEO transition. “Wolfspeed is materially undervalued relative to its strategic value, and I will focus on driving the company’s priorities to explore options to unlock value.”

Figure 2 Lowe sold off Cree’s LED lighting business and turned the sole focus on SiC under the Wolfspeed brand.

For a start, Wolfspeed has been struggling in the transition from 150-mm to 200-mm SiC wafers. It has also been facing slowing orders from the electric vehicle (EV), industrial and renewable energy markets. The company recently dropped plans to build a SiC fab in Ensdrof, Germany.

These two CEO office transitions don’t come as a surprise to the semiconductor industry watchers. And it surely won’t be the last as we are about to enter 2025. The semiconductor industry is highly competitive, and stakes are even higher when you are a vertically-integrated chip outfit.

Related Content

• Microchip, Micrel CEOs Duel Over Deal
• CEO interview: Microchip’s Steve Sanghi
• Wolfspeed Set to Invest $5 Billion in SiC Expansion
• Wolfspeed to Build 200-mm SiC Wafer Fab in Germany
• CEO Sanghi bets Microchip’s future on power, connectivity

The post The CEO office transitions at Microchip and Wolfspeed appeared first on EDN.

Specialty analog foundry Tower Semiconductor Ltd of Migdal Haemek, Israel has begun volume production of 1.6Tbps silicon photonic products for multiple lead customers based on its latest silicon photonics (SiPho) platform. The firm’s latest platform includes innovations that have helped to double data rates relative to its existing 800Gpbs high-volume products. These innovations have been developed in close collaboration with several tier-1 customers that have designed breakthrough 1.6Tbps products on this enhanced platform and have now begun to order production quantities...

Materials, networking and laser technology firm Coherent Corp of Saxonburg, PA, USA has announced the production release of high-speed indium phosphide (InP) photodiodes...

AlixLabs AB of Lund, Sweden — which was spun off from Lund University in 2019 and has developed the Atomic Layer Etching (ALE) Pitch Splitting technology (APS) — has been granted SEK4m (about €345,000) in funding from Swedish innovation agency Vinnova. The funding is spread out over three years, with SEK658,000 (~€56,000) credited immediately, with the remainder to follow over the coming three years. The funds will help AlixLabs to advance its APS technology to a higher Technology Readiness Level (TRL) and to strengthen customer engagement efforts...

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Scintil Photonics of Grenoble, France and Toronto, Canada, a fabless developer of augmented silicon photonic integrated circuits, has appointed Matt Crowley as chief executive officer and established a US subsidiary to support its expanding customer base in data centers, machine learning and artificial intelligence (AI)...

A recent design idea, “Negative time-constant and PWM program a versatile ADC front end,” offered a pretty peculiar ADC front end (see Figure 1). It comprises a programmable gain (PG) instrumentation amplifier (INA). It uses PWM control of a flying capacitor to implement a 110-dB CMRR, high impedance differential input and negative time-constant exponential amplification with more than 100 discrete programmable gain steps. It’s then topped off with a built-in sample and hold (S&H). Hence PGINASH. Catchy. Ahem.

Figure 1 PGINASH: An unconventional ADC front end with INA inputs, programmable gain, and sample and hold.

Wow the engineering world with your unique design: Design Ideas Submission Guide

 Due to A1c’s gain of (R3 / R2 + 1) = 2, during the PWM = 1 gain accumulation phase the connection established from U1c’s output through U2a and R1 to C creates positive feedback that makes the voltage captured on C multiply exponentially with a (negative) time-constant Tc of (nominally):

Tc = R1*(C + Cstray) =
= 14.3k*(0.001µF + (8pF (from U2a) + 1pF (from U1c)))
= 14.3k*1009pF = 14.43µs
= 10µs / ln(2)
G = gain increment of 20.1 = 1.0718 = 0.6021dB per us of accumulation time T
G10 = 2.0 = 6.021dB per 10µs of T
This combines with A1c’s fixed gain of two to total
Nominal net Gain = 2GT/10µs

Of course, the keyword here is “nominally.” Both R1 and C will have nonzero tolerances, perhaps as poor as ±1%, and ditto for R2 and R3. Moreover, further time-constant, and therefore gain, error can arise from U2 switch to switch ON resistance mismatches. The net bad news, pessimistically assuming worst case mutual error reinforcement of all the time-constant component tolerances, is A1c’s gain may vary by ±2% and G by as much as ±3%. This is far from adequate for precision data acquisition! What to do?

The following sequence is suggested as a simple software-based in-circuit calibration method using a connected ADC and requiring just two calibration voltages to be manually connected to the IA inputs as calibration progresses, to combat the various causes of front-end error. 

GAIN ERROR

The first calibration voltage (Vcal) is used to explicitly measure the as-built gain factors. Here’s how it works:

 Vcal = Vfs/Vheadroom
where
Vfs = ADC full-scale Vin
Vheadroom = (2*1.02)*(2*1.04)2 = 8.8
e.g., if Vfs = 5v, Vcal = 0.57v

 Vcal’s absolute accuracy isn’t particularly important, +/-1% is plenty adequate. But it should be stable to better than 1 lsb during the calibration process. Connect Vcal to the INA inputs, then take two ADC conversions: D1 with gain accumulation time T =10 µs and D2 with T = 20 µs. Thus, if 2x = the as-built A1c gain and G = the as-built exponential gain, the ADC will read:

D1 = ADC(2x *G10*Vcal)
D2 = ADC(2x*G10*G10*Vcal)

 Averaging a number (perhaps 16) acquisitions of each value is probably a good idea for best accuracy. The next step is some arithmetic:

D2/D1 = (2x*G10*G10*Vcal)/(2x*G10*Vcal) = G10
D1/ (G10*Vcal) = (2x*G10*Vcal)/(G10*Vcal) = 2x
G = (G10)0.1

That wasn’t so bad, was it? Now we if we want to set (most) any desired conversion gain of Y, we just need to compute a gain accumulation interval of:

T(µs) = log(Y/2x)/log(G)

Note if that this math yields T < 1 µs, we’ll need to bump Y for some extra time (and gain) to allow for capacitor “flight” and signal acquisition.

INPUT OFFSET ERROR

There is, however, another error source we haven’t covered: U1 input offsets. Although the TLV9164 typical offset is only 200 µV, max can range as high as 1.2 mV. If uncorrected, the three input amplifiers’ offsets could sum to 3.6 mV. This would render the upper gain range of our amplifier of little value. To fix it, we need another input voltage reference (Vzero), some more arithmetic, and another ADC conversion to measure the Voff offset and allow software subtraction. We’ll use lots of gain to get plenty of resolution. Vzero should ideally be accurate and stable to <10 µV to take full advantage of the 9164’s excellent 0.25 µV/oC drift spec’.

Let Vzero = 4.00mV
N = log(Vfs/(.008v * 2x))/log(G)
D3 =  ADC(2x*GN*(Vzero + Voff))
Voff = D3/(2x*GN) – Vzero

 And there you have it. To accurately massage any raw ADC result into the actual Vin input that produced it, write:

Vin = (ADC(Vin)/(2x GN)) – Voff

 But avoid GN  > Vfs /(2x*Voff). Otherwise A1c and the ADC may be driven into saturation by amplified offset. Also, things may (okay, will) get noisy.

Okay. But what about…

LEAKAGE CURRENT ERROR

The leakage current conundrum comes from the fact that negative time-constant current from U1c through R1 isn’t the only source of gain-phase charge for C. Unfortunately, leakage currents from U2’s X pin and U1’s noninverting input also contribute a mischievous share. U1’s contribution is a negligible 10 pA or so, but U2’s can be large enough to become problematic.

The burning question is: How much to HC4053 switches really leak? Reeeeeally?  Datasheets are of surprisingly little help, with the answer seeming to range over literally a million-to-one, pA to µA, range.

Figure 2 quantifies the result for some plausible 100 pA to 1 µA numbers.

Figure 2 The input referred current – equivalent voltage offsets.

 Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Negative time-constant and PWM program a versatile ADC front end
• Simulating the front-end of your ADC
• Parsing PWM (DAC) performance: Part 1—Mitigating errors
• PWM DAC settles in one period of the pulse train

The post In-situ software calibration of the flying capacitor PGINASH appeared first on EDN.

In a trading update, epiwafer and substrate maker IQE plc of Cardiff, Wales, UK says it expects revenue for full-year 2024 of about £115m, roughly flat with 2023’s £115.3m (rather than September’s forecast of year-on-year growth, to the lower end of analysts’ forecast of £130–153.7m). “In line with the rest of the industry, we are continuing to see a slower-than-anticipated recovery in key sectors driven by weak consumer demand in end markets,” the firm says. IQE expects this to result in an adjusted EBITDA of at least £5m (up from 2023’s £4.3m, albeit below analysts’ forecast in April of £11.1–16.6m)...

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — says that its board of directors has determined and agreed with Gregg Lowe that in November he will depart from his roles as president & CEO and as a member of the board. Hence, with the support of a global executive search firm, the board is seeking to identify a permanent CEO...

Employing network-on-chip (NoC) technology in system-on-chip (SoC) designs has been proven to reduce routing congestion and lower power consumption. Now, a new NoC-enabled tiling methodology helps speed development, facilitates scaling, participates in power reduction technology and contributes to increased design reuse for SoCs targeting artificial intelligence (AI) applications.

For these discussions, we will assume that AI encompasses use cases such as machine learning (ML) and inferencing.

Soft and hard tiles

One challenge in engineering is that the same term may be used to refer to different things. The term “tile,” for example, has multiple meanings. Some people equate tiles with chiplets, which are small, independent silicon dies, all presented on a common silicon or organic substrate or interposer. Chiplets may be thought of as “hard tiles.”

By comparison, many SoCs, including those intended for AI applications, employ arrays of processing elements (PEs), which can be considered “soft tiles.” For example, refer to the generic SoC depicted in Figure 1.

Figure 1 High-level block diagram shows SoC containing a neural processing unit (NPU). Source: Arteris

In addition to a processor cluster comprising multiple general-purpose central processing units (CPUs), along with several other intellectual property (IP) blocks, the SoC may also contain specialized processors or hardware accelerators. These units include an image signal processor (ISP), a graphics processing unit (GPU) and a neural processing unit (NPU), designed for high-performance, low-power AI processing.

In turn, the NPU comprises an array of identical PEs. In the not-so-distant past, these PEs were typically realized as relatively simple multiply-accumulate (MAC) functions, where MAC refers to a multiplication followed by an addition. By comparison, today’s SoCs often contain PEs with multiple IPs connected via an internal NoC.

Implementing soft tiling by hand

In the common SoC scenario we are considering here, NoCs may be employed at multiple levels in the design hierarchy. For example, a NoC can be used at the top level to connect the processor cluster, ISP, GPU, NPU and other IPs. NoCs may be implemented in various topologies, including ring, star, tree, mesh and more. Even at the top level of the SoC hierarchy, some devices may employ multiple NoCs.

As has already been noted, each PE in the NPU may consist of multiple IPs connected using an internal NoC. Furthermore, all the PEs in the NPU can be connected using a NoC, typically implemented as a mesh topology.

The traditional hand-crafted approach to implementing the NPU starts by creating a single PE. In addition to its AI accelerator logic, the PE will also contain one or more network interface units (NIUs) to connect the PE to the main mesh NoC. This is illustrated in Figure 2a.

Figure 2 This is how designers implement soft tiling by hand. Source: Arteris

If we assume that the NPU specification calls for a 4×4 array of PEs, the designer will replicate the PE 16 times using a cut-and-paste methodology (Figure 2b). Next, NoC tools will be used to auto-generate the NoC (Figure 2c). During this process, the NoC generator automatically assigns unique identifiers (IDs) to each of the NoC’s switching elements. However, the NIUs in the PEs will still have identical IDs; that is, the default ID from the PE’s creation.

For the NoC to transfer data from source nodes to destination nodes, the NIU in each PE must have a unique ID. This requires the designer to hand-modify each PE instance to provide it with its own ID. In addition to being time-consuming, this process is prone to error, which can impact downstream testing and verification.

This hand-crafted tiling technique poses several challenges. For example, changes to the PE specification are often made early in the process. For each change, the designer has two options: (a) manually replicate the change across all PE instances in the array, or (b) modify only the original PE and then repeat the entire hand-crafted soft tiling process. Both options are time consuming and error prone.

Also, performing soft tiling by hand is not conducive to scaling. If it becomes necessary to replace the original 4×4 array with an 8×8 version, such as for a derivative product, the process becomes increasingly cumbersome and problematic.

NoC-enabled tiling

The phrase “NoC-enabled tiling” refers to an emerging trend in SoC design. This evolutionary approach uses proven, robust NoC IP to facilitate scaling, condense design time, speed testing and reduce design risk.

NoC-enabled tiling commences with the designer creating a single PE as before. In this case, however, the NoC tools can be used to automatically replicate the PEs, generate the NoC and configure the NIUs in the PEs, all in a matter of seconds. The designer only needs to specify the required dimensions of the array.

Figure 3 This is how NoC-enabled tiling is carried out. Source: Arteris

In addition to dramatically speeding the process of generating the array, this “correct by construction” approach removes any chance of human-induced errors. It also enables the design team to quickly and easily accommodate change requests to the PE early in the SoC development process. Furthermore, it greatly facilitates scaling and design reuse, including the creation of derivative designs.

An evolving market

Based on an analysis of AI SoC designs currently under development by their customers, the Arteris team has determined the relative use of soft tiling in key verticals and horizontals for AI today. This is illustrated in Figure 4, where the areas of the circles reflect the relative number of application use cases.

Figure 4 NoC-enabled tiling is shown in key verticals and horizontals for AI today. Source: Arteris

Designing multi-billion-transistor SoCs is time-consuming and involves many challenges. Some SoC devices, such as those intended for AI applications, may include functions like NPUs that comprise arrays of PEs. Here, NoC-enabled tiling is an emerging trend and it’s supported only by leading NoC IPs and tools.

Andy Nightingale, VP of product management and marketing at Arteris, has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm.

 

Related Content

• SoC Interconnect: Don’t DIY!
• What is the future for Network-on-Chip?
• SoC design: When is a network-on-chip (NoC) not enough
• Network-on-chip (NoC) interconnect topologies explained
• Why verification matters in network-on-chip (NoC) design

The post Speeding AI SoC development with NoC-enabled tiling appeared first on EDN.

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The recent Design Idea “Getting an audio signal with a THD < 0.0002% made easy,” discloses a low THD sine generator which led me to dust off a design that I had published in AudioXpress magazine [1] (see Figure 1).

Figure 1 The “Simple Sineman” circuit [1] is based on a simpler version of the circuit having approximately -80dB THD [2].

Wow the engineering world with your unique design: Design Ideas Submission Guide

Requirements for an analog oscillator

Before getting into the detail of how this circuit works, it’s worth recalling certain requirements for an analog oscillator: a feedback circuit which, at the oscillation frequency fosc Hz, has a loop gain magnitude of unity and a phase shift of either 0 or a multiple of 360 degrees. One means of implementing this is to place a notch filter in the feedback loop of an op amp. You might be forgiven for thinking that fosc is at the filter’s notch frequency fnotch Hz. But obviously, infinite attenuation is not consistent with a unity gain loop. Not so obviously, the op amp’s internal compensation network adds a -90° phase shift to its inherent -180° inverting input-to-output phase shift. What is then needed for oscillation is a filter which, at fosc, exhibits both a -90° phase shift and has an attenuation of Aosc, where Aosc is the op amp gain magnitude at fosc. But how can we find a filter capable of meeting such precise constraints?

The “dual-T” notch filter

The innovative “dual-T” notch filter in Figure 1 saves the day. It’s made up of C1, C2, C3, R1, R2, R3A, and R3B. I had a need for a 2400-Hz oscillator and so chose the values shown. One way to place a notch at fnotch Hz is to use the following process and equations:

Choose a value C for C1, C2 and C3                                                (1)

and set R1 and R2 equal to 1 / (2π* fnotch*C*√3)                    (2)

set R3 = R3A + R3B equal to 12 / (2π* fnotch*C*√3)                   (3)

An analysis of this filter type shows that there is always a value of R3 which produces an infinite attenuation notch regardless of the variations of the other component values due to tolerances. Since there is clearly no attenuation at DC, this means that any attenuation from none to infinity can be had at some frequency. The analysis also shows that there is always some frequency below fnotch at which the phase shift is -90°. The appropriate value of R3 causes that phase shift to coincide with the necessary attenuation of Aosc at fosc. Figure 2 gives a feeling for some phase and gain magnitude responses of the filter as R3B is varied. Table 1 relates the oscillation and notch frequencies and values of R3 for a -90° phase shift at various attenuations Aosc.

Figure 2 Responses of the dual-T notch filter. To simulate practical variances from the ideal, capacitor values were randomly selected to be within 1% of 10 nF, and R1 and R2 to be within 0.1% of ideal values for a 2400-Hz fosc. A value of R3 that produced a 130 dB notch depth was calculated, and results are shown with it and with several slightly larger R3 values. -90° phase shifts with attenuations from 65 to 130 dB are evident for various R3 values.

Attenuation, dB	1 – fosc/fnotch	NOtol = 1 – fosc/fnotch
-90	0.01%	-0.01%
-80	0.03%	-0.02%
-70	0.11%	-0.05%
-60	0.35%	-0.18%
-50	1.07%	-0.56%

Table 1. Variations in the oscillation with respect to the notch frequencies and in R3 values for a -90° phase shift at various Aosc attenuations.

Knowing the values of fosc and Aosc, the value of fnotch can be calculated from Table 1. From this, the values of the capacitors and the resistors R1 and R2 can be calculated from equations (1) and (2). With 0.1% resistors for R1 and R2 and 1% capacitors, fnotch will be kept within a range of the tolerance product Stol = 1 +/- 1.01*1.001 ≈ 1.1% of the intended value. Note that regardless of component tolerances, there is always the option of adding a pot in series with either R1 or R2. The aggregate value of that pot plus resistor should have a range of Stol centered at the equation (2) value. The values and tolerances of R3A and R3B should be selected so that R3 can be adjusted to within Stol – NOtol (see Table 1) of the equation (3) value.

It’s worth noting that with the better-known twin-T notch filter [3], I was unable to meet the phase and attenuation requirements simultaneously by varying only a single resistor value. Even if this were possible, the capacitors in the dual T are conveniently identical, while the twin-T’s requirement of a value ratio of 2 limits capacitor choices. This is also a good time to mention that polystyrene capacitors offer the lowest harmonic distortion [4], with non-metalized polypropylene being a secondary choice.

Establishing oscillation amplitude

Of course, the elephant in the room is what I haven’t yet mentioned—the requirement for establishing an oscillation amplitude. One way of doing this is to parallel the R3 resistor plus pot with a non-linear resistor whose value varies inversely with signal level. Unfortunately, any such non-linearity increases harmonic distortion. So it makes sense to choose a non-linear component designed specifically for low harmonic distortion audio applications. The NE570 (an improved version of the SA571 seen in Figure 1) is a low harmonic distortion compressor/expandor IC intended for audio applications [5]. A block diagram of the part appears in Figure 3.

Figure 3 A block diagram of the function of the SA571 and NE570 compandor IC, curtesy of On Semiconductor.

As can been seen, the part has a “delta G” cell whose current gain is controlled by the capacitively filtered output of the rectifier. The capacitively-coupled inputs to both functions are connected in Figure 1 through resistors I’ve added to reduce the functions’ operating levels. These are driven by the output of the LME49720 op amp U2A. (The op amp provided with the SA571/NE570 is of the 741 type and should not be used in extremely low THD applications. Its output and one end of the 20K resistor R3 can be left unconnected. Its inverting input is connected to that of U2A.) Note the 1.8-V reference which is the unavoidable DC operating voltage of the delta G cell and both inputs of U2A.

The SA571/NE570 are dual parts, and use is made of the secondary unit. Its rectifier capacitor pin is grounded to disable its delta G cell, whose input is floating. The uncommitted side of its R3 is connected to its op amp output to produce a stable 3 VDC source. This source drives the Figure 1 R10 pot to supply a current to the THD trim pin. R10 is adjusted to null out the small amount of 2nd harmonic distortion produced by the delta G cell (and possibly by U2A). I powered the circuit from batteries for portability and added the LEDs to keep fresh 9-V batteries from exceeding the +/- 18 V maximum power supply ratings of the op amp. The SA571’s 30k resistor connecting the op amp inverting inputs to ground is unavoidable. With Figure 1’s R3, it biases that op amp’s output to approximately 4.5 V( (≈45k/30k + 1)*1.8 V ). This level can be reduced by connecting a resistor from the 3-V source to U2A‘s inverting input (not provided in the Figure 1 circuit). With or without this additional resistor, remember to keep a proper DC bias across output electrolytic capacitor C5.

The added passive components at the NE570 inputs are chosen to allow R3 to be adjusted for a 3 Vrms output from U2A, the level at which its datasheet indicates that that op amp exhibits the lowest THD.

Measuring distortion

To measure distortion, I attenuated the oscillator output’s fundamental by running the signal through a second dual T filter with a pot in series with each resistor. By laboriously tweaking each pot in turn, I was able to attenuate the fundamental by 70 dB. The filtered output was applied to an SR770 spectrum analyzer which can accurately measure signals within an 80 dB dynamic range. Tweaking the THD pot to minimize the 2nd harmonic level, I measured the levels of the oscillator harmonics and applied corrections for the filter attenuations at each frequency (see Table 2.) I then took the rms of the levels corrected for the attenuations of the second dual T filter and arrived at a THD more than 130 dB below the oscillator fundamental.

Harmonic Number	Filter Attenuation, dB
2	11.81
3	6.54
4	5.14
5	3.78
7	2.78
9	2.49

Table 2 Attenuation of higher harmonics by a dual-T filter tuned as described in the text to maximize attenuation of the oscillator fundamental.

The NE570 and LME49720 datasheets and parts are available online and through DigiKey. Small quantities of the NE570 for experimenters can be had from numerous eBay vendors.

I believe that it’s tough to beat the combination of simplicity and performance afforded by this design and welcome comments from anyone who builds and tests it.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content

• Getting an audio signal with a THD < 0.0002% made easy
• Measure an amplifier’s THD without external filters
• Ultra-low distortion oscillator, part 2: the real deal
• A simple circuit with an optocoupler creates a “tube” sound
• How to control your impulses—part 2

References

1. Paul, C, The Simple Sineman, audioxpress, November 2013, p. 52
2. Jung, “Gain Control 1C for Audio Signal Processing,” Ham Radio, 1977,http://waltjung.org/PDFs/Gain_Control_IC_for_Audio_Signal_Processing_HR_0777.pdf.
3. https://learningaboutelectronics.com/Articles/Notch-filter-calculator.php#answer1
4. https://www.tedss.com/LearnMore/Polystyrene-Film-Capacitors offers a wide array of polystyrene capacitors
5. ON Semiconductor, NE570 datasheet, https://www.onsemi.com/pdf/datasheet/ne570-d.pdf

The post A simple, purely analog -130dB THD sine wave generator appeared first on EDN.

For third-quarter 2024, deposition equipment maker Aixtron SE of Herzogenrath, near Aachen, Germany has reported revenue of €156.3m (up 18.6% on €131.8m last quarter but down 5% on €165m a year ago). This is in the lower half of the guidance range of €150–180m, as the delivery of a major micro-LED-related project was postponed from Q3 to Q4/2024 at the customer’s request...

For third-quarter 2024, CVD Equipment Corp of Central Islip, NY, USA (a designer and maker of chemical vapor deposition, thermal processing, physical vapor transport, gas and chemical delivery control systems, and other equipment and process solutions for developing and manufacturing materials and coatings) has reported revenue of $8.2m, up 31.4% on $6.2m a year ago. Growth is due mainly to higher CVD Equipment system revenue and an increase in gas delivery system revenue by the SDC segment, plus $0.8m from a modification of a customer contract...

The US Department of Defense (DoD) has invested an additional $160m of funds from the Biden–Harris Administration’s ‘Creating Helpful Incentives to Produce Semiconductors (CHIPS) and Science Act’ to advance US microelectronics capabilities through the Microelectronics Commons, a collaborative national network of technology hubs. Following the award in September of $269m for 33 new technical projects and the award of just under $240m released a year previously to initially launch the eight hubs, the latest funding in October represents a milestone for the CHIPS Act’s mission to strengthen the USA’s global leadership in microelectronics and semiconductor manufacturing...

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