Новини світу мікро- та наноелектроніки

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Intel is at the crossroads, again, and so is its charismatic chief, Pat Gelsinger, who was brought for a turnaround of this American semiconductor giant more than three years ago. Is trouble brewing at the Santa Clara, California-based chip industry icon? According to a recent Reuters story that chronicles Gelsinger’s three years at the helm, it looks more so.

The Reuters story titled “Inside Intel, CEO Pat Gelsinger fumbled the revival of an American icon” comes soon after the news about a possible patch-up between the foundry operations of Intel and Samsung, two outfits competing with fab market leader TSMC at cutting-edge semiconductor manufacturing processes.

While the hookup between these two TSMC rivals isn’t without merits, industry watchers mostly see it as a non-starter. Samsung, which entered the foundry business in 2017, has been able to grab an 11.5% fab market share compared to TSMC’s 62.3%. Intel, on the other hand, is just at the starting gate when it comes to the foundry business it set up in 2021.

While Gelsinger sought to transform Intel by venturing into the foundry business, the chipmaker steadily lost ground to AMD in the lucrative data center processors business. Meanwhile, its bread-and-butter PC processors business is still reeling from the post-pandemic glut. But Intel’s troubles don’t end here. Another elephant in the room, besides Intel Foundry, is the struggling artificial intelligence (AI) chips business.

Apparently, Intel is late to the AI party, and just like data center processors, that puts it behind companies like AMD and Nvidia. Intel, which launched three AI initiatives in 2019, including a GPU, hasn’t much to show so far and its Gaudi AI accelerator manufactured at TSMC seems to be falling short of expectations.

Figure 1 Gaudi was touted as an alternative to Nvidia’s GPUs. Source: Intel

While Gelsinger declined to be interviewed for this Reuters story, Intel’s statements published in this special report seem to have come straight from Gelsinger’s corner office. “Pat is leading one of the largest, boldest and most consequential corporate turnarounds in American business history,” said the Intel statement. “3.5 years into the journey, we have made immense progress—and we’re going to finish the job.”

Is Gelsinger in trouble?

Intel Foundry seems to be all Gelsinger is betting on, but this premise has proven easier said than done. As Sandra Rivera, now CEO of Altera and then head of Intel’s data center business, said while talking about Intel’s GPU foray, “It’s a journey, and everything looks simpler from the outside.” This premise perfectly fits Intel’s fab gambit as well.

Soon after taking the charge, Gelsinger vowed to form a foundry business to compete with TSMC and promised to develop five manufacturing nodes in five years. However, its 18A processing node has been facing delays, and one of its early customers, Broadcom, reportedly has yield issues. A mere 20% of its chips have passed the early tests.

Intel maintains that 18A is on track for launch in 2025. But as Goldman Sachs analyst Toshiya Hari notes, semiconductor vendors have little incentive to bet on Intel’s manufacturing when TSMC continues to serve them well.

Figure 2 The news about problems with the launch of 18 processing doesn’t bode well for the company’s foundry ambitions. Source: Intel

When a large company becomes an acquisition target, it generally spells doom. So, in another statement in the Reuters story, Intel said that it won’t let merger speculation distract it from executing its five-year turnaround plan. That clearly shows the pressure and how Gelsinger is asking more time to put the house in order.

Will Gelsinger get more time? He acknowledges a lot of work ahead but is confident that Intel will pull it off. But if the foundry business betting on Intel’s chip manufacturing prowess takes longer to bear fruit, Gelsinger’s rocky tenure may end sooner than later.

Related Content

• Change of guard at Intel Foundry, again
• Intel Paints Their AI Future with Gaudi 3
• Intel 3 Represents an Intel Foundry Milestone
• Computex 2024: Pat Gelsinger vs. Jensen Huang
• Intel unveils service-oriented internal foundry model

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https://preview.redd.it/lksgcptotbyd1.png?width=850&format=png&auto=webp&s=eb9ea2693e789f9f4a0d58eb264ed990f23914ad this board is for controlling 5 stepper motor using for a split flap display project. I'm new to the whole electronique thing so there is probably a thousand wrong thing with this board but it's my first one so i hope to get better. submitted by /u/tatoinee [link] [comments]

Piezoelectric actuators (benders, stacks, chips, etc.) are excellent fast and precise means for generation and control of micro, nano, and even atomic scale movement on millisecond and faster timescales. Unfortunately, they are also excellent high-Q resonators. Figure 1 shows what you can expect if you’re in a hurry to move a piezo and simply hit it with a unit step. Result: a massive (nearly 100%) overshoot with prolonged follow-on ringing.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 Typical piezo actuator response to squarewave drive with ringing and ~100% overshoot.

 Don’t worry. It’ll get there. Eventually. But don’t hold your breath. Clearly something has to be done to modify the drive waveshape if we’re at all interested in speed and settling time. Many possibilities exist, but Figure 2 illustrates a remarkably simple yet effective trick that actually takes advantage of the piezo’s natural 2x overshoot: Half and Half step drive.

Figure 2 Half &Half drive step with half amplitude and half resonance period kills overshoot and ringing.

 The surprisingly simple trick is to split the drive step into an initial step with half the desired movement amplitude and a duration of exactly half the piezo resonance period. Hence: “Half & Half”(H&H) drive. The half-step is then followed by application of the full step amplitude to hold the actuator in its new position.

The physics underlying H&H rely on kinetic energy imparted to the mass of the actuator during the first quarter cycle to be just sufficient to overcome actuator elasticity during the second quarter, this bringing the actuator to a graceful stop at half cycle’s end. The drive voltage is then stepped to the full value, holding the actuator stationary at the final position.

Shown in Figure 3 is H&H would work for a sequence of arbitrary piezo moves.

Figure 3 Example of three arbitrary H&H moves: (T2 – T1) = (T4 – T3) = (T6 – T5) = ½ piezo resonance period.

If implemented in software, the H&H algorithm would be simplicity itself and look something like this:

Let DAC = current contents of DAC output register
N = new content for DAC required to produce desired piezo motion
Step 1: replace DAC = (DAC + N) / 2
Step 2: wait one piezo resonance half-period
Step 3: replace DAC = N
Done

If implemented in analog circuitry, H&H might look like Figure 4. Here’s how it works.

Figure 4 The analog implementation of H&H.

 The C1, R1, C2, R2||R3 voltage divider performs the half-amplitude division function of the H&H algorithm, while dual-polarity comparators U2 detect the leading edge of each voltage step. Step detection triggers U3a, which is adjusted via the TUNE pot to have a timeout equal to half the piezo resonance period, giving us the other “half”.

U3a timeout triggers U3b, which turns on U1, outputting the full step amplitude, completing the move. The older metal gate CMOS 4066 is used due to its superior low-leakage Roff spec’ while the parallel connection of all four of its internal switches yields an adequately low Ron.

U4 is just a place keeper for a suitable piezo drive amplifier to translate from the 5-V logic of the H&H circuitry to piezo drive voltage and power levels.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Piezoelectric Technology: A Primer
• Reducing MLCCs’ piezoelectric effects and audible noise
• Increase piezoelectric transducer acoustic output with a simple circuit
• Reduce acoustic noise from capacitors

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NXP has expanded its eIQ AI and ML software development environment with two new tools to simplify AI deployment at the edge. The software supports low-latency, energy-efficient, and privacy-focused AI, enabling ML algorithms to run on a range of edge processors, from small MCUs to advanced application processors.

The eIQ Time Series Studio introduces an automated machine learning workflow for efficiently developing and deploying time-series ML models on MCU-class devices, including NXP’s MCX series of MCUs and i.MX RT crossover MCUs. It supports various input signals—voltage, current, temperature, vibration, pressure, sound, and time of flight—as well as multi-modal sensor fusion.

GenAI Flow provides the building blocks for creating Large Language Models (LLMs) that power generative AI applications. With Retrieval Augmented Generation (RAG), it securely fine-tunes models on domain-specific knowledge and private data without exposing sensitive information to the model or processor providers. By linking multiple modules in a single flow, users can customize LLMs for specific tasks and optimize them for edge deployment on MPUs like the i.MX 95 application processor.

To learn more and access the newest version of the eIQ machine learning development environment, click on the product page link below.

eIQ product page

NXP Semiconductors 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Half-duplex RS-485 transceivers from MaxLinear offer extended ESD and EFT protection to ensure reliable communication in industrial environments. The MxL8312x and MxL8321x families include nine product SKUs with three speed options—250 kbps, 500 kbps, and 50 Mbps—and three package variants, including small 3×3-mm types.

These families expand MaxLinear’s portfolio with mid- and high-tier products alongside the MxL8310x and MxL8311x lineup of RS-485 transceivers. Smaller form-factor packages, higher speeds, and enhanced system-level ESD and EFT protection make them well-suited for delivering high performance under harsh conditions. Key applications include factory automation, industrial motor drives, robotics, and building automation.

The transceivers’ bus pins tolerate up to ±4 kV of electrical fast transients (IEC 61000-4-4) and up to ±12 kV of electrostatic discharge (IEC 61000-4-2). A supply range of 3.3 V to 5 V supports reliable operation in systems with potential power drops, while an extended common-mode range of up to ±15 V ensures stable communication over long distances or in applications with significant ground plane shifts between devices. MxL83214 devices are cable of supporting 50-Mbps data rates with strong pulse symmetry and low propagation delays.

In addition to conventional 4.9×3.9-mm NSOIC-8 packages, the transceivers are offered in 3×3-mm MSOP-8 and VSON-8 packages. The MxL83121, MxL83122, MxL83211, MxL83212, and MxL83214 are available now.

MaxLinear

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Vishay’s VOFD341A and VOFD343A IGBT and MOSFET drivers, available in stretched SO-6 packages, provide peak output current of up to 4 A. Their high peak output current allows for faster switching by eliminating the need for an additional driver stage. Each device contains an AlGaAs LED optically coupled to an integrated circuit with a power output stage, specifically designed for driving power IGBTs and MOSFETs in motor control inverters.

The drivers support an operating voltage range of 15 V to 30 V and feature an extended temperature range of -40°C to +125°C, ensuring a sufficient safety margin for more compact designs. They also have a maximum propagation delay of 200 ns, which minimizes switching losses and facilitates more precise PWM regulation.

Additionally, the drivers’ high noise immunity of 50 kV/µs helps prevent failures in fast-switching power stages. Their stretched SO-6 package provides a maximum rated withstanding isolation voltage of 5000 VRMS.

Samples and production quantities of the 3-A VOFD341A and 4-A VOFD343A are available now, with lead times of six weeks.

VOFD341A product page 

VOFD343A product page 

Vishay Intertechnology 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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With a thickness of only 20 µm and a diameter of 300 mm, Infineon’s silicon power wafers are the thinnest in the industry. These ultra-thin wafers are a quarter the thickness of a human hair and half the thickness of typical wafers, which range from 40 µm to 60 µm. This achievement in semiconductor manufacturing technology will increase energy efficiency, power density, and reliability in power conversion for applications such as AI data centers, motor control, and computing.

Infineon reports that reducing the thickness of a wafer by half lowers the substrate resistance by 50%, resulting in over a 15% reduction in power loss in power systems compared to conventional silicon wafers. For high-end AI server applications, the ultra-thin wafer technology enhances vertical power delivery designs based on vertical trench MOSFETs, enabling a close connection to the AI chip processor. This minimizes power loss and improves overall efficiency.

Infineon’s wafer technology has been qualified and integrated into its smart power stages, which are now being delivered to initial customers. As the ramp-up of ultra-thin wafer technology progresses, Infineon anticipates that it will replace existing conventional wafer technology for low-voltage power converters within the next three to four years.

Infineon will present the first ultra-thin silicon wafer publicly at electronica 2024.

Infineon Technologies 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Murata’s stretchable printed circuit (SPC) offers both flexibility and the ability to stretch or deform without losing functionality. It can be used in wearable therapeutic devices and vital monitoring tools, providing improved accuracy, durability, and patient comfort compared to current devices.

Many existing devices are too rigid for certain applications, leading to patient discomfort, poor contact with surfaces, and unstable data acquisition. The SPC’s flexibility, stretchability, and adaptability support multi-sensing capabilities and a wide range of user requirements. Its soft material is gentle on the skin, making it well-suited for disposable EEG, EMG, and ECG electrodes that meet ANSI/AAMI EC12 standards. The stretchable design allows a single device to fit various body areas, like elbows and knees, and accommodate patients of different sizes.

SPC technology ensures seamless integration and optimal performance through telescopic component mounting and hybrid bonding between substrates. Its shield layer effectively blocks electromagnetic noise, providing reliable signal-path protection. The substrate construction also enhances moisture resistance and supports sustained high-voltage operation.

Murata’s SPC is customizable based on application requirements.

SPC product page

Murata Manufacturing

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The new PIC16F131xx microcontrollers in TME’s offer from Microchip are ideal for the evolving and miniaturizing electronic equipment market, offering efficient power management and predictable response times for controllers. 

Key features include core independent peripherals (CIPs) like the configurable logic block (CLB), which allows for predictable circuit behavior without burdening the CPU, thereby saving energy. These microcontrollers, based on the classic 8-bit Harvard architecture, come in various packages (DIP, DFN, SSOP, TSSOP, SOIC, and VQFN) with 6 to 18 I/O pins, and support a wide voltage range (1.8V to 5.5V DC). They operate at a 32 MHz clock frequency, with instruction execution times as low as 125 ns, and offer 256 to 1024 bits of SRAM and up to 14 kB of FLASH program memory. 

The microcontrollers are equipped with an array of peripherals, including PWM generators, counters/timers, EUSART serial bus controllers, and MSSP modules for I2C or SPI operation. They also feature configurable comparators, an 8-bit DAC, and a 10-bit ADC with hardware processing capabilities (ADCC) 

The core independent peripherals (CIPs) allow the microcontrollers to handle tasks like sensor communication without using the CPU, thus enhancing efficiency and simplifying programming. The CLB technology, a highlight of the PIC16F131xx series, uses basic logic gates configurable by the designer, facilitating functional safety and rapid response times.  

The Curiosity Nano development kit for the PIC16F131xx series offers a convenient platform for exploring the microcontrollers’ capabilities, featuring an integrated debugger, programming device, and access to microcontroller pins. The EV06M52A kit, equipped with the PIC16F13145 microcontroller, includes a USB-C port for power and programming, an LDO MIC5353 regulator, a green LED for power and programming status, a yellow LED, and a button for user interaction.  

Additionally, adapters like the AC164162 extend the functionality of the Curiosity Nano boards, offering compatibility with mikroBUS standard connectors and an integrated charging system for lithium-ion and lithium-polymer cells. 

The new microcontroller series from Microchip offers efficient power management, predictable response times, and innovative features like core independent peripherals (CIPs) and configurable logic blocks (CLB). These microcontrollers, ideal for modern embedded systems, come in various packages and support a wide voltage range, enhancing their versatility and performance. The Curiosity Nano development kit and its adapters further facilitate easy development and prototyping. 

These products are available in TME’s offer, providing a comprehensive solution for designers and developers looking to leverage the latest advancements in microcontroller technology. 

Text prepared by Transfer Multisort Elektronik S.p. z o.o. 

 

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The surge in memory-hungry artificial intelligence (AI) and machine learning (ML) applications has ushered in a new wave of accelerated computing demand. As new design parameters ramp up processing needs, more resources are being packed into single units, resulting in complex processes, overburdened systems, and higher chances of anomalies. In addition, demands of these complex chips presents challenges with meeting reliability, availability, and serviceability (RAS) requirements.

One major, yet often overlooked, RAS concern and root cause of computing errors is silent data corruption (SDC). Unlike software-related issues, which typically trigger alerts and fail-safe mechanisms, SDC issues in hardware can go undetected. For instance, a compromised CPU may miscalculate data, leading to corrupt datasets that can take months to resolve and cost organizations significantly more to fix.

Figure 1 A compromised CPU may lead to corrupt datasets that can take months to resolve. Source: Synopsys

Meta Research highlights that these errors are systemic across generations of CPUs, stressing the importance of robust detection mechanisms and fault-tolerant hardware and software architectures to mitigate the impact of silent errors in large-scale data centers. Anything above zero errors is an issue given the size, speed, and reach of hyperscalers. Even a single error can result in a significant issue.

This article will explore the concept of SDC, why it continues to be a pervasive issue for designers, and what the industry can do to prevent it from impacting future chip designs.

The multifaceted hurdle

Industry leaders are often hesitant to invest in resources to address SDC because they don’t fully understand the problem. This reluctance can lead to higher costs in the long run, as organizations may face significant operational setbacks due to undetected SDC errors. Debugging these issues is costly and not scalable, often resulting in delayed product releases and disrupted production cycles.

To put this into perspective, today’s machine learning algorithms run on tens of thousands of chips, and if even one in 1,000 chips is defective, the resulting data corruption can obstruct entire datasets, leading to massive expenditures for repairs. While cost is a large factor, the hesitation to invest in SDC prevention and fixes is not the only challenge. The complexity and scale of the problem also make it difficult for decision makers to take proactive measures.

Figure 2 Defect screening rate is shown using DCDIAG test to assess a processor. Source: Intel

Chips have long production cycles, and addressing SDC can take several years before fixes are reflected in new hardware. Beyond the lengthy product lifecycles, it’s also difficult to measure the scale of SDC errors, presenting a big challenge for chipmakers. Communicating the magnitude and urgency of an issue to decision makers without solid evidence or data is a daunting task.

How to combat silent data corruption

When a customer receives a faulty chip, the chip is typically sent back to the manufacturer for replacement. However, this process is merely a remedy for the larger SDC issue. To shift from symptom mitigation to a problem-solving solution, here are some avenues the industry should consider:

• Research investments: SDC is an area the industry is aware of but lacks comprehensive understanding. We need researchers and engineers to focus on SDC despite how costly the investment will be. This involves generating and sharing extensive data for analysis, identifying anomalies, and diagnosing potential issues like time delays or data leaks. All things considered, enhanced research will help clarify and manage SDC effectively.
• Incentive models: Establishing stronger incentives with more data for manufacturers to address SDC will help tackle the growing problem. Like the cybersecurity industry, creating industry-wide standards for what constitutes a safe and secure product could help mitigate SDC risks.
• Sensor implementation: Implementing sensors in chips that alert chip designers to a potential problem is another solution to consider, similar to automotive sensors that alert the owner when tire pressure is low. A faulty chip can go one to two years without being detected, but sensors will be able to detect a problem before it’s too late.
• AI and ML toolbox: AI algorithms, an option that is still in the early stages, could flag conditions indicative of SDC, though this requires substantial data for training. Effective implementation would necessitate careful curation of datasets and intentional design of AI models to ensure accurate detection.
• Silicon lifecycle management (SLM) strategy: SLM is a process that allows chip designers to monitor, analyze and optimize their semiconductor devices throughout its life. By executing this strategy, it makes it easier for designers to track and gain actionable insights on their device’s RAS in real time and ultimately, detecting SDC before it’s too late.

Partly due to its stealthy nature, SDC has become a growing problem as the scale of computing has increased over time, and the first step to solving a problem is recognizing that a problem exists.

Now is the time for action, and we need stakeholders from all areas—academics, researchers, chip designers, manufacturers, software and hardware engineers, vendors, government and others—to collaborate and take a closer look at underlying processes. Together, we can develop solutions at every step of the chip lifecycle that effectively mitigate the lasting impacts of SDC.

Jyotika Athavale is the director for engineering architecture at Synopsys, leading quality, reliability and safety research, pathfinding, and architectures for data centers and automotive applications.

Randy Fish is the director of product line management for the Silicon Lifecycle Management (SLM) family at Synopsys.

Related Content

• Uncovering Silent Data Errors with AI
• Avoid corruption in nonvolatile memory
• A systems approach to embedded code fault detection
• Understanding the effects of power failure on flash-based SSDs
• Protecting your embedded software against memory corruption

The post Understanding and combating silent data corruption appeared first on EDN.

Wide-bandgap power semiconductor materials, component and foundry services provider Sanan Semiconductor Co Ltd of Changsha City, Hunan, China has expanded its silicon carbide (SiC) power product portfolio by launching 1700V and 2000V devices, offering high power efficiency in applications ranging from renewable energy to electric vehicle charging infrastructure...

JST Manufacturing Inc of Meridian, ID, USA (a provider of wet benches, single-wafer surface preparation equipment and chemical processing systems) has appointed Dr Ismail Kashkoush as chief technology officer. Bringing over 30 years of engineering and industry expertise, he will lead JST’s engineering, technology and product line teams in the development of its surface preparation products and processes...

For coverage of all the key business and technology developments in compound semiconductors and advanced silicon materials and devices over the last month, subscribe to Semiconductor Today magazine...