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We stand at the dawn of a new era in chip design as artificial intelligence (AI) moves from a conceptual promise to a practical necessity in the semiconductor landscape. Semiconductor companies are looking to AI to help manage design complexity, accelerate development cycles, and maintain the high standards of quality and reliability demanded by the semiconductor industry.

IC design teams are confronting physical, electrical, and reliability verification challenges that require new approaches to achieve acceptable speed and cost. Advanced-node designs bring thousands of design rules, dense hierarchical layouts, and millions of circuit errors that need to be debugged during the design flow. Manual workflows that once sufficed now create schedule bottlenecks which threaten product launches and market windows.

This creates a fundamental tension between speed and risk: Verification teams need AI-driven acceleration to manage complexity and compress schedules, yet IC signoff remains one of engineering’s most risk-averse domains.

A single undetected error can cost millions in respins or field failures. The question facing design organizations is not whether to adopt AI, but how to deploy it in ways that enhance both speed and confidence.

The intelligence foundation: Generative and agentic AI platforms

By balancing advanced algorithms with openness, these platforms can serve design needs while upholding intellectual property (IP) integrity—a crucial factor for building trust. Such systems ensure that designers can tap into a powerful, secure, and customizable environment, enabling continuous learning within a protected infrastructure.

The AI platforms becoming available are designed to integrate across the entire electronic design automation (EDA) tool stack, providing a unified intelligence layer. Figure 1 shows an example of a system architecture that integrates AI models with a multimodal “data lake” to support diverse verification tasks.

Figure 1 In an AI platform for chip design, the internal architecture with AI models and a multimodal data lake underpin the tools for a design flow. Usage modalities are shown on the right. Source: Siemens EDA

Determinism at the core: Why signoff engines must remain AI-free

A strategic consideration in the age of AI is that for the core signoff calculations—which determine whether a chip design is clean and ready for manufacturing—must be done with rigorous, deterministic algorithms, not probabilistic AI models. IC design teams responsible for signoff need confidence that repeated runs will always produce the same results; there is no room for AI “hallucinations” seen with probabilistic models.

This foundation in determinism directly supports trust in any design flow that includes AI. Engineers, managers, and foundry partners must be able to rely on results, providing certainty that each signoff result is the product of rigorous, provable mathematics. Figure 2 illustrates how a deterministic signoff engine remains central to the process, ensuring reproducible analysis and audit-ready results, while AI-powered tools enhance peripheral tasks like setup, error debugging, and collaboration.

Figure 2 This diagram illustrates an AI-augmented signoff process, detailing inputs, the core deterministic signoff engine, AI-accelerated setup, AI-powered error grouping and debug, AI-enabled collaboration tools, and the resulting outputs. Source: Siemens EDA

Productivity revolution: Where AI transforms the verification journey

While the core signoff remains deterministic, the path leading to signoff involves a series of complex phases that are ripe for AI-driven optimization. Leveraging AI in conjunction with deterministic engines is already improving productivity in three primary areas:

Resource optimization

Setting up verification jobs is increasingly complex, time consuming, and error prone due to the number of tasks and different compute environments, from on-premise clusters to the cloud. AI can help engineers manage and optimize these jobs by providing real-time monitoring, actionable recommendations, and post-run analytics. This approach improves hardware usage through compute resource optimization and speeds up job turnaround.

Error debugging and prioritization

One of the biggest bottlenecks in signoff is debugging. Designs at advanced nodes often generate millions of errors in early verification passes. AI-powered tools let designers sift rapidly through enormous error sets by categorizing and prioritizing issues so engineering attention is immediately focused on the most critical problems. In one instance, a leading GPU manufacturer leveraged AI-driven visual analysis to reduce verification time by 50%—translating weeks of effort into just days.

Collaboration and delegation

Modern semiconductor teams are globally dispersed. AI can group errors and assign them to specific team members, ensuring that productivity isn’t lost in handoffs. Applying familiar digital collaboration workflows—such as bookmarking and assignment—in an engineering context brings clarity and speed to what used to be a fragmented process.

AI-driven verification tools, like the one illustrated in Figure 3, integrate full chip analysis with intelligent debug capabilities to streamline error management and team communication.

Figure 3 Modern verification software provides a visual interface for full chip analysis, intelligent debugging through error clustering and prioritization, and enhanced user collaboration for streamlined results distribution. Source: Siemens EDA

Learning and growing with AI-assisted tools

AI in physical or electrical verification is not just about automation for its own sake. Features that provide contextual, in-house documentation and root-cause explanations help both experienced and junior designers understand not only what went wrong, but why it matters and how to fix it.

Incorporation of AI into design tools can be used to capture critical designer knowledge that can be leveraged throughout the organization. In this way, AI is part of the debug process, where a training aid accelerates ramp-up and enables distributed teams to achieve expert-level productivity.

Figure 4 shows how an intelligent interface can display a detailed list of design checks with results, allowing users to add fixing suggestions, view visual comparisons, and access shared notes. In this example, this “assistant” gets more valuable over time as it captures designer expertise every time it’s utilized.

Figure 4 Capturing notes about fixing a violation or displaying shared insights across the organization enhances the design verification flow. Source: Siemens EDA

Keeping IP secure: Customization, openness, and control

Gaining trust in AI also depends on how data is managed and knowledge is shared. A “data lake” approach ensures each organization can incorporate its own designs, best practices, and internal documentation into the AI system—always within a secure, isolated environment. The result is continuous system learning and richer insight that ensures sensitive IP remains strictly within the company boundary.

As design and manufacturing complexity continue to grow, the industry is extending AI-enabled productivity gains to additional domains: layout versus schematic (LVS), electrical reliability, and even automated error correction. The roadmap is ambitious, but the guiding philosophy remains clear: trust the deterministic core and unleash productivity with AI where it adds value.

AI with accountability: A balanced approach

The semiconductor industry’s balance between innovation and risk requires a nuanced approach to AI. By aiming for practical automation around a bedrock of deterministic signoff, design teams can achieve real-time productivity and confidence without compromising on quality or control.

As industry moves toward higher complexity chips, this blend of innovation and trust will be the true differentiator in AI-driven EDA.

Carey Robertson, VP of product management at Siemens EDA, oversees the product development for Calibre Design Side products. He has been with Mentor Graphics/Siemens EDA for 27 years in various product management/engineering roles. Prior to Siemens EDA, Carey was a design engineer at Digital Equipment Corp. (DEC), working on microprocessor design.

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Keysight Technologies, today announced that AttoTude Inc., a pioneer of next-generation ASICs over Dielectric interconnect technology for AI and hyperscale data center applications, has expanded its use of Keysight EDA software to manage its full IC design workflow. As a result, AttoTude has reduced its design cycles by more than 50% while achieving first-pass silicon success across advanced RF, sub-THz, and THz tape-outs that underpin its guided-wave interconnect platform.

Design velocity is emerging as a competitive advantage, with global semiconductor revenue forecast to exceed $1.3 trillion in 2026 and AI semiconductors expected to account for 30% of the market. For organizations developing AI interconnect technologies, accelerating silicon development while minimizing costly respins is vital to delivering the required bandwidth, efficiency, and scalability.

AttoTude designs integrated circuits that support per-lane data rates of 200G, 400G, and 800G, where on-chip interconnects behave as waveguides and accurate electromagnetic simulation is essential. With engineers working in parallel on sub-THz and THz subsystems, coordinating workloads without a shared, version-controlled environment makes first-pass silicon success difficult to achieve at scale. With the Keysight Advanced Design System (ADS) platform, AttoTude has cut design cycles to less than six weeks, with designs consistently performing to specification on first silicon.

Utilizing Keysight’s design data management software, AttoTude maintains a single source of truth across its design environment, giving engineers full traceability and visibility at every stage. System-level scenario planning allows the team to explore design trade-offs before committing to silicon, with simulation-to-measurement correlation ensuring results reflect performance. As operating frequencies extend from RF into the sub-THz and THz domains, maintaining consistency between layouts, electromagnetic models, and simulation data becomes critical to delivering reliable silicon.

Richard Chan, ASIC Architect and Development Leader, AttoTude, said: “Developing an ASICs over Dielectric interconnect platform that spans signaling frequencies from 100 GHz to 3 THz requires an exceptional level of design accuracy and simulation fidelity. Keysight’s EDA software has enabled our engineering team to move faster with greater confidence, helping us accelerate development while consistently achieving first-pass silicon success.”

Nilesh Kamdar, General Manager, Keysight EDA, said: “At Keysight, we measure success by what our customers achieve. The next generation of AI infrastructure will be built by the teams that move from design to silicon fastest, and AttoTude is proving what that speed makes possible.”

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The rise of generative AI and large-language models is forcing a complete redesign of data centers in India. Traditional setups designed for 5 to 10 kW per rack simply cannot handle modern GPU clusters, which regularly push power densities beyond 30 to 100 kW. When you hit those numbers, standard air conditioning stops working, and the risk of thermal throttling or total power failure becomes a daily operational challenge.

Running an AI-ready facility today comes down to specialized power electronics, direct-to-chip liquid cooling, heavy-duty physical enclosures, and rock-solid grid stability. Here is how five key infrastructure providers are building the physical hardware behind India’s AI compute push.

1. Delta Electronics India

AI workloads pull massive, continuous surges of electricity while throwing off extreme heat. Delta handles both sides of that equation with specialized power electronics and liquid cooling built explicitly for compute-dense environments. The portfolio centers on megawatt-scale power shelves, high-efficiency UPS systems, and specialized Liquid-to-Liquid (L2L) and Liquid-to-Air (L2A) Cooling Distribution Units (CDUs). By routing direct-to-chip liquid cooling straight to high-TDP processors, Delta keeps Power Usage Effectiveness (PUE) low without letting high-density racks overheat under peak workloads.

2. Eaton India

Training large AI models creates sudden, severe power spikes that can strain local grids and trigger dangerous voltage sags within a facility. Eaton solves this at the power layer with high-density Power Distribution Units (PDUs), energy-storage-ready UPS setups, and smart switchgear designed to buffer heavy load fluctuations. Their systems make it possible to integrate renewable energy directly into high-density data centers while keeping internal power quality steady around the clock.

3. Stulz India

When heat outputs surpass standard HVAC limits, precision thermal management takes over. Stulz specializes in custom direct to-chip and liquid cooling infrastructure, precision air handling, and high-capacity chillers engineered for dense server rooms. Their fluid distribution loops allow operators to shift from hybrid air-water systems toward full liquid cooling setups, keeping sensitive server components running safely without risking heat-induced performance drops.

4. Rittal India

Heavy AI server nodes—packed with multiple GPUs and fluid lines—are drastically heavier and more complex than standard IT equipment. Rittal manufactures industrial-grade modular rack systems, climate-controlled enclosures, and inline cooling manifolds engineered to bear heavy structural loads. Their sealed rack designs integrate liquid lines directly into the enclosure frame, keeping complex server arrays organized, cooled, and isolated within small physical footprints.

5. CoolIT Systems

When rack densities cross the 100 kW mark, pulling heat directly off the silicon becomes non-negotiable. CoolIT builds the custom cold plates, fluid distribution manifolds, and heat-exchange units that sit directly on top of high-performance chips. Partnering with global server OEMs and data center builders, they provide the internal liquid loops necessary to keep high frequency processors running cool under continuous parallel processing loads.

Building the Foundation for AI Compute

India’s AI growth depends entirely on what is happening on the server room floor. The real work is being done by high efficiency power converters, liquid cooling loops, robust enclosures, and stable sub-stations. As compute demands scale up, these hardware manufacturers are laying down the actual foundation that makes real-world AI processing possible.

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The Council of Scientific and Industrial Research – National Aerospace Laboratories (CSIR-NAL) have launched a trilogy of home-made micro and small gas turbine engines, in a move aimed at strengthening India’s capabilities in the hi-end aerospace propulsion and unmanned defence domain.

Launched on August 25 at the SSB Auditorium at CSIR Headquarters in New Delhi, the engines are the NJ-05, NJ-50 and NJ-100 that produce thrusts of 5kg, 50kg and 100kg. These compact propulsion systems units have been developed to address critical requirements for indigenous defence technologies and are suitable to fit in tactical UAVs, drone interceptors and other small missile systems.

The ceremony was attended by senior officials of the scientific and defence sectors of India. Air Marshal Tejinder Singh, the Chief of Integrated Defence Staff to the Chairman of the Chiefs of Staff Committee was the chief guest. Dr N. Kalaiselvi, Director General of CSIR and Secretary, of the Department of Scientific and Industrial Research emphasized the significance of developing specialised and critical aerospace subsystems indigenously, supporting India’s goal of achieving self-reliance in critical propulsion technologies under the ‘Atmanirbhar Bharat’ initiative.

The NJ-05 serves as a critical building block in this program. According to CSIR-NAL, the technology demonstrator has achieved full development and was successfully demonstrated on a small scale flight test model aircraft. It produces 50 N static sea level rated thrust with design speed ranging to 100,000 rpm, generating up to 75 N thrust.

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KYOCERA AVX, a leading global manufacturer of advanced electronic components engineered to accelerate technological innovation and build a better future, released two new series of compact, vibration-proof aluminum electrolytic capacitors engineered for harsh industrial environments.

Designed to overcome the mechanical stress challenges that have limited the application of aluminum electrolytic capacitors in industrial applications, the new AEVA and AEVB Series aluminum electrolytic capacitors feature compact, surface-mount form factors equipped with innovative plastic supports that improve vibration performance and unique termination shapes that maximize the soldering area. These features also increase the capacitors’ board mounting strength.

The new AEVA and AEVB Series aluminum electrolytic capacitors feature liquid electrolyte dielectrics, provide high-CV performance in smaller packages than competing can-type aluminum electrolytics, and ruggedly withstand up to 30g acceleration and operating temperatures as low as -55°C and as high as +125°C. They exhibit very low ESR, low leakage (≤0.01CV or 3μA, whichever is greater), and high endurance, with rated lifetimes up to 5,000 hours at rated voltage and 125°C, and are halogen-free, lead-free compatible, and RoHS compliant. Both series are ideally suited for industrial applications exposed to high vibration and temperatures — including robotics, embedded motor control units, photovoltaic inverters, power tools, DC/DC converters, and uninterruptable power supplies (UPS) — and are shipped on 15” reels and compatible with reflow soldering to support automated placement.

AEVA Series vibration-proof aluminum electrolytic capacitors are currently available in five case sizes (0810, 1010, 1213, 1616, and 1821) and rated for 6.3–100VDC, 10μF–4,700μF ±20%, operating temperatures extending from -55°C to +125°C, and up to 4,000 hours endurance at rated voltage and 125°C.

AEVB Series vibration-proof aluminum electrolytic capacitors are currently available in four case sizes (0810, 1010, 1213, and 1616) and rated for 16–50VDC, 47μF–2,200μF ±20%, operating temperatures extending from -40°C to +125°C, and up to 5,000 hours endurance at rated voltage and 125°C.

“Mechanical stress has long been a critical concern for aluminum electrolytic capacitors,” said Mack Cartagena, Staff Research Development Engineer, KYOCERA AVX. “To overcome this common challenge, we gave the new AEVA and AEVB series a unique plastic support and special terminations designed to increase the soldering area. These features significantly improve board mounting strength and ensure reliable performance under up to 30g of acceleration. These capacitors are also rated for operating temperatures up to +125°C to effectively address the demands of industrial applications, and every unit is tested in accordance with international standards to uphold the exceptional quality that KYOCERA AVX is known for.”

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The G3VH SiC MOSFET relay from Aratas America supports high-voltage switching applications requiring load voltages of 1800 V or 3300 V. SiC MOSFET technology enables high-voltage switching with low leakage current and fast switching while minimizing power loss and heat generation.

The G3VH relay is well suited for semiconductor test equipment, battery management systems, measuring instruments, and other applications demanding precise, high-voltage switching. Available in a 6-pin DIP with either board-mount or surface-mount terminals, the device contributes to equipment miniaturization.

The 1800-V and 3300-V versions support continuous load currents of 30 mA and 300 mA, respectively, with maximum leakage currents of 10 µA and 1 µA when the relay is open. Maximum turn-on times are 1 ms for the 1800-V version and 2 ms for the 3300-V version, while turn-off time is 0.2 ms for both versions. On-resistance is 200 Ω for the 1800-V version and 5 Ω for the 3300-V version. These specifications are measured at an input current (IF) of 10 mA and the respective continuous load current, with the load current applied for less than 1 s.

G3VH relays are available from authorized distributors, including Arrow Electronics, Newark, and Mouser.

G3VH product page 

Aratas America 

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Advantech has launched four industrial vision intelligence products based on the Qualcomm Dragonwing IQ-9075 processor. The AOM-6741 SMARC module, ASR-A503/AFE-A503 robotic controllers, and AIR-055 edge AI system deliver up to 100 TOPS of AI performance and provide interfaces for multi-camera vision processing. They enable real-time vision reasoning for robotics, industrial automation, and smart surveillance applications.

The Dragonwing IQ-9075 integrates an ISP, VPU, and NPU with MIPI-CSI, USB 3.0, and GbE interfaces for image preprocessing and video streaming. It supports multi-camera deployments and computer vision workloads such as object detection, tracking, and OCR. The processor also features an 8-core Kryo Gen 6 CPU and an integrated MCU subsystem for real-time, deterministic performance.

Each IQ9-powered product offers a range of communication interfaces. The AOM-6741 full-size SMARC 2.2 edge AI module includes four 4-lane MIPI-CSI camera inputs. The ASR-A503 4-in. single-board robot controller and AFE-A503 enclosed controller provide sensor connections for up to eight GMSL cameras. The AIR-055 edge AI inference system supports multimodal inputs in a fanless, enclosed design.

Samples of the AOM-6741, ASR-A503, AFE-A503, and AIR-055 are now available.

Advantech

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Toshiba’s TCKE1401NM 75-V, 6-A eFuse provides 48-V power-line protection for industrial and consumer equipment, including servers and power tools. In addition to short-circuit, overcurrent, and overvoltage protection, it integrates reverse current blocking, input reverse polarity protection, and thermal shutdown in a 4×4-mm VQFN24D package.

The TCKE1401NM operates from a 4.7-V to 75-V input, with an 80-V absolute maximum input voltage. Its high-voltage tolerance makes it suitable for power-line protection in 24-V, 48-V, and 54-V systems. The eFuse has a maximum output current of 6 A and integrates a MOSFET with a typical on-resistance of 44.5 mΩ, helping to reduce power loss during operation.

Operating thresholds for overcurrent limiting (0.82 A to 6.43 A typical), undervoltage lockout, and overvoltage protection are set with external resistors. Slew-rate control is adjustable with an external capacitor to reduce inrush current. Overcurrent fault response is selectable via a mode pin for either auto-retry or latch-off operation. Reverse current blocking and reverse polarity protection are provided using an external MOSFET.

Toshiba says it has now begun shipments of the TCKE1401NM eFuse.

TCKE1401NM product page 

Toshiba Electronic Devices & Storage 

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Morse Micro’s MM8108-RD09 and MM8108-RD17 USB dongle reference designs add Wi-Fi HaLow connectivity to existing devices. The RD09 uses host-side drivers for Windows, Linux, and macOS, while the driverless RD17 presents itself as a standard USB Ethernet interface. Both designs are based on the company’s MM8108 Wi-Fi HaLow SoC, which uses a 1-GHz 256-QAM physical layer to deliver maximum PHY throughput of 43.4 Mbps over a distance of up to 1 km.

The MM8108-RD09 provides Wi-Fi HaLow connectivity for access points and client devices. OpenWrt drivers enable HaLow functionality on routers and APs with a USB interface, while native Windows and Linux drivers and a macOS application support client devices.

The MM8108-RD17 provides driverless Wi-Fi HaLow connectivity for a wide range of client devices. The USB dongle appears to the host as a standard CDC-NCM Ethernet interface, enabling use with industrial computers, robots, point-of-sale terminals, and Android or iOS devices. A pairing button enables device authentication through Wi-Fi Easy Connect, which uses the Device Provisioning Protocol (DPP).

Morse Micro provides schematics and software for the MM8108-RD09 and MM8108-RD17 reference designs to tier-1 customers through its sales team.

Morse Micro

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Semtech’s LR2022 and LR2012 LoRa Plus transceivers target a range of IoT deployments, from sub-GHz sensors to global multiband non-terrestrial networks (NTNs). The devices are subsets of the previously announced LR2021 and share its fourth-generation LoRa Plus IP core.

Both transceivers provide LoRa receiver sensitivity down to −141.5 dBm at SF12 with 125-kHz bandwidth and data rates up to 125 kbps for LoRa and 2 Mbps with FSK modulation. A single, switchless front-end design enables multiregion operation, while increased frequency offset tolerance improves performance across different frequency bands.

The dual-band LR2022 covers terrestrial sub-GHz, 2.4-GHz ISM, and NTN L and S bands and supports LoRaWAN, Bluetooth LE, and FSK-based legacy protocols. The sub-GHz-only LR2012 supports LoRaWAN, Wi-SUN, wireless M-Bus, and FSK-based proprietary protocols. Transmitter output power ranges from +22 dBm to −10 dBm in the sub-GHz band for both devices, while the LR2022 provides +12 dBm to −15 dBm in the 2.4-GHz band.

The LR2022 and LR2012 transceivers are now in production.

LR2022 product page

LR2012 product page

Semtech

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Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has begun mass production of its 100V integrated GaN power-stage IC family: EPC23108, EPC23109, EPC23110 and EPC23111...

Infineon Technologies AG of Munich, Germany is supplying silicon carbide (SiC) power semiconductors to renewable energy solutions provider Fox ESS Co Ltd of Wenzhou, China to enhance the efficiency of its residential energy storage systems (ESS). Leveraging Infineon’s CoolSiC MOSFETs 1200V G2 in the Q-DPAK package, Fox ESS has reduced switching losses by 70%. As a result, the company’s PQ3-Ultra energy storage system achieves a peak photovoltaic (PV) inverter efficiency of up to 98.78% in grid-tied operation and a peak battery charge/discharge efficiency of up to 98.47%...

Discover AirForce, a fabrication system from Hasso Plattner Institute that uses a single inflatable tube to build large animated structures, including an eight-meter robotic dinosaur you can assemble alone.

КПІ та Польща посилюють співпрацю у сфері безбар’єрності та ветеранської підтримки KPI4U-2 ср, 08/26/2026 - 18:00

Infineon Technologies is now supplying silicon carbide (SiC) power semiconductors to Fox ESS, a renewable energy solution provider, to enhance the efficiency of its residential energy storage systems (ESS). Leveraging Infineon’s CoolSiC MOSFETs 1200 V G2 in the Q-DPAK package, Fox ESS has reduced switching losses by 70%. As a result, the company’s PQ3-Ultra energy storage system achieves a peak photovoltaic (PV) inverter efficiency of up to 98.78% in grid-tied operation and a peak battery charge/discharge efficiency of up to 98.47%.

“With our SiC MOSFETs in the Q-DPAK package, we are enabling a new level of efficiency, thermal performance and design flexibility for residential energy storage systems,” said Amit Raut, Application Manager Photovoltaic and Residential ESS at Infineon. “Fox ESS is demonstrating how advanced SiC technology can translate into measurable system-level gains and support the broader adoption of clean energy solutions in homes worldwide.”

Compared with conventional bottom-side-cooled designs, the Q-DPAK package supports improved PCB layout, helping to reduce parasitic effects and stray inductance while enabling superior thermal management. Its compact footprint supports space-saving system designs, while compatibility with automated assembly simplifies cost-efficient, scalable manufacturing.

Silicon Carbide Technology for High-Performance Energy Storage Solutions

Within Fox ESS’s energy storage system, Infineon’s CoolSiC MOSFETs 1200 V G2 in the top-side-cooled Q-DPAK package deliver optimised thermal performance, system efficiency and power density. Infineon has specifically designed the devices for demanding applications requiring high performance and reliability. Featuring Infineon’s advanced .XT interconnection technology, they reduce thermal resistance and operating junction temperature, while the trench gate architecture helps lower switching losses.

“The collaboration with Infineon is a major pillar of our strategy to deliver high-performance energy storage solutions,” said Daniel Deng, R&D Director at Fox ESS. “Infineon’s CoolSiC technology offers superior efficiency and outstanding reliability, values that perfectly match our philosophy. By working together, we will further advance the performance of residential energy storage systems and accelerate the adoption of renewable energy.”

For its hybrid ESS solution combining the PQ-H3-Ultra-10.0 inverter with the EQ3300-5 battery, Fox ESS has achieved a System Performance Index (SPI) of 97.0 percent in a recent test by HTW Berlin University of Applied Sciences and AQUU Research. This ranks Fox ESS first in the 10-kW class among all hybrid inverter and storage systems tested in 2026 and marks the highest SPI score recorded since the evaluation was launched in 2018. Over the past three years, Fox ESS has installed more than 890,000 PV inverters and over one million batteries in more than 70 countries.

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Some folks prefer pushbutton switches to take effect on push instead of release. These buttons do that very thing.

I suppose it’s really just a matter of taste, but I’ve always liked momentary contact switches that act when you push them better than those that wait until you let go. It’s really an arbitrary thing, so I wouldn’t presume to criticize designs that choose the latter over the former, like this one from one of my favorite Design Idea contributors.

It’s not worse. Or better, for that matter. Just different. 

Wow the engineering world with your unique design: Design Ideas Submission Guide

In contrast to RJ’s design, Figure 1’s circuit implements my preferred method. It bumps DPOT U2’s setting by one count each time the UP button is pressed, and un-bumps it when DOWN is mashed.

Figure 1 This pushbutton-to-digital-potentiometer interface is optimal for impatient people.

Here’s how it works.

Pushing either button makes U1a’s pin 3 go high. Contact bounce is filtered out by R3C1’s ~5 ms time constant, and Schmidt trigger inverter U1d then delivers a single clean low-going transition to U2’s clock input. This makes U2’s wiper take one step up if its pin 2 is high (i.e., the UP button is pressed and DOWN isn’t) or one step down if  pin 2 is low (i.e., DOWN is down).

Other than that difference, there’s really no compelling reason to choose Figure 1 over RJ’s circuit. Figure 1’s parts count does include one fewer chip, but so what? They’re cheap.

But stay tuned for future developments that go-when-pushed makes possible, which might be more significant…

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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The post DPOT push up/down appeared first on EDN.

Cree LED Inc of Durham, NC, USA (a Penguin Solutions brand) and NanoLumens Inc of Peachtree Corners, GA, USA have entered into a mutually beneficial patent cross-license agreement that resolves a patent infringement dispute involving Cree LED’s patents related to LED components commonly used in LED displays...

– Anwesh Koley, Executive Editor, ELE Times

The government is serious about making India a global technology hub and how! After the visible success of the first phase of the India Semiconductor Mission, policy makers are walking the talk with the 2nd phase of the India Semiconductor Mission (ISM 2.0). In a move that could well be termed monumental, a staggering Rs 1,27,500 crore (around $13.25 billion) has been approved towards building an integrated semiconductor ecosystem across major Indian states.

The Indian semiconductor market is currently valued at around $45–$50 billion and is expected to expand to $100–$110 billion by 2030. At a time when India is working to strengthen its position in the global semiconductor supply chain, Semicon 2.0 is expected to provide a significant boost to India’s electronics and semiconductors industry. The emphasis of ISM 2.0 will be on deepening the country’s semiconductor and design ecosystem.

A Resilient Pursuit of Indigenous Capacity Expansion

What stands out is how Semicon 2.0 builds on the foundation laid by ISM 1.0. While the first phase focused on establishing India’s semiconductor base through ecosystem creation, ATMP/OSAT and early project execution, Semicon 2.0 is notably broader in scope – spanning chip design IP, equipment and materials, fabs, advanced packaging, R&D and talent development. While much of the conversation around chips has focused on fabrication plants, the latest developments indicate that India is building a broader ecosystem that includes packaging, testing, display manufacturing, and advanced materials.

Airing his views on phase 2 of the ISM, Amitesh Kumar Sinha, CEO, ISM, said, “As India’s semiconductor journey has already gathered momentum, the India Semiconductor Mission (ISM) has laid a strong foundation for semiconductor manufacturing in India, with 10 approved projects—including 2 fabs and 8 ATMP or OSAT units—attracting investments of around Rs 1.6 lakh crore. With ISM 2.0, the focus now shifts to deepening the value chain across materials, equipment, IP, and supply chain resilience.”

Harnessing Global Efficiencies

As India moves decisively from semiconductor policy to on-ground execution, ISM 2.0 provides a structured pathway to leverage the strengths of global partners in advanced manufacturing, supply chain integration, and design, while accelerating India’s capabilities across assembly, testing, packaging, the broader component ecosystem and overall Semiconductor ecosystem.

India sees strong potential for deeper participation from South Asian countries like Singapore across the value chain. “I would like to assure that ISM is all set to support any further investments in the sector. We are fully committed to facilitating and supporting such investments—ensuring a trusted, scalable, and globally competitive semiconductor ecosystem anchored in strong international partnerships,” affirmed Sinha.

As countries continue to diversify global chip supply chains, India’s semiconductor roadmap is increasingly viewed as a long-term manufacturing and strategic play rather than a short-term production target. India’s world-class engineering talent is a proven asset, and sustained R&D investments are expected to further elevate its position in the global supply chain.

What’s New in ISM 2.0

Finance Minister Nirmala Sitharaman announced ISM 2.0 in the Union Budget 2026, with an initial emphasis on design, equipment and materials. The announcement confirmed that Semicon 2.0 will broaden this framework further, encompassing design, machines and materials, fabs, the strengthening of ATMP/OSAT capabilities, research and development, and, significantly, talent development.

Indian Semiconductor Mission 1.0 focused on setting up basic chip making and packaging factories with a budget of Rs 76,000 crore. Taking this initiative a step further, Indian Semiconductor Mission 2.0 expands and strengthens the whole supply chain with a budget of Rs 1,27,500 crore. Indian Semiconductor Mission 1.0 made progress with 12 manufacturing units with investments over Rs 1.64 lakh crore. 24 Semiconductor design projects from startups have been approved for financial support while 105 startups have been granted access to EDA tools.

Under Indian Semiconductor Mission 2.0 government financial support is structured to deepen and strengthen the domestic value chain. For example, subsidies up to 40% on silicon fabrication plants and subsidies up to 35% on other fabrication plants. Semicon 2.0 is more diverse and deeper than ISM 1.0 because of the massive budget, focus on ​the semiconductor ecosystem, industry-led research and development centers and training programs, which lay the foundation for resilient supply chains and high value employment.

ISM 1.0 delivered approvals, investments, and early commercial production. Semicon 2.0 is aimed at deepening domestic capability across the value chain, from materials and equipment to advanced packaging, R&D, and skilled talent. If Semicon 1.0 was about proving that India can enter semiconductors, Semicon 2.0 is about proving that India can scale them.

The ISM (1.0 and 2.0) is critical for India Inc, because the growth of semiconductor supply and ecosystem is highly essential for India to build and grow its own microchip and semiconductor industry. This goes a long way in reducing foreign reliance, encouraging local and domestic industries, economic growth, employment, education, skill based teaching and national security. These foundational capabilities shield the country from global disruptions and foster sustainable, high value technical industries.

Key Components of Semicon 2.0

The Rs 127,500 crore initiative is a comprehensive push to build India’s semiconductor capabilities for the long term. Hailing this budgetary approval, Hitesh Garg, Vice President and India Managing Director, NXP Semiconductors, said, “As India progresses toward the vision of a “Viksit Bharat” by 2047, the Union Budget will be a critical lever in shaping the country’s medium- to long-term growth trajectory—particularly as global supply chains diversify and technology-led manufacturing becomes central to economic resilience and national competitiveness.”

Since ISM 1.0, the key focus has revolved around talent development, supply-chain readiness, access to raw materials, and long-term competitiveness against established semiconductor hubs. ISM 2.0 framework is expected to address some of these gaps by supporting equipment, chemicals, design ecosystems, and research capabilities. The key focus areas of Semiconductor 2.0 are broadly based on six pillars:

1) Design: The first pillar is based on chip design. Under phase 2, the aim is to develop designs of chips and systems and IPs. ISM 2.0 will focus on designing full stack Indian semiconductor intellectual property, and fortifying both domestic and global supply chains

2) Machines and Materials: Companies and Industries that are involved in the manufacturing process and research and development of machines, materials, chemicals that are essential for manufacturing semiconductors will be encouraged.

3) Setting up more fabrication plants: Efforts will be made to attract more manufacturers to come to India and set up fabrication plants to manufacture chips. Fabrication plants like silicon, compound semiconductor, display etc.

4) Strengthening the ATMP (Assembling, Testing, Marking and Packaging) industry: Setting up of ATMP/ OSAT units is encouraged for strengthening the semiconductor supply chain. Several approved proposals aim to leverage indigenous technologies for the assembly, testing, and packaging of semiconductor chips.

5) Research and Development: Research and Development of semiconductors is essential for advanced technological mechanisms to create better, faster electronic devices. The focus is on developing more advanced nodes and advanced technologies within and outside India.

6) Talent development: Talent development in semiconductors is the process of educating, training, and upskilling people to build a skilled workforce for chip design, manufacturing, testing, packaging, and research. With 315 universities training students using the latest EDA tools, about 68,000 students have already been trained.

“Government initiatives such as ISM 2.0 are a defining milestone in India’s journey toward global semiconductor leadership. By expanding support across the entire value chain from manufacturing and advanced packaging to critical materials and design, this initiative builds a foundation for long-term competitiveness,” Garg opined.

India Semiconductor Mission 2.0: Why it Stands Apart

By structuring Semicon 2.0 around six key pillars, the government has taken a holistic view of the industry. The clear roadmap that the sector’s future lays out is especially commendable. This is not merely about setting up a few fabs; it is about building the foundation for India’s semiconductor future over the coming years. While achieving this vision will require sustained effort, collaboration, investment, and strong industry-government partnership, the direction remains clear.

Airing his optimism for phase 2, Vinay Shenoy, MD, Infineon Technologies, India, said, “ISM 2.0 marks a decisive step in India’s journey from semiconductor consumer to semiconductor innovator. For Infineon, having invested in India’s ecosystem for over 25 years, this signals strong policy continuity and ambition. The enhanced focus reinforces our belief that India has the talent and capabilities to further strengthen its position as a global hub for chip innovation, particularly in areas driving decarbonization and digitalization.”

Policy Assurance

The government’s recent approvals, including projects in Gujarat, Odisha, Assam, and Uttar Pradesh, reflect a shift from policy announcements to infrastructure creation. Companies such as Tata Electronics, Micron, CG Power, and Kaynes Semicon are now part of a growing domestic semiconductor network that aims to reduce import dependence and strengthen India’s role in global electronics manufacturing.

NXP’s Garg further reiterated the semiconductor manufacturer’s commitment towards this massive capacity-building initiative. “At NXP, we are fully committed to this vision. We continue to advance cutting-edge R&D locally and nurture future-ready talent. We believe that collaborative ecosystem innovation is the key, and we look forward to partnering with industry, academia, and policymakers to drive India’s emergence as a global semiconductor hub.”

What makes this phase significant is the focus beyond just fabs. Advanced packaging technologies, display assembly, compound semiconductors, and supply-chain support systems are emerging as equally important areas. Industry observers believe this approach could help India gradually build capabilities in sectors linked to automotive electronics, telecom, AI hardware, and industrial devices.

Conclusion: A Robust Framework for India Semicon Inc

Through Semicon 2.0, India is demonstrating its readiness to emerge as a trusted and resilient partner in the global semiconductor value chain. The long-term policy support and substantial investment approved by the Cabinet underscore India’s determination to advance domestic capabilities and attract world-class semiconductor manufacturing to the country.

Semiconductor technology is at the heart of all critical technologies and India must catch up with the global leaders in this domain. Strategic strength and ability to lead development of new technologies, R&D and emerging areas of expertise cannot be achieved without electronics and semiconductors. ISM 2.0 is a timely move that will take us to the next level and deliver immense social and economic benefits for India.

This landmark announcement strengthens India’s backend semiconductor capabilities by enabling large-scale production of discrete chips tailored to high-growth sectors such as electric vehicles and industrial automation. Little wonder then, that as time progresses, India’s electronics and semiconductor ecosystem is steadily advancing towards becoming a self-reliant and globally competitive manufacturing hub.

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