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Cadence has added an agent for RTL generation to its ChipStack AI Super Agent platform for front-end silicon design and verification. The new agent extends ChipStack’s autonomous verification and debugging capabilities to PPA-driven spec-to-RTL generation, RTL analysis, and refinement—all from natural language prompts.

In early evaluations, the RTL Generation Agent delivers an average 24% reduction in area and 18% reduction in power versus pure foundation-model code generation, while producing 100% functionally accurate RTL. In addition to RTL creation, existing RTL can be updated based on new requirements. The upgrade flow applies AI automation to RTL revision, enabling customers to adapt legacy RTL to new architecture requirements, PPA targets, and functional requirements.

Early collaborations with Honda R&D demonstrate the use of these AI capabilities for PPA and productivity improvements on next-generation SoCs. Honda is evaluating the RTL Generation Agent on advanced automotive SoCs, where safety-critical requirements and tight power and cost constraints demand highly optimized RTL.

The expanded ChipStack AI Super Agent is expected to become available to select early-access customers in the fourth quarter of 2026.

Cadence

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Omnivision’s OAX7700 ultra-low-power ASIC is an always-on vision AI companion processor for vehicle security systems, supporting sensor resolutions up to 720p. An integrated neural processing unit (NPU) allows designers to develop custom algorithms for human presence detection, object classification, and distance measurement. The ASIC can upgrade existing exterior camera solutions, such as surround-view systems and edge AI-based parking surveillance systems.

In always-on mode, the camera continuously monitors the vehicle’s surroundings, consuming minimal power until an event triggers it to switch to normal mode. It records up to 10 seconds of pre-roll video that the ECU analyzes to validate the trigger before activating an alarm, if required. This helps the system avoid false triggers from wind, birds, or other non-threatening motion.

According to Omnivision, parking surveillance systems equipped with the OAX7700 ASIC consume 97% less power than existing solutions. The chip also reduces the processing burden on the central compute platform, enabling more efficient decision-making at the edge.

The OAX7700 integrates stacked PSRAM and flash memory in its 60-pin BGA package. Samples are available now, with production scheduled for the first quarter of 2027.

OAX7700 product page 

Omnivision

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Eggtronic has announced a 140-W USB-C Power Delivery (PD) 3.1 AC/DC reference design for notebook adapters and other USB-C powered devices. The evaluation board combines Eggtronic’s EPIC dual-controller chipset with Renesas’ TP70H150G4LSG 700-V, 150-mΩ SuperGaN FET, achieving 95.5% peak efficiency and more than 92% efficiency at light loads.

Unlike conventional USB-C adapters that rely on costly LLC, AHB, or ACF topologies, the EPIC-based design retains the simplicity and BOM cost of a QR flyback converter. The primary-side controller (EPIC2ACB04) manages both the active totem-pole PFC front end and QuarEgg ZVS flyback switching stage, while the secondary-side companion controller (EPIC2ACQ07) handles synchronous rectification, output-voltage regulation, and USB PD 3.1 protocol management.

Operating from a universal input of 90 VAC to 264 VAC, the system provides an output of up to 28 V at 5 A. It also features optoless digital isolation, replacing optocouplers and digital isolators with an integrated high-speed, ultra-low-latency digital feedback loop for improved transient response and reliability.

The 140-W USB-C PD 3.1 reference design is available now.

Eggtronic

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The Melexis MLX91224 and MLX91225 isolated Hall current sensors measure up to 100 ARMS in automotive and energy applications. Offered in three compact SOIC packages, each device integrates a current conductor, sensing element, signal conditioning, and galvanic isolation. This integration minimizes ohmic losses and simplifies designs for EV powertrains, DC/DC converters, chargers, and solar systems.

The integrated current path runs directly through the package’s low-impedance lead frame, while two sets of Hall plates differentially sense the magnetic flux generated by the current. Differential sensing minimizes disturbance from external magnetic fields and enables a high-speed linear analog output proportional to the measured current. Package-dependent isolation ratings allow working voltages up to 1640 VRMS.

Developed as an ISO 26262 ASIL B Safety Element out of Context (SEooC), the sensors support safety-related current measurement in high-voltage automotive systems. The MLX91224 is designed for 5-V systems, while the MLX91225 is designed for 3.3-V systems. Both devices offer AC and DC current measurement, bipolar or unipolar sensing, and ratiometric or fixed output configurations.

Engineering samples of the MLX91224 and MLX91225 are available in limited quantities.

Melexis

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Powered by BrainChip’s AKD1500 edge AI coprocessor, the AKD1500 PCIe development card enables developers to run models built with existing AI frameworks. The card plugs into a standard PCIe slot in a desktop, workstation, industrial PC, or single-board computer, providing access to the AKD1500’s self-learning capabilities for edge AI development.

The AKD1500 coprocessor chip uses the Akida neuromorphic processing engine to deliver up to 800 effective GOPS at <1 mW/GOP for low-power AI neural network acceleration. Its built-in capacity for on-device learning allows for secure application personalization without needing a cloud connection or extensive retraining.

The PCIe development card complements the AKD1500’s other deployment options, including an M.2 module, packaged and unpackaged silicon, and licensable IP. Developers can test their own models with streaming data on a PC, then deploy the validated models on AKD1500 hardware without modification.

Available through BrainChip’s online store, the AKD1500 PCIe development card is priced at $149.

AKD1500 PCIe product page

BrainChip Holdings 

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For decades, polyethylene naphthalate (PEN) held a small but critical place in high-performance capacitors. It was never the volume material that biaxially oriented polypropylene (BOPP) is, since cost and production capacity kept it niche. But capacitor engineers reached for PEN when BOPP ran out of room: when temperatures climbed, when packages had to shrink, or when a higher dielectric constant was the only way to hit the energy target.

Now capacitor-grade PEN is disappearing. Major suppliers are signaling PEN end-of-life, and capacitor manufacturers serving aerospace, defense, power grids, transportation, and industrial power electronics are asking what comes next.

It’s tempting to treat this as a sourcing problem. In other words, find a comparable dielectric, drop it into the existing capacitor, qualify it, and move on. But that instinct is wrong.

The product you build to replace a PEN capacitor should not be a like-for-like copy with a different dielectric inside. It should be a better capacitor, because major applications are pushing every power electronic component beyond legacy use, and capacitors desperately need to keep up.

Component under the most pressure

AI compute, data center buildout, and electrified transport have driven the most disruptive shift in power demand in generations. Forecasts are rewritten quarterly, interconnection queues are stacking up, and hyperscalers are standing up their own power generation to avoid the wait.

These trends converge on a single component. Capacitors are being asked to handle higher voltages, cycle faster, and survive more thermal stress for decades without drifting out of spec. When program teams walk through where a design holds up or starts to compromise, the conversation lands on the capacitor, its energy density, its footprint and mass, its thermal behavior, and how long it survives the duty cycle.

That conversation is happening earlier in the design cycle than it used to. The capacitor manufacturers responding to these demands earliest are the ones getting designed in.

What PEN capacitor actually did

PEN is at the end-of-life stage, and the capacitors that depend on it can’t just swap in a substitute film and move on. It did two different jobs, and they belong to two different capacitors.

In aerospace pulse power, hardened defense systems, and directed-energy applications, PEN was a high-voltage, energy-dense enabler for rapid discharge. It let designers pack more energy into a smaller capacitor at a given voltage rating.

In EV power electronics, grid subsystems, and rail traction, PEN was chosen not for peak energy density, but for its ability to sustain intense duty cycles and thermal stress, often with a DC bias. A capacitor that functions without derating under all use-scenarios is invaluable to final product design.

Treating those as one problem is what makes PEN replacement feel impossible. It attempts to solve two separate capacitor-design problems, energy density under pulse and thermal stability under load, which should lead to separate design answers.

HDC: Rebuilding the energy-dense capacitor

The first job, exemplified by uses in aerospace, pulse power, hardened defense systems, and fusion, gets picked up by a different class of material entirely. Where PEN was used to shrink a capacitor and push its energy density, the successor is a high dielectric constant (HDC) material, which changes what the capacitor can do, not just what is wound inside it.

Film developers have begun introducing nanolayered metamaterial dielectrics, built from hundreds to thousands of alternating polymer layers, with dielectric constants in the 3.7 to 4.7 range, well above BOPP and many PEN grades, and breakdown strengths of 790 to 820 V/µm. In a finished part, that can mean up to 4× the energy storage in as little as half the footprint of a conventional film capacitor, with improved thermal stability and longer operational life. For a pulse module, a Marx bank, or a grid capacitor competing for volume and mass, is a smaller, lighter, more robust component, not just a spec-sheet footnote.

The trade-off is real and worth stating plainly to a design audience: HDC carries a higher dissipation factor than the lowest-loss dielectrics, so more energy shows up as heat. That constrains how fast and how often the capacitor can be cycled, which is why HDC belongs in energy-density and pulse-duty capacitors—defense pulse modules, mass-constrained aerospace systems, fusion driver banks, and intermittent-duty transportation electronics—rather than continuous switching.

LDF: A lower loss and faster switching capacitor

For the other PEN job—continuous cycling at high repetition rate over decades—the answer is a low dissipation factor (LDF) dielectric, which trades some energy density for very low loss and long thermal endurance in grid inverters, FACTS devices, and industrial drives. This lower dissipation factor means there is less self-heating, greater efficiency of energy transfer, and less stress on components, leading to more reliable and longer lifetimes.

PEN also functions at environmental temperatures above traditional BOPP but below far more expensive alternatives. Due to nanolayering, LDF can incorporate stabilizing layers, which ensure enhanced functionality rivaling PEN, while reducing thermal expansion and device derating. This results in finished capacitors that can be used in hotter or high energy environments without massively increasing component cost.

What capacitor manufacturers should do

PEN’s disappearance marks an inflection point. The capacitor architecture chosen now gets locked in for the life of the platform—30 years or more on the grid and in aerospace. Four moves separate the winners.

1. Stop hunting for a one-to-one PEN part

There is no universal replacement capacitor. Segment the installed PEN base by what each capacitor was actually doing—energy density and volume route to HDC, lifetime and efficiency route to LDF—and qualify against that. The segmentation work up-front is what accelerates qualification.

2. Design the capacitor for the duty cycle, not the datasheet

AI data centers, EV powertrains, fusion supplies, and grid assets load capacitors differently. A manufacturer who can build to more than one duty cycle expands its addressable market; one who can serve only a single profile gets squeezed.

3. Treat heat as a capacitor-and-system problem

HDC trades efficiency for energy density, and that only works if the surrounding power electronics remove the heat. Pair capacitor selection with explicit thermal models and validated test data, and qualifications go faster with fewer field failures.

4. Make provenance part of the product

More than 70% of conventional capacitor film originates in China. Buyers hardening the grid, defense platforms, and AI infrastructure are increasingly unwilling to carry that concentration risk. A documented U.S. or allied-nation supply chain is a procurement advantage, and it drops into standard metallizing and winding lines, so qualifying it does not require retooling.

First to qualify, first to win

Those four moves take time to execute, and time is the one input nobody can manufacture more of. Capacitor qualification takes 12 to 24 months. The clock is already running. The manufacturers who commit now to the right capacitor, not the cheapest lookalike, get designed into a decade of rising power demand. Those who requalify a copy of the PEN part will spend that decade watching competitors take the design wins.

Alec Laws is senior product manager for dielectric films at Peak Nano.

Related Content

• Trends in capacitors
• Capacitor matchmaker
• Getting Familiar with Capacitors
• Selecting and Applying Film Capacitors
• Film capacitors: Characteristics and uses in power applications

The post With PEN nearing end-of-life, capacitors built on it must change appeared first on EDN.

This versatile Design Idea survives and reports open- and short-circuits, not to mention multiplying efficiencies.

Generally accepted tech folklore says that after you drive relays and solenoids into full actuation, only half as much coil voltage and current—and therefore only a fourth as much power—is needed to hold them there. Consequently, driver designs that continuously apply full voltage burn four times the power and heat the coil four times hotter than the job really requires.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1’s driver circuit employs pulse width modulation (PWM) to dramatically diminish post-pull-in power waste. As an extra added bonus, it also survives and reports open- and short-circuit faults on the GPI status bit.

Figure 1 In this circuit, driver transistor Q2’s PWM duty cycle varies from 100% at actuation to a power saving 50% sustain. It can accommodate load currents up to half an amp. R5 protects current limiter Q3’s base-emitter junction from destruction by over-current events. And Q1 detects coil opens and shorts.

Here’s how it works.

The PWM signal on the general-purpose output (GPO) bit sets Q2’s conduction duty cycle from 0% to 100% to ~50%, from off to full voltage pull-in to quarter-power sustain. Q3 protects Q1 from over-current resulting from shorted coil faults. And Q1 utilizes relay/solenoid coil L1’s inductive “kickback” to detect correct driver operation and report it as a logic “1” on the general purpose input (GPI) pin…or, if kickback is absent (meaning the coil is open or shorted), its logical opposite, “0”.

Figure 2 not-to-scale sketches the driver timing.

Figure 2 In this timing diagram, T1 = timeout to first fault check = L1/R timeconstant = ~500us. T2 = ~100% PWM duty cycle to power initial actuation = ~10ms. T3 = ~50% sustain duty cycle for as long as application requires. And T4 = PWM sustain cycle = ~100us = 10kHz.

In summary, Figure 1’s circuit neither squanders power nor requires changing component values to accommodate different supply voltages. And it’s simple. Along with, dare I say, beautiful? I guess I just did!

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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It wasn’t that long ago that space-rated components were special in every possible sense. They had to be ordered via a different process well in advance of fabrication, manufactured to order, undergo the additional tests to qualify them, and more.

Most of the attention of spaced-rated component vendors was on larger ICs such as processors, FPGAs, communication components, and similar. Basic analog ICs were not on that list of potentially available space-rated devices.

Yet designers know that a viable functioning system requires more than those larger ICs. It also takes the small-to-medium analog ICs serving in mundane yet vital roles such as basic current amplifiers, level sifting, and temperature sensing to complete a design.

But times have changed. The listing of these basic-function analog ICs as standard items means that design uncertainty is reduced along with time to project completion and cost. It’s part of the mainstreaming of space satellites, with the proliferation of low-Earth orbit (LEO) and medium-Earth orbit (MEO) vehicles in unit volumes that were unimaginable just a decade or so ago. Both amateur satellite designers (such as CubeSat) and commercial operations are beneficiaries of space-rated standard catalog parts.

One of the key enablers of space-rated components was the 2024 release of QML Class P, a qualification standard for radiation-hardened plastic-encapsulated ICs used in space applications. It extends MIL-PRF-38535 specifications via SAE standard AS6294 to provide a reliable plastic alternative to traditional ceramic packaging.

Engineers designing small satellites for LEO missions with shorter mission durations and lower-cost targets have begun to use commercial-off-the-shelf (COTS) ICs, which receive no special screening from manufacturers to address the hazards of spaceflight. But these are a limited subset of the broader picture in satellite designs.

As evidence of the increase in these space-rated basic-analog ICs, one example comes from Texas Instruments, who introduced three very different ICs with these ratings in the past few months. Radiation-hardened performance for each is spelled out in detail in their respective comprehensive datasheets, including total ionizing dose (TID) and single-event effects (SEE), with the latter for both single event latch-up (SEL) and single event transient (SET) occurrences.

• INA951-SEP is a current-sense amplifier that can measure voltage drops across shunt resistors over a wide common-mode range from –4 V to 80 V (Figure 1). The negative common-mode voltage allows the device to operate below ground, thus accommodating precise measurement of recirculating currents in half-bridge applications.

Figure 1 The current-sense amplifier is a widely used arrangement; it’s based on measuring the voltage across a known sense resistor. Source: Texas Instruments

• TRF0108-SP is a radiation-hardness-assured, differential to single-ended (D2S) RF amplifier for near-DC to 12 GHz use (Figure 2).

Figure 2 TRF0108-SP performs the simple yet essential function of translating differential DAC output signals between near-DC and 12 GHz into a single-ended signal compatible with a power amplifier (PA). Source: Texas Instruments

A common application for this device is as a buffer amplifier for an RF DAC that has differential outputs. In many conventional designs, passive baluns are used to interface differential amplifier outputs with single-ended RF DACs. TRF0108-SP replaces these bulky and expensive passive baluns while offering excellent gain and phase imbalance, as well as input and output return loss.

• Finally, there’s temperature. It’s a rare system of any sort (whether space-related or not) that doesn’t need temperature sensing across multiple points, either for its native functionality or to monitor operating conditions independent of that functionality. That’s where the TMP9R01-SP high-accuracy remote and local temperature sensor has its place (Figure 3).

Figure 3 The TMP9R01-SP high-accuracy temperature sensor reads and digitizes the temperature of its internal sensor as well as up to nine bus-linked remote sensors. Source: Texas Instruments

The device measures remote temperature (–64°C to 191°C range and ±1.5°C maximum error) by forcing a bias current through an external BJT or the integrated diode/junction of an FPGA, ADC, or ASIC, digitizing the resulting ΔVBE and reporting temperature with 0.0625⁰C resolution. An additional on-chip sensor provides local temperature measurement (±2.0⁰C maximum error).

Of course, the push for standard-catalog space-rated ICs is not just from one vendor. Others, such as Microchip Technology, have a long list of such ICs in their catalogs; while many are higher-level components such as processors and FPGAs, a large number are analog and power devices.

“Volume production” has a different meaning for spacecraft

Until the relatively recent proliferation of LEO and MEO satellites, a satellite was individually designed and tested, with no two exactly alike. Certainly, there were cases where subsections were reused in subsequent craft, but each satellite was largely unique.

Interestingly, there is one dramatic exception to this uniqueness dating way back, although it’s a small one. Identical twins Voyager 1 (launched September 5, 1977) and Voyager 2 (August 20, 1977) were built by NASA on an accelerated schedule, as they had a very tight launch window (Figure 4); see Voyager: Seeking Newer Worlds in the Third Great Age of Discovery.

Figure 4 The twin Voyager spacecraft were designed and built on an extremely tight schedule with no room for launch delay, and were optimized for long-term, scientific investigation missions. They are both still traveling and functioning, but with diminished resources, after nearly 50 years in the harshness of space. Source: NASA

That launch timing was super-critical to take advantage of an upcoming and very rare “grand alignment” of Jupiter, Saturn, Uranus, and Neptune. The Voyagers could fly by these planets using gravitational “slingshots” after their initial powered launch and boost phases.

Amazingly, they are both still functioning with greatly reduced capabilities after nearly 50 years in space, well beyond their planned ten-year mission, and have left our heliosphere and entered interstellar space. I haven’t been able to find out how the designers were able to use “ancient” components to create spacecraft that could survive the intense radiation of deep space; none of the documentation I have seen discusses that consideration.

There are other moderate-volume production examples from the past: the original Iridium satellite system (launched from 1987 to 1998) for worldwide voice-call connectively, which we now take as “no big deal”. It was a system using 66 MEO satellites (see “Eccentric Orbits: The Iridium Story”).

Once the premise of the concept was accepted, Iridium built the needed satellites and some spares in two batches, with all units in each batch identical. This allowed them to schedule parts procurement, assembly, test, and delivery in a very different way than the one-off approach that had been previously used.

Now we have GPS and GNSS with their hundreds of satellites, and the Starlink internet service with its thousands. Space-based systems and the need for space-rated components have clearly transitioned from single-unit designs to moderate volumes. While the numbers are orders of magnitude lower than for a mass-market consumer product such as a smartphone, it is still a meaningful shift.

We are in the beneficial “positive feedback” loop where demand for standard space-rated basic analog components is driving availability while such availability, in turn, is driving demand and opening new opportunities. We’ve seen this pattern many times in high-technology products and we’ll undoubtedly see it again.

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

Related Content

• Choosing power supply components for New Space
• Voyagers 1 and 2: Forty Years and Still Going (Even If Not So Strong)
• The Convergence of Traditional and New Space Electronics Solutions
• A brief history of electronic reliability in space—including today’s risks and how to mitigate them

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Using the concept and leveraging the example circuits in this Design Idea, you can divide any frequency by any number divisible by 2.

Any dividend frequency can be divided by any number representable by 2n, resulting in a square wave output quotient with a 50% duty cycle, using binary counters. Unfortunately, this capability is not more broadly applicable to other divisor numbers, at least directly. I had a requirement to do frequency division of a square wave signal by 10, resulting in a 50% duty cycle output, for use in a PLL (phase lock loop) based project. This objective is not directly achievable by any IC I’m aware of.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Hence, I came up with the circuit shown in Figure 1. Here, the input frequency is first divided by 5 and then by 2, resulting in a 50% duty cycle waveform. Using this idea, you can divide any frequency by any number which itself is divisible by 2. For example, extending the concept, the circuit in Figure 2 divides by 48, again with a 50% duty cycle output. The first stage divides by 24, and the second stage divides by 2.

Figure 1 This circuit divides the input frequency by 10. The output is a 2.4 kHz square wave with a 50% duty cycle. The ICs’ power supply and ground pins are not shown. For division by other numbers, change the DIP switch (DSW1) setting: OFF=1, ON=0.

How does Figure 1’s circuit work? U1 is a 12-stage counter. The input square wave is connected to U1’s CLK input. U2 is a 4-bit digital comparator. It has 4 inputs (A0 to A3), along with another 4 inputs (B0 to B3) for comparison purposes. It also has 3 more cascading inputs (A>B, A=B, A>B). U2 is wired for divide-by-5 by setting the DIP switch to value 0101. And its cascading inputs are wired per the 4585 datasheet (PDF).

U2’s QA=B output goes HIGH after every 5th count of U1. It increments U3 and simultaneously resets U1, which restarts counting from zero. The U2 QA=B output is divided by 2 by U3; U3’s Q0 output ends up being the input frequency divided by 10, with a 50% duty cycle. Since U2 is a 4-bit comparator, this circuit can be used for frequency division by any number(N) up to 24, prior to final division by 2. Set the DIP switch accordingly for N (OFF=1, ON=0). The total division is by 2N. Hence,  Figure 1 is a circuit that divides an input frequency by N, where N is conveniently settable by a DIP switch.

Figure 2 This circuit divides the input frequency by 48. The output is a 1 kHz square wave with a 50% duty cycle. It uses two 4585 comparators (U2 and U4) connected in cascade. Again, the ICs’ power supply and ground pins are not shown. The same circuit can also be used for division by other numbers (see the text for more information).

How does Figure 2’s circuit work? As previously noted, it’s just an extension of the one in Figure 1, in this case dividing the input frequency by 48. It first divides by 24 and then by 2. The binary representation of 24 is 00011000. To accommodate the design objective, a second 4585 comparator U4 is added, cascading with U2. U2’s A0 to A3 inputs, along with A0 of U4, are connected to U1’s Q0 to Q4 outputs. And U4’s B0, along with U2’s B0 to B3, are hardwired as 11000 (24).

No DIP switch is included this time, although one may be added if necessary for further design flexibility. The cascading outputs and inputs are again connected as per the 4585 IC datasheet. U4’s Q4=B output is connected to the clock input of U3 and to MR of U1. Hence, counter U1 counts up to 24 and then resets to start from zero. U3’s CLK input is therefore one per 24 pulses, and is further divided by 2. The resultant U3 Q0 output is the input frequency divided by 48, with a 50% duty cycle.

The circuit in Figure 2 can be used to initially divide by any number up to 28, and then by 2 in the next stage. To accomplish this objective,connect Q4, Q5, Q6 and Q7 of U1 to A0, A1, A2 and A3 of U4. Set the divisor in binary by appropriately connecting B0, B1, B2 and B3 of U2 and B0, B1, B2 and B3 of U4 to either “1” or “0” (VDD or VSS). And the idea can be further extended for division by any number by suitably selecting counters and the number of cascaded 4585 comparators.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

• Injection locking acts as a frequency divider and improves oscillator performance
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The post Frequency division by any number, with a 50% duty cycle output appeared first on EDN.

A new microcontroller family boosts real-time control performance for power and motor applications through higher control-loop frequency, accuracy, and system efficiency. This enables the MCUs to meet the needs of applications that require precise, high-speed control for power conversion, including AI server PSUs, EV charging systems, high-end motor control, solar, and switched-mode power supply (SMPS).

Infineon’s PSOC Control C3 Performance Line is based on Arm Cortex-M33 dual-core architecture operating at up to 200 MHz. These MCUs—featuring a programmable power control accelerator (PPCA) hardware accelerator—offer zero-wait-state access to analog and digital peripherals to enable high-performance systems to respond to real-time events with minimal delay.

Figure 1 The new MCU family mainly targets motor control and power conversion applications. Source: Infineon

The PSOC Control C3 MCUs are also wide-bandgap (WBG)-ready with fast, precise analog processing and digital control to improve control-loop accuracy and system efficiency. They support systems designed with WBG switches while achieving best-in-class control loop frequencies, accuracy, and efficiency for applications such as data centers, telecom, solar, and EV charging systems.

“The family is designed for digital control applications that need higher switching frequencies while providing precision, security, and maximum system efficiency,” said Steve Tateosian, senior VP and GM of IoT, consumer, and industrial MCUs at Infineon Technologies.

“As the industry shifts from analog to digital control for power conversion and motor control applications, the PSOC Control C3 Performance Line meets these needs for increased performance, system flexibility, security, and scalability without increasing the footprint,” he added. Tateosian also noted that the MCUs provide high functional integration for multi-output power supplies and low standby power for battery-powered applications.

Figure 2 The new real-time control MCUs are scalable in terms of features, packages, pinouts, memory, and performance. Source: Infineon

Security is also a key tenant of these control MCUs for power conversion and motor control applications. The MCUs are compliant with post-quantum cryptography (PQC) requirements for firmware protection outlined in the Commercial National Security Algorithm (CNSA) Suite 2.0.

The CNSA 2.0-compatible MCUs include SHA-512 and LMS firmware verification for secure boot and firmware update verification. These MCUs also support Platform Security Architecture (PSA) Level 3 enablement.

These real-time control MCUs are supported by the ModusToolbox Power Suite and Motor Suite GUI. These unified software and ecosystem platforms aid developers with dedicated tools and advanced libraries.

Samples of the PSOC Control C3 Performance Line MCUs with PQC compliance are available now.

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• The PQC Silicon Is Here Today for Tomorrow’s Quantum Threats

The post MCUs for power conversion and motor control feature PQC appeared first on EDN.

This initial entry in a planned dissection series analyzes the insides of a long distance-capable fiber optic cable networking adapter containing a focused-beam laser.

Last week’s tutorial, the conceptual kickoff to the teardown coverage cadence that begins today, provided what I hoped was a concise but comprehensive tutorial into the diversity of implementation options available with small form-factor pluggable (SFP) modules. Today’s premier patient, as mentioned last week, is a 10 Gbit LX SFP+ module. Specifically, it’s TP-Link’s TL-SM311LS, a member of the company’s business-tailored Omada product line.

Does X mark the multi-cable spot, or not?

Two things particularly interest me in perusing the TL-SM311LS product page. First off, the company refers to it there not as a SFP module but as a “Mini GBIC Module”, using the less common alternative naming convention that I’d noted upfront in last week’s coverage.

Secondly, it’s an “LX” module, with the “L” referencing long range transmission capabilities, specifically in this case specified as up to 20 km (~12.5 miles). The “X” typically references a module that’s usable with both single-mode and multimode cable, albeit at differing max transmission distances and, in both mode cable cases, at a common 1310 nm wavelength. However, TP-Link only documents the SM311LS as usable with 9/125 μm single-mode fiber cable, a seeming characteristic of the alternative “LR” module designator.

I sourced the SM311LS from the Resale (formerly Warehouse) section of Amazon’s website, where it set me back $16.99, versus a $19.99 MSRP. Here’s how it arrived, within a generic cardboard shipping box, and as usual accompanied in the following photos by a 0.75′′/19.1 mm diameter U.S. penny for size comparison purposes.

And here’s our patient, with dimensions of 2.1×0.5×0.5 (55.4×13.7×12.9 mm), after freeing it from its Styrofoam and antistatic bag sarcophagus. Top.

Right side (with “right” referencing its orientation when inserted in a network switch or other gear’s SFP port).

Bottom.

And left side.

The double-sided 20-contact (10 per side) connector is on one end.

The other end begs for a bit more explanation.

Removing the dust cap exposes to view the fiber optic connector mate sites, from two perspectives: first right-side-up and then upside down.

How do you tell which is the transmit one, and which is for data reception? One way is to look at the directions of the two arrows at far left in the earlier top side shot. And what’s with the blue-color lever beyond them? For that, we’ll need to revisit the earlier bottom side shot.

Tab-restrained removal, and internal access

See that tiny tab sticking out of the bottom, to the left of the product label? It’s spring-loaded, temporarily retracting flush with the bottom edge during module insertion and returning to its original position once the module is in place (thereby also locking the module in place). The other means of retracting it, thus enabling module removal, is to move the lever midway through its arc, halfway between the two positions shown in the dust-cap-installed and -removed photos.

And speaking of tabs, did you already notice the tiny ones halfway down both sides in the earlier shots? They’re our pathway inside. Use a small-but-solid “poker” of some sort to pull them back out, and you can then slide the outer chassis away from the interior assembly.

Turning the PCB right-side up again caused the black plastic piece normally covering the fiber optic cable female connectors (and visible in the previous photos) to fall away.

Here’s the underside of the PCB again, standalone and with that plastic piece temporarily back in place.

Now with all supplemental pieces removed, revealing the details of their bottom-pin retraction function operation.

The right side again, this time absent the outer enclosure and other extra bits.

And the left side, upside-down compared to its normal-operation orientation.

One more screw to go.

And the PCB is finally free.

I’ll start with the simple stuff: the SFP and fiber optics connector ends.

Frickin’ laser beams

Potentially obscure reference

Let’s next revisit the PCB underside, now free of its metal surroundings.

The orange-color assemblage at far left is the fiber optic receiver. Below it is the chrome-color laser transmitter. And the ICs to their right? The larger eight-lead one, in a TSOP-1 package, is the GT24C08A-2ZLI, an 8K-bit serial I²C EEPROM from Chinese supplier Giantec Semiconductor. Third-party SFP modules typically use memory such as this to, among other things, “spoof” networking equipment that would normally accept only same-name-brand (translation: expensive) SFP modules.

Remember my last-week comments about how single-mode technology has dramatically dropped in price in recent years, thanks in no small part to the “availability of non-proprietary, widely compatible modules”? Here’s a case study example. And the smaller six-lead IC below and to its right? If I’m right and the PCB mark next to it is “Q1”, then it’s likely a dual-transistor device.

But the “371H” mark on top, which I’m guessing is a date code or lot trace code versus an actual product code, isn’t helpful from an identity-sleuthing standpoint, at least to me. Reader assistance here is as-always appreciated.

I’d wondered, after first seeing all these ICs (and particularly before realizing that the larger one was “only” a nonvolatile memory), why they were on the PCB underside, as I’d assumed they were heat sources. Then I saw the PCB topside for the first time and instantly realized why.

The far more sizeable, albeit sole, device on this side, packaged in a 28-lead QFN and marked “3320C” on the top line, is the Uxfastic UX3320, a G/EPON ONU fiber transceiver developed by another Chinese manufacturer, Xiamen UX High-Speed IC. Presumably, given the lack of other logic anywhere on the PCB, it has integrated SFP interface capabilities.

To that point, and in closing, keep in mind that what we’re looking at today is a conventional (and legacy?) 1 Gbps SFP module. Recall from the “laundry list” in last week’s post that I also have a number of both higher-bitrate SFP and SFP+ modules in my teardown queue, and even a QSFP+ version, along with multimode modules to contrast against this and other single-mode offerings. I don’t know about you, but I’m intrigued to learn not only about each of them in an absolute sense but also relatively speaking, in comparing (including contrasting) them against each other.

With that “teaser” now out there, I’ll close for today. Please let me know your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

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• TP-Link MC220L: Media conversion keeps the network well
• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• Design considerations in high-speed fiber networks

The post SFP: The single-mode module autopsy appeared first on EDN.

Power that looks perfect can still betray you. Hidden distortions in the mains lurk behind flawless root mean square (RMS) readings—waiting to trip up even the best‑designed systems.

You’ve built the device exactly to spec, tested it in the lab, and watched it run flawlessly—only to have it mysteriously reset, flicker, or fail once deployed in the field. The nightmare begins when your trusty digital multimeter (DMM) or scope insists the mains are rock‑solid at nominal RMS, lulling you into false confidence.

In reality, hidden sags, swells, harmonics, and transients are wreaking havoc beneath that “perfect” reading. This is where a power quality analyzer (PQA) steps in—the engineer’s ultimate diagnostic lens for uncovering the real-world anomalies that standard tools simply cannot see.

An oscilloscope is the sprinter—built for speed, capturing fleeting microsecond transients in a narrow time window. It’s invaluable for spotting fast spikes but blind to the bigger picture.

A power quality analyzer (PQA), on the other hand, is the marathon runner—continuously logging over hours or days, aggregating long-term trends, tracking intense inrush currents during equipment startup, and checking compliance against standards like IEEE 519. Where the scope gives you snapshots, the PQA delivers the full story of your mains health.

Scopes give you snapshots, DMMs give you averages, but PQAs give you the truth—continuous visibility into harmonics, sags, swells, and transients that silently sabotage systems. If you want to design for the real world, you need to see the grid as it really is: noisy, imperfect, and unpredictable.

Figure 1 The PQ3198 power quality analyzer kit integrates specialized current clamps and voltage leads to capture and analyze transient grid anomalies. Source: Hioki

The rogue’s gallery of power quality villains

Three hidden villains—harmonics, sags and swells, and transients—quietly sabotage “perfect” power until a PQA exposes them.

• Harmonics – the waveform polluters: Nonlinear loads such as switching supplies, LED drivers, and variable frequency drives (VFDs) gulp current in pulses instead of smooth sine waves. Those pulses spawn integer multiples of the fundamental 50 Hz/60 Hz frequency. To quantify this mess, engineers look beyond total harmonic distortion (THD) to total demand distortion (TDD), preventing misleading percentage readings when equipment runs at light loads. In practice, “Triplen” harmonics—specifically the odd multiples of the third (3rd, 9th, 15th, etc.)—pile up in the neutral conductor, driving overheating, high crest factors, and insulation breakdown that can cripple systems.
• Sags and swells – the voltage rollercoaster: Large inductive loads like motors or HVAC compressors can drag voltage down to 85% of nominal, enough to brown‑out a microcontroller in an instant. On the flip side, when heavy loads shed or phases drift out of balance, the line can swell, stressing insulation and sensitive electronics. These rollercoaster swings slip past a DMM but are tracked relentlessly by a PQA.
• Transients – the semiconductor killers: Lightning strikes, capacitor bank switching, or routine grid events can unleash sub‑microsecond, high‑energy impulses. These spikes punch straight through ESD diodes and input protection, leaving semiconductors scarred or destroyed. A PQA captures these assassins in action, providing the context that scopes alone often miss.

Visual interpretation: The phasor diagram

One of the most practical screens on a PQA is the phasor display—a live map of voltage and current vectors that instantly reveals system health. A balanced three-phase system shows vectors neatly spaced at 120° with equal lengths, but any angular deviation or unequal magnitudes signal phase imbalance, a silent motor killer that drives counter-torque and winding stress.

Equally important is the power factor: the angular gap between voltage and current vectors tells the story of displacement power factor (DPF), with lagging angles exposing inductive loads and leading angles flagging capacitive behaviour. However, because modern switching supplies also introduce distortion power factor via harmonic wave shaping, a PQA is vital to calculate the true power factor—ensuring you aren’t paying penalties for hidden inefficiencies that standard meters completely miss.

Figure 2 A PQA plots three-phase voltage and current relationships on a central phasor diagram to analyze phase angles, magnitudes, and power quality metrics. Source: Neo Messtechnik

Two sidenotes

First, while engineers often use these terms interchangeably when looking at a PQA screen, there is a distinct technical difference: a vector diagram maps static, space-dependent quantities with a magnitude and a fixed directional orientation (like mechanical force or magnetic fields), whereas a phasor diagram is a frozen snapshot of a constantly rotating, time-dependent AC waveform.

Because all three phases in a stable grid spin at the exact same frequency, “stopping the clock” allows the PQA to display their angular relationships cleanly on a 2D plane. In short, all phasors can be mathematically treated and plotted as 2D vectors on a screen, but if it represents a repeating, alternating AC waveform, it’s technically a phasor.

Second, while traditional PQAs capture localized, steady-state anomalies, phasor measurement units (PMUs) provide real-time, wide-area situational awareness across modern power grids. By utilizing GPS time-synchronization, PMUs measure electrical waves across geographically disparate locations simultaneously.

They sample voltage and current waveforms at high speeds—typically 30 to 120 observations per second—to deliver time-stamped synchrophasor data. This precision tracking of phase angles and magnitudes allows grid operators to detect dynamic instabilities, monitor wide-area power oscillations, and prevent wide-scale blackouts in increasingly complex, renewable-heavy distribution networks.

Beyond the basics: Today’s PQA landscape

Modern PQAs go far beyond the fundamentals. They’re now Class A certified under IEC 61000‑4‑30 Edition 3, tuned to detect supraharmonics in the 2–150 kHz band from EV chargers, solar inverters, and LED drivers. They are capable of microsecond‑level transient capture with sampling rates approaching 1 MHz.

A sidenote on supraharmonics – the new phantom: Classic harmonics stop at the 50th or 63rd order, but these higher‑frequency disturbances don’t just stress wiring—they interfere with IoT devices, smart meters, and communication systems, making them a new frontier for power quality monitoring.

Take a real‑world example. During EV charger rollouts in several European cities, utilities discovered that chargers injecting switching noise around 20–25 kHz were confusing smart meters. The supraharmonic interference overlapped with PLC communication bands, causing meters to misreport consumption data and triggering billing errors. PQAs tuned for the 2–150 kHz band exposed the culprit, proving that supraharmonics aren’t just abstract lab phenomena—they can directly disrupt grid intelligence and customer trust.

At the same time, IEEE 519‑2022 has tightened harmonic distortion limits at the point of common coupling, reflecting today’s nonlinear load environment and ensuring compliance reporting is more rigorous than ever. With cloud dashboards, automated reporting, and integration into data centres, renewable systems, and utility grids, PQAs have become essential tools for navigating a world where distributed energy resources make power quality more unpredictable than ever.

Building a DIY power quality analyzer

Building a DIY PQA is an incredibly rewarding, multi-disciplinary challenge that bridges the gap between embedded design, real-time digital signal processing (DSP), and high-voltage safety. To accurately capture complex multi-channel dynamics—such as system unbalance, triplen harmonics, and ground faults—a scratch-built approach demands an agile microcontroller like the dual-core ESP32 sampling at upward of 10 kHz per channel to perform continuous Fast Fourier Transforms (FFTs) up to the 50th harmonic.

While developers looking to deploy high-speed, multi-channel discrete ADCs (such as the ADS131M08) can achieve synchronous sampling across all inputs without phase skew, those wanting to offload the heavy math entirely can leverage a specialized polyphase metering IC like the Analog Devices ADE7880.

ADE7880 utilizes an on-chip, hardware-isolated adaptive real-time monitoring (ARTM) harmonic engine to automatically track fundamental frequency drift and calculate full THD+N over SPI. No matter the architectural route, strict implementation of galvanic isolation via components like the ZMPT101B voltage transformer is non-negotiable to protect downstream hardware, and firmware must be thoroughly vetted using low-voltage AC-AC step-down transformers before introducing the system to live, lethal mains environments.

Figure 3. Simplified block diagram of ADS131M08 reveals a fully integrated, 8-channel signal chain architecture featuring independent PGAs, ΔΣADCs, digital filtering, and dedicated calibration blocks feeding into a centralized control interface. Source: Texas Instruments

Designing for the real world means accepting that the grid is noisy, unpredictable, and far from perfect. Hidden distortions, imbalances, and transients are not exceptions; they’re the rule. A PQA equips engineers to see beyond the illusion of “perfect power” and design systems that survive in the wild.

So, here’s the challenge: What’s the weirdest power‑quality phantom you’ve ever had to hunt down in the field? Share your story in the comments—because every anomaly teaches us something new about resilience.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Power System Harmonic Analysis using ETAP
• Distortion in power amplifiers: the input stage
• Distortion in power amplifiers: the sources of distortion
• Signal integrity and power integrity analysis in 3D IC design
• Highly integrated approach to power system design in the AI era

The post Unmasking the ghosts in your grid with power quality analyzers appeared first on EDN.

Chime in with your suggestions in the comments. We’ll even allow the mechanical engineers out there to participate. Well…maybe.

The following are a few of the tips, advice, rules, or guiding principles, I’ve discovered after many years of engineering and in various engineering positions. I’m not an expert in engineering management; this list is just items I’ve discovered from being in the engineering trenches (or should I say, cubes).

Do you have a memorable experience solving an engineering problem at work or in your spare time? Tell us your Tale

General engineering

• Trust the math. We’re lucky to be in a profession where many design solutions can be derived using mathematics – it is more science than art. Use the math and trust its results.
• You can’t violate the laws of physics no matter how smart you are. I’ve been in a room when presentations have been made of a design, but where the basic concept violated some law of physics. These poor people spent a lot of time heading to the dead-end.
• Be clever only when it’s needed. Don’t design in an “interesting” part into a company project unless it is needed. Save that exploration for your home projects.
• Build on previous designs if you can. Reusing parts of a proven solution is very good for business, and for your career.
• Document everything – code, tests, schematics, simulations, sketches. This is for the next engineer and for possible patent filings. It leaves a nice trail of work done to get to a solution.
• Work on the biggest unknowns first. This brings the risk to a project down quickly. If these issues cannot be resolved, the project concept may be able to be changed to avoid the issue.
• Estimate a project’s tasks to 8-hour resolution – make a list of all pieces of the project – code to write, circuits to design, mechanical, docs, testing, etc. Typically, you bring a representative of each design section into a room for a number of days. You discuss all areas of the design down to the smallest detail. I have found that if you break it down to a one-day task level, your time estimates will be very accurate, and you also may discover some risks early. Also never assume an 8-hour workday means 8 hours of engineering – many things get in the way. I always use 80% for the actual engineering time in a day.
• Fight for your time estimates. Management may tell you that your time estimate is too long, and give you a number that is too short. If you do a deep estimate down to the 8-hour level, you should be confident of the estimate and you can, and should, defend it. Don’t get pushed into an impossible time line.
• Adding people to a project in the middle may slow it down. Management may say they will give you more people. It depends on the project and where in the project you are, but more people can also be a time-sapping burden.
• Focus on your piece and trust the others to focus on theirs. I often had people tell me how this other team will not be ready when their part is needed. This is for a project manager to worry about. Keep your eyes on your part and make sure you’re ready on time.
• There is a fog-of-war on large projects. Project details can get lost and confused, especially on a large project. Things get missed in the activity – this is one of the project managers main tracking jobs. Make sure your part is well documented and progress/issues well communicated.
• Always stay calm. Things will go wrong; project disasters will happen. If you stay calm during these times, you will see that fixing the issue will go much smoother.
• Make sure all applicable department managers have signed off on the product spec. If someone wants a change, all departments need to sign off after engineering re-quotes the time/cost requirement changes.

Testing and troubleshooting

• Pay attention to anomalies. Anomalies are often dismissed, but these can be clues to an underlying problem. Document these anomalies for future reference.
• Ship what you tested – if you change anything, always retest. Don’t assume it will work.
• Use simulations but verify in the lab as there may be unaccounted-for parasitics. All components can have some level of parasitics; resistors can have capacitance and inductance. Capacitors can have resistance and inductance; capacitance values can change relative to the applied voltage. Inductors have resistance and winding to winding capacitance. Transistors, FETs, and all semiconductors can have various capacitance, inductive, and resistive parasitics. Don’t even get me started on crystals.

Your job

• None of us is irreplaceable. The company probably wouldn’t collapse if you were gone tomorrow. Management knows that – you need to know that, too.
• Take care of your career yourself. Don’t depend on your company to move you along in your career. Push for a position you want. Discuss wages if you want an increase. Work to get the training you want and need.

Hardware engineering

• Never assume a part can be substituted with one from a different manufacturer, product line, or value without retesting in the product.
• Understand basic practical thermodynamics as it applies to electronics design – this knowledge is needed often in electrical engineering (EE)-type projects. Calculations are needed when using things like heatsinks, PCB heat dissipation, thermal vias, active or convection cooling, heat pipes, etc. Much of this can be dealt with by an EE without the need for a mechanical engineer.
• Tell your manager that the first PCB assembly will have issues, the second works sometimes, and the third’s the charm. I’m not sure I’ve ever seen a PCB be perfect on the first pass (except maybe a very simple one). Problems can be EMI issues, schematic errors, assembly issues, pad/trace tweaks, mechanical issues, etc. The latest layout and simulation tools help a lot, but they won’t tell you that you spelled the company name wrong on the silkscreen.

Firmware engineering

• Don’t write obfuscated code. If it seems a bit cryptic, then document it well. ( I actually saw production code with the line “Bet you don’t know what this does”.)
• Stop using so many pointers.
• All code has bugs, even yours.
• Use a coding standard – consider MISRA guidelines.
• Use lots of comments – at the top of the program file, at the top of every procedure, the top of large conditionals, and on all cryptic statements.
• Adding your comments to AI-written code will help assure that you understand the code.
• No magic numbers in the code – if you have an actual number in a line of code, consider if it is better defined in something like a #define or const.
• Keep fixing code to remove all warnings from your compiled code – fix anything that shows an error code, at any level.
• Minimize the use of global level variables (I’m admittedly a serial violator of this crime.)
• Always check to see if pointers are in bounds. You may be creating unstable code along with security issues.
• Consider using AI, because it can often speed things up. Then again, though, it can also slow them down. My experience is that it can write very nice-looking code that typically compiles, but often there are subtle errors, especially on boundary conditions. So, don’t trust but verify, but suspect and test.
• Avoid dynamic memory allocation if you possibly can. This can very quickly lead to hard-to-understand crashes.

For managers

• Employees are expensive, and equipment is cheap if it speeds their work up. Get them what they ask for.
• Employee training is important – encourage and pay for expos and classes. Set up vendor presentations (and buy lunch).
• Encourage patent filings and implement bonuses for filed and granted patents. Patents are good for the company portfolio and the employee’s morale, as well as your recognition of support.
• All engineers have a type of engineering that they are good at. They may good at systems engineering, clean-sheet-of-paper designers (those that can design a device from scratch based solely on a concept) , lab test engineering, simulator/modeling, maintenance and component engineering, estimating/spec writing, customer facing or not, field engineering, analog and digital engineering, EMI/EMC experts, etc., etc. You wouldn’t assign a digital engineer to do a complex analog design; in the same fashion, don’t assign an engineer that’s good at analyzing field data to a clean-sheet-of-paper task (and vice-versa).
• If you lead, supervise, or manage, never ever micromanage. This is discouraging to an employee. If you think they’re not performing, ask if they need assistance. If you think they are in over their heads, back off their task list or move them to another task or project.

For everyone

• The 50% rule – this is my rule that states that 50% of the information you get from a user, having an issue with a device you designed, will be misleading or untrue. That doesn’t (hopefully) mean that they lied. It means they exaggerated, interpreted what happened and gave you the interpretation, mis-remembered a sequence of events, or used incorrect terminology (for example, said that the device died instead of that the screen or keyboard locked up). All data from the field must be vetted before digging too deep. ( I’m being generous with 50% because I actually believe the occurrence of this is more like 75%.)

I’m sure all the engineers out there have many other tips to add to this list. Let’s see some of yours in the comments. We’ll even allow mechanical engineers to chime in.

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

The post Some tips for electrical engineers appeared first on EDN.

Part 1 of this mini-series covering single event upset (SEU) challenges in FPGA architectures examined radiation particles and related SEU challenges for FPGA applications that require robustness and predictability in ground-based and terrestrial applications.

Part 2 of the mini-series will cover SEU detection, recovery, and validation for FPGAs used in mission-critical systems such as aerospace, defense, telecommunications, and industrial applications.

Detection and recovery from SEUs require a layered strategy that addresses the distinct vulnerabilities of configuration RAM (CRAM), user logic, and embedded data storage. No single technique provides comprehensive coverage across all FPGA resource types. Instead, an effective approach combines complementary methods, each targeting a specific failure mode, with recovery mechanisms that are tightly coupled to the detection events that trigger them.

The following sections describe the detection techniques and their associated recovery strategies, from configuration-layer monitoring to logic-level redundancy to system-level behavioral observation.

CRAM readback and scrubbing

CRAM readback is the most basic detection technique for SEUs in CRAM. The system calculates a cyclic redundancy check (CRC) for the bitstream. An internal hardened configuration block in the FPGA reads back the CRAM contents and compares the calculated CRC to the expected result. If the results don’t match, the system can set a status flag to alert the user, for example via an internal interrupt to a soft processor or an external pin to a system-level board controller.

If the system flags an SEU error, the user can take action, for example:

• Stop the FPGA application and reload the bitstream, overwriting the CRAM to fix the flipped bit.
• Wait for an accumulation of SEUs before halting the application and reloading the bitstream.
• In some applications, it may be acceptable to power cycle the board and thereby the FPGA, which automatically reloads the bitstream upon power-up.

SEU scrubbing is another SEU recovery technique. Some FPGAs contain blind scrubbing circuits that run in the background and can periodically rewrite the entire bitstream regardless of whether the system detects an error. It’s easy to implement blind scrubbing because it does not require comparison logic; the downside is that blind scrubbing cannot give diagnostics on error rates and specific locations of SEU.

You can schedule scrubbing continuously or for a fixed period, depending on the application and trade-offs on additional power utilization. At terrestrial levels, you can usually set scrubbing intervals further apart, while at higher elevations, given the higher probability of radiation particles, intervals should be shorter.

More advanced SEU readback scrubbing circuits can detect and fix SEUs and report multiple upsets within a bitstream frame. Recent FPGA architectures have bitstreams that have frames that program subsets of the CRAM. Each frame is protected with single error correction and double error detection (SECDED). The SEU readback scrubbing circuit reads the contents of the CRAM and compares the calculated error correction code (ECC) for each frame with a known good ECC for that frame.

If the comparison fails, the circuit can locate the single bit failure based on the ECC mismatch signature and re-write the bitstream frame with the incorrect bit corrected. The SEU readback circuit is more complex and can give better diagnostics for error rates and failure locations. If the readback detects multiple uncorrectable errors however, you may need to reload the entire bitstream or power cycle the FPGA.

Error detection and correction for block RAM

Block RAM upsets require a dedicated detection and correction strategy because the stored data changes dynamically during operation and cannot be protected by static configuration scrubbing. Data written to RAM is wider by a certain number of bits, depending on the data width and encoding used for protection.

If you use an ECC encoder when writing data to RAM, you can use an ECC decoder when reading from RAM to detect corruption. ECC encoders and decoders can detect and correct single- and double-bit errors. From a system design perspective, using ECC to protect block RAM adds latency for encoding and decoding.

Some FPGAs have in-silicon ECC encoders for writing to the RAM and ECC decoders for reading from the RAM to detect and correct corrupted bits. These hardware-based encoders/decoders use more silicon area, have higher power, and have additional output delays. Implementing ECC encoding and decoding in your RTL design is a good option if few block RAMs are used for critical functions such as soft processor program memory, high integrity data paths, or state machine storage.

Triple modular redundancy (TMR)

TMR is the most robust mitigation strategy to guard against SEU errors. TMR requires three independent copies of a circuit to produce the same output. Each circuit has its own copy of combinational and sequential logic. The system compares the result from all three circuits, and two out of the three must match. This method provides a correct result even if one circuit is corrupted.

TMR provides continuous cycle-to-cycle error masking without any detection latency, and is very effective for protecting state machines, control logic, and safety-critical signal paths. However, TMR requires very strict architectural implementation to guarantee that none of the circuits share logic or routing with each other.

Although robust, TMR comes with a large trade-off in terms of FPGA resource usage and power. You need to use at least three times the resources to accommodate the triple redundancy and plan on higher power requirements as a result. Additionally, TMR cannot self-correct a bit error. A bit flip in one of the circuits continues to be corrupt until CRAM scrubbing can address the corruption.

Measuring SEU rates in FPGAs

Quantifying the reliability of an FPGA’s exposure to SEU can be done with specific testing using particle beam accelerators in specialized facilities. The standard figure of merit for terrestrial SEU rate is the soft error rate (SER) expressed in failures in time (FIT), where one FIT equals one failure per 10⁹ device hours.

Most FPGA manufacturers that support SEU detection and scrubbing reserve time at reputable facilities that can provide high energy beams of heavy ions, neutrons, protons, and alpha particles. Facilities can be found in the U.S., Canada, Switzerland, and Japan. This ground-based approach for accelerated testing helps to characterize the FPGA family’s radiation sensitivity. FIT data from the testing helps predict upset rates in target environments.

Ground-based testing and analytical modeling provide pre-deployment FIT rate estimates, but operational monitoring during deployment in the application environment provides the most accurate characterization of device behavior. CRAM detection and scrubbing circuits can log time, location, and frequency of detected SEUs, which you can compare to pre-deployment predictions.

If you observe rates that differ from pre-deployment predictions, you can redesign critical circuits, change scrubbing intervals, and/or change operational range. Most FPGA users work closely with their FPGA vendor to understand measured ground-based FIT rates from beam testing within a specific family and compare it to the application environment testing results.

FPGAs with SEU capabilities

Take the case of Efinix’s Titanium and Topaz families that are built on TSMC’s 16-nm FinFET process. These FPGAs benefit from the inherent SEU sensitivity advantages of the FinFET geometry relative to planar 2D transistor architectures at equivalent geometry.

These FPGas have characterized SEU behavior through independent testing conducted per JEDEC Std. JESD89A for alpha particles and per STd. JESD89 and JESD89-A for neutron particles, providing design engineers with measured FIT data from which you can determine system-level reliability.

The company’s Titanium FPGAs have CRAM SEU detection that lets design engineers monitor configuration integrity and respond to detected upsets through external recovery actions. Efinix also provides data on the FIT contribution from SEU events (transient failure rate) in a soft-error rate (SER) report.

Design engineers can use this data to determine whether on-chip mitigation features are required to achieve target Probabilistic Metric for random Hardware Failures (PMHF) values under ISO 26262-5 for their specific ASIL level.

Next, Titanium Edge FPGAs pair SEU detection capability with hardware scrubbing. The scrubbing architecture implements SECDED on a per-frame basis, operating at clock rates up to 80 MHz. SECDED enables automatic single-bit error correction without an external processor, and it flags uncorrectable double-bit errors for system-level response.

The SEU detection is configurable to meet different application needs. Automatic detection cycles through CRAM frames without user intervention, providing the lowest mean time to detection and the highest assurance of configuration integrity. Manual monitoring allows you to initiate a scrub cycle on demand.

Similarly, you can set detection and correction triggering as automatic, manual, or fixed-rate operation, tailoring the scrubbing interval to your deployment environment’s potential SEU rate. To support design validation and test system robustness, Titanium Edge FPGAs include a hardware error injection capability that can inject a single-bit error at any location within the CRAM array.

Finally, Topaz FPGAs have similar SEU detection capabilities as the Titanium family, but they don’t have the Titanium Edge scrubbing architecture overhead. System designers can monitor detected SEU errors and recover from them via an external action. This family is targeted at high-volume applications such as machine vision, industrial robotics, and broadcast imaging and controls.

Why SEU detection is critical

Radiation-induced SEUs represent a reliability challenge in modern FPGA design and technology. SEUs can silently flip bits that corrupt configuration memory, embedded memory, routing, and logic, thereby negatively impacting system behavior.

The threat to smaller process geometry FPGAs affects terrestrial applications as well as ground-based applications where thousands of FPGAs may be deployed in a system. Ground-based FIT rates may be low for a single FPGA, but when thousands are deployed, the probability of SEU impacting system behavior may increase to a level that requires detection and recovery.

Packaging technology advancements to reduce trace radioactive impurities and alpha particle emission have helped FPGA vendors reduce FIT rates. However, heavy ions, protons, and neutrons continue to expose FPGA vulnerabilities and require heavy beam testing to quantify the sensitivity to SEU and resulting FIT rates.

Detecting SEUs and scrubbing FPGA CRAM are critical to quantify an accumulation of errors that may require a reconfiguration or power cycle. Similarly, quantifying SEU errors within a specific altitude profile can guide systems on scrubbing cycle time by analyzing system power trade-offs versus expected error rates.

You must also analyze the trade-offs when planning for embedded block RAM protection. Error detection and correction require a lot of logic resources that could be soft or hardened in silicon. If you don’t need to detect and correct errors in all block RAM, a soft implementation for mission-critical block RAM can save power and resource utilization.

The most comprehensive strategy to protect against critical control and data path errors is TMR, but with a heavy cost of three times the resources and additional power. Alternatively, some applications may use a mix of TMR, block RAM ECC, and CRAM SEU detection and scrubbing.

No matter which method you choose for mitigating SEU exposure, it’s important to work with the FPGA vendor to understand their testing methodology and resulting FIT rate data. The FPGA FIT rate data can then be extrapolated to understand and compare actual measurements with the application profile.

Mik Ichiba is principal field applications engineer at Efinix. He is a seasoned semiconductor and embedded systems professional with more than 30 years of experience spanning hardware architecture, PCB design, ASIC development, FPGA architecture, and system-level engineering. Throughout his career, Mik has worked across the hardware design lifecycle, helping organizations translate complex technical requirements into practical, high-performance solutions.

Editor’s Note

This is Part 2 of the mini-series about SEU challenges in FPGA architectures. Part 1 covered SEU radiation particles and related SEU challenges for FPGA applications that require robustness and predictability in ground-based and terrestrial applications.

Related Content

• Using FPGAs in mission-critical systems
• Rethinking the Logic-Routing Tradeoff in FPGAs
• Understanding Single Event Effects (SEEs) in FPGAs
• Enhancing robust SEU mitigation with 28-nm FPGAs
• Learn about SEU Immunity in Terrestrial FPGA Applications

The post FPGA architecture: SEU detection and recovery strategies appeared first on EDN.

Packaging innovation in the AI era has reached the doorsteps of power electronics. A new architecture uses the silicon wafer itself as the package foundation to enable a highly integrated approach to power system design. It optimizes electrical, mechanical, and thermal design together from the outset to help designers achieve higher power density and improve system performance.

Embedded Power Platform (EPP) unveiled by onsemi claims to have reimagined the package from passive housing into an active contributor to power design performance. It enables a seamless integration and interconnection of silicon, silicon carbide (SiC), and gallium nitride (GaN) technologies within a highly integrated wafer-level architecture.

Figure 1 In EPP, heterogeneous dies are embedded in silicon and connected through wafer-level redistribution layers. Source: onsemi

“For decades, the semiconductor and the package have been treated as separate technologies,” noted Hassane El-Khoury, President and CEO of onsemi. “EPP changes that by making the silicon itself part of the system architecture.” It does that by combining advanced semiconductor technologies, manufacturing, and system-level optimization into a single power design.

The AI era is creating new infrastructure challenges that computing power alone can’t solve. Take data centers, for instance, where design engineers must move and manage more electricity in server racks while controlling heat, efficiency, cost, and development time. That limits how much compute capacity can fit within a rack.

That’s mainly because traditional power system design approaches treat power electronics, mechanical design, and thermal design as separate engineering challenges. As a result, each layer is optimized independently and sequentially, so decisions made at one stage can create compromises in another. That, in turn, leads to additional engineering iterations, costly late-stage changes, and longer development cycles.

EPP replaces the sequential model with a common platform that can be co-designed, co-simulated, and co-optimized. That transforms it into a technology-agnostic platform that supports different applications and semiconductor materials while scaling across multiple power levels. As a result, multiple devices such as FETs, drivers, and controllers can be embedded together in a single package and co-optimized for electrical, thermal, and mechanical performance.

Figure 2 EPP claims to introduce a fundamentally new approach to how power is delivered, managed, and optimized. Source: onsemi

This enables tighter electrical coupling, combines power and control in a single platform, and reduces system-level complexity. According to onsemi, in a solid-state circuit-breaker design, the EPP-based solution was approximately 50% smaller and 20% cooler than existing designs.

Beyond data center power

Carmaker Subaru—an early engagement partner for EPP—is working with onsemi to evaluate how the platform could support future electrified vehicle architectures. Subaru will gain early access to engineering samples, simulation models, and technical expertise as the two companies explore opportunities to improve vehicle performance and streamline development.

Efficiency losses, thermal limitations, development complexity, and system size often constrain EV traction inverters. Here, EPP’s scalable architecture helps develop a single inverter platform that spans low-end to high-end vehicle applications. This lets carmakers reuse a common design across multiple vehicle models and power classes, reducing R&D and manufacturing costs, accelerating qualification and development cycles, improving vehicle range, and lowering system costs.

As AI, automotive, and industrial markets drive demand for more power in less space, a new architecture claims to redefine system power delivery by integrating multiple dies into a single silicon device. EPP also claims to enable 3 – 5x higher power density than current solutions through a highly integrated approach to power system design.

These claims will surely be tested in data center and EV power designs, where designers must improve efficiency while managing heat, size, and cost. EPP is expected to begin sampling in 2026 with strategic customers and ecosystem participants across automotive and AI applications.

Related Content

• The shift to 800-VDC power architectures in AI factories
• Power systems: the first parameter to evaluate is efficiency
• Low Power Design Techniques, Design Methodology, and Tools
• LTpowerPlanner: A system-level power architecture design tool
• Designing a data center power architecture with supply and processor rail-monitoring solutions

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Want to network-connect your gear using prevalent wired Ethernet? Or interference-impervious optical fiber? How about a bandwidth boost? Or a range extension? SFP and its siblings do it all.

One recent sequential-coverage cadence of mine just wrapped up, with part 4 of the “Debugging intermittent Comcast” run done. Another, my longstanding TP-Link smart plug teardown series, is nearing the finish line, with its next entry queued up to appear on EDN a week from next Monday and its final entry scheduled for next-month publication.

But if indeed all good things must sooner or later come to an end, other good things can also emerge in their stead. That’s what I hope will be the case for the small form-factor pluggable (SFP) module teardown series set to start next Monday. I first learned of SFP through my efforts to galvanically isolate my various LAN devices from lightning EMI-prone Ethernet and coax cables running outside of my residence.

Multi-gig gains ascendancy

I’ve subsequently become intrigued (also with pending editorial-coverage consequences) with the increasing (and dramatically so) cost-effectiveness of mainstream network switches, routers, and other devices based on 2.5 GbE technology. Take a look, for example, at this enterprise managed switch from the late 2000s, which cost several thousand dollars when brand new.

Granted, it has 24 primary Ethernet ports, but they “only” offer 10/100 Mbps. At far left are two more GbE Ethernet ports. And in-between the two RJ-45 arrays are two 1 Gbit SFP ports.

Fast-forward to today. This switch is admittedly unmanaged and has only eight RJ-45 ports.

But those RJ-45 ports are 2.5 GbE. The SFP ports are next-gen SFP+, 10 GbE. And the price tag? $41.39 at Amazon as I write these words.

Or this one:

Four fewer RJ-45s, albeit still 2.5 GbE. Once again, two 10 GbE SFP+ ports. And the price? $31.99. One of them is on an Amazon delivery truck headed to me later today as we speak, in fact. And in a near-future planned post, I’ll even detail how it’s possible to (and I in fact did) transform one into a fully user-managed variant using hacked factory firmware and/or open-source software.

Why 2.5 GbE (along with, to a lesser extent, 5 GbE) has become mainstream is a topic for another post another day (soon). Similarly, I’ll save for the near future more discussion on why 10 GbE SFP+ ports are appearing on mainstream gear like this. Today, in advance of a plethora of teardowns to come on a diversity of module variants I’ve been collecting in recent weeks, I just want to focus on what SFP is, along with its predecessor and siblings.

Without further ado, and focusing predominantly on the “flavors” most commonly used in consumer and workgroup settings, therefore in highest production volume, which typically translates to lowest cost (if you feel like your head’s about to explode after absorbing the full suite of SFP implementation options documented on Wikipedia, it’s perfectly understandable!)…

Mechanical form factors

Before SFP, there was GBIC, the gigabit interface converter, initially defined in 1995 and used with Gigabit Ethernet and Fibre Channel. As Wikipedia notes, “By standardizing on a hot swappable electrical interface, a single gigabit port can support a wide range of physical media, from copper to long-wave single-mode optical fiber, at lengths of hundreds of kilometers.”

Keeping in mind inevitable bandwidth extrapolation, thanks to further technology evolution, the same basic definition applies to 20-pin SFP, therefore explaining its alternative name, mini-GBIC.

Quad SFP (QSFP), as the name implies, supports four simultaneous bidirectional data lanes (therefore the 38-pin connector). The first picture above is of a standalone transceiver; the second shows an active optical cable (AOC) version conceptually like, albeit of course more complex than, the SFP-based ones I’m currently using in my network for galvanic isolation purposes.

The module is of the same height (8.5 mm/0.33 in.) as SFP, as is the XFP module I’ll discuss next. But it’s wider than SFP (18.35 mm/0.722 in. vs 13.4 mm/0.53 in.), although adapters can allow SFP modules to fit in QSFP sockets. And it’s also deeper than SFP; 72.4 mm/2.85 in. vs 56.5 mm/2.22 in.

Last, and least common nowadays, is another SFP precursor, aforementioned 30-pin XFP, dating from 2002. It’s even deeper than QSFP, 78.0 mm/3.07 in. The above photo is of it alongside SFP.

System interfaces

Commonplace SFP interfaces run at 100 Mbps and 1, 2.5 and 5 Gbps. The bitrate similarly to Ethernet counterparts is not accidental SFP+ leverages the same SFP mechanical form factor discussed earlier but runs at 10 Gbps and 25 Gbps, the latter alternatively known as SFP28. Less common 50 and 100 Mbps SFFP+ variants (SFP56 and SFP112) are also available, as are “DD” double density flavors which leverage up to 8 data lanes. Higher speed SFP+ versions migrate from non-return-to-zero (NRZ) modulation to four-level pulse-amplitude modulation (PAM-4).

Interconnect options

SFP modules connect to each other, as well as directly to system in some cases, via three main cable material and associated transceiver options: fiber optics in conjunction with electro-optical converters, RJ-45 Ethernet, and basic copper wire.

I’ll discuss fiber optics in more detail in the next section; for now, I’ll note the following:

• Both plastic and glass cable construction material options are available. Plastic characteristics include (with glass characteristics essentially the exact opposite):
  • Lower cost
  • Greater flexibility and overall handling safety
  • But much shorter usable distance due to high attenuation loss
  • Low tolerance of temperature extremes
• When the cable is permanently installed to SFP modules on both ends, it’s referred to (as alluded to earlier) as an active optical cable (AOC).

RJ-45 modules mate the SFP or SFP+ circuitry to an Ethernet transceiver. Speeds up to 10 GbE, such as with the module shown at the top of this section, are widely available. These modules tend to run “hotter” than fiber optical or basic wire alternatives, all other factors being equal.

Passive direct-attached-cable (DAC) wire harness-based cables are the most elementary version of this particular form factor, with the shortest effective range. Active copper cables (ACC), as a helpful white paper from NADDOD explains, “use a redriver chip architecture, employing continuous time linear equalization (CTLE) to boost signals on the receiver (Rx) side, acting as analog signal amplifiers.” And active electrical cables (AECs) “are more advanced, using a retimer chip architecture to amplify and equalize signals at both transmitter (Tx) and receiver (Rx) ends, with added clock data recovery (CDR) to reduce jitter, offering higher signal integrity and clearer data transmission.”

Wavelengths

SFP modules most commonly run at the following wavelengths (all are center frequencies):

• 850 nm (“multimode”)
• 1300 nm (“multimode”)/1310 nm (“single-mode”)
• 1550 nm (“single-mode”)

The distinction between multimode and single-mode fiber optics is important to comprehend and keep in mind, as the two technologies are not interchangeable (although some modules will work with both associated cable material types).

Multimode was historically much less expensive to implement, at the tradeoff of lower usable transmission distance. It features a comparatively larger cable core (50 to 62.5 microns) that lets multiple light signals travel down different paths at the same time, and it usually uses lower-cost LEDs or vertical-cavity surface-emitting lasers (VCSELs).

Single-mode features a comparatively tiny core (about 8 to 10 microns), which allows only a single ray of light to pass straight through without bouncing off the edges, and it uses focused lasers as a light source. Its historical cost disadvantage versus “multimode” has more recently decreased, due in part to the availability of non-proprietary, widely compatible modules. And as noted earlier, it generally specifies much longer usable transmission distances.

Cable tiers

We’ve already discussed fiber optic cable materials and construction options, along with associated light source and reception approaches. Each combination also has multiple quality tiers, which are commonly color-coded for ease of user recognition and interpretation.

Multimode cable comes in OM1 through OM5 options, with OM1 and OM2 now in legacy status and OM3 and OM4 most common nowadays. The fundamental tradeoffs between them involve lower cost (OM3) versus higher modal bandwidth and longer transmission spans (OM4).

For single-mode fiber optics, it’s simpler—OS1 and OS2—although the two types are incompatible in that they cannot be directly connected to each other. Cost, bandwidth and transmission distance are again the predominant evaluation criteria between them, although construction variances also tend to favor OS1 for indoor use and OS2 for outdoor applications.

Fiber connectors

Legacy GBIC deployments used the Standard (or Subscriber) Connector (SC) to mate cables to modules. Newer SFP-based implementations have switched to the much smaller Lucent Connector (LC). AOC fiber interconnect with SC plugs on one end and LC plugs on the other is also commonly available to bridge legacy and newer networking hardware.

Module flavors

As mentioned earlier, I’ve got a bunch of modules in hand, which I plan to tear down and internals-share with you in the coming months. As you can likely already imagine, the implementation diversity inherent in combining the numerous technology variables discussed in the previous sections results in oft-“interesting” module results. Here’s what I’ll be dissecting:

• 1 Gbit SR (short range, multimode) SFP module
• 1 Gbit LX (long range, usable with both single-mode and multimode cable at differing distances) SFP+ module
• 1 Gbit SFP to RJ45 transceiver module
• 5 Gbit ZX+ (extended long-haul range, single-mode) SFP module
• 10 Gbit IR (intermediate range, single-mode) SFP+ module
• 10 Gbit 0.3 meter/1 foot DAC cable
• 25 Gbit SR (short range, multimode) SFP+ (SFP28) module
• 40 Gbit SR QSFP+ module

The last one, whose image is at the top of this section, is particularly interesting (at least to me). It’s a 1 Gbit “BX” SFP module, with BX standing for bidirectional. Compared to the prior fiber-based modules, which use one strand for transmission and the other for reception (so you need to be sure when you hook them up that each strand’s transmission connection on one module end mates up with the other module’s receiver connection at the other end, and vice versa!), a BX module both transmits and receives across a common single cable strand.

The wavelengths employed by each module are vendor-specific, so you need to be careful in reading the specifications to ensure that you’ll end up with a transmit-and-receive wavelength matched pairing on both ends of the cable. Or just play it safe and buy all your modules from a single supplier, using a common model number.

And here’s a further “wrinkle” on the concept; in the above picture, since only a single strand is in use, there’s only one exposed optical connector site necessary. cSFP modules instead continue to use both fiber cable connectors, combining two bidirectional electro-optical subsystems in one module for doubled per-cable transfer rates. Tricky, eh?

That’s all I’ve got for you today. Look for my initial module teardown in the series, of the aforementioned 10 Gbit LX SFP+ module, to come early next week. And until then, I as always welcome your series-so-far thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• TP-Link MC220L: Media conversion keeps the network well
• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
• Design considerations in high-speed fiber networks

The post SFP: Add-in module delivers diminutive performance, flexibility appeared first on EDN.

The ST SafeSense VD56GA 1.1-Mpixel automotive image sensor enables infrared in-cabin sensing for driver and occupant monitoring applications. Based on ST’s DeepNIR BSI pixel architecture, the sensor delivers 35% higher modulation transfer function (MTF) and nearly 60% higher quantum efficiency (QE) than the previous generation. The higher MTF and infrared sensitivity result in sharper images, while the sensor’s small CSP allows discreet in-cabin camera designs for space-constrained installations.

With 2.43×2.43-µm pixels, the global-shutter sensor’s 1.1-Mpixel architecture achieves virtual 2-Mpixel performance. According to ST, the VDA56GA can reduce overall camera-module costs through lower-cost optics, simplified infrared illumination, and less demanding optical filtering. Embedded image-processing functions, including mirror, crop, dark calibration, auto exposure, and piecewise-linear processing, eliminate the need for external image processing. Together, these features can help designers deploy driver and occupant monitoring across a broader range of vehicle models.

The sensor is undergoing AEC-Q100 Grade 2 qualification, with a −40°C to +125°C operating junction-temperature range. It is compliant with ISO 26262 for ASIL B system integration and ISO/SAE 21434 for automotive cybersecurity.

Samples are available now. Pricing information and sample requests are available from local ST sales offices.

VD56GA product page 

STMicroelectronics

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Vishay’s XFD11KxxCA flat-clamping transient voltage suppression (TVS) devices provide 11 kW of peak pulse power dissipation at 10/1000 µs. Offered in surface-mount DO-218AC packages, the bidirectional devices maintain a low clamping ratio (VC/VBR) close to 1.0, supporting high power density.

The XFD11KxxCA series comprises 15 devices, each available in commercial and AEC-Q101 qualified grades. They have clamping voltages of 40.6 V to 104.0 V, breakdown voltages from 36.7 V to 104 V, and standoff voltages from 33 V to 85 V, making them suitable for 12-V, 24-V, and 48-V automotive powertrains. At the same standoff voltage, they have lower clamping voltage than conventional TVS products in DO-218 packages and deliver approximately 1.6 times higher peak pulse current, up to 207.1 A at 10/1000 µs.

Additional key specifications include an 8/20-µs surge capability of up to 2140 A and maximum leakage current of 10 µA at the standoff voltage (VWM) to minimize power loss. The series’ low, stable clamping and breakdown voltages over a wide temperature range of -55°C to +175°C allow the use of lower-voltage downstream components, reducing voltage overshoot and enabling smaller design guard bands.

Samples and production quantities of the XFD11KxxCA series are available now, with lead times of 12 weeks.

XFD11KxxCA product page

Vishay Intertechnology

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Singular Photonics’ Litavis is a CMOS single-photon avalanche diode (SPAD) image sensor with integrated digital photon processing on-chip and in-pixel. By processing photon events directly on-chip, it reduces the volume of raw data that must be transferred and processed externally.  According to the company, Litavis enables scalable real-time imaging systems with lower latency and improved power efficiency.

The 3D-stacked, back-side-illuminated (BSI) sensor captures spatial and temporal information while extracting scene information such as depth and event characteristics. Its software-configurable architecture combines photon-counting imaging, programmable time gating, and photon timing within a scalable SPAD array. Litavis supports intensity, timing, and histogramming modes concurrently, allowing users to dynamically adjust sensor parameters in software without requiring a new hardware design.

Litavis provides continuous 256×256-pixel photon-counting imaging under low-light conditions and simultaneously generates time-stamped photon events across a 64×64-macropixel timing grid. It delivers 47% photon detection efficiency (PDE) at 785 nm, 37-ps timing resolution, and 4.3-ns dead time, with a 100% fill factor enabled by microlenses.

The SPAD-based sensor targets applications including machine vision, physical AI, robotics, depth sensing, and scientific imaging. A timeline for sensor availability was not provided at the time of this announcement.

Litavis product page  

Singular Photonics  

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Anti-surge chip resistors in Rohm’s SDR01 series deliver a rated power of 0.33 W in the 0402 (1005 metric) package. The devices save board space and lower component count by replacing larger-size resistors in automotive, industrial, and AI server applications that require increased mounting density.

With optimized resistive element and electrode designs, the SDR01 series achieves a high rated power in the 0402 size while maintaining the reliability expected of high anti-surge chip resistors. The devices maintain their 0.33-W rating at terminal temperatures up to 125°C, making them suitable for demanding thermal environments.

Qualified to AEC-Q200, the chip resistors operate over a temperature range of -55°C to +155°C. The SDR01MZPF has a resistance tolerance of ±1% and a resistance range of 1 Ω to 2.2 MΩ, with a TCR of ±100 ppm/°C from 10 Ω to 2.2 MΩ. The corresponding ratings for the SDR01MZPJ are ±5%, 1 Ω to 10 MΩ, and a TCR of ±200 ppm/°C from 10 Ω to 10 MΩ, respectively.

The SDR01 series is now in mass production.

Rohm Semiconductor 

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