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Three smart home hubs, from two different companies. All supporting both 2.4 GHz Wi-Fi and proprietary 900 MHz wireless links. How do they differ, and are similar? Let’s find out.

Last month, I told you about TP-Link’s Tapo Hubs and their functional similarity to Blink’s Sync Modules. And last week, I took apart Blink’s second-generation hub, comparing it to its premiere predecessor which’d gone “under the knife” nearly a decade earlier. Today, I’ll be dissecting the entry-level Tapo H100 hub I conceptually covered in late March.

How comparable (or not) is its design to those of its Blink competitors? Let’s dive in and see.

Smart hub brothers from different mothers?

I shared a full set of outer box shots last month; so to avoid redundancy, this time I’ll show only the perspective that’s different, since last month’s device remains in ongoing use while this one (with a different serial number) is intended (initially, at least) solely for dissection.

As usual, it’s accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes. Also note that, per the common “US/1.26” notation on the sticker found on the bottom of both boxes, this device and last month’s H100 are presumably based on the same hardware version.

Opening up the packaging, you’ll find a sliver of literature inside, with our patient below it.

The only constant is change

On the product support page I initially referenced earlier, you’ll also discover that there have been four hardware versions to date: v1.0, v1.2, my v1.26, and the subsequent (I’m assuming) v1.8. Attempts to mix-and-match divergent hardware, as I’ve noted before, can be problematic. That said, most households will contain only a single hub device (versus multiple sensors and other “smart” peripherals), minimizing the potential-problem set size in this particular case.

Before continuing, let’s revisit the backside of the device, this time zooming on the markings.

Notice what looks like a label stuck on top of part of the original info? That’s exactly what it is.

As it turns out, the FCC ID found on the backside markings (2AXJ4H100) was also later updated; it’s now 2BH7FH100. Are the two changes related? Dunno.

Time to dive inside, a task that, compared to TP-Link smart switches of (recent) past, was thankfully fairly straightforward this time around.

Inside the front half of the enclosure, you’ll find a speaker (used, for example, to implement the sound emitted when the hub is paired with, and activated by, a “smart” doorbell).

And the mechanical assembly for the pairing-and-reset switch is shown on one side, as seen earlier.

Categorizing the guts

Here, however, is the view that most of you are most interested in, I guess.

The bottom half of the PCB disconnected itself from the back half of the enclosure while I was prying apart the two halves.

Further bending back the PCB reveals how the AC “prongs” connect to it.

As well as the PCB backside itself.

The small five-lead IC in the middle, PCB-labeled U4, is marked:

TACeY1

Its identity is unknown to me (readers?). Below it, in a larger seven-lead package, is On-Bright Electronics’ OB2512NJP offline primary-side-regulation (PSR) power switch. Below that is a M7 high voltage rectifier diode. And to its left is another (bridge and three-lead, this time) rectifier, Galaxy Microelectronics’ MBF10M.

Back to the PCB front side, after “un-popping” the PCB (putting it back in its normal place within the enclosure, which is upside down in both the prior-version and the following photo versus its normal orientation).

Note first the two antennae, one embedded and along the lower edge, the other discrete and along the right side. I assume one’s for 2.4 GHz Wi-Fi while the other supports TP-Link’s proprietary 900 MHz ISM band “ultra-low power wireless protocol”. Reader suggestions as to which is what are greatly appreciated in the comments.

In the upper right (again, lower left in normal operating orientation) is the status LED, which ends up shining out the device front cover. The pairing-and-reset switch is along the left side. The top half of the PCB, perhaps obviously given the sizeable transformer, houses the AC/DC conversion circuitry (the fact that the AC prongs are directly behind it at the rear of the device is another functional tipoff).

And, last but not least, the various ICs. In the lower right corner of the transformer is an Eon Silicon Solution EN56Q64-104HIP 64 Mbit serial flash memory, which we’ve seen before in both higher and lower capacities. I assume it houses the code for Realtek’s RTL8710CM SoC below and to its left, also found in the first two of the three TP-Link smart switches I’ve dissected so far. At the bottom, in the middle, is WayTronic’s WT588F02B audio DSP with an integrated DAC, which “can directly drive 8R 0.5W speakers”, an unsurprising function given the speaker connection directly to the left of it. Above and to the right of the audio DSP is another IC I can’t ID:

35UT
53C1

And above and to the left of the mono speaker connector is one final mystery:

300A
S992
515

Reader insights into any of the chips I was unable to identify, as well as broader thoughts on anything I’ve discussed here, are always welcome in the comments.

Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• The Tapo Hub: TP-Link joins the low-bandwidth, long-range RF club
• The Blink Sync Module 2: Faster response and local storage, too
• Teardown: Security camera network module
• TP-Link’s Kasa HS103: A smart plug with solid network connectivity
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again

The post TP-Link’s Tapo H100: Smart sensing unencumbered appeared first on EDN.

Ketone detection may sound like the domain of biochemistry, but at its core, it’s also an electronics challenge: how do we translate a chemical presence into a measurable electrical signal?

The key lies in the ability of circuits to convert molecular interactions into quantifiable outputs. Through principles like signal conversion, amplification, and conditioning, electronics transform invisible chemical activity into reliable data, making ketone monitoring practical and accurate while underscoring how deeply electronics shape modern health technologies.

Ketones: Small molecules, big impact

Ketone detection is crucial because these molecules act as direct indicators of how the body manages its energy balance. Moderate levels can reflect healthy states such as fasting, exercise, or adherence to ketogenic diets, while dangerously high concentrations may signal conditions like diabetic ketoacidosis that require urgent medical attention.

By providing timely and accurate measurements, ketone monitoring empowers individuals to optimize nutrition and performance and gives clinicians essential data to prevent and manage metabolic complications. In both everyday wellness and clinical care, reliable ketone tracking plays a decisive role in safeguarding health.

Overview of ketone detection sensors

Nowadays ketone detection has moved well beyond the lab bench and into lifestyle and wearable electronics. Compact analyzers are being built into fitness trackers, smartwatches, and portable health devices, giving users real-time insights into metabolism and diet. This evolution is powered by the fundamentals of electronics—miniaturization, low-power design, and signal processing—that make complex biochemical measurements practical in everyday life, turning health monitoring into a seamless part of daily routines.

While electronics provide the backbone for translating chemistry into measurable signals, the choice of sensor defines how ketones are detected. Electrochemical sensors generate currents via redox reactions, optical sensors capture variations in light absorption or fluorescence, and chemiresistive sensors—including semiconductor gas sensors—exploit surface-level conductivity shifts. Each technology offers a unique pathway from molecular interaction to electrical output, setting the stage for circuits to amplify, filter, and interpret the data with precision.

Ketone sensing: The gold standard and beyond

In practice, blood testing is the clinical gold standard, using the enzyme β-hydroxybutyrate dehydrogenase (HBDH) to generate a precise electrical signal from β-hydroxybutyrate (BHB). Keep note that a blood ketone meter functions as a miniaturized potentiostat; it maintains a fixed voltage across the biosensor to measure the current produced by this reaction, providing the data needed to distinguish safe ketosis from metabolic crisis.

Figure 1 Today’s multifunction blood meter kits provide a fast and reliable method for measuring β-ketone, blood glucose, and other parameters from fresh whole blood samples in just a few simple steps. Source: eLinkCare

However, the field is evolving beyond the invasive finger-prick. Researchers are now optimizing alternative biomarkers and delivery methods to bridge the gap between clinical accuracy and user convenience.

Exhaled breath analysis targets acetone—a volatile byproduct of fat metabolism. Current technologies, such as chemiresistive metal-oxide sensors, offer a high-frequency, non-invasive “proxy” for ketosis. While breath analysis currently lacks the clinical precision required for acute emergencies like diabetic ketoacidosis (DKA), it provides a sustainable, pain-free alternative for routine wellness tracking.

In a nutshell, ketone breath analyzers typically employ semiconductor-based, chemiresistive sensors to detect acetone—a byproduct of fat metabolism—in exhaled breath. These sensors function by measuring changes in electrical resistance triggered by volatile organic compounds (VOCs), which serves as a proxy for blood ketone concentration. High-end models often integrate CMOS technology to enhance both sensitivity and measurement precision.

Figure 2 Ketone breath analyzers and subcutaneous sensors deliver real-time feedback on ketosis levels. Source: Author

Continuous ketone monitoring (CKM) is an emerging technology that utilizes a small subcutaneous sensor—similar to a continuous glucose monitor (CGM)—to measure BHB levels in the interstitial fluid. By providing real-time data and automated alerts, these devices aim to detect rising ketone levels before they escalate into metabolic emergencies, effectively transitioning patient care from ‘spot-check’ diagnostics to continuous, proactive health management.

Note that a subcutaneous sensor is a tiny, flexible filament inserted into the fatty tissue just beneath the skin. By monitoring the interstitial fluid in this layer, the sensor uses enzymes to measure specific chemical markers—like glucose or ketones—and converts those readings into a continuous digital stream. Because it stays in place for several days and does not require venous access, it offers a painless, real-time alternative to repeated finger-prick testing.

Electronic biosensing for makers

To wrap this up, remember that while the medical industry uses highly proprietary, pre-calibrated systems, the underlying principle is a fantastic playground for makers.

Whether you are working with a glucose oxidase strip for blood sugar or a β-hydroxybutyrate strip for ketone levels, the principle is the same: enzyme-mediated reactions generate electrons that must be measured against a stable reference potential.

Once you master the transimpedance amplifier (TIA), you have essentially built the core of a professional-grade diagnostic instrument. In fact, most commercial biosensors integrate the TIA and supporting circuitry into an analog front end (AFE), which delivers low-noise performance and simplifies design, an approach that makers can emulate at smaller scale when experimenting.

On a related note, amperometry is the electrochemical technique at the heart of most biosensor strips. It involves applying a fixed potential to an electrode and measuring the resulting current, which is directly proportional to the concentration of the analyte.

In glucose oxidase strips, the enzymatic reaction produces hydrogen peroxide that is oxidized at the electrode, while in β-hydroxybutyrate strips, NADH transfers electrons through a mediator. In both cases, the transimpedance amplifier converts this tiny current into a usable voltage signal, enabling accurate, low-noise measurement.

Figure 3 Quick view shows a closeup of a standard ketone blood tester strip. Source: Author

For those curious about non-chemical ketone monitoring, it’s worth noting that hobbyists have also experimented with MQ13x series gas sensors such as MQ138 to approximate acetone levels in breath.

These gas sensors are not medical-grade and require careful calibration against known standards, but they can respond to volatile organic compounds in exhaled breath. Pairing one with a microcontroller, a stable heater supply and signal conditioning circuitry give you a rough, experimental ketone breath analyzer. It’s a fun proof-of-concept project—ideal for learning sensor physics and electronics.

Figure 4 MQ138 sensor module helps detect acetone in exhaled breath, enabling experimental DIY ketone analysis. Source: Author

Just keep in mind that for any real-world health tracking, these DIY setups should be for educational exploration only. Medical-grade devices undergo extensive clinical validation to handle variables like hematocrit levels, temperature, and signal interference—factors that a prototype might miss.

Finally, do not let the complexity of biomedical electronics intimidate you. Every expert once started as a novice tinkering with circuits and sensors. Dive in, experiment boldly, and let curiosity be your guide—the frontier of electronic biosensing is wide open for makers willing to explore.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• What’s in store for optical biosensors?
• The critical role of sensors in medical devices
• Designer’s guide: Sensors for medical applications
• Developing medical sensors compliant with global requirements
• Tools and techniques for electrical characterization of biosensors

The post Electronic biosensing: A quick take on ketone detection appeared first on EDN.

Automated test equipment (ATE) supplier Teradyne is bolstering its test solutions for semiconductor design by acquiring TestInsight, a provider of test program creation, pattern conversion, and pre-silicon validation tools used across ATE platforms and semiconductor design environments.

By acquiring a supplier of semiconductor test development, validation, and conversion software, Teradyne aims to scale its next generation of pre-silicon validation and automated pattern generation technologies. That strengthens Teradyne’s ability to support semiconductor design-in activities to accelerate time-to-market in the emerging AI and data center markets.

Here is how pattern conversion across multiple cores and CPUs accelerates the test program. Source: TestInsight

Greg Smith, president and CEO of Teradyne, calls TestInsight’s tools foundational to modern test program development. “By integrating the TestInsight team into Teradyne, we enhance our ability to help customers achieve silicon readiness faster and with greater confidence.”

The acquisition will allow Teradyne to combine its ATE platforms with TestInsight’s tightly integrated design-to-test workflow, thereby reducing debug cycles, improving coverage, and enabling earlier test program readiness. In short, the acquisition of a design-to-test software firm will help Teradyne close the gap between design and test in semiconductor design environments.

TestInsight announced that it will continue to support its existing customers across all ATE platforms.

Related Content

• Low-Budget Automatic Test Equipment
• How to power automated test equipment
• Automated Test Equipment for 3D Magnetic Sensors
• Optimizing Automated Test Equipment for Quality and Complexity
• Flexible Test Strategies Keeping Pace with Semiconductor Evolution

The post Teradyne snaps up TestInsight to boost ATE for semiconductors appeared first on EDN.

Aliasing is thankfully becoming a less frequent problem due to improved instrument designs. Users should still be aware of it to prevent time- and money-costly errors.

Aliasing is an ever-present potential problem in sampled data acquisition systems. It occurs when input signals are sampled at a sample rate that is too low. If you haven’t been bamboozled by an aliased signal, you are extremely lucky.

Sampled data instruments, such as digitizers and digital oscilloscopes, must sample their input signals at a rate greater than twice the highest frequency component present in the input signal. If this criterion is not met, then aliasing can occur. Figure 1 shows an example of aliasing.

Figure 1 In this example of aliasing, a 50MHz sine wave was acquired at sampling rates of 1 Giga samples per second (GS/s) and 55 Mega samples per second (MS/s). The 55 MS/s acquisition is aliased and displayed as a 5 MHz waveform.
Source: Art Pini

A 50 MHz sine wave was acquired at both 1 GS/s and 55 MS/s. The waveform acquired at 1 GS/s has the correct frequency of 50 MHz as shown in the frequency parameter P1. The waveform acquired at 55 MS/s is aliased and has a frequency of 5 MHz as reported in parameter readout P2. The alias waveform will appear as having a different frequency than the correctly sampled waveform. This can be a significant problem that can be costly if not addressed carefully.

Let’s look into aliasing and learn how to deal with it. Sampling is a mixing process. When you apply an input signal to a sampler, the resulting output from the sampler contains the original waveforms, the sampling waveform, and the sum and difference frequencies, including the harmonics of the sampling signal. This is illustrated in Figure 2.

Figure 2 Sampling is a mixing or multiplicative process. The baseband frequency spectrum of the acquired signal appears as the upper and lower sidebands about the sampling frequency and all its harmonics.
Source: Art Pini

A correctly sampled waveform will have more than two samples per cycle at the bandwidth limit. In the sampler output, the baseband frequency spectrum of the input signal will appear as upper and lower sidebands about the sampling frequency and its harmonics. The right-hand graphs show the output spectrum of the sampler for the correct sampling rate (upper) and the undersampled case (lower). As the sampling frequency is decreased below twice the input signal bandwidth, the lower sideband of the sampling frequency interferes with the baseband signal, resulting in aliasing.

In the time-domain view (left-hand graphs), the aliased signal lacks sufficient time resolution to track the input waveform. Returning to the example in Figure 1, the 50 MHz input sampled at 55 MS/s will result in sum and difference image frequencies that are above and below the 55 MS/s sampling frequency. The lower sideband image falls into the baseband region of the spectrum and is the source of the 5 MHz alias signal.

Current digital instrument designs generally use sampling rates much higher than the instrument’s analog bandwidth. Some instruments may use sharp-cutoff anti-aliasing low-pass filters to limit the input bandwidth and control the instrument’s frequency response. These techniques, combined with long acquisition memories, also minimize this classic problem.  Still, users should be aware of aliasing.

Recognizing Aliasing

It is good practice to determine the frequency of the measured signal and verify that it has not been aliased. If the characteristics of the input signal are unknown, it is good practice to view the signal at the highest available sample rate, then decrease the sampling rate as needed. If aliasing occurs, you will see the signal’s frequency change as you select a lower sampling rate.

Another hint that a signal is an alias is that it will appear to have an unstable trigger and will jump erratically in time. This occurs because the instrument is triggered by the signal, and the alias, with fewer samples, may not display the trigger point. The instrument displays the nearest sample, which varies from one acquisition to the next, causing instability.

Aliasing can also be recognized by observing the effect on the input signal’s frequency-domain spectrum as the signal’s frequency is varied. A spectral component that shows a decrease in frequency when the input signal’s frequency is increased, a reversal of direction, is an alias. As the frequency of a sine wave increases, the spectral line corresponding to that sine wave will move to the right until it hits the Nyquist frequency of one-half the sample rate.

As the frequency increases above Nyquist, an aliased image from the lower sideband about the sampling frequency will fold back into the baseband spectrum, moving downward in frequency. The lower-sideband images for each harmonic of the sampling frequency show this reversal. Upper sideband images will move in the correct direction. This phenomenon is called spectral folding.

A helpful technique to view an aliased signal

If the signal is a relatively simple periodic waveform, such as the example sine wave, then enabling infinite display persistence will show the underlying waveform, as shown in Figure 3.

Figure 3 The aliased signal (upper trace) and the same signal displayed with infinite persistence turned on (lower trace). The persistence display accumulates all the sample values showing the original 50 MHz waveform.
Source: Art Pini

All sample points in the aliased waveform are real. If infinite persistence is enabled, all samples are accumulated on the persistence display, and the original unaliased waveform is eventually recovered. This technique won’t work for complex signals such as non-return-to-zero (NRZ) data or broadband signals.

Using aliased waveforms

Given that aliased signals are made up of real samples, an aliased signal can be used in measurements, as long as the signal’s frequency is not being measured. Consider measuring the output of a remote keyless entry transmitter. This device outputs a pulse-modulated RF signal with a carrier frequency of 433MHz. This signal has a relatively narrow bandwidth about the carrier frequency. The information being transmitted is encoded in a 400 ms pulse pattern.

Two measurement scenarios are needed. The first is to characterize the RF signal. Parameters like frequency. Also, the shape of the RF envelope affects the purity of the transmitted signal. The second measurement would involve decoding the information content. Using an oscilloscope with a 20 Mega sample (MS) memory at a horizontal scale setting of 100 ms per division (1 second acquisition time), the sampling rate would be 20 MS/s. Figure 4 shows the two measurement processes for both the RF and Data decoding measurements.

Figure 4 Measurements on a remote keyless entry transmitter use an aliased signal to decode digital data.
Source: Art Pini

The traces on the left side of the screen show the RF measurements. The signal is acquired at 20 GS/s, and its leading edge is captured. The oscilloscope measures the RF carrier frequency at 433.9 MHz. The envelope of the RF carrier is extracted by applying the absolute value function, followed by a low-pass filter to create a peak detector. Trace F1 (bottom) shows the envelope. A copy (Trace F3) of the Envelope is also overlaid on a horizontally expanded zoom view (Trace Z1) of the leading edge of the signal. The envelope can be used to measure the envelope’s rise time.

The right side of the display shows the data decoding process. The entire data packet is acquired on a 100-ms-per-division horizontal scale. The sampling rate is 20 MS/s. The RF carrier is aliased down to 6.13 MHz as measured in parameter P2. The aliased frequency of the carrier is the result of mixing the twenty-second harmonic of the sampling rate with the 433.9 MHz carrier. The same envelope detection technique is applied to the entire packet, rendering the data content as an NRZ signal. Aliasing has enabled the acquisition of the entire signal data packet.

Conclusion

Aliasing in digital instruments is a digitizer characteristic that is becoming less frequent a problem due to improved instrument designs, including anti-aliasing filters, oversampling, and very long acquisition memories. Users should still be aware of aliasing to prevent errors that cost time and money.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

Related Content

• Sampling and aliasing
• Using oscilloscope filters for better measurements
• Combating noise and interference in oscilloscopes and digitizers
• Building a low-cost, precision digital oscilloscope—Part 1
• Building a low-cost, precision digital oscilloscope – Part 2

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Many Bluetooth Low Energy (LE) applications depend on reliable, high‑throughput data transfer between connected devices. Typical use cases include over‑the‑air (OTA) firmware updates, sensor data streaming, and bulk data transport between embedded systems. Although the Bluetooth LE specification defines clear upper bounds on achievable data rate, measured throughput in real systems often falls well below these limits.

This discrepancy is not caused by a single factor. Instead, it arises from the interaction of connection‑event timing, controller scheduling behavior, protocol stack implementation, and radio‑frequency conditions.

While modern Bluetooth LE devices commonly support Data Length Extension (DLE), the 2-Mbps Physical Layer (PHY), and large Attribute Protocol (ATT) Maximum Transmission Unit (MTU) sizes, these features alone do not determine achievable throughput.

This article focuses on the practical constraints that shape Bluetooth LE Generic Attribute Profile (GATT) write throughput in deployed systems and explains why throughput behavior is frequently non‑linear and platform‑dependent.

Assumptions and test context

To isolate timing and scheduling effects from feature limitations, the analysis presented here assumes a contemporary Bluetooth LE configuration with the following capabilities:

• Support for DLE on both Central and Peripheral
• Use of the 2-Mbps PHY
• A negotiated ATT MTU of 251 bytes
• Transmit‑side buffering sufficient to queue multiple packets
• Use of GATT Write Without Response operations
• A receiver capable of sustaining the incoming data rate without application‑level back‑pressure

GATT Write Without Response is used to minimize protocol overhead and eliminate application‑layer acknowledgments that would otherwise consume airtime and delay buffer reuse. Although this write type omits an explicit GATT‑layer acknowledgment, delivery to the receiver’s Link Layer remains guaranteed by the Bluetooth LE protocol.

Under these assumptions, throughput might be expected to scale directly with the number of packets transmitted per connection interval. In practice, this assumption does not hold.

Theoretical throughput

With Data Length Extension enabled, a single Bluetooth LE Link Layer packet can carry up to 251 bytes of payload. After accounting for Logical Link Control and Adaptation Protocol (L2CAP) and Attribute Protocol (ATT) headers, 244 bytes remain available for application data.

Using the 2-Mbps PHY, the on‑air time for a maximum‑length data packet followed by its acknowledgment is approximately 1.4 ms. If a connection interval could be filled entirely with such packet exchanges, without additional Link Layer procedures or timing gaps, the resulting application‑layer throughput would be approximately 170 KBps.

This value represents an upper bound that is rarely approached in practice.

Connection events and packet scheduling

Bluetooth LE communication occurs within periodic connection events scheduled at intervals defined by the connection interval parameter. During each event, the Central and Peripheral exchange packets until one side terminates the event or the available time expires.

Most controllers support transmitting multiple packets within a single connection event, but the maximum number of packets allowed per event is not specified by the Bluetooth standard and is instead determined by the controller and stack implementation. As a result, packet scheduling behavior can vary significantly across platforms.

This difference is illustrated in Figure 1. In the left‑hand chart, a wireless MCU acting as the Central can pack 20 packets into a 30‑ms connection interval, using most of the available airtime before entering a short end‑of‑event dead time. In contrast, the right‑hand chart shows a smartphone operating as the Central, where the connection‑event length is capped at five packets, even though additional airtime remains available within the same interval.

Figure 1 Packet scheduling within a Bluetooth LE connection interval varies by platform. A wireless MCU Central fills most of a 30‑ms interval with data packets, while a smartphone Central limits the number of packets per connection event, leaving unused airtime. Source: Microchip

Such limits are particularly common on mobile platforms, where power management and radio coexistence requirements constrain connection‑event length. When the number of packets per event is capped, increasing the connection interval does not necessarily increase throughput, because the additional airtime cannot be used for data transmission.

Residual time and end‑of‑event dead time

Two timing effects significantly reduce usable airtime within each connection interval:

• Residual time, which occurs when the remaining interval is too short to accommodate another full packet exchange.
• End‑of‑event dead time, during which the controller prepares for the next scheduled event and does not permit further transmissions.

The impact of these effects is illustrated in Figure 2. The figure shows that a maximum‑length data packet followed by its acknowledgment occupies approximately 1.4 ms of on‑air time. When the remaining portion of a connection interval is shorter than this duration, the controller cannot schedule another packet exchange, even though some airtime remains available.

Figure 2 Residual airtime and end‑of‑event dead time limit packet scheduling at short connection intervals. A maximum‑size packet and its acknowledgment require approximately 1.4 ms, preventing additional transmissions when insufficient time remains. Source: Microchip

The duration of end‑of‑event dead time varies widely between controller implementations and is not explicitly defined by the Bluetooth specification. In many systems, this behavior can only be identified and quantified through direct measurement.

At short connection intervals, residual and dead time consume a relatively large fraction of each interval, limiting the number of packets that can be transmitted. At longer intervals, this overhead can be amortized across additional packets, improving average throughput if packet scheduling is not otherwise constrained.

Non‑linear throughput behavior

Because residual and end‑of‑event dead time depend on internal scheduling thresholds, Bluetooth LE throughput as a function of connection interval is often non‑linear. Small changes in the connection interval can result in unexpected increases or decreases in throughput, depending on how the interval aligns with controller‑specific timing constraints.

These effects are illustrated in Figure 3, which compares measured throughput across a range of connection intervals under different environmental and platform conditions. In the left‑hand graph, an off‑the‑shelf wireless system‑on‑chip (SoC) is evaluated as both Central and Peripheral. Measurements taken in a shielded environment (orange) show consistently higher throughput than those collected in an open office (blue), indicating the impact of ambient interference on achievable performance.

Figure 3 Measured throughput versus connection interval illustrates non‑linear behavior and environmental sensitivity. Results from both a wireless SoC platform and a Zephyr GATT throughput test show higher throughput in low‑interference conditions and increased variability at longer intervals. Source: Microchip

The right‑hand graph, derived from a Zephyr GATT throughput test, reinforces this behavior while also highlighting the non‑linear relationship between connection interval and throughput. As the interval increases, throughput does not scale monotonically; instead, it exhibits discontinuities and increased variance, particularly at longer intervals where residual and dead time are amortized over more packets.

These results emphasize that throughput cannot be predicted solely from the Bluetooth LE specification. Instead, it’s strongly influenced by platform‑specific scheduling behavior and the prevailing radio‑frequency environment.

Impact of interference

Longer connection intervals typically improve throughput in clean radio‑frequency environments by amortizing residual airtime across additional packets. However, they also increase sensitivity to interference. During long connection events, many packets may be transmitted back‑to‑back; if packet loss or repeated cyclic redundancy check errors occur early in the event, some controllers terminate the event prematurely.

When this occurs, a substantial portion of the connection interval may remain unused, resulting in a sharp reduction in throughput. Shorter connection intervals limit the amount of airtime lost when errors occur and often produce more consistent throughput in noisy environments, albeit with a lower theoretical maximum.

While parameters such as PHY speed, MTU size, DLE, and GATT characteristic length are largely fixed in modern Bluetooth LE systems, connection‑event timing and controller behavior ultimately determine achievable throughput.

The connection interval remains the primary tuning parameter, but its effect is non‑linear and highly dependent on implementation details. For systems that limit packet count per connection event, selecting an interval that closely matches the allowed packet budget is critical. When longer events are supported, throughput gains must be weighed against increased sensitivity to interference.

For design engineers, optimizing Bluetooth LE throughput requires empirical evaluation and platform‑specific characterization rather than reliance on specification‑level performance limits. At a practical level, this places increased importance on controller implementations and protocol stacks that offer fine‑grained configurability on both the Central and Peripheral sides, enabling precise control over connection parameters, event length, and buffering behavior.

Wireless MCU platforms, such as Microchip’s PIC32‑BZ6 multiprotocol wireless MCU family, are representative of designs that emphasize this level of stack configurability and visibility. By allowing engineers to tune behavior symmetrically on both ends of the link and observe the resulting timing effects, such platforms can simplify the process of analyzing throughput bottlenecks and optimizing data transfer performance under real‑world operating conditions.

The ability to measure connection‑event timing, packet scheduling, and error behavior at the controller and stack levels enables more repeatable, data‑driven throughput characterization during development.

Patrick Fitzpatrick is senior technical staff engineer for software at Microchip’s Wireless Business Unit.

Related Content

• Bluetooth low energy (BLE) explained
• The basics of Bluetooth Low Energy (BLE)
• Bluetooth 5 variations complicate PHY testing
• Why Industrial Operations are Turning to Bluetooth Technology
• Secure Bluetooth LE adoption on rise in automotive applications

The post Bluetooth LE throughput: Why real‑world performance falls short of specs appeared first on EDN.

Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

The post The system architect’s sketchbook: The coherency wall appeared first on EDN.

With Keysight Assembly simulation software, automotive manufacturers can virtually test shop-floor processes to identify issues early in development. Late-stage assembly failures drive delays, rework, and recalls. By delivering early insight and integrating with existing ecosystems, the software improves body-in-white assembly workflows.

Developed with automotive OEM partners, Keysight Assembly enables engineers to replicate processes such as part positioning, clamping, and spot welding through guided workflows and templates—without requiring finite element modeling (FEM) expertise. It also provides early visibility into distortion and dimensional risks, shortening production timelines and improving build accuracy.

Keysight Assembly integrates with Keysight’s stamping simulation software, allowing engineers to carry stamped-part data across the process—from forming through assembly—and validate outcomes against pre-production scan data. It also integrates with CAD, product lifecycle management (PLM), Excel, and existing digital workflows without disrupting established practices.

Learn more about Keysight Assembly and related webinars here.

Keysight Technologies  

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Littelfuse’s TDB series of miniature DIP switches uses a 1.27-mm half-pitch, surface-mount design to reduce PCB footprint. The compact devices support high-density layouts where space, reliability, and manufacturability matter.

The switches are available in 2-, 4-, 6-, 8-, and 10-position SPST configurations, with body lengths ranging from 3.67 mm to 13.83 mm depending on position count. Contact ratings of up to 50 VDC, 100 mA (steady state) and 24 VDC, 25 mA (switching) make them suitable for low-power industrial control, as well as consumer IoT and smart home devices. Contact resistance is 100 mΩ maximum, and insulation resistance is 100 MΩ minimum at 100 VDC.

Compatible with automated SMT assembly, the switches feature gold-plated bifurcated contacts and top tape sealing for post-reflow washable processing. They offer a mechanical and electrical life of 1000 cycles and operate over a temperature range of –40°C to +85°C.

The TDB series switches are available in tube or tape-and-reel packaging for high-volume production. Samples can be obtained through authorized Littelfuse distributors.

TDB series product page 

Littelfuse

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The Vishay WLKN-000 two-way Wilkinson power divider/combiner operates from 15 GHz to 20 GHz, centered at 18 GHz. By integrating a resistor with the transmission lines, the compact surface-mount device simplifies system design and saves space in aerospace, defense, and 5G/6G connectivity applications.

Low insertion loss of <0.5 dB below 19 GHz—said to be one of the industry’s lowest­—and return loss of 10 dB to 15 dB enhance system efficiency by reducing power dissipation throughout the signal path. Unlike narrowband or resistive splitters, the WLKN-000 offers high output-to-output isolation of <20 dB at the center frequency. This limits crosstalk, protects downstream amplifiers during combining, and maintains stable performance across parallel RF paths.

The thin-film device operates over a temperature range of −55°C to +155°C, supporting reliable performance in challenging environments. Applications include automotive ADAS, radio transceivers, LEO satellites, base station terminals, drones, weapons guidance systems, and phased-array radar systems.

Samples of the WLKN-000 in 1817 SMD packages are available now; production quantities have a lead time of 20 weeks.

WLKN-000 product page 

Vishay Intertechnology 

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Part of Diodes’ RobustISO family, the API782x series of dual-channel digital isolators delivers 5.7-kVRMS isolation for 1 minute per UL 1577. The devices offer reliable protection for digital control and communication signals in solar inverters, motor control, industrial automation, and data center equipment.

The API782x series meets reinforced and basic isolation requirements across multiple standards, including VDE, UL, and CQC. The devices are rated for an 8-kV peak isolation voltage per DIN VDE 0884-17 and a 12.8-kV peak surge isolation voltage for transient events. Based on Diodes’ reliability calculations for the capacitive isolation barrier, the components offer a predicted operational lifetime exceeding 40 years.

The isolators support data rates up to 100 Mbps and provide a minimum CMTI of 150 kV/µs. The API7820 features both channels in the same direction, while the API7821 provides both channels in the opposite direction with either a high or low default output state. They operate from a 2.5-V to 5.5-V supply voltage and typically consume 2.1 mA per channel at 1 Mbps.

API782x isolators in SO-16WW packages are available through Diodes’ authorized distributors.

API782x product page 

Diodes

The post Digital isolators strengthen industrial systems appeared first on EDN.

Microchip’s dsPIC33AK256MP306 digital signal controller (DSC) combines a 200-MHz, 32-bit core and double-precision FPU with high-resolution PWMs and high-speed ADCs. It also includes a hardware crypto accelerator with support for post-quantum cryptography (PQC). Offered in a 36-pin VQFN package, the DSC saves space and simplifies PCB layout in power conversion, motor control, and intelligent sensing applications.

The dsPIC33AK256MP306’s four PWM generator pairs (eight outputs) deliver fine edge placement (FEP) resolution down to 78 ps. Three 12-bit SAR ADCs operate at up to 40 Msamples/s, alongside 5-ns comparators and 12-bit DACs with slope compensation. These features enable fast, deterministic control loops for high-efficiency DC/DC converters, auxiliary rails, and high-frequency SiC/GaN systems. An integrated touch controller extends support to sensing and HMI functions.

To address growing cybersecurity requirements, the dsPIC33AK256MP306 family supports secure boot, firmware updates, and debug, with hardware-accelerated PQC aligned to emerging standards for connected control systems. Live update capability maintains uninterrupted firmware upgrades in high-availability systems.

Prices for the dsPIC33AK256MP306 start at $1.97 in lots of 5000 units.

dsPIC33AK256MP306 product page

Microchip Technology 

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Four cameras, from two companies. Similar at first glance. Quite different once you zoom in and ponder the picture a while. Which approach is superior? Share your opinions in the comments!

The way this is going, and to remain honest both with myself and all of you, I’m at least for now going to need to start referring to myself as a “camera collector” versus a photographer. I keep accumulating particularly noteworthy (therefore also rare) gear when I come across lightly used, but still reasonably priced, examples on eBay and elsewhere. But I can’t seem to find any spare time to actually use anything in my steadily expanding hardware inventory…at least not yet.

Will I ever be able to retire?

First World problem. I know. My latest examples of acquisition excess fall into the “pocketable” camera category. First off are two Pentax devices. As regular readers may recall from my past writeups, I’m nearing a half-century as a “Pentaxian”, a term originating on a t-shirt I snagged at the company’s CES booth a “few” years ago, prior to the brand’s acquisition by Ricoh. The new-to-me cameras are both members of the company’s “Q” product series: a first-generation Q:

and the successor Q7, skipping (at least so far) the in-between Q10 as well as the Q-S1 concluding iteration. I’d long known about the Q family, which originated a decade-and-a-half back, but enthusiastic reviews from folks such as Micro Four Nerds (the prior blog link is supplemented by the following video) tipped me over the acquisition edge:

Key differences between my two Pentax Q-series cameras include:

• Sensor size: 1/2.3″ on the Q, 1/1.7″ on the Q7, albeit both delivering 12 Mpixel resolution. By the way, the origin of this particular sensor dimension terminology is a story in and of itself, which I’ll save for another day; for now, see here.
• Body construction: Magnesium alloy on the Q, (still-rugged) plastic on the Q7

Note too, for comparison-to-come purposes, that neither model embeds an electronic viewfinder (EVF), although they both include both a pop-up flash and a hot shoe tailored for an optional external flash unit (which can operate in tandem with the pop-up) or a transmitter.

Potato, potahto (or tomato?)

Then I came across Chris Niccolls’ extensive writeup, “The Panasonic Lumix GM-5 Is the Greatest Digital Camera Ever Made”, along with an associated video, at PetaPixel:

Insert hook and reel me in. Regular readers may also recall I’ve been slowly-but-steadily collecting Micro Four Thirds (M43) gear in recent years, now spanning a “few” cameras from two suppliers (Olympus-now-OM System and Panasonic; the Blackmagic Design video cameras I own are both higher-end Canon EF mount-based models), one of which ended up as a gift for my wife. Well, my stable is now even fuller; I bought both a Panasonic Lumix DMC-GM1:

and the successor DMC-GM5:

both of which are also more than a decade old at this point. Here’s another Micro Four Nerds review writeup-plus-video combo, this time focused (bad pun intended) on the GM1:

along with a coverage content tandem on the GM5 (to be clear, I have no affiliation with Micro Four Nerds or any other “influencer” showcased here; I’m just a fan):

Notable differences between the two models include the following:

• Supplemental illumination: pop-up built-in flash on the GM1 (but no hot shoe), hot shoe (but no integrated flash) on the GM5, and
• Viewfinder: backside LCD only on the GM1, added EVF (electronic viewfinder, space-supplanting the predecessor’s pop-up flash) on the GM5

Sensor inconsistencies

Although the four cameras, from two manufacturers’ model lines, are conceptually similar (“pocketable”), their respective implementations are quite different. The inherent tradeoffs leading to each development team’s decisions and resultant product capabilities and limitations are interesting (IMHO at least) to ponder. Note that I have no company-representative insight, either quotable or off-the-record; what follows are just my educated guesses.

As already mentioned, my two Pentax Q variants’ image sensors are both 12 Mpixel in resolution, albeit with differing dimensions; the ~60% larger-area of the Q7’s sensor translates into improved low-light performance and wider dynamic range thanks to expanded pixel pitch and other factors. Conversely, the Panasonic GM1 and GM5’s image sensors are, as far as I can tell, identical, with 16 Mpixel resolutions. That said, M43 image sensors have roughly 9x the surface area of the 1/2.3″ sensor in the Pentax Q, and are still approximately 4x larger (again, surface area, not necessarily active image capture area) of the 1/1.7″ sensor in the Pentax Q7.

Stabilization tradeoffs

All four (total, including my two) Pentax Q family members also supported in-body image stabilization (IBIS), in and of itself a curious choice given the lightweight bodies and accompanying lenses, all of which would seemingly diminish the need for mechanical stabilization of any sort. To wit, neither Panasonic camera mentioned here implements IBIS, nor did any Panasonic-branded M43 lenses support optical image stabilization (OIS), at least at the time that the GM1 and GM5 were in production.

That said, M43 partner then-Olympus did have OIS-inclusive optics in its “glass” portfolio at the time, which could as-needed be used on Panasonic bodies given the two manufacturers’ lens mount compatibility. OIS is, generally speaking, inferior to IBIS, although as I’ve previously noted, it’s particularly effective with telephoto lenses. But it’s arguably better than nothing at all, or to interpolation-based digital image stabilization, for that matter.

Here are a couple of example videos discussing the similarities and differences between IBIS and OIS along with concept examples of both IS forms in action, as well as how they can collaborate:

This one from Canon has a Japanese audio track albeit with English subtitles:

Keep in mind, too, that given the Panasonic cameras’ larger-sized image sensors versus the Pentax alternatives, therefore larger pitch pixels despite the 33.3% higher resolutions, image stabilization was inherently less necessary in the M43 case given that improved light-gathering capability translated into the ability to operate them at blur-suppressing higher shutter speeds.

Space constraints

The added stabilization hardware surrounding the image sensor in the Pentax Q-family bodies, coupled with the desire to maintain their compact weight and dimensions, also compelled the company to dispense with a mechanical shutter, at least in the bodies themselves. Instead, a subset of the then-available eight-lens suite embedded mechanical leaf shutters in the lenses. More broadly, an “electronic shutter” implemented in the image sensor was available in all body-plus-lens cases, albeit with “rolling shutter” and other tradeoffs.

A hollow victory?

Ironically, in spite of these likely-difficult tradeoff decisions made by its development team, Pentax still ended up with Q-series camera bodies that were (slightly) larger than that of the Panasonic DC-GM1, as Robin Wong, another well-known photo enthusiast “personality”, notes in his Pentax- and Panasonic-themed blog posts and videos:

I’ve got more to say about the two companies’ contrasting approaches to the “pocketable” camera market, including the tradeoffs between multi-supplier standard and sole-sourced proprietary lens mounts …but I’ll save that for another day and writeup (or few). For now, I’ll wrap up my writeup and hand the keyboard to you for your so-far thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN Magazine.

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• Scrutinizing a camera flash transmitter
• Multi-source vs proprietary: photography case studies
• SD card speeds: question your assumptions
• Tamron’s TAP-in Console: A nexus for camera lens update and control

The post Engineering tradeoffs: a camera case study appeared first on EDN.

Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

The post The system architect’s sketchbook: The AI hiring frenzy appeared first on EDN.

Multicore processing boosts performance and energy efficiency in many coding situations. Bare-metal algorithms further enhance these benefits.

Many embedded firmware engineers have seemingly not yet tried multicore processing. Using processors with more than one core can actually make your architecture and coding easier. And the part you may find surprising is that setting up and using multicores processors is very easy to do.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Typically, multicore programs are used in systems with an OS, but if you’re like me, my projects are typically bare-metal. I have long used multicore under an RTOS but have historically avoided multicore on bare-metal systems. But ever since I discovered how easy it was to use multicore on bare-metal, it has become part of my go-to design architecture.

Let’s look at how this is accomplished. The examples and discussions that follow are based on using an RP2040 two-core microcontroller with code developed on an Arduino IDE. RP2040 development boards can be found for around $5 USD. Also, although I will discuss a two-core setup, expanding to larger core count processors will use the same concepts.

So why didn’t I use multicore designs sooner? I had some concerns that there were difficulties that I wasn’t ready to take on. Some of these were:

• How to keep each core’s code separate
• How to start multiple cores
• How the cores talk to each other (i.e., how to transfer data among cores)
• What peripherals each core can use; do they need to be checked out or registered, for example

It turns out that all these issues are actually very easy to deal with. Let’s look at them one at a time.

First, how do you separate the code for each core? In a single-core Arduino C program there are two major sections: the setup section (which begins like this: void setup()) and the loop section (which begins like this: void loop()). If you are using two cores, the first core, core 0, will use these sections just as used in a single-core design.

The code for the second core, core 1, will have a function defining its main loop. Let’s name it core1_main. Then in the core 0’s setup section, enter the line multicore_launch_core1(core1_main);. That line will start the function, called core1_main, running on the second core. (Note: I find it much cleaner to put the core 1 code in a separate tab in the Arduino IDE.) Unlike the main loop in an Arduino C program, you will need to wrap the code in core 1 in a while(1); loop. Another item to include is the line #include "pico/multicore.h" at the top of the code.

Be aware that there are other approaches for setting up code in the second core. They include methods that allow core 1 to use its own setup function. Use your favorite AI or other research tool to discover other methods of setting up code and executing code on the second core.

Here’s a very simple example having each core blinking its own LED:

#include #include "pico/multicore.h" // ----------------------------- // Core 1 code // ----------------------------- void core1_main() { pinMode(14, OUTPUT); while (1) { digitalWrite(14, HIGH); delay(500); digitalWrite(14, LOW); delay(500); } } // ----------------------------- // Core 0 code // ----------------------------- void setup() { pinMode(15, OUTPUT); // Start core 1 multicore_launch_core1(core1_main); } void loop() { digitalWrite(15, HIGH); delay(300); digitalWrite(15, LOW); delay(300); }

This example gives you an idea of how to get the two cores executing their own tasks. Typically, though, you would want to have some sort of communication between the cores. This can be achieved very simply by using a variable that each core can see and modify. It turns out that the entire memory space of the microcontroller can be seen and modified by either core. So, if you define a global variable at the top of the code (just below the #include statements), it can be used to transfer data between cores.

Make sure that the variable is tagged as volatile as it can change at any time. Also remember that the RP2040 is a 32-bit microcontroller and reading and writing 64-bit values is not atomic, so care must be taken to not read a transferred 64-bit value before both halves have been transferred. A simple flag can help here. This simple method of using shared memory to transfer data is easy but can be dangerous if you’re not careful—similar to global variables—but bare-metal developers typically like this tight control over resources.

This method of transferring data is good for simple tasks, but you may want to use FIFOs to handle more data and to remove some syncing issues. These are not difficult to write, and you’ll also find pre-written packages online. For more sophisticated programs, you can investigate mailboxes, semaphores, flags, etc. from various sources…but now we’re getting into RTOS functions.

Now let’s look at sharing peripherals between cores. In our bare-metal architecture, the best explanation is that any core can use any peripheral at any time. This situation is both good and bad. Good because there are no flags to set, no checkouts that need to happen, and no negotiations to be made: just use the peripheral. Bad in the sense that without some form of coordination the two cores can attempt to set up the same peripheral at the same time, in different configurations.

What I have found useful in my designs is that I have typically separated the code in the two cores such that each core always uses peripherals that are not used by the other core. If that not the case in your designs, you may want to implement a resource lock method using flags. Related is the interesting fact that both cores can use the serial port (only configured by one core) without any necessary handshaking or flags. Do note, though, that the serial communications will be interleaved. That said, I find this very handy since I can Serial.print() from either core during debugging.

Let’s answer one last question: why do I want to use more than one core? The first reason is the obvious one: you get more computing power. But more than that, by separating tasks from each other you may find coding easier and cleaner. That’s because there are no concerns about the multiple tasks fighting for cycles, especially for time-sensitive tasks. Also, if you are using multiple interrupts, separating these tasks between cores can remove the complexity of interrupts occurring at the same time and thereby holding off one or the other. Another benefit is that you may have faster response to events happening as you can essentially monitor and respond to twice as many events.

Here’s another code example using some of the concepts discussed earlier. This code uses core 1 to monitor the serial port looking for a G or an R. If it sees a G, it sets the shared variable led_color to 1. Core 0 continuously monitors led_color and turns on the green LED if the led_color is 1. Similarly, if core 1 sees a R it changes led_color to 0 and core 0 then then turns on the red LED:

#include #include "pico/multicore.h" // ---------------------------- // LED pin assignments // ---------------------------- #define RED_LED_PIN 14 #define GREEN_LED_PIN 15 // ---------------------------- // Shared variable between cores // 0 = RED, 1 = GREEN // ---------------------------- volatile int led_color = 0; // ====================================================== // Core 1: Serial monitor // ====================================================== void core1_entry() { while (!Serial) { delay(10); } while (1) { if (Serial.available() > 0) { char c = Serial.read(); if (c == 'G' || c == 'g') { led_color = 1; Serial.println("Set LED = GREEN"); } else if (c == 'R' || c == 'r') { led_color = 0; Serial.println("Set LED = RED"); } } delay(2); } } // ====================================================== // Core 0 setup // ====================================================== void setup() { Serial.begin(115200); pinMode(RED_LED_PIN, OUTPUT); pinMode(GREEN_LED_PIN, OUTPUT); // Launch Core 1 multicore_launch_core1(core1_entry); } // ====================================================== // Core 0 loop — LED logic now lives here // ====================================================== void loop() { if (led_color == 1) { digitalWrite(GREEN_LED_PIN, HIGH); digitalWrite(RED_LED_PIN, LOW); } else { digitalWrite(RED_LED_PIN, HIGH); digitalWrite(GREEN_LED_PIN, LOW); } delay(5); }

It may now be becoming clearer to you where the benefits lie in using more than one core. Think of something more complex, say, a program that monitors the serial port for modifications to settings, along with a high-speed ADC being read with a tight tolerance on jitter. Having the serial port code running on one core and the ADC code in another core would make this combination much easier to get working cleanly.

Give multicore code design a try! It’s easy, I think you’ll find lots of uses for it, and you’ll also find it makes coding easier and more organized.

p.s. Both pieces of code shown in this article were initially written by CoPilot per author instructions. The author subsequently only made minor modifications.

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

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• The next RISC-V processor frontier: AI
• Partitioning to optimize AI inference for multi-core platforms
• Multicore architectures, Part 1 – Key drivers
• Multicore architectures, Part 2 – Multicore characteristics
• Multicore architectures, Part 3 – Communications and memory
• Multicore architectures, Part 4 – Application specificity

The post Give bare-metal multicore processing a try appeared first on EDN.

The Wireless Broadband Alliance (WBA) has released guidelines to strengthen security, privacy, and trust across Wi-Fi networks. These guidelines help organizations reduce exposure to common Wi-Fi threats, improve user trust, and simplify interoperability across networks and partners.

The guidelines also address the growing need for carrier-grade security that aligns with user expectations.

1. Prevent connections to rogue and fake networks

Wi-Fi devices must validate network certificates before sharing credentials by using 802.1X and Extensible Authentication Protocol (EAP). That ensures users connect only to legitimate networks, significantly reducing the risk of evil-twin and rogue access point (AP) attacks.

2. Protect data over the air

Data traffic confidentiality and integrity can be ensured by enforcing WPA2/WPA3-Enterprise with Advanced Encryption Standard (AES) and Protected Management Frames (PMF). That prevents passive sniffing, de-authentication attacks, and many man-in-the-middle techniques, bringing Wi-Fi security closer to cellular-grade protection.

3. Preserve user identity privacy without breaking compliance

Balance privacy and traceability by using anonymous identities, encrypted inner identities, pseudonyms, and chargeable-user-identity (CUI). That protects personally identifiable information during authentication while still enabling lawful intercept, billing, and incident handling when required.

4. Secure credentials end-to-end

Credentials are protected throughout their lifecycle, from device to network to backend systems. Secure OS key stores on devices and hardened credential storage in identity provider systems. So, tamper-resistant SIMs and USIMs for mobile credentials reduce the risk of large-scale credential theft.

5. Harden the entire access network

Security extends beyond the radio link. Physical security of access points and controllers, encrypted AP-to-controller links, secure backhaul design, and local breakout architectures ensure that data traffic remains protected across the full network path.

6. Secure AAA and roaming signaling

This guideline recognizes that the control plane is often overlooked; so, it strongly recommends RADIUS over TLS or DTLS for all AAA and roaming exchanges. That protects authentication and accounting traffic from interception or manipulation, aligning with OpenRoaming and WRIX requirements.

7. Add layer-2 protections against lateral attacks

Layer-2 traffic inspection, client isolation, proxy ARP, and multicast and broadcast controls are employed to limit damage even if a malicious device connects and thus reduce client-to-client attacks such as ARP spoofing and broadcast abuse.

8. Enforce security through federation and governance

Security is reinforced not only technically but operationally through OpenRoaming and the WRIX legal framework. As a result, security requirements, responsibilities, and privacy obligations can be consistently enforced across operators, identity providers, and hubs.

Related Content

• Securing a wireless network–The basics
• How to achieve better IoT security in Wi-Fi modules
• How to make 802.11 systems combine security with affordability
• 10 things to consider when securing an embedded 802.11 Wi-Fi device

The post 8 Wi-Fi security guidelines issued by Wireless Broadband Alliance appeared first on EDN.

Tracking down rodentia (or otherwise)-caused cable cuts, and differentiating them from normal open circuits, is critical. Evolving the circuit design for expanded functionality makes it even more valuable.

It’s just part of the job.  Every design engineer learns early (if not so happily) about the inevitable necessity of detecting, confronting, and swatting “bugs” in circuitry.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In a recent Design Idea, frequent contributor Jayapal Ramalingam extends this art of circuit defect detection and deletion from dealing with mere insects to coping with something much more formidable: rats!

With so many rodents and creatures around the plant, a cable cut can happen at any time

The cables being subjected to those toothy threats transport signals from field contacts monitoring pressure, temperature, valve position, limit switches, manual operator inputs, etc., to process control systems. The possible consequences of mistaking an undetected cable break for an open contact range from the merely inconvenient to the catastrophic. An example of the latter might be a critical valve that’s actually open but erroneously read as closed—viz., Three Mile Island?

Mr. Ramalingam’s clever solution to the problem of undetected cable cuts is a current transmitter design that adds a third current level to the two that are inherent to an ON/OFF contact.  Thusly.

20mA = contact closed, cable intact
4mA = contact open, cable intact
0mA = cable cut, contact state unknown

It therefore explicitly verifies cable continuity, preventing the mistaking of an open circuit for an open contact. See his article for details.

Mr. Ramalingam’s circuit works, is proven, and has nothing significantly wrong with it.  Its utility, however, is limited to that single function.  It might be significantly more convenient and thrifty if its role could be combined with another in a multipurpose design, provided, of course, that said design would be of no greater cost or complexity than the single-purpose transmitter.  Figure 1 and Figure 2 show such a circuit adapted from an earlier article.

Figure 1  0/20mA to 4/20mA current loop converter.

Figure 2 Field contact OFF/ON to 4/20mA current loop converter.

Note that the circuits are identical, so that only one design needs to be fabricated, documented, and stocked.

Calibration in this new role is quick and simple and completed in a single pass:

1. Open contact.
2. Tweak 4mA adj for 4mA output.
3. Close contact.
4. Tweak 20mA adj for 20mA output.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content 

• Is your PLC/DCS reading the field contacts reliably?
• Silly simple precision 0/20mA to 4/20mA converter

The post Double-duty current loop transmitter appeared first on EDN.

Flagship consumer electronic device launches are among the most operationally complex events in modern engineering. They require years of coordination across hardware, silicon, RF, software, operations, supply chain, and manufacturing. Yet, despite mature processes and experienced teams, flagship programs remain vulnerable to schedule volatility.

The root cause is rarely inadequate engineering talent. More often, it’s structural. Manufacturing realities are integrated too late into architectural decision-making. System-level validation, when deployed early and continuously, functions not as a downstream quality checkpoint, but as an organizational mechanism for compressing schedule risk before capital and timeline commitments are locked.

Financial exposure at flagship scale

At flagship scale, schedule slip is not simply an engineering inconvenience. It’s a material financial event.

Apple’s fiscal year 2025 results reported approximately $416 billion in annual revenue, with iPhone revenue representing roughly half of total sales. Samsung’s Mobile Experience division reported approximately $26 billion in quarterly revenue during. For programs operating at this scale, a one-month delay during a peak launch cycle can defer revenue comparable to the annual revenue of many mid-sized technology firms.

Even outside tier-one OEMs, launch timing directly impacts channel readiness, carrier alignment, ecosystem momentum, and competitive positioning. In high-volume hardware, schedule is strategy.

The challenge is that many launch delays are not caused by unforeseen global disruptions, but by late-stage design changes triggered during production ramp. Industry analyses consistently show that a significant portion of late engineering change orders originate from integration and manufacturability issues that were technically detectable earlier in the development cycle.

When these issues surface during ramp, optionality has already collapsed. Tooling is frozen, suppliers are capacity-allocated, and marketing calendars are committed. At that stage, validation confirms risk rather than preventing it.

Why component-level validation fails at scale

Traditional validation strategies are optimized for component correctness. Subsystems are tested against modular specifications, and readiness decisions are based on aggregated subsystem pass rates. This approach ensures that parts function independently; however, it does not guarantee that the system functions reliably under real-world, high-volume conditions.

Many failure modes emerge only during full-system interaction. Digital signal interference, RF coexistence conflicts, thermal coupling between tightly integrated subsystems, and parasitic effects often cannot be fully replicated in isolated bench testing.

For example, a high-speed display flex cable may pass standalone signal integrity validation. During system-level engineering verification testing (EVT) under real RF load, that same cable can radiate broadband noise that desensitizes the primary cellular receiver. The result is a coexistence failure that frequently forces late-stage shielding changes or mechanical redesign.

Similarly, assembly processes introduce stress, tolerance stack-up, and handling variability that are absent in early prototypes. Component-level validation ensures parts are defect-free. It does not predict how those parts behave when integrated and manufactured at scale. The consequence is predictable: issues emerge when yield sensitivity tightens during ramp.

A defect observed in 1 out of 100 early validation units translates into 10,000 defective devices at a one-million-unit scale. At millions of units, small deltas compound rapidly.

The design–manufacturing impedance mismatch

A recurring root cause of late-stage validation failures is misalignment between design optimization and manufacturing constraints. Design teams optimize for performance, power efficiency, compact form factor, and cost targets. Manufacturing teams optimize for yield stability, throughput, repeatability, and process capability. Both are correct within their domains.

Failure occurs when manufacturing sensitivity is not structurally integrated into architectural trade-off decisions. In cross-functional reviews, performance metrics are often presented without quantified yield sensitivity analysis. Design freeze decisions may proceed based on functional validation, while manufacturing risk remains probabilistic rather than modeled. Schedule pressure can incentivize accepting integration risk with the assumption that ramp will resolve residual issues.

System-level validation acts as the translation layer between these domains. When embedded early, it exposes divergence between design intent and production feasibility while design changes remain affordable. The cost-of-change curve, widely cited in engineering economics literature, demonstrates that defects discovered during mass production can cost orders of magnitude more to correct than those identified during early design phases. Whether the multiplier is 10x or 100x depends on context, but the direction is consistent: late discovery amplifies cost and schedule exposure.

System-level validation as risk compression

Reframing system-level validation as a schedule-risk compression mechanism changes how engineering organizations deploy it. Risk compression means reducing the variance between projected and actual ramp performance before high-volume commitments are made. It means narrowing the gap between modeled yield and early ramp yield while architectural flexibility still exists.

Consider a ten-million-unit program targeting 97% yield but only achieving 94% during early ramp. A 3% delta produces 300,000 additional defective units. At a $500 bill-of-materials cost, that equates to $150 million in direct exposure: before accounting for logistics, containment actions, rework, warranty impact, and brand degradation.

When system-level validation is embedded earlier in the development cycle, integration uncertainty is resolved before tooling freeze and capacity allocation. Manufacturing sensitivity becomes an architectural input, not a downstream constraint. Validation shifts from reactive confirmation to proactive risk reduction.

Governance implications for senior managers

For senior engineering and manufacturing managers, the implication is structural. System-level validation must be positioned upstream of design freeze, not solely before ramp. In practice, this requires:

• Upstream integration: Embedding manufacturing engineering into early architecture discussions.
• Quantified sensitivity: Requiring quantified yield sensitivity data before design freeze.
• Strategic alignment: Aligning validation milestones with major financial commitments.
• Holistic ownership: Elevating system-level risk ownership to program leadership rather than distributing it across siloed subsystem teams.

Organizations that treat system-level validation as a downstream quality function implicitly accept schedule volatility as a cost of doing business. Organizations that embed it as a bridge between design architecture and manufacturing execution create structural advantage. They stabilize flagship launch timelines, reduce ramp inefficiency, and preserve optionality when trade-offs are still affordable.

Ayokunle Oni is a system engineering program manager at Apple, where he helps coordinate the iPhone hardware design and engineering process across cross-functional teams. He specializes in system integration and validation and has led complex engineering programs from concept through production, working closely with global manufacturing and vendor partners.

Related Content

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• Early verification and validation using model-based design
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• Hardware Verification: What AI Gets Right When It Generates Your Testbench — and What It Misses

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Electric motors are everywhere—from the cars we drive to the appliances in our homes—but most rely on rare earth magnets that come with high costs and environmental challenges. A new wave of innovation is changing that story. Magnet-free electric motors are proving that smart engineering can deliver powerful performance without depending on scarce materials.

By removing rare earths from the equation, these designs promise cleaner supply chains, more sustainable production, and fresh opportunities for industries ranging from electric vehicles to renewable energy. It’s a shift that could redefine how we think about powering the future.

Why rare earths matter

Rare earth magnets, especially neodymium and dysprosium, have been the secret ingredient behind the compact, high-torque motors that power everything from electric vehicles to wind turbines. Their ability to deliver strong magnetic fields in small packages has made them indispensable in modern motor design.

But there is a catch: mining and processing rare earths is energy-intensive, environmentally challenging, and geographically concentrated in just a few regions of the world. This creates supply chain risks, price volatility, and sustainability concerns that ripple across industries.

By understanding why rare earths became so central to electric motors, we can better appreciate the significance of moving beyond them—and why magnet-free designs are more than just an engineering curiosity. They represent a strategic shift toward resilience, affordability, and cleaner technology.

How do you pull without a magnet

So how do you build a motor without magnets? The answer lies in clever engineering that takes advantage of the natural properties of materials and the geometry of the motor itself. Instead of relying on powerful magnets to create motion, magnet-free designs use principles like reluctance torque—where the rotor naturally aligns with the path of least magnetic resistance—or induction, where currents in the rotor generate the force needed to spin.

These approaches may sound technical, but the idea is simple: by rethinking the fundamentals, engineers can coax motors into delivering the same performance we expect, without the rare earth magnets. The result is a motor that can be lighter, more affordable, and easier to manufacture at scale. And because these designs lean on widely available materials, they sidestep the supply chain bottlenecks that have long plagued magnet-based motors.

Why it matters

Magnet-free motors are not just an engineering breakthrough; they are a practical step toward cleaner, more resilient technology. By removing rare earths, manufacturers can cut costs, ease supply chain pressures, and reduce environmental impact.

The benefits ripple across industries: in electric vehicles, they promise more affordable and sustainable mobility; in renewable energy, they support wind turbines and other systems without relying on scarce materials; and in industrial machinery, they offer reliable performance with simpler, more scalable production.

In short, magnet-free motors matter because they combine innovation with real-world impact, helping power a future that is smarter, greener, and less dependent on limited resources.

Figure 1 Today’s magnet-free electric motors deliver high efficiencies for heavy-duty and commercial vehicle applications. Source: Advanced Electric Machines

Working principles of magnet-free motors

For learners, makers, and anyone with a curious engineering mind, the real excitement lies in how magnet-free motors actually work. Instead of relying on rare earth magnets to generate motion, these designs tap into fundamental physics—using reluctance torque, induction, or clever rotor geometry to produce rotation.

Think of it as guiding the motor to “want” to align itself with paths of least resistance, or harnessing currents induced in the rotor to drive movement. The beauty is that these principles are elegant, scalable, and rooted in concepts every engineer encounters early in their studies. By revisiting the basics with fresh eyes, magnet-free motors show how fundamental science can be reimagined to solve modern challenges.

At their core, magnet-free motors rely on clever ways to generate motion without permanent magnets, using principles that every curious engineer can appreciate.

That is, reluctance motors exploit the tendency of a rotor to align with the path of least magnetic resistance, producing torque through geometry rather than magnets. Induction motors create rotation by inducing currents in the rotor with alternating fields, a design that is simple yet powerful. Synchronous reluctance motors combine aspects of both, offering efficiency and control that rival traditional designs.

Each approach shows how fundamental physics—magnetic fields, current flow, and mechanical alignment—can be harnessed in different ways to achieve the same goal: reliable rotation. For learners, makers, and innovators, these principles are a reminder that rethinking the basics can unlock new possibilities for sustainable engineering.

Figure 2 A synchronous reluctance motor demonstrates magnet‑free operation with smooth torque characteristics. Source: ABB

It’s important to note that not all reluctance motors are the same. A synchronous reluctance motor (SynRM) runs in step with the supply frequency, using flux barriers in the rotor to align with the path of least magnetic resistance, delivering smooth torque and efficiency. A switched reluctance motor (SRM), by contrast, relies on sequentially energizing stator phases to pull a simple steel rotor around; it’s rugged and powerful but tends to be noisier with more torque ripple.

Sitting between these designs is the permanent magnet assisted SynRM (PMA‑SynRM), which adds small magnets to stabilize the field and boost efficiency while still using far fewer rare earths than traditional permanent magnet motors. Together, these variations show the spectrum of approaches engineers use to balance performance, simplicity, and sustainability.

Unlocking SynRM performance with VFDs

While SynRMs deliver smooth torque and efficiency, they typically need a variable frequency drive (VFD) to start and stay synchronized with the stator’s rotating field. The VFD supplies control frequency and voltage, making these motors flexible but dependent on modern power electronics.

By contrast, older induction motors could start “across the line”—plugged directly into the grid—though at the cost of high inrush currents and less precise control. This reliance on VFDs underscores how magnet-free motor innovation is inseparable from advances in drive technology, reminding designers that motor and electronics progress go hand in hand.

As a worthy side note, VFD is the electronic brain that makes modern motors flexible. By adjusting the frequency and voltage, it lets a motor start gently, avoid the punishing inrush currents of direct grid connection, and run at variable speeds with precision. For SynRMs, the VFD is essential—it keeps the rotor locked in sync with the stator’s rotating field. Older induction motors could start “across the line” without such electronics, but that simplicity came at the cost of efficiency and control.

Figure 3 A compact VFD module suitable for driving 3-phase SynRM motors supports efficient control in both industrial and household applications. Source: Mean Well

From a design standpoint, the dependence on VFDs is both enabling and constraining. On the enabling side, drives unlock efficiency gains, smoother torque, and precise speed control that make SynRMs competitive with permanent-magnet machines.

On the constraining side, they add cost, require integration expertise, and shift part of the reliability burden from the motor to the electronics. For engineers, it means evaluating magnet-free motors is not just about rotor geometry; it’s about the total system, where sustainability benefits must be balanced against drive complexity and lifecycle economics.

Note that modern control strategies such as field-oriented control (FOC) and sensorless vector control extend the capabilities of these VFDs. FOC regulates stator currents to deliver precise torque and flux, while sensorless vector methods estimate rotor position without mechanical sensors, reducing cost and improving reliability. Together, they allow SynRMs—and other magnet-free designs—to match the responsiveness and efficiency of permanent-magnet machines.

Quick FOC take: Field‑oriented control does not have to be daunting. For makers eager to experiment, compact FOC shields/modules provide a straightforward, low‑power entry point. The Arduino SimpleFOC Shield is a practical example, lowering barriers and making hand-on exploration accessible.

Figure 4 SimpleFOC Shield empowers accessible FOC experimentation for Arduino users. Source: Author

Next, getting into design significance, the combination of magnet-free motor design, advanced VFDs, and intelligent control strategies has broad implications. Engineers gain access to motors that are lighter, more affordable, and easier to manufacture at scale, while sidestepping rare-earth supply chain constraints.

In the long run, magnet-free motors not only reduce dependence on scarce materials but also align with global sustainability goals, positioning them as a cornerstone of next-generation electrification across industries spanning from manufacturing to consumer appliances.

Closing thoughts

Magnet-free motors are steadily moving from concept to reality, driven by both maker ingenuity and industry ambition. With BMW and Mahle advancing externally excited synchronous motors to reduce rare-earth dependence, and Tesla having already demonstrated the scalability of induction motors, the message is clear: sustainable propulsion can deliver performance without compromise.

For makers and engineers alike, this is an invitation to experiment boldly and rethink motor design fundamentals, because the next leap in innovation may emerge as much from a personal workbench as from an automotive R&D lab.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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Following the introduction of Industry 4.0, power electronics are becoming more significant in both digital and industrial infrastructures. Factories, energy systems, and data centers are getting smarter and more connected. This requires efficient power solutions that offer high power density and can scale with them.

Semiconductors are expected to deliver performance beyond the limits of conventional silicon-based power devices. Wide-bandgap (WBG) materials such as silicon carbide (SiC) and gallium nitride (GaN), as well as novel approaches to designing, packaging, and controlling power devices, are helping achieve the main goals of Industry 4.0: efficiency, flexibility, scalability, and intelligence.

800-VDC power architecture

One of the most significant changes introduced in the power system is the move of data centers to 800-VDC distribution, as detailed in an Nvidia white paper. Traditional systems that use AC and low-voltage DC can’t keep up with the speed and growth needs of AI-based workloads. High-performance computing clusters, especially those that support generative AI and machine learning, demand more power and should use it as efficiently as possible.

By raising the distribution voltage to 800 VDC, operators can reduce the current for a given power level. This approach offers the benefits of reduced I2R losses and the ability to use thinner wires. Overall, efficiency can thus be increased, and more power can be integrated in the same area or volume. The design also becomes less complicated because there are fewer steps in the conversion process.

This new architecture directly affects semiconductor requirements. Power devices need to perform well at higher voltages with minimum loss and support fast switching. Chipmakers and manufacturers are developing power solutions to support Nvidia’s 800-VDC power architecture reference design for next-generation AI factories to improve efficiency and reduce power losses.

To support gigawatt-scale AI factories based on an 800-VDC power architecture, Flex, for example, introduced a new reference design (Figure 1) that integrates power, liquid cooling, and compute capabilities into a modular assembly. This prefabricated solution streamlines the implementation of 800-VDC architectures and, according to the company, enables 30% faster deployment than conventional systems.

Figure 1: Flex’s reference design accelerates giga-scale AI factory deployment through a modular and preassembled structure. (Source: Flex) SiC semiconductor advances

Due to its physical properties, such as high breakdown voltage, low switching losses, and high thermal conductivity, SiC can operate efficiently and provide high reliability in high-voltage and high-power environments.

At the high-voltage end, SiC devices are going into the multi-kilovolt range. More devices are gaining ratings above 1,200 V, making SiC more common in places where silicon-based power devices used to be the norm.

Navitas Semiconductor recently announced the availability of samples for its 2,300-V and 3,300-V high-voltage SiC products, specifically designed to increase efficiency in AI data centers, power grids, and renewable energy infrastructure. The devices, available in discrete, module, and known-good-die formats, are based on the company’s Trench-Assisted Planar architecture.

This semiconductor structure optimizes electric-field management, significantly reducing voltage stress and improving avalanche robustness compared with traditional trench- or planar-MOSFET designs. It also achieves lower RDS(on) at high temperatures and better current spreading.

As power devices improve, their packaging becomes increasingly crucial to the overall performance of the system. Newer packages are designed to reduce parasitic inductance, improve thermal management, and handle larger current densities.

These advancements in packaging technology enable higher performance and efficiency gains. Texas Instruments (TI), for example, recently unveiled two isolated power modules for applications from data centers to electric vehicles that require improvements in power density, efficiency, and safety. The UCC34141-Q1 and UCC33420 isolated power modules leverage TI’s IsoShield technology, which copackages a high-performance planar transformer and an isolated power stage, providing functional, basic, and reinforced isolation capabilities.

TI’s proprietary multichip packaging solution claims up to 3× higher power density than discrete solutions in isolated power designs and shrinks the solution size by as much as 70% by packing more power into smaller spaces. Applications range from factory automation PLC modules and EV and powertrain systems to grid infrastructure and rack and server power.

Wolfspeed Inc. has revealed that its 300-mm SiC platform, leveraging patent-pending innovations, is set to become a key material component for AI and high-performance computing (HPC) packaging by the late 2020s. Figure 2 shows a conceptual demonstration of an interposer substrate built on the company’s 300-mm SiC wafer. According to Wolfspeed, the SiC substrate helps to improve the thermal, mechanical, and electrical performance of next-generation packaging structures required by AI and HPC systems.

Figure 2: Conceptual demonstration of a 100 × 100-mm interposer substrate enabled by Wolfspeed’s 300-mm SiC wafer (Source: Wolfspeed Inc.) GaN advances

While SiC excels at high voltages, GaN is suited for low- and medium-voltage applications, especially below 650 V. This semiconductor can switch at high frequencies, up to the megahertz range, with very low power loss, making power converters more efficient and smaller and requiring less cooling.

One important trend in GaN’s growth is integration. For example, Schottky diodes could be incorporated into GaN transistors to reduce losses from reverse conduction and make it easier to build power stages. Following this concept, Infineon Technologies AG has introduced the industry’s first industrial-grade GaN power transistors featuring an integrated Schottky diode.

Traditionally, GaN devices in hard-switching applications suffer from higher power losses due to their large body-diode voltage drop. This issue gets worse during the “deadtime” of a power controller. Engineers previously solved this by adding an external Schottky diode or complex controller tuning, both of which increase design time and costs. The new CoolGaN transistor G5 family solves this by integrating the diode directly into the transistor, reducing deadtime losses and boosting overall system efficiency.

Another important trend is bidirectional switching, where new GaN devices can block current and voltage in both directions. This simplifies converter topologies and requires fewer components. This capability is especially crucial for applications such as energy storage systems, EV chargers, and power-factor-correction circuits.

Renesas Electronics Corp. has introduced the industry’s first bidirectional switch (TP65B110HRU) based on depletion-mode (d-mode) GaN technology (Figure 3). Most current high-power conversion systems rely on unidirectional silicon or SiC switches that block current in only one direction. This limitation forces engineers to design multi-stage circuits or use “back-to-back” switch configurations, which significantly increases component count and reduces overall efficiency.

By integrating bidirectional blocking into one GaN product, this technology enables “single-stage” power conversion. The high switching speed and low stored charge of GaN also enable higher power density and switching frequencies. According to the company, this architecture has demonstrated over 97.5% power efficiency, providing a solution well-suited for AI data centers, on-board EV chargers, and renewable energy applications.

Figure 3: Renesas’s TP65B110HRU high-voltage d-mode bidirectional GaN switches (Source: Renesas Electronics Corp.) Solid-state transformers

Solid-state transformers (SSTs) are a huge change in how power is transferred and controlled. SSTs are not like ordinary transformers, as they use power electronic converters to modify, split, and control the voltage.

Using this technology, more advanced features become available. These include two-way power flow, real-time voltage management, and the capacity to operate with renewable energy sources. Smart grids, microgrids, and Industry 4.0 all need SSTs that can change rapidly and easily. For SSTs to grow, WBG semiconductors are particularly significant.

For example, Infineon and DG Matrix, a company specializing in SSTs, have partnered to integrate SiC semiconductors into the Interport multiport SST platform. This collaboration aims to modernize the connection between the public grid and energy-intensive applications such as AI data centers, EV charging, and industrial microgrids.

Unlike traditional copper- and iron-based transformers, SSTs are semiconductor-based devices. They are smaller and lighter, accelerating deployment and providing higher power density. Adopting Infineon’s SiC technology, these SST systems achieve improved efficiency and reliability.

The technology enables direct power conversion from medium-voltage grid levels to the low-voltage requirements of modern digital infrastructure. DG Matrix plans to scale toward higher-voltage platforms to support the global rollout of high-performance power infrastructure.

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The technology treadmill never stops, and so it goes with Blink’s second-generation hub device versus its predecessor.

Last month, I compared the conceptually similar (and thankfully, concurrent-use RF-compatible) hub-and-spokes approaches used by Blink and TP-Link for their respective battery-operated device ecosystems. Blink’s particular hub implementation, the first-generation Sync Module still in active use at my residence to this very day, doesn’t support local recording storage, only to the cloud, a service which fortunately is free for me (albeit in a somewhat limited-duration fashion) as a legacy customer.

(it’s more recently been moved from my office to the laundry room, and as regular readers know from other recent writeups, that Belkin Wemo smart switch above it is also now DOA)

Gratis capacity for non-geriatrics

But when I saw an inexpensive “for parts only” second-generation Sync Module available for sale on eBay, I still jumped on the opportunity, driven by curiosity. Primary differences between the two generations include, for the more recent model:

• A functionally active embedded USB-A connector, for mating with a flash stick or other mass storage device for local recording storage
• More robust, therefore more responsive, integrated processing, and
• Claimed wider-range Wi-Fi coverage

Turns out the device itself works fine, at least to the degree I’ve tested it so far; I was able to factory-reset it, and the Blink app can now “see” it (although I haven’t yet set it up). The only thing missing was the originally included AC/DC adapter with a micro-USB output, but I’ve got plenty of spares of those already, along with the one currently fueling its same-dimensions precursor in case I ever decide to upgrade in situ. So, let’s dive inside and see what we can learn, both in an absolute sense and relative to the first-gen Sync Module that I took apart…yikes….nearly seven years ago. Shall we?

Here’s today’s patient, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

All-important FCC ID (2AF77-H2121520):

Micro-USB power input:

and now-functional USB-A data port:

Open sesame

I wish everything I tore down was this easy to open up:

At this point…

Let’s pause a moment for some interesting (at least to me) background info. In re-reading my archaic first-gen teardown verbiage, I noted that I’d written (among other things) the following:

Today’s teardown candidate is that very same Sync Module. The one currently in use with my Blink XT cameras matches their black color; this particular one was purchased standalone off Ebay specifically for teardown purposes and is white (and previously used). Color scheme deviations aside, the two models are functionally identical.

I was right with my “identical” claim, at least with respect to the functional angle. And I’d already noted the color deviation. But further (and more recent) research has enlightened me that there were other (non-functional) hardware differences between my in-use device and the one I took apart, too. Blink actually brought to production multiple main variations of the first-generation Blink Sync Module (including a low-volume initial “launch” iteration), along with region-specific tweaks of each variant reflective of differing RF spectrum regulations:

There have been 5 main revisions of sync modules:

Version 0 which was white and has a (non-functional) ethernet port and (non-functional) USB and BLE (non-functional) available. This was the ‘launch’ era.

 Version 1a which is white and has a (non-functional) ethernet port and (non-functional) USB.

Version 1b which is white or black and has a (non-functional) USB.

Version 1c which can be white or black and has no ports.

These were all the general ‘XT’ era modules.

Version 2 (the current one) which has a functional USB port.

All the modules are currently compatible with each other, but Modules 0, 1a,b,c have support ‘no longer guaranteed’.

However, this isn’t the end of the story, as the boards inside all come in combinations of EU and US and Intl flavors (due to regulatory / radio differences) too!

I’m guessing that the version I tore down back in mid-2019 was a “Version 1a”. I suppose it also could have been a “Version 0”, although I didn’t come across any Bluetooth Low Energy circuitry inside it. The one still in use here is a “Version 1b”.

Intra-generational variation

When the Redditor who wrote the above shared his thoughts four years ago, there may have been only one (initial) version of the Sync Module 2 we’re looking at today. Fast forward to the present, however, there now have been (at least) two. The initial hardware was based on Atheros silicon for both the processor and Wi-Fi module; Blink subsequently switched to NXP-sourced ICs for both the processor and wireless subsystems, the latter this time supporting not only Wi-Fi but also both Bluetooth and BLE.

Onward. Remove two screws:

And the PCB pops right out:

You’ve already gotten a glimpse of the PCB frontside, so in fairness to its backside counterpart, let’s start there with the detailed analysis:

Admittedly, there’s not much of note, unless you’re into passives and embedded traces, that is. At lower left is the reset-and-pairing switch. And to its right is a Winbond W25Q256JV 256 Mbit serial NOR flash memory, presumably for system code storage. For comparisons sake, here’s the comparatively sparse backside of the first-gen Sync Module PCB:

Now flipping the PCB back over…

I didn’t bother expending much effort at peeling the initially stubborn sticker off the processor; I already know from the NXP logo visibly atop the chip in its upper right corner in conjunction with the helpful Wiki reference page I’d found that it’s the second iteration of the second-gen design, employing NXP’s MCIMX6Z0DVM09AB application processor with the following specs:

• ARM Cortex-A7 running Linux
• 900MHz
• SRAM: 128kB
• SPI/UART/I2C
• 96KB bootrom, 128KB internal RAM
• Has Arm TrustZone

That other NXP chip I previously noted is the 88W8987-NYE2 wireless “solution”. Below the processor is an ISSI IS43TR16640BL 1 Gbit DDR2 SDRAM. And at the top center of the PCB is one more notable (albeit tiny) IC. Labeled as follows:

455A
CQRX
220

It’s Silicon Labs’ Si4455 sub-GHz wireless transceiver, which (as the name) implies implements the proprietary long-range 900 MHz channel that Blink refers to as the LFR (low-frequency radio) beacon.

In closing, here’s the first-generation Sync Module PCB topside for comparisons sake:

And with that, I’ll turn it over to you for your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN Magazine.

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