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Advances in autonomous driving and advanced driver-assistance systems (ADAS) now enable vehicles to understand their surroundings in real time, a complex process based on the concepts of perception and sensor fusion.

Perception refers to the ability to detect and classify objects, recognize traffic signs, track pedestrians, and map the road. However, every type of sensor has its own physical limitations. Sensor fusion is the technology that bridges this gap by intelligently combining data from sensors using advanced algorithms.

In this article, we will explore how perception and sensor fusion are driving evolution and innovations in the three main categories of automotive sensors: radar, LiDAR, and cameras. We also highlight several radar, LiDAR, and camera products with advanced features to improve ADAS imaging and perception.

Radar performs in harsh environments

Automotive radar offers excellent performance in tough conditions, such as fog, rain, and darkness, where cameras and LiDAR are less effective. The introduction of 4D imaging radar has added elevation (height) to the standard range, velocity, and azimuth outputs. 4D radar can thus generate dense point clouds that were once available only with LiDAR. According to MarketsandMarkets, the 4D imaging radar market was valued at $390 million in 2025 and is expected to grow to $1.2 billion by 2030, at a compound annual growth rate of 25.2%.

Hirain Technologies has developed the LRR615, a long-range imaging radar built around Arbe Robotics Ltd.’s 4D imaging radar chipset solution. The radar system is the first to be equipped with a high-density waveguide antenna. This feature provides improved image clarity, detection sensitivity, and signal integrity.

Designed to be cost-effective and manufacturable on a large scale, the LRR615 can be paired with cameras in autonomous-driving systems, providing an alternative to LiDAR. After integrating, calibrating, and validating the device, Hirain is setting up the manufacturing process to achieve an annual production of 10,000 units.

Arbe’s chipset (Figure 1) is a multichip architecture that integrates three proprietary, automotive-grade integrated circuits that process ultra-high-resolution data. The chipset can process real-time data from 2,304 virtual channels, achieve 3-Tbits/s equivalent processing throughput, and provide over 10,000 detections at 20 fps.

Arbe’s chipset is based on GlobalFoundries’ (GF’s) proprietary 22FDX process technology. This platform, specifically addressing automotive radar, integrates RF, analog, and digital processing blocks on the same die. This reduces system costs and accelerates time to market. According to GF, using its technology, Arbe is the first in the industry to create a real-time, 4D image of the surrounding environment, achieving a 1° resolution.

Figure 1: Arbe’s automotive-grade chipset integrates a safety processor, security, dual-core DSP, and application processor. (Source: Arbe Robotics Ltd.)

Another relevant application of automotive radar is in-cabin monitoring. An example is Texas Instruments Inc.’s AWRL6844, a 57- to 64-GHz mmWave radar sensor designed for occupancy monitoring, including seat-belt reminder systems, child-presence detection, and intrusion detection (Figure 2).

The AWRL6844 is a low-power device integrating four transmitters and four receivers. This high-resolution sensing data is processed by specific AI algorithms running on a customizable, on-chip hardware accelerator and DSP. This single-chip solution improves detection accuracy, reduces processing time, and enables a safer driving environment.

Figure 2: The TI AWRL684x mmWave sensor device employs FMCW radar technology to support multiple in-cabin applications. (Source: Texas Instruments Inc.)

Infineon Technologies AG offers a similar product, the XENSIV BGT60ATR24AIP 57.7- to 62.4-GHz radar sensor based on FMCW technology. Available in a compact, 8 × 8-mm2 package with antenna-in-package technology, the device features ultra‑low power consumption, high precision, and advanced sensing, making it suitable for contactless, high-accuracy in‑cabin monitoring.

LiDAR advances with better perception and identification

MicroVision Inc., a company specializing in advanced perception solutions that recently acquired the assets from Luminar Technologies, introduced its Tri-LiDAR architecture. This solution integrates two MOVIA S short-range sensors (placed on the front corners) with one forward-facing HALO long-range LiDAR, delivering continuous, 360° environmental coverage (Figure 3).

The company’s software platform performs the real-time fusion of the data coming from all the sensors and generates a single, high-fidelity point cloud. This enables accurate object detection, classification, and tracking, delivering a real-time perception system.

According to the company, Tri-LiDAR provides three main benefits: a reduction in the power consumption of each sensor, a reduction in the packaging of each sensor, and a cost reduction of the system.

Figure 3: Top view of the MicroVision Tri-LiDAR system (Source: MicroVision Inc.)

Aeva Inc., a company specializing in sensing and perception systems, has licensed Cadence Tensilica Vision DSP IP to support the signal-processing tasks of its 4D LiDAR systems.

Tensilica Vision DSPs’ low-power architecture and Tensilica Instruction Extension language make Tensilica DSPs suited for applications in which real-time signal processing, low latency, and high efficiency are mandatory. According to Aeva, the flexibility and performance of Cadence’s Vision DSP technology will improve the perception and scalability of its solutions, addressing automotive and industrial applications.

Hesai Technology, a company specializing in 3D perception, announced the Picasso 6D Full-Color LiDAR SPAD-SoC, a solution that natively captures 3D spatial geometry (X, Y, Z) and 3D color data (R, G, B) on a single chip, eliminating the need for fusion of separate camera and LiDAR data.

By performing the sensor data fusion directly at the silicon level (the single-photon avalanche-diode SoC), the Picasso chip produces high-resolution, colorized point clouds simultaneously, allowing for better identification of objects such as traffic lights, lane markings, and construction zones. Hesai’s ETX LiDAR, upgraded to support up to 4,320 channels, will integrate this technology and will be available in the second half of 2026.

Lumotive, a company specializing in programmable optical semiconductors, has introduced a solid-state LiDAR platform that combines its commercially available LM10 Light Control Metasurface (LCM) with the ADS6311 Hawk sensor from Adaps Photonics.

The solution (Figure 4) delivers a 180° horizontal field of view and operates at 30 fps, eliminating blind spots, improving the tracking of fast-moving objects, and reducing the number of sensors required. Lumotive’s LCM technology electronically steers light at semiconductor speed, without encountering the limitations associated with mechanical scanners and fixed-channel VCSEL arrays. In addition to 180° horizontal coverage, the sensor offers up to 140° vertical coverage, configurable through software to optimize range, resolution, and frame rate.

Figure 4: The architecture of Lumotive’s solid-state LiDAR system doubles the frame rate typically achieved by many direct ToF LiDAR systems while extending sensing distances to as much as 50 meters. (Source: Lumotive)

Cameras shift to 8-MP sensors

Cameras are rapidly migrating to 8-MP sensors, representing the new baseline for ADAS front and side cameras. The higher resolution directly increases the detection range at highway speeds, enabling confident object classification at distances that 2-MP and 5-MP sensors cannot reliably achieve.

Omnivision introduced the OX08D20 8‑MP CMOS automotive image sensor based on its proprietary TheiaCel technology. The device is an improved version of the OX08D10 sensor for exterior cameras widely used in ADAS and autonomous-driving systems.

The OX08D20 image sensor features a 60-fps frame rate, 2× higher than its predecessor, OX08D10, enabling dual-use cameras. With 60 fps, the video flows more smoothly. This allows car manufacturers to save money, space, and wiring by using one camera to handle both background autonomous-driving tasks and real-time visual displays for the driver. The sensor also supports the latest cybersecurity standard MIPI CSE 2.0 (Camera Service Extensions v2.0) developed by the MIPI Alliance.

Omnivision’s TheiaCel technology has been designed to capture high-quality images even in extreme lighting conditions. It achieves high dynamic range (HDR) using a single exposure. In this way, the LED flicker experienced in traditional HDR sensors is eliminated.

Sony Semiconductor Solutions introduced the IMX828, the industry’s first 8-MP CMOS image sensor for automotive cameras featuring a built-in MIPI A-PHY transmission interface. Traditional automotive camera systems require externally mounted serializer chips to transfer data safely to the vehicle’s electronic control unit. By embedding the MIPI A-PHY interface directly into the sensor, Sony eliminates the need for this additional hardware.

This feature enables a reduction in board size and module power consumption and limits heat generation. The chip also integrates a proprietary error-handling circuit that resists external noise disruptions.

NXP Semiconductors’ 4K MIPI CMOS camera module (IMX-OS08A20) is a high-performance development tool for consumer, industrial, and automotive vision systems. It is built on OmniVision’s 8-MP OS08A20 sensor and adopts PureCel and Nyxel technologies to capture 4K Ultra-HD video at 60 fps.

The development kit includes the 8-MP sensor module, a MINI-SAS interface cable, and an adapter board. It is designed to plug directly into the NXP i.MX 8M Plus Evaluation Kit. The module’s high-resolution performance makes it well-suited for automotive in-cabin applications, such as driver-monitoring systems and occupant-monitoring systems.

The post Designer’s guide: Radar, LiDAR, and cameras advance ADAS appeared first on EDN.

LED manufacturers continue to enhance their LED designs for automotive lighting, enabling greater differentiation in the car’s exterior and interior illumination as well as improving safety features. Many of the latest developments focus on several key areas: smaller form factors for space-constrained and sleeker designs, improved thermal performance, and flexible color control.

LED driver developments go hand in hand with these advances to support these next-generation LEDs, focusing on advancements in packaging, heat dissipation, and simpler designs for easier integration and space savings.

Here is a selection of LED and LED drivers introduced over the past year, targeting automotive exterior and interior lighting applications. They focus on a range of improvements that deliver smaller form factors, greater heat dissipation, higher system efficiency, enhanced light output, and precise color control.

Automotive LED innovations such as compact, high-luminance designs enable sleeker lighting systems while maintaining uniform, energy-efficient light output. (Source: Adobe Stock)

A new generation of LEDs

Some of the latest automotive LED designs address the demand for sleek front lighting. One example is ams Osram’s OSLON Compact RM for next-generation slim headlamp systems. It addresses design aesthetics in automotive lighting with its high luminance, compact form factor, homogeneous light, and color appearance, allowing for the creation of signature lighting elements for brand identity, the company said.

The Compact LED is a 0.5-mm2 rectangular high-current chip, housed in a compact ceramic package. The small size enables optical systems with heights as low as 10 mm, enabling ultra-slim headlamp designs that were previously difficult to achieve, according to ams Osram. The two-pad package design supports solder stability on aluminum boards, suiting it for a variety of automotive lighting applications.

The LED delivers improved optical efficacy through its adapted light-emitting area (LEA) of 0.6 × 0.9 mm with an aspect ratio of 1:1.5. It features high luminance and uniform light output, free from dark zones, while maintaining high energy efficiency, a key factor for EVs.

The OSLON Compact RM for advanced front-lighting applications targets three light functions: low beam, static high beam, and adaptive driving beam (ADB) LED matrix systems. Thanks to its rectangular LEA, vertically oriented within the package, the OSLON Compact RM enables precise pixel-to-pixel alignment and provides a greater vertical light spread in ADB systems. At a driving current of 1 A, it claims an impressive luminance of 209 Mnits, which ensures maximum optical performance even with small lens components, according to the company.

Ams Osram’s OSLON Compact RM (Source: ams Osram)

Ams Osram also enhanced its offerings for automotive interior applications with the launch of its OSIRE E3030 RGB LED with significantly enhanced light output. Aimed at next-generation ambient lighting solutions, the RGB LED pairs a high light output in the 0.5-W range with precisely controllable color variety, meeting both function and aesthetic requirements.

Depending on the selected color location, the OSIRE E3030 delivers typical luminous emissions for red and blue, ranging from 22.4 to 40 lumens or from 7.1 to 14 lumens at a binning current of 200 mA, and from 28 to 50 lumens for green at a binning current of 150 mA. It offers a wide range of available wavelengths for an expanded color gamut and individually addressable color channels for greater flexibility in terms of color selection and color mixing.

The OSIRE E3030 measures 3 × 3 × 0.6 mm, suiting it for applications with space constraints. In addition, the delta arrangement of the LED chips ensures exceptional color-over-angle performance, according to the company.

The OSIRE E3030 is also resistant to vibration and temperature fluctuations, meeting automotive standards. It is AEC-Q102-qualified.

Ams Osram’s OSIRE E3030 RGB LED (Source: ams Osram)

Also claiming ultra-small footprints and profiles, Lumileds has introduced two LED series—the LUXEON Versat 2016 and the LUXEON Altilon SMD-A—targeting a variety of automotive lighting applications.

The LUXEON Versat 2016 automotive LED is an AEC-Q-qualified LED portfolio with a broad color and performance range, measuring 2.0 × 1.6 mm with a z-height of only 0.52 mm. The LED not only offers standard direct and phosphor-converted colors but also LED-emission spectral tuning to match transmission characteristics of foils as used in car-body and grille illumination for superior color control, Lumileds said.

Targeting animated, personalized car-body lighting, the LUXEON Versat 2016 delivers features such as singular optical elements, backlit optical surfaces, and 3D illuminated structures for car illumination beyond traditional signaling into styling and communication lighting, the company said. The automotive LED can also be used in daytime running lights (DRLs), turn, stop, tail, and side-marker applications.

Lumileds also introduced the LUXEON Altilon SMD-A LED, claimed as the thinnest single-chip addressable LED, targeting high-performance automotive forward lighting. It has a z-height of only 433 µm, which allows for optical structures to be designed with greater accuracy and efficacy. This means the optics can be designed closer to the LED, which improves optical efficiency.

The advanced package is said to increase luminance, thermal capabilities, and robustness for demanding front fog, low/high beam, and ADB.

In addition, the small edges of the LUXEON Altilon SMD-A improve contrast, measuring 1:247, and produce a sharp, natural cutoff. Lumileds said reducing the gap between LEAs to 70 µm and achieving the optimal die-to-phosphor size increases luminance for further cost-performance improvements. The series is available in four configurations: 1×2, 1×3, 1×4, and 1×5.

Lumileds’ Altilon SMD-A LEDs (Source: Lumileds Holding B.V.)

For aftermarket automotive lighting applications, Cree LED, a Penguin Solutions brand, introduced the XLamp XE-B LEDs in an ultra-compact package for directional lighting applications. This latest XLamp Element LED extends the family into a smaller form factor, measuring 0.9 × 1.4 mm, while delivering high intensity in optical systems, whether used individually or in arrays, according to the company.

Claiming new levels of performance from an extremely small light source, the automotive LED delivers up to 60% higher intensity than existing LEDs with a larger, 1 × 1-mm light-emitting surface. While it is optimized for directional lighting applications that benefit from multi-color LED designs and suited for indoor directional lighting, architectural lighting, and entertainment lighting, it also targets aftermarket automotive lighting, in which compact size, high intensity, and precise color control are all key requirements.

The XE-B LED series is built on Cree’s advanced Element platform, enabling the smallest possible distance between the LED chip and the package edge, which allows tighter spacing, improved optical control, and seamless integration with secondary optics. It also features a large, electrically isolated thermal pad that supports advanced printed-circuit-board (PCB) designs, delivering a direct thermal path to the heat sink for excellent heat dissipation and long operating lifetimes, even at maximum current, the company said.

The XE-B LEDs enable precise and consistent color mixing with a consistent 1-A maximum current across all colors and a uniform package design. It offers 17 colors plus a full range of white options.

Cree LED’s XLamp XE-B LEDs (Source: Cree LED)

LED drivers optimize automotive lighting

Targeting improved safety, aesthetics, and personalization, Diodes Inc. offers the automotive-compliant AL5958Q matrix LED driver with a 48-channel constant-current source, capable of up to 32 scans. Suited for automotive dynamic lighting, the device targets narrow-pixel mini- and micro-LED displays, which require multiple RGB LEDs to produce animated, dynamic lighting with data and information. Applications include central information displays, cluster displays, head-up displays, grill and emblem lights, body LED panels, interior lights, and rear lights.

The AL5958Q features built-in intelligent matrix display command functions that reduce the processing overhead on the local microcontroller (MCU). Key functions include automatic black-frame insertion to mitigate blurs caused by scanning switches, reduction of last-scan- and next-scan-line ghost images to eliminate ghosting from parasitic capacitors, and suppression of short-LED caterpillars.

Other features include open-LED fail lines and staggered current output delay to minimize inrush current, as well as grayscale enhancement (also known as low-brightness uniformity compensation), a grayscale clock watchdog timer, and sleep mode for power savings.

Differentiated features include the integrated 16 N-MOSFETs, allowing support of both static and dynamic systems, and multiplex-pulse-density modulation technology that enhances the refresh rate of dynamic scanning systems without increasing the frequency of the grayscale clock. This mitigates electromagnetic interference (EMI) due to high clock frequencies, Diodes said.

The AL5958Q also features high, 16-bit resolution dimming, coupled with its RGB support, for highly precise brightness control and color mixing. The current output for each color group can be configured either through three external current-sensing resistors or by programming three 6-bit global current control registers.

The device also offers advanced diagnostic features and protection mechanisms for monitoring capabilities. These include error flag registers applied to LED open/short to read out each channel using open/short detection, undervoltage lockout (UVLO) protection, and a watchdog timer.

The AL5958Q is supplied in a wettable W-QFN9090-76/SWP (Type A1) package and operates in a –40°C to 125°C ambient temperature range. Multiple AL5958Q devices can be daisy-chained without limitation. Diodes also offers a standard compliance version, the AL5958, for industrial and commercial applications.

Diodes Inc.’s AL5958Q matrix LED driver (Source: Diodes Inc.)

Lumissil Microsystems recently introduced the IS32FL3776 matrix LED driver for software-defined exterior lighting module applications. Enabling a combination of expressive and thermally efficient exterior lighting, these systems use matrix LED patterns to communicate vehicle intent, safety status, and driver-assistance cues, as well as brand identity.

The IS32FL3776, housed in a QFN-60 package, supports compact, individually addressable LED designs used in RGB mini-LED displays, full-width front-light strips, grille lamps, automated-driving-system marker lamps, and other vehicle lighting functions.

The IS32FL3776 integrates 36 constant-current sink channels and six scanning supply-switch controls to support a 36 × 6 matrix of up to 216 individually addressable LEDs. The dense matrix architecture targets large, intelligent signal display (ISD) lighting surfaces with fewer external components.

For high-quality animations, the IS32FL3776 features high-resolution, high-frequency, dithered pulse-width-modulation (PWM) control for fine brightness adjustment and a reduction in visible flicker and camera banding. Other features that help maintain uniform, artifact-free illumination across dense LED arrays include integrated current adjustment, matrix de-ghosting, low-headroom operation, and synchronized scanning.

This LED driver offers high-speed SPI and LumiBus UART interfaces that allow multiple driver ICs or distributed lamp PCBs to operate in synchronization for large-area displays and coordinated lighting animations.

The IS32FL3776 packs features for improved system efficiency and thermal performance. DCFB adaptive control is used to optimize the LED supply rail while maintaining only the headroom needed for proper current regulation, and an internal ADC and FBO feedback pin works with an external DC/DC converter to reduce driver power dissipation in large or high-brightness matrix displays.

It also supports external PMOS operation for additional thermal optimization, which moves high-side switching dissipation outside the IC package into external FETs and PCB copper, Lumissil said.

Other features include spread-spectrum PWM clocking, phase-delay control, and staged switching to help reduce supply ripple, EMI emissions, and audible-noise risk in high-brightness or high-duty-cycle ISD lighting applications; and diagnostic, protection, and communication-integrity features including LED open/short detection, ADC-based monitoring, overcurrent protection, UVLO protection, thermal shutdown, and CRC error detection.

Lumissil Microsystems’ IS32FL3776 matrix LED driver (Source: Lumissil Microsystems)

Lumissil addresses 48-V automotive systems with the introduction of the IS32LT3962 dual-channel LED controller. By using the IS32LT3962, as automotive lighting shifts from 12-V to 48-V systems, lighting designers can achieve improved power efficiency, reduced thermal stress, and lower wiring harness cost and weight, according to the company.

The IS32LT3962 drives two independent high-voltage LED strings for automotive applications such as high-/low-beam headlights, DRLs, and turn signals and enables lamp driver modules to support two functions (e.g., high beam and low beam) with a single IC to reduce space. The dual-output channel enables independent channel brightness control, with combined analog and internal/external PWM dimming for more compact lighting solutions.

The LED controller supports a wide, 5-V to 80-V input/output range for 24-V to 48-V battery systems and delivers flexibility with buck, buck-boost, SEPIC, or boost topologies on each channel. Other features include dual analog dimming pins to enable LED binning and thermal current roll-off using an external NTC, programmable undervoltage current reduction, and spread-spectrum operation combined with 180° phase shifting to help reduce system-level EMI.

The IS32LT3962 is housed in a compact WFQFN-32 package with an exposed pad for enhanced thermal dissipation. The operating temperature range is –40°C to 125°C Automotive Temperature Grade 1.

Lumissil Microsystems’ IS32LT3962 LED controller (Source: Lumissil Microsystems)

Melexis recently announced the launch of the MLX81119, an 18-channel LIN RGB LED controller with an integrated DC/DC converter. This LED controller is designed to simplify and optimize automotive lighting systems.

The MLX81119, housed in a 5 × 5-mm QFN32 package, is powered by Melexis’s 16-bit MCU, with an integrated memory subsystem that includes 32 KB of flash, 13.5 KB of ROM, and 4 KB of RAM to support the application, LED calibration coefficients, and additional system data. It is designed to reduce power dissipation, external components, and space requirements in dense vehicle applications such as door panels, dashboards, and charge port lighting by generating the LED supply voltage locally on the chip.

Simplifying the external power stage, the LED controller operates with as few as two capacitors and a single inductor, eliminating the need for a separate DC/DC controller and associated passives. This design reduces component count and PCB area for more compact lighting modules and easier integration in space-constrained locations.

In conventional architectures, supplying LEDs via external DC/DC converters increases heat generation, component count, and layout complexity, making it harder to meet physical, efficiency, and thermal constraints as automakers increase lighting deployments to meet growing requirements for new functionality, personalization, and brand differentiation, according to Melexis.

The 18-channel MLX81119 addresses these challenges by integrating a 1-A DC/DC converter that generates an optimized local LED supply voltage, programmable between 2.5 V and 6 V. This means the LED controller does not dissipate excess voltage as heat. It dynamically adapts the LED supply to the active color mix and operating conditions to reduce power losses and thermal stress, according to the company, which is not achievable with fixed external DC/DC converter solutions.

The MLX81119 features 18 low-side current sources configurable up to 60 mA and independent 16-bit PWM control. It supports up to six RGB LEDs per device, enabling smooth color transitions and advanced lighting animations, and provides built-in direct and indirect temperature sensing that allows active compensation across all channels, so color points remain stable over the full automotive temperature range.

The MLX81119 integrates a complete LIN system, including transceiver and protocol handler, fully compliant with LIN 2.x and SAE J2602. Developed according to ISO 26262, the device supports up to ASIL-B implementations.

Melexis’s MLX81119 LIN RGB LED controller (Source: Melexis)

Novosense Microelectronics has expanded its portfolio of high-performance LED driver ICs for exterior and interior lighting with several new series. These devices feature high-side and low-side linear drivers, as well as integrated MCU solutions for RGB/RGBW ambient control, and deliver precise current regulation, advanced diagnostics, and robust thermal management for safer, more energy-efficient, and customizable lighting systems.

The lineup includes the NSL21912/16/24 12-, 16-, and 24-channel high-side linear LED drivers, NSL23716x 16-channel low-side linear LED driver, NSL2163x linear LED driver with thermal balancing, and NSUC1500 ambient lighting driver system-on-chip.

The NSL21912/16/24 series devices are automotive high-side LED drivers that deliver 100 mA per channel with 12-bit PWM dimming. They support automatic thermal sharing via VS shunt resistors for higher thermal performance. Other features include configurable LED fault detection, integrated E2PROM for fail-safe functions, a UART interface up to 2 Mbits/s, and optional ASIL-B functional-safety support.

The NSL23716x 16-channel automotive low-side LED driver delivers 100 mA per channel and 12-bit independent PWM dimming. It integrates programmable thermal derating, LED open-/short-circuit detection, and overheat protection with automatic shutdown. It also incorporates built-in OTP memory that supports fail-safe safety functions, and an optional CAN PHY interface eliminates the need for an external transceiver, simplifying design and improving system reliability.

The NSL2163x three-channel automotive linear LED driver provides up to 200 mA per channel and operates directly from a 5-V to 40-V battery supply. The device supports thermal sharing via external shunt resistors and integrates LED open-/short-circuit detection with thermal shutdown for enhanced system reliability. It offers an optional, low-power EN-pin version.

The highly integrated NSUC1500 IC for ambient lighting integrates an Arm Cortex-M3 core and four-channel high-precision current-mode LED drivers. The device provides 16-bit independent PWM dimming and 6-bit analog dimming capabilities. It enables more accurate dimming and color-mixing control while compensating for lumen depreciation, Novosense said. The NSUC1500 is compliant with the AEC-Q100 Grade 1 and CISPR 25 Class 5 EMC standards.

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With the increasing popularity of renewable energy and electric vehicles, the large-scale application of bidirectional isolated DC/DC converters is growing. This article will focus on energy storage systems (ESSs), with an overview of the isolated bidirectional topologies used in ESSs.

Figure 1 shows a typical residential ESS. A unidirectional DC/DC converter, also known as a maximum power-point tracker, converts the energy generated by solar panels and then feeds that energy to a high-voltage DC bus. An inverter may transfer this energy to the electric grid, or the energy may be stored in the battery system, where a bidirectional DC/DC converter charges and discharges the battery.

Figure 1 This block diagram shows the constituent pieces of a residential ESS system. Source: Texas Instruments

Because of safety considerations, residential ESSs use low-voltage batteries, such as 48V. Therefore, the DC/DC converter must provide galvanic isolation between the high-voltage DC bus and the battery. Because the DC bus and battery vary from the voltage ranges shown in Figure 1, one of the design priorities for the converter is to have a wide voltage-adjustment range.

The traditional solution is usually an open-loop inductor-inductor-capacitor (LLC) and a closed-loop buck/boost converter. The benefit of this solution is that it is easy to control and has a wide voltage-adjustment range, but a two-stage converter results in lower total system efficiency and higher costs.

To optimize the performance of the bidirectional DC/DC converter, a one-stage solution is preferable. Compared to a two-stage solution, a one-stage solution has higher efficiency and lower costs, but it also needs a more complex control scheme to achieve high performance. The most popular one-stage solutions are LLC, capacitor-inductor-inductor-inductor-capacitor (CLLLC), dual active bridge (DAB) and series resonant DAB (SR-DAB).

As shown in Figure 2, an LLC resonant converter can achieve very low switching losses. When operating near or below the resonant frequency, the LLC can achieve zero voltage switching (ZVS) on active bridges and zero current switching on rectifier bridges. When operating above the resonant frequency, an LLC can only achieve ZVS on active bridges.

Figure 2 A LLC resonant converter, shown in this schematic, can achieve very low switching losses. Source: Texas Instruments

Since this converter soft switches during turnon and turnoff, the electromagnetic interference emissions are comparatively low to other converters without soft switching. But designers generally only use the LLC resonant converter for unidirectional power transfer. It is not good for wide-gain-range applications such as ESSs because the voltage gain curve is flat when the switching frequency is higher than the resonant frequency, as shown in Figure 3.

Figure 3 This LLC voltage gain curve is flat when the switching frequency is higher than the resonant frequency. Source: Texas Instruments

Adding resonant elements on the secondary side of the transformer will form a bidirectional CLLLC resonant converter. As shown in Figure 4, the converter resonance network is symmetrical and proportional to the transformer’s turns ratio, so this converter maintains the resonance law and functionalities, such as soft-switching features in both forward and reverse operation.

Figure 4 A bidirectional CLLLC, shown in this schematic, is symmetrical and proportional to the transformer’s turns ratio. Source: Texas Instruments

A major advantage of this topology is the ability to provide symmetrical bidirectional power transfer. The effect of the secondary resonant tank may cause the voltage gain curve to have multiple crests, however, as shown in Figure 5. Similar to an LLC converter, a CLLLC also has a narrow voltage adjustment range and consists of five resonant elements, which increases the size and cost of the system, while the additional inductor also introduces additional losses.

Figure 5 The effect of the secondary resonant tank, shown in this gain curve of a CLLLC, may cause the voltage gain curve to have multiple crests. Source: Texas Instruments

Figure 6 shows the basic DAB topology, which consists of a full bridge with active switches on both the primary and secondary sides. The main advantages of the DAB converter are its inherent bidirectional capability, faster dynamic response, and wider voltage-adjusted range compared to the LLC and CLLLC topologies.

Figure 6 The basic DAB topology, shown in this schematic, consists of a full bridge with active switches on both the primary and secondary sides. Source: Texas Instruments

Through the most basic single-phase-shift (SPS) control, it is possible to adjust the polarity and magnitude of the phase-shift angle between the primary and secondary bridges, thereby controlling the magnitude and direction of its transmission power. The peak current of transistors and the circulating current are large with SPS control, however, which results in high turnoff losses as well as circulation losses.

ZVS is also difficult to achieve at light loads. With advanced modulation schemes such as triple-phase shift, a DAB converter can theoretically achieve ZVS over the entire operating range and could optimize high peak current and circulating current, but will require significantly more complex system analysis.

Inserting a series resonant tank into the DAB converter forms an SR-DAB, as shown in Figure 7. Similar to a series resonant converter, an SR-DAB needs to operate above the resonant frequency in order to ensure that the converter is in the inductive region, which is a necessary condition to realize ZVS. Given the resonance features of the circuit, the inductor current of an SR-DAB is almost sinusoidal, which could have a smaller turnoff current and root-mean-square inductor current compared to a traditional DAB.

Figure 7 Inserting a series resonant tank into the DAB converter forms an SR-DAB, as shown in this schematic. Source: Texas Instruments

Table 1 summarizes the primary features of the four isolated bidirectional DC/DC topologies.

	LLC	CLLLC	DAB	SR-DAB
Voltage adjustment range	Narrow	Narrow	Wide	Wide
Transient response	Slow	Slow	Fast	Fast: phase shift plus fixed frequency Slow: phase shift plus variable frequency
ZVS range	Wide (full-range ZVS）	Wide (full-range ZVS）	Narrow (no ZVS at light loads)	Medium
Turnoff current	Low	Low	High (with SPS)	Medium (with SPS)
Control complexity	Moderate	Moderate	Simple (SPS) Complex (TPS)	Simple (SPS) Complex (TPS)

Table 1 This table summarizes various DC/DC topologies.

All four topologies provide isolation and bidirectional power transfer functions; however, DAB and SR-DAB are more suitable for ESS applications given their wide voltage-adjustment range and faster dynamic response. In addition, an SR-DAB has a lower turnoff current and a wider ZVS range compared to a DAB, with higher efficiency than a DAB as well.

For more details about the DAB topology, see the Texas Instruments Power Supply Design Seminar paper, “Dual Active Bridge Topology Overview.”

Guangzhi Cui is a power systems engineer at Texas Instruments. In this role, he handles industrial power system design and provides semiconductor power system solutions and customer technical support.

 

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• Power Tips #89: High-frequency resonant converter design considerations, Part 1
• Power Tips #92: High-frequency resonant converter design considerations, Part 2
• Power Tips #117: Measure your LLC resonant tank before testing at full operating conditions
• Power Tips #97: Shape an LLC-SRC gain curve to meet battery charger needs

The post Power Tips #155: How to choose the best topology for isolated energy storage systems appeared first on EDN.

Filters are circuits comprising resistors, inductors and capacitors that pass certain frequency bands and attenuate others. Active filters use operational amplifiers (op amps) with resistors and capacitors, whereas passive filters do not include an amplifier.

Active filters have an advantage over passive filters in that they can have gain. The gain factor in an active filter enables higher-order filters as well as a wider range of filter-response characteristics. For example, a band-pass filter with a narrow bandwidth would be challenging to implement with only passive components given the limited gain of passive filters.

The amplifier also allows the filter to drive a load impedance without affecting the filter response, whereas the passive filter response generally changes significantly with loading. Finally, a passive filter may require an inductor, which may add cost and PCB space, compared to an active filter that only requires the amplifier, resistors, and capacitors.

Generally, you can design active filters with simple software programs such as Filter Design Tool. This tool designs an active filter based on your filter specifications, type, response, and topology. The final output for the software tool is a schematic with all the necessary component values. Filter Design Tool does assume that the op amp is ideal, however, and its response can change when using a practical op amp.

This article covers the most common active filter nonidealities, with recommendations on how to mitigate the problem.

Gain-bandwidth limitations

As mentioned previously, the purpose of an active filter is to pass one range of frequencies (pass band) while attenuating another range of frequencies (stop band). The ability of an amplifier to achieve this goal depends heavily on the gain-bandwidth product specification. When using an op amp with insufficient gain bandwidth in an active filter, the stop-band attenuation will not match the expected ideal filter response; specifically, the gain will stop rolling off and will begin to increase rather than decrease.

Figure 1 shows the simulated gain response of a Sallen-Key active filter using three different op-amp models with gain bandwidths ranging from 1.2 MHz to 11 MHz. The term Sallen-Key describes the topology or the specific connections of circuit components. Here, Filter Design Tool recommends a minimum gain bandwidth of 7.1 MHz, so op amps like OPA170 and OPA340 don’t meet that requirement but OPA140 does.

Figure 1 Sallen-Key low-pass filter response is shown for different gain-bandwidth op amps. Source: Texas Instruments

The attenuation in the stop band should continue to roll off at –40dB/decade; however, once the amplifier reaches its gain-bandwidth limit, it stops attenuating. The larger the gain-bandwidth of the op amp, the better the stop-band attenuation.

The figure above showed the effects of insufficient gain bandwidth on a Sallen-Key topology. The Sallen-Key topology is a noninverting type of active filter, while the multiple-feedback topology is an inverting type of active filter. The multiple-feedback topology band-stop attenuation is better than the Sallen-Key topology for low-gain-bandwidth designs.

Figure 2 shows the multiple-feedback response for the same three op amps used in the Sallen-Key example. The multiple-feedback response continues to roll off even after the frequency exceeds the gain-bandwidth limitation of the op amp. For the multiple-feedback circuit, the rolloff transitions from 40dB/decade to 20dB/decade when reaching the bandwidth limitation.

Figure 2 Multiple-feedback low-pass filter response is shown for different gain-bandwidth op amps. Source: Texas Instruments

To summarize, it’s important for active filters to follow the gain-bandwidth limitation given by the filter design software. A higher gain bandwidth will improve the stop-band attenuation, so depending on the range of frequencies that you need to reject, it may be necessary to choose a gain bandwidth 10 or 100 times the recommended minimum.

In cases where it’s not practical to choose an amplifier with a high gain bandwidth, use the multiple-feedback topology because its response is less dependent on gain bandwidth than the Sallen-Key topology.

Source impedance effects

All signal sources have a finite output impedance. A signal source can be commercial test equipment, an amplifier output, or an analog sensor. The output impedance of test equipment or amplifiers is generally very low, while the output impedance of a sensor can be high. Sources with low output impedance will have a minimal effect on filter response.

Conversely, a signal source such as a bridge sensor can have a high output impedance, which may significantly affect the filter response. As with the gain-bandwidth limitations, some filter topologies will be more sensitive to source impedance than others.

Figure 3 compares and contrasts the impact of source impedance on the Sallen-Key and multiple-feedback topologies. In this case, Sallen-Key is much less sensitive to source impedance than multiple feedback. The example plots the response for a 250 Ω, 500 Ω and 1,000 Ω source impedance. The multiple-feedback topology gain is significantly affected by the source impedance, but the effect on the Sallen-Key topology is minimal.

Figure 3 Source-impedance effect on response is displayed for the Sallen-Key and multiple-feedback topologies. Source: Texas Instruments

Component tolerance

Resistor tolerance will affect the cutoff frequencies and gain of active filters. For a low- or high-pass filter, a small shift in the cutoff frequency will not be a significant problem for most applications. For example, if a low-pass filter has an ideal cutoff frequency of 1 kHz but the component tolerance sets the actual frequency to 1.1 kHz, that will not be an issue for most applications.

Band-pass and band-stop filters, conversely, often have very precise bandwidth and center frequency requirements. For example, if a band-stop filter is designed to attenuate a 60-Hz signal, then the center frequency of the stop band should be very close to 60 Hz in order to properly attenuate the 60-Hz signal.

Figure 4 illustrates how component tolerance can affect the center frequency of a band-pass filter. The filter has a center frequency of 1 kHz and a bandwidth of 100 Hz. The circuit was tested using Monte Carlo analysis with good and poor component tolerance (good tolerance: RTOL = 0.1%, CTOL = 1%; poor tolerance: RTOL = 1%, CTOL = 5%). Monte Carlo analysis randomizes the component values according to the assigned tolerance for a set number of runs.

Figure 4 Here is a view of component tolerance impact on band-pass center frequency. Source: Texas Instruments

In this example, you can see much better control of the band-pass center frequency for the more precise (good) tolerance case. For the poor tolerance case, the center frequency is between 932 Hz and 1.106 kHz. The goal of this filter is to pass 1 kHz and reject all other frequencies. For many of the poor-tolerance Monte Carlo runs, a 1-kHz signal would be significantly attenuated because of the shifted center frequency.

The problem with component tolerance is most significant on band-pass and band-stop filters. There are two ways to avoid tolerance issues for these filters. The obvious approach to minimize the error is to choose resistors and capacitors with good tolerance. Generally, precision resistors of 0.1% are easy to find and not that expensive compared to the amplifier cost.

For capacitors, the C0G or film type have the best tolerance, temperature coefficient, and distortion. Unfortunately, these capacitors can be expensive, and the best tolerance is typically 1%. Furthermore, the maximum capacitance for C0G capacitors is generally 100 nF.

Another approach to minimizing the effect of component tolerance is to widen the bandwidth of the filter. The example shown in Figure 4 uses a 100-Hz bandwidth. Running the same example with a 400-Hz bandwidth would show that both the poor and good tolerance cases would pass the 1-kHz center frequency. However, the disadvantage of increasing the bandwidth is that the stop-band attenuation would not be as effective for the wide-bandwidth case.

Noise gain in active filters

All amplifiers and resistors generate noise because of the random motion of electrons inside the resistors and the semiconductor material. It’s possible to calculate this noise mathematically based on the circuit components.

The noise for an op amp is defined as a noise signal source on the noninverting input of the op amp. The gain seen by the noise signal source is called the noise gain. For active filters, the noise gain and noise bandwidth can be significantly different than the signal gain and bandwidth of the filter.

Figure 5 illustrates a multiple-feedback low-pass filter signal gain and noise-gain response. The top schematic shows the signal gain of the filter, while the bottom schematic shows the noise-gain configuration. To simulate noise gain, you simply add a signal source to the noninverting input and short out other voltage sources.

Figure 5 See the noise gain vs. signal gain for a multiple-feedback low-pass filter. Source: Texas Instruments

Comparing the noise gain and signal gain on the Bode plot shows that the noise gain has a much wider and higher frequency response than the signal gain. Sometimes engineers conducting noise analysis of filters assume that the filter transfer function will limit the noise and are surprised that the noise is higher than expected.

This unexpected increase in noise is because the op amp’s intrinsic noise source is located at the noninverting input and not at the signal input. Thus, the increase in noise gain and noise bandwidth causes an increase in output noise that engineers often overlook because they are considering signal gain and not the noise gain.

As the above figure shows, a low-pass active filter has a higher and wider frequency noise gain than the signal gain. This effect is even more significant on band-pass and band-stop filters. Figure 6 compares the noise gain and signal gain of a band-pass filter with a 100-Hz bandwidth. In this case the noise gain is about 46dB (200 V/V) higher than the signal gain.

Figure 6 Noise gain vs. signal gain is shown for a band-pass filter. Source: Texas Instruments

This high noise gain will significantly boost the op-amp noise. But engineers who analyze the circuit by just looking at the signal gain may not expect the higher output noise because of the noise gain.

One way to reduce the impact of noise gain for band-pass and band-stop filters is to increase the filter bandwidth. This is counterintuitive because noise is usually larger for wide-bandwidth circuits. However, for bandpass filters, the noise gain is higher for narrow-bandwidth filters and lower for wide-bandwidth filters. Figure 7 shows how noise gain is higher for the narrow-bandwidth filter.

Figure 7 Noise gain vs. noise bandwidth is shown for band-pass filters. Source: Texas Instruments

Resources for active filters

Fully understanding active filters is a deep and relatively complex subject. You can use Filter Design Tool to design active filters, because this tool and other filter design tools generally assume ideal op-amp characteristics, but the best practice is to confirm your design using a SPICE simulator.

Art Kay is an application engineer in the precision amplifiers team at Texas Instruments. He specializes in support of low noise data acquisition systems and has published a book on intrinsic noise analysis. He also co-published a useful summary of analog engineering relationships and a companion software tool.

Related Content

• Active Filters for Video
• Signal Chain Basics #43: Active Filters
• Software Tool Aids Design of Active Filters
• Designing RC active filters with standard-component values
• Free program designs and analyzes passive and active filters

The post Active filters: Design tips and tricks appeared first on EDN.

Agriculture has become one of the fastest-growing applications for autonomous systems. Self-driving tractors, robotic sprayers, autonomous mowers, and unmanned aerial vehicles (UAVs) are helping growers address labor shortages while improving productivity and reducing operating costs.

Much of this progress has been enabled by satellite navigation. GPS, often combined with real-time kinematic (RTK) corrections, provides the centimeter-level positioning needed for planting, spraying, harvesting, and mapping. In open fields, these systems perform remarkably well.

However, not every agricultural environment offers an unobstructed view of the sky.

As autonomy expands into orchards, vineyards, and other crop operations, satellite navigation alone becomes increasingly unreliable. Dense tree canopies can block and attenuate GPS signals; branches and leaves create multipath reflections; and satellite visibility changes continuously as vehicles move through the rows. The result is inconsistent positioning precisely where autonomous machines must operate with the greatest precision.

For engineers developing autonomous agricultural equipment, maintaining accurate localization during periods of degraded GPS has become one of the industry’s most significant technical challenges.

The hidden challenge of tree canopies

Unlike row crops, orchards present a constantly changing navigation environment.

Vehicles repeatedly transition between open sky and dense canopy. GPS receivers may temporarily lose satellites or receive reflected signals instead of direct ones while traversing through the canopy. Even when the receiver maintains a position fix, accuracy can deteriorate significantly.

These errors quickly affect autonomous operation.

A tractor may slowly drift toward an adjacent row. A sprayer can apply chemicals outside the intended area or miss sections entirely. A robotic mower may require operator intervention after losing its planned trajectory. For UAVs performing inspection or precision spraying missions, degraded positioning can reduce mapping accuracy, compromise flight stability, and result in uneven or incomplete spray coverage.

Because these interruptions occur frequently—but not continuously—they are particularly difficult to manage. Autonomous systems must seamlessly maintain localization while GPS quality fluctuates throughout the mission.

Why sensor fusion matters

Modern autonomous platforms rarely depend on GPS alone. Instead, they combine information from multiple sensors, including cameras, LiDAR, radar, wheel odometry, and inertial measurement units (IMUs). Software continuously fuses these measurements into a single estimate of the vehicle’s position and orientation.

Among these sensors, the IMU plays a unique role because it measures motion directly. Accelerometers measure linear acceleration while gyroscopes measure angular rotation, allowing the navigation system to estimate vehicle movement regardless of external infrastructure.

When GPS becomes unreliable, the inertial system effectively bridges the gap until the satellite signal and positioning recover. The quality of that bridge, however, depends almost entirely on the quality of the inertial sensors themselves.

Not all IMUs perform the same

Most commercial agricultural equipment relies on microelectromechanical systems (MEMS)-based IMUs because they are compact and relatively inexpensive. These sensors work well for many applications but are very sensitive to temperature, vibration, and electromagnetic interference (EMI). They also do not work under various environments and gradually accumulate bias errors that grow over time.

During a brief GPS interruption, the accumulated error may be negligible.

During longer outages beneath dense tree canopy, however, heading errors begin translating directly into position errors. As the vehicle continues moving, localization drift increases until GPS becomes available again.

Historically, engineers solved this problem using fiber optic gyroscopes (FOGs) or ring laser gyroscopes. While highly accurate and insensitive to temperature, vibration, and EMI, FOG-based solutions are generally too large, expensive, and power-hungry for widespread deployment into commercial and agricultural applications.

Recent advances in silicon photonics are beginning to change that tradeoff by making optical gyroscope technology available in much smaller and more practical form factors.

Optical navigation moves into agriculture

One example is Anello Photonics’ silicon photonic optical gyroscope (SiPhOG), which integrates optical gyroscope technology using silicon photonics manufacturing techniques. The technology delivers significantly improved heading stability compared with conventional MEMS-only solutions while remaining compact enough for commercial autonomous platforms.

SiPhOG technology, integrated into the Anello Ground INS system, delivers improved heading stability while meeting the size requirements of autonomous platforms. (Source: Anello Photonics)

Rather than replacing GPS, systems such as the Anello Ground INS combine optical inertial sensing with dual RTK-capable GNSS receivers and advanced sensor fusion. The inertial system maintains accurate motion estimates while GPS measurements fluctuate, allowing navigation performance to remain stable through temporary signal degradation.

The value of this approach becomes especially apparent in orchards.

In field testing conducted in a commercial walnut orchard near Fresno, California, an autonomous ground vehicle equipped with the Anello Ground INS operated beneath dense tree canopy, where satellite visibility was significantly reduced. While a conventional GPS-based navigation solution drifted often by more than 5 meters during the passage through the canopy, the Anello Ground INS maintained sub-half-meter positioning throughout the test.

Although performance always depends on operating conditions and vehicle integration, the demonstration illustrates how improving inertial heading directly improves overall localization when GPS quality deteriorates.

Performance of autonomous ground vehicle navigating beneath dense walnut orchard canopy using the Anello Ground INS. (Source: Anello Photonics)

The same challenge exists in the air

Ground vehicles are not the only agricultural platforms facing degraded GPS. UAVs performing crop scouting, precision spraying, multispectral imaging, and field mapping frequently operate at low altitude near trees, where satellite visibility can also become inconsistent. For these applications, high-quality inertial sensing contributes not only to navigation accuracy but also to flight stability.

For example, the Anello X3 IMU applies the same SiPhOG technology in a compact IMU designed for UAVs and other autonomous aerial systems. By providing more stable inertial measurements during temporary GPS degradation, the X3 supports reliable flight control and more consistent navigation in challenging agricultural environments. Learn more about the benefits of inertial technology for precision agriculture here.

Looking beyond GPS

Agricultural autonomy will continue to rely on GNSS, and RTK will remain an essential component of precision farming. However, as autonomous machines move beyond open fields into orchards, vineyards, forests, and other GPS-challenged environments, satellite positioning alone is no longer sufficient.

The future of autonomous agriculture will depend on resilient sensor fusion architectures that combine GNSS with increasingly capable inertial technologies. Advances in integrated silicon photonics, enabling new, small, integrated optical gyroscopes, are making navigation performance once reserved for high-end aerospace systems accessible to the commercial agricultural market.

While GPS has transformed precision agriculture, the next leap forward will be driven by technologies that enable autonomous machines to operate reliably when satellite signals are degraded or unavailable. As resilient inertial navigation becomes an integral part of modern sensor fusion architectures, autonomous tractors, robotic implements, and UAVs will deliver greater accuracy, reliability, and operational confidence, bringing agriculture one step closer to true, all-condition autonomy.

The post Why autonomous agriculture needs inertial navigation appeared first on EDN.

As OEMs in high-reliability industries, including automotive, industrial, and military/aerospace, move to next-generation designs, they are looking for interconnects that not only offer high reliability and ruggedness but also greater design flexibility and miniaturization. The availability of more product options and easier integration and installation are also key requirements.

The combination of greater flexibility and miniaturization is delivering space and cost savings across rugged designs while supporting next-generation systems, such as vehicle platforms that are packing more and more electronic components into space-constrained devices.

Here is a selection of connectors and cable assemblies introduced over the past year that meet the right balance of features for these application trends. These include software-defined vehicles (SDVs) and zonal electronic/electrical (E/E) architectures; next-generation military/aerospace systems and unmanned aerial vehicles (UAVs); and industrial automation systems that need greater flexibility and adaptability.

Automotive connectors and cables

Molex recently expanded its HSAutoLink interconnect portfolio with the launch of the HSAutoLink G, comprised of terminals, connectors, PCB headers, and cables. It joins the existing rugged, high-speed HSAutoLink, HSAutoLink II, and HSAutoLink C families.

The connector system provides multi-gigabit Ethernet connections of up to 25 Gbits/s in a compact, USCAR-compatible interface, making it suited to address rising bandwidth demands driven by advanced driver-assistance systems (ADAS), radar, LiDAR, zonal architecture, immersive displays, and central compute modules.

By extending support with Ethernet connections up to 25 Gbits/s, these interconnects can meet the high bandwidth requirements in SDVs and autonomous mobility platforms, Molex said.

Fitting within existing USCAR Ethernet interfaces, the HSAutoLink G enables future-proof product designs that reduce space and weight in compact modules while streamlining system integration and upgrades. Key features include advanced electromagnetic-interference (EMI) shielding and controlled differential impedance to maintain signal integrity for high-speed communications in dense environments. This helps prevent signal failures, validation delays, and costly design changes, the company said.

Other features include an anti-stubbing design that protects the contacts during the mating process to reduce the risk of mis-mating, as well as the addition of multiple, uniform ground-contact points to enhance EMI suppression for higher reliability.

Molex’s HSAutoLink G automotive Ethernet connector system (Source: Molex)

As automakers shift to SDVs and zonal E/E architectures, TE Connectivity (TE) has introduced a portfolio of interconnects for automotive electronic control units (ECUs). The Inside Device Connectivity portfolio is designed to support the next generation of vehicle platforms. The purpose-built portfolio includes board-to-board, wire-to-board, flex-to-board, and wire-to-wire connector solutions for compact, high-performance applications.

The Inside Device Connectivity portfolio is tailored to the specific needs of SDVs, enabling scalable and standardized connector configurations while reducing weight, packaging space, and integration complexity, TE said.

At the same time, these interconnects are optimized for EMI-sensitive and vibration-intensive environments with high misalignment tolerance and ruggedness against vibration, contamination, temperature shifts, and humidity. Other features include current capacity up to 45 A for wire-to-board and up to 18 A for board-to-board; a pitch of 0.4 mm to 10.16 mm with up to 180 pins; and crimp, IDC, and mass terminations.

These connectors target different application areas in an SDV, including ECUs, power conversion (on-board charger inverters and DC/DC converters), battery systems (battery, cell module controller, and battery management system), high-performance computers, ADAS (radar and LiDAR), and black-box systems (such as lighting).

TE’s Inside Device Connectivity portfolio (Source: TE Connectivity)

Interconnects for military, aerospace, and UAVs

Samtec Inc. recently expanded its SMPM cable-to-board precision RF connector family with small-form-factor threaded cable-to-board-mated sets, targeting high-vibration environments. Suited for applications such as military, aerospace, and communication applications, the connector assemblies feature a threaded SMPM MIL-STD-348 interface with a retractable threaded coupling nut.

High-vibration environments can exceed the retention capabilities of traditional push-on RF interconnects, Samtec explained, requiring a more secure and robust connection.

The threaded SMPM cable-to-board-mated connector sets—including the RF047-A and RF086 millimeter-wave, low-loss cable assembly families handling up to 67 GHz, as well as the SMPMT threaded, SMPM millimeter-wave board-mount plugs available up to 60 GHz—are designed with enhanced mechanical strength. They feature full detent or smooth bore for varying retention forces and offer mixed technology board termination, which provides resistance to mechanical stress and supports high frequency.

The RF047-A is a 0.047-inch, low-loss, flexible microwave cable assembly (29 AWG) with an extremely small bend radius of 3.18 mm. The RF086 is a 0.086-inch, low-loss, flexible cable (23 AWG) with a bend radius of 8.9 mm. Both operate up to 125°C. A variety of end options are available for application-specific customization.

These precision RF connectors are available from stock. The RF047-A cable assembly and SMPMT threaded plugs are part of the Samtec Reserve program with one-day shipment.

Samtec’s threaded SMPM cable-to-board-mated connector sets (Source: Samtec Inc.)

For avionics and UAVs, Times Microwave Systems launched its Levitate cable assembly line for both military and commercial RF systems. Designed for efficiency, weight savings, and electrical performance, these ultra-lightweight cable assemblies with minimal loss are suited for avionics applications across UAV Groups 1 through 5.

Times Microwave Systems claims that the Levitate assemblies provide the lightest weight per unit of loss available on the market today, enabling engineers to reduce overall system mass without compromising RF performance. They cover a range of airborne applications, including flight control, communications, and surveillance.

Providing a balance between cost, performance, and availability, the Levitate cable assembly is available in multiple sizes, including the LVT047, LVT086, LVT141, LVT157, and LVT196. All assemblies are engineered for dual use in military and commercial RF systems. The flexible construction of the LVT047, LVT086, and LVT141 assemblies is suited for in-the-box applications, and the ultra-lightweight LVT157 and LVT196 support critical RF runs connecting antennas to LRUs.

Times Microwave Systems’ Levitate cable assembly line (Source: Times Microwave Systems)

Connectors for industrial automation

Aimed at delivering greater design flexibility and simplicity, binder USA LP, a subsidiary of binder Group, recently announced a new generation of hybrid connectors for industrial automation. The B23 series combines power supply and shielded data transmission in one compact connector and enables Ethernet transmission rates of up to 100 Mbits/s.

The B23 connector is built for one-cable-automation concepts, addressing key market requirements that call for a reduced cabling effort and increased data rates in industrial systems. This simplifies integration and system architectures.

The hybrid connector reduces cabling effort by enabling power and communication via a single interface, which also reduces installation times and potential sources of error, binder said. One example cited is drive technology, in which servo motors and drive systems can be connected with just one cable. It can also be used in modular machine and plant architectures, as well as robotics and flexible manufacturing systems.

The B23 connector also targets the trend toward decentralized automation that requires rugged, pluggable connections and a high degree of protection. Key specs include power transmission up to 28 A at up to 630 V and shielded Ethernet/EtherCAT (according to Cat 5) data transmission up to 100 Mbits/s. Other features include a bayonet quick-locking system for secure connections, screw-clamp termination for field use, and IEC 61076-2-118 standardization.

Meeting both field and device integration requirements, the B23 is available in a field-attachable version and as a panel-mount connector for device installation. Versions with single-wire termination and THT contacts are available.

Binder’s B23 connector (Source: binder USA LP)

Hirose Electric Co. Ltd. expanded its high-density BGA mezzanine connector portfolio with a COM-HPC standard-compatible version that supports PCIe Gen5 (32 GT/s), Gen6 (64 GT/s PAM4), and 100-Gb Ethernet (4 × 25 Gb). The IT18 Series can be used in industrial automation, medical imaging, and T&M equipment.

The BGA mezzanine connector features an ultra-high-density pin count of 400 positions in a 0.635-mm pitch, delivering high-speed transmission in a low profile. Stacking heights include 5 mm and 10 mm. It also features high crosstalk suppression, including far-end-crosstalk cancellation technology.

The open-field design (open pin-field grid array) of the connector is adaptable to various layouts, allowing for greater flexibility across different applications. Because pins are not locked into a fixed pattern, customers can route signals, grounds, and power to improve density and performance, which also helps with signal-integrity optimization, Hirose said.

Featuring a rugged design, the IT18 Series connector uses a metal cap to reduce warpage and protect contacts from flux. The cap minimizes reflow defects by suppressing deformation during heating and protecting against foreign particles in the environment, the company said. Other key features include a large guide to ensure proper mating and retention tabs that prevent cracks in solder balls.

Hirose’s IT18 Series BGA mezzanine connector (Source: Hirose Electric Co. Ltd.)

The post Optimize hi-rel designs with rugged, flexible interconnects appeared first on EDN.

Full-featured, high-priced products address many users’ needs. But free and low-cost options, sometimes for augmentation purposes, other times operating standalone, also have their place.

As regular readers may already have noticed, I regularly embed FCC certification IDs in my teardowns and other writeups, complete with links to the associated FCC website pages for additional documentation, images, and other information on the products I’m discussing. Long ago, so far in the past that I no longer remember where and when, I came across someone else (iFixit, mebbe?) who was using shortcut URLs of the following format instead of fuller URLs:

http://www.fcc.io/INSERT_FCC_CERTIFICATION_ID

You can tell how old the service is by the fact that it still works using the non-secure version of HTTP. In fact, for a long time, my potentially faulty recollection is that the “https” version of the URL didn’t work at all, although I just checked and it’s now supported, too.

I long assumed this shortcut interstitial URL service was run by the FCC itself. However, motivated by curiosity one day, I entered http://www.fcc.io standalone in my web browser. Here’s what I found on the home page:

FCC.io

What?

A simple search and URL shortener for FCC ID queries.

Why?

I can never find the search form on the FCC site, so fcc.io should be easy enough to remember. Fcc.io provides a way to share FCC ID searches with other people via links, email, IRC, or IM.

How?

The URL scheme is simple:

• https://fcc.io/”FCC ID”

Try these:

• https://fcc.io/NPI
• https://fcc.io/NPI71646
• https://fcc.io/grantee/lego

To-do

Other search suggestions?

Email to dominicgs@gmail.com

Disclaimer

Neither this site, nor its author, are affiliated with the FCC in any way.

Running on GitHub pages

Good for you, dominicdgs@gmail.com (who appears to be Dominic Spill, formerly “next door” to me in Evergreen, CO per his Github page and now with Apple in Cupertino, CA per LinkedIn)!

Another example, which I briefly introduced recently, are the open source FreeFileSync and related RealTimeSync utilities developed by the FreeFileSync project, and supporting Linux, MacOS and Windows systems alike. The ability to automatically backup or sync (the latter both uni- and bi-directionally) the contents of one or multiple directories to another storage device (a USB-C tethered RAID 1 external HDD array, in my case) became critical to my workflow when I added associate editor duties to my longstanding contributing editor relationship with EDN. The two-utility package has worked without a hitch in the two-plus months (as I write this) since I’ve installed them, and I anticipate further non-drama functionality in the future, too.

Per these and other examples to come, this post will therefore be a to-developer “love letter” regarding software packages and services that have become essential to me, and for personal and/or professional reasons. As you continue reading, think about what similar examples you can derive from your own life. You’ll have an opportunity to share them with us, too, at the end.

Enhanced text editors

MacOS comes bundled with the TextEdit graphical text editor, with others (Nano and Vim) also accessible via the Terminal command line. And if a beefier word processor is what you’re looking for, there’s always the also-gratis Pages. So why on earth would I pay $59.99 (new) or $29.99 (previous-version upgrade) for Bare Bones Software’s BBEdit? Check out this list of features. Or see what fellow fan John Gruber has to say about it, notably in a 30-year retrospective summary published four-plus years ago.

From my standpoint, the ability to automatically re-open one-to-multiple tabs’ worth of content, regardless of whether it’s/they’ve been saved recently (or at all, for that matter), after program shutdowns and restarts and even full operating system reboots, and as long as I haven’t manually closed a tab, is by itself worth the price tag. It’s “saved my bacon” on innumerable occasions.

If you’d like a free “taste” of the full-featured version, a 30-day evaluation time period is supported. And “Free Mode”, the successor to the original freeware TextWrangler software from the same company, will extend the gratis party to eternity if you don’t need access to any of the program’s paid-only capabilities.

What about Windows? Here the seemingly most common enhancement to the bundled graphical Notepad and command line Microsoft Edit editors is Notepad++ (Github link), which is free and open source (not to mention 20+ years old!). Its primary developer is Don Ho; another set of developers led by Andrey Letov recently ported it to MacOS while initially retaining the original name (and notably, without getting Ho’s permission first) and was subsequently compelled by both legal threats and broader community outrage to rename it to Nextpad++ (again, Github link).

And Linux? The already-bundled text editors are generally more robust in this case, befitting this operating system’s comparative “power user” community, but a diversity of add-on options unsurprisingly also exists. Linux users out there, I welcome your suggestions in the comments!

Networked TV services

Windows 7 reached End of Life (EOL) and officially lost extended support on January 14, 2020. Windows 8.1 followed it out the door on January 10, 2023. With them went official support for Media Center, a Microsoft-developed digital video recorder and media player application that first appeared within a special-purpose Windows XP edition in 2005.

I’ve been running various versions of Media Center since the very beginning, initially to ingest broadcast television coming over NTSC and (later) ATSC antenna feeds, later transitioning to cable television feeds in conjunction with a networked CableCARD receiver, and for subsequent display on televisions in conjunction with both Xbox game consoles and standalone Media Center Extender devices.

And I’ve continued doing so even though, as previously noted, the operating system foundations are no longer supported, not to mention the fact that the service’s built-in electronic program guide was discontinued on January 14, 2020. How? The alternative program guide data I’m tapping into is SchedulesDirect, a non-profit “community” (with, as far as know, exactly one active developer employee) and a $35 yearly membership fee.

And how do I get the SchedulesDirect-sourced data into Media Center? That’s where EPG123 (GitHub link), another one-person development project, comes in. Gary An has worked tirelessly for the past decade-plus (ever since Microsoft switched from Zap2it to Rovi as its guide data provider, even prior to shutting down its EPG service entirely) to create and maintain EPG123, fixing bugs, responding to SchedulesDirect service evolutions, and the like.

He’s also a regular support presence on the community forum at The Green Button website. And while he’s happy to accept donations, he doesn’t charge a penny for his software. Bless you, Gary!

An essential email add-on

Mozilla’s Thunderbird has been my personal email client of choice for nearing two decades now (just as the organization’s Firefox browser is for web access…and SeaMonkey is for HTML editing…), and I access email via POP3 so that I can exclusively retain an archive locally. So, you can probably imagine how voluminous my Thunderbird database is at this point. Everything’s (fairly) neatly organized into per-topic folders, mind you, but there are probably thousands of them at this point, in a multi-email account (plus RSS) and multi-level nested arrangement.

That’s why I heavily rely on an add-on called Nostalgy (GitHub link), which enables me to move (or copy) incoming emails from my inbox to a desired target folder, and more broadly from any source folder to another, using only convenient keystrokes. Why Nostalgy hasn’t been adopted by and natively included in Thunderbird by this point is baffling to me, both because of its inherent benefits and because the constant changes to the email client’s database structure and other factors make maintaining it a headache for a third-party developer alternative.

Speaking of which, the add-on was originally developed and maintained by Alain Frisch. Source code maintenance and enhancement duties were later taken up by Klaus Buecher, who renamed it Nostalgy++. It’s an oft-thankless task, as I gather from the commentary that accompanies both new-release notes and periodic requests for donations. But to that point, and as with EPG123, fiscal compensation is voluntary, not obligatory. Long may you continue to code, Klaus, and thank you for your software service!

Squashing a longstanding File Explorer bug

This last one’s a doozy. For decades now, through innumerable version updates small and large alike, Windows has proven itself incapable of permanently retaining user-requested changes to File Manager settings, either folder-specific or all-encompassing, and related to both file sorting and content display strategies.

I might, for example (and regularly do, in fact) tell it that I no longer want it to cluster together chronologically similar groups of files within a folder, instead displaying them solely in a basic alphabetized list format, and to more globally revise this particular setting. Or to tone down the displayed thumbnail size in image-related folders.

The requested changes “stick”…as long as I don’t move to a different folder, that is. Maybe, in fact, they remain as I’d previously requested the next time (or, pushing my luck, few times) I return to that folder. But usually, they immediately revert to defaults. And my random likelihood of ongoing settings-change-sticking success is even less if I quit and then re-open File Explorer, not to mention after a system reboot. Sooner or later, Microsoft insists that its default way is best.

Back in March, the company finally publicly acknowledged the problem (along with plenty of others) and promised that remedies were on the way. I’ll believe it when I see it. And I’m not going to wait. I’d already found, and happily am still using, an independently developed “fix” for these and other File Explorer quirks called WinSetView:

WinSetView provides an easy way to set Windows File Explorer default folder views. For example, if you want Details view, with a particular selection of column headings enabled across all folders, then WinSetView will do that for you.

For more details, please see the extended summary.

WinSetView is open source. It’s inobtrusive, either running portably or fully installed. It does what it promises, nothing more or less, and changes are easily reversible. And it’s free. Kudos to you, developers LesFerch and Thysbelon. You’ve enabled me to (arguably) cling to my sanity.

Now it’s your turn

These are all just examples, apparently particularly notable ones, because they’ve risen to the top of the list brainstormed and assembled in, and subsequently coming out of, my noggin. I’m confident that the catalog as it currently exists isn’t comprehensive, for me (I may think of and add one-to-a-few more entries before this piece is published, in fact) and certainly more globally. Which is where you come in.

What software and services, specifically focused in function and freeware-or-low cost, have you come across that help simplify your life? Share your thoughts in the comments, please, for both your own resultant fame and others’ consideration, adoption and benefit. Thanks!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

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• Open Source: Keep It Current Or Suffer The Consequences
• Open source: not always a successful course

The post Unsung software and services heroes ease our days appeared first on EDN.

Here’s a question your grandfather could have answered: Would you rather have a million dollars today or a penny that doubles every day for a month? Most people take the million. The penny reaches $5 million by day 30.

Human intuition is simply bad at exponential math. We think in straight lines, and compounding curves surprise us every time. Now run that intuition in reverse.

An AI coding agent that’s right 98% of the time sounds impressive. And 98% is a generous assumption, probably better than reality for most tasks. But apply that accuracy across 34 steps with no verification in the loop, and you’ve crossed the coin-flip line. More likely wrong than right. The math is 0.98^34 = 0.505.

The surprise is the same one your grandfather felt. And in a safety-critical development environment, the consequences are not a missed investment opportunity.

Sophisticated agentic systems don’t run open-loop. They compile, test, lint, and self-verify at each step, and the public record shows it works.

Andreas Kling ported Ladybird’s LibJS engine from C++ to Rust using AI agents across hundreds of human-directed prompts, producing 25,000 lines of Rust with zero regressions across 65,359 tests and byte-for-byte identical bytecode output. The human was in the loop at every decision point, which is precisely why it worked.

The Bun JavaScript runtime went further. AI Weekly highlighted that Claude agents rewrote roughly one million lines of Zig to Rust autonomously across 6,755 commits, passing 99.8% of its existing test suite. It also left 13,044 unsafe Rust blocks, where a comparable handwritten project would have 73. A passing test suite doesn’t surface this safety debt—it stops a safety-critical certification in its tracks.

Both of these projects succeeded because verification ran inside the loop at every step. They also illustrate exactly where the limits are. In most software development contexts, the floor is an efficiency problem. Verification catches it, the agent retries, and the process converges. Expensive in tokens and time, but recoverable.

In safety-critical development, the calculus is different. This is where functional correctness testing and safety-critical qualification part ways. Bun passed its own test suite. Ladybird produced byte-for-byte identical bytecode. Those are impressive results. But they are not safety cases. ISO 26262, DO-178C, and IEC 62304 don’t recognize self-generated test results as qualified verification evidence.

Your braking system software doesn’t get partial credit for passing tests it wrote for itself. Your insulin pump firmware isn’t certified on a curve. The standards assume deterministic tools producing verifiable evidence—qualified tools, documented configurations, and traceable outputs. An agentic workflow that self-verifies is better than one that doesn’t. But in safety-critical development, it still isn’t enough.

What safety-critical compliance actually requires isn’t vague.

ISO 26262 mandates a documented safety plan, requirements with bidirectional traceability from hazard analysis through to verified implementation, and evidence that coding guidelines—typically MISRA C or CERT C—were enforced by a qualified tool using a qualified configuration.

DO-178C adds structural coverage requirements. At the highest criticality levels, every statement, every branch, and every condition and its complement must be exercised by tests that are themselves traced to requirements.

IEC 62304 requires a software development lifecycle with documented verification activities at each phase. In every case, the evidence must be generated as the work happens rather than reconstructed afterward—and not self-certified by the tool that produced the artifact being evaluated.

The open-loop pipeline isn’t an edge case; it’s what every team promises to fix after the next release. A requirements review is handed to a code generator, a documentation tool, and a traceability updater with testing saved for the end. That’s not an agentic worst case. That’s a pipeline. At 98% per-step accuracy across 34 stages, you’ve crossed the coin-flip line before you’ve run a single test.

The answer isn’t a better model. It’s the same answer safety-critical engineers have always given to unreliable processes. You don’t improve your way to acceptable; you gate your way there.

Static analysis enforces expected coding patterns and flags dangerous anti-patterns like uninitialized memory, undefined behavior, and violations of MISRA or CERT rules that exist precisely because they’ve caused failures before.

Unit tests verify that individual components behave as specified under known conditions. And coverage in safety-critical development isn’t a spot-checking exercise. DO-178C requires 100% MC/DC coverage at DAL A, and ISO 26262 requires the same at ASIL D. Every line. Every branch. Every condition.

Each gate resets the accumulated uncertainty back toward zero before the next stage compounds it further. That’s not a new idea. It’s how you build software that people’s lives depend on.

The question AI raises isn’t whether to use gates. It’s whether the gates you already have are positioned to catch what an AI agent introduces and whether you’ve thought carefully about where in the workflow the uncertainty is actually accumulating.

The gates were designed for a world where code has an author who made deliberate choices. A human developer who writes an uninitialized variable made a mistake. A human developer who skips a boundary check made a tradeoff. Static analysis flags both—the developer understands the finding in context, and the correction is made by someone who knows what the code is supposed to do. The evidence trail is intact. The intent is recoverable.

An AI agent doesn’t make mistakes in that sense. It produces outputs that are statistically consistent with its training: plausible, often correct, and occasionally wrong in ways that look right.

The static analysis tool will still flag the MISRA violation. The unit test will still fail on the boundary condition. But the developer reviewing the finding is now one step removed from the original intent because there wasn’t original intent in the human sense. There was a probability distribution. And when you ask the agent why it made that choice, the answer is not recoverable in any form a certification auditor can use.

The gates catch the artifact. They don’t reconstruct the argument. In a safety case, you need both, and one of them must have been generated as the decisions were made, not reverse engineered from the output afterward.

The consumer technology press calls it “hallucination,” which means the AI confidently states something wrong. This term captures the symptom, but not the mechanism.

In safety-critical engineering the mechanism is what matters. ISO/PAS 8800, the emerging automotive standard for AI safety that the broader embedded industry is watching closely as a template, uses the term “functional insufficiency”: an unexpected error under specific conditions not adequately represented during development. As EDN noted, for engineers building software for medical devices, industrial automation, rail, aerospace, and defense, dismissing this document as “just for cars” would be a missed opportunity.

The distinction matters. Hallucination implies the system invented something from nothing. Functional insufficiency describes something more precise. The system performed exactly as its training data suggested it should, and the training data didn’t cover this case.

You can’t fix a hallucination by improving the model. You can’t fix a functional insufficiency that way either. What you can do is bound it, monitor it, and build an architecture that prevents it from propagating into a safety-critical decision unchecked.

None of this is an argument against AI in safety-critical development. These industries already have the architectural foundations to manage it responsibly. That argument is already lost, and it should be. AI tools are accelerating development, surfacing defects earlier, and handling the kind of repetitive verification work that exhausts engineers and introduces its own error rate.

The question was never whether AI would enter these industries. It’s here. The question is whether the engineering discipline surrounding it will keep pace.

Compound uncertainty doesn’t care about your intentions or your vendor’s benchmark scores. A 98% accurate agent in a 34-step open-loop workflow has already crossed the coin-flip line. Those numbers don’t improve because the use case is important or the schedule is tight.

Compound uncertainty in multi-step workflows. Even with 95% per-step accuracy, overall success rate declines sharply as the number of workflow steps (N) increases—not because model performance degrades, but because the workflow itself compounds error. Source: Parasoft

What does improve the outcome is treating AI in safety-critical development the way these industries have always treated unreliable components: with gates, evidence, and documented reasoning that survives an audit.

The standards that govern medical devices, aviation software, and automotive systems were written for a deterministic world. But the principles they encode—rigorous verification, traceable decisions, complete coverage, and structured safety arguments—turn out to be exactly the right response to a world where probabilistic behavior slipped into the development process before anyone checked its credentials.

ISO/PAS 8800 is the automotive industry’s first formal attempt to extend those principles into AI-specific territory. Other domains are watching. The framework outlined in the embedded world—manage uncertainty, bound it, argue it, and monitor it—applies whether you’re building firmware for a ventilator or a flight control system or an autonomous vehicle.

You will never eliminate functional insufficiency from an AI system. However, you can build an architecture that catches it before it becomes a safety event. That’s not a limitation of technology. It’s just engineering.

Arthur Hicken is a senior software evangelist at Parasoft.

Ricardo Camacho is director of product strategy for embedded and safety critical compliance at Parasoft.

Related Content

• AI Safety Moves to the Forefront
• Specifying Objectives is Key to AI Safety
• Can We Trust AI in Safety Critical Systems?
• Safe Automated Driving Starts with Architecture
• The impact of AI/ML on qualifying safety-critical software

The post Compound uncertainty: AI’s hidden risk in safety-critical development appeared first on EDN.

Wide-bandgap (WBG) materials, particularly silicon carbide (SiC) and gallium nitride (GaN), are no longer considered exotic semiconductors. The automotive industry has chosen them for their ability to switch faster, tolerate higher blocking voltages and temperatures, and dissipate less energy than conventional silicon.

The physical and electrical characteristics of SiC and GaN enable improved efficiency in electric and hybrid drivetrains, higher power density, and better thermal management. This article examines the current state and next steps for both technologies across different key automotive areas, including traction inverters, on-board chargers (OBCs), DC/DC converters, and auxiliary power systems.

Traction inverters: the realm of SiC, but GaN makes headway

The transition from a 400-V to 800-V bus architecture, a common trend in electric-vehicle design, has halved the current required to deliver the same power. This reduction, in turn, enables ultra-fast charging, as EVs can absorb more power without incurring hazardous current levels or excessive heating. Moreover, the 800-V bus power delivery significantly lowers internal heat loss and allows for lighter and thinner vehicle wiring.

This architecture shift is a key factor for WBG adoption. At 800 V, the traction inverter operates with bus voltages that are very close, or even higher, than the rating limits of conventional silicon power devices, such as IGBTs.

SiC MOSFETs, rated at 1,200 V or higher with low on-resistance (RDS(on)) and fast-switching behavior, are suited for this application. In 2021, SiC inverters had a market share of less than 8% in global EV production, reaching 24% by 2026, according to market research firm Market Intelo. Analysts estimate that by 2030, SiC inverters will reach a 55% market share across EV production.

In January 2025, Wolfspeed Inc. introduced its Gen 4 SiC MOSFET platform, covering 750-V, 1,200-V, and 2,300-V voltage classes in discrete, module, and bare-die form. Compared with the previous version, Gen 4 technology reduces the specific on-resistance (Ron,sp) at high temperatures by up to 21% (with an even higher reduction at low temperatures) and provides improved turn-on performance with reduced ringing.

Built on this platform are the 1,200-V six-pack power modules (Figure 1), part of the automotive-qualified YM Six-Pack module line. These modules integrate a direct-cooled pin-fin baseplate and use sintered die-attach layers, copper-clip interconnects, and epoxy encapsulation to improve power-cycling capability. According to Wolfspeed, they deliver a 3× higher power-cycling capability at rated operating temperature than comparable competitor modules. The YM package size is compatible with existing IGBT inverter housings, simplifying platform migration.

Figure 1: Based on Wolfspeed’s Gen 4 SiC MOSFET technology, the six-pack YM power modules comply with the AQG-324 automotive standard. (Source: Wolfspeed Inc.)

Wolfspeed recently introduced its Gen 5 SiC MOSFET planar technology. Manufactured in Wolfspeed’s 200-mm fabs, the latest generation further reduces Ron,sp by up to 27% for 1,200-V devices, raising continuous junction temperature to 200°C for improved reliability.

STMicroelectronics provides 750-V and 1,200-V, automotive-qualified devices for 400-V and 800-V EV traction inverters, thanks to the introduction of the company’s Gen 4 SiC MOSFET technology. Gen 4 devices offer reduced RDS(on) (8.2 mΩ and 10.2–10.9 mΩ for the 750-V and 1,200-V classes, respectively) to cut conduction losses.

ST also announced the ongoing development of a higher-temperature-capable architecture to further reduce RDS(on) at high junction temperatures, meeting the requirements of air-cooled or passively cooled traction inverter designs.

Rohm Semiconductor introduced the TRCDRIVE pack, designed for xEV traction inverters. Built on Gen 4 SiC MOSFET technology, these 750-V and 1,200-V, two-in-one SiC molded modules feature higher power density, a compact layout that optimizes heat dissipation, and signal terminals supporting press-fit mounting (Figure 2).

Figure 2: Rohm’s TRCDRIVE pack modules offer high power density and simplify assembly through press-fit pins. (Source: Rohm Semiconductor)

Rohm also partnered with Schaeffler on a high-voltage inverter brick in mass production for a leading Chinese automaker. The brick integrates Rohm’s Gen 4 SiC MOSFET bare chips with a DC-link capacitor, a cooling solution, and a DC boost function. The design allows 800-V EVs to use a 400-V charging infrastructure. More recently, Rohm announced the availability of its Gen 5 SiC MOSFETs, targeting xEV traction inverters with a further reduction of RDS(on) at high temperatures.

Cambridge GaN Devices (CGD) has developed a 650-V ICeGaN device for automotive applications, including xEV traction inverters. While the device offers a lower blocking voltage than SiC counterparts, according to CGD, it can be paralleled without suffering imbalance or requiring a careful selection of components with similar characteristics.

The ICeGaN device integrates protection features, offering low RDS(on) (9 mΩ), reduced losses, and improved thermal management. CGD has also showcased a multilevel, 800-V inverter based on this device that can power electric motors to over 100-kW peak, 75-kW continuous power.

OBCs: SiC and GaN share the space

The OBC converts the AC grid power to the DC required by the main battery. It operates at lower power (typically 11 kW to 22 kW for passenger cars) than the traction inverter. SiC MOSFETs are currently the most common choice for OBCs, particularly for 800-V battery systems in which 1,200-V SiC devices offer wide operating margins and high reliability.

Rohm released a family of 750-V and 1,200-V SiC molded modules in the HSDIP20 package for xEV OBCs. The package integrates components for power-factor correction (PFC) and LLC conversion, including SiC MOSFETs, an insulating substrate, and decoupling elements. Available in four-in-one and six-in-one configurations, the modules reduce chip temperature by up to 38°C under a 25-W output load compared with discrete SiC MOSFETs.

Navitas Semiconductor announced the automotive qualification of its high-power GaNSafe Gen 4 ICs to both AEC-Q100 (integrated circuit) and AEC-Q101 (discrete transistor) standards (Figure 3). The GaNSafe family integrates control, gate drive, and sensing. It also offers short-circuit protection with a maximum latency of 350 ns, 2-kV ESD protection on all pins, programmable slew rate control, and elimination of the negative gate drive requirement. The devices are suited for OBCs and HV-LV DC/DC converters.

Navitas also introduced the first production-ready, 650-V bidirectional GaNFast ICs with IsoFast isolated gate drivers. This solution enables OBCs with a single-stage AC/DC topology that eliminates the conventional two-stage approach (with a separate PFC and DC/DC).

Figure 3: For the automotive-qualification process, Navitas prepared a reliability report with over seven years of production and field-data analysis. (Source: Navitas Semiconductor)

DC/DC converters and 48-V systems: GaN gains ground

GaN power devices are being adopted in DC/DC converters for EV applications. In EVs, DC/DC converters step down the main 400-V or 800-V battery bus to 12 V or 48 V for vehicle auxiliary loads. For example, Vitesco Technologies selected Infineon Technologies AG’s CoolGaN 650-V devices for its Generation 5+ DC/DC converter. The fast-switching capability of GaN at 650 V enables higher converter switching frequencies, which reduces the size of the magnetics and filtering capacitors.

Figure 4: Infineon’s 100-V CoolGaN transistors target applications such as zone control and main DC/DC converters, auxiliary systems, and Class D audio amplifiers. (Source: Infineon Technologies AG)

Also, auxiliary vehicle systems, such as electric power steering pumps, cooling fans, HVAC compressors, and 48-V mild hybrid motor generators, operate at voltage levels at which 100-V- to 200-V-rated GaN devices are fully suitable today.

One example is Infineon’s automotive-grade GaN transistor family that is suitable for low-voltage subsystems, such as 48-V and auxiliary power rails in hybrid and full-electric vehicles. These CoolGaN 100-V G1 devices (Figure 4) are qualified to AEC-Q101.

SiC is also used in DC/DC converters, particularly for bidirectional designs operating from 800-V battery systems. The Rohm HSDIP20 molded modules mentioned in the OBC section are specified for both PFC and LLC DC/DC stages, making them suitable for OBC and DC/DC converter applications.

Final considerations

After reaching mature status as a semiconductor technology, the primary challenge for SiC has shifted to scaling up production volume and reducing costs. The wide adoption of SiC in the automotive industry has forced the transition from older, 150-mm to 200-mm wafers, with the setup of dedicated fabs. This shift significantly reduces the cost of single chips and increases the yield per wafer. Wolfspeed has advanced production by developing the industry’s first 300-mm, single-crystal SiC wafer.

In the past, GaN faced issues with automotive adoption due to a lack of long-term field-reliability data. As mentioned, several GaN devices have successfully achieved AEC-Q101 and AEC-Q100 qualifications. Moreover, several manufacturers, including Texas Instruments Inc., are claiming a failure-in-time rate for GaN devices below 1 (fewer than one failure per billion device-hours) over a targeted 10- or 15-year lifecycle.

Interestingly, GaN is also experiencing a 300-mm trend. Because GaN is typically grown on top of standard silicon substrates (GaN-on-Si), companies such as Infineon have scaled 300-mm GaN power wafer technology by using existing silicon manufacturing lines, lowering the device costs.

Imec also announced plans to manufacture 300-mm GaN wafers with several partners, including Aixtron, GlobalFoundries, KLA Corporation, Synopsys, and Veeco. The GaN program will focus first on using 300-mm Si(111) as a substrate for low-power applications, followed by high-power applications (650 V and above) using 300-mm semi-spec and CMOS-compatible QST­ engineered substrates from Qromis Inc.

The post How SiC and GaN are reshaping automotive power electronics appeared first on EDN.

Based on BrainChip’s Akida neuromorphic engine, the AKD1500 edge AI coprocessor is now available in a compact M.2 2230 (22×30 mm) form factor. The card features a B+M key edge connector for use with Raspberry Pi 5 and compatible host systems, enabling fanless, plug-and-play AI acceleration without redesigning existing power or cooling systems.

Operating from a 3.3-V supply, the AKD1500 M.2 card connects through a two-lane PCIe Gen2 host interface. The coprocessor integrates 32 neural processing units (NPUs) and delivers up to 800 effective GOPS (INT4) for edge AI inference. It also includes 1 MB of dual-port on-chip memory and consumes a typical 250 mW at 400 MHz.

The event-based digital architecture delivers ultra-low-power acceleration for standard neural network models and supports on-device learning, enabling applications to adapt without a cloud connection or full model retraining. Models are developed and optimized using BrainChip’s MetaTF software flow with TensorFlow/Keras and PyTorch front ends before deployment to the card.

The AKD1500 M.2 card with a B+M key connector is priced at $129 and is available for purchase directly from BrainChip.

AKD1500 M.2 product page 

BrainChip Holdings 

The post Edge AI coprocessor adopts M.2 form factor appeared first on EDN.

Advantech is launching a portfolio of servers based on AMD EPYC 9006 SP8 processors to support next-generation AI infrastructure. Servers, such as the SKY-924E5F, provide the scalability and reliability required for AI, high-performance computing (HPC), networking, and mission-critical industrial workloads.

EPYC 9006 series server CPUs feature up to 128 Zen 6 or Zen 6c cores, 256 threads, and 2-nm process technology, delivering up to a 20% average performance improvement over the previous generation and up to a 20% performance-per-watt improvement. These processors enable more virtual machines, higher throughput, and improved system efficiency. With up to 128 PCIe Gen6 lanes per CPU, CXL 3.1 memory expansion, and support for DDR5-8000MHz and MRDIMM-12800MHz, the EPYC-powered servers provide balanced compute, memory, and I/O performance.

The edge servers support GPU-accelerated AI workloads and AFA-ready high-density E1.S/E3.S NVMe SSD storage. The lineup includes the following models:

• SKY-642E5, 4U MGX GPU server for large-scale AI acceleration
• SKY-722E5, 2U DC-MHS server with DC-SCM capability for modular data center and edge AI deployments
• SKY-712E5, 1U DC-MHS server with HHHL and FH-3/4L expansion card compatibility for high-density enterprise edge and cloud workloads
• SKY-822E5, 2U short-depth DC-SCM modular server accommodating 2–3 dual-slot GPU cards for space-constrained edge data centers
• SKY-924E5F, 2U 4-node front-access server for distributed edge computing
• ASMB-982 and ASMB-832, server boards for flexible, expandable system designs

A timeline for server availability was not provided at the time of this announcement. Learn more about the Advantech + AMD EPYC 9006 platform here.

Advantech

The post Advantech AI servers leverage AMD EPYC appeared first on EDN.

Optimized for physical AI, AMD’s Ryzen AI Embedded X100 series processors combine CPU, GPU, and NPU resources on a single embedded SoC. With up to 16 AMD Zen 5 CPU cores, an integrated GPU, power-efficient NPU, and unified memory, the processors handle perception, reasoning, and real-time control workloads in robotics, industrial automation, aerospace and defense, and other embedded systems.

AMD says the series delivers up to 2.1× higher multithreaded CPU performance, 1.7× higher graphics performance, and 3.5× higher AI token generation with 1.4× faster time-to-first-token than Intel Core Ultra Series 3 processors. The company also says the processors provide up to 3× higher peak FP32 performance than the NVIDIA Jetson T5000 and an average 1.7× faster beamforming for cardiac ultrasound than the NVIDIA RTX 4000 Ada.

The Ryzen AI Embedded X100 series supports an open software stack with Linux, the AMD ROCm GPU software stack, the Xen Hypervisor, and AI frameworks including PyTorch, ONNX, and TensorFlow. AMD also provides tools to migrate CUDA codebases to ROCm.

Production availability of the Ryzen AI Embedded X100 series is expected in Q4 2026. Learn more about the processors on the product page or in AMD’s technical blog.

Advanced Micro Devices 

The post Ryzen processors power physical AI workloads appeared first on EDN.

Advanced Energy’s AIH03ZPFC power factor correction (PFC) converter delivers 1100 W of output power in a half-brick form factor. The board-mount module achieves up to 97.3% peak efficiency and a power density of 380 W/in³. According to the company, this represents a 2.3% improvement in efficiency and a 44% increase in power density over its previous-generation PFC devices.

The AIH03ZPFC integrates features that enhance functionality in a small half-brick design, including internal inrush limiting, digital PMBus control and monitoring, and auxiliary power support for external housekeeping functions. These capabilities make the converter well suited for industrial, medical, defense, and telecommunications systems with demanding size and efficiency requirements.

The AIH03ZPFC provides a 390-VDC output with 1% load regulation, maintains a unity power factor across an 85-VAC to 264-VAC input range, and requires no power derating under low-line conditions.

Baseplate contact cooling supports operation from -20°C to +100°C, with startup at temperatures as low as -40°C. The encapsulated half-brick package measures 2.4 × 2.3 in. (61 × 58.4 mm) and has an installed height of 0.52 in. (13.3 mm).

AIH03ZPFC product page

Advanced Energy Industries

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Cadence says its AuraStack AI Super Agent is the industry’s first agentic AI platform for PCB and advanced packaging design. Running on the company’s Allegro AI Studio and accelerated by NVIDIA Blackwell GPUs and NVIDIA CUDA-X libraries, the platform coordinates domain-specific AI agents across planning, implementation, and tightly integrated multiphysics analysis. AuraStack joins Cadence’s ChipStack, InnoStack, and ViraStack AI Super Agents, extending the company’s agentic AI portfolio across IC design, advanced packaging, and PCB design.

Built on the same architecture as Cadence’s ChipStack AI Super Agent, AuraStack combines agentic AI with simulation and optimization tools to automate design exploration, implementation, and signoff. An AI-driven multiphysics foundation concurrently models electrical, thermal, and mechanical behavior to support earlier design optimization.

According to Cadence, AuraStack can accelerate time to market by up to 2× and increase productivity by up to 15× while identifying system issues earlier in the design process to help reduce costly respins. It also enables system-level co-optimization with advanced packaging technologies, including CoWoS, to improve product performance and manufacturability.

Cadence plans to make the AuraStack AI Super Agent available in 2026.

AuraStack product page 

Cadence

The post AI platform unifies PCB, advanced packaging workflows appeared first on EDN.

As the automotive industry shifts toward software-defined vehicles (SDVs), with features and updates delivered via software, vehicle electrical/electronic (E/E) architectures are evolving. These architectures are moving away from traditional flat and domain-based designs, in which separate control units for each function were the norm, to zonal architectures that group vehicle functions based on various criteria, such as physical location, application group, and other functional criteria in zone electronic control units (ECUs).

In a zonal architecture, each zone of a vehicle, such as front, rear, or cabin, has a high-performance controller managing local devices and communicating with other controllers over high-speed networks. This approach is faster to update, easier to scale, less complex, and even cheaper, but it also presents new technical challenges for automakers to overcome. The good news is that innovative microcontroller (MCU) solutions can help tackle those challenges.

Key challenges in the shift to zonal architectures

Zonal architectures offer clear benefits of reducing wiring complexity and consolidating compute resources.

However, each zone controller in an SDV must handle a wide range of tasks, from low-level real-time control of sensors and actuators (such as sensing braking pressure, steering angle, or controlling window-lift motors) to high-level data processing tasks (including controlling advanced safety systems or vehicle dynamics or running local AI models to process sensor data). This means the ECUs in a zonal design require compute capabilities that can handle both time-sensitive and compute-intensive workloads concurrently.

Maintaining freedom from interference among functions is a key challenge. Zonal designs consolidate diverse functions, from safety-critical functions such as braking to non-critical functions such as body control on a single ECU with shared compute and communication resources. Without proper safeguards, a fault in one function could disrupt others.

To prevent this, robust isolation mechanisms such as hardware-enforced separation are needed. Ideally, these features should be embedded in the hardware design rather than software implementation to minimize the impact on performance, behavior, or safety.

In-vehicle networks also need rethinking. Modern SDVs generate massive amounts of data from sensors and devices, including cameras, LiDAR, and radar, to support advanced driver-assistance and autonomous-driving features. The vehicle network must ensure that this data is delivered in a predictable and time-sensitive manner.

Traditional in-vehicle networks such as CAN, LIN, and FlexRay struggle to meet these demands at the scale of the modern SDV. Moreover, Ethernet is increasingly used in vehicles for its advantages in performance, reliability, and connectivity options, and at the same time, many legacy devices in the vehicle still use CAN or LIN.

To ensure network performance and avoid communication bottlenecks, next-gen vehicle controllers should include native support for Ethernet and CAN networking on-chip. A well-architected MCU will also enable sufficient control and acceleration features to reduce latency and ensure predictable message delivery, ultimately resulting in deterministic communications at the vehicle level.

Next-generation automotive MCUs need to adopt improved, low-latency architectures and design philosophies to overcome key challenges in the shift to zonal architectures. (Source: NXP Semiconductors) Making updates secure, easy, and fast

A hallmark of SDVs is the ability and the need to receive secure over-the-air (OTA) updates throughout the vehicle’s life. This contrasts with traditional vehicle designs with dozens of ECUs for which updates are complex, time-consuming, and often performed only in service environments.

For an SDV built on a zonal E/E architecture, software updates can be pushed to a selected number of controllers that can be responsible for the software of an entire region of the vehicle, such as the front zone or the rear chassis zone. To support these frequent updates with minimal downtime, embedded nonvolatile memory (eNVM) needs to be upgraded as well to a more versatile option with much faster write speeds and higher endurance.

How modern MCUs lay the foundation for next-gen SDVs

Next-generation automotive MCUs need to adopt improved, low-latency architectures and design philosophies to overcome these challenges. Rather than relying on a homogeneous architecture, the implementation of heterogeneous cores optimized by functions is required.

The NXP S32K5 MCU, for example, integrates different kinds of CPU cores complemented by various accelerators for dedicated functions such as AI/ML, signal processing, and network acceleration, enabling designers to assign the right function to the right core. Furthermore, a dedicated low-power engine is available for simple tasks, such as periodic wakeups and sensor monitoring, which can help optimize battery life in electric vehicles.

The integration of multiple functions of mixed criticality warrants robust mechanisms to ensure freedom from interference. The S32K5 lives up to this challenge by implementing features such as XRDC, an in-house NXP IP for isolation and resource allocation in hardware from pin to core.

Moreover, dedicated network accelerators need to be implemented for CAN2CAN (communication between CAN networks) and CAN2ETH (communication between CAN and Ethernet networks) acceleration to ensure deterministic and low-latency architectures.

In addition, integrating an Ethernet switch with fast data-routing capabilities ensures that the latest-generation Ethernet vehicle architectures can achieve latency requirements with minimal CPU load.

With an embedded MRAM as the eNVM, the S32K5 offers write speeds that are 15× faster than conventional eFlash. Write without erase and endurance of 1M write cycles of MRAM helps optimize costs, simplify software development, and minimize downtime for the frequent OTA updates expected in an SDV architecture.

Building the foundation for next-gen SDVs

Zonal architectures are emerging as a necessity for next-gen vehicles because they align with the needs of SDVs. They concentrate compute, reduce complexity, and enable new, software-driven experiences. With the latest generation of MCUs as the building blocks, automakers now have more tools to develop zonal vehicle architectures to deliver the high performance, reliability, and flexibility required by next-gen vehicles.

The post Accelerating the shift to next-gen SDVs with zonal MCUs appeared first on EDN.

Self-heated Darlingtion transistor pair linearly senses airflow using just two wires for both power in and signal out.

Suppose we take a common TO-92 transistor and heat it to a constant temperature differential above ambient.  The power input required to keep it there will be determined by its thermal impedance ZT relative to the surrounding air. This suggests it might be handy for air flow measurement.  Maybe even moreso if it needed only a simple two-wire connection for both (phantom) power supply from, and signal delivery to, the supporting electronics.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Please see the Related content listings below for a more detailed treatment of the subject.  Figure 1 graphs the resulting power vs air speed relationship.  Unfortunately, it’s badly bent.

Figure 1 This graph logs power dissipated vs air speed of a TO92 held at a constant 31oC above ambient. Pw = 31/ZT.

Figure 2 shows a practical thermostat circuit to achieve and maintain the delta-T while outputting a signal predictably related to Pw.  It utilizes a Darlington sensor transistor pair (Q1 and Q2) to compensate for ambient temperature and convert the resulting nonlinear Pw curve into a linearized airflow readout.  Its current mode, phantom-power output is compatible and convenient for the long cable runs often seen in airflow measurement applications.

Figure 2 This circuit implements a phantom-powered Darlington anemometer with a 40-140 mA current mode output.  Adjust R10 to calibrate 40 mA (zero fpm), and R11 to calibrate 140 mA (250 fpm). The adjustments interact so some iteration may be necessary.  Sorry ‘bout that.

Q1 serves as the self-heated sensor with Q2 providing ambient temperature compensation.  Opamp A2 runs a feedback loop that forces a constant Vbe differential between Q1 and Q2.  This establishes a constant 31oC temperature differential between Q1 and ambient.  It does this (with the help of Darlington current gain) by forcing Q1’s current draw (I) through R3 to drive Q1’s power dissipation (Pw) to follow the Figure 1 curve of heat-vs-air flow.

Okay so far.  But how does compensation for Figure 1’s nonlinearity happen?   Well, happily the function of Q1’s Pw vs collector current I isn’t linear either.  In fact Pw = 5vI – I2R3.  That quadratic I2 term is the key.  It creates the lovely linearizing curve shown in Figure 3.

Figure 3 This graph logs Q1 power dissipation vs  collector current.  Pw = 5vI – I2R3.

The 2nd-order curvature of fig. 3 irons out (most of) the bend in Figure 1 and results in a linear 33 to 125 mA current draw over the 0 to 250 fpm flow rate range. Although the match isn’t perfect, when converted to the 40 to 140 mA by opamp A1 and output transistor Q4, the realized output is a calibrated readout of air speed that differs from ideal by less than +/- 5% from 0 to 250 fpm, as shown in Figure 4.

Figure 4 This graph logs anemometer output vs airspeed. FPM = 2.5(Iout – 40mA).

Note that most (~90%) of the output current is actually drawn by inverted regulator U1 as it maintains a constant 5v across the (thirsty) thermal transistors.  All that’s left for A2 and Q4 is to conduct several mA of shim current to establish and maintain calibration, which barely gets Q4 warm.  U1, however, can be called on to dissipate about three quarters of a watt and thus should be bundled in a TO220 or similar package.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Self-heated Darlington transistor pair comprises new air flow sensor
• Linearized portable anemometer with thermostated Darlington pair
• Nonlinearities of Darlington airflow sensor and VFC compensate each other
• Improve thermal airflow sensor PSRR with just two resistors
• A groovy apparatus for calibrating miniature high sensitivity anemometers

The post Phantom-powered solid-state linear airflow sensor appeared first on EDN.

When people talk about AI hardware, the conversation usually begins with the AI accelerator. That is understandable. GPUs, custom AI accelerators, CPUs, and high-performance compute dies are the most visible symbols of the AI era. They are also where much of the leading-edge semiconductor investment is focused.

Advanced logic nodes, extreme transistor density, high-performance standard-cell libraries, and sophisticated design methodologies are all essential to scaling AI compute. But an AI accelerator alone does not create AI infrastructure.

A modern AI system is not one chip, one fab, one node, or one technology family. It’s a physical system built from many semiconductor ecosystems converging through packaging, substrates, interconnect, power delivery, cooling, reliability engineering, and manufacturing scale. And that distinction matters.

The AI era is not only pushing logic scaling. It’s forcing the semiconductor industry to rethink how different fab outputs—logic, memory, analog, power, compound semiconductor devices, photonics, MEMS, and mature-node control silicon—come together as one physical infrastructure platform. In other words: AI infrastructure is becoming a multi-fab physical realization stack.

This is the missing link in many AI hardware discussions.

The visible part: Leading-edge logic

The most visible part of AI hardware is the leading-edge logic die. This includes GPUs, CPUs, AI accelerators, network processors, and custom compute engines. These devices depend on advanced process technology, dense routing, high-performance transistors, complex power grids, and increasingly sophisticated design automation.

But the logic die is only the center of computation; it’s not the full system. The accelerator may execute the matrix operations, tensor workloads, inference engines, training loops, and dataflow schedules, but its usefulness depends on everything around it.

• How fast data can reach it
• How close memory can be placed
• How efficiently power can be delivered
• How heat can be removed
• How signals can escape the package
• How optical or electrical I/O can scale
• How the package can be manufactured and yielded
• How the system can be tested, qualified, and deployed

This is why AI hardware is no longer just a logic-node conversation. The accelerator is the most visible object, but the infrastructure stack, outlined below, is the real product.

1. Memory fabs: HBM becomes part of the compute architecture

AI compute is deeply memory constrained. The value of an accelerator depends not only on peak compute performance, but on how effectively it can access data. This is why memory fabs are central to AI infrastructure.

DRAM, NAND, and especially high-bandwidth memory (HBM) are no longer secondary components in the system. HBM has become part of the AI compute architecture itself. The location, bandwidth, thermal behavior, power profile, and package integration of memory directly affect system-level performance. This changes the role of packaging.

Advanced packaging platforms such as CoWoS, interposers, bridges, and other high-density integration methods are not merely ways to place chips together. They are mechanisms for bringing logic and memory into a physical relationship that conventional board-level integration cannot support.

The memory fab produces the memory device, but the AI system requires memory to be integrated into a bandwidth-dense, thermally stable, mechanically reliable, and yieldable package. That is physical realization.

2. Analog and mixed-signal fabs: The hidden interface layer

AI hardware may appear digital from the outside, but every real system depends on analog and mixed-signal functions. Interfaces, clocking, sensors, converters, retimers, voltage regulators, power management ICs, monitoring circuits, and control loops often come from process technologies very different from leading-edge logic.

These functions are not always glamorous, but they are essential. They help manage signal integrity, power sequencing, telemetry, control, protection, timing, and communication between the digital compute die and the rest of the system. This is one reason mature-node and specialty-node capacity remains important.

Not every device in an AI system belongs on the most advanced logic node. Many functions are better implemented on older, more stable, more cost-effective, or more specialized processes. AI infrastructure therefore depends on both leading-edge and non-leading-edge semiconductor manufacturing. The system is advanced because the pieces work together, not because every piece is manufactured on the smallest node.

3. Power semiconductor fabs: Energy delivery becomes a scaling limiter

AI systems are power-hungry. As accelerators, memory stacks, switch chips, and rack-level systems scale, power delivery becomes one of the central limits. This pulls power semiconductor fabs directly into the AI infrastructure discussion.

Power conversion, voltage regulation, current delivery, board-level power architecture, rack-level distribution, and data-center energy efficiency are now deeply connected to semiconductor scaling. Technologies such as silicon power devices, GaN, SiC, advanced voltage regulators, and power management ICs all become part of the AI hardware stack.

The challenge is not simply generating more compute. The challenge is delivering usable power to the compute fabric with acceptable loss, noise, heat, and reliability. This is where chiplet and package architecture become tightly coupled to power architecture.

The industry can no longer treat power delivery as a board-level afterthought. For high-current AI systems, power is a physical design problem across die, package, substrate, board, rack, and facility. A compute die may come from a leading-edge logic fab, but the system cannot scale unless the power ecosystem scales with it.

4. Compound semiconductor fabs: Efficiency, RF, and high-performance physical interfaces

Compound semiconductor technologies such as GaN, SiC, GaAs, and related material systems are also part of the broader AI infrastructure stack. They are important for high-efficiency power conversion, RF systems, high-frequency communication, and specialized physical interfaces. While they may not sit inside the main AI accelerator, they support the physical infrastructure around advanced compute.

This matters because AI systems are becoming more energy- and communication-limited. As data centers scale, the efficiency of power conversion, the quality of high-speed links, and the ability to move signals across packages, boards, racks, and facilities become increasingly important. Compound semiconductor devices can play a role in those parts of the system.

Again, this reinforces the broader point: AI infrastructure is not a single-fab product. It’s a convergence of many semiconductor technologies.

5. Photonics fabs: Data movement becomes optical

AI scaling is also stressing electrical interconnect. As systems grow from single accelerators to multi-chip modules, boards, racks, clusters, and data centers, data movement becomes a dominant challenge. Electrical I/O remains essential, but optical communication is becoming increasingly important for bandwidth, distance, energy efficiency, and system architecture.

This brings photonics fabs into the AI infrastructure stack. Silicon photonics, lasers, modulators, detectors, waveguides, optical transceivers, and eventually co-packaged optics (CPO) all represent a different manufacturing and integration ecosystem from conventional logic.

But photonic devices alone do not solve the problem. They must be connected to ICs, packaged with optical interfaces, aligned to fiber or waveguides, stabilized against temperature and mechanical stress, tested at the package level, and qualified for product deployment.

This is why CPO is not only a photonics problem; it’s a packaging, thermal, mechanical, electrical, optical, manufacturing, and reliability problem. A photonics fab can create the optical device. But AI infrastructure requires the optical path to become a stable product-scale system.

6. Mature-node fabs: The infrastructure control layer

Mature-node fabs are often underestimated in AI discussions. But AI infrastructure depends heavily on mature-node silicon for control, sensing, power management, monitoring, security, timing, industrial interfaces, and system management. Many of these functions do not require leading-edge process nodes. On the contrary, they may benefit from mature, robust, and well-characterized process manufacturing technologies.

The AI system may be marketed around the accelerator, but it operates through a large population of supporting devices. Controllers, power management ICs, sensors, retimers, interface chips, baseboard management devices, and other infrastructure ICs help keep the system functional, observable, and controllable.

Without this layer, the accelerator is only a powerful device without a complete operating environment. This is another reason the AI era should not be understood only through leading-edge logic capacity.

Advanced packaging as the convergence platform

If many fab ecosystems create the pieces, advanced packaging becomes one of the main places where those pieces converge. This is why CoWoS, CoWoP, chiplets, CPO, interposers, bridges, substrates, wafer-scale integration, and advanced package-to-board transitions are so important.

They are not just packaging formats; they are also physical convergence platforms. They bring together logic, memory, photonics, power delivery, substrates, interconnect, thermal paths, and mechanical constraints into one manufacturable system.

But that convergence is difficult because each technology arrives with different physical requirements:

• Logic needs dense routing and power delivery
• HBM needs high-bandwidth proximity and thermal control
• Photonics needs optical alignment and temperature stability
• Power devices need current handling and efficiency
• Analog interfaces need noise control and signal integrity
• Substrates need dimensional stability, low loss, and manufacturability
• Cooling systems need physical access to heat sources
• Test flows need visibility into the assembled system
• Reliability flows need confidence across materials and interfaces

This is why advanced packaging is not only “putting chips together.” It’s the physical realization layer of AI infrastructure.

Why “one fab” thinking is no longer enough

Traditional semiconductor conversations often separate the world into categories: logic, memory, analog, power, photonics, packaging, board, system. That separation is useful for organization. But it can hide the real scaling challenge: how AI infrastructure forces these domains to interact.

The logic die affects memory placement. Memory placement affects package size and thermal behavior. Thermal behavior affects power delivery. Power delivery affects substrate design. Substrate design affects signal integrity and manufacturability. Optical I/O affects package architecture. Package architecture affects test access, reliability, and yield.

The outcome is a coupled physical system. A limitation in one layer can become a bottleneck for the entire infrastructure platform. This is why the industry needs to think beyond individual fab outputs and toward a connected realization stack.

From device performance to physical realization

Device performance is still important. Material properties are still important. Transistor density is still important. But they are not sufficient by themselves. A material with excellent properties must still be processed, patterned, bonded, inspected, assembled, tested, and qualified.

A photonic device with strong lab performance must still survive package stress, temperature drift, fiber attach, calibration, and product reliability. A power device with high efficiency must still fit into a board, rack, or package-level power architecture. A high-density substrate must still meet warpage, routing, via, reliability, yield, and cost targets.

An AI accelerator with impressive compute density must still receive data, power, cooling, and system-level integration. This is the central shift: The next era of AI hardware will not be defined only by the best device. It will be defined by the best realized system.

The multi-fab physical realization stack

A more complete way to view AI infrastructure is as a multi-fab stack:

• Logic fabs create the compute engines
• Memory fabs create the bandwidth and capacity layer
• Analog and mixed-signal fabs create interfaces, control, and conversion
• Power semiconductor fabs support efficient energy delivery
• Compound semiconductor fabs enable high-efficiency power and high-frequency functions
• Photonics fabs enable optical data movement
• Mature-node fabs provide control, monitoring, and infrastructure silicon
• Packaging and OSAT flows bring heterogeneous devices into one manufacturable platform
• Substrate and materials ecosystems provide the physical foundation
• Thermal and cooling systems keep the infrastructure operational
• Test, reliability, and yield flows determine whether the system can scale

This is the AI physical realization stack. It’s broader than the accelerator, it’s broader than the package, and it’s broader than the fab.

AI infrastructure is a convergence problem

AI infrastructure is often described through the language of compute performance. But the real system is much larger. It’s a convergence problem across fabs, materials, packages, substrates, optics, power, cooling, manufacturing, test, reliability, and yield.

Leading-edge logic remains essential, but it’s only one layer. The AI accelerator becomes valuable when it’s connected to memory, powered efficiently, cooled effectively, packaged reliably, linked optically or electrically, controlled by supporting silicon, and manufactured at scale.

That’s why the next phase of AI hardware should be understood as a multi-fab physical realization stack.

• Different fabs
• Different materials
• Different devices
• Different process technologies
• One AI infrastructure system

The companies and ecosystems that win will not be those that optimize one layer in isolation. They will be those that connect many semiconductor technologies into reliable, manufacturable, and scalable infrastructure.

And for that, material properties are important, device performance is important, and packaging density is important. But physical realization is what makes them valuable.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Related Content

• True Wafer-Level Packaging
• Wafer Level Chip Size Package (WLCSP) Guidelines
• Intel’s Embarrassment of Riches: Advanced Packaging
• Nvidia, TSMC, and advanced packaging realignment in 2025
• Intel flash move could put wafer-level packages on the map

The post AI infrastructure is a multi-fab physical realization stack appeared first on EDN.

The global semiconductor industry is transitioning to the post-quantum cryptography (PQC) era. PQC is changing how digital systems defend against potential mathematical attacks. PQC algorithms are designed to protect against hackers who try to recover secret keys by breaking the underlying mathematics. However, physical hardware attacks can bypass mathematically secure algorithms, even if a PQC algorithm is perfectly implemented.

As organizations migrate to PQC, replacing the cryptographic assets being protected—PQC private keys, root keys, firmware signing keys—becomes costly and complex in deployed devices like automotive electronic control units (ECUs) and industrial or defense systems. When a chip processes post-quantum algorithms, it handles significantly larger key sizes and more complex mathematical operations than legacy cryptography.

This extended processing time and high computational intensity widen the vulnerability window, leaving the silicon exposed to physical tampering such as side-channel attacks (SCAs) and fault injection attacks (FIAs).

Mathematically upgrading to PQC only stops a hacker sitting at a quantum computer miles away. It does not stop a hacker from attempting physical attacks. This is where analog anti-tamper security IP comes into play. Analog sensors provide the first layer of defense to secure the silicon itself by detecting tampering techniques used in physical attacks, such as clock, voltage and temperature attacks, as well as electromagnetic and laser fault injection attacks.

Clock, voltage, and temperature attacks

A clock attack occurs when a hacker alters the incoming clock’s frequency or timing on a chip to cause glitches in an effort to interrupt normal operations and extract sensitive information. A clock attack monitor can be implemented to track the frequency and timing of the clock signal. If there is any unusual activity, an alert would be raised and preventive action taken.

A voltage glitch attack takes place when a hacker tries to tamper with the incoming power supply. Generating voltage drops or spikes can cause errors that impact encryption algorithms and bypass security procedures. A voltage glitch detector identifies when there is an unexpected change in voltage and sets off an alarm to reset or shutdown the system to protect against data loss.

A temperature or thermal attack involves a hacker quickly heating or cooling a device to generate timing or supply errors without having access to the clock signal or power supply. A temperature sensor can check for sudden temperature variations and then apply countermeasures if required.

Electromagnetic and laser fault injection attacks

An electromagnetic fault injection (EMFI) attack is when the hacker tampers with a device using an electromagnetic pulse, so no electrical contact or physical connection to the chip’s pins is required. An EMFI sensor can be integrated into the silicon to detect even small changes in the internal magnetic field on the device and respond swiftly to stop an attack from causing damage.

A laser fault injection (LFI) attack occurs when a laser beam is used by a hacker to induce errors to breach security and corrupt data. An LFI sensor is placed on a chip to monitor specific transient characteristics of a malicious laser pulse. If there are any indications of an attack, then the sensor can ensure that secret keys are erased or the device may be forced into lockdown mode.

PQC’s physical side

As PQC becomes more widely adopted, the frequency and complexity of physical hardware attacks are expected to rise. Whilst the latest cryptographic algorithms may resist quantum computers, hackers will continue to exploit physical vulnerabilities because without robust protection these are often easier than breaking the underlying mathematics.

This looks set to drive demand for analog anti-tamper IP that can detect clock, voltage, temperature, EMFI and LFI attacks, trigger responses such as key zeroization or secure reset if required, complement digital root of trust (RoT) solutions, and strengthen compliance with hardware security requirements in sectors such as automotive, industrial, financial and government.

Analog IP solutions offer a continuous line of defense, including clock, voltage, temperature and EMFI sensors, which complement digital RoT systems. As physical attack routes evolve, adding optical and LFI detection to the physical security envelope will become the benchmark for securing next-generation system-on-chips (SoCs).

While PQC addresses the security of cryptographic algorithms, analog anti-tamper IP protects the physical implementation of those algorithms. As organizations invest in PQC, safeguarding the hardware root of trust and stopping physical attacks becomes an even more critical part of a comprehensive security strategy.

Chris Morrison is VP of product marketing at Agile Analog.

Related Content

• Looming Quantum Threat as PQC Market Expands
• Post-quantum cryptography (PQC) knocks on MCU doors
• Post-Quantum Cryptography Incorporated into SoCs via eFPGA
• The need for post-quantum cryptography in the quantum decade
• Test and Measurement Strategies for QKD, PQC and Hybrid Systems

The post Why analog anti-tamper security IP is crucial in the PQC era appeared first on EDN.

Expensive shortwave radios include beat frequency oscillators, so why not also add one to an inexpensive radio version?

Broadcast shortwave (SW) radio use may be declining, but there are still lots of interesting signals to listen to between 1.6 and 30 MHz, such as amateur radio (Reference 1), pirate radio stations (Reference 2), aeronautical weather reports (Reference 3) and long-distance aircraft communications (Reference 4). Unfortunately most of these use Single Side Band (SSB) as opposed to the Amplitude Modulation (AM) used by broadcasters, which cannot be received on cheap domestic SW radios.

Wow the engineering world with your unique design: Design Ideas Submission Guide

AM consists of a radio frequency (RF) carrier wave (in red) which is partially modulated by the information – speech or music – (green), as shown in Figure 1a. The time domain signal in Figure 1a can alternatively be viewed in the frequency domain as in Figure 1b, where the carrier is surrounded by two smaller sidebands containing the information. A diode detector can demodulate this signal. In the time domain, the approach can be regarded as rectification with a low pass filter. In the frequency domain, the non-linear action of the diode mixes the carrier with the sidebands, therefore down-converting it back to an audio signal.

Figure 1 This sequence of images shows AM in the time  (a) and frequency domains (b), along with SSB in the frequency domain (c).

SSB lacks this carrier, with only one sideband as shown in Figure 1c. To demodulate SSB, an external carrier signal must be added; the resulting signal can then be demodulated with a diode detector like AM. This additional carrier is sometimes referred to as a Carrier Insertion Oscillator (CIO) or Beat Frequency Oscillator (BFO). Expensive SW radios include a BFO, so why not try and add one to a cheap one?

SSB demodulation

Many SW radios for SSB published in hobbyist magazines apply a high amplitude BFO signal to the input of the diode detector alongside the intermediate frequency (IF) signal, as shown in Figure 2a. The high BFO amplitude tends to overload any Automatic Gain Control (AGC) loop. Hence, in this type of receiver the AGC loop is disabled and the radio’s dynamic range is alternatively managed by manual RF and/or IF gain control.

Figure 2 These block diagrams show shortwave radios with BFO (a) and low-level BFO injection (b).

Adding a BFO to an existing radio in the way shown in Figure 2a would involve substantial modification to the radio to disable the AGC loop and integrate a manual RF gain control, if not already present. A second disadvantage with this technique is that because the IF signal has a large amplitude at the input of the detector, it can leak into the BFO and modulate it, therefore introducing distortion to the point of making the signal unintelligible.

The Eddystone EB35 radio from the late 1960s (Reference 5) overcame the leakage issue by injecting a low-amplitude BFO signal into the input of the IF amplifier chain. It does however still disable the AGC and instead rely on manual RF gain control.

Proposed here is a method of injecting the BFO at low amplitude into the input of the IF amplifier chain and controlling its level so as to best match the received signal when the existing AGC loop is operational, as shown in Figure 2b. The BFO with level control can be built into an external box with minimum modification, hence is easy to incorporate and then later remove from a valuable vintage radio receiver.

External BFO

The schematic of the BFO is shown in Figure 3. The oscillator is a Hartley type where a tap on transformer T1 provides the feedback. This is generally at 25% of the winding. T1 is a recycled IF transformer from an old transistor radio. Most low-cost radios like those shown in Figure 2 use an IF frequency between 455 and 470 kHz.

Figure 3 In this BFO schematic, VR1 is the pitch and VR2 is the level.

TR1 is a BC548 transistor, which although not known for its high frequency performance has sufficient gain at 455 kHz. The IF transformer includes a capacitor to set its operating frequency. To operate effectively as a BFO, the frequency needs are varied over a small range of a few kHz. This is achieved with a varactor diode D1, which here is half of a 1 A bridge rectifier (Reference 6) and controlled by VR1.

Level control is provided by VR2. The level of the carrier is reduced further by selecting a low values for C5 of 5pF. The values of C2 and C3 are not very critical, but past experience has shown that their optimum values are:

where fR is the operating frequency in MHz and C2 = C3 in pF. This is based on the optimum capacitor values for a Colpitts oscillator (Reference 7). The BFO is designed to run off 5V, so a voltage regulator (Reg1) is included. A 78L05 could be used, but in this application the radio used—a Realistic Patrolman SW60—had a 6 V supply, so a low-drop out K5050 regulator was used instead.

A photograph of the BFO built in a small plastic box and stuck to the back of the SW60 is shown in Figure 4. An additional hole is drilled in the box so that the core of T1 can be tuned. Although the SW60 is based on NPN transistors, it is a positive ground design, so the screen of the coaxial cable is connected to the input of Reg1 and the purple wire is ground. Another version was built for use with a WWII-era PCR radio where the cables passed through an unused headphone jack socket—requiring no modification to the case.

Figure 4 In this photograph of the BFO attached to the SW60, the top control is BFO level and off, the bottom is BFO pitch, and T1 is the metal can on the right.

Operation

When first used, the radio should be tuned between stations so only background white noise in heard. The BFO level control should be set to maximum. Doing this may cause a change in the sound of the noise. It is likely that the BFO will be operating outside of the IF bandwidth and will need to be tuning in.

Set the pitch control to approximately midpoint and with a trimmer tool, adjust the core of T1. As the BFO is tuned across the IF bandwidth, the general tone of the noise will drop and then increase on the other side. Generally, it should be adjusted so that the tone is at its lowest. Turning the pitch control should now cause the tone of the noise to rise on either side. At this point the level control can be backed off as it is probably driving the AGC loop. The optimum level control point is when the background noise is at maximum volume.

Tuning the radio to somewhere in the 7-7.3 MHz range in the late afternoon and evening should pull in stations in the 40-meter amateur band. If the signal sounds distorted, trying increasing the BFO level and the fidelity should improve. Adjusting the pitch control will of course affect the pitch of the received signal. When these two controls are correctly adjusted, the received signal fidelity is very good.

References

1. Amateur Radio bands: https://en.wikipedia.org/wiki/Amateur_radio_frequency_allocations
2. Shortwave Pirate Radio Stations: https://www.hfunderground.com/wiki/List_of_Pirate_Radio_Frequencies
3. VOLMET frequencies: https://dxinfocentre.com/volmet.htm
4. Aeronautical HF Radio: https://swling.com/blog/2015/09/aeronautical-hf-radio-map/
5. Eddystone EC10 Receiver: https://eddystoneusergroup.org.uk/Manuals/Eddystone%20EC10%20Manual.pdf
6. Rectifier diodes as varicaps (varactors): https://www.hanssummers.com/varicap/varicapdiode.html
7. NE602 Application note: https://www.scribd.com/document/46152488/Single-Chip-Frequency-Converter

Gavin Watkins is the founder of GapRF, a producer of online EDA tools focusing on the RF supply chain. When not doing that, he is happiest noodling around in his lab, working on audio electronics and RF projects, and restoring vintage equipment.

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The post Add-on beat frequency oscillator (BFO) for shortwave radio appeared first on EDN.

AI infrastructure is moving from server-scale acceleration to multi-rack supernodes that must behave like a single, highly available computer. Distributed optical circuit switching offers a practical way to extend scale-up fabrics with lower latency, lower power, flexible topology control, and limited disruption to existing data center architecture.

AI data centers are entering a phase where the hardest problem is not simply building a faster accelerator. It’s keeping thousands of accelerators fed, synchronized, and available as one machine. Training frontier models, serving long-context inference, and running agentic workloads all create a similar demand: more devices must communicate over longer distances without allowing the network to dominate cost, latency, power, or reliability.

That changes the definition of scale-up. It’s no longer only the set of links inside a server or rack. Increasingly, scale-up must span multiple racks while preserving the low-latency behavior programmers expect from a tightly coupled system.

Nvidia has framed the issue in similar terms, noting that as AI factories reach “extreme scale,” networking infrastructure “must be reinvented to keep pace.” The company’s recent silicon photonics announcements focus on exactly the metrics now becoming critical in AI infrastructure: power efficiency, signal integrity, resilience, and deployment speed.

That emphasis reflects a broader industry shift. The bottleneck is no longer just whether a link can move bits from one endpoint to another. It’s whether the entire fabric can support large, tightly synchronized accelerator domains while reducing power, limiting failure points, and remaining practical to deploy and service.

Copper has been the default for scale-up because it’s familiar, low latency, and economical at short reach, but physics is becoming less forgiving as per-lane data rates rise. Longer copper paths increase insertion loss and signal-integrity burden; thicker wires help the signal but work against density, airflow, and manufacturability.

Rack-scale cable trays become difficult to assemble and service, and a failure may require replacing large mechanical units rather than a small module. Retimers, equalization, and more complex board design can extend the life of copper, but they do not remove the underlying reach-density-power tradeoff.

Traditional pluggable optics solve part of this problem. They move data farther with less distance penalty than copper and are widely deployed in scale-out networks. But a scale-up fabric is different from a scale-out Ethernet fabric. Scale-up traffic often has stricter latency, synchronization, and collective-communication requirements, and in emerging architectures may carry memory-semantic traffic rather than ordinary packetized network traffic.

In that environment, the raw specifications of an optical link alone are not sufficient. The fabric also needs deterministic paths, fast reconfiguration, high serviceability, and smaller, more containable failure domains.

Figure 1 Next-generation scale-up and scale-out solutions extend the limits of traditional electrical interconnect and pluggable optical modules. Source: Lightelligence

Co-packaged optics (CPO) is an important long-term solution, but it’s not a simple drop-in replacement for today’s data center designs. Bringing optical engines into or near the package changes the thermal, packaging, manufacturing, serviceability, and qualification model. Recent industry discussions around CPO focus heavily on these operational issues: how to manufacture high-yield optical assemblies, make optical interfaces field-serviceable, and manage light sources and redundancy at scale.

Nvidia’s recent Spectrum-X Ethernet Photonics announcements also show where early CPO commercialization is gaining traction: scale-out and scale-across AI-factory networking. Scale-up CPO will follow, but it asks a different question: how do we preserve the behavior of a tightly coupled compute domain while changing the physical medium underneath it?

This is where distributed optical circuit switching, or dOCS, becomes important. Rather than concentrating the switching function in precious rack space, a dOCS architecture distributes compact silicon-photonic switching elements close to servers, GPU trays, or XPU clusters. This improves compute density by eliminating the switch chassis.

The goal is to keep data in the optical domain from port to port through the switch path, reducing unnecessary optical-electrical-optical conversions and avoiding the power and cost burden of very large centralized electrical switch ASICs. In practical terms, dOCS treats the scale-up network less like a fixed cable plant and more like a configurable optical fabric.

Figure 2 A distributed optical circuit switch (dOCS) integrates the optical interconnect and switching functions into one compact module. Source: Lightelligence

The distinction matters. A centralized switch can become expensive, power-intensive, and operationally painful as scale-up domains grow. It can also create a large failure domain. A distributed optical switch breaks the switching function into smaller modules, shrinking the blast radius of any one failure and enabling more granular service.

In one described implementation, the dOCS module integrates optical interconnect and optical circuit-switching functions in a compact module built around silicon photonics, controller, driver, and receiver circuitry. The architecture is intended to support millisecond-level failover, including substitution of a hot-standby GPU when a device fails.

For AI workloads, the value of that reconfigurability is not only resilience, it’s also topology control. Different phases of training and inference stress the fabric differently.

Dense all-reduce operations, mixture-of-experts routing, retrieval, key value (KV)-cache movement, and pipeline-parallel execution do not all benefit from the same topology. A circuit-switched optical layer can expose topologies such as ring, mesh, or dragonfly and allow the cluster manager to adjust the fabric according to specific workload-parallelism requirements.

Recent dOCS-based supernode work has described real-time topology reconfiguration and elastic expansion beyond 500 GPUs in a single logical domain. The broader architectural point is more important than the exact number: the network should become a schedulable resource, not a static constraint.

This also helps explain why dOCS is especially relevant to certain architectures. A supernode is not just a cluster with a marketing label. It is a tightly interconnected group of GPUs or other accelerators that attempts to behave like one large compute unit. In that context, effective model FLOPs utilization depends on how much time accelerators spend computing rather than waiting.

Optical scale-up links can extend reach across racks, while circuit switching can create predictable paths for high-volume collective traffic. The result is not simply more bandwidth on a datasheet; it’s a path to higher sustained utilization.

The same argument applies to memory. AI systems are increasingly constrained by memory capacity, memory bandwidth, and the location of memory relative to compute. High-bandwidth memory (HBM) on the accelerator remains essential, but it’s finite and expensive. Long-context inference and agentic workloads amplify the pressure by generating large KV caches and preserving more state across interactions.

CXL is important because it provides cache-coherent connectivity for processors, memory expansion, and accelerators, enabling resource sharing with lower software complexity. But coherent memory fabrics still need physical reach. Optical PCIe/CXL links and reconfigurable optical switching can help move memory from a stranded local resource toward a pooled resource available across boards, servers, and racks.

The practical advantage of dOCS is that it creates an intermediate deployment path. Data center operators do not need to redesign every server, change every protocol, or wait for full CPO maturity before gaining optical reach and switching flexibility in the scale-up domain. A dOCS-based fabric can be designed to remain protocol agnostic at the physical layer, supporting multiple higher-level fabrics while changing the transmission medium and switching mechanism underneath.

That matters because AI data centers are heterogeneous. They include GPUs, CPUs, XPUs, switches, storage, memory expansion devices, and management controllers sourced from multiple vendors and refreshed on different schedules.

Figure 3 As shown in this example, the dOCS architecture offers a practical advantage by creating an intermediate deployment path. Source: Lightelligence

A sensible roadmap is therefore not copper versus CPO, or pluggables versus CPO. It’s a staged migration. Linear pluggable optics can address immediate reach and power issues with limited architectural change. Distributed optical circuit switching can add fabric-level reconfiguration, availability, and scale-up reach.

Near-packaged optics can shorten electrical traces and improve density. CPO optics can eventually move optical I/O directly beside GPUs or switch ASICs for the highest bandwidth density and lowest electrical loss. Each step moves optics closer to the compute, but each step should also preserve serviceability and operational practicality.

The AI infrastructure industry is learning a familiar lesson from earlier computing transitions: the winning technology is rarely the one with the most elegant device physics alone. It’s the one that fits into systems, software, manufacturing, and operations at the right time.

The dOCS architecture fits that requirement because it attacks a real bottleneck now. It extends scale-up beyond the practical limits of copper, avoids inefficiencies of repeated electrical conversion, supports flexible accelerator-fabric topologies, and improves system uptime by localizing failures and rapidly rerouting traffic or switching to standby resources when hardware fails.

The future data center will almost certainly use several optical technologies at once: pluggable optics, linear drive optics, near-packaged optics, CPO, optical I/O chiplets, CXL-enabled memory fabrics, and optical circuit switches. The case for dOCS is that it gives operators a rapid-deploy scale-up option while the rest of the optical roadmap matures.

For AI infrastructure, that may be the most important kind of innovation: not a clean-sheet replacement for the data center, but a way to make the next supernode larger, more efficient, more available, and easier to deploy than the last one.

Maurice (Mo) Steinman is senior VP and U.S. GM at Lightelligence. He has enjoyed a 40-year career in the semiconductor industry, working for such companies as Digital, Compaq, HP, Intel and AMD, where he held the title of Senior Fellow before joining Lightelligence. Steinman has expertise in SoC architecture, SoC interconnect, memory subsystems, and energy management.

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