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Add-on features are all the rage in electronic products. But are they actually handy or just embody bells and whistles? What’s their hardware and software cost? And more importantly, do they serve an actual value or merely add to the user-experience clutter? Bill Schweber looks at this user interface mystery and finds some answers.

Read the full story at EDN’s sister publication, Planet Analog.

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The post Add-on features in electronic products: The good part appeared first on EDN.

A new software combines connectivity, scalability and data-driven artificial intelligence (AI) capabilities to push the boundaries of the IC verification process and make chip design teams more productive. Questa One aims to address the verification productivity gap for large, complex designs spanning IP to IC to systems.

The steadily increasing complexity of 3DICs, chiplet-based designs, and software-defined architectures is further compounded by a critical talent shortage and growing demands for enhanced security and lower power consumption. “Questa One uses new technical advances to deliver the fastest functional, fault, and formal verification engines available,” said Abhi Kolpekwar, VP and GM of digital verification technologies at Siemens EDA.

Figure 1 Questa One strives to redefine IC verification from a reactive process into an intelligent, self-optimizing system. Source: Siemens EDA

A recent Wilson Research Group survey suggests that one in seven IC projects achieves first-time silicon success. Chris Giles, director of product management for static and formal at Siemens EDA, calls this a jaw-dropping and staggering drop. “Our approach is to enable engineers to do more with less, with not just faster engines but also faster engineers with fewer workloads,” he said.

Figure 2 Here is a view of the decline in first-time silicon success and the increase in FPGA bugs. Source: Wilson Research Group

Giles spoke with EDN to explain the technology fundamentals of this new verification tool.

Quest One’s three tenets

Giles said that Questa One has been developed around three core principles:

1. Scalable verification: It allows engineers to speed verification closure. Giles noted that the semiconductor industry is struggling to tackle large designs. “That’s why we see a decline in first-time silicon success,” he added. “Chip designs are getting so large that it’s difficult to verify them in one piece.” Questa One verification aims to allow engineers to work on large chip designs.
2. Data-driven verification: It leverages data for AI-powered analytics to bring new insights and to improve verification productivity. “It collects datasets that allow verification tools to either make recommendations or directly decide what to do next and do it productively,” said Giles.
3. Connected verification: Questa One connects EDA tools and verification IP to form a cohesive ecosystem for robust verification, validation, and test operations. In other words, it uses a broad set of technologies and analyses to provide insights and raw verification power.

Figure 3: Questa One offerings are shown with three main value propositions summed up at the bottom. Source: Siemens EDA

Quest One’s four components

Questa One has the following focus areas:

1. Questa One simulator: This simulator engine is built from the ground up. It performs functional and fault simulation for RTL, GLS, and DFT applications with parallel processing and profiling add-ons.
2. Questa One SFV: The stimulus-free verification (SFV) solution delivers user productivity through synergistic combinations of static and formal analyses, AI, automation, and parallelization. “The current static and formal technology is very fragmented, challenging high productivity,” Giles said. “SFV integrates static and formal analyses, AI, and parallelization to address this challenge.”
3. Questa One verification IQ: It’s a coverage solution that utilizes generative, analytic, and prescriptive AI to drive verification closure faster with fewer workloads. “It features an intelligent interface that provides insight into the entire verification ecosystem,” Giles added.
4. Questa One Avery VIP: The solution, based on Avery’s high-quality VIP and high-coverage compliance test suites (CTS), offers protocol-aware debug and coverage analytics to help increase productivity. It supports 3DIC and chiplet verification from IP to system-on-chip (SoC) design.

Figure 4 Four main components of Questa One include a simulator, a static and formal verification solution, a verification intelligence coverage analysis solution, and an Avery identifier. Siemens EDA

Questa One in works

Semiconductor IP supplier Rambus acknowledged an improved verification experience in managing data center workloads like generative AI while implementing IPs for PCIe, CXL, and HBM interfaces. Rambus particularly mentioned Questa One’s simulation, static and formal analysis, and verification IP technologies.

Then there is Arm, which used Questa One simulator to reduce regression time in its latest AArch64 architecture. “The Questa One verification solution has improved our verification productivity across traditional on-premises and cloud deployments,” said Karima Dridi, head of productivity engineering at Arm.

MediaTek, another early user of Questa One, has utilized its formal verification and simulation technologies. “Questa One Property Assist utilizes generative AI to save us weeks of engineering time, and Questa One Regression Navigator predicts which simulation tests are most likely to fail, runs them first, and saves days of regression and debugging time,” said Chienlin Huang, senior technical manager of Connectivity Technology Department at MediaTek.

Questa One claims to yield step-function gains in smart regression, smart analysis, smart engine, and smart debug domains. Design testimonials from Arm, MediaTek, and Rambus are a good start.

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The post IC verification tool addresses design complexity, productivity gap appeared first on EDN.

In April 2012, EDN published a circuit by John Fattaruso that lets you quickly measure the drain-source saturation current and the pinch-off voltage of both an N-JFET and a P-JFET. The pinch-off voltage (Vp) is measured by inserting a very large resistance between the source and the ground. The drain-source saturation current (IDSS) is measured by inserting a small resistance between the source and the ground. Then, the voltage across this resistor is measured, and both Vp and IDSS can be calculated using Ohm’s law. 

There is a catch with this circuit: Since IDSS is measured across a non-zero resistor, there is a deviation from the real IDSS, see Figure 1. This circuit does not really measure point A, but actually measures point B slightly before this. For JFETs with lower Vp voltages and/or higher IDSS currents, there can be a deviation between the measured and real IDSS value of 5% or more.

Figure 1 A standard N-JFET drain-source current vs gate-source voltage curve.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Circuit idea

The accuracy of the circuit can be drastically increased by making a couple of minor changes. Figure 2 shows the basic circuit. 

Figure 2 A basic, improved circuit for the JFET IDSS and Vp measurement.

An astute reader will immediately see the two circuits’ similarities and differences. Switch 1 is, again, used to select between N-channel JFETs and their less common sibling: P-channel JFETs.

Switch 2 is used to select between Vp and IDSS measurement. In the position as drawn, IDSS is measured. In this position, A1 is set up as a transimpedance amplifier. 

With the op-amp’s non-inverting input connected to ground, A1 will keep the inverting input, and hence the source, to ground as well. This guarantees that the true IDSS is measured. Resistor R3 then converts the current to a voltage that can be measured at the output of A1. 

When Switch 2 is flipped to the other position, A1 is set up as a simple voltage follower. The pinch-off voltage that develops across R1 is then buffered and available at the output of A1.

Full implementation

Now that we have seen the basic circuit, we can look at a full implementation (Figure 3). Resistor R2 limits the current that can flow in case a JFET is inserted incorrectly. In pinch-off measurement mode, the impedances around Q1, R1 and A1 are all pretty high. To limit the influence of noise, capacitor C1 is added. It is best to keep these wires short and/or to build the circuit in a shielded box. 

Figure 3 First implementation of the practical circuit used to measure  IDSS and Vp.

Most operational amplifiers can only source or sink a small amount of current. The drain-source saturation current can easily be in the tens of milliamperes. To boost the current output capabilities of A1, a complementary bipolar transistor output stage is added. Please note that the output is not short-circuit proof. If preferred, a simple 1 kΩ to 10 kΩ resistor can be added in series with the output. 

With the current resistor values in the circuit, a pinch-off voltage of ±10 V can be measured and a saturation current of ~ ±100 mA. 

Although there are JFETs with large saturation currents (think J109 with IDSS > 40 mA and J108 with IDSS > 80 mA!), this is simply not needed for most JFETs. So, a variation on this circuit was developed. The pinch-off voltage remained the same, but the saturation current was returned to 25 mA, covering almost all JFET types. A further requirement was that the output voltage range for both measurements needed to be the same: 0 … ±5 V. This was so that a moving coil meter readout could be used with a single range.

See Figure 4 for the implementation.

Figure 4 A circuit with the tailored measurement range that is suited for most JFETs.

Read-out

A read-out needs to be added to make this a complete measurement instrument. Since I have a large stock of moving coil meters, I decided to use one of these for the read-out. To some, they may look antiquated, but they are a joy to use and a marvel of mechanical engineering! The output can be positive or negative depending on whether you are measuring Vp or IDSS, and whether an N-type JFET or a P-type JFET is being tested. So, this is something that needs to be dealt with. Also, it would be nice if there were some kind of polarity indication. See Figure 5 for the read-out circuit.

Figure 5 The readout circuit with sensitive polarity indication. 

The 1-mA moving coil meter is included in the feedback loop around the op-amp. D3-D6 form a common rectifier bridge so that, independent of the polarity of the input voltage, the meter is always fed a positive current. 

Transistors Q1 and Q2 serve as a polarity indication. Positive voltages will turn on Q1 and LED D9. LED D10 will indicate negative voltages. 

D7,8 are not needed for the rectification. Because of these diodes, the A1 output voltage must be above/below ±1.8 V before any significant current will flow through the meter. This, in turn, guarantees that transistors Q1 and Q2 will already turn on at very low input voltages, giving a good polarity indication across the whole input range.

Test socket

Over the years, manufacturers have created JFETs with almost every possible pin-out, so making a single universal test socket is not so trivial. With three leads, there are 3! = 6 possible combinations as shown in Table 1.

#	Pin-out
1	G	D	S
2	G	S	D
3	D	G	S
4	D	S	G
5	S	G	D
6	S	D	G

Table 1 The six possible pin-out combinations that can be used for an off-the-shelf JFET.

Of course, a JFET with a pin-out of S-D-G (#6) can be tested in a socket with pin-out G-D-S (#1), simply by inserting it reverse in the socket. This effectively eliminates half of the possible combinations. So we are left with the following three, as shown in Table 2. 

#	Pin-out
1	G	D	S
2	G	S	D
3	D	G	S
4	= #2 reverse
5	= #3 reverse
6	= #1 reverse

Table 2 A reduction in the number of pin-out combinations by simply reversing the component within the test socket.

After a bit of doodling, we can create a single five-pin test socket that can accommodate every possible JFET pin-out as shown in Table 3.

#	Pin-out
	D	S	G	D	S

Table 3 A singular 5-pin test socket to accommodate all possible JFET pin-outs. 

There are two different variants possible; this is left as an exercise to the reader. The same logic can be applied to create universal test sockets for bipolar transistors, of course.

Figure 6 The final PCB implementation of the practical JFET circuit used to measure IDSS and Vp, showing the test socket. 

In closing

Thanks to John Fattaruso for his excellent design idea, which sprouted this idea! We all stand on the shoulders of the giants that came before us.

Cor van Rij blew his first fuse at 10 under the close supervision of his father, who promptly forbade him from ever working on the house mains again. He built his first regenerative receiver at the age of 12, and as a boy, his bedroom was decorated with all sorts of antennas, and a huge collection of disassembled radios took up every horizontal surface. He studied electronics and graduated cum laude.

He worked as a data design engineer and engineering manager in the telecom industry. And has worked for almost 20 years as a principal electrical design engineer, specializing in analog and RF electronics and embedded firmware. Every day is a new discovery!

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The post A simple circuit to let you characterize JFETs more accurately appeared first on EDN.

Earlier this year, within the concluding post of a multi-part series that explored a not-as-advertised portable power generator, its already-broken-on-delivery bundled solar panel:

and the second solar panel I’d also bought for the setup (and subsequently also returned):

I discussed the primary options (serial and parallel) for merging the outputs of multiple solar panels, the respective strengths and shortcomings of the two approaches and, in the parallel-connection case, the extra circuitry that (unless already built into the panels themselves) would likely be necessary to prevent reverse-current hotspots in situations where one or both panels were in dim light-to-darkness.

Since both panels I’d bought, plus the portable power generator they were intended to “feed”, were all based on Anderson Powerpole PP15-45 connectors:

the parallel combiner I’d also bought from (and subsequently also returned to) Amazon had Anderson Powerpole connectors on both input ends, plus the output:

What if anything was inside it beyond just two pairs of input wire, with like-polarity cables soldered together and to an output strand, all within an intermediary watertight compartment? And if more, why? Here’s what I wrote back then:

Assume first that the combiner cable simply merges the panels’ respective positive and negative feeds, with no added intermediary electronics between them and the electrons’ intended destination. What happens, first, if all the parallel-connected panels are in shade (or to my earlier “dark” wording surrogate, it’s nighttime)? If the generator is already charged up, its battery pack’s voltage potential will be higher than that of the panels themselves, resulting in possible reverse current flow from the generator to the panels. Further, what happens if there’s an illumination discrepancy between the panels? Here again there’ll be a voltage potential differential, this time between them. And so, in this case, even if they’re still charging up the generator’s batteries as intended, there’ll also be charging-rate-inefficient (not to mention potentially damaging; keep reading) current flow from one panel to the other.

The result, described in this crowded diagram from the same combiner-cable listing on Amazon:

is what’s commonly referred to as a “hotspot” on one or all panels. Whether or not it negatively impacts panel operating lifetime is, judging from the online discussions I’ve auditioned, a topic of no shortage of debate, although I suspect that at least some folks who are skeptical are also naïve…which leads to my next point: how do you prevent (or at least minimize) reverse current flow back to one or both panels? With high power-tolerant diodes, I’ll postulate.

Those folks who think you can direct-connect multiple panels in parallel with nothing but wire? What I suspect they don’t realize is that there are probably reverse current-suppressing diodes already in the panels, minimally one per but often also multiple (since each panel, particularly for large-area models, is comprised of multiple sub-panels stitched together within the common frame). The perhaps-already-obvious downside of this approach is that there’s a forward-bias voltage drop across each diode, which runs counter to the aspiration of pushing as much charge power as possible to the destination battery pack…

If you look closely at the earlier “crowded diagram” you can see a blurry image of what the combiner cable’s circuitry supposedly looks like inside:

And I closed with this:

Prior to starting this writeup, I returned the original combiner cable I bought, since due to my in-parallel return of the Duracell and Energizer devices, I no longer needed the cable, either. But I’ve just re-bought one, to satisfy my own “what’s inside” research-induced curiosity, which I’ll share with you in a teardown to come.

That time is now. Since I strongly suspected my teardown would be destructive, I picked up the cheapest combiner I could find on Amazon. This one, to be precise, from the same supplier I’d chosen before (therefore presumably with the same “guts” in between the output and inputs):

In this particular case, the combiner was intended for use with Jackery portable power stations (historically based on, as I’ve noted before, either a DC7909 or DC8020 connector depending on the model), so it included native-plus-adapter support for both plug standards. Today’s patient was “Amazon Warehouse”-sourced, therefore $3.20 cheaper than the $15.99 list price. And again, I assumed it wouldn’t live past my dissection of it, anyway. Speaking of which, here it is:

Now freed, along with its associated output adapter, from clear-plastic captivity and as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

Input(s) end:

Middle thirds, top and bottom:

And output end, both “bare” and adapter-augmented:

Back to the middle third for a side view. Look, it’s an ultrasonic welded seam all the way around!

I’m glad to see that at least some of you enjoyed my attempted (successfully, so, albeit not cleanly) breach of an ultrasonic-welded wall wart case at the beginning of last month.

To the Hackaday crowd: No, it wasn’t intended as an April Fools’ joke. I had no idea what day Aalyia was going to publish it, although in retrospect, excellent choice, my esteemed colleague!

This time I decided to downscale my “implements of destruction” somewhat, downgrading from a 2.5 lb. sledge to a more modest ball-peen hammer,  and to a more diminutive but no less sharp (unfortunately, this time absent a “hammer end”) paint scraper:

I’d also like to introduce you to my equally diminutive, recently acquired vise, the surrogate for the Black & Decker Workmate I used last time. Isn’t it dainty (albeit surprisingly sturdy)?

It took a few more whacks than I would have preferred (or maybe I was just being cautious after last time’s results), but eventually I got inside, and cleanly so this time, if I do say so myself:

The other side…not so much, although still not bad (and yes, to several readers’ suggestions, I also own a hacksaw, which I’ve used before in similar situations; I was just angling for variety):

All that was left was a flat-head screwdriver acting as a lever arm to pry the two halves apart:

And we’re in:

This initial perspective is of the bottom of the device:

Note the thick PCB traces and their routings. Keep this in mind when we flip it to the other side:

Speaking of which, let’s next remove those two screws:

And the PCB’s now free:

Here’s the bottom side of the PCB again, now absent the case half that previously surrounded it:

And here’s the now-exposed top half, blurrily glimpsed earlier in one of the “stock photos”, that we all really care about:

Zooming in a bit:

And now even closer, courtesy of my crude, inexpensive loupe-as-supplemental-lens setup:

Those are indeed “high power-tolerant diodes”! Specifically, they’re multi-sourced (does anyone there know if the first line “LGE” mark refers to LG Electronics?) MBRD1045 Schottky devices, variously referred to both “diodes” and “rectifiers”, the latter because their Schottky-derived low forward voltage loss makes them amenable to use in (among other things) full-wave rectifier circuits like the one seen in last month’s “wall wart”. In actuality, the two terms refer to the same thing, as a discussion forum thread I came across in my research made clear. This memorable phrase in one of the thread’s posts cracked me up (no, I won’t reveal if I agree!):

EEs are not known for consistency and precise language.

Admittedly, a circuit diagram I found in several suppliers’ datasheets gave me initial pause:

Two anode pins? Were the same-polarity outputs of both solar cells combined ahead of the diode? And if so, why were there four diodes in the design, instead of just two?

Eventually, even before doing the math and calculating that the spec’d 10 A of peak per-diode forward current would barely-at-best enable free flow of even one solar panel’s electron output (thereby, I suspect, being the primary cause, vs the slight forward voltage drop across the diodes, of my previously mentioned inefficiency results noted by some combiner users), far from two panels’ aggregate load, I’d also realized that such a setup would only achieve one of the two desired combiner objectives. It would indeed prevent this scenario:

What happens, first, if all the parallel-connected panels are in shade (or to my earlier “dark” wording surrogate, it’s nighttime)? If the generator is already charged up, its battery pack’s voltage potential will be higher than that of the panels themselves, resulting in possible reverse current flow from the generator to the panels.

But it would do nothing to current flow-correct this other key potential “hotspot” scenario:

What happens if there’s an illumination discrepancy between the panels? Here again there’ll be a voltage potential differential, this time between them. And so, in this case, even if they’re still charging up the generator’s batteries as intended, there’ll also be charging-rate-inefficient (not to mention potentially damaging; keep reading) current flow from one panel to the other.

So, four diodes total it is, two for each panel (one for the output and the other for the return), with both anode connections of each diode leveraged for a common input, and the two panels’ respective positive and negative pairs combined after the multi-diode structure. This “digital guy” may yet evolve embryonic-at-least analog and power electronics expertise…nah. C’mon let’s get real. Delusions are inexhaustible, don’cha know. Regardless, did I get the analysis right, or have I missed something obvious? Sound off with your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post Cutting into a multi-solar panel parallel combiner appeared first on EDN.

Bluetooth channel sounding—a new protocol stack designed to enable secure and precise distance measurement between two Bluetooth Low Energy (LE) devices—is propelling Bluetooth technology into a new era of location awareness. It offers true distance awareness while enhancing Bluetooth devices’ ranging capabilities.

Bluetooth channel sounding’s use spans from helping locate devices such as phones or tablets to digital security enhancements like geofencing. It can also be used in smart locks, pet trackers, vehicle keyless entry, and access control applications.

Hardware and software solutions are starting to emerge to fulfill the potential of Bluetooth channel sounding and provide sub-meter accuracy for Bluetooth-empowered devices. These solutions include reference boards, development kits, and software stacks.

Below are two design case studies demonstrating the potential of Bluetooth channel sounding technology.

Radio board and antenna hardware

Silicon Labs’ xG24 radio board—designed to work with Pro Kit—aims to help developers create and prototype products using Bluetooth channel sounding for precise distance estimation. Pro Kit includes a BRD4198A EFR32xG24 2.4 GHz +10-dBm radio board, a dipole antenna, and reference designs. It works with either a coprocessor with an external MCU or a wireless system-on-chip (SoC) with an integrated MCU.

Another xG24 Dev Kit features a dual-antenna PCB design and a channel sounding visualizer tool to allow developers to view distance measurements in real time. Single-antenna hardware offered in the Pro Kit has fewer antenna paths and limited multipath information, which makes it more suitable for basic Bluetooth channel sounding applications.

Figure 1 USB or coin cell powered development platform with a dual-antenna design and up to +10 dBm output power. Source: Silicon Labs

On the other hand, dual-antenna hardware offers higher accuracy, better spatial performance, and enhanced multipath resolution, making it suitable for advanced applications such as key fobs and tags that demand precise distance estimation (Figure 1). Its antenna diversity also bolsters signal quality and robustness.

Software stack

Bluetooth channel sounding technology uses phase-based ranging (PBR), round trip time (RTT), or both to accurately measure the distance between two Bluetooth LE-connected devices. PBR utilizes the principle of phase rotation in RF signals to determine precise distance between two devices. On the other hand, RTT, a communication channel, refers to the duration a signal takes to travel from the initiator to the reflector and back again.

The above solution from Silicon Labs uses both, employing RTT to verify and cross-check the PBR measurements. However, Metirionic, a German supplier of wireless ranging and positioning technologies, offers an alternative to both PBR and RTT by leveraging the channel impulse response (CIR) technique for highly accurate and reliable distance estimation.

Figure 2 The channel sound evaluation kit is built around Nordic Semiconductor’s nRF54L15 wireless MCU. Source: Metirionic

Its Bluetooth channel sounding evaluation kit—Metirionic Advanced Ranging Stack (MARS)—is a low-power signal-processing upper-layer software (Figure 2). It can run on Nordic’s nRF54L15 embedded MCU, on an external MCU or processor, or on a host PC to ensure precise, reliable and real-time ranging and location accuracy for industrial, Internet of Things (IoT), real-time location services (RTLS), logistics, and secure access applications.

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The post Two design solutions for Bluetooth channel sounding appeared first on EDN.

We took a family trip with our grandsons to the New York Transit Museum in Brooklyn, NY. Retired subway cars were on display, some of them seemingly not that old while others dated way, way back. Visitors could freely roam in and out. I was in this one car that had been in service in 1903 which meant it predated the advent of electronics. Even the vacuum tube had not yet been invented by then.

I noticed the passenger area’s bare light bulbs and got really close to one (Figure 1). It was rated at 56 watts and 120 volts. A question came to mind as to how did that car use 120-volt light bulbs when the third rail voltage was (and still is) 600 volts DC?

Figure 1 A subway car light bulb up close showing 56-W and 120-V rating.

When we got home, I tried looking up subway car technical data, but when I came to a wiring schematic, I couldn’t read it. The symbols were indecipherable to me. Only then did it dawn on me that five such bulbs connected in series would be operable from 120 x 5 = 600 volts. If any one of the five were to burn out, all five would go dark, but then maintenance would change all five and discard four good bulbs with the one blown out bulb. It sounded wasteful, but it would have been a practical approach.

Is that the actual truth? I don’t know, and there was nobody on hand to ask, even if I had been quick enough of wit to inquire. Also, I just wasn’t smart enough on site to see if the total number of bulbs in the car was a multiple of five. Maybe one day, I can do that.

Another point about those subway bulbs is that they had left-handed threads on their bases, while household bulbs use right-handed threads. This was to discourage light bulb thefts. Stolen bulbs would not fit into light bulb sockets in households, only into the sockets of subway cars.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Antique NYC subway cars appeared first on EDN.

Quantum computers are among today’s most exciting emerging technologies, but their design, testing, and manufacturing require unparalleled care to avoid damaging their components. Semiconductors are sensitive, so they require production environments with minimal contamination risks. Cleanrooms are the industry-standard solution, but even these facilities must reach higher standards for quantum computer development.

While a cleanroom overhaul is inherently expensive and disruptive, these costs may be minimal compared to the potential of quantum technology. A quantum chip from Google was recently able to complete a calculation that would take a classic supercomputer roughly 10 septillion years in just five minutes.

This enormous processing upgrade is thanks to quantum computers’ use of qubits instead of bits. Whereas a bit represents either one or zero, a qubit can be both simultaneously—a seemingly small distinction with a dramatic impact on computing speed and power. However, the superconductors and other components necessary to enable this process are highly sensitive to external disturbances.

Many cutting-edge quantum innovations rely on nanotechnology to achieve the desired performance. Nanomaterials have superior thermal stability and electrical conductivity, making them ideal for high-power applications like quantum computing. They also let electronics engineers fit more components in a confined space to uphold Moore’s law.

As helpful as such technologies are, working with them creates an issue in conventional settings. Given their size, nanomaterials are easily contaminateable and breakable. The intensity of quantum operations exacerbates this sensitivity. Even slight deviations in temperatures, light, and air quality could jeopardize the performance of this highly sophisticated and expensive equipment.

Source: University of Waterloo

A look inside the quantum cleanroom

Quantum cleanrooms are the solution. Engineers must design and build tomorrow’s cutting-edge devices in equally cutting-edge production facilities. Even a conventional cleanroom may be too prone to contamination and environmental variability to support quantum computer development.

The most common cleanroom ratings today are ISO 7 and 8, which allow concentrations of 352,000 and 3.52 million 0.5-micron particles per cubic meter, respectively. These standards also don’t consider any particulate matter below 0.5 microns. While that’s sufficient for traditional semiconductor engineering, quantum cleanrooms must go further. Ratings of ISO 6 and above that do limit sub-0.5-micron particles are necessary.

Cleanrooms for quantum development also need different sanitation methods. Researchers at Berkeley Lab recently found that gentler component cleaning resulted in an 87% increase in induction, making parts more resistant to electrical noise. The method in question used lower temperatures, vacuums, and suspended components to minimize environmental hazards.

Even lighting and ambient temperatures require attention in the quantum cleanroom. Many of these components are photosensitive to blue wavelengths, particularly, so overhead lights should lean more toward the warm end of the spectrum. Quantum circuits also tend to be temperature-sensitive, so these cleanrooms must use gentle refrigeration techniques to keep the area cold.

Quantum electronics engineers must get used to cleanrooms

As quantum technology advances, electronics design engineers may need to adapt to it. The professionals designing, testing, and producing tomorrow’s most advanced electronics must learn to work with their unique production requirements. Getting used to the quantum cleanroom is a crucial step in getting ready for this next generation of computing.

Ellie Gabel is a freelance writer as well as an associate editor at Revolutionized.

 

 

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The post Quantum cleanrooms: Extreme environments for building tomorrow’s computers appeared first on EDN.

With a built-in MEMS resonator, SiTime’s Symphonic SiT30100 mobile clock generator replaces up to four discrete timing devices. It provides accurate clock signals for 5G and GNSS chipsets in mobile and IoT devices such as smartphones, tablets, laptops, and asset trackers.

An integrated temperature sensor feeds precise data to compensation algorithms, helping maintain clock stability. This improves GPS accuracy and reduces lock time, enabling stable performance even in harsh environmental conditions.

The SiT30100 delivers four clock outputs at 76.8 MHz, 38.4 MHz, or 19.2 MHz—configurable from any output—for baseband, RF, and GNSS applications. By eliminating the need for an external resonator, the SiT30100 enables a compact 2.22-mm² single-chip solution. Multiple Output Enable pins allow selective output control to reduce power consumption and minimize EMI. The device also features a temperature-to-digital converter with a single-wire UART interface for system-level temperature compensation, supporting frequency stability down to ±0.5 ppm.

The Symphonic mobile clock generator is available now in a 10-pin chip-scale package.

Symphonic SiT30100 product page

SiTime

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Navitas Semiconductor’s latest GeneSiC MOSFETs exceed AEC-Q101 standards, extending lifetime in automotive and industrial systems. Based on trench-assisted planar technology, they are available in HV-T2Pak top-side cooled packages with 6.45-mm creepage and a CTI above 600 V, supporting IEC-compliant operation up to 1200 V.

Navitas uses the term AEC-Plus to designate parts that exceed the AEC-Q101 reliability tests published by the Automotive Electronics Council (AEC), based on multi-lot stress-test results. This in-house benchmark layers additional stress conditions onto standard AEC-Q101 and JEDEC protocols to better mirror real-world automotive and industrial mission profiles by:

• Incorporating dynamic reverse bias (D-HTRB) and dynamic gate switching (D-HTGB) tests
• Running power- and temperature-cycling for over twice the standard duration
• Extending static high-temperature, high-voltage tests (HTRB, HTGB) to over three times the AEC-Q101 interval
• Qualifying parts to 200 °C TJMAX for improved overload capability

Housed in the 14×18.5-mm HV-T2Pak, the initial portfolio includes 1200-V devices with on-resistance from 18 mΩ to 135 mΩ and 650-V devices ranging from 20 mΩ to 55 mΩ. Lower on-resistance (<15 mΩ) SiC MOSFETs in the same package will follow later in 2025. For more information on GeneSiC MOSFETs, click here.

Navitas Semiconductor 

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Sonair’s 3D ultrasonic sensor uses acoustic detection and ranging (ADAR) to enable 360° obstacle detection up to 5 meters. Each ADAR sensor offers a 180×180° field of view, allowing autonomous mobile robots (AMRs) to safely navigate around people and objects.

The beamforming technology behind ADAR—used in SONAR, RADAR, and medical imaging—has been under development at Norway’s MiNaLab research center for over 20 years and is now adapted for in-air ultrasonic sensing.

ADAR empowers autonomous robots with omnidirectional depth perception, enabling them to ‘hear’ their surroundings in real-time 3D using airborne soundwaves to interpret spatial information. The sensor forms a 5-meter virtual shield that helps people and robots safely share space. It combines wavelength-matched transducers with efficient signal processing for beamforming and object recognition.

The 3D ultrasonic sensors offer a cost-effective alternative to LiDAR and camera-based systems, typically consuming just 5 W and performing more reliably in challenging conditions such as poor lighting, dust, and temperature fluctuations.

Sonair’s ADAR sensor is developed in accordance with ISO 13849-1:2023 PLd / SIL2, with safety certification expected by year-end. The company will unveil the sensor to North American audiences at Automate 2025, with shipments scheduled to begin in July.

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Designed for life science applications, the PLT5 488HB_EP cyan laser diode from ams OSRAM delivers 300 mW of output power at 488 nm. It offers five times the optical output and over 40% higher efficiency than its predecessor—key for DNA sequencing, flow cytometry, and other diagnostic tasks.

According to the company, cyan light effectively stimulates fluorescent dyes in diagnostic devices like flow cytometers and blood testing equipment. The laser diode provides precise wavelength control of ±2 nm, ensuring accurate results in diagnostics, and features a high modulation bandwidth that enhances both signal quality and the speed of analytical processes. Additionally, the PLT5 488HB_EP has low thermal resistance, enabling reliable operation at high temperatures.

While well-suited for life science research, the cyan laser diode also shows potential in other applications. In stage and stadium lighting, for example, it expands the color gamut, producing more vivid visual effects. In fluorescence microscopy, the 488-nanometer wavelength enhances visibility, making it easier to observe fine details that may be difficult to detect with conventional light sources.

PLT5 488HB_EP product page

ams OSRAM 

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CoolSiC JFETs from Infineon provide low conduction losses and robust turn-off behavior for solid-state protection and power distribution. Their strong short-circuit capability, linear-mode thermal stability, and accurate overvoltage control make them well-suited for solid-state circuit breakers, automotive battery disconnect switches, and industrial safety relays.

The bulk-channel optimized JFETs offer RDS(on) values as low as 1.5 mΩ for 750 V devices and 2.3 mΩ for 1200 V variants. Housed in a top-side cooled Q-DPAK, they enable straightforward paralleling and scalable current handling. Consistent switching performance under thermal stress and fault conditions ensures reliable operation in demanding environments.

Engineering samples of the new CoolSiC JFET devices will be available in late 2025, with volume production beginning in 2026. The portfolio will expand to include a range of packages and modules. For more information, click here.

Infineon Technologies 

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Generating analog sawtooth waveforms (linear ramp followed by a quick reset to zero) from digital timing signals is a common function. It usually requires a negative supply as sketched in Figure 1, where Vsaw = -(-V) Tsq/(R1C1).

Figure 1 The usual topology for converting digital square waves to analog sawtooth requires a negative rail.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Negative current through R1 ramps up inverting integrator A1’s output until switch U1 resets it to zero. This topology is simple and works well, but it has the disadvantage of needing a separate negative rail so the integrator can be referenced to ground. Also, the RC network in front of U1, which needs to differentiate the positive edge of the square wave, is kind of messy and less than precise.

Figure 2 shows an alternative sawtooth topology that employs flying capacitor C2 to reset A1. This allows it to be referenced to the positive rail instead of ground, eliminating the need for Figure 1’s negative rail and pulse differentiation. Here’s how it works.

Figure 2 Flying capacitor C2 resets the RRIO ramp to zero volts, allowing it to be referenced to the positive rail instead of ground.

RRIO op-amp A1’s positive input being tied to the VL positive rail allows R1 to act as a current sink between ground and A1’s summing point. This ramps A1’s output positively to:

Vsaw = VL Tsq / (R1C1)

Simultaneously, flying capacitor C2 charges to Vsaw via its connection to A1’s output through U1a. Then, on the positive-going edge of “Square In,” the bottom end of C2 is connected to A1 summing point while its top end switches from ground to VL. This dumps a quantum of charge into C1:

(VL + (Vsaw – VL))C2 = VsawC2

Given that C1 = C2, this resets “Saw Out” to ground as shown in Figure 3.

Figure 3 “Square In” and “Saw Out” voltage waveforms where Vsaw = VL T/(R1C1).

For best accuracy, R1, C1 and C2 should be precision types.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Dual RRIO op amp makes buffered and adjustable triangles and square waves
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• Adjustable triangle/sawtooth wave generator using 555 timer
• Squashed triangles: sines, but with teeth?
• Sawtooth Generator Circuit with 741 IC

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A NOR flash memory serving advanced driver assistant systems (ADAS), zone control, gateway, and digital cockpit designs has achieved ASIL-D functional safety certification from SGS-TÜV, a testing, inspection, analysis, and certification services specialist. External experts from this assurance organization validated Infineon’s SEMPER NOR flash memory for the most stringent safety performance in automotive applications after a detailed analysis of product safety documentation under the ISO 26262:2018 standard.

Infineon also claims that its SEMPER NOR flash is the first memory product developed in compliance with the ISO26262 functional safety standard. “We are proud that the experts at SGS-TÜV have certified our achievements in functional safety and invite our customers to design SEMPER NOR products into their most demanding applications,” said Rainer Hoehler, senior VP and general manager of memory solutions at Infineon.

OEMs and regulators demand the highest levels of safety in automotive designs, from battery management to ADAS to autonomous driving. Source: Infineon

According to Infineon, the ASIL-D certification applies to the full range of SEMPER NOR memory products. That includes HYPERBUS and JEDEC xSPI octal interfaces as well as 256-megabit to 2-gigabit densities. Moreover, these memory products are qualified to AEC-Q100 grade 1 standard.

More information about NOR flash memory and its ASIL-D functional safety certification is available on Infineon’s Memory Solutions Hub web portal. The company also offers the “SEMPER SDK Safe” software development package alongside this NOR flash memory.

Related Content

• The Shift from 2D to 3D NOR Flash
• Flash 101: NAND Flash vs NOR Flash
• Flash 101: The NOR Flash electrical interface
• NOR flash eyes IoT devices catering to more code, data
• Improving performance using SPI-DDR NOR flash memory

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By the time you read this, sometime in May, Lent will be over. As I’m writing it in late March, Lent’s ~half over. I’m splitting the difference and going with an Easter theme for this piece.

Back in February 2012, I bought a CyberPower CP825AVRG, one of several UPSs (uninterruptable power supplies) currently inhabiting my abode, on sale from Staples for $54.99. Here are some stock photos of it:

Aside from the inevitable couple of iterations of SLA battery replacements, it’s still going strong more than a decade later, through two subsequent residence (including one time zone) transitions, with one exception, which ironically has nothing to do with its battery-backup power output facilities. The four outlets along the left side in the first two earlier stock photos are both battery-backed and surge protected; the ones along the right only offer surge-protection support. And, unsurprisingly, the one in the lower right corner has seen the most unplug-and-replug use, due to its under-desk proximity-to-me.

The UPS problem

A few months back, I woke up one morning to find my iPad Pro’s battery only partially full, even though I’d as-usual plugged it into its USB-C charger the night before:

As mentioned before, I’ve owned this particular charger since mid-2019, so it wouldn’t have surprised me to learn that it had finally “given up the ghost”. But on a hunch, driven by my admittedly obsessive thriftiness, I carried the charger, USB-C cable and iPad Pro over to an available AC outlet one room over, plugged everything in and…the tablet started charging.

If the problem’s not with the charger, it’s obviously with the outlet the charger’s plugged into instead, right? I confirmed this hypothesis by plugging the charger back into the UPS and wiggling it, wherein I could tell from the telltale “beep” coming from the tablet when charging was (now inconstantly) happening there. At least one of that AC outlet’s contacts buried deep inside the UPS was no longer making a solid connection with whatever was plugged into it.

The short-term solution

My initial workaround employed an intermediary short extension cord plugged into the UPS, with the charger (or anything else I might want to power at the time) plugged into that:

The aspired-for improvement was two-fold; the extension cord’s “female” connector end would bear the brunt of subsequent charger, e.g., unplugs and re-plugs, plus the added “earth ground” NEMA 5-15 prong on the “male” connector end would give the to-UPS connection more rigidity.

And my “hack” worked…for a while. But then the UPS’ AC connection to the extension cord started giving out, too, whenever I’d breathe on it (I’m exaggerating, but only a bit).

Opening the UPS up

At this point, I was about ready to give up on the CP825AVRG; I planned to put duct tape over the flaky AC outlet, along with taping a note to the UPS, and then donate it. After all, those CyberPower LE850G successors I’d mentioned in late 2022 were still sitting in their boxes awaiting their turns in the spotlight, and with slightly higher power output along with two more total outlets (one battery-backed, the other surge-only), to boot:

But like I said earlier, the CP825AVRG was otherwise still chugging along fine; it’s even supported by my Mac mini over USB for running-on-batteries alert purposes (note the connector in the upper right corner of this stock photo):

And have I already mentioned my admittedly obsessive thriftiness? Plus, hey, I’m an engineer; I’ll take any opportunity to tear something apart and satisfy my curiosity. So, one recent evening, I grabbed a screwdriver and, throwing caution to the wind (after unplugging the darn thing and waiting a few minutes for capacitive discharge, of course!), dove in:

Buh-bye, temporarily (hopefully), battery:

In addition to the (already removed) screw that held the battery compartment lid in place, six other deeply recessed ones keep the two case halves together. You know what comes next:

Let’s focus in on the half that we particularly care about:

Brian: My, what a big transformer you have!
UPS: All the better to magnetically voltage-convert with!

Ahem. Today’s attention emphasis is on the left side of the device, associated with the surge-only outlets (since, in contrast to the earlier “stock” shots, the UPS is now upside down). I was initially disheartened, thinking I’d need to disassemble the entire thing to get to them. But then, after moving some wiring out of the way:

I realize that above them was a black plastic panel held in place by three screws:

The culprit

That’s more like it. Our patient is the outlet in the lower left corner. Zooming in, you can see the particular contact (the lowest one) that’s now “stretched” and no longer makes reliable contact with whatever’s plugged into it:

Grab a pair of needle-nose pliers. Squeeze gently. And…voila:

The insides

This is not going to be a full teardown; I wanted to return the UPS to full functionality, after all, not send it to the landfill. But while I had it partially apart, I went ahead and snapped some more photos for your enjoyment. Here’s the right-side vertically-mounted PCB, front-to-back (as oriented in the earlier overview shots), inner side first:

Now for the other (outer) side of that same PCB, in the same front-to-back order:

Now for the inside of the PCB at the back of the device:

And, last but not least, the inside and outside of the PCB in the back left corner:

It’s alive!

All that’s left is to retrace my disassembly steps in reverse, plug everything back in, grab a just-in-case fire extinguisher (kidding…maybe…), hit the power button and…we’re back in business!

Keen-eyed readers may have already noticed, by the way, that I’ve already replaced the elementary diminutive extension cord previously in that lower-right AC outlet with a “splitter”:

similar to two others you’ll see already in use there, for augmented total-available-outlets purposes. And on that note, by the way, I’m not under any delusion that my “fix” will last through the remainder of the UPS’s otherwise-operational lifetime. The metal in that contact is already fatigued; it’s only a matter of time until it stretches back out of reliable-contact place.

“I use everything until it completely falls apart”

That all said, in closing I’ll share the intro to an article on Yvon Chouinard in the latest (as I write this) issue of National Geographic, which I saw the very day after my successful-for-now repair:

Yvon Chouinard laughs when he tries to remember the oldest piece of gear he owns. Perhaps it’s a piton he forged in the late 1950s, after he taught himself blacksmithing and started Chouinard Equipment, Ltd.? Or maybe it’s one of the rugged rugby shirts his next company, Patagonia, made for climbing? Possibly the “fleece” jacket prototype Patagonia built using toilet-seat-cover fabric, which has since become an outdoors icon?

 “Almost everything I have is old,” says Chouinard, 86, grinning. “I use everything until it completely falls apart.” The Patagonia founder glances around the office of his Wyoming ranch—a pinewood house with a view of the Tetons that he and his friends built in 1976—then raises his hands to show that the sleeves of his faded plaid shirt are all in tatters. “My whole life has been pretty simple, really. I’m not a consumer.”

I’m no Yvon Chouinard. My life isn’t simple. And I’m definitely a consumer. But that all said, I’d like to think I still share at least a bit of his longstanding “dirtbag aesthetic”. Agree or disagree? Any other thoughts? Let me know in the comments.

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• Putting an APC UPS out of its (and my) misery
• Modern UPSs: Their creative control schemes and power sources
• A holiday shopping guide for engineers: 2022 edition
• Ungluing a GaN charger

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In Part 1 of this Design Idea (DI), we saw how a standard electret microphone capsule can be persuaded to detect infrasonic signals down to a fraction of a Hertz by adding some fairly simple equalization. In this second and concluding part, we will improve that circuitry and also add an audio output to allow us to hear the otherwise inaudible.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 shows the revised schematic. While the equalization is much the same, the circuitry around the mic itself is more elaborate. Originally, the mic was fed straight from the power rail, potentially causing feedback problems. Now, it is powered from a clean reference source and also enclosed in a feedback loop to help stabilize its operating point.

Figure 1 A new input buffer stabilizes the mic’s operation, while other additions improve the circuit’s performance.

R1 and D1 define a nominal +1.24-V reference supply for the mic’s positive terminal. (D1 is not specified. I used an LM385-1.2, but that family is now obsolete—why?? They seemed trouble-free and well-specified, the -ADJ version being especially useful. But LMV431s or LM4041s look good.) In the absence of any offset, A1’s output rests at -1.24 V, needed for the low end of the mic’s load resistor R4. When everything is set up and stable, the junction of R4 and the mic’s negative terminal is close to 0 V (or common). The mic’s signal rides on that, and is amplified by A2, a portion of it being fed back into A1 by R5 to help to stabilize the mic’s operating point.

Calibration and setting up

All microphones behave slightly differently, mainly owing to the spreads on their internal JFETs, so some initial calibration is needed: the load resistor R4 must be trimmed. Sw1a allows R5 to be open-circuited to speed up this initial adjustment, while Sw1b keeps C2 out of circuit (see below) for the same reason. They are shown in the operating position on the schematic.

Once set, operation will be stabilized by feedback, largely compensating for temperature changes. Without the feedback from A2, the tempco of the voltage across the mic measured around 13 mV/°C; with it, it drops to around 1. R18 trims the residual offset, which can otherwise be up to 200 mV at the output of A4.

C1, at 100n, is enough to hold A1 stable during calibration, but it is C2—10 µF—that defines the low 3-dB point of A1’s circuit, once allowance has been made for the reduction in its effective value by the feedback. If C2 is in circuit at start-up, things take takes ages to settle, so that capacitor is pre-charged and only switched seconds after switch-on. (Charge-injection, as shown in Part 1’s Figure 5, scarcely helped here, perhaps because the feedback neutralizes it.)

U1a generates that delay. C3 and R6 control the period, with R7 and C4 adding positive feedback for a snappy action. U1a then switches U1b to control how C2 is connected. During start-up, C2 is connected between A1’s output (-1.24 V) and the common rail, charging it to its expected operating voltage; during operation, it spans R3, defining the circuit’s time-constant.

That hysteresis is necessary because controlling a ’4053 directly with the slowly changing voltage from an RC network leads to it oscillating (at least with the Motorola and RCA devices to hand; those names alone date them). The chosen delay is longer than strictly necessary, given the values of C1 and R3, but it allows time for the rest of the circuit to settle better. This leaves a spare section of the ’4053; using it to repeat the pre-charging trick on C5 or to short out R14+15 during the start-up period made little difference to the overall settling time.

Acoustically isolating the mic and allowing both it and the circuit to settle properly before calibration is necessary. Temporarily enclosing it in two hollow hemispheres of modeling clay, loosely sealed together, works well. During operation, it should be shielded from any air movements. Even a single sheet of fabric suffices, but a block of open-cell plastic foam or a wodge of acoustic fiber should be even better.

 The rest of the circuit

The circuit around A3 is unchanged except for the added offset-trimming pot R18. A4 adds a two-pole Sallen–Key low-pass filter (f3dB ≈ 12 Hz) to the signal path so that, along with the roll-off from A3, any 50/60 Hz components are attenuated by 35 to 40 dB.

C8 and R14+15 define the overall low-end cut-off which, with the values shown, can vary from about 300 mHz to 1.7 Hz (3 dB points). With R15 maxed out, C1/R3’s time-constant is dominant.

In Part 1, we tried a meter for indication but found it to be rather slow. However, it now becomes a useful add-on, allowing the mic’s load resistance and the offset trim to be set easily. It still indicates the lowest frequencies well.

Figure 2 shows the response to changes in air pressure with R15 set to both its maximum and minimum values. While these are LTspice-derived traces, they closely match the real-world measurements. Compare the top, red trace with Figure 2 in Part 1.

Figure 2 The calculated frequency responses of the circuit with the limiting values of R15.

Actual results are shown in Figure 3. These used the test rig described in Part 1, and were taken with R15 set for maximum bandwidth. Like Part 1’s Figure 5, with which it can be compared, it was scanned manually, so don’t trust the frequency scale to be truly logarithmic. As before, the trace wanders vertically because of flicker or 1/f noise from the JFET, but the overall response and linearity are both clear.

Figure 3 Measured response using a real microphone in the pressure-chamber test rig.

The microphone used was the 10mm-diameter type which was to hand. “Other types are available” but may work differently. Tests using salvaged 5-mm units imply that the sensitivity is roughly proportional to the diaphragm’s area—or the square of its diameter—which seems reasonable. The 5-mm devices were both newer and quieter, presumably like their internal JFETs, so their overall S/N ratios were similar. Use the largest ones you can.

Hearing the infrasound

If we take the infrasonic signals and use them to modulate an audio tone, we can then hear what’s going on, or at least a proxy for it. A recent DI was for a pitch-linear VCO: this DI is of course the project (or gadget) for which that was needed (or wanted).

The oscillator used here is almost identical to one of the variants in that article. It’s shown in Figure 4. We won’t describe its operation here (you can refer back for the details) but there are some changes and additions.

Figure 4 Frequency-modulating an audio tone lets us hear the form of the infrasonics.

As before, the main part of it generates a tone whose frequency is centered at around 500 Hz and which varies by plus or minus an octave—doubling or halving the frequency—for control inputs ranging from plus to minus a volt (roughly), so that it is linear in pitch rather than frequency. That control input is of course the detected infrasonic signal.

Under extreme conditions, that signal can span the power rails—up to ±2.5 V—so it is potted down by R23 and R24. (Something non-linear in place of R24 is tempting but untried. That should allow low-level signals through almost unchanged while compressing the peaks. Perhaps two pairs of back-to-back 1N4148s, with a higher value for R23…)

The audio square wave from U2b feeds R28 and the pair of limiting diodes bridged by C13 and C14 to give a trapezoid of about a volt peak-to-peak. That may be excessive, so C13/14 also pot it down to ~100 mV pk–pk. A8 buffers the signal, R29 providing a ground path while scarcely shunting C14.

For a straightforward ~1 V pk–pk audio output, short out C13, make C14 33 nF, and eliminate R29 and pot R30. Even simpler (and cruder) would be to feed the phones directly from U2 through a 5k pot acting as a volume control. Extra filtering caps across the phones could then be added to taste.

Mixing and matching

We may want that lower signal level because it’s then comparable with the output from A2, which is the mic’s amplified wideband audio signal. R30 lets us cross-fade between that and our tones, should we want to. (And we may, a little later.) The output can now be fed to a power amp (I used a TDA7052A—not shown) and speaker or earphones (with a series resistor). With the left and right ’phones in parallel, the sound is roughly in the middle of your head; connecting them in series (out of phase) gives an “out there” effect, which can be less distracting if you also want to hear the complex soundscape of the planes, trains, and automobiles causing the infrasonics.

While it might be nice to include a sound file here so that you can hear the results, we will have to make do with something visual: a typical trace, showing a passing high-speed train a few hundred meters distant while a couple of planes much further away approach Heathrow Airport.

Figure 5 The effects of a nearby train, a plane or two, and some local traffic can be seen in this trace. Note the x-axis time scale.

Air is not the only element

We mentioned cross-fading earlier, but why might we want it? Two things that I have yet to try will be under the ground and underwater. Sealing a mic in a suitable and appropriately-weighted drinks bottle should make an interesting hydrophone, and the local canal will soon be awash with propeller noises. But will these mainly be directly audible or much lower in frequency? Pressure variations should couple through the bottle walls to the air within and thence to the mic, though probably with low efficiently. Filling the bottle with oil might improve that, at least until it seeps into the mic’s innards.

Another bottle, buried in and grouted into the ground (the local bedrock is chalk, exposed in places) may work as a geophone, not that there should be much audio in that underworld. Seismically quiet it may be round here, but we still get the odd rumble at magnitude 2 or 3.

Final flights of fancy

Wouldn’t it be nice to have a pair of mics, suitably spaced to make a stereo pair and each with its own equalization, perhaps with their summed outputs controlling the tone’s frequency and their individual ones adjusting the relative left–right amplitudes? Control of phase might also be needed, that being the main source of directional information at low frequencies, which could involve some rather complicated voltage-controlled all-pass filtering. Or something. Or a DSP.

If you want to see what electrets can do if customized by serious funding, search for “NASA infrasound” which will produce a slew of fascinating results, spanning environments from the ocean depths to the edge of space. While this DI cannot compete with NASA’s sub-millihertz detection capability, it should be just as much fun and is certainly rather cheaper.

Editor’s Note:

 Part 1 of this DI uses an electret mic to create infrasound. It starts with a basic equalization circuit validated with a DIY test fixture and simulations, and ends with a deeper analysis of the circuit’s real response.

 Part 2 includes refinements to make the circuit more usable while extending its detectable spectrum with an additional technique that allows us to hear the infrasonic signals.

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

 Related Content

• Revealing the infrasonic underworld cheaply, Part 1
• Squashed triangles: sines, but with teeth?
• A pitch-linear VCO, part 1: Getting it going
• Earplugs ready? Let’s make some noise!
• Supersized log-scale audio meter

 

The post Revealing the infrasonic underworld cheaply, Part 2 appeared first on EDN.

Analysts estimate that the global market for semiconductors will exceed $600 billion in 2025 and hit the $1 trillion mark by 2030, suggesting a CAGR of over 8%. It’s no surprise that the drivers behind this growth include the semiconductor devices and systems needed to support the rapidly growing segments like artificial intelligence (AI), automotive industries (autonomous driving and EVs), data centers and cloud computing, communications, and consumer electronics.

Electronic design automation (EDA) plays a critical role in the growth of the global semiconductor industry. Yet it’s relatively unknown outside of those who participate directly in the industry. In order to understand the value of EDA, it helps to grasp where EDA fits within the semiconductor supply chain.

Semiconductor value chain

The semiconductor supply chain is both complex and globally distributed. If we consider the portion of the supply chain from design through finished semiconductor products—packaged chips and systems, for example—it comprises the parts shown below.

Figure 1 The semiconductor supply chain encompasses product specification, chip design and verification, manufacturing and assembly, and test and packaging. Source: Bob Smith

Semiconductor companies are the primary users of EDA tools required for designing chips that may contain upward of billions of transistors. In addition to EDA tools, these companies also use semiconductor intellectual property (IP) blocks that are pre-designed and characterized functional blocks to help simplify the design process.

The beginning of the process that feeds the supply chain is the development of new chip designs. Leading into design is the upfront planning, including assessing the target market(s) and market timing requirements—both too early and too late must be avoided—and functional and performance characteristics. Once the plan is in place, the chip design process begins.

Chip design is a complex process that starts with architectural planning and detailed specifications on chip functionality and performance (Figure 2). The next steps take the design through different levels of abstraction and verification. All the blocks in the diagram are served by EDA vendors providing many different EDA products.

Figure 2 Chip design and verification are complex and require several steps before the design can be handed off to manufacturing. Source: Bob Smith

Register transfer level (RTL) design creates a software model of the chip using a hardware description language (HDL) such as Verilog or VHDL. This design must then be rigorously verified using a simulator, and in some cases, the use of hardware-assisted verification known as hardware emulators or FPGA prototypes. Once the software-based design is verified, the next step is another transformation.

Synthesis takes the RTL software design and transforms it into a logic-level netlist. The netlist is a collection of logical components and blocks interconnected to form the circuitry that will perform the chip’s functions. Additional verifications steps are performed after synthesis to ensure that the netlist works as expected.

Once the netlist is verified, the next step is the creation of the actual physical geometries used to define the structures (transistors) and interconnects (wires) that will be manufactured. This step is called place and route. “Place” refers to locating the functional blocks on the chip and “route” speaks to generating the wires that interconnect the blocks.

Physical design is followed by exhaustive verification steps that include checking functionality and timing. Other checks such as power and thermal integrity and design and electrical rule checking assess that requirements for the target semiconductor process have been met. These verification steps are the “gatekeepers” that must be satisfied before the design can be released to manufacturing.

The manufacturing industry includes providers of the equipment and materials that are used to manufacture semiconductor chips. Once manufactured, the fabricated chips are handed off to companies that specialize in the next step of assembly, test, and packaging.

In this final step before the chips can be delivered to market, these companies test the chips and then assemble them into packages. The packaged chips then head to distribution channels that ultimately deliver the chips to product manufacturers to assemble into their products.

The value of EDA

The total revenue contribution of these segments of the supply chain in 2024 was approximately $420 billion. In this same period, the EDA segment generated about $20 billion or ~ 5% of the total revenue. While this sounds like a small piece of the puzzle, the value of EDA goes far beyond what revenue numbers convey.

Where is this “unseen” value in EDA coming from? The answer lies in the complexities of the design process itself, and the driving need to keep up with the competition.

Modern chip design is both complex and challenging. The most sophisticated chips may contain tens of billions of transistors—far beyond the realm of unaided manual design.

Moreover, time to market is everything in the highly competitive market. The ability to design and deliver a new chip to address a market need on time and with the features that will ensure success in the end market is a daunting task. Design teams invest in the EDA and verification tools that help them optimize these tradeoffs.

The cost of designing and verifying a leading-edge chip can be in the hundreds of millions of dollars to go from concept to design completion and release to manufacturing. A design flaw or late delivery can mean the end of a promising new chip and lead to hundreds of millions of dollars or more in unrecoverable costs. Failure is not an option.

EDA tools are the engines that drive the design process and allow semiconductor manufacturers to meet ever-shrinking market windows. The EDA tools themselves and the methodology and flows (“recipes”) that each company develops around them are regarded as highly valuable trade secrets.

While time to market is at the top of the list, there are other considerations that EDA tools also address. These can include product safety, product lifecycle and suitability for specialized applications for markets such as vehicles, medical devices, and defense and aerospace. All these requirements mandate sophisticated design and verification tools that can be applied to ensure designs meet these needs—and deliver on time.

EDA plays another valuable role in the chain as a key driver in bringing new process technologies to market. Development of new semiconductor processes relies on tight partnerships between the process developers and the EDA companies.

It’s expensive to bring a new process to the point where it has been characterized and dialed-in so that it can deliver the yield and performance that potential customers will demand. But to be able to accept designs, semiconductor manufacturing must be able to support the customers with verified EDA tools and flows that will support the new technology. No tool support, no customers.

Semiconductor design is at the front end of the supply chain and the EDA industry provides the tools that are essential for turning out today’s complex chip designs. Without availability of these design automation tools, the new innovations and products that drive the global semiconductor industry forward would come to a screeching halt and the supply chain would wither and atrophy.

Value beyond licensing fee

The insatiable demand for new products from the electronics industry keeps intense pressure on the semiconductor manufacturers to deliver the future. In turn, this demands that the EDA industry continually deliver new tools, technologies and functionality that support the ongoing move to the future. Simply said, there would be no new products or growth in the global electronics market without EDA. Measuring the EDA market solely on revenue contribution vastly understates the value that EDA delivers to the global semiconductor industry.

The ultimate value that the EDA industry delivers to the global semiconductor industry is almost incalculable. Certainly, it is far beyond the licensing and maintenance revenues that the industry generates.

Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI technology community, representing members in the electronic system and semiconductor design ecosystem responsible for its management and operations.

 

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The post A short primer on EDA’s value in IC design appeared first on EDN.

A month back, I tore down Walmart’s onn. 4K Streaming Box, the Google TV-based successor to the company’s initial Android TV-based UHD Streaming Device that I’d dissected mid-last year. And as promised in last month’s coverage, this time I’ll be taking a look at the guts of its “stick” form factor sibling, the Google TV-based Full HD Streaming Device, the successor to the Android TV-based FHD streaming stick predecessor that went “under the knife” last December.

Device, stick, or box?

Read through those previous two sentences again and you might catch the meaning behind the “just don’t call it a stick” bit in this writeup’s title; similarly, you might get why last month I wrote:

Also, it’s now called a “box”, versus a “device”. Hold that latter thought until next month…

The word “device” seems to have inconsistent form factor association within Walmart. In the first-generation onn. product line, it referred to the “box”, with the rectangular form factor explicitly called a “stick”. This time around, the “stick” is the “device”, with the square form factor referred to as a “box” instead. Then again, as I mentioned last month, the first generation “box’s” UHD maximum output resolution is now instead referred to as “4K”, and similarly, the “stick” form factor has transitioned from “2K FHD” to “Full HD” in the product name, so…

Anyway…in last month’s piece, I pointed out the surprising-to-me commonality between the hardware in the two “box” generations’ designs. Will the same be the case with the two generations of “stick” devices? And as with Walmart’s “box” devices in comparison to the TiVo RA2400 Stream 4K, will I also encounter commonality between Walmart’s “sticks” and other manufacturers’ devices? There’s only one way to find out…let’s begin with a “stock” shot:

Unboxing the product

Now for the actual packaging of today’s patient, which set me back $14.88 in November 2023.

The joke never seems to get old, at least for me…you might disagree…

Open sesame:

It’s a box-within-a-box!

Flip open the top flap, and we get our first glimpse of the still-protected-by-plastic device inside, along with a sliver of literature (PDF here).

Here they are now freed from their cardboard captivity, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

Underneath are the AC power adapter, an HDMI extension cable, the remote control and a set of batteries for the latter:

Here’s a close-up of the AC power adapter’s micro-USB connector:

and its markings; interestingly, the max input current is higher than that for last month’s “box” PSU (0.25 A vs 0.2 A), although the output current specs are the same (1 A). I suspect that the input current variance is just efficiency-reflective of the sourcing deviation between the two PSUs, not of the respective systems’ actual power requirements. In fact, I’m expecting a lower-power-consumption SoC inside this time, along with decreased memory and the like.

Here are the “male” and “female” ends of the HDMI extension cable:

And here’s the battery compartment-exposed backside of the remote control, which appears to be identical to last month’s “box” remote:

The teardown

Now for our patient, with dimensions of 3.54 x 1.18 x 0.51 inches (90.5 x 30 x 13 mm), quite close to those of its Android TV-based precursor (3.81 x 1.39 x 0.61 inches). That said, there are some physical design variations between them:

• No passive airflow vents either top or bottom this time, and
• Last time there was no status LED included in the design, and the recessed reset switch and micro-USB power input were on opposite sides of the device. This time, the micro-USB power input is on one end (with the HDMI connector again on the other), and a status LED has been added, next to the reset switch.

A closeup of that last shot reveals, among other things, the FCC ID (2AYYS-8822K2VTG, and no, reminiscent of what I also said last month, I don’t know why there are 21 different FCC documents posted for this ID, either!).

Applying a spudger to the gap between the two case halves get them apart with damage to only one of the plastic tabs.

For orientation purposes, we’re looking at the inside of the top half of the device case, along with the top of the PCB (“top” and “bottom” being somewhat meaningless with a “stick” form factor, as I’ve noted before, but I’m going by where the brand logo is stamped on the case):

The PCB then lifts easily out of the remaining bottom case half.

Here’s the inside of the bottom half of the case, once again accompanied by the top of the PCB:

and now with the PCB flipped over to reveal its bottom side. Note, for example, the light guide (aka, light pipe, light tube) that, as with the one we saw last month, routes the output of the LED on the PCB (at bottom, to the right of the Faraday cage) to the outside world.

Speaking of Faraday cages, let’s flip back to the PCB topside and begin our disassembly. En route to that destination, here are snapshots of both sides:

The heat sink on top clung to the Faraday cage below it stubbornly finally relented in the face of my intense spudger attention.

The Faraday Cage itself was much less removal-resistant:

A look at the ICs

Focusing in proved to be…interesting, among other things (including initially frustrating).

The IC on the left was easy to ID, although the marking was faint (stay tuned for another photo where it’s clearer, courtesy of augmented lighting). It’s Amlogic’s S805X2, another in a long line of examples of onn. devices based on application processors from this supplier. The S805X2 was introduced in Q2 2020, and Wikipedia lumps it into the company’s fourth-generation product line in seeming contrast to the “2” end character in its product line. The “X”, as I explained last month and versus the “Y” version seen in that teardown, refers to its integration of wired Ethernet support, which is a bit curious, particularly for a “stick” form factor device, albeit not unique (note, for example, Ethernet over micro-USB on the Chromecast Ultra).

Versus the Amlogic S805Y-B seen in the Android TV-based “stick” predecessor, the S805X2 bumps up the quad-core Arm Cortex-A35 processor cluster’s clock speed from 1.5 GHz to 1.8 GHz (vs 2 GHz in the Amlogic S905Y4 seen last month, however), upgrades the GPU from the Mali-450MP to the Mali-G31 MP2, and (like last month’s S905Y4) adds decoding support for the AV1 video codec. And speaking of Chromecasts, I need to give credit where it’s due (the Reddit crowd) on this one; it’s essentially-to-exactly the same SoC found in the “HD” variant of Google’s Chromecast with Google TV. The only variance, for which I can’t find clarifying documentation, is that in this case it’s marked “S805X2-B” whereas the one in Google’s design is the “S805X2G”.

Move to the right and you’ll encounter another example of Chromecast with Google TV commonality…sort of. And this one caused me no shortage of teeth-gnashing until I eventually figured it out. Revisiting my last-December teardown of this device’s Android TV-based predecessor, you’ll find that it contains 1 GByte of system DRAM, comprised of two 4 Gbit memory devices. Last month’s “box” sibling, conversely, touts 2 GBytes of system DRAM, assembled from two 8 Gbit memories. I already knew from the product specs on Walmart’s website that this device embeds 1.5 GBytes of DRAM. And so, since I’d thought memory pretty much always is sold in binary-increment capacities (1, 2, 4, 8, 16…), I figured that as with the similarly 1.5 GByte-equipped Chromecast with Google TV HD Edition, I’d find the two-device combo of 8 Gbit and 4 Gbit memories inside.

Problem is, though, that after identifying the other two notable ICs in this design, which you’ll see next, I could only find one other chip: this one. And it’s marking were unlike any I’d ever seen before. Again, they’re quite faint under ambient light; I tried both a loupe and supplemental lighting to make at least the company logo clearer for both me and thee:

Here’s the four-line mark:

[COMPANY LOGO] ARTMEM
ATL4X12324
M102
325M10

Doing web searches for “ARTMEM”, “ATL4X12324” and the combination of the two got me…basically nothing. Eventually, however, I stumbled across an obscure page on MIT’s website that clued me in to the likely full company name, Artmem Technology. That website is totally            in Chinese, however, which didn’t help me at all. But after searching again on the full “Artmem Technology” phrase, I came across the website of another China-based semiconductor supplier, Rayson HI-Tech, which offers an English-language option and identifies Artmem as its subsidiary.

Progress! Diving further into Rayson’s website, specifically to the “Industrial/Automotive LPDDR4/4X” product page, I indeed found a 1.5 GByte product variant (along with other non-binary increment options…3 GBytes and 6 GBytes, specifically) with the following parameters:

• Product model: RS384M32LX4D2BNR-53BT
• Bit width: x32
• Speed (presumably max, and operating voltage-dependent): 3733 Mbps
• Encapsulation mode: FBGA 200-ball
• (Operating) voltage: 1.8/1.1/0.6V
• (Operating) temperature: 25-85°C)

I’m guessing this is our chip, with alternate (subsidiary) supplier branding. Is there an atypical 12 Gbit monolithic memory die inside that package? Or did the company combine more common 8 Gbit and 4 Gbit die side-by-side under a single package “lid”? Or was it a three-die 4 Gbit “stack”? Or did the supplier just “down-bin” a 16 Gbit die to come up with the 12 Gbit guaranteed capacity? I ran this mystery by my long-time colleague Jim Handy, semiconductor memory expert at market analyst firm Objective Analysis, and he had several insights:

• Non-binary packaged unit capacities are more common than I’d realized, especially for LPDDR DRAM variants (which are also commonly spec’d in GByte vs Gbit densities)
• His guess is that there’s a three-die “sandwich” inside, with each die 4 Gbit in capacity, likely sourced from CXMT and/or JHICC, the two major DRAM makers in China, and
• The built-in translation support offered by Google’s Chrome browser works pretty well, judging from the screenshots of Artmem Technology’s English language auto-converted website that he sent me (I’m normally a Mozilla Firefox guy).

Please respond in the comments, readers, if you have additional informed insights on this!

The other notable IC—wireless module, to be precise, as you’ve probably already guessed from its antennas’ proximity—on this side of the PCB and to the right of the mystery DRAM, is much easier to ID. Like its predecessor in last December’s teardown, and unlike its sibling in last month’s teardown, it’s clearly marked on top. This is the 6222B-SRC from Fn-Link, containing a Realtek RTL8822CS Bluetooth-plus-Wi-Fi transceiver (which you can see in the internal photos on the FCC website). There was no separate (PCB-embedded or otherwise) Bluetooth antenna that I could see in this particular design, and Fn-Link’s documentation subsequently confirmed my suspicion that the module optionally supports multiplexing the 2.4-GHz Bluetooth and Wi-Fi functions on the same antenna:

Speaking of which, here are some closeups of those antennas:

Last, but not least, let’s flip the PCB back over again and see what’s underneath that bottom-side Faraday cage we earlier glimpsed:

It’s the nonvolatile memory counterpart to the earlier volatile DRAM; a FORESEE FEMDNN008G-08A39 8 GByte eMMC NAND flash memory module. FORESEE is one of the brand names of a Chinese company called Longsys, who had also acquired the Lexar brand from Micron Technology back in 2017. And speaking of “see”, I think that’s all to see today, at least from me. Let me know what I might have overlooked in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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• Walmart’s onn. 4K streaming box: A Google TV upgrade doesn’t clobber its cost
• The Google Chromecast Gen 3: Gluey and screwy
• The Google Chromecast Gen 2 (2015): A form factor redesign with beefier Wi-Fi, too
• Google’s Chromecast with Google TV: Dissecting the HD edition

The post Walmart’s onn. full HD streaming device: Still not thick, just don’t call it a stick appeared first on EDN.

Embedded Multi-die Interconnect Bridge-T (EMIB-T) was a prominent highlight of the Intel Foundry Direct Connect event. Intel is promoting this advanced packaging technology as a key building block for high-speed chiplet designs and has partnered with major EDA and IP houses to accelerate implementations around EMIB-T technology.

As the nomenclature shows, EMIB-T is built around the Embedded Multi-die Interconnect Bridge (EMIB) technology, a high-bandwidth, low-latency, and low-power interconnect for multi-die silicon. EMIB-T stands for EMIB-TSV and it supports high-bandwidth interfaces like HBM4 and Universal Chiplet Interconnect Express (UCIe). In other words, it’s an EMIB implementation that uses the through-silicon via (TSV) technique to send the signal through the bridge with TSVs instead of wrapping the signal around the bridge.

Figure 1 EMIB-T, which adds TSVs to the bridge, can ease the enablement of IP integration from other packaging designs. Source: Intel

Another way to see EMIB-T is the combination of EMIB 2.5D and Foveros 3D packaging technologies for high interconnect densities at die sizes beyond the reticle limit. Foveros is a 3D chip stacking technology that significantly reduces the size of bump pitches, increasing interconnect density.

All three major EDA powerhouses have joined the Intel Foundry Chiplet Alliance Program, which is intrinsically linked to EMIB-T technology. So, all three are working closely with Intel Foundry to develop advanced packaging workflows for EMIB-T. Start with Cadence’s solution, which helps streamline the integration of complex multi-chiplet architectures.

Next, Siemens EDA has announced the certification of a TSV-based reference workflow for EMIB-T. It supports detailed implementations and thermal analysis of the die, EMIB-T and package substrate, signal and power integrity analysis, and package assembly design kit (PADK)-driven verification.

Synopsys is also collaborating with Intel Foundry to develop an EDA workflow for EMIB-T advanced packaging technology using its 3DIC Compiler. In addition to the EDA trio, Intel Foundry has engaged other players for EMIB-T support. For instance, Keysight EDA is working closely with Intel Foundry to bolster the chiplet interoperability ecosystem.

Figure 2 The EMIB-T advanced packaging technology promises power, performance, and area (PPA) advantages for multi-die chiplet designs. Source: Intel

The EMIB-T silicon bridge technology is a major step toward harnessing advanced packaging for the rapidly emerging chiplets world. Intel Foundry Direct Connect highlighted how the Santa Clara, California-based chipmaker sees this advanced packaging technology in its future roadmaps. More technical details about EMIB-T are likely to emerge later in 2025.

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The generation of single sideband (SSB) signals first came to my attention via ham radio back in the early 1960s. My call was then and still is WA2IBH. The best phonetic I had for that call sign was “WA2 I’ve Been Had” but that’s merely a side note.

Most voice communication through ham radio back then was done by amplitude modulation or AM signals. When you heard someone on the air with an AM signal, the voice quality was usually pretty good. As I recall, the E.F. Johnson Viking Ranger transmitter was thought of as having the very best audio quality. Of course, when you had many signals on the air at the same time with different carrier frequencies, heterodyne squeals were an unpleasant fact of life which often degraded the intelligibility of the person whom you wanted to hear.

Enter into service, SSB.

To demodulate an SSB signal, a receiver needs to reinsert a carrier signal to replace the carrier signal that the sender is NOT transmitting. The resultant sound is intelligible, but the idea of audio quality is a lost cause. A human voice in a demodulated SSB transmission is difficult to linguistically describe. Perhaps it might be thought of as listening to a cross between Donald Duck and Mickey Mouse. A big improvement, though, is that there are no heterodyne squeals. All you hear from multiple signals coming through at the same time are distorted but intelligible voices. This is a MAJOR improvement. However, the acceptance of SSB in ham radio was not universally enthusiastic.

Short-wave receivers produced up through the 1950s would have automatic gain control (AGC) built in, but the response times of the AGC function were not well suited to SSB service. Modern AGC designs have “fast attack and slow decay,” meaning that the receiver gain is reduced very quickly upon arrival of an overly strong signal and that receiver gain is subsequently restored slowly. Since SSB signals have amplitudes that are “spiky,” meaning high peak amplitude to average amplitude ratios, the AGC circuits of these older receivers could be “pumped” by SSB signals, even if the receiver were not tuned exactly to the SSB signal’s exact frequency. Reception of pretty much anything else could and often was very badly affected. Modern AGC control is much better.

Many non-SSB users confronted by AGC pumping incorrectly assumed that SSB users were guilty of “splatter,” the descriptive term for the spectral spread of an overmodulated (> 100%) AM transmission. Derogatory terms such as “splatter sideband” and “silly sideband” were in common use.

Today, ham radio voice communication is dominated by SSB.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Single sideband generation, Part 2 appeared first on EDN.