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Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

The post The system architect’s sketchbook: Inside the simulation appeared first on EDN.

In the world of audio, silence is often as valuable as sound. Whether it is the low rumble of an airplane cabin, the drone of traffic, or the hiss of background noise in a recording, unwanted audio can compromise clarity and comfort.

Active noise control (ANC) offers a sophisticated solution: instead of merely blocking noise, it uses microphones, processors, and speakers to generate an equal and opposite signal that cancels interference in real time.

This marriage of acoustics and digital signal processing has transformed how we experience music, communication, and quiet itself, making ANC one of the most elegant applications of engineering in audio systems.

 

Active noise control vs. active noise cancellation

Before the dive, it’s good to note that active noise control (ANC) is the overarching engineering principle—using sound to counter sound—while active noise cancellation is its most familiar audio application, seen in headphones, earbuds, and car cabins.

This distinction matters because it shows how a fundamental control concept translates into everyday listening, making the science behind ANC directly relevant to how we experience clarity and comfort in audio systems.

Noise management: Isolation, reduction, and cancellation

To effectively manage sound, it’s important to distinguish between passive isolation, active noise reduction (ANR), and active noise cancellation (ANC), as these terms are often conflated in consumer marketing. Passive noise isolation provides the foundation, using physical barriers like dense ear-cup foam and high-quality seals to block sound waves from entering the ear canal, making it effective against a broad spectrum of high-frequency noises.

Beyond this physical barrier, active noise reduction (ANR) and active noise cancellation (ANC) represent the same advanced technology; the former term being more common in aviation and industrial sectors, and the latter in consumer retail. Both utilize integrated microphones and digital signal processing to sample environmental noise and generate a precise “anti-noise” signal in real time.

By applying the principle of destructive interference—creating an inverted wave that effectively neutralizes the original sound—these active systems are uniquely capable of erasing steady, low-frequency sounds that passive methods struggle to mitigate.

Nature’s ANC: How treefrogs and other animals tune out the world

Nature is the original engineer when it comes to acoustics, and while you will not find animals with electronic hardware, some species have evolved ingenious biological mechanisms that function on the exact same principle as active noise cancellation (ANC).

The most striking example is found in certain species of treefrogs, which face the daunting challenge of picking out a specific mate’s call amidst a deafening swamp-wide chorus. To solve this, they possess an internal connection between their eardrums that passes through their lungs; this allows the lungs to act as an acoustic filter, creating a phase-cancellation effect that effectively “mutes” the frequencies of competing species while amplifying the call of their own.

Beyond this direct analogue to ANC, many animals utilize other strategies to combat environmental noise, such as the “Lombard effect,” where birds and primates actively adjust the pitch or volume of their vocalizations to cut through ambient chaos, or the “jamming avoidance response” seen in electric fish, which shift their pulse frequencies to prevent signal interference. Ultimately, while these animals are not wearing headsets, evolution has mastered the art of filtering out the noise to focus on what matters most.

And as a historic note, ADI’s SSM2000 was a pivotal audio IC that revolutionized noise reduction through its patented HUSH “single-ended” technology.

Unlike traditional systems that required complex pre-encoding, SSM2000 could adaptively and dynamically strip away hiss and background noise from any audio source on the fly. By integrating a sophisticated dynamic filter and downward expander into a single, cost-effective package, it became the industry standard for enhancing signal clarity in 1990s consumer electronics—ranging from car stereos to early PC sound cards—offering a clever, hardware-based solution for high-fidelity sound that paved the way for modern signal processing.

Figure 1 From the 1990’s SSM2000 to today’s DSP-driven architectures, engineers leverage biological noise-suppression mechanisms to deliver precision audio clarity. Source: Author

Inside active noise cancellation systems

Active noise cancellation (ANC) works by detecting and analyzing incoming sound patterns, then generating an opposing “anti-noise” signal to neutralize them. This process significantly reduces the level of background noise you hear. ANC is especially effective against steady, low-frequency sounds such as ceiling fans or engine hums. While it’s most commonly found in stereo headsets that cover both ears, some mono headsets also incorporate ANC technology to enhance noise management.

Figure 2 Sketch demonstrates the core principle of ANC. Source Author

In essence, ANC works by generating an anti-noise waveform that mirrors the shape and frequency of the unwanted sound. This waveform is produced at a phase angle of exactly 180° opposite to the noise, so when both signals meet at the target area, they effectively cancel each other out.

ANC systems can be implemented through different hardware configurations:

• Feed-forward ANC: A microphone is positioned on the outside of the earphone to capture external noise before it reaches the ear.
• Feed-back ANC: A microphone is placed inside the earphone, monitoring the sound that actually enters the ear canal and canceling it in real time.
• Hybrid ANC: This combines both feed-forward and feed-back methods, offering more precise and adaptive noise reduction across a wider range of frequencies. That is, two microphones are used to form a closed-loop design. The reference microphone forecasts incoming external noise, while the error microphone audits the sound inside the ear canal. This dual setup enables the system to cancel noise effectively and avoid feedback issues.

Beyond hardware design, ANC relies on adaptive cancellation. This technique uses one or more microphones to continuously detect external noise and dynamically adjust the anti-noise waveform in real time to suit changing environments.

While some specialized industrial noise-control systems use a ‘synthesis method’—where the noise pattern is sampled and a known waveform is generated to counteract it—modern consumer headphones rely almost exclusively on adaptive, real-time processing to handle the unpredictable and constantly changing noise of the real world.

Broadband vs. narrowband noise cancellation

In the field of active noise control engineering, the terms broadband and narrowband carry meanings that differ from their use in telecommunications. Broadband ANC refers to systems designed to reduce unpredictable, wide-frequency environmental noise such as traffic, crowd chatter, or wind.

Because this type of noise is random, the system requires a coherent reference signal to generate an effective anti-noise waveform. By measuring the primary noise upstream, the digital controller can model the phase and magnitude of the disturbance in real time, allowing correlated noise to be canceled downstream at the loudspeaker.

Narrowband ANC, on the other hand, is tailored to periodic noise generated by rotational machinery, such as engines or fans. Instead of relying solely on an acoustic input microphone to capture the noise mid-propagation, the system uses a non-acoustic reference—such as a tachometer signal—to determine the fundamental rotational frequency.

Since repetitive noise occurs at predictable harmonics of this frequency, the control system can model these components with high precision. This approach is particularly effective in vehicle cabins, where it suppresses specific engine-related vibrations without interfering with speech, radio performance, or essential warning signals.

Modern ANC implementations often combine these strategies, resulting in adaptive broadband feedforward control, which utilizes acoustic sensors, and adaptive narrowband feedforward control, which employs non-acoustic sensors like accelerometers or tachometers.

Figure 3 A simple graphic depicts destructive interference as anti-noise combines with unwanted noise to reduce residual noise. Source: Author

Balancing promise and pitfalls: The realities of ANC

So, while active noise cancellation promises remarkable benefits—quieting the hum of engines, reducing fatigue during long journeys, and sharpening the clarity of music or speech—it also comes with challenges that beginners should appreciate. ANC systems excel at steady, low-frequency sounds but falter when faced with sudden or irregular noise.

Engineers must carefully tune parameters such as the damping ratio, which governs system stability, and the phase response, which determines how precisely the inverted signal cancels the original. Too much damping can make the system sluggish, while too little risks instability or even amplifying certain frequencies.

Latency in signal processing, microphone placement, and the physical limits of speakers all add complexity. Understanding these trade-offs is vital, because ANC is not about achieving perfect silence; it’s about learning how physics and signal processing collaborate to reduce chaos in real-world conditions.

Silence from chaos: The beginner’s journey into active noise cancellation

Active noise cancellation is one of those technologies that feels almost magical, yet it’s rooted in a principle simple enough for beginners to explore. Imagine sitting in a room filled with the steady hum of a fan or the drone of traffic outside and then hearing that noise dissolve because of a circuit you built yourself. That is the essence of ANC—capturing unwanted sound, inverting its waveform, and blending it back so the disturbance cancels itself out.

For those new to the field, the journey does not require professional acoustic labs or high-end industrial equipment; a pair of microphones, a set of speakers, and basic signal processing components are sufficient to begin. However, it is important to be clear: designing a functional ANC system from scratch is one of the most formidable challenges a hobbyist can undertake. It demands more than just coding skills; it requires a deep understanding of wave physics, precise timing, and acoustic dynamics.

The complexity of this task lies in the “latency budget”—the critical window of time the system has to process external noise and generate an inverse wave before it reaches the ear. If the processing takes too long, the waves will not align properly, failing to achieve destructive interference.

Fortunately, the barrier to entry has lowered. Modern, high-speed microcontrollers and dedicated DSP hardware now allow hobbyists to implement adaptive filters that were once exclusive to expensive, industrial-grade equipment. Chips from major players like Analog Devices and ams OSRAM bring ANC within reach of hobbyists, offering playful possibilities for makers eager to experiment with noise cancellation and advanced audio signal-processing projects.

As an introductory analog experiment, serious hobbyists can explore active noise cancellation by setting up a microphone to capture ambient noise, inverting that signal via an active phase-inverter, and summing it back into the audio path to create destructive interference. While this approach lacks the adaptive processing of digital systems, it provides a masterclass in phase alignment, group delay, and the iterative challenge of balancing amplitude in real-world signal paths.

Well, the first time you hear noise dissolve because of your own project, you realize it’s not just about electronics, it is about discovering how human ingenuity can carve silence out of chaos. That is the real inspiration of ANC for beginners: a hands-on path into the power of sound, silence, and imagination, now made more accessible than ever by today’s tools.

Ready to explore? Begin your first ANC experiment today and discover how you can turn noise into silence with your own hands.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Active Noise Cancellation
• The Basics and Acoustic Echo Cancellation
• Digital Active Noise Cancellation for Consumers Who Want It All
• Active noise control – a software-based approach for automobiles
• Active noise cancellation: Trends, concepts, and technical challenges

The post Active noise control: Engineering silence in audio systems appeared first on EDN.

Step-down buck converters used in 48V-to-5V power supply designs are becoming increasingly common in automotive and industrial applications, especially in advanced driver assistance systems, in-vehicle infotainment, and robotics. While synchronous buck topologies achieve high efficiency, they sometimes fall short of expected performance. In some cases, switching behavior, controller bias, power, and thermal performance can create limiting losses, resulting in a decrease in efficiency.

Figure 1 shows the efficiency of Texas Instruments’ 48 VIN, 960 W four-phase buck converter with integrated GaN reference design (PMP23595), with the output voltage set to 5 V using forced pulse-width modulation operation without cooling.

Figure 1 Efficiency of 48 VIN to 5 VOUT at a 400 kHz switching frequency. Source: Texas Instruments

The efficiency curve in Figure 1 can meet the specifications of most 48V-to-5V power supply designs, but could fall just below the intended target for others. Rather than changing topology or adding complexity, it’s possible to make some practical adjustments within a standard buck converter to boost efficiency further.

Figure 2 shows the efficiency curve for of the 48V-5V buck converter under several test configurations, including added thermal management, switching frequency adjustment and external bias operation. These configurations were selected to isolate the effects of each adjustment and indicate that different loss mechanisms dominate depending on the operating point. Let’s look at each adjustment in greater detail.

Figure 2 Efficiency of 48VIN to 5VOUT with multiple adjustments. Source: Texas Instruments

Adjustment No. 1: Thermal performance

Adding a cooling system, in this case a heat sink, produced a negligible improvement at a low output current but resulted in a clear improvement above 30 A.

At a low output current, the total power dissipation remains relatively small, and device temperatures remain closer to ambient. Thus, reducing thermal resistance provides little effect.

At higher output current, conduction losses increase with IOUT2, causing the field-effect transistor (FET) junction temperature and inductor temperature to rise. As temperature increases, the FET drain-to-source on-resistance (RDS(on)) and inductor copper resistance increase, further increasing conduction losses. Incorporating a heat sink or some form of cooling reduces this rise in junction temperature, directly lowering temperature-dependent resistances. Another result is a measurable reduction in conduction losses, which appear as improved efficiency at high currents. At a high current – 80 A in this scenario – the improvement reached 0.8%.

Adjustment No. 2: Switching frequency

Reducing the switching frequency from 400 kHz to 250 kHz while ensuring that the inductance value was still suitable improved efficiency approximately 0.5% through the mid-current range and 1% in the high-current range. However, decreasing the switching frequency too much with the same inductor value can result in higher core losses if you don’t manage the ripple current correctly.

Reduced switching-related losses cause this behavior, such as field-effect transistor turn-on and turn-off losses, gate-drive losses, and internal controller switching losses. At a 48-V input, these losses scale quickly with both current and switching frequency.

At light loads, reducing the switching frequency produces smaller efficiency improvements, suggesting that fixed losses such as quiescent current or inductor core loss dominate in this region and limit the overall impact of this adjustment.

Adjustment No. 3: Controller bias power

In a forced pulse-width modulation configuration, supplying the controller bias from an external 5-V source improves efficiency by approximately 0.5% in the light- to mid-current range.

Deriving bias from VOUT remains a viable option if the output voltage is not a much higher voltage (such as 24 V and above) or much lower (such as 3V and below).

When deriving bias power internally from the output rail, a small portion of the converter’s output power operates the controller. At light loads, this overhead represents a slightly larger fraction of the total output power.

At higher output currents, the conduction losses in the FETs and inductor begin to dominate. In this region, the controller bias power becomes such a small fraction of total losses that it no longer produces a measurable efficiency benefit. As a result, the externally biased efficiency curve converges with the internally biased efficiency curve.

Adjustment No. 4: Inductor optimization

The inductor can play a larger role in efficiency than its direct current resistance (DCR) alone suggests. While copper losses depend on DCR and scale with the output current, core losses depend strongly on ripple current and switching frequency.

If the ripple current is high, core losses can become significant. This is especially common with powdered iron core material, which can have high core losses if you don’t account for the ripple current.

Increasing the inductance reduces ripple current and core losses but may increase DCR. Conversely, using a very low DCR inductor while having excessive ripple current can increase core losses to the point where it offsets the efficiency boost. The inductor choice balances DCR and ripple current such that neither copper nor core losses dominate.

When looking to improve converter efficiency, identify which loss mechanism dominates the operating region of interest as a useful first step. For what we have seen here on this synchronous buck converter, you can evaluate it quickly:

• If light-load efficiency is low, examine the switching frequency and internal bias losses.
• If efficiency is low at high current, focus on conduction losses and thermal management.
• If the losses appear higher than expected across the full current range, review the inductor ripple current and core material.

Once you identify the dominant loss mechanism, minor design adjustments can often lead to measurable efficiency gains.

The high-efficiency system in this exercise used the TI reference design that I mentioned earlier, which includes the LMG708B0 synchronous step-down converter with integrated GaN configured to a 5-V output with a reduced inductance of 2.5µH.

References

1. Jacob, Mathew. “Select inductors for buck converters to get optimum efficiency and reliability.” Texas Instruments Analog Design Journal article, literature No. SLYT775, 3Q2019.

Matthew Bowers is a systems engineer in TI’s Power Design Services team, focused on developing power solutions for automotive applications. Matthew received his bachelor’s degree in electrical engineering from Texas Tech University in 2023.

 

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• Power Tips #127: Using advanced control methods to increase the power density of GaN-based PFC

The post Power Tips #151: Improving efficiency in 48V-input multiphase buck converters with GaN appeared first on EDN.

Arm is now a chip vendor—what does it mean for the semiconductor industry? EE Times’ Nitin Dahad was at the event in San Francisco, California, where the British IP giant unveiled its first chip, an AGI CPU for data centers. He reports on what it means for the company, now increasingly dubbed Arm 2.0, and how this launch will impact its standing in the semiconductor industry. He also explains the delicate balancing act that Arm will have to play moving forward.

Read the full article at EDN’s sister publication, EE Times.

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The post What does Arm’s own chip stand for? appeared first on EDN.

Over the last few years, there has been growing interest across the global semiconductor packaging industry with a new approach. Co-packaged optics (CPO) involves integrating optical fibers, used for data transmission, directly onto the same package or photonic IC die as semiconductor chips. Traditionally, semiconductor packaging has used copper interconnects, but these can consume large amounts of power and lead to signal weakening at high frequencies when the distance is further than a couple of meters.

With CPO, the optical components are integrated directly into a package, and the long copper trace between the switch and the optical module is replaced with short, high-integrity connections. Optical signaling uses far less power at high data rates than electrical signaling. As CPO reduces the distance between optical components and the semiconductor dice, this lowers latency, improves high-speed signal integrity, and accelerates data transfer.

All of which are fundamental for the next generation of AI devices for high performance computing (HPC) inside the data center systems. Nevertheless, there are obstacles that need to be overcome with CPO and when designing photonic packages, especially for integrated photonic circuits or photonic chips. This is why advances in photonic package design are coming to the forefront.

 

Overcoming CPO obstacles

When co-packaging photonics with electronics, there can be signal integrity issues. Electrical crosstalk must be reduced to improve signal quality. Using short interconnects and low-parasitic layouts are the most appropriate tactics when used alongside co-design tools for optical optimization. Signal integrity can be ensured without requiring complex routing or more space, as optical interconnects can support multi-terabit-per-second data rates over long distances with only minor signal loss.

Mounting a large photonic IC die onto a laminate or organic substrate can be problematic. Due to the coefficient of thermal expansion (CTE) mismatch between the substrate and the photonic IC die, non-negligible die warpage may occur. This warpage can significantly degrade optical signal performance in the photonic IC waveguides during data transmission, leading to substantial reductions in optical signal power and quality.

In addition, excessive warpage may introduce mechanical stress in the photonic IC die, altering its material properties and further impacting optical performance. While using a ceramic substrate could mitigate these issues, it’s more costly and is not widely adopted today.

Dealing with temperature variations can be a concern with photonic devices, but efficient thermal management and thorough thermal design can help to improve performance and reliability. Integrating photonics with electronics may require thermoelectric coolers (TECs) and heat sinks along with smart thermal simulations throughout the design process.

Sub-micron alignment is also a complex technical task. Optical misalignment can lead to significant insertion losses, as well as disrupting device performance. Leveraging passive alignment techniques with etched features or alignment markers may mean lower levels of accuracy, but this is the lowest cost. Active alignment, using real-time optical feedback, results in better performance and efficiency, though it’s far more complex and costly.

Addressing challenges when testing optical components involves using built-in test waveguides, automated optical probing systems, and standardized test procedures during and after packaging. Integrating optical and electrical components into a single package not only makes the manufacturing process more complicated, the associated risks and costs are also greater due to the different assembly phases. It’s possible to cut through the complexity and improve yields by using standardized processes for CPO assembly.

The future of CPO and photonic package design

As a result of the growing interest in CPO and photonic packaging, there have been advances in photonic package design. CPO enables faster data transmission and improved power-efficiency when compared to the conventional copper-based interconnects approach. It has many advantages, including high-speed communication and lower power consumption, but there are also concerns related to signal integrity, thermal management, optical alignment, and costs.

Advances in photonic package design can overcome these obstacles and help electronic design engineers create new architectures that would not be viable with traditional semiconductor packaging. As the semiconductor industry continues to rapidly evolve, with more complex devices requiring high-performance, compact and power-efficient chips, CPO with advanced photonic package design will become increasingly important.

Dr Larry Zu is CEO of Sarcina Technology.

Special Section: Chiplets Design

• What the special section on chiplets design has to offer
• Chiplet innovation isn’t waiting for perfect standards
• Scoping out the chiplet-based design flow
• Demystifying 3D ICs: A practical framework for heterogeneous integration
• Chiplets: 8 best practices for engineering multi-die designs

The post Overcoming interconnect obstacles with co-packaged optics (CPO) appeared first on EDN.

Leveraging low-power wireless connectivity isn’t proprietary to a single smart-home technology and product supplier, no matter that each company’s implementation of the concept may be.

Back in 2019, when I first conceptually explored, then tore down, and finally implemented personally a Blink outdoor security system (still operational to this very day):

• Blink: Security cameras with a power- and bandwidth-stingy uplink
• Teardown: Security camera network module
• Teardown: Blink XT security camera
• Blink: Security camera system installation and impressions

The aspect of the architecture that intrigued me the most was the camera’s battery-powered nature. How on earth were they spec’d to run for up to two years (far from nearly five in real life) solely on two lithium AA cells while still regularly remaining user-accessible over Wi-Fi?

The answer, as those of you who’ve already read my writeups (and remember them) know, was a two-fold response:

• The entire system wasn’t battery-powered, and
• The communications infrastructure wasn’t solely Wi-Fi

In-between the cameras (back then, I was apparently using quarters for size comparison purposes, not pennies):

and the Internet is a Sync Module:

Multi-spectral stinginess

Requoting my original piece in the series:

A Blink system consists of one or multiple tiny cameras, each connected both directly to a common router or to an access point intermediary (and from there to the Internet) via Wi-Fi, and to a common (and equally diminutive) Sync Module control point (which itself then connects to that same router or access point intermediary via Wi-Fi) via a proprietary “LFR” long-range 900 MHz channel.

The purpose of the Sync Module may be non-intuitive to those of you who (like me) have used standalone cameras before…until you realize that each camera is claimed to be capable of running for up to two years on a single set of two AA lithium cells. Perhaps obviously, this power stinginess precludes continuous video broadcast from each camera, a “constraint” which also neatly preserves both available LAN and WAN bandwidth. Instead, the Android or iOS smartphone or tablet app first communicates with the Sync Module and uses it to initiate subsequent transmission from a network-connected camera (generic web browser access to the cameras is unfortunately not available, although you can also view the cameras’ outputs from either a standalone Echo Show or Spot, or a Kindle Fire tablet in Echo Show mode).

That the battery-powered network nodes (cameras in this case) are battery-based is convenient from a location-flexibility standpoint, not necessitating running wired-power feeds to them, just as the fact that they’re wireless precludes needing to run Cat5 spans to them. And in some cases, it also enables ongoing implementation functionality (at least to a degree) even if premises power goes down.

Discerning degree of dryness

Fast forward to the present. My wife and I recently bought a couple of ionizing humidifiers for the house, one of them “smart” (believe it or not; stay tuned for coverage to come):

The (upstairs) thermostats for our (downstairs) furnaces, one for each horizontal half of the house, supposedly also report residence humidity, but I’ve never believed the data they feed me; they perpetually say that it’s “<15%”. I could have just bought a cheap hygrometer (standalone humidity sensor) for $5 or so; this one’s even solar-rechargeable:

But when I came across one, the T315, part of TP-Link’s Tapo smart home product suite, I knew I had to have it:

It was less than $25 at Amazon. It leveraged Kindle-reminiscent display tech. And I already had several other Tapo devices active in the home. How hard could it be to add one more?

Ingenuity redux

Not hard, it turned out, but not quite as straightforward as I’d initially envisioned. The Tapo T315 is battery-powered, just like those Blink XT cameras. And equally similarly (can you already guess where I’m going here?), just as with TP-Link’s other smart sensors—buttons (doorbells, etc.), door and window contacts, presence, motion, water leak (hold that last thought), etc.—this time, in-between it and my router, there’s therefore a required (drum roll) smart hub!

Since my data payload size was modest in this case, I went with the entry-level Tapo H100, which Amazon also sells for sub-$25:

And I quote (sound familiar?):

The Tapo Hub is the heart of your Tapo smart home, connecting devices like smart sensors, switches and buttons, using an ultra-low power wireless protocol. This technology helps battery-powered devices last up to 10 times longer.

The company also sells more advanced (but still economical) hubs that further comprehend battery-powered Tapo security cameras (including, I’m assuming, transitioning them to Wi-Fi for active broadcast streaming, and also supporting local recording storage); the mid-range microSD card-based H200 and high-end H500, the latter shipping with 16 GBytes of eMMC flash memory and (believe it or not) further expandable via an optional 2.5” SATA HDD or SSD.

Here’s the packaging for the Tapo H100 smart hub, which I needed to activate first:

And here’s what was inside, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes, along with a sliver of literature which I didn’t bother photographing:

Nitty-gritty details:

Right-side configuration and reset switch:

After plugging it in to a power strip-housed AC outlet, setup was multi-step but straightforward:

Success!

Desert, jungle, or somewhere in-between?

Now for the Tapo T315 hygrometer. Packaging first, again:

Setup, including connection to the now-active hub several rooms over, was once again easy:

And there we are! Sub-15% humidity…pfft…

Water, water, (hopefully not) every where…

Feeling pretty good about myself, I decided to push my luck once more. When the plumber replaced our geriatric (but thankfully not yet leaking) water heater downstairs in the furnace room a few years ago, he threw in a standalone leak detection sensor (a valuable albeit often overlooked addition to any residence) to reside on the floor next to it:

Note, however, this bit in the operating instructions:

Replacing the battery: Replace the battery if the alarm has operated for an extended period of time, or if the battery expiration date is approaching. You may want to mark the battery expiration date on a piece of tape and attach it to the alarm when you install the battery.

Let’s be real. I know myself well enough to realize that once I set it, I’m going to forget it. I was admittedly surprised to learn, after replacing it (more accurately, moving it; it now sits below the whole-house water filter enclosure in a different room) that unlike my carbon monoxide detectors at their end-of-life dates, it didn’t at least chirp when its battery was getting low. That said, we’d only hear the sound if we were there at the time, and assuming it was loud enough to capture our attention. And further to that point, more generally, if we were away when a leak started, we’d be blissfully ignorant of what was going on…at least at first, until we returned home, that is.

Enter the $19.99 (on Amazon as I write this) TP-Link Tapo T300 Smart Water Leak Sensor:

Once again, box shots first:

Followed by what’s inside (minus, again, the also-provided piece of paperwork):

Yank the blue plastic strip to activate the factory-installed and user-replaceable two-battery connection:

Thereby auto-transitioning the sensor to setup mode:

Go through the brain-dead simple setup steps:

And voilà:

Dissections, etc., to come

My mixed Kasa-plus-Tapo smart home topology is functionally rock-solid so far, including the hub-based portion. Buh-bye, Belkin Wemo…and maybe, someday, Blink, too. To be clear, Blink and TP-Link’s disparate ecosystems, coupled with the latter’s comparatively greater product type diversity, would be the sole long-term replacement motivation (specifically, mothballing my Blink cameras and replacing them with TP-Link equivalents).

My Blink gear also continues to work just fine, including no evidence whatsoever of any functionally degrading interference between its and TP-Link’s respective ultra-low power wireless links. That all said, I’ll undoubtedly further expand my TP-Link-sourced stuff in the future; stay tuned for more hands-on coverage. Speaking of which, I’ve also got a redundant Tapo H100 smart hub and T300 smart water leak sensor, both sitting on the shelf, queued up for teardown, along with a display-less sibling of the T315 hygrometer, the Tapo T310 Smart Temperature and Humidity Sensor ($17.99 at Amazon):

I hope you’re looking forward to those analyses as well. Until then, let me know what you think in the comments!

—Brian Dipert is the Principal at Sierra Media and a former technical editor at EDN Magazine, where he still regularly contributes as a freelancer.

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The post The Tapo Hub: TP-Link joins the low-bandwidth, long-range RF club appeared first on EDN.

The 6G transition is no longer a distant theoretical exercise; it’s a commercial inevitability driven by fundamental requirements for cellular standards to keep moving forward. 5G penetration has already surpassed 75% and is on a trajectory to reach 95% within a few years. We are witnessing an appreciation for continued call quality and data throughput improvements despite an explosion in mobile traffic.

However, the wireless ecosystem projects that even this capacity will soon overload due to accelerating AI content, the integration of satellite communications (SATCOM) into the cellular fold, and the rise of physical AI. 6G is the industry’s response to keep pace with that exponential growth in data communication demand.

The 2030 countdown: Why 2026 is the crucial starting line

To understand the urgency, one must look at the decadal cycle of cellular evolution. History shows it takes about five years to finalize a standard and fold its requirements into a functional ecosystem. While 6G is anticipated to take off commercially by 2030, the work-back schedule reveals a tight timeline for product builders. By 2029, hardware must be ready for compliance testing, meaning component technologies must be finalized by 2028.

Consequently, underlying embedded systems must be built in 2027, necessitating that architectural definitions start as early as 2026. As an example of what is going on in the industry, Qualcomm’s CEO recently hinted at the Snapdragon Summit that 6G-capable devices could appear as early as 2028 for trials, making the 2028 Olympics a perfect arena for tech demos.

Unlocking the “Golden Band”: FR3 and the business of spectrum

Beyond architectural shifts, 6G introduces the Frequency Range 3 (FR3) spectrum, spanning 7.125 GHz to 24.25 GHz. Often called the “Golden Band for 6G,” FR3 offers the perfect balance between the wide coverage of lower bands and the massive capacity of mmWave.

This spectrum is expected to be a major business driver, enabling the 10x higher data rates targets (up to 200 Gbps) and supporting “massive MIMO evolution” to handle the projected 4x traffic growth by 2030 (going over 5.4 zettabytes as indicated by the GSMA Intelligence report).

Sustainable networks

Sustainability is a core pillar of 6G, with network operators seeking to reduce OpEx, as 25% of it is driven by power demand. 6G moves from an “always-on” to a “smart-on” philosophy, aiming for 30-50% increase in power efficiency. Key techniques include:

• Enhanced deep sleep modes: Enabling base stations to achieve near-zero power consumption when no active users are present, and reduction in periodic signaling (current 5G standard mandates high periodic signaling that in practice keeps a lot of the RF and power amplifier components active at all times).
• AI-driven beamforming: Using AI to direct signals precisely to users, reducing energy waste from broad, inefficient broadcasting.
• AI-driven resource management: Using AI at the higher protocol layers for effective radio resources management.

The AI-native revolution: Moving intelligence to the air interface

One of the most significant shifts in 6G is the move toward an AI-native air interface. Unlike 5G’s rigid mathematical models, 6G uses deep learning to dynamically adapt signal processing blocks. This enables “adaptive waveforms” that adjust modulation in real-time to environmental conditions.

It also facilitates integrated sensing and communication (ISAC), where RF reflections provide precise spatial awareness, allowing the network to proactively adjust beamforming based on user movement.

The coordination challenge: Managing two-sided AI

This transition introduces a complex challenge in how the transmitter (base station) and receiver (device) coordinate their intelligence. Unlike traditional algorithms, AI components must be synchronized through AI lifecycle management (LCM). The industry is weighing one-sided models (device-only optimization) against two-sided architectures (essential for tasks like CSI compression).

In two-sided designs, the device acts as a neural encoder and the base station as a decoder; these must be coordinated pairs to some extent. The level of coordination is still in study, as there are few optional schemes. Examples for those schemes are fully matched neural networks couples, or alternatively, independent at the NN architecture level but trained on the same dataset.

This raises critical questions on the protocol level: should the network use model ID-based selection (activating pre-loaded models) or model transfer (pushing new neural weights over the air) or weights transfer?

Programmable intelligence: Why DSPs are the preferred path

Because 3GPP specifications remain fluid, the need for flexibility through programmability has never been higher. Developing 6G on hard-wired logic is risky, as spec changes could render silicon obsolete. This is why digital signal processors (DSPs) are the preferred architecture. Modern DSPs are uniquely suited for the AI-native physical layer; they possess the massive number of MACs required for matrix operations and are highly efficient at the vector processing necessary for neural networks.

Leading technology vendors also offer dedicated AI ISA for accelerated NN activation functions. A fully programmable modem powered by AI-native DSP offers a “safe bet,” allowing developers to adapt as 6G settles while maintaining the performance needed to lead the market.

Elad Baram is director of product marketing for the Mobile Broadband Business Unit at Ceva.

Related Content

• Get ready for 6G
• 5G & 6G: Adoption, technologies and use cases
• 5G-Advanced to 6G: What’s next for wireless networks
• Making waves: Engineering a spectrum revolution for 6G
• The aspects of 6G that will matter to wireless design engineers

The post The 6G clock ticking: Why silicon architecture for 2030 must start in 2026 appeared first on EDN.

For decades, I’ve had a fascination with voltage-to-frequency converters and the 555 analog timer chip, and therefore a double obsession with VFCs based on the 555. In fact, my first Design Ideas (DI) submission (in 1974) was for a 555 VFC. It was not only published but also selected as the best DI of the year. That was it, I was thenceforth hooked forever.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The simple 555 VFC design to be presented here, so far as I know and as unlikely as it sounds for so *ahem* “mature” a part as the 555, is novel. It runs with good linearity and accuracy at 1 MHz, with even faster operation possible. That’s 100x faster than that 1974 555 frequency converter.

I hope you’ll find its details interesting.  Here’s how it works. The story begins with Figure 1.

Figure 1 Starred components are precision, including the +5 V supply, but something’s missing.

There’s nothing novel about the input current source comprising A1, Q1, and surrounding parts. It supplies 0 to 1 mA to the U1 current-to-frequency converter in response to its input voltage, as scaled and offset by R1 and R2.  The values shown set a 0 to +5 V input span.  R1 = 1.8M and R2 = 200k would make it -5 V to +5 V. 

A capacitor added in parallel with R2 will provide extra noise rejection. But the inherent noise immunity of the VFC analog-to-digital conversion is good, so you probably won’t need it.

Moving further into the circuit is when things do start to get weird, because the usual two resistors associated with 555 oscillators are missing. Also missing is the usual astable 555 1/3V+ peak-to-peak voltage swing.  This topology generates a 2/3V+ Vpp linear sawtooth waveform that resets, not to V+/3, but to zero. Unfortunately, while the sawtooth is nicely linear, due to U1’s internal switching delays Td, the frequency versus Q1 current Iq1 relationship is not very linear. Figure 2 shows how bad it is:

Frequency of oscillation (FOO) = 1.0/((VthC2/Ir3 + Td) = 1.0/(1.0ns/Ir3 + Td)

Figure 2 Nonlinear red curve versus ideal black shows ~20% linearity error from LMC555 internal delays.

Luckily, as derived in another recent DI: “Improve 555 frequency linearity.“

…it’s an easy fix. It consists of a single resistor, R4, connected between the Dch (discharge) and Thr (threshold) pins. R4 is used to linearize the current-versus-frequency function by biasing the Thr pin upward by IcR4. That cuts short the duration of the positive-going timing ramp and thereby the sawtooth period by the same amount that the delays lengthen it: IcR4/(Ic/C2) = R4C2 = Td.

Thus, if R4 is chosen so R4C2 = Td as shown in Figure 3, nonlinearity compensation will be (at least theoretically) complete over the full range of control current. The frequency of oscillator (FOO) for this circuit: 

FOO = 1/((VthC2)/Iq1 + 212ns – Td) = 1/(1.0ncb/Iq1 + 212ns – 212ns) = 1/(1.0ncb /Iq1) = 1000 Iq1 MHz = 1MHz(+5v – Vin)/+5v

Figure 3 R4C2 = Td = 212ns = nonlinearity compensation for 555 internal delays.

Now FOO will linearly track Iq1 and therefore Vin as shown in Figure 4.

Figure 4 Nonlinearity disappears if R4 = Td/C2 =212 ns/300 pF = 706 ohms.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included the best Design Idea of the year in 1974 and 2001.

Related Content

• Improve 555 frequency linearity.
• Tune 555 frequency over 4 decades
• 555 VCO revisited
• Inverted MOSFET helps 555 oscillator ignore power supply and temp variations
• Gated 555 astable hits the ground running

 

The post 1MHz 555 VFC appeared first on EDN.

Semiconductor design is in the midst of a structural shift. For decades, performance gains were achieved by packing more transistors into single, monolithic dies. But the physical limitations of these dies—and the process technologies used to create them—are at odds with the ever-increasing compute, memory, and I/O demands of modern workloads. In other words, process technology advances alone are not enough to keep up with modern workloads.

Stepping in to address these demands are multi-die designs, which combine several smaller dies (known as chiplets) inside a single standard or advanced package. These multi-die architectures are reshaping how engineers build everything from AI accelerators to automotive ADAS systems. By disaggregating compute, memory, and I/O, teams can mix and match chiplets—often from different process nodes—to optimize performance, energy efficiency, size, or cost.

However, multi-die designs introduce new engineering complexities and design considerations, spanning packaging, verification, thermal dynamics, and more.

Here are eight best practices for developing chiplet designs.

1. Leverage the ecosystem

Chiplet design is evolving through collaboration. Standards bodies such as the UCIe Consortium and JEDEC are defining interoperability, test, and reliability specifications. Research organizations like imec and ASRA are shaping automotive-grade chiplet guidelines. Leveraging this ecosystem reduces integration risk and helps ensure long-term compatibility.

Partnering with experienced IP and packaging vendors is also recommended. These providers can help teams fill resource and expertise gaps, focus on meaningful differentiation, and accelerate time to market.

2. Partition with purpose

Every successful chiplet design for multi-die systems begins with smart partitioning. This means dividing the system into functional domains—such as compute, memory, and I/O—and determining the best process technology for each. Advanced nodes typically provide the highest performance and density, while mature nodes can often be used for less demanding functions to help reduce cost.

Establishing a partitioning strategy early in the design process helps prevent late-stage trade-offs and simplifies future upgrades. And using standards-based interfaces between chiplets keeps the architecture scalable, allowing future upgrades (using newer chiplets) without major redesign.

3. Match node to function

The newest process node isn’t always the right one. Memory may not benefit from extreme scaling the way logic does, and analog or mixed-signal blocks often perform better on proven geometries. Selecting process nodes strategically—based on power, area, and yield targets—balances performance with manufacturability.

Design topology should also be considered. In 3D stacking, compute functionality based on the most advanced process nodes is typically placed on the top die, while I/O and SRAM functionality based on older, more cost-effective process nodes are placed on the bottom die. This approach lowers interconnect latency and power consumption but increases thermal complexity. Conversely, a 2.5D design—where chiplets are placed side-by-side—simplifies cooling and routing but often results in higher interconnect latency and power consumption.

4. Treat packaging as part of the design

The package is no longer a container—it’s part of the circuit—and teams must choose from several options. Organic substrates, silicon interposers, and full 3D stacks offer varying levels of signal density, cost, and yield. As such, they should be evaluated alongside system architecture in the earliest phases of design exploration.

Testing and yield must also be considered. Each chiplet should be thoroughly validated as a known good die (KGD) prior to integration to ensure reliability. Incorporating hierarchical test features within each chiplet enables effective post-packaging verification.

Additionally, designing die-to-die interfaces with built-in redundancy and repair capabilities can help recover yield during assembly and address potential link failures throughout the product’s lifecycle. Because packaging materials and lead times vary among suppliers, early and proactive coordination with the supply chain is key to avoiding unexpected delays and ensuring a smooth production process.

5. Engineer the interconnect like a subsystem

In multi-die designs, the communication between dies often defines overall performance. Die-to-die connectivity, bandwidth, latency, and signal integrity should be planned long before layout.

While standards such as UCIe are emerging to guide interoperability, each implementation faces unique physical challenges—including optimizing the “beachfront” area for micro bump placement, ensuring precise clock alignment, and managing routing density constraints.

6. Verify the entire system

Traditional block-level verification is insufficient for multi-die designs. Integration across process nodes, tool flows, and packaging layers demands system-level verification from the outset. Multi-physics analysis should be performed on the die and complete multi-die system in a package.

Hardware-assisted verification, emulation, and fast simulation environments can reveal timing or interoperability issues that static tests miss. Hierarchical testing validates individual dies, then re-verifies the assembled system to confirm consistent performance. Adding thermal and crosstalk analysis closes the loop between electrical and mechanical design domains.

7. Secure every interface

Multiple dies mean multiple entry points. Each chiplet must authenticate itself to the system and protect its data links. Embedding a root of trust (RoT) in a main or system chiplet can enable secure key management and firmware validation.

Encrypting traffic between chiplets prevents tampering, while a secure boot sequence ensures the system initializes only trusted code. Designing these controls at the architecture stage is far more effective than stitching them in later.

8. Design for control and reliability

Complex packages benefit from a dedicated control and management subsystem, a small processor that handles initialization, telemetry, and security functions. This control layer also manages reliability, availability, and serviceability (RAS), gathering data from sensors across chiplets to detect issues before they escalate.

Telemetry from this subsystem helps engineers tune performance and maintain uptime, especially in data center and automotive environments where predictability is everything.

From integration to innovation

As the semiconductor industry transitions from monolithic dies to multi-die architectures, engineering teams must adopt new strategies to address the unique challenges and opportunities of chiplet-based designs. By leveraging industry ecosystems, partitioning systems purposefully, matching nodes to functions, treating packaging as integral to the design, engineering robust interconnects, verifying at the system level, securing every interface, and implementing dedicated control and reliability measures, organizations can maximize the benefits of chiplets—achieving enhanced performance, flexibility, and scalability.

Embracing these best practices will not only accelerate innovation but also ensure that multi-die solutions meet the demands of tomorrow’s complex applications.

Rob Kruger is product management director for multi-die strategy at Interface IP Product Management Group of Synopsys.

Special Section: Chiplets Design

• What the special section on chiplets design has to offer
• Chiplet innovation isn’t waiting for perfect standards
• Scoping out the chiplet-based design flow
• Demystifying 3D ICs: A practical framework for heterogeneous integration

The post Chiplets: 8 best practices for engineering multi-die designs appeared first on EDN.

In process industries, field contacts from pressure, temperature, flow switches, limit switches, push buttons, etc., are read by programmable logic controllers and/or distributed control systems (PLC/DCS) through digital input modules.

They are located in the unit control room, which is at least 100 meters away from the field. Long cables run between them. They supply 24 VDC to these contacts and measure the current through them to determine status, such as open or closed.  With so many rodents and creatures around the plant, a cable cut can happen at any time, even if adequate precautions are taken.

Wow the engineering world with your unique design: Design Ideas Submission Guide

A PLC/DCS cannot distinguish between contact open and cable open. A wrong decision may be made by PLC/DCS if a cable open is read as a field contact open, which may still be closed. Solutions currently available commercially are very expensive and therefore not adopted across all industries. Running parallel wires is also done for some critical contacts.

Figure 1’s circuit provides an economical and reliable solution for distinguishing between a cable open and a field contact open. This circuit outputs 4 mA for contact open, 20 mA for contact closed, and 0 mA for cable open. This small module may be placed very close to the field contact. The contact status may be read by an analog input module instead of a digital input module.

Figure 1 The current output (Io) is given to the analog inputs of the DCS/PLC. R7 is the load inside of the analog input module of the DCS/PLC.

How does the circuit work?

1. When the field contact is open:

• Current at pin3 of U1A=0= (Vr/R2) –( Io*R6/(R4+R6))
• Hence, (Vr/R2) = ( Io*R6/(R4+R6)

Vr is the output of the voltage regulator U3, which is 5 V. When substituting the component values shown in Figure 1, Io is approximately 4 mA.

2. When the field contact is closed:

• Current at pin3 of U1A =0= ((Vr/R2) +(Vr/R3))–( Io*R6/(R4+R6))
• Hence, ((Vr/R2) +(Vr/R3)) = ( Io*R6/(R4+R6))

Substituting the component values, Io comes out to around 20 mA. Q1 adjusts the current flowing through R6, which is Io, the output of this circuit. The circuit around Q2 limits the maximum output current to around 30 mA.

The circuit in Figure 1 is for testing. SW1 can be operated to set the field contact to closed or open. The output current (Io) is around 4 mA for open field contact, 20 mA for a closed field contact, and 0 mA for cable open. SW2 is operated to create an open cable condition.

Precise values are not necessary; hence, precision components are not needed. The PLC/DCS needs to be programmed to read around 0 mA, 4 mA, and 20 mA to decode cable open, contact open, and contact closed conditions.

Figure 2 shows the interface module housing the above circuitry. You do not need a separate power supply for this module, as it takes power from PLC/DCS. The connection of this module to the field contact and the analog input of the PLC/DCS is shown here.

Figure 2 The interface module circuit and connection to the field contact. The DCS/PLC’s analog input is also shown. 

A thorough explanation of this circuit can be viewed in the embedded video below. 

 

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

• A 0-20mA source current to 4-20mA loop current converter
• Silly simple precision 0/20mA to 4/20mA converter
• A two-wire temperature transmitter using an RTD sensor

The post Is your PLC/DCS reading the field contacts reliably? appeared first on EDN.

For decades, the semiconductor industry has relied on the relentless pursuit of Moore’s Law—the doubling of transistors on an IC every two years—to deliver ever-increasing performance and functionality. This traditional approach, primarily focused on scaling individual transistors and integrating more components onto a single, monolithic 2D die, has driven innovation across countless industries.

However, as we approach the physical limits of silicon, and the economic realities of advanced process nodes become increasingly prohibitive, the conventional path of monolithic scaling is facing significant roadblocks. Companies are encountering diminishing returns in terms of performance gains, escalating design and manufacturing costs, and challenges in integrating diverse functionalities onto a single chip without compromising yield or power efficiency.

In response to these growing pressures, a fundamental shift is occurring in chip design: the move toward 3D ICs and heterogeneous integration. This paradigm offers a compelling alternative, allowing companies to overcome the limitations of traditional 2D scaling by integrating multiple specialized chiplets—each potentially manufactured on different process technologies and optimized for specific tasks—into a single, advanced package.

Beyond raw performance, the shift to 3D IC offers benefits in design flexibility, manufacturing economics, and form factor by mixing dies manufactured on different process nodes. This modularity enables the use of cutting-edge processes only where absolutely necessary for performance, while leveraging more mature, cost-effective nodes for other functions. This approach also facilitates the creation of smaller, more integrated systems, crucial for devices where space is at a premium.

The unique challenges of advanced packaging

The shift to 3D IC advanced packaging isn’t without its complexities. Heterogeneous integration introduces a new set of design challenges that traditional monolithic approaches simply didn’t encounter. Existing design tools and methodologies are insufficient for the scale and complexity of heterogeneous integration.

With 3D IC design now featuring hundreds of thousands to millions of connections, it’s impractical to use manual methods like spreadsheets to manage the intricate connectivity and interactions between 3D layers.

3D IC designers also face the daunting task of managing a myriad of diverse IP and data formats. Source data for connectivity is supplied in a multitude of formats, including CSV files, LEF/DEF, GDS, Verilog RTL, and plain text files.

Integrating multi-vendor chiplets exacerbates the need for standardized, machine-readable design-models to ensure operability across different EDA tool design workflows. Furthermore, 3D IC designs typically include multiple dies from different foundries and processes, increasing the risk of failure and making them harder to identify and fix.

Because data is often dynamic, with updates received throughout the design process, incorporating new versions of design IP threatens to obliterate existing data, especially when IC and package designers work concurrently. So, designers must be able to accept input from various stakeholders—often designing their content concurrently—to create a design that is both electrically and physically correct.

Ensuring the integrity and functionality of these complex systems demands comprehensive system-level verification, not individual component checks. To truly harness the immense power of heterogeneous integration and confidently navigate these multifaceted challenges, a robust, systematic, and proven framework is not just beneficial—it’s foundational. Otherwise, without a clear roadmap, design teams risk costly iterations, delayed time-to-market, and sub-optimal product performance.

System technology co-optimization: The key to efficient 3D IC design

System technology co-optimization (STCO) is exactly that foundational framework: an advanced, holistic methodology that elevates optimization beyond the considerations of a single die. Instead of narrowly tuning devices at the wafer or chip level—a practice known as device technology co-optimization (DTCO)—STCO allows for the optimization of power, performance, area, cost, and reliability across various components as a unified whole, including silicon, packages, interposers, PCBs, and even mechanical components.

Thus, STCO provides the system-centric framework needed for organizations to stay ahead of the curve in 3D IC design, maximizing value, minimizing risk, and unlocking new levels of competitive differentiation.

STCO breaks down silos that historically separated silicon, package, and board design, and it leverages system-level analysis to guide critical decisions—such as chiplet partitioning, placement, interconnect planning, and assembly verification—early in the design flow. This integrated approach not only reveals downstream issues much sooner but also enables “shift-left” validation and optimization, preventing costly respins and delays.

The strategic benefits of STCO are profound for organizations embracing 3D IC design. Companies can realize shorter design cycles with fewer iterations and handoffs, thanks to continuous verification and ongoing feedback between domains.

Cross-functional teams—from system architects to packaging, DFT, and manufacturing engineers—can observe interdependencies and work together to resolve them proactively. This leads to faster time-to-market, improved first-pass yield, and the ability to confidently deliver innovative, heterogeneous products that meet aggressive performance requirements.

Mastering heterogeneous integration: Your expert guide

This is precisely where the Heterogeneous Integration eBook series becomes a handy guide. This eBook series doesn’t just describe the challenges, it provides a comprehensive, actionable methodology to overcome them.

This robust 10-step methodology for heterogeneous integration, formulated by author of this article, guides designers through the entire process: from the initial creation of the 3D digital twin and system-level planning to detailed design optimization, rigorous verification, and final sign-off. By following this methodology, designers are ensured a streamlined and predictable path to robust advanced package development.

Designers gain expert insights into building a complete digital model, optimizing physical layouts, ensuring robust verification, and preparing designs for successful manufacturing. The series is structured into four eBooks, each focusing on a critical stage of the heterogeneous integration journey—from initial 3D Digital Twin Creation and Assembly Floorplanning, through Scenario Completion, and finally to the crucial Signoff phase—empowering design teams with the knowledge and best practices to confidently lead the next wave of chip innovation.

If you’re ready to move beyond outdated methodologies and truly unlock the power of 3D IC and heterogeneous integration, now is the time to act. The Heterogeneous Integration eBook Series offers not just theory, but a proven framework to help conquer the formidable challenges of advanced packaging.

Don’t let complexity stand in the way—arm yourself with strategies for system-level optimization, cross-domain collaboration, and predictable first-pass success.

Keith Felton is marketing manager for Xpedition IC packaging solutions at Siemens EDA. Working extensively in IC package design since the late 1980s, Keith drove the launch of the industry’s first dedicated system-in-package design solution in the early 2000s and led the team that launched Siemens OSAT Alliance program.

Special Section: Chiplets Design

• What the special section on chiplets design has to offer
• Chiplet innovation isn’t waiting for perfect standards
• Scoping out the chiplet-based design flow

The post Demystifying 3D ICs: A practical framework for heterogeneous integration appeared first on EDN.

When a bathroom scale gives you multiple different weight-measurement results from consecutive usage attempts, is it cheating if you pick the lowest outcome of the lot?

Two years ago (with publication following a few months later), I took apart my wife’s fancy bathroom scale, which measured not only weight but also body mass index and fat percentage:

but whose LCD had gone AWOL and had subsequently been replaced by a simpler successor. Speaking of simple, this time we’ll look at the insides of my first digital bathroom scale, which replaced a traditional mechanical forebear. It’s Innotech’s model ID-767, the black-colored variant to be exact, which I’d bought on sale for $14.99 from Amazon in spring 2018.

Simpler vs. better

Stock images to start:

No, I didn’t keep mine next to the bed:

Hey loser, don’t you want to be a weight “losser” too?

Consistent inconsistency

About those “error-free readings within 0.2 lb” and “accurately weighs up to 400 lb” claims…

There was much to like about the Innotech model 767. It was svelte and light, with long battery life. It responded quickly when I stepped on it. And I liked its looks, too. Accuracy, on the other hand, was not its strong suite. I very well might have had a bad unit. But if I stepped on it, read the display, then stepped off and repeated the procedure, my second result would be consistently inconsistent, varying from the first by several pounds (albeit always down). And I never knew which reading to believe. The saying “you get what you pay for” perhaps applies?

And then it decided to take a spontaneous swan dive off the counter (where I’d placed it while cleaning the bathroom one day) to the tile floor below, resulting in my not liking its looks as much as before:

You’ll have to trust me when I tell you that its measurement inconsistency predated the dent!

So, I decided to retire it; more accurately, replace it (meh):

and turn it into a teardown candidate.

Incriminating reflections

Here are some overview shots to start. I have no idea who that is reflected in the first one…and speaking of weight, I’d also appreciate no snide comments about that poor person’s bulbous soft waistline, please:

The short URL printed on this sticker, as-usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes, is presumably intended to redirect here but no longer works, at least when I tried it:

This switch, when repeatedly pressed, toggles between the “3 weight units” featured in one of the earlier-seen stock photos: pounds, kilograms and rarely-seen stones:

A widely available AAA triple-battery power source (my kitchen scale, conversely, takes CR2032 coin cells, I was reminded the other night when I replaced one of the pair) is a nice touch:

Time to dive inside. Underneath each of the rubber “feet” is, to the “4 weighing sensors” highlight in one of the stock images, a strain gauge load cell. I discussed them in detail back in July 2024 so I’ll spare you the repetitive prose; check out my earlier teardown for all the details.

It’s delightfully wiggly ( and yes, admittedly, I’m easily amused):

But underneath…nope, no screw heads:

So, I redirected my attention to the scale’s sides, a decision which ended up leading to success:

Voilà:

Minimalist construction

Boring part first; here’s the inside of the lower half of the scale:

Next, the good stuff:

The first things you probably noticed were the four load cells in the corners (or maybe you saw the display-plus-PCB, in which case, please stand by; your patience is appreciated). Here they are in clockwise order, starting with the one in the upper left (upper right when the scale is in its normal usage orientation):

Here’s the first one again, being removed:

and now flipped upside down (the strain gauge structure is presumably underneath the glue):

Now for the stuff in the center (see, your patience was quickly rewarded!), the PCB, with this side showing nothing notable save for the weight-unit toggle switch:

and the next-door LCD:

Remove a few screws, and they’re free!

Now flip both 180°:

Dominating the landscape on this side of the PCB is…a blob, unfortunately obscuring the identity of the control chip. Generally speaking, considering the price tag therefore the bill-of-materials cost constraints, this design is impressively sparse in response:

The backside of the display backlight strives to redirect the aggregate glow toward the front:

where it’s further diffused by another peel-away-able layer:

Here’s the LCD itself:

As you may have already noticed, a red/black two-wire pair within the broader wiring harness powers the backlight. What about power (not to mention control) between the PCB and the LCD? That’s handled by an elastomeric strip with multiple embedded conductors, pressing against the PCB’s counterparts, an approach which we’ve seen plenty of times before:

Weighing in

For grins, in closing, I decided to put it back together and see if it still worked. Success!

Booting:

And ready and waiting to deliver additional impermanent results:

That’s all I’ve got for you today! As always, please share your thoughts in the comments.

—Brian Dipert is the Principal at Sierra Media and a former technical editor at EDN Magazine, where he still regularly contributes as a freelancer.

Related Content

• Dissecting a feature-enhanced digital bathroom scale
• Shipping Scale Converted from Bathroom Scale
• What good is 17.24 bits of flicker-free res?

The post A scale that tells inconsistent-weight tales appeared first on EDN.

We’ve come to expect the U.S.-based global positioning system (GPS) to be available and ubiquitous for the countless military, commercial, and consumer applications dependent on it. Its diverse uses represent a huge leap from its original military-centric objective for determining an object’s precise location (positioning), chart its path to a destination (navigation), and manage its movement along that path (guidance)—usually summarized as PNG.

Applications that were not even conceived, let alone doable, are now enabled by tiny GPS ICs and systems that provide amazingly accurate and precise results—you can make your own list here.

If you want some insight into the people who made GPS happen despite severe technical and bureaucratic obstacles, check out Pinpoint: How GPS Is Changing Technology, Culture, and Our Minds by Greg Milner. Though somewhat dated now in its discussion of social implications, this fascinating book from 2016 tells the story of GPS from its conceptual origins as a bomb guidance system to its presence in almost everything we do.

Despite the sense that GPS is everywhere, the reality is that it was never the situation. Underwater, tunnels, indoor sites, and similar RF-blocked locations simply can’t receive enough of the relatively weak satellite signals to provide a viable result.

Now, we’re seeing many more situations where GPS signals are also being “denied” due to deliberate interference or spoofed via false signals by players with various motives. Some of the consequences are modest (lost dogs can’t be found), but others have more serious implications.

One possible solution is to increase the power of the transmitted signals, but that’s technically difficult and won’t happen for years even if and when it does—and doing so will still not help in many of these cases.

Alternatives to GPS

There’s a significant amount of research and product development toward devising ways to provide PNG using non-GPS, non-RF techniques driven by sensors for which jamming or signal access is not an issue. All of them require a considerable amount of computation to make sense of the sensed signals and transform data into results; none of them provide the performance of a GPS-based system—at least not yet. Much of the R&D work is being done by startups and innovators, in addition to traditional sensor vendors.

Among the non-GPS possibilities are:

• Inertial sensing

This is not new, of course, and has been used for decades, beginning with gyroscopes and accelerometers. Both sensors are now reduced to small, low-power MEMS devices that are orders of magnitude smaller, lighter, and lower-power than their electromechanical predecessors of just a few decades ago and even compared to the laser and fiber-optic versions that leverage the Sagnac effect and interferometry. Still, their accuracy is not as good as a high-end GPS system, but it’s improving.

For example, ANELLO Photonics has developed a silicon photonics optical gyroscope—dubbed SiPhOG—that uses an on-chip waveguide manufacturing process, integrated with a patented silicon photonic integrated circuit (Figure 1). Together, they claim these offer fiber-optic gyro performance with a standard silicon manufacturing process.

Figure 1 This silicon photonics optical gyroscope uses an on-chip waveguide manufacturing process that is integrated with a patented silicon photonic IC. Source: ANELLO Photonics

• Magnetic sensors

The Earth’s magnetic field is pervasive, ubiquitous, and unjammable. It’s also uneven, with highly localized variations due to differences in the Earth’s outer-crust and under-crust layers as well as deeper causes (literally) from flows of conducting material within the Earth (Figure 2).

Figure 2 This geomagnetic map of part of the Northern hemisphere is a starting point for more detailed, higher-resolution images and variations, and changes that must be captured for effective magnetic navigation. Source: Geomag

Using supersensitive quantum-based magnetic sensors based on optically pumped, cesium-based, split-beam scalar magnetometers, which have an absolute accuracy between one and three nanoteslas, it’s possible to read that field with high precision. The Earth’s core field has values ranging from 25 to 65 microtesla (that’s 0.25 to 0.65 gauss) at the surface while magnetic anomaly field of interest typically varies by just hundreds of nanotesla.

The readings are then matched to pre-existing maps of Earth’s field. This scheme has the disadvantage of not being very accurate compared to GPS, partially because the Earth’s magnetic field is not static and matching maps need constant updating.

Despite these challenges, companies such as SandboxAQ have developed a navigation technology (AQNav) that leverages proprietary large quantitative models (LQMs) and powerful quantum sensors to make use of the Earth’s crustal magnetic field. By combining high-sensitivity magnetometers with AI algorithms to identify unique magnetic patterns and locate position in real time, it’s possible to determine position in that field. The sensing is entirely passive, so users remain undetected.

• Visual matching

This uses a simple concept of matching what a camera sees to the verified landmarks on a map. Visual terrain-following has been used for decades in cruise missiles which follow a precise terrain-image pattern. Orders-of-magnitude improvements in imaging quality and the associated algorithms needed to process and match the observed image to the map now make this technology even more precise.

One vendor pursuing this approach is Vermeer Corp. Their system uses between one and four electro-optical/infrared camera feeds simultaneously to map real-time video to a locally stored 2.5D or 3D map database to generate an accurate location signal.

• Celestial navigation

This classic approach to navigation now uses modern, automated versions of the transit, celestial charts and precise clocks, aided by computerized calculations. This is a case of “back to the future” but in a new form and implementation.

• E-LORAN

LOng-RAnge Navigation was a hyperbolic radio navigation system developed by the United States during World War II. The third iteration, LORAN-C, was initiated in the late 1960s, but the stations and system were decommissioned in the 1990s due to the availability and performance of GPS.

It uses the differences in timing of received signals from multiple high-power transmitters in the 100-kHz band (yes, that’s kilohertz) to developed positioning information.

Enhanced LORAN is a standard which builds on the now obsolete LORAN system by putting more information into the modulation of the carrier as well as adding a data channel. Like LORAN, E-LORAN offers some benefits such as near-impossibility of jamming and spoofing, but it also requires many high-power transmitters and many of these need to be in inhospitable or remote locations which are difficult to support (Figure 3).

Figure 3 Like its predecessor LORAN, the enhanced LORAN system will require an extensive physical infrastructure located around the world. Source: UrsaNav

While E-LORAN proponents are eternally hopeful, the project has had difficulty getting traction and support due to technical challenges (primarily at the transmitter side), very high up-front infrastructure costs, and best-case accuracy of about 50 to 100 meters (although there are proposed ways to improve that number).

The realities of dealing with a GPS-unavailable world

Many of these alternatives are being enabled by advances in quantum-based sensors. Some may even require supercooled arrangements with all the obvious downsides of that requirement. Each of them offers the virtue of not being jammable or denied.

At the same time, none offers the amazing accuracy and simplicity of GPS for the user. No single technology offers anything close to GPS. A viable alternative, even with reduced accuracy, will require advances in sensors and gigabytes of support data such as maps. Any GPS alternative will also require tight fusion and merging of unrelated sensor technologies and outputs, huge datasets, and extensive use of AI and machine learning to create useful results.

It will be fascinating to see which one of these, if any, takes a dominant role in non-GPS settings, or will it be a balanced fusion? Perhaps some unexpected physical phenomenon will come from behind, as has happened so often in the past. As they say, “predictions are very hard to make, especially about the future.”

Related Content

• When your sensors mislead you
• Sensors Without Wires, But Not “Wireless”
• Navigating without GPS requires advanced sensors, intensive analog
• Sophisticated Sensors, Extreme Conditioning, Advanced Algorithms Yield Amazing Geolocation Results

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It was with humble spirit and a good dose of Mea Culpa that a semiconductor company, from whom some very large-scale digital large-scale integration (LSI) chips were purchased, had a problem (later corrected, thank goodness) in that their chips would malfunction when powering up if their +5V rail voltage rose too slowly as the system was being turned on.

The vendor’s recommendation was to apply a 0 V (off) to +5 V (on) rail voltage with a steeper rise time (< 45 ms) than our power supply could deliver. We decided that we needed a switching arrangement that would operate as follows in Figure 1.

Figure 1 Providing a steep +5-V rail voltage rise time. 

One problem with making something like this was that the input voltage could indeed rise very slowly through ½ volt to 1 volt to 2 volts, and so forth, which were voltage levels that were well below specification limits for any voltage monitoring IC we could find.

The resulting operations were erratic and unpredictable at arbitrarily low input voltages. This did not help the LSI situation even one little bit. (Yes, I am aware of the pun.)

Remedy was achieved using the following circuit in Figure 2. 

Figure 2 Rail voltage switch, four loads.

The result obtained was as follows:

Figure 3 Rail voltage delay and rise time speedup.

This worked predictably down to arbitrarily low power supply voltages because there would be no response whatsoever, as long as the TLV431 didn’t see some voltage high enough to get itself conducting.

When the power supply voltage did get high enough to turn on the TLV431 at the time we’re calling “t1”, the power MOSFETs would turn on, and there would be a downward but very short-duration transient voltage drop from the power supply, which would be recovered from very quickly. The rail voltage thus presented to the LSI chips had a sufficiently quick rise time of its own to make those chips happy.

The end result made a bunch of human beings happy, too.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Silly Simple Supply Sequencing
• Power-Supply Sequencing for Low-Voltage Processors
• Shunt Regulator Eases Power-Supply Start-Up Woes
• Use a TL431 Shunt Regulator to Limit High AC Input Voltage
• Fundamentals of Designing with MOSFET Power Switches

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Part 1 of this article series on gallium nitride (GaN) fundamentals described crystal structures and the formation of the two-dimensional electron gas (2DEG), along with material figures of merit and the transition from depletion-mode to enhancement-mode GaN HEMTs.

Part 2 will outline hybrid structures and the RDS(on)  penalty, as well as provide further details on GaN HEMTs and substrate choices for GaN. It will also make the case for the path to monolithic integration while showing how ohmic contacts, metallization, and packaging advantages are facilitating this design roadmap.

Figure 1 Schematic of low-voltage enhancement-mode silicon MOSFET is shown in series with a depletion-mode GaN HEMT: Cascode circuit (a) and enable/direct-drive circuit (b). Source: Efficient Power Conversion (EPC)

An alternative to monolithic enhancement-mode GaN transistors is the hybrid cascode configuration, pairing a low-voltage enhancement-mode silicon MOSFET with a high-voltage depletion-mode GaN HEMT in series. Figure 1 above illustrates two variants.

The cascode configuration, in particular, is highlighted as a pragmatic intermediate solution: a low-voltage enhancement-mode Si MOSFET is connected in series with a high-voltage d-mode GaN HEMT. The MOSFET gate is the external control terminal; when it turns on, the GaN gate-source is pulled close to zero and the HEMT conducts. When the MOSFET turns off, the GaN gate sees a negative bias through the MOSFET, turning off the high electron mobility transistor (HEMT) and providing normally-off behavior at the system level.

A natural question is how much extra RDS(on) the silicon MOSFET adds to the GaN device. Figure 2 shows a useful plot of the percentage contribution of the MOSFET to total RDS(on) versus the rated voltage of the cascode system. At high voltage, the GaN device dominates, and the MOSFET contribution becomes small.

Figure 2 Percentage RDS(on) contribution from the low-voltage MOSFET in a cascode configuration is shown as a function of the rated breakdown voltage of the composite device. Source: Efficient Power Conversion (EPC)

From this chart, a 600-V cascode device adds only around 3% extra RDS(on) due to the low-voltage MOSFET, because the GaN HEMT’s drift resistance dominates at such high voltage. At lower voltages, the GaN device resistance drops rapidly with VBR, so the MOSFET contribution becomes increasingly significant. For this reason, cascode solutions are practical and attractive for higher voltages (above roughly 200 V), whereas for 100–150 V class devices, monolithic e-mode GaN is generally preferable.

The direct-drive (enable) variant exposes the depletion-mode GaN gate directly to the external driver (typically 0 V on, -12 to -14 V off). The silicon MOSFET serves as a safety “enable” switch, connected to the gate driver’s undervoltage lockout (UVLO). During normal operation, the silicon device remains on and experiences no switching; it only blocks the GaN gate if supply fails. This configuration offers precise control of GaN dynamics but requires bipolar drive capability.

Reverse conduction in HEMT transistors

Reverse conduction behavior is a clear advantage of enhancement-mode GaN HEMTs. The source potential increases in relation to the gate when current is forced from the source to drain while the device is nominally off.

This process continues until the threshold condition for the formation of 2DEG is reached beneath the gate region. The channel now reorganizes and conducts in the opposite direction. Unlike the body diode of a silicon MOSFET, which depends on minority-carrier injection and storage, this is a majority-carrier mechanism. So, there is no stored minority charge and consequently no reverse-recovery penalty.

A positive gate voltage establishes the 2DEG channel during forward conduction, enabling current to move from the drain to the source. When reverse conduction occurs, as it does during a synchronous rectifier’s dead time, current moves from the source to the drain when the drain is at least the threshold voltage lower than the gate.

Conduction is then determined by channel resistance, and the device functions similarly to a low-drop diode. In contrast to silicon MOSFETs, which suffer reverse-recovery losses because of charge storage effects, current almost immediately stops once the reverse bias is eliminated.

Vertical GaN and substrate choices

Instead of using lateral 2DEG transport, vertical GaN transistors employ a conduction path perpendicular to the wafer surface. In a typical structure, p-GaN regions linked to the source extend from the surface toward the drain, and the drain contact is positioned at the bottom of a thick n-GaN drift region. When a negative gate voltage is applied, the n-GaN between the p-regions beneath the gate is depleted, preventing current flow.

The depleted region collapses and electrons move vertically from source to drain when the gate is positively biased. This architecture has the potential to compete with high-voltage SiC devices because it can support breakdown voltages above 1000 V while maintaining quick switching. The sub-650 V market is dominated by lateral GaN, mainly because silicon substrates are more affordable and scalable.

The cost of standard 200-mm silicon wafers is only a few tens of dollars per wafer, which enables direct reuse of established CMOS fabs and high-volume manufacturing, including the potential for monolithic integration of sensing circuits and drivers. Bulk GaN substrates for vertical devices, on the other hand, are still restricted to small diameters (usually ≤150 mm) and cost several hundred to over a thousand dollars per wafer, or tens of dollars per cm². This severely limits cost competitiveness at mid voltages.

From a performance perspective, lateral GaN HEMTs benefit from the creation of a high-density 2DEG, which offers exceptionally high electron mobility and low channel resistance. This translates into excellent light-load efficiency and high-frequency operation, which are essential for applications like DC-DC converters, server power supplies, telecom, and consumer fast chargers.

Vertical architectures, currently dominated by SiC MOSFETs, continue to be the preferred solution for voltages above ~900 V because they provide superior robustness at high electric fields and decouple blocking voltage from lateral device dimensions. While SiC and future vertical GaN aim for high-voltage applications, lateral GaN emphasizes cost-performance optimization over voltage scaling in this regime, solidifying its leadership in the mid-voltage range.

Building a GaN HEMT transistor

Fabrication of a GaN HEMT begins with epitaxial growth of the GaN/AlGaN heterostructure on a foreign substrate. Unlike silicon devices, where the active layer matches the substrate, GaN HEMTs require heteroepitaxy, growing a wurtzite crystal on a substrate with mismatched lattice constant and thermal expansion.

Four substrate materials dominate: bulk GaN, sapphire (Al₂O₃), silicon carbide (SiC), and silicon (Si). Each offers trade-offs in lattice mismatch, thermal expansion coefficient, thermal conductivity, and cost. Silicon (111) orientation substrates have emerged as the commercial workhorse due to their low cost ($1–2 per 200 mm wafer) and compatibility with existing CMOS fabrication infrastructure, despite a 17% lattice mismatch (a_GaN = 3.189 Å vs. a_Si = 3.84 Å) and thermal expansion difference of 3 × 10⁻⁶ K⁻¹.

Heteroepitaxy grows one crystal on a dissimilar substrate. Metal-organic chemical vapor deposition (MOCVD) deposits the GaN/AlGaN layers. The process starts with an AlN seed layer on the substrate to initiate nucleation. An AlGaN buffer layer creates the transition to pure GaN crystal structure. A thick GaN layer forms the semi-insulating base. Finally, a thin AlGaN barrier layer induces strain that forms the 2DEG conduction channel.

Figure 3 illustrates the complete epitaxial stack from substrate to 2DEG interface. For enhancement-mode devices, a p-GaN cap layer grows atop the AlGaN barrier, introducing positive charge to deplete the 2DEG at zero gate bias (Figure 4). This stack enables lateral electron transport parallel to the surface, distinguishing GaN HEMTs from vertical silicon MOSFETs.

Figure 3 The illustration highlights basic steps involved in creating a GaN heteroepitaxial structure: Starting silicon substrate (a), aluminum nitride (AlN) seed layer grown (b), various Al GaN layers grown to transition the lattice from AlN to GaN (c), GaN layer grown (d), and AlGaN barrier layer grown (e). Source: Efficient Power Conversion (EPC)

Figure 4 An additional GaN layer, doped with p-type impurities, can be added to the heteroepitaxy process when producing an enhancement-mode device. Source: Efficient Power Conversion (EPC)

Ohmic contacts and metallization

Source and drain electrodes must form low-resistance ohmic contacts to the 2DEG, penetrating the AlGaN barrier. Multiple metal layers and high-temperature annealing create reliable shunts. The gate electrode sits atop the AlGaN (or p-GaN), modulating the channel via electric field.

Back-end processing adds multilevel copper interconnects with tungsten vias, scaling gate width across thousands of parallel cells. Final passivation (SiNₓ) protects the surface and shapes electric fields to prevent premature breakdown.

Chip-scale packages (BGA and LGA) minimize parasitics, supporting megahertz switching with minimal ringing. Recent advances in QFN (Quad, Flad, No-Lead) have brought packaging alternatives that have minimal compromises in parasitic inductance, resistance, and thermal conductivity.

In either chip-scale of QFN packages, lateral conduction enables bottom-side cooling and ultra-low inductance packaging. Ball grid array (BGA) formats use SnAgCu micro-bumps (150 µm pitch) for 100–650 V devices (1.5 × 1.0 mm² footprint). LGA variants (3.9 × 2.6 mm²) handle 100 V half-bridges at 10 A continuous. Package loop inductance drops below 0.2 nH, supporting dI/dt >2000 A/µs without significant ringing—impossible in wire-bonded discrete packages

The path to monolithic integration

The lateral architecture of GaN HEMTs—where current flows parallel to the surface—eliminates the need for deep vertical vias or trenches, enabling unprecedented levels of monolithic integration. Unlike vertical silicon or SiC devices, multiple passive and signal-level transistors and passive components occupy the same epitaxial plane, with interconnects formed in overlying metal layers. This allows fabrication of complete power stages on a single die smaller than a grain of rice.

Figure 5 A typical process creates solder bars on an enhancement-mode GaN HEMT (not to scale). Source: Efficient Power Conversion (EPC)

Monolithic GaN stages eliminate interconnect parasitics that plague discrete implementations:

• No bond wires: Package inductance <0.2 nH vs. 1–5 nH with discrete multi-chip QFN
• Zero common source and gate loop inductance
• Pin count reduction: 99% fewer external connections vs. discrete half-bridge + drivers

Compared to silicon DrMOS (driver + MOSFET), GaN integration yields:

• 10× lower QG → MHz switching without excessive gate losses
• Zero QRR → no reverse recovery in synchronous rectification
• 25× smaller die area → lower cost at equivalent performance

Maurizio Di Paolo Emilio is director of global marketing communications at Efficient Power Conversion (EPC), where he manages worldwide initiatives to showcase the company’s GaN innovations. He is a prolific technical author of books on GaN, SiC, energy harvesting and data acquisition and control systems, and has extensive experience as editor of technical publications for power electronics, wide bandgap semiconductors, and embedded systems.

Editor’s Note:

The content in this article uses references and technical data from the book GaN Power Devices for Efficient Power Conversion (Fourth Edition) authored by Alex Lidow, Michael de Rooij, John Glaser, Alejandro Pozo Arribas, Shengke Zhang, Marco Palma, David Reusch, Johan Strydom.

Related Content

• SiC vs. GaN: Who wins
• The advantages of Vertical GaN Technology
• A brief history of gallium nitride (GaN) semiconductors
• A new IDM era kickstarts in the gallium nitride (GaN) world
• New GaN Technology Makes Driving GaN-Based HEMTs Easier

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A DC/DC power delivery board from Navitas Semiconductor enables direct conversion from 800 V to 6 V in a single stage. Showcased at NVIDIA GTC 2026, the design eliminates the conventional 48-V intermediate bus converter stage within compute server trays, simplifying power delivery for NVIDIA AI infrastructure.

Using GaNFast power ICs, the board reaches 96.5% peak efficiency at full load with 1-MHz switching and a power density of 2.1 kW/in³. The primary side integrates sixteen 650-V GaNFast FETs in DFN 8×8 packages with dual-side cooling in a stacked full-bridge topology, while center-tapped outputs use 25-V silicon MOSFETs. High-frequency switching enables smaller passives and planar magnetics, increasing power density.

The Navitas power delivery board is about 20% thinner than a mobile phone. Its ultra-low profile allows close placement to the GPU board, minimizing loop inductance to improve transient response and power distribution efficiency.

For more information, contact a Navitas representative or email info@navitassemi.com. A timeline for availability was not provided at the time of this announcement.

Navitas Semiconductor 

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The ST64UWB family of ultra-wideband SoCs from ST provides increased range and processing capability for automotive applications. Backward compatible with IEEE 802.15.4z, the chips also support the emerging IEEE 802.15.4ab UWB standard, enabling device localization and tracking at distances of several hundred meters. Target use cases include hands-free digital keys and high-accuracy vehicle localization.

Enhancements such as multi-millisecond ranging (MMS) and narrow-band assistance (NBA) provide greater operating range and improve link robustness, particularly for devices carried in bags or rear pockets. These features also facilitate close-range direction finding for more accurate interpretation of user position and movement. In addition, IEEE 802.15.4ab strengthens radar mode for more reliable in-vehicle child presence detection.

The ST64UWAB-A100 and ST64UWB-A500 are built on an 18-nm FD-SOI process, increasing link budget by nearly 3 dB versus bulk technologies and boosting range by up to ~50% beyond IEEE 802.15.4ab. Both devices integrate an Arm Cortex-M85 core, while the ST64UWB-A500 adds AI acceleration and DSP capabilities for edge AI-based radar applications. A third device, the ST64UWB-C100, expands the lineup to cover industrial and consumer applications.

The devices are now sampling to leading Tier 1 suppliers and OEMs.

ST64UWB product page 

STMicroelectronics

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Semtech’s 224-Gbps/lane TIAs and drivers power 800G–3.2T transceivers and optical engines for AI/ML clusters, hyperscale data centers, and cloud infrastructure. Compliant with CEI‑224G‑Linear and LPO‑MSA, they support half-retimed (LRO), linear pluggable (LPO), next‑gen (XPO), near‑packaged (NPO), and co‑packaged (CPO) optics.

The 224G TIA family—GN1834L, GN1834DL, and GN1838DL—offers quad- and octal-channel architectures with flexible layouts. On-chip equalization, high linearity, and low noise boost signal integrity for LPO and next-generation linear optics.

The 224G Mach-Zehnder Modulator (MZM) drivers—quad GN1877 and octal GN1887—support SiPho, InP MZM, and TFLN optical transmitters with tunable gain and output swing. A CEI‑224G‑Linear host-side equalizer covers a wide range of host interfaces, from compact NPO/CPO to varied LRO/LPO/XPO trace lengths.

Both the TIA and driver series integrate real-time link monitoring and telemetry, enabling proactive diagnostics to reduce link flapping and improve network reliability.

The GN1834L, GN1834DL, and GN1887 are available now; GN1838DL and GN1877 are expected in April 2026.

For more information, visit Semtech’s optical page.

Semtech

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AOS has introduced two MOSFETs—the 25‑V AONC40212 and 80‑V AONC68816—in 3.3×3.3‑mm source-down DFN packages with double-side cooling. This packaging supports high power density in DC/DC intermediate bus converters and meets the strict thermal demands of AI servers and data centers.

The MOSFETs use an optimized top-clip design on the exposed drain, enabling double-sided thermal transfer to remove heat efficiently. Compared with single-sided devices, this approach reduces thermal stress and heat buildup. The large top clip achieves a low maximum thermal resistance of 0.9 °C/W, enhancing thermal performance in demanding applications.

The AONC40202 and AONC68816 MOSFETs support continuous drain currents of 405 A and 119 A, respectively, at 25 °C, with pulsed currents up to 644 A and 476 A. The devices have maximum on-resistances of 0.7 mΩ for the 25-V part and 4.7 mΩ for the 80-V part, while maintaining junction temperatures up to 175 °C. Bottom-side thermal resistance is 1.1 °C/W for both devices.

Available now with a lead time of 14–16 weeks, the AONC40202 and AONC68816 cost $1.85 and $1.95 each in lots of 1000 units.

Alpha & Omega Semiconductor 

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Infineon’s XDPE1E multiphase PWM buck controllers and TDA49720/12/06 PMBus POL buck regulators streamline voltage regulation in AI data centers, helping customers boost compute performance per rack. With digital control and telemetry-enabled point-of-load regulation, these devices reduce design cycles and accelerate platform bring-up.

Designed for multiprocessor AI platforms and advanced VR inductor topologies, the XDPE1E3G6A and XDPE1E496A digital 3- and 4-loop buck controllers feature configurable phase allocation and fully programmable phase firing order. They support multiple protocols, including PMBus, AVSBus, SVID, and SVI3, ensuring compatibility across processor ecosystems. Digital control features and integrated tools help manage dynamic AI loads, reduce bench time, and improve system robustness.

The TDA49720/12/06 integrated POL buck regulators deliver 6-A, 12-A, and 20-A outputs in 3×3 mm and 3×3.5 mm packages. PMBus telemetry enables reliability monitoring and system optimization, while a proprietary valley current mode constant-on-time control ensures fast transient response, cycle-by-cycle current limiting, and all-MLCC output capacitance compatibility.

More information can be found on Infineon’s digital multiphase controller page and POL voltage regulator page. A timeline for availability was not provided at the time of this announcement.

Infineon Technologies 

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