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Adaptive SoCs in AMD’s Versal RF series integrate direct RF sampling data converters, dedicated DSP hard IP, and AI engines in a single chip. The devices offer wideband-spectrum observability and up to 80 TOPS of digital signal processing performance in a SWaP-optimized design for radar, spectral analysis, and test and measurement applications. They also provide programmable logic and ample memory to create powerful accelerators.

Versal RF SoCs enable wideband spectrum capture and analysis with 14-bit multichannel RF ADCs and RF DACs. These converters support input/output frequencies up to 18 GHz and sampling rates up to 32 Gsamples/s. Select DSP functions, like 4-Gsample/s FFT/iFFT, channelizer, polyphase resampler, and LDPC decoder, run on dedicated hard IP blocks, cutting dynamic power by up to 80% compared to AMD soft logic.

Versal RF silicon samples and evaluation kits are expected in Q4 2025, with production shipments beginning in the first half of 2027.

Versal RF product page 

AMD

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Nexus 2 is Lattice Semiconductor’s next-generation small FPGA platform, featuring improved power efficiency, edge connectivity, and security. Built on a 16-nm FinFET TSMC process, Nexus 2 FPGAs offer 65k to 220k system logic cells in a form factor that is up to 5 times smaller than similar class devices.

According to Lattice, Nexus 2 FPGAs deliver up to 3 times lower power consumption and up to 10 times greater energy efficiency for edge sensor monitoring compared to competing devices in the same class. Fast connectivity is enabled by a multiprotocol 16-Gbps SERDES, PCIe Gen 4 controller, and MIPI D-PHY/C-PHY interfaces operating at speeds up to 7.98 Gbps.

Nexus 2 FPGAs support a broad range of security functions, including 256-bit AES-GCM encryption and SHA3-512 hashing, compliant with FIPS 140-3 Level 2 standards. The devices also feature crypto agility, anti-tamper protection, and post-quantum readiness.

The Nexus 2 platform is designed to allow rapid development of new device families based on a single platform. The first of these, the Certus-N2 family of general-purpose small FPGAs, is now available for sampling.

Nexus 2 product page  

Certus-N2 product page 

Lattice Semiconductor 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Lattice launches small-size FPGA platform appeared first on EDN.

Joining Synaptics’ Veros IoT connectivity family is the SYN20708, a dual-core SoC that supports Bluetooth 5.4 and IEEE 802.15.4. The Matter-compliant chip enables Bluetooth Classic, Bluetooth Low Energy (BLE), Zigbee, and Thread protocols to operate concurrently on both cores, allowing simultaneous connections to multiple endpoints in heterogeneous network environments.

The SYN20708 employs a modular software architecture that simplifies development for systems requiring low latency, extended range, low power, and interoperability. It can be used in a range of consumer, automotive, healthcare, and industrial applications, including dedicated home hubs and automotive infotainment systems.

The SoC features dual-antenna maximum ratio combining (MRC) and transmit beamforming (TxBF) to enhance signal quality and double communication range. It is Bluetooth 5.4 certified and Bluetooth 6.0 compliant, enabling channel sounding, Bluetooth Classic Audio, and LE Audio. The SoC supports IEEE 802.15.4 (OpenThread and ZBOSS) up to Version 2, along with BLE Long Range, angle of departure (AoD), and angle of arrival (AoA) capabilities. Synaptics’ proprietary CoEX technology improves coexistence in the 2.4-GHz band.

The SYN20708 wireless SoC is available now.

SYN20708 product page

Synaptics

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Multiprotocol wireless SoC is Matter-compliant appeared first on EDN.

A 4-phase PWM controller from AOS, paired with industry-standard DrMOS power stages, boosts system efficiency for NVIDIA Blackwell GPU platforms. The AOZ73004CQI, which powers AI servers and graphics cards based on the Blackwell architecture, is fully compliant with the Open Voltage Regulator (OpenVReg) OVR4-22 standard.

The AOZ73004CQI’s cycle-by-cycle current limit aligns with the GPU’s overcurrent protection requirements, enabling safe power throttling to maximize performance. It features an external reference input and PWMVID interface for dynamic output voltage control. By reducing ripple effects, the controller achieves PWMVID slew rates of up to 30 mV/µs—a threefold increase over typical rates. Additionally, deep-off and shallow-off power states minimize power consumption.

The AOZ73004CQI with 4-phase PWM is not limited to using four DrMOS power stages as standard. AOS’s proprietary DrMOS design allows precise turn-on timing, enabling one PWM to drive two or three DrMOS devices. By doubling or tripling DrMOS, designers can create a high-power, multiphase system with up to 12 power stages.

Prices for the AOZ73004CQI buck controller start at $1.20 each in lots of 1000 units.

AOZ73004CQI product page 

Alpha & Omega Semiconductor 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Multiphase PWM controller powers Blackwell GPUs appeared first on EDN.

With 36 programmable LED current channels, the AL5887Q from Diodes drives up to 12 RGB configurations or 36 individual LEDs. The automotive-compliant linear driver provides a hardware-selectable I2C or SPI digital interface, along with an internal 12-bit PWM for precise color and brightness control. Designers can create dynamic lighting patterns and rich color depths for both interior and exterior lamps.

An external resistor sets the output current for all 36 channels, with each channel’s current digitally configurable up to 70 mA without the need for paralleling. An automatic power-saving mode reduces current to 15 µA, and a quiescent shutdown mode cuts it to 1 µA when all LEDs are off for more than 30 ms, minimizing energy draw from the car’s battery.

The AL5887Q includes multiple protection features, such as an open-drain fault pin with diagnostic fault registers and individual fault mask registers. It also provides overtemperature protection with a pre-OTP warning.

The AEC-Q100 qualified AL5887Q driver costs $1.13 each in lots of 1000 units.

AL5887Q product page

Diodes

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Multichannel driver enhances automotive lighting appeared first on EDN.

The ubiquitous variable resistance circuit network shown in Figure 1…

Figure 1 Classic adjustable resistance; Rmax = Rs + Rr; Rmin = Rs.

…can be accurately synthesized in solid state circuitry built around a digital potentiometer (Dpot) as discussed in “Synthesize precision Dpot resistances that aren’t in the catalog.” Its accuracy holds up despite pot resistance element tolerance and is independent of wiper resistance. See Figure 2 for the circuit.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 2 Synthetic Dpot evades problems by using FET shunt, precision fixed resistors, and op-amp; Rab > Rmax; Rp = (Rmax-1 – Rab-1)-1; Rs = (Rmin-1 – Rab-1 – Rp-1)-1.

But a sticky question remains: What if the polarity of the Va – Vb differential is subject to reversal? Figure 1 can of course accommodate this without a second thought, but it’s a killer for Figure 2.

A simple—but unfortunately unworkable—solution is shown in Figure 3.

Figure 3 Simply paralleling complementary N and P channel MOSFETs might look good but won’t work beyond a few hundred mV of |Va – Vb|.

The problem arises of course from the parasitic body diodes common to MOSFETs, which conduct and bypass the transistor if the reverse polarity source-drain differential is ever more than a few tenths of a volt.

Figure 4 shows the simplest (not very simple) solution I’ve been able to come up with.

Figure 4 Two complementary anti-series FET pairs connected in parallel allow bipolar operation.

Inspection of Figure 4 shows a couple extra FETs have been added in anti-series with the paralleled complementary transistors of Figure 3, together with polarity comparator amplifier A2. A2 enables the Q1/Q2 pair for (Va – Vb) > 0, Q3/Q4 for (Va – Vb) < 0. 

The TLV9152 with its 4.5-MHz gain-bandwidth, 400-ns overload recovery, and 21-V/µs slew rate is a fairly good choice for this application. Nevertheless, significant crossover distortion can be expected to creep in for low signal amplitudes and frequencies above 10 kHz or so.

Design equations are unchanged from Figure 2.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

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• Dpot pseudolog + log lookup table = actual logarithmic gain
• Digital potentiometer simulates log taper to accurately set gain
• Op-amp wipes out DPOT wiper resistance
• Adjust op-amp gain from -30 dB to +60 dB with one linear pot

The post Synthesize precision bipolar Dpot rheostats appeared first on EDN.

All buck converters need capacitors on the input. Actually, in a perfect world, if the supply had zero output impedance and infinite current capacity and the tracks had zero resistance or inductance, you wouldn’t need input capacitors. But since this is infinitesimally unlikely, it’s best to assume that your buck converter will need input capacitors.

Input capacitors store the charge that supplies the current pulse when the high-side switch turns on; they are recharged by the input supply when the high-side switch is off (Figure 1).

Figure 1 The above diagram shows simplified current waveform in the input capacitor current during the buck DC/DC switching cycle, assuming infinite output inductance. Source: Texas Instruments

The switching action of the buck converter charges and discharges the input capacitor, causing the voltage across it to rise and fall. This voltage change represents the input voltage ripple of the converter at the switching frequency. The input capacitor filters the input current pulses to minimize the ripple on the input supply voltage.

The amount of capacitance governs the voltage ripple, so the capacitor must be rated to withstand the root-mean-square (RMS) current ripple. The RMS current calculation assumes the presence of only one input capacitor, with no equivalent series resistance (ESR) or equivalent series inductance (ESL). The finite output inductance accounts for the current ripple on the input side, as shown in Figure 2.

Figure 2 Input capacitor ripple current and calculated RMS current are displayed by TI’s Power Stage Designer software. Source: Texas Instruments

Current sharing between parallel input capacitors

Most practical implementations use multiple input capacitors in parallel to provide the required capacitance. These capacitors often include a small-value, high-frequency multilayer ceramic capacitor (MLCC), for example, 100 nF. One or more larger MLCCs (10 µF or 22 µF) are used, and sometimes accompany a polarized large-value bulk capacitor (100 µF).

Each capacitor is performing similar yet different functions; the high-frequency MLCC decouples fast transient currents caused by the MOSFET switching process in DC/DC converter. The larger MLCCs source the current pulses to the converter at the switching frequency and its harmonics. The bulk capacitor supplies the current required to respond to output load transients when the impedance of the input source means that it cannot respond as quickly.

Where used, a large bulk capacitor has a significant ESR, which provides some damping of the input filter’s Q factor. Depending on its equivalent impedance at the switching frequency relative to the ceramic capacitors, the capacitor may also have significant RMS current at the switching frequency.

The datasheet of a bulk capacitor specifies a maximum RMS current rating to prevent self-heating and ensure that its lifetime is not degraded. The MLCCs have a much smaller ESR and correspondingly much less self-heating because of the RMS current. Even so, circuit designers sometimes overlook the maximum RMS current specified in ceramic capacitor datasheets. Therefore, it is important to understand the RMS currents in each of the individual input capacitors.

If you are using multiple larger MLCCs, you can combine them and enter the equivalent capacitance into the current-sharing calculator for calculating RMS currents in parallel input capacitors. The calculation of RMS current considers the fundamental frequency only. Nonetheless, this calculation tool is a useful refinement of the single input capacitor RMS current calculation.

Consider an application where VIN = 9 V, VOUT = 3 V, IOUT = 12.4 A, fSW = 440 kHz and L = 1 µH. The three parallel input capacitors could then be 100 nF (MLCC), ESR = 30 mΩ, ESL = 0.5 nH; 10 µF (MLCC), ESR = 2 mΩ, ESL = 2 nH; and 100 µF (bulk), ESR = 25 mΩ, ESL = 5 nH. The ESL here includes the PCB track inductance.

Figure 3 shows the capacitor current-sharing calculator results for this example. The 100-nF capacitor draws a low RMS current of 40 mA as expected. The larger MLCC and bulk capacitors divide their RMS currents more evenly at 4.77 A and 5.42 A, respectively.

Figure 3 Output is shown from TI’s Power Stage Designer capacitor current-sharing calculator. Source: Texas Instruments

In reality, the actual capacitance of the 10-µF MLCC is somewhat lower because of the voltage applied. For example, a 10-µF, 25-V X7R MLCC in an 0805 package might only provide 30% of its rated capacitance when biased at 12 V, in which case the large bulk capacitor’s current is 6.38 A, which may exceed its RMS rating.

The solution is to use a larger capacitor package size and parallel multiple capacitors. For example, a 10-µF, 25-V X7R MLCC in a 1210 package retains 80% of its rated capacitance when biased at 12 V. Three of these capacitors have a total effective value of 24 µF when used for C2 in the capacitor current-sharing calculator.

Using these capacitors in parallel reduces the RMS current in the large bulk capacitor to 3.07 A, which is more manageable. Placing the three 10-µF MLCCs in parallel also reduces the overall ESR and ESL of the C2 branch by a factor of three.

The low capacitance of the 100-nF MLCC and its relatively high ESR mean that this capacitor plays little part in sourcing the current at the switching frequency and its lower-order harmonics. The function of this capacitor is to decouple nanosecond current transients seen at the switching instants of the DC/DC converter’s MOSFETs. Designers often refer to it as the high-frequency capacitor.

In order to be effective, it’s essential to place the high-frequency capacitor as close as possible to the input voltage and ground terminals of the regulator using the shortest (lowest inductance) PCB routing possible. Otherwise, the parasitic inductance of the tracks will prevent this high-frequency capacitor from decoupling the high-frequency harmonics of the switching frequency.

It’s also important to use as small a package as possible to minimize the ESL of the capacitor. A high-frequency capacitor with a value of <100 nF can be beneficial for decoupling at a specific frequency when compared to its ESR and impedance curve. A smaller capacitor will have a higher self-resonance frequency.

Similarly, always place the larger MLCCs as close as possible to the converter to minimize their parasitic track inductance and maximize their effectiveness at the switching frequency and its harmonics.

Figure 3 also shows that, although the overall RMS current in the overall input capacitor (were it a single equivalent capacitor) is 6 A, the sum of RMS currents in the C1, C2 and C3 branches is >6 A and does not follow Kirchhoff’s current law. The law only applies to the instantaneous values, or to the complex addition of the time-varying and phase-shifted currents.

Using PSpice for TI or TINA-TI software

Designers who need more than three input capacitor branches for their applications can use PSpice for TI simulation software or TINA-TI software. These tools enable more complex RMS current calculations, including harmonics alongside the fundamental switching frequency and the use of a more sophisticated model for the capacitor, which captures the frequency-dependent nature of the ESR.

TINA-TI software can compute the RMS current in each capacitor branch in the following way: run the simulation, click the desired current waveform to select it, and from the Process menu option in the waveform window, select Averages. TINA-TI software uses a numerical integration over the start and end display times of the simulation to calculate the RMS current.

Figure 4 shows the simulation view. For clarity in this example, we omitted the 100-nF capacitor because its current is very low and contributes to ringing at the switching edges. The Power Stage Designer software analysis of the total input capacitor current waveform for the converter calculates the input current (IIN), which is 6 ARMS, the same value as for Figure 2.

Figure 4 Output from TINA-TI software shows the capacitor branch current waveforms and calculated RMS current in C2. Source: Texas Instruments

The capacitor current waveforms in each branch are quite different compared to the idealized trapezoidal waveform that ignores their ESR and ESL. This difference has implications for DC/DC converters such as the TI LM60440, which has two parallel voltage input (VIN) and ground (GND) pins.

The mirror-image pin configuration enables designers to connect two identical parallel input loops, meaning that they can place double input capacitance (both high frequency and bulk) in parallel close to the two pairs of power input (PVIN) and power ground (PGND) pins. The two parallel current loops also halve the effective parasitic inductance.

In addition, the two mirrored-input current loops have equal and opposite magnetic fields, allowing some H-field cancellation that further reduces the parasitic inductance (Figure 5). Figure 4 suggests that if you don’t carefully match the parallel loops in capacitor values, ESR, ESL and layout for equal parasitic impedances, then the current in the parallel capacitor paths can differ significantly.

Figure 5 Parallel input and output loops are shown in a symmetrical “butterfly” layout. Source: Texas Instruments

Software tool use considerations

To correctly specify input capacitors for buck DC/DC converters, you must know the RMS currents in the capacitors. You can estimate the currents from equations, or more simply by using software tools like TI’s Power Stage Designer. You can also use this tool to estimate the currents in up to three parallel input capacitor branches, as commonly used in practical converter designs.

More complex simulation packages such as TINA-TI software or PSpice for TI can compute the currents, including harmonics and fundamental frequencies. These tools can also model frequency-dependent parasitic impedance and many more parallel branches, illustrating the importance of matching the input capacitor combinations in mirrored input butterfly layouts.

Dr. Dan Tooth is Member of Group Technical Staff at Texas Instruments. He joined TI in 2007 and has been a field application engineer for over 17 years. He is responsible for supporting TI’s analog and power product portfolio in ADAS, EV and diverse industrial applications.

Dr. Jim Perkins Senior Member of Technical Staff at Texas Instruments. He joined TI in 2011 as part of the acquisition of National Semiconductor and has been a field application engineer for over 25 years. He is now mainly responsible for supporting TI’s analog and power product portfolio in grid infrastructure applications such as EV charging and smart metering.

Related Content

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The post Understanding currents in DC/DC buck converter input capacitors appeared first on EDN.

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Penn State is to receive $3m from the US Defense Advanced Research Projects Agency (DARPA) as part of a larger grant awarded to defense, aerospace and technology company Northrop Grumman. The joint project aims to develop a novel method for integrating gallium nitride (GaN) with silicon substrates, since GaN provides superior performance and faster switching speeds for power-intensive applications while silicon offers scalability and affordability. This hybrid approach can lead to more efficient power electronics with lower production costs, suiting high-demand applications like electric vehicles, power electronics and data centers, where efficiency and durability are critical...

Silicon photonics-based chip-to-chip optical connectivity firm Ayar Labs of San Jose, CA, USA has secured $155m in a Series D funding round led by Advent Global Opportunities and Light Street Capital. Other new strategic and financial investors participating in the round include 3M Ventures and Autopilot...

NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — says that NYSE Regulation has sent it a warning letter, as provided under Section 1009(a) of the NYSE American LLC Company Guide, describing violations by the firm of Sections 301 and 713 of the Company Guide...

ROHM has announced the adoption of its PMICs in power reference designs focused on the next-generation cockpit SoCs ‘Dolphin3’ (REF67003) and ‘Dolphin5’ (REF67005) by Telechips, a major fabless semiconductor manufacturer for automotive applications headquartered in Pangyo, South Korea. Intended for use inside the cockpits of European automakers, these designs are scheduled for mass production in 2025.

ROHM and Telechips have been engaged in technical exchanges since 2021, fostering a close collaborative relationship from the early stages of SoC chip design. As a first step in achieving this goal, ROHM’s power supply solutions have been integrated into Telechips’ power supply reference designs. These solutions support diverse model development by combining sub-PMICs and DrMOS with the main PMIC for SoCs.

For infotainment applications, the Dolphin3 application processor (AP) power reference design includes the BD96801Qxx-C main PMIC for SoCs. Similarly, the Dolphin5 AP power reference design developed for next-generation digital cockpits combines the BD96805Qxx-C and BD96811Fxx-C main PMICs for SoC with the BD96806Qxx-C sub-PMIC for SoC, improving overall system efficiency and reliability.

Modern cockpits are equipped with multiple displays, such as instrument clusters and infotainment systems, with each automotive application becoming increasingly multifunctional. As the processing power required for automotive SoCs increases, power ICs like PMICs must be able to support high currents while maintaining high efficiency. At the same time, manufacturers require flexible solutions that can accommodate different vehicle types and model variations with minimal circuit modifications. ROHM SoC PMICs address these challenges with high efficiency operation and internal memory (One Time Programmable ROM) that allows for custom output voltage settings and sequence control, enabling compatibility with large currents when paired with a sub-PMIC or DrMOS.

Moonsoo Kim,
Senior Vice President and Head of System Semiconductor R&D Center, Telechips Inc.

“Telechips offers reference designs and core technologies centered around automotive SoCs for next-generation ADAS and cockpit applications. We are pleased to have developed a power reference design that supports the advanced features and larger displays found in next-generation cockpits by utilizing power solutions from ROHM, a global semiconductor manufacturer. Leveraging ROHM’s power supply solutions allows these reference designs to achieve advanced functionality while maintaining low power consumption. ROHM power solutions are highly scalable, so we look forward to future model expansions and continued collaboration.”

Sumihiro Takashima,
Corporate Officer and Director of the LSI Business Unit, ROHM Co., Ltd.

“We are pleased that our power reference designs have been adopted by Telechips, a company with a strong track record in automotive SoCs. As ADAS continues to evolve and cockpits become more multifunctional, power supply ICs must handle larger currents while minimizing current consumption. ROHM SoC PMICs meet the high current demands of next-generation cockpits by adding a DrMOS or sub-PMIC in the stage after the main PMIC. This setup achieves high efficiency operation that contributes to lower power consumption. Going forward, ROHM will continue our partnership with Telechips to deepen our understanding of next-generation cockpits and ADAS, driving further evolution in the automotive sector through rapid product development.”

The post ROHM’s PMICs for SoCs have been Adopted in Reference Designs for Telechips’ Next-Generation Cockpits appeared first on ELE Times.

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The increasing connectivity of road vehicles leads to a growing need for cybersecurity. The United Nations Economic Commission for Europe (UNECE) has therefore adopted the R155 and R156 regulations, which define the cybersecurity requirements for OEMs. OEMs who want to sell new vehicles in UNECE-regulated markets must hold a valid type approval certificate and implement cybersecurity practices throughout the supply chain to minimize the risk of attack throughout the vehicle’s lifecycle. The TRAVEO T2G Automotive Microcontroller family for Body and Cluster from Infineon Technologies AG features a Hardware Security Module (HSM) that is capable of executing secured boot and ensuring secured isolation of HSM applications and data. To further enhance this, Infineon plans to retrospectively implement product compliance for the TRAVEO T2G automotive microcontroller family with the latest automotive cybersecurity standard ISO/SAE 21434. All necessary documentation, including the Cybersecurity Manual and Cybersecurity Case Report, will be provided to customers.

“With ISO/SAE 21434 compliant TRAVEO T2G automotive microcontrollers, OEMs’ effort to comply with UNECE R155 and R156 regulations will be significantly reduced. This enables faster time to the regulated markets”, said Ralf Koedel, Vice President Automotive Microcontroller at Infineon. “For existing customers, compliance becomes simpler, faster and more cost-effective while allowing the reuse of existing software and hardware. New customers can also benefit from the ISO/SAE 21434 compliance.”

The TRAVEO T2G microcontrollers are based on the Arm Cortex-M4(Single core)/M7(Single core/Dual core/ Quad core) core and deliver high performance, enhanced human-machine interfaces, high-security and advanced networking protocols tailored for a wide range of automotive applications. They offer state-of-the-art real-time performance, safety and security features. This is reflected, among other things, in the introduction of HSM (Hardware Security Module), dedicated Cortex-M0+ for secured processing, and embedded flash in dual bank mode for FOTA requirements.

With the planned new product compliance, developers can continue to use the TRAVEO T2G MCUs to develop their ISO/SAE 21434 compliant ECUs. As a result, they will benefit from lower product development costs and faster time-to-market for both existing and new platforms.

The post Infineon plans to implement ISO/SAE 21434 product compliance for TRAVEO T2G automotive microcontrollers appeared first on ELE Times.

Well it is something simple, I even took it apart fro the support to see what was going under it. But I didn't was able to wath to much as, it was glued. So the rainbow cable was blocking the main ic. Also, I watched a little drop of resin wich makes me think, that, or it was the main controller (not really sure, as the visible chips aside were plenty big), or it was just the e-paper driver. Maybe the second. Anyways. Even being a simple thing, it looked awesome. I thought this e-paper screen were more slow to refresh their frames, but this seemed to work faster than I thought. So this is my story of today and why now I want to buy an e-paper screen to test it with my raspberry zero 2w. Also, I can't imagine how expensive that screen is. And maybe will just end up in the trash once the decide is not necessary anymore, or just if the batteries die 😓 Hope it ends on good hands in the future (mine if possible, maybe leaving a note like a post it, behind. I will do it xd). submitted by /u/InsectOk8268 [link] [comments]