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Sneaky peak: sneaky feedback paths that de-stabilize an otherwise stable feedback loop

EDN Network - Tue, 09/20/2022 - 20:50

I have long held to the belief that electrons are smarter than people. Even the best engineers can fall prey to subtleties that electrons will readily act upon, especially when it comes to finding sneak feedback paths that can really screw up an otherwise stable feedback loop. We look here at a case study.

There was this multiple output DC power supply whose design was occasionally loop unstable and I was looking for the reason why and seeking to find a remedy. I set up an injected signal, call that “E-test”, as shown in Figure 1 so that by examining E2 with respect to E1, I could look at the gain and phase properties of the feedback loop.

Figure 1 Basic loop gain test plan for E-test.

There was a galvanic isolation barrier in the design, so the test setup was placed as follows (Figure 2):

Figure 2 Loop gain test plan in more detail.

We now look at how the Isolation Barrier Circuit was configured (Figure 3):

Figure 3 The alternating action clamping isolation barrier circuit.

The signal input voltage, E (on the left), gets transferred to the signal output voltage, E (on the right) by having a DC current source that drives the transformer secondary center tap to induce alternate clamping action via the two diodes on the transformer’s primary. We lose some level due to the Vcesat of the two NPN transistors and the forward voltage drops of the four diodes, but a linear transfer function from input to output is very closely achieved. A more detailed circuit is shown in Figure 4.

Figure 4 The alternative action clamping isolation barrier circuit in a bit more detail than Figure 3.

Please take mental note of the 8-volt power supply at the 1N4623 zener diode. We will return to consider the nature of those two parts a little later.

This pair of curves shown in Figure 5 shows the output of the isolation barrier circuit and the subsequent output of a  PWM control signal versus input to the isolation barrier circuit. For the sake of feedback loop control, that is all we need.  

Figure 5 The isolation barrier circuit linearity.

Although now superseded, the Hewlett-Packard 4395A Network Analyzer was used for loop testing (Figure 6).

Figure 6 To the left, the HP 4395A network analyzer used for our E-test. To the right, its attachment to the unit under test (UUT).

The 4395A was attached to the UUT via the 1:1 interface transformer shown in Figure 7. The braid of the coaxial cable served as the test transformer’s primary while the center conductor of the cable served as the test transformer’s secondary. The two 100 Ω resistors provide a nearly 50 Ω load for the analyzer’s RF output while the 100 Ω and 10 Ω resistors create a very small E-test in order to keep the power supply’s operating status as close to normal as possible while we do our measurements.

Figure 7 The test transformer and its attachment to the HP 4395A network analyzer.

We ran our loop gain tests at various levels of excitation for E-test and got a big surprise.

 As the test signal level from the analyzer was taken from 0 dBm downward to -12 dBm, we had different test results (Figure 8).

Figure 8 Loop gain Seen for (a) 0 dBm, (b) -3 dBm, (c) -6 dBm, (d) -9 dBm, (e) -10 dBm and (f) -12 dBm excitation from the network analyzer.

While the loop gain roll-off characteristic looked good at first when the network analyzer was set to an output level of 0 dBm, the roll-off characteristic changed dramatically as the excitation level was changed.

The culprit was discovered as follows (Figure 9):

Figure 9 The sneak feedback path.

The 8 volts of power was being derived from the very same inverter that the PWM action was controlling, which led to a sneak feedback path as shown above. The on resistance of the zener diode facilitated that path and, in my suspicion, Rzener varied versus test excitation which led to the weird test results.

The zener was replaced with an active IC as follows (Figure 10):

Figure 10 Eliminating the sneak feedback path.

By using the LM136 with its extremely low dynamic resistance and changing one resistor to restore the PNP transistor’s Q-point, the sneak feedback path was eliminated.

Test results became the following (Figure 11):

Figure 11 Loop gain and loop phase with sneak path removed.

With the sneak feedback path broken, the gain-phase results were good and alike to each other at all levels of test drive.

We had incorrectly assumed the power supply was a linear system. Because of the zener’s behavior, the power supply was really a non-linear system.

Starting from scratch as it were, loop gain and loop phase tests should always be run at varying levels of excitation to see if the test results match each other at every excitation level. If they don’t, you have a non-linearity somewhere that may cause trouble for you and/or for your end user.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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Class 2 ceramic capacitors—can you trust them?

EDN Network - Tue, 09/20/2022 - 19:14

When Ceramic Capacitors Go Bad – Aging.

Capacitor Aging applies to all Class 2 ceramic capacitors as they are built of ferroelectric materials. C0G types (Class 1) do not exhibit this aging effect, however, they are built out of non-ferroelectric dielectric materials.

All ferroelectric materials age, yes even ferrite-based magnetic parts age, as do the X7R and other high-density capacitor types.

This aging happens whether the part is in use or, just sitting in a bin somewhere. All Class 2 capacitors will lose capacitance over time.

This aging is due to the magnetic dipoles in the structure becoming less random with time, changing the dielectric constant of the material; this is a reversible process. When the capacitor dielectric material is taken to above its Curie temperature of around 125oC, the material becomes random again and the capacitor returns to its original value. This is called reforming or de-aging. After reforming, the aging process starts all over again. Even reflow soldering will probably heat the capacitors enough so that they reform, as noted on the Johanson Technology FAQ page [1] which states:

“After the soldering process, the capacitors have essentially been De-Aged.”

Although Johanson Technology suggests that if you are purposely going to de-age your capacitors on a board, you subject them to a 150oC soak for 1.5 hours, just to make sure you get all the capacitors to at least the Curie temperature.

The rate of capacitance aging for X7R types is nominally given as 2.5 to 3% per decade-hours of time since reforming (Figure 1).

This means: After manufacturing, the capacitor loses around 3% for every decade-hour since the capacitor material was last at the material’s Curie temperature.

The next most common Class 2 dielectric used in electronics, the X5R is typically given an aging rate of 3 to 7% depending on the manufacturer, although most manufacturers quote the larger 5 to 7% values. This suggests that just specifying a “X5R type” from several different manufacturers and expecting similar results, can lead to very different aging performance.

Figure 1 A typical capacitor aging chart, like the kind that you will find on some manufacturers’ data sheets. The upper curve is for a C0G. It is flat because these types do not exhibit the aging phenomena. The middle curve is for a typical X7R which may age at around -3% per decade-hour. The lower curve is for an X5R which is reported to age at any rate from -3% to -7% per decade-hour depending on which datasheet you look at. It turns out that these sorts of curves are inaccurate when the capacitors are biased, and in circuit.

If the rate of capacitance change for an X7R capacitor type is 3% per decade-hour. The net capacitance loss, compared to the datum point of 10 hours will be:

  • at 100 Hours, the capacitor will be -3%
  • at 1000 Hours it will be -9%
  • at 10,000 hours it will be -12%
  • at 100,000 hours or 11 years, the change will nominally be -15%

This aging is the same basic effect as applying DC bias to the capacitor. More DC bias (field strength) causes more of the magnetic dipoles in the material to line up, causing a decrease in the dielectric constant of the material.

What About Other Factors?

It was always assumed that the DC bias change and the aging capacitance changes happened independently and were merely additive.

Recently, however, it has been documented by Vishay [2] that adding DC bias to an X7R capacitor can increase the aging rate substantially. Vishay calculated that their capacitors have a nonlinear aging rate when biased to 100% of rated voltage and they report that some of their competitors may have an even greater rate of aging under DC bias (Figure 2).

Figure 2 Vishay’s study of X7R aging when 100% rated DC bias is included. The upper curve is for a Vishay capacitor and the lower curve(s) are some of the worst performances that they measured. Source: Vishay Vitramon [2]

Figure 2 shows some results of a 50V capacitor being biased at 100% of the rated working voltage. Vishay in their report also measured some 50V capacitors at 40% bias voltage. There, the aging rate was more linear, but, they report that some capacitors still exhibit substantial aging in the first 1000 hours. See the referenced report [2] for all the details.

The Vishay article also looked at the aging recovery with the removal of DC bias and found that this de-aged the capacitors at least somewhat and they recovered at least partially from the lost capacitance. Again, the results, according to Vishay, were highly dependent on the manufacturer tested.

The Vishay study did not present any data past 1000 hours.

Now you might well ask: “What about the effect of aging if I have DC bias and the operating temperature at higher than 25oC?”

That is an excellent question, a report published in the Journal of Electroceramics in 2008 [3] also seems to show that for X7R types, the effect of DC bias. And, with increased operating temperature, produces yet again an increased and nonlinear aging rate. However, the good news is that this aging rate seems to settle down in the 10,000- to 100,000-hour range to a maximum loss of about -25% compared to the 10-hour datum.

These nonlinear aging rates show a bottoming out with time, making sense from a material’s perspective. As voltage or time is applied to a Class 2 capacitor, the materials’ magnetic dipoles become less random. But there is a point where all the dipoles are 100% aligned, either through applied voltage or time aging, yet there will still be some capacitance as the material still has some dielectric constant, albeit much reduced.

What you have done by applying DC Bias and/or increasing operating temperature is just to accelerate the aging process.

The Vishay study used the classic 0.1µF, 50V-rated, 0603 size, X7R capacitor for their tests. It is not clear how a newer 2.2µF, 10V-rated, 0603 size, X7R capacitor would perform when similarly tested. These newer, lower-rated voltage, higher capacitance capacitors are what we circuit designers are all using more of, and it seems like more work needs to be done to give us the confidence that we have a handle on what the 10,000- to 100,000-hour capacitance limits might actually be in real-world use cases.


A comparison chart may be built for an X7R capacitor based on available data. Table 1 shows the cumulative effects of DC bias, temperature, and time aging on two capacitors that might be picked for a modern application.

Table 1 Comparison of two X7R, 0603-sized capacitors from manufacturers’ data. Both are assumed to have 5V bias and be operating at 70 Deg C. Even though the initial capacitance was double on one of the parts, the final result at 100,000 hours is much closer. All data is based on manufacturer’s data sheets, 100,000-hour aging is estimated.

The first capacitor is a 1µf, 25V, 0603 size, and the second is a 2.2µf, 10V, 0603 size, both are assumed to be biased at 5V and operated at 70oC. The total aging at 100,000 hours is due to normal aging, plus DC bias, plus operating temperature and is extrapolated to be -25% worst case from references [2] and [3]. Please note: The key word above is “extrapolated”, as I have no data of my own to back this up.

Even this linear multiplicative adding of terms is misleading as the total cannot be greater than probably an 80% capacitance drop total under any circumstances. This is because when all the magnetic dipoles are 100% lined up, the material will still have some residual dielectric constant. Hence, the situation is more complex than the simple back-of-the-napkin linear calculation that Table 1 shows.

More likely is the situation in Figure 3, which was derived from several manufacturers’ published data on DC bias effects alone. Figure 3 does show what happens to the capacitance of the capacitor when the dielectric material dipole alignment is increased from 0% (totally random) to 100% (totally aligned) which would represent the absolute worst case of DC bias, operating temperature, and aging combined.

Figure 3 A plot was made by studying several manufacturers’ curves of DC bias versus capacitance change and was extrapolated to this curve that shows the likely capacitance change versus a X7R capacitor dielectric material dipole alignment. The 0% is random alignment (left-hand side x-axis), and 100% is when the dipoles are aligned (right-hand side x-axis) showing approximately nearly 80% possible total capacitance loss.


The takeaway from all this for me is:

1) I had severe issues after the “Great Capacitor Shortage” of 2017 in how X7R parts acted when the manufacturers were scrambling to meet orders and substitutions, both known and unknown were made. I found a worse drop in capacitance with DC bias, among other parametric issues between capacitor batches produced before and after the shortage took hold in seemingly identical part numbers.

This makes me leery of trusting decades-old manufacturers’ published information, especially when the technology is changing as rapidly as it is. Even if you do your own reliability studies, you can’t be sure when the next capacitor shortage will change all the formulations again and make it all for naught.

2) The newer information on increased aging rate with DC bias and the elevated operating temperature seems to suggest that at 10 years, the designer might be wise to add another 25% to the expected X7R capacitance drop due to aging + operating temperature + DC bias aging effect. This is in ADDITION to the initial capacitance drop due to tolerance, temperature coefficient, and DC bias alone.

3) This accelerated DC bias + elevated operating temperature capacitance drop suggests that using high temperature, accelerated life testing to at least 1000 hours may help to understand the expected true capacitance change expected for longer expected lifetime products. Note: You can’t go much above 90oC for fear of de-aging the capacitors while you are testing them.

4) Using low rated voltage, high capacitance X7R capacitors running at high working voltage percentages may be problematic for bulk output filtering of a switching power supply, where the capacitance is used to stabilize the control loop, especially if you have to reach a longer operational lifetime. Test to at least 1000 hours at elevated temperatures or use another tried and true capacitor technology like tantalum or aluminum electrolytic for your bulk capacitance needs.

5) Using low rated voltage, high capacitance X7R capacitors running at high working voltage percentages may be fine for low dropout regulators (LDO) output filtering applications. In these applications, a maximum series resistance value, and perhaps some minimum capacitance value might be needed, but at the opposite extremes of these values will usually still provide a stable regulator. Check the regulators’ data sheet to verify.

6) Since X7R is the best of the bunch of all the rest of the Class 2 dielectric capacitors, it seems to strongly suggest that X5R’s be relegated to only high frequency bypassing on multi-megahertz digital circuits where the most important aspect of the capacitor is series inductance rather than any capacitance value. Be sure to see Part I of this article and the notes about piezoelectric effects also.

Bonus – Check Those Data Sheets

I looked at the manufacturers published capacitance versus DC bias data for two common, 0603 size, X7R capacitor types. The first one is the common 0.1µF, 50V that is used everywhere for decoupling (Bonus Figure 1), the second is a high density 1µf, 10V type (Bonus Figure 2).

Bonus Figure 1 A comparison of three manufacturers 0.1µF, 50V, 10%, X7R capacitors capacitance versus DC bias.

Bonus Figure 2 A comparison of three manufacturers 1µF, 10V, 10%, X7R capacitors capacitance versus DC bias.

As can be seen, every manufacturer has a different formulation for their X7R dielectric, and it changes based on the rated capacitor voltage. Keep this in mind when you run into a shortage and pick some other “equivalent” part number, it may not be as equivalent as you think!


[1] Christopher England, Johanson Dielectrics, “CERAMIC CAPACITOR AGING MADE SIMPLE” https://www.johansondielectrics.com/ceramic-capacitor-aging-made-simple

[2] Vishay Vitramon, Paul Coppens, Eli Bershadsky, John Rogers, and Brian Ward, “Time-Dependent Capacitance Drift of X7R MLCCs”, Vishay Vitramon, December 2021 https://www.vishay.com/docs/45263/timedepcapdrix7rmlccexptoconstdcbiasvolt.pdf

[3] Tsurumi, T., Shono, M., Kakemoto, H. et al. “Mechanism of capacitance aging under DC-bias field in X7R-MLCCs”, Journal of Electroceramics, Volume 21, 2008. https://link.springer.com/article/10.1007/s10832-007-9071-0

Steve Hageman has been a confirmed “Analog-Crazy” since about the fifth grade. He has had the pleasure of designing op-amps, switched-mode power supplies, gigahertz-sampling oscilloscopes, lock-in amplifiers, radio receivers, RF circuits up to 50 GHz, and test equipment for digital wireless products. He knows that all modern designs can’t be done with Rs, Ls, and Cs, so he dabbles with programming PCs and embedded systems just enough to get the job done.

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Test challenges in calibrating power for server designs

EDN Network - Tue, 09/20/2022 - 15:45

The global pandemic has accelerated the adoption of emerging semiconductor technologies to meet market demands, which has enabled companies with superior technology to outperform their competition. More than 50% of companies will need to build new digital businesses to stay economically viable, and recovery from the pandemic will involve permanent changes to many dimensions of an organization, including the pace at which it conducts business; its core value proposition; and the talent.

With digital and technology-driven disruptions creating a winner-takes-all dynamic in an expanding number of industries, only a subset of organizations is likely to thrive. In today’s competitive semiconductor market, where top companies have robust and expansive technology portfolios that are always evolving, a strong technology foundation is critical for success. The time is now for these companies to make bold and innovative investments in advanced technology and digital capabilities.

Effects of pandemic on digital ecosystem

The pandemic has amplified the need for technology growth and has encouraged innovation across the entire digital ecosystem, from big data and artificial intelligence (AI) to cloud computing and Internet of Things (IoT). Traditional brick and mortar retail companies have embraced technology to remain relevant and meet the demands of tech-savvy consumers. Big data has facilitated the digitization of various industries and exponential growth in eCommerce. Additionally, with travel restrictions imposed nearly worldwide, work from home became ubiquitous, resulting in an unanticipated surge in the uptake of cloud gaming and high-performance computing (HPC) as a service.

Figure 1 The above chart shows the compound annual growth rate for server sales. Source: Teradyne

The server market supporting AI hyperscalers is expected to grow by 50% year over year through 2025, while cloud gaming CAGR is expected to grow at an astonishing 72% through 2025. However, super high-performance systems have especially challenging power requirements clocking up to 10.2 KWatts per server. The emerging class of exascale high-performance computers—computing systems capable of calculating at least 1018 IEEE 754 Double Precision operations per second—and trillion parameter AI models for tasks such as accurate conversational AI require months to train, even with the processing power of today’s supercomputers.

Figure 2 In a typical server architecture, all processing components require power usage. Source: Teradyne

Power management challenges due to higher demand for computing power

As computing power increases, transistor count per die increases in tandem. Although process node counts have decreased over the years, die size is increasing as transistor counts double every 18 months. So, onboard real estate for power management devices decreases to accommodate larger processors. Consequently, increasing current draw coupled with decreasing availability of board development area for silicon-based MOSFETs, which supply current to the processors, results in an interesting power management challenge.

Figure 3 The above data highlights battling current requirements and available design space. Source: Teradyne

An insatiable appetite for higher power processors, for applications such as AI training servers, drives a substantial increase in MOSFET drivers. To keep heat generation as low as possible and maximize energy efficiency, these devices are designed with low RDSON to deliver hundreds of amps of current to the processors they are powering. However, high-volume MOSFET drivers with extremely low RDSON measuring less than 1 mΩ create challenges for semiconductor test.

Test challenges for achieving precise measurements

Testing semiconductors prior to the installation in final application is critical to ensure devices meet specified requirements for the lifetime of their use. Sustaining competitive cost of test (COT), while providing complete test coverage, requires precision high-power instrumentation to operate accurately and efficiently.

Measuring precision voltages across the 1 mΩ gate resistance on the MOSFET driver requires tens of amps of current to flow through. High bandwidth, precision and power instruments from automated test equipment (ATE) can efficiently measure RDSON resistance accurately. However, parasitic resistance from the device interface boards (DIB) and a device test socket’s contact resistance, which can measure up to 50 times of the MOSFET driver’s RDSON, pushes the boundaries of maintaining optimal utilization of the test cell.

Additionally, high current pulsing can cause magnetic coupling into adjacent traces, compromising measured value for adjacent sites in high parallelism solution. Unfortunately, the industry practice of shielding or closely coupling high-current traces is not viable when dealing with current-induced magnetic coupling. In order to address this challenge, the high-current traces must be laid out as broadside differential pairs to optimize the magnetic field cancelation. Pulsing substantial current through high-contact resistance generates excessive heat and damages contact pins over time.

Precise RDSON measurements of devices could be achieved by meticulously designing onboard circuitry supporting application calibration to eliminate path and contact resistance. The onboard circuit has a secondary function to ensure the safe operation of all instruments deployed. Optimal throughput could be achieved by maintaining high equipment efficiency via an ideal test environment.

New power instruments with improved bandwidth, coupled with innovative test techniques, help to prolong the contact pin lifespan by shortening pulse width and incorporating an ultra-efficient contact resistance check before each test execution. Increasing the power instrument’s bandwidth delivers faster DI/DT, translating to shorter test times and the possibility of increasing site counts, resulting in higher overall throughput. Prolonging the contact pin lifespan also reduces consumables’ expenses.

Boosting energy efficiency with new materials like GaN

As deep-learning AI becomes more pervasive, the insatiable demand for computing power will ensue and supporting power management semiconductors will experience intense growth. Meanwhile, the carbon footprint from data centers is attracting attention and regulatory policies are being enacted to ensure data centers are equipped with energy-efficient equipment. In 2019, data centers consumed about 2% of the world’s electricity, but this number is expected to rise to up to 8% by 2030.

The efficiency of MOSFETs typically maxes out at 95%. To meet the growing energy consumption of data centers, new materials and processes such as gallium nitride (GaN) are being developed to address the shortcomings of traditional semiconductor materials. With higher efficiency and switching frequencies, GaN power supplies deliver more power than their silicon-based predecessors with a similar footprint. “Turbocharged” GaN power supplies delivering higher power on a similar footprint could increase overall server density by up to 56% on existing racks.

Figure 4 The above table compares material properties of silicon and gallium nitride. Source: Teradyne

Gallium nitride power supplies deliver three benefits compared to silicon-based power supplies. First, existing data centers can increase their data density. Second, more efficient power supplies translate into lower operating costs. Finally, the data center can reduce its CO2 emissions as part of the global goal to achieve net-zero emissions by the year 2050.

The primary industry challenge with GaN transistors is the high dynamic on-resistance which is difficult to measure when switched at required high frequencies. Top test equipment manufacturers are working to develop the precision instrumentation required to guarantee GaN RDSON specifications. Soon, GaN will replace silicon as the preferred material technology for delivering power, but until GaN’s hard switching dynamic on-resistance can be measured consistently and accurately, silicon-based processors will continue to be utilized.

As demand for high-performance computing applications, often delivered as a service, increases, semiconductor companies must rise to the challenge to remain competitive by adopting new technologies and processes. Advances in power management and new materials like GaN will ensure the technology is able to keep up with the applications driving it. However, with these new technologies come a number of challenges, both for manufacturing and test. Those that can be nimble enough to adapt will find success in these new and emerging markets.

Aik-Moh Ng is a product manager for analog power test products at Teradyne.

Lauren Getz is a product manager for analog power test products at Teradyne.

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Aukey dash cam teardown redux: this time, the DRA5 gets a look

EDN Network - Mon, 09/19/2022 - 20:26

Back in January of last year, I mentioned that the prior July I’d purchased and subsequently non-destructively tore down Aukey’s DRA1 dash cam. What I didn’t tell you at that time was that earlier that same month, I’d also bought Aukey’s DRA5 dash cam, with the same teardown aspiration in mind. Both products were bought on sale from Amazon; $29.88 plus tax for the DRA1, versus $26.17 plus tax for the DRA5 (ironically, neither product can be found on Amazon any longer; Aukey was one of the many China-based merchants purged in mid-2021). And, although the DRA5’s more diminutive dimensions, translating into a tinier LCD, are presumably the rationale for its slightly lower price, it’s not necessarily a downgrade at the end of the day.

Potentially quite the contrary, actually; the smaller DRA5’s installed presence on the dash board or windshield is less obvious to others than with the bulkier DRA1, and the DRA5 is also easier to rotate in order to capture footage of what’s going on not only in front of you but also behind and to the side of your vehicle (if, for example, you’re pulled over for a traffic stop and want to record the consequent interaction with the police). Plus, independent reviews claim that the DRA5 delivers higher image quality than does its DRA1 sibling; more on that in a minute:

For comparison, here’s that same reviewer’s earlier take on the DRA1:

I’ll start with some “stock” images of the DRA5:

The accessories suite is a topic of some confusion. Reviews I’d read had indicated that the DRA5 includes only permanent adhesive-based mounts, versus the DRA1 which also included a temporary suction mount; reviews of the DRA5 also made a point of noting the suction-option omission. And indeed, as you’ll soon see, that (adhesive-only) was the case with the DRA5 I bought in early July 2020. But both the earlier product and the following accessories “stock” photos show only a suction mount, as is also solely listed in the user manual:

For comparison purposes, before diving into the DRA5, here’s the earlier “stock” photo for the DRA1 from my January 2021 teardown writeup:

In contrast, here’s the latest version, complete with a suction mount, right off Aukey’s website:

And here’s the original suite of accessories, showing both temporary and permanent mount options, along with the DRA1’s dimensions (presumably unchanged):

versus the latest iteration of the accessory suite from Anker’s website and user manual:

Methinks Anker’s been over time tweaking its included-mounts options for both products, whether for cost-reduction reasons, in response to reviewer and customer feedback, or both.

Onward. Here’s a table containing specification excerpts from both products’ user manuals. Note that, as my earlier review mentioned, there’s some dispute as to whether the DRA1 uses (as documented) the GalaxyCore GC2053 2 Mpixel image sensor and/or the lower-end GalaxyCore GC2023; the DRA5 seemingly exclusively relies on the higher-end GC2053:

I’ve already mentioned the image sensor model discrepancy between various Aukey documents (and versions of them), which could at least in part explain the image quality variance between the DRA1 and DRA5 noted in the earlier reviewer video. One other discrepancy I found is regarding the DRA1 aperture; the user manual claims that it’s f/2.4, while the product page specs it at f1.8; the DRA5’s aperture is consistently documented at f/2. If the former DRA1 spec is correct, it could further explain the image quality discrepancy between the two dash cams; whereas f/2 would lead to narrower depth of field than f/2.4, it would conversely translate into slightly better light capture (exposure) capabilities, particularly important when using the dash cam after dark. That all said, both dash cams apparently employ the same system (including image) processor, the Novatek NT96658. To wit, the image-related specs for the two dash cams are identical—resolutions, frame rates, and formats—along with recording modes and the like. 

Overview…err…over…let’s dive inside the DRA5, shall we? I’ll begin with a shrinkwrap side-of-box shot to show a label no longer present once the wrapper is discarded:

Now…off with that clear plastic cover!

Opening the lid, who wants to bet that that’s the dash cam inside the protective white bag?

Underneath it and the black Styrofoam it’s also nestled in is the documentation-and-accessories assortment, per earlier comments, no suction mount in my particular case: 

Here’s a closeup of the “cigarette lighter” power adapter, revealing its specs:

And now back to that mysterious white bag; hey, I was right!

Time for some pre-dissection shots; front, with the microphone above the lens and the speakers below it (at least per the user manual; stand by for contrary evidence) and the as-usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

One side: once again, Aukey went with a geriatric mini-USB power input. And re the GPS input, it’s an industry-standard 4-pin 3.5 mm female connector. You mate it to an Aukey GM-32 (or third-party equivalent) external GPS antenna-plus-receiver, which’ll set you back another ~$20:

Other side: that’s the microSD memory card slot, supporting capacities up to 128 GBytes (Class 10 or higher write speeds recommended):

Two bottom-side views, showcasing even more passive ventilation slots, along with dubious certification claims:

A top-side peek at the mount locking clip:

And last, but not least, that 1.5” LCD, non-touch-supportive therefore accompanied by control buttons below it (along with a user-feedback LCD in the upper right corner):

Here’s a refreshing change of pace; getting inside required only my fingernails to breach the seam between the two case halves:

Open sesame:

Disconnecting the flex cable between the PCB and display at the PCB end enables an unobstructed view of the LCD backside:

along with our first glimpse of the PCB (stack, as it turned out; keep reading):

Particularly notable is the earlier-mentioned system SoC, along with the switches associated with the four control buttons seen before. Three of the four screws whose removal are necessary to get the PCB out of the half-case are also obvious to the naked eye. And who wants to bet that there’s a fourth screw under that black foam piece in the upper right corner?

I win again!

Unsurprising, especially in retrospect (but then again, what isn’t), given the DRA5’s much smaller size than the DRA1 precursor, Aukey went with a two-PCB stack this time around versus being able to squeeze everything onto one circuit board. The approach necessitates two flex cables this time around, one (which we’ve already seen) between the processor board and the LCD, and the newly revealed one between the processor board and image sensor board. Unsnapping another connector…

The other side of the processor board now can be viewed unobscured:

At left are the GPS and power input connectors. At right is the microSD slot. The mic connects to the PCB at lower left, with the speaker connections at upper right; hold that thought. At top is the other end of the flex cable connecting this PCB to the image sensor board. And in-between the flex cable connector and speaker solder points…is that a battery I see? Just like the one in the DRA1? Even though both dash cams were supposedly supercapacitor-based? Hmm…

Discrepancy snark concluded (or not?), let’s look at what was previously attached to the other end of that flex cable:

Remember how I previously mentioned that the user manual said that the microphone was above the lens? Sorry, Anker, that’s the speaker; the microphone is in the lower right corner. Then again, you did the same transducer switcheroo with the DRA1, so at least you’re consistently wrong. Sigh…discrepancy snark now concluded.

Here’s a closeup of the PCB, clarifying the path forward:

If you look closely, you might be able to tell that the heads of the two screws in the center are slightly bigger than the one in the upper right corner or the ones in the lower corners. Sufficiently loosening them releases their hold on the lens assembly:

And removing the other three screws enables extraction of the board from the case and a look at the image sensor itself:

One of the lens mount screws remains associated with the PCB, as you can see. And look at that weird-shaped bubble of what’s presumably supposed to be the environment (moisture, dust, etc.) barrier translucent adhesive at the lens base-to-PCB junction:

With the PCB removed, the lens can also be extracted out the back of the case:

Here’s the infrared filter at its back end:

And two side views, once again showing evidence of assembly-line focus fine-tuning, subsequently retained via a dab of fast-drying solid-grip glue:

I’ll conclude with some unexpected news. As regular readers may already realize, whenever possible I strive to conduct my teardowns in a non-destructive manner so that I can reassemble my victims and, after confirming ongoing functionality, donate them to charity. Although I was able to accomplish this with the earlier DRA1, I doubted I’d be able to replicate my success this time around, given the multi-PCB and multi-cable added complexity of the DRA5. Nevertheless, I persisted. And after carefully putting Humpty Dumpty back together again:

Woo hoo! Excuse me while I finish typing so that I can pat myself on the back. I’ll hand the keyboard over to you, dear readers, for your thoughts in the comments.

Brian Dipert is Editor-in-Chief of the Embedded Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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Linearized portable anemometer with thermostated Darlington pair

EDN Network - Mon, 09/19/2022 - 18:20

This self-heated constant-temperature-delta transistor anemometer is cheap, rugged, and sensitive.  It relies on the relationship between airspeed (AF) and thermal impedance (ZT = oC/W) of a heated air flow sensor as shown in the formula below for a 2N4401 transistor in TO-92:

ZT = ZJ + 1/(SC + KT √AF )
ZJ = junction-to-case thermal impedance = 44°C/W
SC = still-air case-to-ambient conductivity = 6.4 mW/°C
KT = “King’s Law” thermal diffusion constant = 0.75 mW/°C√fpm
AF = air flow in ft/min

If the transistor junction is held at a constant temperature differential above ambient (e.g., Dt = 31oC), the power required to do so will be a function of air speed P = 31/ZT as shown in Figure 1.  Note the annoying non-linearity.

Wow the engineering world with your unique design: Design Ideas Submission Guide

 Figure 1 Power dissipated versus air flow of TO92 held at a constant 31oC above ambient      (Pw = 31/ZT).

Figure 2 shows a practical portable thermostat circuit to achieve and maintain this delta-T utilizing a Darlington transistor pair (Q1 and Q2) to compensate for ambient temperature and convert the resulting nonlinear Pw curve into a linearized anemometer air flow readout.

Figure 2 Linearized portable Darlington anemometer schematic.

Here’s how it works.

Q1 serves as the self-heated sensor modeled in the Figure 1 math, with Q2 providing ambient temperature compensation. Op-amp A2 runs a feedback loop that forces the Vbe differential between Q1 and Q2 (and thus the temperature differential between Q1 and ambient) to hold a constant 31oC. It does this (with the help of Darlington current gain) by forcing Q1’s current draw (I) through R3 to drive Q1’s power dissipation (Pw) to follow the Figure 1 curve of heat-vs-air flow. The resulting voltage developed (IR3) is the basis of the air speed measurement.

Okay so far. But how does compensation for Figure 1’s nonlinearity happen?

Well, it turns out the function of Q1’s Pw vs collector current, I, isn’t linear either. In fact:

Pw = 5vI – I2R3

That quadratic I2 term is very useful. It’s responsible for the lovely curve shown in Figure 3.

Figure 3 Q1 power versus collector current.

The 2nd-order curvature of Figure 3 is what compensates for the bend in Figure 1. Although the match isn’t perfect, when inverted, offset, and scaled by op-amp A1, the realized output is a calibrated readout (1V = 100fpm) of air speed that differs from ideal by less than +/- 5% from 0 to 250fpm, as shown in Figure 4.

Figure 4 Darlington anemometer output versus actual airspeed.

The resulting sensitivity to relatively slow air flow is ideal for the measurement of cooling-fan forced-air distribution, air infiltration tracking in HVAC installations, and many similar applications where the achieved measurement accuracy and range are adequate.

Dynamic response to changes in airflow is good with a Q1 forced thermal time constant of about three seconds. Also, solid-state sensor durability is better than that of delicate hot-wire sensors.

A detail of Figure 2 worthy of mention is Q3, which I include to preclude the possibility of the A2 feedback loop getting “stuck” when a transient or other misadventure might cause R3 voltage drop to exceed 2.5 V. This is a potentially bad thing because the Pw vs I curve would go “over-the-top” and invert the I vs Pw feedback term from negative to positive, causing A2’s output to latch with the Darlington saturated and stay thus stuck for as long as power is provided. 

If saturation approaches, Q3 conducts and forces A2 to limit Darlington drive to a safe level until the transient passes and normal temperature regulation can recover.

Another useful detail is “upside-down” regulator U1 which provides not only necessary stability for the 5 V power rail, but also “splits” input power and provides an unregulated, but still useful, negative rail for the op-amps. This simple but handy trick is described in an earlier Design Idea.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a ways. In all, a total of 64 submissions have been accepted since his first contribution was published in 1974.

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The ups and downs in the CMOS image sensor market

EDN Network - Mon, 09/19/2022 - 14:30

CMOS image sensors—the unsung hero of the opto-semiconductor market—are staring at what some technology managers in China call a perfect storm amid a slowdown in smartphone shipments and a pause in the increase of embedded cameras being designed in new handsets. According to IC Insights’ August 3Q Update of The McClean Report, the CMOS image sensor market is on track to suffer its first decline in 13 years, with sales expected to fall 7% to $18.6 billion.

It’s worth mentioning that nearly two-thirds of CMOS image sensors are used in mobile phones. An average handset incorporates three cameras, one on the front, facing the user for selfies, and two main cameras on the backside of the phones. On the other hand, a high-end smartphone could feature five or more cameras.

Another factor, as pointed out by some industry observers, has been the U.S. trade bans on China. As a result, Sony, the market leader in CMOS image sensors, has been struggling to match image-resolution requirements for camera phones produced by the leading Chinese system manufacturers in the first half of 2022. However, according to Yole Intelligence, part of Yole Group, the market has now stabilized after a bubble caused by CMOS image sensor stockpiling as a consequence of U.S. sanctions against major China-based companies.

Figure 1 CMOS image sensors are expected to slowly regain growth momentum. Source: IC Insights

At the same time, however, both Yole and IC Insights forecast new growth cycles from smartphone upgrades and other markets such as automotive cameras, medical imaging, and intelligent security networks. IC Insights’ August 3Q Update expects CMOS image sensor sales to rise by a CAGR of 6.0% between 2021 and 2026 to reach $26.9 billion in the final year of the forecast.

CMOS image sensor’s quest for new growth venues is apparent from recent announcements. For instance, Sony, which accounted for about 43% of CMOS image sensor sales worldwide in 2021, has recently announced a 1/3-type CMOS image sensor for security cameras with approximately 5.12 megapixels. It simultaneously delivers both full-pixel output of the whole captured image and high-speed output of regions of interest.

Figure 2 The CMOS image sensor for security cameras simultaneously delivers a full-pixel output of captured images and high-speed output of regions of interest. Source: Sony Semiconductor Solutions (SSS)

The new image sensor leverages Dual Speed Streaming technology to output all of the pixels in a captured image at a maximum rate of 40 frames per second while simultaneously outputting specific user-set regions of interest at high speed. As a result, it can provide comprehensive images of scenes and support high-speed recognition of specific objects at a high level of detail.

In the post-Covid design world, even the CMOS image sensor, the ever-trustable growth engine, wasn’t spared from ups and downs. The good news is that it’s now stabilizing while continuing to innovate and seek sockets in new design areas like automotive and security imaging. As Yole puts it, the CMOS image sensor market has bottomed out at 2.8% year-on-year growth in 2021 and is ready to start a new growth cycle in 2022.

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The Prominent Advancements in the Medical Field

Electronic lovers - Sun, 09/18/2022 - 18:25

The medical field is a highly competitive, dynamic industry. It’s driven by discoveries, new knowledge, and changes in the environment that we live in. The advancements are just amazing, and they’re constantly happening. Here are some of the significant advances that have occurred in the medical field.

1. The inventor of the MRI machine

Russell Blackford was the person who invented the MRI machine. He was born in Australia in 1948. Mr. Blackford discovered that NMR or nuclear magnetic resonance could be used to detect different substances and even map complete human beings. The brain is a significant part of a human being that needs to be detected on time to handle medical complications and the lack of oxygen it receives.

2. The development of computers and tablets

The computer department has made significant progress in recent years, especially with the introduction of tablets with touchscreens on them. The tablets are an easy way for physicians to access and pass on information to the patient. Medical facilities also use these computers to provide patients with health care. The touch screen will make it easier for patients to use the computer and get all the necessary information in minutes without hassle.

3. The development of medical implants and surgery

The medical implants and surgery developed over the years have made this a more exciting, vital, and essential part of medicine. Medical implants can perform scans or treatments while allowing the patient to lead an everyday life. Operating on someone before they are ready can also lead to serious complications that may even kill them.

4. The development of fusion surgery

Using nucleus pulposus is one way to combat back pain in patients. The spindle cells are located in the lumbar spine, between the vertebrae that make up the lumbar region of their bodies. They help to cushion the vertebral bodies from the pressure from the spinal tissues. This can prevent injury and pain.

5. The development of endoscopic surgery

Endoscopic surgery is a way to perform surgical procedures using a flexible tube called an endoscope. During this procedure, instead of going through a patient’s body, doctors tend to use an endoscope that goes through incisions made in the mouth or anus and then into the interior space of the body where they will do their work. It’s safe and has no complications that come with it because they already know where surgery should be done inside the body before they even get there.

6. EHR

Electronic health records, or EHR, is what it’s called. An electronic health record is simply a system that physicians and other medical professionals use to store information about their patients. Having records stored on the computer makes it easy for doctors and other medical professionals to refer to the patient’s history of the disease or any prior treatments they received. You can learn more at HealthTECH Resources about EHR.

7. Digital Marketing

Digital marketing in the medical field is a very effective way to promote the services of the clinics around you or your practice. The digital world has become a part of everyone’s life. This makes it easier for patients to find what they need online than in the conventional ways we used back then. The marketing is done online also leads to a better conversion rate as well. You can go now to learn more about digital marketing to know how it works.

8. The formation of fluid therapy

Fluid therapy has been used in medicine for many years now as a way to help treat patients with kidney problems or other complications that prevent them from absorbing enough fluids in their bodies. 

9. Isotope applications

Isotopes have been used in medicine for many years as a way to identify necessary elements that are present in the body and to detect disease. They help test whether a person has too much of something or not enough of it.

10. The development of virtual nursing homes

These great tools have been developed to help elderly patients with dementia or Alzheimer’s. They can communicate with friends and family who may not live nearby because this application allows them to do that through video chat. They will also be able to lead a more normal life and still have fun while they are at it while taking care of their health needs and getting the right treatments they need so they can stay healthy for longer.

11. The development of the science of cosmetic surgery

Cosmetic surgery has improved people’s appearance by giving them a facial or body part that they may not have before. Now, it’s more important than ever to use them because many people don’t look at them all the same as they did in the past and want to change for the better. It is another way for people to live healthier and happier lives. 

12. The development of gene therapy

Gene therapy has been used in medicine to introduce genes into a patient’s body and cure them from diseases like cancer or diabetes, for example. This technique has been used to treat some people with HIV and AIDS. Gene therapy is usually done using viruses, but in this case, it’s done using an engineered virus. This treatment can be complicated and expensive, so doctors generally want to see how it works on animals or half-finished human bodies before using it on humans. 

13. The use of bone marrow transplantation

Bone marrow transplantation is a procedure that has been used for many years now as a way to save lives and make patients feel better about themselves again. The procedure is done by extracting the bone marrow from the donor and transplanting it into the recipient. This has been used to treat patients with leukemia, for example, because it helps them to recover faster.

In conclusion, the medical world has come a long way over the years, and it has been able to help people live healthier and happier lives all around the world. All these advancements are a direct result of the people working in this field and making their work available to others.

Healthcare Information Technology (HIT) and its Applications

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Weekly discussion, complaint, and rant thread

Reddit:Electronics - Sat, 09/17/2022 - 17:00

Open to anything, including discussions, complaints, and rants.

Sub rules do not apply, so don't bother reporting incivility, off-topic, or spam.

Reddit-wide rules do apply.

To see the newest posts, sort the comments by "new" (instead of "best" or "top").

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Google joins NIST in a bid to democratize chip design

EDN Network - Fri, 09/16/2022 - 16:56

Another attempt to democratize chip design is on the horizon, this time constituting government, industry, and academia. Google has joined hands with the National Institute of Standards and Technology (NIST) to develop and produce chips that researchers at universities as well as engineers at startups will be able to use without restriction or licensing fees.

SkyWater Technology will manufacture these chips at its fab in Bloomington, Minnesota on 200-mm wafers. Google will pay the initial cost of setting up production and subsidize the first production run. And NIST, with its university research partners, will design the circuitry for the chips. NIST’s research partners include the University of Michigan, the University of Maryland, George Washington University, Brown University, and Carnegie Mellon University.

NIST plans to design as many as 40 chips, and researchers will be able to put these open-source chips to use in nanosensors, bioelectronics, and advanced devices needed for artificial intelligence (AI) and quantum computing. The legal framework of this collaboration eliminates licensing fees, which is expected to dramatically bring down the cost of these chips. Otherwise, the cost of designing a chip can run into hundreds of thousands of dollars, posing a major hurdle for university researchers and startup engineers.

NIST developed this chip to measure the performance of memory devices used by AI algorithms.

According to NIST director Laurie E. Locascio, the collaboration was planned before the recent passage of the CHIPS Act, but now it certainly looks part of the efforts to enhance the U.S. leadership in the semiconductor industry. It will, for instance, allow design engineers to prototype designs and integrate chips in their production cycles quickly and efficiently.

Though we have seen somewhat similar efforts to democratize semiconductor design in the past, with Google, a known disruptor in the technology world, it seems to be a more credible effort. And the momentum built around the CHIPS Act could certainly help this semiconductor endeavor operating on an open-source model.

NIST will host a virtual workshop on chip design to be carried out in collaboration with Google on 20-21 September 2022.

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GaN FETs for 48V DC/DC conversion

EDN Network - Fri, 09/16/2022 - 16:53

EPC expands its portfolio of off-the-shelf GaN FETs in thermally enhanced packages with the introduction of the 100-V, 3.8-mΩ EPC2306. The device is footprint-compatible with the previously released 100-V, 1.8-mΩ EPC2302. Engineers can trade off on-resistance versus price to optimize designs for efficiency or cost by dropping in a different part number in the same PCB footprint.

The EPC2306 enhancement-mode GaN power transistor is intended for 48-V DC/DC conversion in high-density computing, 48-V BLDC motor drives for e-mobility and robotics, solar optimizers and microinverters, and Class D audio applications. In addition to low RDS(on) of 3.8 mΩ, the FET provides low QG, QGD, and QOSS for low conduction and switching losses. Its thermally enhanced QFN package has an exposed top and a footprint of just 3×5 mm.

A half-bridge development board featuring the EPC2306 GaN FET simplifies the evaluation process to speed time to market. With a maximum voltage of 100 V and maximum output current of 45 A, the EPC90145 mounts all critical components on a 50.8×50.8-mm board.

Available now from Digi-Key, the EPC2306 GaN FET costs $3.08 in lots of 1000 units, while the EPC90145 development board costs $200.

EPC2306 product page

EPC90145 product page

Efficient Power Conversion

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Linear redrivers minimize signal integrity issues

EDN Network - Fri, 09/16/2022 - 16:51

Three 1.8-V, 20-Gbps linear redrivers from Diodes allow equalizer and flat gain adjustments to improve signal integrity in USB4 Gen3, Thunderbolt 4.0, and DisplayPort 2.0 connections. The devices offer various settings to mitigate channel loss and extend reach, and they are transparent to channel link training.

Aimed at laptops, desktops, monitors, and docking stations, the PI2DPX2020, PI2DPX2023, and PI2DPX2063 operate in a 4-to-4 configuration and exhibit ultra-low latency of less than 300 ps for better interoperability and data throughput. Auto power-savings modes are built in. Each part is housed in a tiny 32-pin WLGA package with dimensions of 2.85×4.5 mm and operates over a temperature range of -40°C to +85°C.

The PI2DPX2020 redriver provides configurable operating modes for maximum design-in flexibility. These include 20-Gbps/40-Gbps USB4 Gen3 (x1/x2), 20.625-Gbps/41.25-Gbps Thunderbolt 4.0 (x1/x2), 10-Gbps/20-Gbps USB4 Gen 2 (x1/x2), 20-Gbps USB4 Gen2/2 lanes of DisplayPort 2.0 and 4 lanes of DisplayPort 2.0.

The 4-lane PI2DPX2023 20-Gbps DisplayPort 2.0 (UHBR20) redriver supports pin-strap equalizer and gain parameter control, while for the PI2DPX2063 20-Gbps DisplayPort 2.0 (UHBR20) redriver achieves the same control via the I2C interface pin.

In lots of 5000 units, the PI2DPX2020, PI2DPX2023, and PI2DPX2063 cost $2.99, $3.00, and $2.95, respectively.

PI2DPX2020 product page

PI2DPX2023 product page

PI2DPX2063 product page


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Keysight teams with IBM to advance Open RAN in Europe

EDN Network - Thu, 09/15/2022 - 19:00

Keysight Technologies has signed a memo of understanding with IBM to accelerate Open RAN deployments in Europe. IBM aims to employ Keysight’s Open Radio Architect (KORA) test solutions at its Open RAN Center of Excellence (CoE) in Spain to help European mobile operators bring to market applications that meet the architecture standards defined by the O-RAN Alliance.

The goal of the partnership is to integrate Keysight’s software-centric Open RAN test, measurement, and emulation tools with IBM’s Cloud Pak for Network Automation, an AI-powered telecommunications cloud platform for automating network operations. Keysight’s Open RAN solutions enable vendors to verify conformance, interoperability, performance, and security, resulting in the deployment of fully interoperable RAN equipment.

IBM’s CoE intends to use Keysight’s RuSIM radio unit simulator to validate O-RAN distributed units; CoreSIM to verify the performance of Open RAN equipment; and Nemo Wireless Network Solutions to optimize and monitor networks.

“IBM’s hybrid cloud, automation and security solutions are utilized by some of the world’s largest telcos to support their efforts for the next era of communication,” stated Oscar Gonzalez Nogueira, Industry Partner at IBM. “The integration of Keysight’s tools into IBM’s Cloud Pak for Network Automation will further support our ecosystem of CSPs to enhance application and network automation.”

Keysight Technologies


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Image sensor improves in-car safety and comfort

EDN Network - Thu, 09/15/2022 - 18:59

ST’s VD/VB1940 automotive-grade dual image sensor monitors the entire vehicle interior covering both the driver and all passengers. While driver monitoring systems (DMS) promise greater road safety by assessing driver alertness, ST’s sensor can empower applications like child-presence detection, passenger safety-belt checks, vital-sign monitoring, gesture recognition, and video/picture recording.

The VD/VB1940 is a 5.1-Mpixel image sensor with both rolling and global shutter modes. Specifically designed to manage RGB and near-infrared (NIR) operations, the sensor outputs RGB Bayer color images on one side and full-resolution NIR images on the other side. The device captures the high dynamic range (HDR) color images needed for an occupant monitoring system, plus the high-quality NIR images typically captured by standard DMS sensors.

The VD/VB1940 captures up to 60 frames/s at full resolution and is fully configurable through an I2C serial interface. Compliant with ISO 26262 standards and ASIL-B safety levels, the part contains cybersecurity features that prevent hacking.

Samples of the VD1940 (bare die) and VB1940 (BGA package) sensors are available now for model year 2024 vehicles.

VD/VB1940 product page


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Cross-platform tools ease ML development on PSoC 6 MCUs

EDN Network - Thu, 09/15/2022 - 18:58

Users of Edge Impulse’s Studio environment can now access Infineon’s Modus Toolbox for building edge machine learning applications on PSoC 6 MCUs. The collaboration expands the Modus Toolbox MCU configuration software and ecosystem to now include the Edge Impulse cloud platform.

Develop and configure applications on the Infineon PSoC 6-based CY8CKIT-062S2-43012 Pioneer Kit coupled with the CY8CKIT-028-SENSE expansion kit for interfacing accelerometer, gyroscope, magnetometer, microphone, pressure, and temperature sensors. Data from these sensors are used with Edge Impulse Studio for generating TinyML-based AI models, optimized for low-power, low-cloud-cost edge environments. Models can then be deployed on any PSoC 6-based MCU.

“With the performance and extremely low-power design of the PSoC 6, running TinyML models down at the edge becomes even more capable than before. By using Edge Impulse to simplify the barrier to machine learning, product makers can focus on real data they collect from the device to make an innovative and effective product,” said Danny Watson, director and software product marketing manager, Infineon.

For more information on the cross-platform offering, click here.

Edge Impulse 

Infineon Technologies 

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