Новини світу мікро- та наноелектроніки

Direct Air Electrolysis for Making Hydrogen out of Thin Air

ELE Times - Thu, 09/08/2022 - 13:34

A team of researchers at the University of Melbourne, working with a colleague from the University of Manchester, has developed a device that can use humidity from the air to make hydrogen gas the group describes their device and its performance under lab conditions.

As scientists around the world seek solutions to reduce global warming, many have focused on the production of hydrogen gas as a replacement energy source. It is a zero-carbon fuel that yields only water as a byproduct when combusted. Hydrogen gas is typically made by splitting water molecules into hydrogen and oxygen, a process called electrolysis. It is carried out by passing an electric current through a sample of water. This starts a chemical reaction that leads to the decomposition of the materials in the molecule.

Most efforts to use electrolysis involve water from a pure source and tend to be complicated and expensive, which is why hydrogen is still not widely used to power vehicles. In this new effort, the researchers simplified the process and used a readily available source of water—humidity.

The device, which the team calls a direct air electrolysis module, was made using sponge-like materials for the electrodes. They liken them to silica gel often seen in moisture absorption packets. The moisture that is gathered moves to a chamber where it is electrolyzed. The key to the success of the module was that the hygroscopic electrolytes can be exposed to the atmosphere all the time.

The electricity to power the reactions was obtained from an easily available renewable resource—a small wind turbine. As positively charged electrodes moved through the water, electrons were pulled from the molecules, resulting in the formation of positively charged oxygen ions and negatively charged hydrogen ions. The oxygen was released and the hydrogen was captured.

The prototype was able to produce hydrogen for more than 12 consecutive days. The researchers also let it run by itself for eight months to determine its durability. And they found that it worked with humidity levels as low as 4%. Testing thus far has shown the device to be capable of producing enough hydrogen to heat a home. They also note that while the prototype is small, it could be scaled up or multiple modules could be connected together.

The post Direct Air Electrolysis for Making Hydrogen out of Thin Air appeared first on ELE Times.

Capturing 3D Images from a Single Exposure

ELE Times - Thu, 09/08/2022 - 13:33

Researchers have developed a camera that uses a thin microlens array and new image processing algorithms to capture 3D information about objects in a scene with a single exposure. The camera could be useful for a variety of applications such as industrial part inspection, gesture recognition, and collecting data for 3D display systems.

“We consider our camera lensless because it replaces the bulk lenses used in conventional cameras with a thin, lightweight microlens array made of a flexible polymer,” said research team leader Weijian Yang from the University of California, Davis. “Because each microlens can observe objects from different viewing angles, it can accomplish complex imaging tasks such as acquiring 3D information from objects partially obscured by objects closer to the camera.” the camera learns from existing data how to digitally reconstruct a 3D scene, it can produce 3D images in real-time.

“This 3D camera could be used to give robots 3D vision, which could help them navigate 3D space or enable complex tasks such as manipulation of fine objects,” said Yang. “It could also be used to acquire rich 3D information that could provide content for 3D displays used in gaming, entertainment or many other applications.”

A camera that learns

The new camera grew out of previous work in which the researchers developed a compact microscope that can image 3D microscopic structures for biomedical applications. “We built the microscope using a microlens array and thought that a similar concept could be applied for imaging macroscopic objects,” said Yang.

The individual lenses in the new camera allow it to see objects from different angles or perspectives, which provides depth information. Although other research groups have developed cameras based on single-layer microlens arrays, it has been difficult to make them practical because of extensive calibration processes and slow reconstruction speeds.

To make a more practical 3D camera for macroscopic objects, the researchers considered the microlens array and the reconstruction algorithm together rather than approaching each separately. They custom-designed and fabricated the microlens array, which contains 37 small lenses distributed in a circular layer of polymer that is just 12 millimeters in diameter. The reconstruction algorithm they developed is based on a highly efficient artificial neural network that learns how to map information from the image back to the objects in a scene.

“Many existing neural networks can perform designated tasks, but the underlying mechanism is difficult to explain and understand,” said Yang. “Our neural network is based on a physical model of image reconstruction. This makes the learning process much easier and results in high-quality reconstructions.”

Once the learning process is complete, it can reconstruct images containing objects that are at different distances away from the camera at a very high speed. The new camera doesn’t need calibration and can be used to map the 3D locations and spatial profiles—or outlines—of objects.

Seeing through objects

After performing numerical simulations to verify the camera’s performance, the researchers performed 2D imaging that showed perceptually pleasing results. They then tested the camera’s ability to perform 3D imaging of objects at different depths. The resulting 3D reconstruction could be refocused to different depths or distances. The camera also created a depth map that agreed with the actual object arrangement.

“In a final demonstration we showed that our camera could image objects behind the opaque obstacles,” said Yang. “To the best of our knowledge, this is the first demonstration of imaging objects behind opaque obstacles using a lensless camera.”

The researchers are currently working to reduce artifacts, or errors, that appear in the 3D reconstructions and to improve the algorithms to gain even higher quality and speed. They also want to miniaturize the overall device footprint so it could fit into a cellphone, which would make it more portable and enable more applications.

“Our lensless 3D camera uses computational imaging, an emerging approach that jointly optimizes imaging hardware and objects reconstruction algorithms to achieve desired imaging tasks and quality,” said Yang. “With the recent development of low-cost, advanced micro-optics manufacturing techniques as well as advancements in machine learning and computational resources, computational imaging will enable many new imaging systems with advanced functionality.”

The post Capturing 3D Images from a Single Exposure appeared first on ELE Times.

Creating an ultrafast Optoelectronic Switch

ELE Times - Thu, 09/08/2022 - 13:32

A team of researchers affiliated with a host of institutions in China has developed an ultrafast optoelectronic switch using a Bose-Einstein condensate of polaritons.

As scientists look for ways to create faster devices, they have turned to light as an information transfer medium instead of electrons. In order to create such devices, switches must be developed that can handle the faster medium that operates at optical frequencies. In this new effort, the researchers have designed and built just such a switch—one that allows for processing in the terahertz range.

To build their new switch, the researchers looked to polaritons as a switch mechanism. Polaritons are quasiparticles that can be made using photons and excitons, and they can be used to create Bose-Einstein condensates that are made up of particles that exist in a single quantum state. Polaritons emit light, which is a necessary part of an optical switch. The researchers noted that a Bose-Einstein condensate made using polaritons could act as a polariton laser, another useful feature in an optical switch. The researchers also noted that some semiconductors, such as zinc oxide, can hold excitons at room temperature, a very handy feature.

To create their switch, the researchers began with a sample of zinc oxide, inside of which existed microcavities. Firing an ultraviolet pump pulse at a cavity for a few femtoseconds resulted in a flash of light from the Bose-Einstein condensate inside, lasting the same length of time. More important, turning off the laser resulted in turning off the flash of light very quickly—1,000 times faster than other optoelectrical switches. This was due to the fast extinction rate of the polariton population. The time it takes an optical switch to turn from on to off and vice versa constitutes one of its most important features, and the rate for this new device was found to be several orders of magnitude better than other polariton switches that have been developed thus far: Good enough to put devices using such a switch in the terahertz range.

The post Creating an ultrafast Optoelectronic Switch appeared first on ELE Times.

Diving Deep into India’s ESDM Industry with Bhupinder Singh

ELE Times - Thu, 09/08/2022 - 12:34

The industry needs a robust supply chain for increased value addition and entrepreneurship, thus making Indian electronics manufacturing globally competitive.

Considering the upward trajectory of India’s electronics manufacturing industry, Bhupinder Singh, CEO, Messe Muenchen India in an exclusive interview with ELE Times Sub Editor Mayank Vashisht, explains how India has gained quite a lot of prominence in the ESDM sector and how electronica India and productronica India is on a perpetual roll to contribute immensely in the electronics industry landscape of the country. In our conversation, Bhupinder also reflected upon the relevance of the sheer efforts that the government of India is making with the introduction of schemes like ‘atmanirbharbharat’ and ‘make in India’ and how this industry can leverage global opportunities by developing a thriving domestic supply chain through trade fairs of international standards such as electronica India and productronica India 2022. Excerpts:

ELE Times: electronica India and productronica India have gained quite a lot of prominence setting new precedence every year in the ESDM industry. How do you keep up with the changing market trends?

Our deep connections with the electronics ecosystem through our advisory boards, industry associations and other stakeholders having in-depth knowledge of the latest trends, combined with the international character of the electronica and productronica trade fairs (in Munich and China) ensure that every year our events in India are more closely aligned with the Indian industry’s interests. When you participate in our shows either as a buyer or an exhibitor, you are not only building your own business but weaving your interests into the larger industry landscape of the country amidst the presence of thought leaders and decision-makers at our exhibitions and conferences. Our shows are supported by the Ministry of Electronics and Information Technology (MeitY) as well as leading industry associations such as the Electronic Industries Association of India (ELCINA), India Cellular and Electronics Association (ICEA), India Electronics & Semiconductor Association (IESA), and Indian PCB Circuit Association (IPCA). These partnerships help us address the complete electronics value chain.

ELE Times: How will you trace back electronica and productronica India’s contribution to India’s electronics industry landscape?

Electronics manufacturing in India has grown considerably over the last decade. It is one of the fastest-growing industries in India and is likely to reach $300 billion by 2025-26. electronica India and productronica India have been close partners in the electronics industry since their inception more than 20 years ago. We have strong participation from Indian companies as well as a wider global reach. While our exhibitions and our focussed matchmaking platform- buyer-seller forum help the industry unlock actual business opportunities, our specially curated conferences help the industry discuss relevant topics, address the challenges faced and explore possible solutions for the industry growth. We empower the Indian industry to build stronger networks for a more robust supply chain. Through our deep connections with the electronics ecosystem in India and global connections, we help the Indian ESDM ecosystem to realise its ambitious growth targets.

ELE Times: With the serious emphasis on schemes like ‘Make in India’ and ‘atmanirbharbharat’ and the sheer efforts made by the government of India with respect to making the country an electronics epicentre of the world, how do you see the industry shaping up in India? Is the aspiration farfetched, from your standpoint? How are you contributing to making India ‘atmanirbhar’?

The Government of India has shown the right intent to reduce dependency on imports and make India self-reliant by implementing schemes such as the NPE 2019, PLI for large-scale electronics manufacturing, SPECS, EMC 2.0 etc.  Each of these schemes has been judiciously created to boost large-scale production, manufacturing clusters, and a robust supply chain ecosystem in the country. However, India still has a long road ahead. If India aims to become a global epicentre for electronics manufacturing, it will require attractive incentives for global companies to set up their base here. Though the financial incentives are encouraging, India suffers from land acquisition complications, lack of local component ecosystem, supply chain challenges, high cost of power supply and logistics, etc. The lack of world-class semiconductor fab units in the country is another major challenge. We will be delving deep into these topics through the ‘India Semiconductor Conclave’ at electronica India and productronica India 2022.

ELE Times: How do you see the growth of the Indian Electronics Industry in the last five years?

India has been one of the front runners amongst all the emerging nations from an economic development standpoint. A major credit of India’s upward trend in GDP growth can be attributed to the electronics sector. This growth is primarily driven by the increasing demand and consumption of electronic products. Electronics manufacturing in India has grown considerably over the last few years. This can be seen in increased mobile phone exports by 75% from the last fiscal. Also, domestic manufacturing of electronic products almost doubled from $37.1 billion in 2015-16 to $74.7 billion in 2020-21. India is expected to become a major semiconductor manufacturing nation in the next 5-6 years. We are moving in the right direction to realize this decades-old dream.

ELE Times: Please highlight the challenges you had to muddle through post-COVID, and how the industry sentiment is, and scenario is changing.

The pandemic put forth a serious challenge to our industry but gave us the opportunity to emerge stronger with a clear purpose and a stronger vision for growth. Post Covid-19 we have worked hard to establish more stringent safety and hygiene protocols in all our physical spaces, including exhibition halls, lounges, offices, etc. While we explored the virtual exhibition route to stay in touch with our buyer and supplier communities at the height of the pandemic, we have emerged with a deeper commitment to our original mission of enabling meaningful handshakes and unlocking business opportunities. Thus, we are now noticing increased enthusiasm for our shows from exhibitors and visitors as they have realised the value of in-person face-to-face meetings. We are already registering higher footfalls at our shows and are excited about delivering more value at our upcoming shows.

ELE Times: Electronic Industry landscape is changing fast in India. Manufacturing and exports are the buzz word these days. Considering the fact, what new shape you are going to give to electronica India and productronica India exhibition in the time to come.

In 2012-13, India’s share in global electronics production was 1.3 percent and in 2020, it only represented 3.6 percent. Though the total electronics market in India in 2019-20 was around $120 billion, the domestic manufacturing value addition was only 15 to 20 percent. At this rate, even if we reach $300 billion worth of electronics manufacturing in 2026, our domestic manufacturing value addition would only be $45-60 billion. In a value chain of any product, components such as semiconductors, displays, and batteries hold 40 percent value. We do not have any component manufacturing ecosystem, due to which we import more than 90 percent of components and miss out on the 40 percent value. This is a major challenge and needs to be addressed urgently. To deliberate on this issue and find out possible solutions, we are introducing India Semiconductor Conclave at electronica India and productronica India 2022. The conclave would comprise knowledge-rich conferences. We are also accelerating the growth of the start-ups by providing them access to technology and market in our trade fairs and are working on enabling funding and mentorship to them, which are most critical for their success.

ELE Times: Research and development are perhaps the most important and significant factors considering the innovation of any technology, still, it comes at the bottom of the due recognition index in India. Do you have any future plans to encourage the participation of researchers in your show from India?

India has always been strong on the design front, be it semiconductor design or system/product design. In fact, there is no chip in the world today that doesn’t touch India and the same holds true for almost all electronics systems/products. Design Linked Incentives (DLI) is a very important scheme by Govt. of India to further encourage innovation in the country. India’s electronics manufacturing industry is leveraging this design expertise and traditional products are making way for smarter and innovative ones. At electronica India and productronica India, we give utmost importance to innovation and R&D. We have a strong technology profile which is evident from the participation of R&D experts and global leaders in the ESDM sector, who develop cutting-edge technologies and provide innovative solutions for real-world problems. Our conferences, such as India PCB Tech and CEO Forum, see policymakers, manufacturers, as well as various stakeholders, exchange valuable information on market and technology trends, technical skills, and policies, to boost the success and growth of the electronics sector.

ELE Times: What is the central thought behind the amalgamation of different verticals circling the electronics and production landscape under one roof?

Electronic products, with their innovative and immersive features, touch every aspect of human lives, businesses, and economies. There is an ever-increasing demand for next-generation, cost-effective products and this is growing exponentially with the rising income levels and higher internet penetration. In the process, many technological innovations take place. To realize this vision, the industry needs a robust supply chain for increased value addition and entrepreneurship, thus making Indian electronics manufacturing globally competitive.

electronica India 2022 is co-located with productronica India 2022, IPCA Expo, MatDispens India, and Smart Cards Expo. electronica India focuses on electronic components, systems, applications, and solutions; productronica India on electronics manufacturing and production solutions; IPCA on PCB and its assembly; MatDispens on bonding solutions such as adhesives, sealants, and related dispensing equipment for industries; and Smart Cards Expo on smart card technology and applications. Together these exhibitions address the entire electronics value chain, contribute to its growth, unlock business opportunities and collaborations, and thereby offer solutions to real-world problems. We look forward to seeing you at the electronica India and productronica India 2022 to be held at the India Expo Mart, Greater Noida on 21-23 September 2022.

Mayank Vashisht | Sub Editor | ELE Times 

The post Diving Deep into India’s ESDM Industry with Bhupinder Singh appeared first on ELE Times.

A wing and a wire

EDN Network - Wed, 09/07/2022 - 17:59

I happened to notice some birds perching on overhead power lines the other day. They would come and go when driven by whatever notions and instincts govern such behavior. These wires must not have been prohibitively hot like the wires discussed earlier.

Maybe in this moment, some wire warmth even offered avian comfort (Figure 1).

Figure 1 Four perched starlings on power lines.

What these birds were not aware of, and what did them no harm in any way, was the fact that they were perched on wires carrying electric power at multi-kilovolt levels. They would blithely land on and take off from those wires over and over again which raised a question.

Most birds around here are of small to moderate size. The starlings in Figure 1 are a good example. Some birds though are really quite large, as this crow is in Figure 2.

Figure 2 A local crow.

Also too, overhead wire insulation doesn’t last forever. I’ve seen it fray.

If any two overhead wires were installed too closely together, perched birds’ wing spans might be able to straddle the distance between such wires. Two birds deciding to take off at just the same moment might make wing tip contact with horrendous consequence (Figure 3).

Figure 3 Calamity strikes when two birds spread their wings and touch wing tips.

Apart from all other power line design requirements, bird proofing of overhead wires by spacing them minimally far apart would seem to be an important factor as well.

Failing that, we might now and then be looking at sidewalk squab.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related articles:

googletag.cmd.push(function() { googletag.display('div-gpt-ad-inread'); });
googletag.cmd.push(function() { googletag.display('div-gpt-ad-native'); }); -->

The post A wing and a wire appeared first on EDN.

New Architecture Improves the Operational Effectiveness of Power Semiconductors

ELE Times - Wed, 09/07/2022 - 15:10

MOSFET improves switching frequency and conversion efficiency

Since the introduction of SMPS into the market in the 1970s, the traditional non-isolated buck regulator architecture has remained essentially unchanged, consisting of two switches or one switch and one diode. The two switches operate out of phase with one another, a “high side” series switch that conducts current to a load limited by a series inductor with stored energy, and a “low side” switch that allows current to continue to flow into the load while releasing energy from the inductor.

By the mid-1980s, silicon metal oxide semiconductor field effect transistors (MOSFET) were introduced, allowing switching frequencies to increase from 20-30 kHz to 200-300 kHz. This increased the frequency leads to a proportionate reduction in the size of the inductor. The use of FETs also increases conversion efficiency by about 10% (from typically 60-70% to 70-80%) and helps accelerate switching transitions, thereby improving EMI performance.

According to Moore’s Law, power conversion is still an analog function and cannot be scaled in silicon. Therefore, the size of silicon remains essentially unchanged. As the material improves, the filtering capacitance technology changes considerably and the capacitor structure decreases. In addition, buck regulators now use multilayer ceramic capacitors (MLCCs) as input and output filters and conductive polymer tantalum solid capacitors (POSCAPs) for bulk capacitance as required. Changes in the inductor are very little and remain wound components for as long as a few amperes or more, typically accounting for 50 percent of the total board space for power conversion. As a result, the inductor has become a problem component that determines the size and height of the overall solution. Any attempt to reduce the size of the solution by reducing inductance implies an increase in switching frequency, a corresponding decrease in efficiency, and an increase in EMI.


New power architecture pursues smaller size and higher efficiency

In pursuit of smaller sizes and higher efficiency power conversion, Murata brings a new power architecture to the market that allows switching frequencies to remain in the range of 1-2 MHz while reducing the required inductance and improving overall power conversion efficiency. Murata uses a patented two-stage architecture, including a charge pump with SMPS (also known as a switched-capacitor converter). Charge pumps are highly proprietary technologies that solve some of the fundamental problems traditionally associated with the poor efficiency and high EMI of charge pumps.

Murata’s two-stage architecture is not a single-stage buck. All work is performed by two switches and one inductor. Input and output voltages are slewed across the inductor. The whole voltage is converted into many small voltage steps in both the input and output steps. In addition, the current using the two-stage architecture flows almost continuously into the system compared to the substantial current pulses seen in the traditional single-stage buck circuits.

The net result of this two-stage architecture is that Murata’s conducted and radiated EMI architecture produces much lower EMI signature because the major source of EMI in single-stage bucks circuits is inductors, since Murata uses much less inductance in the system and therefore naturally eliminates most EMI sources.

This two-stage buck architecture is an architectural innovation using standard “off-the-shelf” FETs in very mature CMOS semiconductor processes. Since the inductor is no longer a dominant component in the bill of materials, the power conversion is reduced from 30-40% of the usual system circuit area to half without compromising efficiency. Finally, since the inductor is normally one of the tallest components in the system, this architecture can provide a thinner solution, increase packing density, and make mobile products slimmer.


Power semiconductors providing lossless voltage reduction conversion

The PE252xx series of the FlexiCP™ power semiconductor introduced by Murata is based on Murata’s proprietary ultra-high efficiency capacitor divider product from its adiabatic or lossless charge pump technology. This technology is well suited to provide a “lossless” step-down voltage conversion for the intermediate bus system to support the downstream point-of-load and achieve the highest level of efficiency, an IC based on an integrated charge pump control architecture integrated with an FET that can be connected in parallel to scale to high power system requirements.

Murata charge pumps can imagine it as a virtually lossless DC transformer with a very small volume that supports open-loop Vout tracks Vin, where Vout is a fixed ratio of Vin (i.e., ÷2, ÷3, ÷4 or ×2, ×3, ×4, etc), may have several ratios within one part (e.g., ÷2, ÷3), and the efficiency remains approximately the same irrespective of the ratio (≈97%), has low-ripple, EMI, noise phase interleaved and soft switching, and can inherently be handled in parallel.

PE25200 in the FlexiCP™ Power Semiconductor Series is a user-selectable divide-by-2 or 3 charger pump capacitor divider IC with an integrated FET that provides up to 45 watts of power at a peak efficiency of 97% and a divider ratio between 2 and 3 enables to converts 2- or 3-cell lithium platforms to 1-cell platforms in mobile computing applications.

PE25200 devices can also use front-end DC-DC converters as part of the 12Vin point-of-load design, and can be applied to FPGA, DDR memory, and ASICs that power datacenter, networking, and optical equipment. PE25200 devices are WLCSP packaged, enable, power good, frequency synchronization, cycle Skipping, have over current protection, over-temperature protection, UVLO, parallel operation, etc.

Typical applications of PE25200 include two-cell and three-cell lithium platforms, ultrabook and notebook, full-size tablets, and products designed with ultra-thin form factor designs, as well as 12VIN point of load designs in networking and telecommunications. Murata also launched the PE25200 Evaluation Kit (EVK) to allow customers to test DC-DC converters.

Another Murata power semiconductor, the FlexiCP™ PE25204, is an ultra-high efficiency front-end DC-DC converter solution that divides the input voltage into three or four voltages and provides up to 72 watts of power at a peak efficiency of 97% for the capacitor divider IC of the 48V divide-by-4 charge pump capacitor with an integrated FET.

PE25204 devices can be connected in parallel to increase output power. The input voltage ranges from 18V to 60V and is supported in divide-by-4 operation, and ranges from 18V to 45V in divide-by-3 operation. PE25204 provides products suitable for data centers, network routers, base stations and optical equipment, and is a high-power, high-efficiency solution for 48V to 12V step-down conversion applications.

PE25204 is WLCSP packaged and can use capacitors in a very thin 1 mm high solution. It supports enable, power good, frequency synchronization, over current protection, over-temperature protection, UVLO, parallel operation, and can be used in ultrabooks/notebook, data centers/servers, networking equipment, base stations, optical equipment, industrial applications, and other products. Murata also provides the PE25204 Evaluation Kit (EK25204-01), which allows customers to easily test the DC-DC converter.

Solutions to significantly reduce size/height and improve conversion efficiency

Murata’s power semiconductor FlexiBK™ PE241xx series is based on an ultra-high efficiency, 2-stage point-of-load regulator combining Murata-proprietary adiabatic or lossless charge pump technology. The technology is well suited to be applied from 2 or 3 cell battery or 12Vin point-of-load, providing step-down voltage conversion and significantly reducing the size/height of the solution while improving conversion efficiency. The IC is based on an integrated charge pump control architecture and integrated FET to configure a two-stage architecture consisting of a charge pump and a buck regulator. FlexiBK™ PE241xx series are available for evaluation kits.

The FlexiBK™ PE241xx series includes PE24101/PE24102, which supports an output channel with a maximum output current of 6A, an input voltage of 5.5V to 14.4V, and an output voltage of 0.6V to 2.0V with a switching frequency of 500 to 2000 kHz, 90% efficient, supports I2C interfaces, and is packaged with WLCSP. PE24101/PE24102 is equipped with ultra-thin and efficient 6A DC-DC MYTNA1R86RELA2RA and MYTNC1R86RELA2RA UltaBK converter modules. It adopts SMD package and supports PGOOD signal, over current protection, over-temperature protection, remote ON/OFF, output sensing, and other functions.

Murata’s another product, the FlexiBK™ PE24108, is a very small, low-profile, and ultra-high efficiency step-down DC-DC converter solution, an ultra-high efficiency, 3.3Vin, 9A, and 2-stage buck regulator IC that enables extremely low height and compact footprint through the use of innovative two-stage designs that combine capacitor divider charge pumps and dual phase buck regulators to provide an output current of 9A per stage over a wide input voltage range of 3V to 3.6V, with up to 4 phases in parallel to support 36A and 3.3V bus power supplies.

PE24108 output voltage is selected by external feedback resistors and can be adjusted by external AVS DAC to adjust between 0.37 and 0.7V for ultra-high efficiency and low-ripple performance for space-critical and noise-sensitive applications such as DSP/ASIC in optical modules or FPGA in networking equipment. PE24108 can be connected in parallel for applications with higher currents, typically optical modules, core supplies, ASIC, and FPGA.


Murata’s unique two-stage architecture for step down conversion is a highly flexible multi-stage architecture, including a combination of proprietary “pipeline” stage switched capacitor network (charge pump) and buck stage. Regardless of the conversion rate, it is almost lossless. Efficiency is largely independent of the difference between input and output voltages. It can greatly reduce the inductor size. Use low voltage FETs built on standard CMOS processes are used in the whole power supply system. Staggered charge pump operation can reduce ripple/EMI emissions and provide better transient performance. It will be one of the best options for power applications.

Courtesy: ARROW Electronics

The post New Architecture Improves the Operational Effectiveness of Power Semiconductors appeared first on ELE Times.

RF Demystified—What Is an RF Attenuator?

ELE Times - Wed, 09/07/2022 - 15:00

The attenuator is a control component, the main function of which is to reduce the strength of the signal passing through it. This type of component is generally used to balance signal levels in the signal chain, to extend the dynamic range of a system, to provide impedance matching, and to implement various calibration techniques in the end application design.


To continue the series of short discourses on RF for non-RF engineers, we will discuss IC attenuators and give some insights into their types, configurations, and specifications. This article aims to assist engineers with getting started with a wide variety of IC products and choosing the right one for an end application. Related articles in this series include: “A Guide for Choosing the Right RF Amplifier for Your Application,” “How to Easily Select the Right Frequency Generation Component,” and “RF Demystified–Understanding Wave Reflections.”

Types of Attenuators

From the key functional perspective, attenuators can be classified as fixed attenuators with an unchanging level of attenuation and variable attenuators with an adjustable level of attenuation. Depending on the form of attenuation control supported by variable attenuators, they can in turn be further classified as voltage variable attenuators (VVAs), featuring analog control, and digital step attenuators (DSAs) that are controlled digitally.

VVAs provide continuous adjustment of attenuation levels that can be set to any value within the given range. Analog variable attenuators are usually employed for automatic gain control circuits, calibration corrections, and other processing functions where smooth and precise control of a signal is required.

DSAs feature a set of discrete attenuation levels allowing for signal strength adjustments with a predetermined attenuation step size. Digitally controlled RFIC attenuators offer a control interface compatible with microcontrollers and provide a good solution to maintain functional integrity in complex designs.

Design Configurations

Attenuator ICs can be realized in GaAs, GaN, SiC, or CMOS technologies using resistors, PIN diodes, FETs, HEMTs, and CMOS transistors. Figure 1 shows three basic topologies that underly various types of attenuator design configurations: T-type, π-type, and bridged-T networks.


Figure 1. Basic attenuator topologies: (a) T-type, (b) π-type, (c) bridged-T networks.

Fixed value attenuators make use of these core topologies realized with resistors in thin film and thick film hybrid technologies to provide fixed levels of attenuation.

VVAs typically use a T-type or π-type configuration with a diode or transistor elements operated in a nonlinear resistance region. The resistance characteristics of the base elements are exploited to adjust the required level of attenuation by varying the control voltage.

DSAs usually employ multiple cascaded units representing individual bits that can be switched in or out to achieve the required level of attenuation. A few configuration examples used for DSA designs are shown in Figure 2. They include configurations with integrated SPDT switches that toggle input and output ports with the attenuating pad and a through line, switched-scaled device designs with transistors or diodes used as switchable resistances, switched-resistor configuration where the resistors can be switched in or out of the circuit, and device-embedded type design with a transistor or a diode as an integral part of the design.


Figure 2. DSA design configuration examples: (a) π-type configuration with integrated switches, (b) switched-scaled FET configuration, (c) switched-resistor configuration, (d) FET-embedded configuration.

Attenuator topologies can be arranged into a reflection- or balanced-type design schematically shown in Figure 3. Reflection-type devices use equal attenuators connected to the output of a 3 dB quadrature coupler and typically offer a large dynamic range. Balanced configurations combine a pair of identical attenuators using two 3 dB quadrature couplers and provide good VSWR and power handling capability.


Figure 3. (a) Reflection-type and (b) balanced-type attenuator design topologies.

In addition to the main design configurations described in this article, there are other types of circuits utilized for realization of IC attenuator components; however, their consideration is beyond the scope of this short article.1,2

Key Specifications

To select the right type of an attenuator for the end application, an engineer must have a good understanding of its key specifications. Apart from the attenuation capabilities and some fundamental parameters such as insertion and return loss, there are other various characteristics used to describe attenuator components of which the key ones include:

  • Frequency range (Hz): the frequencies over which the IC maintains its specified characteristics
  • Attenuation (dB): the amount of suppression in excess of the insertion loss
  • Frequency response: variation of the attenuation level (dB) across the frequency range (Hz)
  • Attenuation range (dB): the total value of attenuation offered by the component
  • Input linearity (dBm): it is usually expressed in terms of the third-order intercept point (IP3) defining a hypothetical point for the input power level at which the power of the corresponding spurious components would reach the same level of the fundamental component
  • Power handling (dBm): it is typically described in terms of the input 1 dB compression point defining the input power level at which the insertion loss of the attenuator decreases by 1 dB; the power handling characteristic is often specified for the average and peak input power levels for the steady state and hot-switching modes
  • Relative phase (degrees): a shift in phase introduced to a signal by the attenuator component

In addition to these common parameters, variable attenuators are also described by their switching characteristics that are typically expressed in ns in terms of rise and fall time, on and off time, and the amplitude and phase settling time of the RF output signal.

There are also specific characteristics inherent to each type of variable attenuators.

For VVAs, they are related to their analog control operation and include:

  • Voltage control range (V): the voltages required to adjust the attenuation level within the attenuation range
  • Control characteristics usually expressed in terms of the attenuation slope (dB/V) and the performance curves showing the level of attenuation as a function of control voltage

For DSAs, their inherent characteristics in turn include:

  • Attenuation accuracy (also known as the state error) (dB): the limit of variation in the attenuation level relative to the nominal value
  • Attenuation step size (dB): the delta between any two successive attenuation states
  • Step error (dB): the limit of variation in the attenuation step size relative to the nominal value
  • Overshoot, undershoot (dB): the level of signal transients (glitches) during state transitions

A good attenuator component is generally required to deliver flat attenuation performance and good VSWR across the operational frequency range, to offer sufficient accuracy and power handling capability, and to ensure smooth glitch-free operation with little signal distortions during state transitions or to provide linear control characteristic.


The broad diversity of IC attenuator components is certainly not limited to only those discussed in this article. We can recognize other types of ICs including frequency-dependent and phase-compensated attenuators, temperature variable attenuators, programmable VVAs with an integrated DAC, and others. However, in this article, we considered the most common categories of IC attenuators as well as discussed their main topologies and key specifications, which can help an RF designer to choose the right component for an end application.

Analog Devices provides the broadest portfolio of integrated RF components in the industry. ADI’s attenuators ICs are available in a wide range of architectures and form factors, giving designers the flexibility to select a part that best aligns with their system requirements. The parts are designed to offer the best-in-class performance and highly reliable operation to address the most demanding requirements across a wide range of applications in instrumentation, communications, military, and aerospace markets.

Anton Patyuchenko, RF Specialist, Analog Devices Inc.

The post RF Demystified—What Is an RF Attenuator? appeared first on ELE Times.

New Robots Require New Ways to Think about Processors

ELE Times - Wed, 09/07/2022 - 14:58

We’re on the cusp of a revolution in robots. After years of relatively moderate growth, sales of commercial and industrial robots are slated to grow by 25% to 35% per year over the next decade, according to Boston Consulting Group, and could reach $260 billion by 2030 to meet the demands of manufacturers, retailers and others to streamline supply chains, enhance safety and boost productivity.

Just as important, AI and other advances in technology will pave the way for more valuable, versatile robots that can take on a wider variety of more complex tasks. Traditionally fixed-function/fixed-task robots will be supplemented with computer vision and other technologies to allow them to detect production drift or variations in quality. Collaborative robots, or cobots, will work alongside humans, handling delicate materials for humans or serving as a third arm for maintenance technicians instead of being isolated behind a safety fence like fixed-function robots are today.

Autonomous mobile robots for helping run ‘lights out’ warehouses and production facilities are also on the rise as a way to reduce energy and increase safety.

Achieving this potential, however, will also require fundamental changes in computing platforms. More powerful and responsive processors for performing more complex tasks while also meeting higher levels of redundancy and safety will be needed. Economics will be a growing consideration too as use cases expand: given the need for redundancy, existing architectures tend to be expensive to implement and power hungry.

With robots often having a service lifetime that can stretch into decades, robotic microprocessors will also have to become more readily reprogrammable so they can handle new tasks and software applications.

A Blueprint for Safety

To avoid the unfolding of safety hazards, industrial robots must offer safety robustness with respect to the detection and prompt handling of faults. Evidence of such capabilities is usually shown via ISO 13849 PL d Category 3 architectural compliance which, in current industry practice, is achieved via redundant channels for all safety-related functions.

Given the need for redundancy, existing architectures that meet PL d Category 3 utilize different boards or components altogether, for duplicating safety functions. However, this strategy tends to be expensive to implement and power hungry. This poses a challenge especially, to the deployment of smaller and power constrained industrial robots.

To this end, Arm has developed a white paper that discusses two different SoC-based concepts for building articulating arm robots that meet the guidelines of ISO 13849-1/4 and IEC 61508-2, two widely adopted performance specification standards for industrial and commercial robots. The paper outlines the necessary safety standards and procedures an SoC must achieve to meet the PL d Category 3 rating under the guidelines, how redundancy can be implemented in an SoC, how to design SoCs for accurately controlling a robotic arm along degrees of motion and how to establish low-latency communication links between robots, humans, and sensors, among other topics.

When compared to current architectures, the concepts, offer a promising solution for deployments in need of small form-factors and low power consumption, while still meeting the safety robustness requirements for achieving PL d Category 3 compliance.

TÜV SÜD Rail GmbH–an international testing, inspection and certification company—examined Arm processors deployed in two different scenarios and found that both would be able to fulfill the safety requirements for PL d Category 3.

In the first, we examine an architecture of an SoC based on Arm processors such as the Arm Cortex-A53, Arm Cortex-A76 or Arm Cortex-R82 for a robot working in conjunction with robots or/or humans. Redundancy is achieved by utilizing two processor cores. The architecture is similar to existing robot designs: manufacturers that shift to Arm-based processors would be able to retain much of their original software stack.

In the second, the dual channel redundancy is achieved via two separated virtual machines running on a single Cortex A core with dual-core lockstep capability. The A core is responsible for performing functions related to actuation and handling of robot communications. A less powerful M-Class core acts as a supervisor of the main processor by notifying the main processor and managing its transition into safe states when a hazardous event is detected. The second concept is optimal for freshly new deployments where software stack portability from legacy implementations is not a concern. Furthermore, by being based on virtualization, the second concept is aligned with trends such as cloud-native deployment.

As general benefits against state-of-the-art practices, both concepts enable the deployment of more power efficient robots while maintaining a small form factor.

Addition by integration

How fast and how far will robotics evolve? One possible analogy lay in the field of automotive. Automotive digital platforms, until recently, were based around networks of largely independent microcontrollers. In the past, vehicle manufacturers would brag about the number of microprocessors their vehicles might contain.

Over the last several years, however, they have gravitated toward zonal processors, larger, more capable processors that can manage multiple functions. These zonal SoCs also often combine CPUs, GPUs, dedicated image processors, and real time processors for better performance and energy efficiency. Hardware-hardened partitions, meanwhile, permit combining critical functions along with functions such as entertainment and navigation on the same die.

Standards initiatives have likewise helped create tighter cooperation between the auto industry and the wider software industry. Although the number of processors per vehicle might be down, the lines of code in a single car—along with the overall functionality and capability of a car’s digital platform—are expected to explode.

Robots share many of the same characteristics as vehicles. Processing must be performed in real time and the number of variables and input to be considered is growing exponentially. Manufacturers have to build a path for future applications and services and, at the same time, ensure safety is never compromised. Just as important, hardware and software providers have to work within often tight thermal, volumetric and economic envelopes. Upgradeability is also paramount: products have to be capable of state-of-the-art functionality and capable of operating for 20 years or more.

Robotics companies and their customers are at a turning point in their history. Arm is dedicated to developing a computing platform to help them shift from the world of static, fixed-function robots to one where factories can be more flexible and versatile to meet the changing needs of the economy. This white paper is one of many steps we are taking. And, if you find yourself drawn to robotics, please send me a note.

The post New Robots Require New Ways to Think about Processors appeared first on ELE Times.

Optical Wafer Defect Inspection at Nano Scale and Beyond

ELE Times - Wed, 09/07/2022 - 14:57

Defect inspection scientists from Huazhong University of Science and Technology, Harbin Institute of Technology, and The Chinese University of Hong Kong make a thorough review of new perspectives and exciting trends on the foundation of former great reviews in the field of defect inspection methods. The review focuses on three specific areas: (1) the defect detectability evaluation, (2) the diverse optical inspection systems, and (3) the post-processing algorithms.

The Nanoscale and Optical Metrology Research Center (NOMRC) led by Prof. Shiyuan Liu and Prof. Jinlong Zhu from Huazhong University of Science and Technology and their collaborators from Harbin Institute of Technology and The Chinese University of Hong Kong wrote the first systematic review to introduce the research background, discuss the latest progress and the trend of optical wafer defect inspection. This review has disclosed that cutting-edge techniques such as nanophotonics, optical vortices, computational imaging, quantitative phase imaging, and deep learning can make a profound impact on sub-10 nm defect inspection. The work may pave new avenues for the field of semiconductor wafer defect inspection.

Prof. Jinlong Zhu and Prof. Shiyuan Liu say that “the ever-shrinking features and space on patterned wafers would dramatically strain the capabilities of all the current metrology and inspection solutions in balancing sensitivity, specificity, process speed, and capture rate.”

Optical far-field wafer inspection remains one of the workhorses for defect inspection in the fab. In a conventional defect inspection tool, the defects are captured by comparing circuit pattern images of adjacent dies. The first author of the review article, Prof. Jinlong Zhu says that “the key to defect inspection is not resolution, but the signal-to-noise ratio (SNR) and contrast. The improvement of SNR and contrast highly depends on sophisticated instruments, advanced modeling architectures, and post-processing algorithms, all of which drove us to make a comprehensive review of wafer defect detection methods from the following three aspects: (1) the defect detectability evaluation, (2) the diverse optical inspection systems, and (3) the post-processing algorithms.”

“It is of great importance to carry out defect detectability assessment for a specific type of inspection tools for advanced nodes,” co-first author Dr. Jiamin Liu explained. “In fact, the evaluation of defect detectability usually involves the formulation of quantitative rules for the SNR of the defect scattering signals, the development of simulation tools for defect scattering signals modeling, and the analysis of defect SNR. We found the defect SNR depends significantly on material and defect topology.”

The conventional approaches in optical defect inspection, such as the amplitude-based one alongside its post-processing algorithms, have been thoroughly discussed. The novel inspection mechanisms including phase-, orbital angular momentum-, terahertz wave-, and hyperbolic Bloch modes-based ones, have been highlighted to remind readers of their potentials in opening up new directions in the field. Besides, X-ray ptychography, the only optical method that can directly image both surface and undersurface sub-20 nm defects for the entire wafer, has also been reviewed and prospected in detail in the article. X-ray ptychography has the potential to penetrate the field by providing revolutionary 3D resolution and sensitivity once the drawbacks include the synchrotron X-ray light source, a massive amount of data, and the low speed being conquered in the future.

“Whether it is the simplest image difference operator or the complex image synthetic algorithm or even the deep learning algorithms, these post-processing algorithms play a critical role in optical defect inspection in terms of improving SNR and contrast of defects. Therefore, we provided a detailed discussion of post-processing algorithms involved in patterned wafer defect inspection with a specific focus on the advantages and disadvantages of deep learning algorithms.

Prof. Jinlong Zhu says that they “do believe that optical defect inspection on patterned wafers will remain a challenging but interesting topic that urgently needs to be addressed.

The post Optical Wafer Defect Inspection at Nano Scale and Beyond appeared first on ELE Times.

Perovskite Solar Cell with High Efficiency and Stability

ELE Times - Wed, 09/07/2022 - 14:31

Researchers at the U.S. Department of Energy’s (DOE’s) National Renewable Energy Laboratory (NREL) have made a technological breakthrough and constructed a perovskite solar cell with the dual benefits of being both highly efficient and highly stable.

The work was done in collaboration with scientists from the University of Toledo, the University of Colorado-Boulder, and the University of California-San Diego.

A unique architectural structure enabled the researchers to record a certified stabilized efficiency of 24% under 1-sun illumination, making it the highest reported of its kind. The highly efficient cell also retained 87% of its original efficiency after 2,400 hours of operation at 55 degrees Celsius.

Perovskite, which refers to a crystalline structure, has emerged in the last decade as an impressive means to efficiently capture sunlight and convert it to electricity. Research into perovskite solar cells has been focused to a large degree on how to increase their stability.

“Some people can demonstrate perovskites with high stability, but efficiency is lower,” said Zhu, a senior scientist in the Chemistry and Nanoscience Center at NREL. “You ought to have high efficiency and high stability simultaneously. That’s challenging.”

The researchers used an inverted architecture, rather than the “normal” architecture that has to date yielded the highest efficiencies. The difference between the two types is defined by how the layers are deposited on the glass substrate. The inverted perovskite architecture is known for its high stability and integration into tandem solar cells. The NREL-led team also added a new molecule, 3-(Aminomethyl) pyridine (3-APy), to the surface of the perovskite. The molecule reacted to the formamidinium within the perovskite to create an electric field on the surface of the perovskite layer.

“That suddenly gave us a huge boost of not only efficiency but also stability,” Zhu said.

The scientists reported that 3-APy reactive surface engineering can improve the efficiency of an inverted cell from less than 23% to greater than 25%. They also noted that reactive surface engineering stands out as an effective approach to significantly enhance the performance of inverted cells “to new state-of-the-art levels of efficiency and operational reliability.”

The post Perovskite Solar Cell with High Efficiency and Stability appeared first on ELE Times.

India, Spearheading to Revitalize its Electronics Manufacturing Landscape

ELE Times - Wed, 09/07/2022 - 14:03

Gain Insights into India’s Electronics Manufacturing Mission

What will it take to transform the Indian ESDM industry from its existing $120 billion to $300 billion in the next 5 years? Come and discover the latest insights at electronica India and productronica India 2022.

Electronics manufacturing in India has grown considerably over the last few years. This can be seen in increased mobile phone exports by nearly 75% from last fiscal. Also, domestic manufacturing has almost doubled to Rs. 5.5 lakh crore in 2021 from Rs. 2.43 lakh crore in 2015-16. There is an insatiable appetite for next-generation, cost-effective electronic products, and this will increase exponentially in the next few years with rising income levels and higher internet penetration.

India is one of the largest consumers of electronic products in the world and is likely to be the fifth largest consumer in the world by 2025. Most Indians today use smartphones, tablets, laptops, wearables, etc. Indian households use a wide range of electronic appliances such as smart televisions, washing machines, refrigerators, air conditioners, home assistants, etc. This domestic demand will only surge over the next few years with increasing income levels, higher internet penetration, and 5G connectivity.

According to MeitY, the total electronics market in India in 2019-20 was valued at around $120 billion. The Government of India (GOI) has outlined a $300 billion vision for this industry by 2026 which includes $180 billion from local demand and the rest from exports.   But a thriving supply chain is the urgent need of the hour. To leverage the multiplier effect of investments in this sector and the vast ocean of global opportunities, a robust supply chain must be created within the country. This will not only increase employment and boost the Indian economy but will make the domestic industry globally competitive in the long term.

The Government of India has shown the right intent to reduce dependency on imports and make India self-reliant by implementing schemes such as the NPE 2019, PLI for large-scale electronics manufacturing, SPECS, EMC 2.0, etc.  Each of these schemes has been judiciously created to boost large-scale production, manufacturing clusters, and a robust supply chain ecosystem in the country.

“India has been one of the front runners amongst all the emerging nations from an economic development standpoint. A major credit of India’s upward trend in GDP growth can be attributed to the electronics sector. This growth is primarily driven by the increasing demand and consumption of electronic products. Electronics manufacturing in India has grown considerably over the last few years. This can be seen in increased mobile phone exports by 75% from the last fiscal. Also, domestic manufacturing of electronic products almost doubled from $37.1 billion in 2015-16 to $74.7 billion in 2020-21. India is expected to become a major semiconductor manufacturing nation in the next 5-6 years. We are moving in the right direction to realize this decades-old dream”, says Bhupinder Singh, CEO, Messe Muenchen India.

Recently, Rajeev Chandrasekhar, Minister of State for Electronics & Information Technology and Skill Development & Entrepreneurship launched a report titled as Globalise to Localise: Exporting at Scale and Deepening the Ecosystem are Vital to Higher Domestic Value Addition’.  The report prepared by India Council for Research on International Economic Relations (ICRIER), in collaboration with India Cellular and Electronics Association (ICEA) explores how India can achieve an electronics production target of US$300 billion and exports of US$120 by 2025-26.  “The Government is laser-focused on achieving the target of 300 billion USD electronic production by 2026. And for this, we have always emphasized strengthening our domestic manufacturing ecosystem to make India more resilient to supply chain disruptions. Our aim is to emerge as a reliable and trusted partner in Global value chains”, says Rajeev Chandrasekhar.

Launching the report, he said that it is very timely and will help the Government identify the challenges that are to be met and the strategies that are to be adopted to achieve this target.

The Minister said that India has succeeded in systematically building a framework and a strategy that has clearly outlined our goals of a 300 bn electronics manufacturing ecosystem with 120 bn dollars of exports by 2026.

Talking about the journey of the Electronics sector in India in the last some years, the Minister said that

Electronics in India have travelled a long way since 2014. We were, in 2014, a country that was increasingly dependent not just on petroleum imports but also on Electronics imports. Systematically Prime Minister Shri Narendra Modi over the years has built back an electronics sector. Today we are, as a consequence of policies of the government led by Prime Minister Shri Narendra Modi, a 76 bn dollar manufacturing economy with 16 bn dollars of exports, with a target of 21 to 25 bn dollars of exports in the next year. But most importantly by 2026, we have clearly laid out the goal of 300 bn dollar manufacturing with a 120 bn dollar of exports. That strategy talks about broadening and deepening the electronics ecosystem.

Highlighting the shift in global value chains in recent years, Rajeev Chandrasekhar said that post-COVID the value chains of electronics are undergoing deep tectonic irreversible changes. It presents to India, the current momentum and opportunity which is explained by the 120 bn dollars export target that India has for 2026.

Rajeev Chandrasekhar further added that this report postulates that we must export aggressively to reach the scale in electronics manufacturing. In addition to domestic production, supplies, and domestic consumption, exports are an important way to get the scales of the other economies that are competing with us. Exports will create a network effect of creating the supply chain interests, and supply chain investments that in turn will increase the value added in the Indian electronics segment.

Current challenges

As per the 2019-20 valuation, $76 billion worth of products were manufactured domestically, and the rest were imported. The domestic value addition is only 15-20 percent, which is an existing challenge for the industry. When it comes to Printed Circuit Board Assemblies (PCBAs), 40 percent of the value is in components, which includes semiconductors, passives, connectors, display, battery, etc. India does not have a component manufacturing ecosystem, and hence, Indian manufacturers miss out on this 40 percent value addition as components are imported from other countries.

The policy initiatives of the government have had a positive effect on manufacturing. However, challenges related to infrastructure, tariffs, and Free Trade Agreements must be resolved for globally competitive, resilient, and massive-scale manufacturing in India.

A thriving supply chain is the urgent need of the hour. To leverage the multiplier effect of investments in this sector and the vast ocean of global opportunities, a robust supply chain must be created within the country. India still has a long road ahead. If India aims to become a global epicentre for electronics manufacturing, it will require attractive incentives for global companies to set up their base here. Though the financial incentives are encouraging, India suffers from land acquisition complications, lack of local component ecosystem, supply chain challenges, high cost of power supply and logistics, etc. The lack of world-class semiconductor fab units in the country is another major challenge.

These are some of the current issues that will be discussed at this year’s edition of electronica India and productronica India 2022. The much-awaited CEO Forum at these trade fairs will bring together industry leaders to speak on ‘Shifting from Assembly to Deep Manufacturing – Building a $300 Billion ESDM Industry by 2026’. Another sought-after forum is the India PCB Tech conference where experts will throw light on ‘Roadmap for Developing PCB Eco-System in India – Vital for an Aatmanirbhar ESDM Sector’.

Policy initiatives in the Semiconductor Industry

In December 2021, GOI announced a $10 billion scheme to promote this ecosystem, and Indian companies have sufficiently established their strengths in fabless semiconductor design. Now is the time to leverage these strengths, build synergies, and scale semiconductor manufacturing (wafer fab) and outsourced semiconductor assembly and testing (OSAT) in the country. This requires effective knowledge-sharing, engagement, and alignment of interests amongst various players, be it wafer fabs, OSAT companies, equipment suppliers, raw materials, specialty gases providers, water treatment companies, etc.

Semiconductor design and manufacturing has emerged as a sector where Indian ESDM companies can prove their capabilities on the global stage. Therefore, under the Design Linked Incentive (DLI) scheme, which is a part of the larger Production Linked Incentive (PLI) scheme, MeitY plans to develop twenty domestic companies involved in semiconductor design and help them achieve a turnover of more than Rs 1500 crore over the next five years. Another worthwhile initiative is the Chip to Startup program through which MeitY plans to train 85,000 highly skilled engineers in the fields of Very Large-Scale Integration and Embedded System Design. It further plans to develop 175 ASICS (Application Specific Integrated Circuits), Working Prototypes of 20 System on Chips (SoC) and IP Core repository over a period of five years.

To leverage these myriad opportunities presented by global demand-supply trends as well as Indian policy initiatives, electronica India and productronica India 2022 will present the India Semiconductor Conclave, a specialized platform for Indian and global companies to brainstorm and align interests in the field of semiconductor manufacturing and design. The industry and government can look forward to this as a specialized platform for knowledge and expertise sharing, effective interfacing between buyers and suppliers across the value chain, and policy-level discussions to establish India as a global destination for semiconductors – both design and manufacturing. This year the India Semiconductor Conclave will include conferences on India’s semiconductor ecosystem and display manufacturing, as well as a special pavilion by MeitY on policy interventions for these segments. This platform will increase in scale over the years to come.

As the Indian ESDM ecosystem increases its contribution to the Indian economy and becomes a formidable player on the global stage, there is no better place to catch all the action live than electronica India and productronica India 2022, to be held from 21-23 September 2022, at the India Expo Mart, Greater Noida.

Must-attend programs at electronica India and productronica India 2022

India Semiconductor Conclave
–          Conference on display manufacturing by ICEA
–          Conference on semiconductor ecosystem by IESA
CEO Forum
India PCB Tech
Buyer-seller forum
PCB Start-up Zone

Mayank Vashisht | Sub Editor | ELE Times

The post India, Spearheading to Revitalize its Electronics Manufacturing Landscape appeared first on ELE Times.

How parasitics create an unexpected EMI filter resonance

EDN Network - Wed, 09/07/2022 - 12:30

Electromagnetic interference (EMI) has a reputation for being one the most difficult aspects in power-supply designs. I think that this reputation comes, in large part, from the fact that most EMI-related challenges are not things that can be solved by looking at the schematic. This can be frustrating, since the schematic serves as the central place where the engineer goes to understand what the circuit does. Sure, you know that there are relevant functions in the design that are not in the schematic—things like code.

You also know that the schematic doesn’t represent things like printed wiring board parasitics. However, in EMI, parasitics like these can have dominating effects in your ability to meet the requirements, forcing you to have the necessary experience to recognize what types of parasitics can positively or negatively impact the EMI spectrum. This Power Tip article will explore how these types of parasitics can create an unexpected EMI filter resonance in a gallium nitride (GaN)-based onboard charger (OBC) for an electric vehicle (EV).

Figure 1 shows a high-level system representation of the OBC. Its primary function is grid-to-vehicle voltage and current battery charging. A secondary function is vehicle-to-grid power flow so that the EV can supplement renewable energy sources that might have a fluctuating peak capacity.

Figure 1 The schematic shows a high-level system representation of the onboard charger (OBC). Source: IEEE

Now, let’s turn our attention to the EMI considerations inside the OBC.

Onboard charger’s EMI review

EMI includes differential-mode (DM) and common-mode (CM) noise. For an OBC system, DM noise is mainly generated by the input current of the power factor correction (PFC), while CM noise can result from both the PFC and the conductor-inductor-inductor-inductor-capacitor (CLLLC). Figure 2 shows the cooling solution (cold plate) for the OBC in the lower right corner of the schematic. The cold plate is critical in preventing the components from overheating; however, its presence introduces parasitic capacitance that affects the EMI.

Figure 2 Parasitic effects causing EMI are shown in the lower right corner of the schematic. Source: Texas Instruments

As shown in Figure 2, there are parasitic capacitances between the switching nodes to the cold plate, between the primary and secondary grounds to the cold plate, and between the primary and secondary winding of the CLLLC transformer. Those parasitic capacitances can generate or affect CM noise-current levels in the system.

With estimated parasitic capacitances, simulations show that in the worst case, the bare DM noise with only the 2.2-µF input capacitor (CX1) is about 110 dBµV. Likewise, the bare CM noise without any CM filter is about 115 dBµV at about 350 kHz. Designing a two-stage EMI filter helps attenuate EMI noise below the Comité International Spécial des Perturbations Radioélectriques (CISPR) 32 standard.

The common-mode impedance of LCM1 and LCM2 at 350 kHz is about 3 kΩ. Their leakage inductances are about 6.4 µH, which are used for DM noise attenuation. CX1 and CX2 are 2.2-µF film capacitors for DM noise attenuation, and CY1, CY2, CY3 and CY4 are 4.7-nF ceramic capacitors for CM noise attenuation.

Ideally, with the designed filter, both the bare CM noise and bare DM noise should be attenuated by more than 65 dBµV, and the EMI noise should meet the CISPR 32 standard. There are still some practical challenges to address, however.

EMI filter resonance

EMI filters are filled with resonances by design. In fact, it is these resonances that enable the filter to attenuate noise and enable a system to pass the EMI standard. Figure 3 shows a typical attenuation curve for an EMI filter. Notice that at frequencies above 100 kHz, the filter does a nice job of reducing amplitude. There are some resonances below 100 kHz, however, that could be quite problematic if they exist on top of a switching frequency.

Figure 3 This is how typical EMI filter attenuation looks like for an onboard charger. Source: Texas Instruments

Obviously, no one would intentionally place a resonance at the switching frequency, but interconnect impedances, component parasitics or both can sometimes push the system to operate in an unintentional way.

Figure 4 shows a slightly modified EMI filter compared to Figure 2. The differences are in the components in red. LP1 and LP2 represent the parasitic inductance of the interconnect between the EMI filter and the PFC input. The presence of LP1 and LP2 required some local capacitance for the PFC current to flow through. Therefore, moving CX1 to the input of the PFC and adding CX0 increased the attenuation of the filter. The four elements in red combine together to create a resonance at 240 kHz. In this design, 240 kHz is the conversion-combined switching frequency of the two-phase PFC. This resonance is going to amplify the switching current and subsequently make the EMI worse at this frequency.

Figure 4 The EMI filter is shown with a resonance at the switching frequency. Source: Texas Instruments

Figure 5 shows the time-domain waveforms of the AC line current flowing through LP1 in magenta, along with the AC input voltage in blue. Notice that the current has a significant 240-kHz sine wave with a 28-A peak-to-peak amplitude. This sine wave is the direct result of the triangular PFC current flowing through the unintended amplifier created by the red components in Figure 4.

Figure 5 The time-domain waveforms of the AC line current are shown flowing through LP1 in magenta. Source: Texas Instruments

Damping a resonance like this can be challenging, since the necessary damper will typically require an inductor or capacitor larger than those used in the circuit. Another possible solution might be to lower the inductance of the interconnect so that the resonance is no longer on top of the switching frequency. In theory this sounds good, but practically speaking, that interconnect is there for a reason; so, making it smaller isn’t really viable.

Another option is to consider the necessity of retaining both CX0 and CX1. You can’t remove CX1 since the PFC requires some local input capacitance for the high-frequency current. However, CX0 is there to increase the capacitance, with the intent of increasing the attenuation. Removing CX0 improved the EMI by approximately 6 dBµV. The amplitude is reduced by 50% and a large percentage of the require attenuation (65 dBµV) needed to pass the standard. That’s a pretty good deal.

Two design takeaways

The takeaway here is twofold. The first is the original premise: the schematic doesn’t tell the whole story for EMI. In this case, there was an unintended resonance caused by interconnect inductance that amplified the switching frequency noise. Recognizing the root cause of the problem is always the most critical step in debugging.

The second takeaway is that sometimes less of a normally good thing (filter capacitors) is better. You can usually address EMI issues by adding components, but in this case, the presence of a component makes the issue worse. Therefore, by removing CX1, we were able to reduce the size of the filter, lower the system cost, and improve the EMI.

Brent McDonald is a system engineer in the Power Supply Design Services team at Texas Instruments.

Related Content

googletag.cmd.push(function() { googletag.display('div-gpt-ad-native'); }); -->

The post How parasitics create an unexpected EMI filter resonance appeared first on EDN.

Energy-efficient Devices using Gallium Nitride

ELE Times - Wed, 09/07/2022 - 10:18

Engineering researchers have created new high-power electronic devices that are more energy efficient than previous technologies. The devices are made possible by a unique technique for “doping” gallium nitride (GaN) in a controlled way.

“Many technologies require power conversion—where power is switched from one format to another,” says Dolar Khachariya, a researcher on the work and a former Ph.D. student at North Carolina State University. “For example, the technology might need to convert AC to DC, or convert electricity into work—like an electric motor. And in any power conversion system, most power loss takes place at the power switch—which is an active component of the electrical circuit that makes the power conversion system.”

“Developing more efficient power electronics like power switches reduces the amount of power lost during the conversion process,” says Khachariya, who is now a researcher at Adroit Materials Inc. “This is particularly important for developing technologies to support a more sustainable power infrastructure, such as smart grids.”

“Our work here not only means that we can reduce energy loss in power electronics, but we can also make the systems for power conversion more compact compared to conventional silicon and silicon carbide electronics,” says Ramón Collazo, researcher and an associate professor of materials science and engineering at NC State. “This makes it possible to incorporate these systems into technologies where they don’t currently fit due to weight or size restrictions, such as in automobiles, ships, airplanes, or technologies distributed throughout a smart grid.”

The researchers outlined a technique that uses ion implantation and activation to dope targeted areas in GaN materials. In other words, they engineered impurities into specific regions on GaN materials to selectively modify the electrical properties of the GaN only in those regions.

In their new paper, the researchers have demonstrated how this technique can be used to create actual devices. Specifically, the researchers used selectively doped GaN materials to create Junction Barrier Schottky (JBS) diodes.

“Power rectifiers, such as JBS diodes, are used as switches in every power system,” Collazo says. “But historically they have been made of the semiconductors silicon or silicon carbide because the electrical properties of undoped GaN are not compatible with the architecture of JBS diodes. It just doesn’t work.”

“We’ve demonstrated that you can selectively dope GaN to create functional JBS diodes and that these diodes are not only functional but enable more power efficient conversion than JBS diodes that use conventional semiconductors. For example, in technical terms, our GaN JBS diode, fabricated on a native GaN substrate, has record high breakdown voltage (915 V) and record low on-resistance.”

“We’re currently working with industry partners to scale up production of selectively doped GaN, and are looking for additional partnerships to work on issues related to more widespread manufacturing and adoption of power devices that make use of this material,” Collazo says.

The post Energy-efficient Devices using Gallium Nitride appeared first on ELE Times.

Stable High-efficiency Perovskite Solar Cells Prime Jump Over

ELE Times - Wed, 09/07/2022 - 10:17

Solar cells manufactured from materials known as “perovskite” are catching up with the efficiency of traditional silicon-based solar cells. At the same time, they have the advantages of low cost and short energy payback time. However, such solar cells have problems with stability—something that researchers at Linköping University, together with international collaborators, have now managed to solve. The results are a major step forwards in the quest for next-generation solar cells.

“Our results open new possibilities to develop efficient and stable solar cells. Further, they provide new insights into how the doping of organic semiconductors works,” says Feng Gao, professor in the Department of Physics, Chemistry, and Biology (IFM) at Linköping University.

Perovskites are crystalline materials with huge potential to contribute to solving the world’s energy shortage. They are cheap to manufacture, with high efficiency and low weight. However, perovskite solar cells can degrade quickly, and it has not been possible to build high-efficiency perovskite-based solar cells with the required stability.

“There seems to be a trade-off between high efficiency and stability in perovskite-based solar cells. High-efficiency perovskite solar cells tend to show low stability and vice versa,” says Tiankai Zhang, a postdoc at IFM.

When solar energy is converted into electricity in perovskite-based solar cells, one or more charge transport layers are usually needed. These lie directly next to the perovskite layer in the solar cell. The organic charge transport layers often need auxiliary molecules in order to function as intended. The material is described as being “doped”.

One doped transport layer called Spiro-OMeTAD is a benchmark in perovskite solar cells and delivers record power conversion efficiencies. But the present method used to dope Spiro-OMeTAD is slow and causes the stability issue of perovskite solar cells.

“We have now managed to eliminate the trade-off that has hindered development, using a new doping strategy for Spiro-OMeTAD. This makes it possible for us to obtain both high efficiency and good stability,” says Tiankai Zhang.

Another principal author of the article, Feng Wang, is a junior lecturer at IFM. He points out that perovskite-based solar cells can be used in many ways, and have many areas of applications.

“One advantage of using perovskites is that the solar cells made are thin, which means that they are light and flexible. They can also be semi-transparent. It would be possible, for example, to apply perovskite-based solar cells onto large windows, or building façades. Silicon-based solar cells are too heavy to be used in this way,” says Feng Wang.

The post Stable High-efficiency Perovskite Solar Cells Prime Jump Over appeared first on ELE Times.

Inspecting an Insteon (and X10) controller

EDN Network - Tue, 09/06/2022 - 18:54

Back in July, I disassembled and detailed the internals of a SmartLabs 2412S Power Line Modem (PLM). While PLMs provide a bridge between a home automation controller (hub or other) and various X10-and-Insteon powerline (as well as Insteon wireless, whether directly or via a powerline-to-wireless intermediary) devices, they contain only minimal native processing and memory facilities. The bulk of these resources alternatively reside in the controller and/or (with a defeatured hub) the cloud server to which it’s Internet-connected.

In that prior writeup, I mentioned that SmartLabs had (only temporarily, as it turns out) abruptly turned out the lights, locked the doors, and powered down the servers in response to a fiscal crisis, in the process crippling the home automation networks of the customers of its cloud-centric hubs. In response, alternative standalone controllers such as those from Universal Devices garnered even more interest than they’d had previously. My Insteon network had been mothballed for more than a decade, since I’d moved from California to Colorado, but I still had (among other things) a never-used and rare Universal Devices ISY-992i/IR PRO controller (the successor ISY-994i series was more common) which I sold on eBay.

Today’s teardown victim is the ISY-992i/IR PRO’s predecessor, an ISY-99i/IR PRO. This unit was the nexus of my personal Insteon network for several years, where it performed error-free and otherwise robustly. The “IR” in the product name references the fact that this particular unit is capable of being controlled not only from a networked computer via its Ethernet port but also via an infrared remote control that supports Philips RC-5 codes. “PRO” references the fact that this device integrates enough memory to support up to 1,024 device/scene combinations and 1,000 programs. I’ll as-usual begin with some overview shots, in a couple of cases with the device accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes.

While the ISY-99i/IR PRO and ISY-992i/IR PRO look identical from the front, the back sides (therefore the top side markings) are notably different:

The ISY-99i/IR PRO includes one RJ-45-based port (A), intended to connect to (and, depending on the PLM model, potentially also capable of being powered by) a PLM, and one DB-9-based port (B), intended for initial configuration for users without a DHCP-enabled network as well as for advanced PC-based troubleshooting. The successor ISY-992i/IR PRO offers two RJ-45 ports, with the DB-9 connector instead labeled “Console”. In both cases, there’s also a barrel plug power input (for when powering via the PLM isn’t supported) and an Ethernet connection.

Whereas the embedded SD card, which we’ll see shortly, is user-accessible via a left-side cover on the ISY-992i/IR PRO, it’s not on the ISY-99i/IR PRO:

And not only is Universal Devices based in Encino, CA, manufacturing also takes place in the United States:

Time to peek inside, a straightforward undertaking after removing the two Philips screws on either side of the unit:

Completely removing the PCB from the chassis is equally straightforward, subsequent to the extraction of four more screws (only two of which are immediately obvious from a glance at the prior photo; revisit the earlier bottom overview image to discern their locations):

This is, I must say, one of the cleanest PCBs I’ve come across. No Faraday cages, no epoxy “blobs” or other tricks to obscure IC identities, only straightforwardly laid out and labeled chips. At bottom is a Samsung K4S641632K-UC75 64 Mbit SDRAM. Above it are an LCX244 octal non-inverting buffer/line driver (manufacturer unknown) and an SST (now Microchip) SST39VF040 4 Mbit EEPROM-derived flash memory. And to their right is the “brains” of the device, a Freescale (now NXP Semiconductors) MCF5270CVM150 ColdFire v2 32-bit RISC SoC.

Continuing toward the top of the PCB, in the upper right corner there’s a Davicom DM9161 physical layer transceiver, implementing the device’s 10/100 Mbit Fast Ethernet facilities. And in close proximity to the RJ-45 and DB-9 connectors, both supporting serial port connectivity, is (unsurprisingly) a Texas Instruments MA3243 (PDF) 3-V to 5.5-V multichannel RS-232 line driver, curiously alongside a Maxim Integrated MAX3078 RS-422/RS-485 interface IC.

About that SD card; it pops right out (and back in) via a standard spring-loaded-and latched eject-and-insert mechanism:

It’s a fairly conventional 128 Mbyte storage device, as it turns out. Quoting from Universal Devices’ documentation:

The ISY has two different memory storage locations. First is the base memory [EDITOR NOTE: the already shown SST flash memory chip soldered to the PCB) where the ISY has some of the basic code like its boot loader, SD file system, and networking facilities. The other memory is the SD card which is where upgraded admin firmware and user files are stored.

Before flipping the PCB over, let’s look at it from sideways perspectives. Front first: the IR module is implemented on a “daughter card” for system manufacturing flexibility, with the main board therefore supporting both IR and non-IR product variants:

Now for the back:

And the two sides:

Finally, let’s see what’s underneath. Not much, as usual, aside from a bunch of visible traces:

I’d lost touch with Universal Devices and its CEO, Michael Kohanim, in recent years, so I was pleasantly surprised to unintentionally come across them several times in recent months. First off, the guy who bought (and then returned to me for refund) the SmartLabs 2412S PLMs I mentioned back in July told me that he had been in communication with the very same Michael Kohanim, who helped him with some remote debugging in striving to figure out whether they still worked (and apparently even found him a functional PLM after mine didn’t pan out).

And then I heard through press coverage that Kohanim had actually put in a bid to buy and resurrect SmartLabs after that company abruptly shut down in late April. Universal Devices had always “punched well above its weight”, from my experience; LinkedIn reports that there are only four full-time employees. It’s nice to hear that a decade after my last in-depth interactions with them, they’re still alive and kicking; I wish them the best going forward. And now it’s over to you, dear readers, for your thoughts in the comments!

Brian Dipert is Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

googletag.cmd.push(function() { googletag.display('div-gpt-ad-inread'); });
googletag.cmd.push(function() { googletag.display('div-gpt-ad-native'); }); -->

The post Inspecting an Insteon (and X10) controller appeared first on EDN.

Frequency doubler with 50 percent duty cycle

EDN Network - Tue, 09/06/2022 - 17:41

Here is a simple frequency doubler circuit that produces a square wave output with a precise 50 percent duty cycle. There are similar circuits in the literature [References 1, 2, 3] which require adjustments or selection of some components to set the duty cycle to 50 percent.

With this circuit, just a matched pair of resistors produces a 50 percent duty cycle output pulse, and, in addition, the pulse duty cycle is not affected by changes in the supply voltage.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The circuit can be seen in Figure 1. It has been tested from 500Hz to 2.8MHz, and I am confident it will work at higher frequencies if you use a faster one-shot for U1. 

 Figure 1 The frequency doubler circuit with a 50 percent duty cycle.

The system uses feedback via op amp U5A to force the one-shot to produce an output square wave with a nominal average value of 2.5 volts that equals the DC reference established by the matched pair (or a set of precision resistors), R26 and R27.

The reference for op amp U5A is derived from the same supply voltage that is used by  one-shot U1A which swings rail-to-rail because it drives a very light load. The result is that the average value of the one-shot’s output and the value of the reference voltage change by the same proportion for supply voltage changes, so the duty cycle does not change.

Exclusive NOR gate U4 is used to buffer the square wave input signal and to double the frequency of the signal. The square wave signals at the input of U4D are delayed relative to each other by two gate delays. The output is a nominal 20 nanosecond pulse train having twice the frequency of the input square wave. These pulses trigger the one-shot to produce doubled output frequency pulses, and the feedback loop forces the duty cycle of the pulses to 50 percent.

Transistors Q5 and Q6 and associated components are a constant current source which charges capacitor C11 at the RX/CX input of the one-shot. The current is limited to about 5 milliamps, which is the max that is implied by the data sheet. My LTspice simulation would not run without the current limiting circuitry. The current limiting also prevents the input of the one-shot from being hit with a large current surge at turn-on or when capacitor C11 is switched for different frequency ranges.

The value of capacitor C11 is left to the user’s discretion 

To my surprise, the circuit will operate with C11 omitted! At low frequencies, the current supplied by the constant current source is in the nanoamps range, which may be in the range of component leakage currents in some applications, and this may cause erratic circuit operation. So, omit C11 with caution.

Omitting C11 may be okay in the frequency range of 1MHz and above. Here, the input capacitance of the one-shot plus stray circuit capacitance may be sufficient.

Table 1 shows the observed frequency range of operation for several values of C5.

For proper operation, the input must be a square wave with 50 percent duty cycle. A pulse with something other than a 50 percent duty cycle can be used if the additional circuitry is implemented (see Figure 1). The additional circuitry produces an output square wave with 50 percent duty cycle that is used as the input to the frequency doubler.

A Schmitt trigger and quad nand gate U3 are used to provide orderly startup for the frequency doubler section. The frequency doubler does not start up until the pulse input is nearly at 50 percent duty cycle.

I have not built this additional circuitry, but I have simulated it with LTspice, it is largely a duplicate of the frequency doubler circuit which I did build and test. 

Reference 4 is an alternative frequency doubler circuit which operates with a pulse input with less than a 50 percent duty cycle, and provides a square wave output with a 50 percent duty cycle.


  1. Wide-range pulse-shaping circuit gives square waves with 50% duty cycle
    R. M. Stitt and R. L. Morrison, Burr-Brown Research Corp., International Airport Industrial Park, Tucson, Ariz.
    400 Ideas for Design volume 3, 1976, page 178.
  2. One-shot with feedback loop maintains constant duty cycle
    H. P. D. Lanyon, Worcester Polytechnic Institute, Worcester, Mass.
    Electronics Designer’s Casebook, page 122. (No volume number or published date given.)
  3. Frequency-doubler produces square-wave output
    Robert L. Taylor, I & F Electronics, Nashville, Tenn.
    Electronics Designer’s Casebook Number 1, page 23. (No published date given.)
  4. Convert any signal to exactly 50% duty cycle
    Jim McLucas
    EDN Design Ideas, June 25, 2013

Jim McLucas retired from Hewlett-Packard Company after 30 years working in production engineering and on design and test of analog and digital circuits.

Related Articles

googletag.cmd.push(function() { googletag.display('div-gpt-ad-native'); }); -->

The post Frequency doubler with 50 percent duty cycle appeared first on EDN.


Subscribe to Кафедра Електронної Інженерії aggregator - Новини світу мікро- та наноелектроніки