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Application For Maker Faire Rome 2024: Deadline June 20th

Open Electronics - Wed, 06/05/2024 - 13:25

Learn More About the Ideas, Makers + Projects at Maker Faire Rome 2024 Developing a multitude of technologies for the sustainability of the planet and for environmental care is imperative today. The depletion of natural resources and the need to conserve what remains have brought technological innovation into our lives, especially at events and expositions […]

The post Application For Maker Faire Rome 2024: Deadline June 20th appeared first on Open Electronics. The author is Boris Landoni

First Solar becomes solar industry’s first EPEAT Climate+ Champion

Semiconductor today - Wed, 06/05/2024 - 11:24
Cadmium telluride (CdTe) thin-film photovoltaic (PV) module maker First Solar Inc of Tempe, AZ, USA says that its Series 6 Plus and Series 7 TR1 products are the world’s first PV solar modules to achieve the EPEAT Climate+ designation, establishing a new benchmark for the solar technology and manufacturing industry...

NUBURU’s distributor Japan Laser Company installs BL250 BlueScan in Osaka office

Semiconductor today - Wed, 06/05/2024 - 11:16
NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — says that distributor Japan Laser Company (JLC) has installed a BL250 BlueScan system in the JLC Osaka office, to be used to demonstrate micro-welding and wire stripping to strategic electronic and medical device customers in the Japanese market...

Geely and ST set up joint lab and sign multi-year SiC device supply deal

Semiconductor today - Wed, 06/05/2024 - 11:07
STMicroelectronics of Geneva, Switzerland and China-based automobile and electric vehicle (EV) maker Geely Auto Group have signed a multi-year silicon carbide (SiC) supply agreement to accelerate their existing cooperation on SiC devices...

Elevating embedded systems with I3C

EDN Network - Wed, 06/05/2024 - 08:51

In modern electronics, embedded systems have become increasingly complex, incorporating a variety of sensors and components in many applications including IoT, computing, wearables and security-sensitive applications. To meet the growing requirements of these markets, the MIPI Alliance has developed the improved inter-integrated circuit® (I3C) interface. I3C is an advanced serial communication interface that offers a major upgrade in how electronic components can communicate with each other by providing faster communication rates, lower power consumption, and improved design flexibility. As a key component of an embedded system, microcontrollers (MCUs) are used to control application functions like sensor signal acquisition and closed-loop control. We will delve into several applications that can utilize an MCU with an I3C communication interface, offering a robust upgrade path and compatibility for I2C and SPI implementations. 

I3C and IoT applications

IoT touches nearly every facet of our daily routines, spanning from household gadgets to sophisticated building automation and wearable devices. These interconnected devices gather and exchange data, fundamentally shaping our digital ecosystem. Within IoT devices, different types of sensors play a pivotal role, measuring, monitoring, and relaying crucial physical attributes like temperature, humidity, pressure, and distance, among others.

The I3C protocol offers several benefits for networked sensor nodes. It enables high-speed communication, with speeds of up to 12.5 MHz in single data rate (SDR) mode. It also supports in-band interrupts and dynamic addressing. In dynamic addressing, a central controller assigns unique addresses to each connected device, preventing address conflicts. Compared to its predecessor I2C, I3C boasts faster speeds, a simpler 2-wire interface, a more efficient protocol structure, and operates at lower voltages to reduce power consumption. These improvements make I3C well-suited for efficiently managing multiple sensor nodes within a connected network.

Incorporating a low cost MCU with built-in I3C peripherals into IoT sensor nodes as an analog “aggregator” can enhance functionality and efficiency of the entire sensor network. In this setup, the MCU’s on-chip analog-to-digital converter (ADC) is utilized to convert readings from multiple analog sensors into digital values. These digital values can then be stored in the MCU’s internal memory for further analysis or organized for more efficient transmission. The aggregated sensor data is transmitted to the main controller via the I3C bus at intervals optimized for system efficiency.

The distinct advantage of I3C in sensor-based systems becomes apparent when considering its capacity to minimize component complexity, cost, and power consumption by necessitating fewer pins and wires compared to alternative communication interfaces. For system designers navigating the demanding IoT market landscape, a compact MCU with I3C communication interface emerges as an essential solution, facilitating the creation of successful IoT devices that align with market requirements.

Multiple protocols and multiple voltages in embedded devices

As technology requirements grow, embedded developers face increasing challenges with backward compatibility. This compatibility is crucial because it allows for embedded systems to be gradually updated, rather than completely redesigned. To help ease the transition to I3C, the new communication protocol addresses the limitations of I2C and SMBus, while using the same two pins as I2C for clock and data to maintain compatibility.

While I3C aims to be backward-compatible with I2C/SMBus protocols, the presence of an I2C/SMBus device on an I3C bus can affect bus performance, even with controller optimization for I3C devices. To resolve this, an MCU with an I3C module can serve as a bridge device, isolating I2C/SMBus target devices from the “pure” I3C bus. This maintains the integrity of the I3C bus, allowing the main I3C controller to communicate with I2C /SPI devices via the bridge MCU. Additionally, the MCU can consolidate interrupts from I2C /SMBus devices and transmit them to the main I3C controller using in-band interrupts, without additional pins or signals.

Embedded systems incorporate various components such as MCUs, sensors, and other circuits. Oftentimes, these components need to be connected to one another, yet they operate in different voltage domains. For instance, analog sensors typically operate at 5 V, while communication protocols like I2C and SMBus require 3.3 V. The I3C bus can even operate at 1 V to match the requirements of modern high-speed processors.

MCUs with a multi-voltage I/O (MVIO) feature resolve voltage incompatibility and eliminate the need for level shifters. This feature enables I3C and I2C /SMBus buses to operate at different voltages simultaneously. For instance, an MCU can run the I3C bus at 1 V while keeping the I2C /SMBus bus at a higher 3.3 V for compatibility with legacy devices.

As shown in Figure 1, Microchip’s PIC18-Q20 MCUs, with MVIO support, offer multiple communication protocols like I3C, SPI, I2C, and UART, and up to three independent operating voltage domains. This flexibility proves highly beneficial in complex networked environments where devices use different protocols and voltages, allowing embedded developers to maintain existing protocols while futureproofing their designs.

Figure 1 The PIC18-Q20 MCUs, with MVIO support, offer multiple communication protocols like I3C, SPI, I2C, and UART, and up to three independent operating voltage domains. This offers flexibility in networked environments where embedded devices may use different protocols and voltages. Source: Microchip

Modern computing infrastructure

People can easily underestimate how much we rely on data centers in our daily digital lives. From conducting business and financial transactions to browsing the internet, storing data, engaging in social networking, attending virtual meetings, and enjoying digital entertainment—all these activities are facilitated by data centers. These centers ensure that our data is safe, our internet is fast, and our digital services are always available.

At the core of the data center lies the modern blade server: a highly advanced computer designed to maximize space efficiency and optimize network performance on a large scale. Due to the crucial nature of their function, certain system tasks within each server chassis are delegated to a sideband controller. While the main processing unit focuses on managing the primary data flow, the sideband controller steps in to enhance network performance. It establishes a secondary communication channel to oversee individual server blades and handles important tasks such as monitoring system health, detecting faults, discovering and configuring devices, updating firmware, and conducting diagnostics without disrupting the main processor. This ensures smooth and efficient operation. Sideband management serves as a critical tool that can greatly enhance the reliability, availability and efficiency of data centers.

Solid state drives (SSDs) are also commonly used in data centers to store and quickly access data. The newest SSD form factor, SNIA® Enterprise and Datacenter Standard Form Factor (EDSFF), has adopted the I3C protocol for sideband communication as a natural upgrade from the existing SMBus protocol. I3C addresses the demand for faster performance, higher data transfer rates, and improved power efficiency. The high-speed communication of I3C enables faster bus management and configuration modifications for enhanced system responsiveness.

Flexible MCUs such as the PIC18-Q20 family (Figure 2) are particularly well-suited for system management tasks in data center and enterprise environments. With up to two separate I3C interfaces, these MCUs can easily connect to an SSD controller for performing system management tasks, as well as to a baseboard management controller (BMC) via a sideband connection. Moreover, with built-in legacy communication protocols like I2C/SMBus, SPI, and UART, these devices represent an ideal solution for both current and next-generation SSD designs.

Figure 2: The PIC18-Q20 family will easily connect to an SSD and BMC controller via a sideband connection. Source: Microchip

I3C’s growing ubiquity

The integration of the I3C protocol has emerged as an enabling force in embedded systems. The enhanced communication capabilities, lower power consumption, and compatibility with existing protocols make I3C a cornerstone for next-generation IoT and computing applications. By optimizing sensor functionalities in IoT devices and data center communication, the versatility of I3C when integrated into MCUs can provide a robust foundation for the modern electronic systems. The adoption of I3C is quickly growing in ubiquity, enabling enhanced performance, reliability, and efficiency.

Stephanie Pinteric and Ulises Iniguez are senior product marketing engineers in Microchip’s 8-bit MCU business unit.

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CGD adds new ICeGaN power IC packages with enhanced thermal performance

Semiconductor today - Tue, 06/04/2024 - 16:46
Fabless firm Cambridge GaN Devices Ltd (CGD) — which was spun out of the University of Cambridge in 2016 to design, develop and commercialize power transistors and ICs that use GaN-on-silicon substrates — has announced two new packages for its ICeGaN family of GaN power ICs that offer enhanced thermal performance and simplify inspection. As variants of the well-proven DFN style, both packages are said to be extremely rugged and reliable...

Image sensor embeds AI to explore image data

EDN Network - Tue, 06/04/2024 - 16:40

A new generation of CMOS image sensors can exploit all the image data to perceive a scene, understand the situation, and intervene by embedding artificial intelligence (AI) in the sensor. CEA-Leti researchers have reported this design breakthrough when demand for smart image sensors is growing rapidly due to their high-performance imaging capabilities in smartphones, automobiles, and medical devices.

The design breakthrough is built on a combination of hybrid bonding and high-density through silicon via (HD TSV) technologies, which facilitates the integration of various components like image sensor arrays, signal processing circuits and memory elements in image sensors with precision and compactness.

The design breakthrough is based on a three-layer test vehicle that featured two embedded Cu-Cu hybrid-bonding interfaces, face-to-face (F2F) and face-to-back (F2B), and with one wafer containing high-density TSVs. Source: CEA-Leti

Communication between the different tiers in an image sensor design necessitates advanced interconnection technology. The new design presented by CEA-Leti employs hybrid bonding due to its very fine pitch in the micron and sub-micron range. It also uses HD TSV, which has a similar density that enables signal transmission through the middle tiers.

“The use of hybrid bonding and HD TSV technologies contribute to the reduction of wire length, a critical factor in enhancing the performance of 3D-stacked architectures,” said Renan Bouis, lead author of the paper titled “Backside Thinning Process Development for High-Density TSV in a 3-Layer Integration.” He added that stacking multiple dies to create 3D architectures, such as three-layer imagers, has led to a paradigm shift in sensor design.

The paper presents the key technological bricks that are mandatory for manufacturing 3D, multilayer smart imagers capable of addressing new applications that require embedded AI. “This sets the stage to work on demonstrating a fully functional three-layer, smart CMOS image sensor, with edge AI capable of addressing high-performance semantic segmentation and object-detection applications,” said Eric Ollier, project manager at CEA-Leti and director of IRT Nanoelec’s Smart Imager program.

The Grenoble, France-based research house CEA-Leti is a major partner of IRT Nanoelec, an R&D institute also based in Grenoble, France.

It’s worth mentioning that at ECTC 2023, CEA-Leti scientists reported a two-layer test vehicle combining a 10-μm high, 1-μm diameter HD TSV and highly controlled hybrid bonding technology, both assembled in F2B configuration. Now, they have shortened the HD TSV to 6-μm height, which led to the development of a two-layer test vehicle exhibiting low dispersion electrical performances and enabling simpler manufacturing.

It’s mainly due to an optimized thinning process that allowed the substrate thickness to be reduced with favorable uniformity. “This reduced height led to a 40% decrease in electrical resistance, in proportion with the length reduction,” said Stéphan Borel, lead author of the paper titled “Low Resistance and High Isolation HD TSV for 3-Layer CMOS Image Sensors”. “Simultaneous lowering of the aspect ratio increased the step coverage of the isolation liner, leading to a better voltage withstand.”

Scientists at CEA-Leti are confident that this smart image sensor technology will enable a variety of new applications.

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5N Plus renews and increases CdTe materials supply agreement with First Solar

Semiconductor today - Tue, 06/04/2024 - 16:26
Specialty semiconductor and performance materials producer 5N Plus Inc of Montreal, Québec, Canada has renewed its supply agreement with First Solar Inc of Tempe, AZ, USA...

Component tolerance sensitivities of single op-amp filter sections

EDN Network - Tue, 06/04/2024 - 15:38

Editor’s note: This DI invites the reader to reference custom Excel sheets for:

Please refer to these as you review this DI.
—Aalyia Shaukat

Several manufacturers offer op amp-based filter design tools [1-3]. Some tools choose off-the-shelf capacitor values, but others select non-standard ones. The option to alter passive component (resistor and capacitor) values while maintaining a given response is often limited, if available at all. Certain tools seem to consider the effects of particular passive component combinations on unwanted variations in filter responses, but others do not. Some limit designs to a specific set of filter characteristics (Butterworth, Bessel, Chebyshev) when filter design tables of quality factor (Q) and resonance frequency f0 (Hz) for other response types are readily available (see section 8.4  in [4] and [5]).

Wow the engineering world with your unique design: Design Ideas Submission Guide

This article addresses second-order op amp-based low, band, and high pass filter sections. A reference for many of the design equations used in the article can be found here [6]. Excel spreadsheets for each filter type allow the user to specify three defining characteristics: passband gain, Q, and resonance frequency f0. It requests the tolerances in percent of the capacitors and the resistors to be used. Each filter has a minimum of four passives, and so there is an infinite number of combinations of values which will satisfy the three characteristics. Because the difference between successive standard capacitor values is at least 10% while that for 1% resistors is only 2%, and because quality capacitors are generally more expensive, the user is given the option of specifying the two capacitors’ values rather than those of the resistors. This leaves it to the spreadsheet to calculate the latter. If desired, near exact resistor values can be implemented in a physical filter cheaply by using two standard parts.

The main purpose of this article is to demonstrate graphically and numerically how different sets of passive component values and tolerances contribute to unwanted variations in filter responses. From these, the user can readily select capacitor values which minimize the combination of a filter’s response sensitivity and component size and cost.

Types of passives used in filters

Before getting into a detailed discussion about sensitivity, it’s worth discussing the types of passive components (see [4] pp. 8.112-8.113) that should be used in filters. For SMD and through-hole applications, 1% metal film resistors are a good, inexpensive choice as are NPO ceramics (stay away from the monolithic, high dielectric value ceramics). For surface mount applications only, there are thin film capacitors. For through-hole, polystyrene, polypropylene, and Teflon capacitors are available. As for active components, this article assumes ideal op amps (which we know are difficult to source). The reference (see [4] pp. 8.114-8.115) gives a discussion of what is required of this component, the biggest concern of which is the gain available at f0 Hz. By “rule of thumb” this should exceed 4·Q2 for the filter by a factor of 10 or more.

But rather than dealing with a rule of thumb, it is recommended to start by simulating the filter using nominal value passive components and an op amp with no high frequency roll-off and a resonance frequency gain of 1000·4·Q2 or more. Then, reduce the gain and introduce a high frequency roll off until a response change is seen. Finally, an op amp with matching or superior characteristics can then be selected and used in a simulation for design confirmation.

Quantizing filter response variations due to component tolerances

Generally, a variation in a passive’s value will result in some change in filter response characteristics. If that change is small enough, there will be some sensitivity S which is a constant of proportionality relating the filter parameter y variation to the passive x’s change. To keep S dimensionless, it will be useful to relate fractional changes in the passive’s value to those of the parameter. Mathematically,

Solving for in the limit as Δx goes to zero, we have:

The instances of x that are of concern are the resistor and capacitor values that make up the filter. The instances of y are the defining filter parameters: passband gain, Q and ω0 = 2π·f0. The following is an example of how the various S values are computed for the low pass filter in Figure 1.

Figure 1 A sample lowpass filter used to compute various S values.

The frequency domain (s-plane) transfer function of the above filter is:

For such a section, this is equal to:

By equating like terms, the various parameters can be computed. But what is really needed is some total sensitivity of each y parameter to a complete filter design, one which involves all its passive components. One way to do this is to use the following equation:

This is the square root of the sum of the squares of the sensitivities of a specific y to each of the i component’s xi multiplied by the tolerance of xi in percent, pct_tolxi. This expression is useful for comparisons between the overall sensitivities of implementations with different sets of component values.

The general filter design approach

Refer to Figure 2 which shows the spreadsheet LPF.xlsx used for the design and analysis of low pass filters. Many of its characteristics are identical to the ones used in the high and bandpass spreadsheets.

Figure 2 A screenshot of the low pass filter spreadsheet where the yellow values are entered by the user, the orange cells are filter component values automatically calculated by the spreadsheet, the bottom parameters are intermediate calculation required by the spreadsheet, and columns F and G contain the sensitivity values. There is also a graph which ignores _ρ and displays a wide range of possible component values from which the user may choose.

The yellow values in column C rows 5 through 14 are the only values entered by the user. These include the filter characterization parameters Q, Gain, and f0; as well as the ratio _ρ = C1/C2 (take note of the comment associated with cell C10); values for C1 and RG (reference designators for the components in the schematic seen in columns B through D and rows 26 through 37); and the percent tolerances of the resistors (r_tol) and the capacitors (c_tol) intended to be used in the filter.

The orange cells, columns B and C, rows 20 to 24, are filter component values calculated by the spreadsheet from these user entries. Columns C and D, rows 43 to 48 contain some of the intermediate calculations required by the spreadsheet.

Columns F and G contain the , , and sensitivities associated with each component x. Only those which have non-zero effects on the total sensitivity parameters SQ, SGain, and Sω0 (also shown in these columns) are listed. Notice that the equation for every parameter calculated by the spreadsheet appears to the right of the parameter value. There is also a graph which ignores _ρ and displays a wide range of possible component values from which the user may choose.

Low Pass filter design

Now let’s take a look at the curves on the graph for parameters _ρ = _C1 /_C2 and sensitivities SQ and Sω0 which are parameterized by _r = _R2/(1/_R1a + 1/_R1b) for values from .01 to 100. These depend only on Q, Gain, and _r. all these are dimensionless.

The _ρ curve shows that for this particular filter, there are no solutions for values less than 4·Q2 = 4. (If you had entered such a value for _ρ, Excel would return the #NUM! error for many spreadsheet calculations.) The curve for Sensitivity of Gain, SGain, can’t be shown on a logarithmic scale—cell G25 shows it to be equal to zero. Why? The pass band (low frequency) Gain is 1, RF is zero, R1b is infinite (the spreadsheet shows it to be ridiculously large), and no passive components have any effect on Gain. (In a physical filter, there is still a sensitivity to the unity gain-configured op amp’s gain, which is actually less than unity due to its finite gain bandwidth product. Hence one of the reasons to simulate filter designs with the intended op amp.) Interestingly, the component sensitivities to Sω0 are independent of Q, _r, _ρ, and Gain for gains greater than or equal to unity, being dependent on tolerances r_tol and c_tol only. If Gain is unity, the only overall sensitivity that can be influenced is SQ, which is minimized in this case for _ρ = 4·Q2 = 4.

When 12.0E-9 is entered for _C1, the expression = 12/2.7 ≈ 4.44 for _ρ is close to 4 to allow the use of standard value capacitors. It will be seen that for low and high pass filters, the least sensitive choice is for a Gain of unity. Figure 3 shows what happens when the Gain requirement is increased by even a small amount to 1.5.

Figure 3 The low pass filter design of Figure 2 with the Gain parameter increased from 1 to 1.5.

Sω0 is unchanged as expected, but the best SQ has now more than doubled and SGain has made a showing, although it’s not much of a concern. The only good news is that _ρ = _C1/_C2 could be reduced to 2.2/1 and _C1 to 2.2E-9 (not shown in Figure 3) with no significant effect on SQ. A significant increase in Gain is definitely not recommended, as it causes a large jump in SQ, as can be seen in Figure 4.

Figure 4 Low Pass Filter screenshot with Gain jumping from from a value of 1 to 5, resulting in a large jump in SQ.

Such large gain values increase the best obtainable value of SQ by a factor of 6 in comparison to the Figure 3 design. The problem is compounded for higher values of Q and for component tolerances greater than 1%.

Low pass filter design summary

It’s no surprise that the best results will be obtained with the lowest tolerance passive components. There is little that can be done to influence the value of Sω0 which is constant for Gain values greater than or equal to unity, and which falls by small amounts only for smaller gains. Fortunately, its value is relatively small. For given values of Q and f0, the least sensitive low pass filter designs overall have a Gain of unity. For such a case, SGain is zero and SQ is at its minimum. Gains of unity or less leave SQ  unchanged, but can cause SGain to rise a small amount above the very stable Sω0. The real problem comes with Gain values greater than unity: Even slightly higher values cause SQ to increase significantly and overwhelm the contributions of SGain and Sω0, but they will reduce the minimum usable value of _ρ, which may be an acceptable tradeoff against increased SQ for some high Q cases. Generally, though, it’s wise to avoid Gain values much greater than unity, you can verify that the commonly recommended case of Gain = 2 to allow _ρ = 1 for equal capacitor values can produce a horrendous increase in SQ.

High pass filter design

Other than a few differences related to interchanging the treatments of R1 and R2 with those of C1 and C2, high pass filter design and the high pass filter design spreadsheet shown in Figure 5 are much like those for the low pass filter. The biggest differences are first, that parameterization of the graph’s curves is by _ρ = _C1/_C2 (assuming values from .01 to 100) rather than by _r = _R2/_R1. For the low pass, any value of _r produces a realizable result, while this is true for _ρ for the high pass. Second, there is no C1b/C1a voltage divider corresponding to the low pass filter’s R1b/R1a—there is only _C1. The introduction of a capacitive voltage divider would require a prior stage to drive a capacitive load, courting oscillation. And so, although the high pass filter cannot support Gain values less than unity, the high and low pass designs show significant similarities. A comparison between Figure 4 and Figure 5 graphs, which employ the same Q, Gain, and f0, show virtually identical results (with _ρ and _r switched).

Figure 5 High Pass Filter screenshot with the same Q, Gain, and f0 requirements as those of Figure 4.

High Pass filter design summary

The comments found in the “Low pass filter design summary” section apply here too, except that there is no option for Gain values less than unity.

Bandpass filter design

Although the least sensitive topology for component tolerances in high and low pass filters is the Sallen-Key, for the bandpass it’s the Delyannis-Friend (aka the multiple feedback configuration). A screenshot of the bandpass filter spreadsheet can be seen in Figure 6.

User data entry with the bandpass is much like that for the low and high pass cases, except that there is no _RG (and therefore no _RF). Once again, please be aware of the comments in the notes in columns D and E. If the background of cell C6 (filter Gain at resonance) is red, there are no realizable filters, calculations in columns C through G should be ignored, and the graph will be blank.

In some cases, the cell C6 background color will be the normal white, but filters will be realizable for certain smaller values of _ρ only, and the graph’s curves will be displayed accordingly. The curves might be absent, or partially or fully present, regardless of the value of _ρ in cell C10. But if C10’s background color is red, the _ρ-dependent calculations in columns C through G should be ignored. Figure 6 is an example where the filter Gain at resonance is close enough to the maximum possible value of 2·Q2 to render high values of _ρ (greater than 30) unrealizable.

Figure 6 A bandpass filter screenshot where user entry data (yellow) is similar to the low and high pass filter excel sheets.

Bandpass filter design summary

It’s surprising that the passive sensitivity curves can be shown to be almost completely independent of the user-specified filter Gain at resonance. This is because for a given Q and f0, the filter Gain is set by the ratio of R1a to R1b. The parallel combination of these components is independent of filter Gain, and the remainder of the filter sees no difference in other than signal level. (Designers should be aware that the op amp can easily clip at or near resonance with too high a gain.) Surprisingly, sensitivities are independent of Q. However, the higher the Q, the higher the op amp open loop gain must be to provide enough margin to accurately implement the required op amp closed loop gain. Simulation of the filter design using the op amp intended for it, or one with similar gain characteristics, is strongly recommended.

Looking at the sensitivity curves only, it could be concluded that the best choice would be for a _ρ of 1 or less. _ρ = 1 has the advantage of the smallest ratio _r = R2 / (R1a || R1b). But consider the Gain of op amp at resonance: Less gain is required at higher values of _ρ, putting less of a burden on op amp open loop gain requirements to provide enough margin to meet the closed loop gain requirement.

Higher values of _ρ increase the overriding SGain by only a small amount. Clearly, there is a rather large disadvantage to values of _ρ less than unity when the demand on op amp closed loop gain is considered. Perhaps the best choice is _ρ = 1. The matched capacitors can be any standard value, SGain is near its smallest value, _r is at its smallest value, and there is only a modest increase in the op amp closed loop (and therefore open loop) gain requirement.

Flexible passive component values

This article and its attendant spreadsheets provide an understanding of the sensitivities of pass band gains, Q’s, and resonance frequencies to the nearly infinite combinations of passive components that can make up low, band, and high pass, single op amp filters. The ability to implement designs using capacitors of readily available values is provided. It is hoped that filter designers will find these to be a useful set of tools whose features are not found elsewhere.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

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References

  1. Texas Instruments. WEBENCH® Filter Design Tool. https://webench.ti.com/filter-design-tool/design/8
  2. Analog Devices. Analog Filter Wizard. https://tools.analog.com/en/filterwizard/
  3. FilterLab Active Filter Designer. https://www.microchip.com/en-us/development-tool/filterlabdesignsoftware
  4. Zumbahlen, Hank. “Chapter 8: Analog Filters.” Linear Circuit Design Handbook. Elsevier, 2008, https://www.analog.com/en/resources/technical-books/linear-circuit-design-handbook.html.
  5. Williams, Arthur Bernard. Analog Filter and Circuit Design Handbook. McGraw-Hill, 2014.
  6. Jurišić, D., Moschytz, G. S., & Mijat, N. (2010). Low-Sensitivity Active-RC Allpole Filters Using Optimized Biquads. Automatika, 51(1), 55–70. https://doi.org/10.1080/00051144.2010.11828355
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Mitsubishi Electric sampling 16W GaN power amplifier module for 5G massive MIMO base stations

Semiconductor today - Tue, 06/04/2024 - 15:02
On 11 June, Tokyo-based Mitsubishi Electric Corp is to begin shipping samples of a new 16W-average-power gallium nitride (GaN) power amplifier module (PAM) for 5G massive MIMO (mMIMO) base stations...

Silanna UV launches 235nm Quad High-Power far-UVC LED at ICFUST

Semiconductor today - Tue, 06/04/2024 - 14:57
Silanna UV of Brisbane, Australia – which provides far-UVC light sources for water quality sensors, gas sensors, disinfection, and HPLC (high-performance liquid chromatography) applications – is launching a new 235nm Quad High-Power far-UVC LED at the International Congress on Far-UVC Science and Technology 2024 (ICFUST) at the University of St Andrews in Scotland, UK (19–21 June). As a sponsor of the event, Silanna UV is showcasing its latest deep-UVC and far-UVC LED innovations...

Micro-LED chip market growing at 84% CAGR to $579m by 2028

Semiconductor today - Tue, 06/04/2024 - 12:41
The micro-LED chip market is rising at a compound annual growth rate (CAGR) of 84% from just $27m in 2023 to $579m by 2028, forecasts TrendForce’s ‘2024 Micro LED Market Trend and Cost Analysis Report’...

New industrial CoolSiC MOSFETs 650 V G2 in TOLT and Thin-TOLL package increase system power density

ELE Times - Tue, 06/04/2024 - 10:57

The electronics industry is witnessing a significant shift towards more compact and powerful systems, driven by technological advancements and a growing focus on decarbonization efforts. With the introduction of the Thin-TOLL 8×8 and TOLT packages, Infineon Technologies AG is actively accelerating and supporting these trends. They enable a maximum utilization of the PCB mainboard and daughter cards, while also taking the system’s thermal requirements and space restrictions into account. The company is now expanding its portfolio of CoolSiC MOSFET discretes 650 V with two new product families housed in the Thin-TOLL 8×8 and TOLT packages. They are based on the CoolSiC Generation 2 (G2) technology, offering significantly improved figures-of-merit, reliability, and ease-of-use. Both product families specifically target high and medium switching-mode power supplies (SMPS), including AI servers, renewable energy, EV chargers, and large home appliances.

The Thin-TOLL package has a form factor of 8×8 mm and offers the best-in-class Thermal Cycling on Board (TCoB) capability on the market. The TOLT package is a top-side cooled (TSC) enclosure with a similar form factor to TOLL. Both package types offer developers several benefits: Using them in AI and server power supply units (PSU), for example, reduces the thickness and length of the daughter cards and allows for a flat heat sink. When used in microinverters, 5G PSU, TV PSU and SMPS, the Thin-TOLL 8×8 package allows for a minimization of the PCB area occupied by the power supply devices on the mainboard, while TOLT keeps the junction temperature of the devices under control, given that these applications typically use convection cooling. In addition, TOLT devices complete Infineon’s top-side cooled CoolSiC industrial portfolio, namely CoolSiC 750 V in Q-DPAK. They enable developers to reduce the PCB footprint occupied by SiC MOSFETs when the power to be delivered to the devices does not require a Q-DPAK package.

Availability

The CoolSiC MOSFETs 650 V G2 in ThinTOLL 8×8 and TOLT are now available in RDS(on) from 20, 40, 50 and 60 mΩ. Additionally, the TOLT variant is also available with an RDS(on) of 15 mΩ. The product family will be expanded by a more granular portfolio by the end of 2024. More information is available at www.infineon.com/coolsic-gen2. Infineon will showcase the CoolSiC MOSFET 650 V Generation 2 at the PCIM in Nuremberg.

Infineon at the PCIM Europe 2024

PCIM Europe will take place in Nuremberg, Germany, from 11 to 13 June 2024. Infineon will present its products and solutions for decarbonization and digitalization in hall 7, booths #470 and #169. Company representatives will also be giving several presentations at the accompanying PCIM Conference and Forums, followed by discussions with the speakers. If you are interested in interviewing an expert at the show, please email media.relations@infineon.com. Industry analysts interested in a briefing can email MarketResearch.Relations@infineon.com. Information about Infineon’s PCIM 2024 show highlights is available at www.infineon.com/pcim.

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TRI to Drive AI Innovation in Smart Factories, in Collaboration with NVIDIA

ELE Times - Tue, 06/04/2024 - 10:35

Test Research, Inc., the leading test and inspection systems provider for the electronics manufacturing industry, today announced a collaboration with NVIDIA and leading Taiwanese electronics manufacturers to accelerate the deployment of AI-driven technologies for smart factories.

The collaboration will integrate the cutting-edge NVIDIA Metropolis for Factories workflow into Test Research, Inc. (TRI)’s portfolio to leverage advanced AI capabilities to optimize manufacturing processes through enhanced automation and defect detection. By combining TRI’s domain expertise in test and inspection with NVIDIA’s AI software stack and computing capabilities, TRI aims to empower manufacturers with intelligent solutions that drive operational efficiencies and unlock new levels of productivity for the electronics manufacturing industry. And looking forward TRI plans to leverage NVIDIA NIM to further increase performance and throughput.

“We are thrilled to collaborate with NVIDIA to deliver innovative, future-proof solutions to our customers in the electronics manufacturing industry,” said Jim Lin, Vice President of Test Research Inc. “With NVIDIA Metropolis for Factories, TRI is poised to help drive the adoption of AI in smart factories, empowering manufacturers to embrace the technologies of tomorrow and stay ahead of the curve.”

NVIDIA Metropolis for Factories is a workflow that simplifies the development, deployment, and scaling of AI-enabled visual inspection applications from edge to cloud. It supports data labeling, computer-vision model training, and model integration, and enables industrial technology companies and manufacturers to develop, deploy, and manage customized quality-control systems. It allows TRI to develop incredibly accurate inspection applications, such as for automated optical inspection (AOI). Metropolis for Factories is helping manufacturers increase production line throughput, reduce costs, and improve production quality.

TRI AI Defect Detection

Thanks to TRI’s AI verification advancements, the detection rate of components has improved significantly, the AI detection accuracy for general chip defects now exceeds 99%. Specific improvements include a detection rate of over 95% for components such as OSC, MLD, SOD, SOT23, RNET, and CNET. X-ray void detection with AI implementation improves the first pass yield rate (FPY) from 85% to 98%. For complex components like the Paladin connector, AI classification reduces the false case rate from approximately 25,000 ppm to around 3,000 ppm, an 88% improvement. Detection improvements are also present in the OCR (optical character recognition) algorithms, and traditional methods achieve 89% accuracy, while AI deep learning OCR reaches a 99.58% detection rate.

TRI AI Smart Programming

TRI AI Smart Programming facilitates predictive decision-making similar to that of an expert or experienced operator, reducing programming time, downtime, and operator training. Traditional programming of 718 components would take around 60 minutes; AI programming reduces this to just 9 minutes, an 85% improvement.

TRI AI Verify Host

The AI Verify Host is a smart repair station that reduces the need for manual re-inspection and lowers operational costs, powered by the Metropolis for Factories workflow. Typically, repair station operators have lower performance and training is not cost-effective. The AI-powered repair station can continuously operate efficiently, outperforming operators while lowering false calls and providing real-time data analytics of the inspection status.

TRI AI Station

Inspection programming is often limited to the operator’s knowledge. TRI AI Station addresses this by performing AI-powered inspections with existing AI models, optimizing the process, increasing efficiency, and lowering operational costs for the experienced workforce. The AI Station supports multiple AOIs and smart scheduling, reducing AI hardware costs and improving resource management.

TRI AI Training Tool

TRI AI Training Tool is a user-friendly interface that generates AI models from existing inspection data. The tool includes a built-in AI labeling tool and supports classification, segmentation, OCR, detection tools, continued training, heat maps, and more.

TRI will harness NVIDIA Triton Inference Server software and the NVIDIA TensorRT software development kit to further speed up AI inferencing of cutting-edge AI-powered solutions for test and inspection, and smart factories for the electronics manufacturing industry. These AI-driven capabilities will enable manufacturers to readily adopt and benefit from innovative AI-powered solutions.

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Introducing the TimeProvider XT Extension System for Migrating to a Modern Synchronization and Timing Systems Architecture

ELE Times - Tue, 06/04/2024 - 10:24

Accessory device to Microchip’s TimeProvider 4100 grandmaster scales up to 200 fully redundant T1, E1 or CC synchronization outputs

Critical infrastructure communication networks require highly accurate and resilient synchronization and timing, but over time these systems age out and must be migrated to a more modern architecture. Microchip Technology announces the new TimeProvider XT Extension System, a fan-out shelf used with redundant TimeProvider 4100 grandmasters to migrate legacy BITS/SSU equipment to a modular and resilient architecture. The TimeProvider XT provides operators with a clear path to replace existing SONET/SDH frequency synchronization equipment while adding timing and phase, which is essential for 5G networks.

As an accessory device to Microchip’s widely deployed TimeProvider 4100 grandmaster, each TimeProvider XT shelf is configured with two distribution modules and two plug-in modules to provide 40 fully redundant and individually programmable outputs with synchronization designed to meet ITU-T G.823 for wander and jitter control. Operators can connect up to five XT shelves to scale up to 200 fully redundant T1/E1/CC communication outputs. All configuration, status monitoring and alarm reporting are done via the TimeProvider 4100 grandmaster. This new solution allows operators to consolidate their critical frequency, timing and phase requirements onto a single modern platform, saving maintenance and service costs.

“With the new TimeProvider XT Extension, network operators can take advantage of state-of-the-art technology that is reliable, scalable and flexible to either overlay or replace their SONET/SDH synchronization systems,” said Randy Brudzinski, vice president of Microchip’s frequency and time systems business unit. “The XT solution is an attractive investment for network operators because it is more than just a replacement for legacy BITS/SSU equipment; it also adds PRTC functionality, delivering frequency, time and phase for next-generation networks.”

This solution is compatible with DCD, SSU 2000, TSG-3800 and TimeHub systems’ wire-wrap and output panels, so that network elements do not have to be rewired. This can save network operators significant deployment time and resources while reducing costs. The TimeProvider XT has a Composite Clock (CC) input which allows for live in-service CC phase cutovers, which are typically performed during maintenance windows to ensure that the synchronization in a network is maintained. The TimeProvider XT system requires the TimeProvider 4100 grandmaster to be running the latest version 2.4 firmware.

The TimeProvider XT Extension system is the newest product to join Microchip’s extensive portfolio of clock and timing systems, which ranges from small plug-in timing server cards to multi-rack national and time scale systems.  As a primary contributor to the world’s time, Microchip’s timing solutions are trusted, reliable and resilient. For more information, visit Microchip’s Timing and Synchronization website.

Development Tools

The TimeProvider XT Extension is supported by TimePictra Management Software, a web-based tool to manage and monitor synchronization architectures.

The post Introducing the TimeProvider XT Extension System for Migrating to a Modern Synchronization and Timing Systems Architecture appeared first on ELE Times.

STMicroelectronics to build the world’s first fully integrated silicon carbide facility in Italy

ELE Times - Tue, 06/04/2024 - 09:22
  • New high-volume 200mm silicon carbide manufacturing facility for power devices and modules, as well as test and packaging, to be built in Catania, Italy
  • Projected 5 billion euros multi-year investment program including 2 billion euros support provided by the State of Italy in the framework of the EU Chips Act
  • Catania Silicon Carbide Campus realizes ST’s plan for fully vertically integrated SiC capabilities from R&D to manufacturing, from substrate to module, on one site, enabling automotive and industrial customers in their shift to electrification and higher energy efficiency.

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announces a new high-volume 200mm silicon carbide (“SiC”) manufacturing facility for power devices and modules, as well as test and packaging, to be built in Catania, Italy. Combined with the SiC substrate manufacturing facility being readied on the same site, these facilities will form ST’s Silicon Carbide Campus, realizing the Company’s vision of a fully vertically integrated manufacturing facility for the mass production of SiC on one site. The creation of the new Silicon Carbide Campus is a key milestone to support customers for SiC devices across automotive, industrial and cloud infrastructure applications, as they transition to electrification and seek higher efficiency.

“The fully integrated capabilities unlocked by the Silicon Carbide Campus in Catania will contribute significantly to ST’s SiC technology leadership for automotive and industrial customers through the next decades,” said Jean-Marc Chery, President and Chief Executive Officer of STMicroelectronics. “The scale and synergies offered by this project will enable us to better innovate with high-volume manufacturing capacity, to the benefit of our European and global customers as they transition to electrification and seek more energy efficient solutions to meet their decarbonization goals.”

The Silicon Carbide Campus will serve as the center of ST’s global SiC ecosystem, integrating all steps in the production flow, including SiC substrate development, epitaxial growth processes, 200mm front-end wafer fabrication and module back-end assembly, as well as process R&D, product design, advanced R&D labs for dies, power systems and modules, and full packaging capabilities. This will achieve a first of a kind in Europe for the mass production of 200mm SiC wafers with each step of the process – substrate, epitaxy & front-end, and back-end – using 200 mm technologies for enhanced yields and performances.

The new facility is targeted to start production in 2026 and to ramp to full capacity by 2033, with up to 15,000 wafers per week at full build-out. The total investment is expected to be around five billion euros, with a support of around two billion euros provided by the State of Italy within the framework of the EU Chips Act. Sustainable practices are integral to the design, development, and operation of the Silicon Carbide Campus to ensure the responsible consumption of resources including water and power.

Additional information
Silicon Carbide (“SiC”) is a key compound material (and technology) consisting of silicon and carbon that offers several advantages over conventional silicon for power applications. The wide bandgap of SiC and its intrinsic characteristics – better thermal conductivity, higher switching speed, low dissipation – make it particularly suitable for the manufacturing of high-voltage power devices (notably above 1,200V). SiC power devices, in the form of SiC MOSFET sold as bare die and full SiC modules, are especially useful in electric vehicles, fast-charging infrastructure, renewable energies and various industrial applications including datacenters, as they offer higher electric currents and lower leakage than traditional silicon semiconductors, increasing energy efficiency. SiC chips are however more difficult and more costly to manufacture than silicon chips with many challenges to overcome in the industrialization of the manufacturing process.

ST’s leadership in SiC is the result of 25 years of focus and commitment in R&D with a large portfolio of key patents. Catania has long been an important site for innovation for ST as the home of the largest SiC R&D and manufacturing operations, successfully contributing to the development of new solutions for producing more and better SiC devices. With an established ecosystem on power electronics, including a long-term, successful collaboration between ST and the University of Catania and the CNR (Italian National Research Council), as well as a large network of suppliers, this investment will strengthen Catania’s role as a global competence center for SiC technology and for further growth opportunities.

ST currently manufactures its flagship high-volume SiC products on two 150-millimeter wafer lines in Catania (Italy) and Ang Mo Kio (Singapore). A third hub is a joint venture with Sanan Optoelectronics, with a 200-millimeter facility under construction in Chongqing (China), dedicated to ST to serve the Chinese market. ST’s wafer production facilities are supported by automotive-qualified, high-volume assembly and test operations in Bouskoura (Morocco) and Shenzhen (China). SiC substrate R&D and industrialization is undertaken in Norrköping (Sweden) and Catania, where ST’s SiC substrates manufacturing facility is ramping up production and most of ST’s SiC product R&D and design staff are based.

The post STMicroelectronics to build the world’s first fully integrated silicon carbide facility in Italy appeared first on ELE Times.

Teensy-Based Electronic Fuel Injection

Reddit:Electronics - Tue, 06/04/2024 - 05:01
Teensy-Based Electronic Fuel Injection

Teensy 4.0 microcontroller reads manifold absolute pressure and crankshaft position and actuates fuel injector. Fuel injector is driven by a TI LM1949 in conjunction with a Darlington pair. System is installed on a Predator 212 small engine, which was originally carbureted.

submitted by /u/buffarlos
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Coherent appoints Jim Anderson as CEO as Mattera retires

Semiconductor today - Mon, 06/03/2024 - 20:10
The board of directors of materials, networking and laser technology firm Coherent Corp of Saxonburg, PA, USA has appointed Jim Anderson, an established industry executive with a proven track record of driving innovation and leading business transformations, as CEO. Anderson also joins the board. He succeeds Dr Vincent D. (Chuck) Mattera Jr, who is retiring as chair & CEO...

AlixLabs gains SEK2.5m grant from Sweden’s Vinnova

Semiconductor today - Mon, 06/03/2024 - 18:11
AlixLabs AB of Stockholm, Sweden — which was spun off from Lund University in 2019 and has developed Atomic Layer Etching (ALE) Pitch Splitting technology (APS) — has been granted SEK2.5m (equivalent to about €220,000) by Sweden’s innovation agency Vinnova, for continuous R&D of its semiconductor products, starting September 2024 through August 2026. The funding is part of a SEK4m (about €350,000) grant from the strategic innovation program Electronic Components and Systems and its Research and Innovation Projects 2024, with SEK1.5m going to Halmstad University...

6mm Potentiometer Upgrade

Reddit:Electronics - Mon, 06/03/2024 - 16:32
6mm Potentiometer Upgrade

I know its not super interesting, but I always had a lot of those cheap and small 6mm potentiometers, shown in the pictures, lying around in my lab. They get the job done, but they dont fit into a breadboard very well, so I decided to create an Upgrade for them using my 3D Printer and soldered Dupont Wires to them. It makes it just so much more convenient for prototyping with my arduino. I uploaded the files on printables: https://www.printables.com/de/model/900579-6mm-potentiometer-based-rotary-controller maybe some of you that have a 3D Printer and the same potentiometers will find them helpful.

submitted by /u/g3rm4ndude
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