Microelectronics world news

Introduction

Modern electronic systems need small, lightweight, high-efficiency power supplies. These supplies require cost-effective methods to take power from the AC power distribution grid and convert it to a form that can run the necessary electronics.

High switching frequencies are among the biggest enablers for small size. To that end, gallium nitride (GaN) switches provide an effective way to achieve these high frequencies given their low parasitic output capacitance (COSS) and rapid turn-on and turn-off times. It is possible, however, to amplify the high-power densities enabled by GaN switches through the use of advanced control techniques.

In this article, I will examine an advanced control method used inside a 5-kW power factor corrector (PFC) for a server. The design uses high-performance GaN FETs to operate the power supplies at the highest practical frequency. The power supply also uses a novel control technology that extracts more performance out of the GaN FETs. The end result is a high-efficiency, small-form-factor design with higher power density.

System overview

It’s well known that the totem-pole PFC is the workhorse of a high-power, high-efficiency PFC. Figure 1 illustrates the topology.

Figure 1 Basic totem-pole PFC topology where S1 and S2 are high-frequency GaN switches and S3 and S4 are low-frequency-switching Si MOSFETs. Source: Texas Instruments

S1 and S2 are high-frequency GaN switches operating with a variable frequency between 70 kHz and 1.2 MHz. S3 and S4 are low-frequency-switching silicon MOSFETs operating at the line frequency (50 to 60 Hz).

During the positive half cycle of the AC line, S2 operates as the control FET and S1 is the synchronous rectifier. S4 is always on and S3 is always off. Figure 2 shows the interval when the inductor current is increasing because control FET S2 is on. Figure 3 shows the interval when the inductor current is discharging through synchronous rectifier S1.

Figure 2 Positive one-half cycle inductor current charge interval. Source: Texas Instruments

Figure 3 Positive one-half cycle inductor discharge interval. Source: Texas Instruments

Figure 4 and Figure 5 illustrate the same behaviors for the negative one-half cycle.

Figure 4 Negative one-half cycle inductor current charge interval. Source: Texas Instruments

Figure 5 Negative one-half cycle inductor discharge interval. Source: Texas Instruments

ZVS

The use of GaN switches for S1 and S2 enables the converter to run at higher switching frequencies given the lower turn-on and turn-off losses of the switch. It is possible to achieve even higher frequencies, however, if the GaN switches can turn on with zero voltage switching (ZVS). The objective for this design is to achieve ZVS on every switching cycle for all line and load conditions. In order to do this, you will need two things:

• Feedback to tell the controller if ZVS has been achieved
• An algorithm that a microcontroller can execute in real time to achieve low total harmonic distortion (THD)

You can accomplish the first item through an integrated zero voltage detection (ZVD) sensor inside the GaN switches [1]. The ZVD flag works by asserting a high signal if the switch turns on with ZVS; if it does not achieve ZVS at turn-on, the ZVD signal stays low. Figure 6 and Figure 7 illustrate this behavior.

Figure 6 ZVD feedback block diagram with the LMG3425R030 GaN FET with an integrated driver, protection and temperature reporting as well as the TMS320F280049C MCU. Source: Texas Instruments

Figure 7 ZVD signal with ZVS (left) and ZVD signal without ZVS (right). The integrated ZVD sensor enables a ZVD flag that can be seen if the switch turns on with ZVS. Source: Texas Instruments

Integrating this function inside the GaN switch provides a number of advantages: minimal component count, low latency and reliable detection of ZVS events.

In addition to the ZVD signal, you also need an algorithm capable of calculating the switch timing parameters such that you can achieve ZVS and low THD simultaneously. Figure 8 is a block diagram of the hardware needed to implement the algorithm.

Figure 8 Hardware needed for the ZVD-based control method that enables an algorithm capable of calculating the switch timing parameters to achieve ZVS and a low THD simultaneously. Source: Texas Instruments

Solving the state plane for ZVS of the resonant transitions of the GaN FET’s drain-to-source voltage (VDS) will give you the algorithm for this design. Figure 9 illustrates the GaN FET VDS, inductor current, and control signals, along with both the time-domain and state-plane plots.

Figure 9 Resonant transition state-plane solution with the GaN FET VDS, inductor current, and control signals, along with both the time-domain and state-plane plots. Source: Texas Instruments

In Figure 9’s state-plane plot:

• “j” is the normalized current at the beginning and end of each dead-time interval
• “m” is the normalized voltage
• “θ” is used for the normalized timing parameters

The figure also shows the normalization relationships. The microcontroller in Figure 8 solves the state-plane system equations shown in Figure 9 such that the system achieves both ZVS and an ideal power factor. The ZVD signal provides feedback to instruct the microcontroller on how to adjust the switching frequency to meet ZVS.

Figure 10 shows the operating waveforms when the applied frequency is too low (left), ideal (center) and too high (right). You can see that both ZVD signals are present only when the applied frequency is at the ideal value; thus, varying the frequency until both FETs achieve ZVD will reveal the ideal operating point.

Figure 10 ZVD control waveforms when the applied frequency is too low (left), ideal (center) and too high (right). Source: Texas Instruments

Hardware performance

Figure 11 is a photo of a two-phase 5-kW design example using GaN and the previously described algorithm.

Figure 11 Two-phase 5 kW GaN-based PFC with the hardware required to apply algorithms to achieve even higher frequencies and enhance the efficiency of the overall solution. Source: Texas Instruments

Table 1 lists the specifications for the design example.

Parameters	Value
AC input	208V-264V
Line frequency	50-60Hz
DC output	400V
Maximum power	5kW
Holdup time at full load	20ms
THD	OCP v3
Electromagnetic interference	European Norm 55022 Class A
Operating frequency	Variable, 75kHz-1.2MHz
Microcontroller	TMS320F280049C
High-frequency GaN FETs	LMG3526R030
Low-frequency silicon FETs	IPT60R022S7XTMA1
Internal dimensions	38mm x 65mm x 263mm
Power density	120W/in3
Switching frequency	70kHz-1.2MHz

 Table 1 Design specifications for hardware example used in Figure 11.

Figure 12 shows the inductor current waveforms (ILA and ILB) and GaN FET VDS waveforms for both phases (VA and VB). The plots are at full power and illustrate three different operating conditions. In each case, you can see ZVS and a sinusoidal current envelope. The conditions for all three plots are VIN = 230VRMS, VOUT = 400V, P = 5kW, and 200V/div, 20A/div and 2µs/div.

Figure 12 The inductor current waveforms (ILA and ILB) and GaN FET VDS waveforms taken at full power for: (a) VIN≪VOUT/2, (b) VIN=VOUT/2, and (c) VIN≫VOUT/2. Source: Texas Instruments

Figure 13 shows the measured efficiency and THD for a system operating with a 230VAC input across the load range.

Figure 13 Efficiency and THD of a two-phase PFC operating with a 230VAC input across the load range. Source: Texas Instruments

 Reducing the footprint of a GaN power supply

GaN switches can increase the power density of a wide variety of applications by enabling faster switching frequencies. However, the addition of technologies such as advanced control algorithms can significantly reduce the footprint of a power supply even further. For more information about the reference design example discussed in this article, see reference [2].

Brent McDonald works as a system engineer for the Texas Instruments Power Supply Design Services team, where he creates reference designs for a variety of high-power applications. Brent received a bachelor’s degree in electrical engineering from the University of Wisconsin-Milwaukee, and a master’s degree, also in electrical engineering, from the University of Colorado Boulder.

Related Content

• Power Tips #124: How to improve the power factor of a PFC
• Power Tips #115: How GaN switch integration enables low THD and high efficiency in PFC
• Power Tips #116: How to reduce THD of a PFC
• PFC totem pole architecture and GaN combine for high power and efficiency

 References

1. Texas Instruments. n.d. LMG3526R030 650-V 30-mΩ GaN FET with Integrated Driver, Protection and Zero-Voltage Detection. Accessed Jan. 22, 2024.
2. Texas Instruments. n.d. “Variable-Frequency, ZVS, 5-kW, GaN-Based, Two-Phase Totem-Pole PFC Reference Design.” Texas Instruments reference design No. PMP40988. Accessed Jan. 22, 2024.

The post Power Tips #127: Using advanced control methods to increase the power density of GaN-based PFC appeared first on EDN.

Design options allow system designers to configure their system with the right performance, reliability, and safety considerations while meeting design cost and efficiency targets. The right design options can be even more important in high-voltage and/or high-current applications. In these high-power designs, an isolation technique with several integrated features can mean the difference between a product that meets and even exceeds customer expectations and one that generates numerous customer complaints.

For example, an integrated solid-state isolator (SSI) based on coreless transformer (CT) provides galvanic isolation with several design benefits. With integrated features such as a dynamic Miller clamp (DMC), overcurrent and overtemperature protection (OTP), under-voltage lockout protection, fast turn-on, and more, an integrated SSI driver can provide essential protection and ensure proper operation and extended life for high-power systems. These integrated protection features are not available in optical-based solid-state relays (SSRs).

Combined with the appropriate power switches, the highly integrated solid-state isolators allow designers to create custom solid-state relays capable of controlling loads in excess of 1,000 V and 100 A. The CT-based isolators enable energy transfer across the isolation barrier capable of driving large MOSFET or IGBT without the added circuitry of a power supply on the isolated side. SSRs designed with these innovative protection features can be highly reliable and extremely robust.

These coreless transformer-based isolators enable ON and OFF control, acting like a relay switch without requiring a secondary side, isolated power supply. Combined with MOSFETs and IGBTs, SSIs enable cost effective, reliable, and low power solid-state relays for a variety of applications. This includes battery management systems, power supplies, power transmission and distribution, programmable logic controllers (PLCs), industrial automation, and robotics as well as smart building applications such as heating, ventilation, and air conditioning (HVAC) controllers and smart thermostats.

Energy transfer through coreless transformer

The main design feature of an SSI device is a coreless transformer which enables power transfer across a galvanic isolation barrier of up to 10 mW. This eliminates the need for an isolated power supply for the switch reducing the bill of material (BOM) volume, count, and cost as well as providing a fast turn ON/OFF feature (≤ 1 µs) to ensure that the safe operating area (SOA) of the switch is adhered to.

Figure 1 Highly integrated solid-state isolators easily drive MOSFETs or IGBTs and do not require an isolated bias supply. Source: Infineon

Integrated protection

The integrated protection features of the CT-based isolators deserve further explanation. These include overcurrent and overtemperature protection (OTP), a dynamic Miller clamp, and under-voltage lockout (latch-off) protection as well as satisfying essential industry standards.

System and switch protection

Depending on the application’s need and product variant selected, SSIs offers overcurrent protection (OCP) as well as OTP either via an external positive temperature coefficient (PTC) thermistor/resistor or a MOSFET’s integrated direct temperature sensor.

In case of a failure event (overcurrent or overtemperature), SSI triggers a latch-off. Once triggered, the protection reacts quickly, turning off in less than 1 μs. Furthermore, it can support the AC-15 system tests, required for electromechanical relays according to the IEC 60947-5-1 under appropriate operating conditions.

Overcurrent protection

When operating solid-state relays, a common problem is the handling of fast overcurrent or short circuit events in the range of 20 A/μs up to 100 A/μs. Isolation issues often result in a short circuit with an extremely high current level that is defined by the power source’s impedance and cabling resistance.

Figure 2 shows a circuit for implementing the overcurrent protection. The shunt resistor (RSh) and its inherent stray inductance (LSh) generate a voltage drop that is monitored by the current sense comparator. Noise on the grid needs to be filtered out from the shunt signal, so an external filter (CF and RF) complements the integrated filter. When the comparator triggers, it activates the fast turn-off and latches the fault leaving the system in a safe state.

Figure 2 The above circuitry implements overcurrent protection using an isolator driver. Source: Infineon

Overtemperature protection

Another major known issue when operating solid-sate relays is the slow overload events that heat up the switches and the current sensor (shunt). Increased load current and insufficient thermal management can additionally shift the overall temperature above the thermal power transistor limits.

Figure 3 shows an example measurement of the overtemperature protection using an isolated driver. The SSI turns off two MOSFETs with integrated temperature sensors configured in a common-source mode. The sensing MOSFET heats up from the load current until the sensor voltage decreases below the comparator trigger threshold. As a result, the SSI’s output is turned off.

Figure 3 Isolated driver’s overtemperature protection triggers within 500 ns. Source: Infineon

The lower part of Figure 3 depicts a detailed zoom into the turn-off in this measurement with a time resolution of 500 ns per division. This reduced timeframe shows that the gate is turned off in much less than 500 ns. This means that the switched transistors do not violate their safe operating area.

Dynamic Miller clamping protection

Some SSIs also have an integrated dynamic Miller clamp to protect against spurious switching due to surge voltages and fast electric transients as well as the dv/dt of the line voltage. The dv/dt applied by the connected AC voltage creates capacitive displacement currents through the parasitic capacitances of a power transistor.

This can lead to parasitic turn-on of the power switch by increasing the voltage at its gate node during its “off” state. The dynamic Miller clamping feature ensures that the power switch remains safe in the “off” state.

When failure is not an option

When matched with the appropriate power switch, the isolator drivers enable switching designs with a much lower resistance compared to optically driven/isolated solid-state solutions. This translates to longer lifespans and lower cost of ownership in system designs. As with all solid-state isolators, the devices also offer superior performance compared to electromagnetic relays, including 40% lower turn-on power loss and increased reliability due to the elimination of moving or degrading parts.

When failure is not an option, the right choice of isolation can mean the difference between design success and failure.

Dan Callen Jr. is a senior manager at Power IC Group of Infineon Technologies.

Davide Giacomini is director of marketing at Power IC Group of Infineon Technologies.

Sameh Snene is a product applications engineer at Infineon Technologies.

Related Content

• Isolated Gate Drivers for GaN MOSFETs
• Gate Driver Solutions Proliferate for Motor Control
• Improving Energy Efficiency with a SiC Isolated Gate Driver
• Galvanic Isolation in Electric and Hybrid Vehicle Applications
• Isolation is good when it’s digital: Protect your people and devices

The post The advantages of coreless transformer-based isolators/drivers appeared first on EDN.

With the continuous surge in demand for silicon carbide (SiC) substrates in recent years, the call for cost reduction in SiC has been growing stronger, as the ultimate product price remains the key determinant for consumers, says market research firm TrendForce...

So I dissembled a old broken vhr and I was really surprised when I found out they used a axial motor back in the day, I thought it was only recently used so yeah submitted by /u/EldenQC [link] [comments]

submitted by /u/EricNava98 [link] [comments]

Admiration for this beautiful technology I own. submitted by /u/CarbonTires [link] [comments]

In this article, we conclude our discussion of VNAs by walking through the steps of a SOLT calibration and examining the potential non-idealities of its reference standards.

​ POV display working The idea was to build a 128 pixel POV display that can display small GIF images. Happy with how it turned out. Like always the GERBER, Code and 3D model is made open-source Also built a Image to code converter for this POV display : https://circuitdigest.com/calculators/pov-display-image-to-code-converter POV display with 3D printed enclosure Full tutorial: POV Displayfrom CircuyitDigest submitted by /u/HotReaction4663 [link] [comments]

So uh apparently I must’ve forgotten to set my dimensions to the silkscreen layer and it printed as traces since it was on the signal layer 😆🤦 submitted by /u/welpthatsucks12345 [link] [comments]

submitted by /u/Athosworld [link] [comments]

This author (Stephen Fleeman) is a retired engineering professor and aerospace engineer, who loves electronics and is one of the most genius circuit analysis gurus I’ve ever met. This is his most recent article on engineering.com. Check out the others too if you like this one! submitted by /u/Wintermute815 [link] [comments]

submitted by /u/AutoModerator
[link] [comments]

Nvidia took the GTC stage to unveil Blackwell, a platform built upon a 208 billion transistor, dual-die GPU with a 10 TB/s chip-to-chip interconnect.

At the Optical Fiber Communication Conference & Exposition (OFC 2024) in San Diego, CA, USA (24–28 March), TRUMPF Photonic Components GmbH of Ulm, Germany (part of the TRUMPF Group) – which makes vertical-cavity surface-emitting lasers (VCSELs) and photodiodes for the consumer electronics, datacoms, industrial sensing & heat treatment and automotive markets – is demonstrating 100Gbps VCSEL performance together with customer Optomind Inc of Suwon, South Korea, which provides optical interconnect solutions for data centers including artificial intelligence (AI) and high-performance computing (HPC) networks. With increasing demand for multi-channel high-speed data transmission in artificial intelligence/machine learning (AI/ML)-based hyperscale cloud computing space, 800Gbps data rate at 100Gbps per lane and beyond is essential...

Silicon photonics-based chip-to-chip optical connectivity firm Ayar Labs of Santa Jose, CA, USA is presenting its latest technology advances and ecosystem partnerships in booth #1511 at the Optical Fiber Communication Conference & Exposition (OFC 2024) in San Diego, CA, USA (24–28 March)...

Three trench Schottky rectifiers from Diodes deliver 2 A with low forward voltage drop in chip-scale packages that require just 0.84 mm2 of PCB space. The SDT2U30CP3 (30 V/2 A), SDT2U40CP3 (40 V/2 A), and SDT2U60CP3 (60 V/2 A) can be used as blocking, boost, switching, or reverse-protection diodes in portable, mobile, and wearable devices.

The rectifiers come in 1.4×0.6-mm X3-DSN1406-2 packages, with a typical profile of 0.25 mm. According to the manufacturer, they are among the smallest in their class. Their low forward voltage drop of 480 mV maximum (580 mV for the SDT2U60CP3) minimizes conduction losses and improves efficiency. Additionally, the devices’ avalanche capability allows them to rapidly respond to voltage spikes to protect electronic circuits from damage.

The SDT2U30CP3, SDT2U40CP3, and SDT2U60CP3 rectifiers cost $0.16, $0.17, and $0.19 each, respectively, in lots of 2500 units. They are lead-free and fully compliant with RoHS 3.0 standards.

SDT2U30CP3 product page

SDT2U40CP3 product page

SDT2U60CP3 product page

Diodes

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post 2-A Schottky rectifiers occupy tiny footprint appeared first on EDN.

Wet aluminum electrolytic capacitors in the AEF series from Kyocera AVX come in 11 different case sizes with capacitance ratings from 2.2 µF to 470 µF. Voltage ratings for the V-chip (can-type) capacitors range from 6.3 VDC to 400 VDC.

Targeting a broad range of industrial and consumer electronics applications, the components can be surface-mounted on high-density PCBs. The series comprises 59 variants in case sizes spanning 0608 to 1216. They exhibit low direct current leakage (DCL) and low equivalent series resistance (ESR), which enables higher tolerance for ripple currents. Capacitance tolerance is ±20%.

AEF series capacitors are available for operation over two temperature ranges: -40°C to +105°C and -55°C to +105°C. They have a lifetime of 6000 hours at +105°C and rated voltages. The devices are supplied with pure tin terminations on 13-in. or 15-in. reels compatible with automated assembly equipment. Standard lead time is 24 weeks.

AEF series product page

Kyocera AVX 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Kyocera AVX rolls out expansive line of capacitors appeared first on EDN.

Frontgrade Technologies has developed a plastic-encapsulated version of its UT32M0R500 radiation-tolerant microcontroller aimed at space missions. Built around a 32-bit Arm Cortex-M0+ core, the plastic UT32M0R500 is set for flight grade production in July 2024 after meeting NASA’s PEM INST-001 Level 2 qualification.

Housed in a 14.5×14.5-mm, 143-pin plastic BGA package, the UT32M0R500 offers the same I/O configuration and features as its ceramic QML counterpart. It tolerates up to 50 krads of total ionizing dose (TID) radiation. For design flexibility, the device combines two independent CAN 2.0B controllers with mission read/write flash memory and system-on-ship functionality. This integration enables designers to manage board utilization, while reducing both cost and complexity.

“The proliferation of satellites for LEO missions is increasing the demand for highly reliable components with efficient SWaP-C characteristics and radiation assurances,” said Dr. J. Mitch Stevison, president and CEO of Frontgrade Technologies. “Adding another plastic device to our portfolio that is qualified to NASA’s Space PEM Level 2 strengthens our position as a trusted provider of high reliability, radiation-assured devices for critical space missions.”

The UT32M0R500 is supported by Arm’s Keil suite of embedded development tools.

UT32M0R500 product page

Frontgrade Technologies

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Plastic ARM-based microcontroller is space-ready appeared first on EDN.

Omnivision’s OV50K40 smartphone image sensor with TheiaCel technology achieves human eye-level high dynamic range (HDR) with a single exposure. Initially introduced in automotive image sensors, TheiCel employs lateral overflow integration capacitors (LOFIC) to provide superior single-exposure HDR, regardless of lighting conditions.

The OV50K40 50-Mpixel image sensor features a 1.2-µm pixel in a 1/1.3-in. optical format. High gain and correlated multiple sampling enable optimal performance in low-light conditions. At 50 Mpixels, the sensor has a maximum image transfer rate of 30 fps. Using 4-cell pixel binning, the OV50K40 delivers 12.5 Mpixels at 120 fps, dropping to 60 fps in HDR mode but with a fourfold increase in sensitivity.

To achieve high-speed autofocus, the OV50K40 offers quad phase detection (QPD). This enables 2×2 phase detection autofocus across the sensor’s entire image array for 100% coverage. An on-chip QPD remosaic enables full 50-Mpixel Bayer output, 8K video, and 2x crop-zoom functionality.

The OV50K40 image sensor is now in mass production.

OV50K40 product page  

Omnivision

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Image sensor elevates smartphone HDR appeared first on EDN.

Qualcomm’s Snapdragon 8s Gen 3 SoC offers select features of the high-end Snapdragon 8 Gen 3 for a wider range of premium Android smartphones. The less expensive 8s Gen 3 chip provides on-device generative AI and an always-sensing image signal processor (ISP).

The SoC’s AI engine supports multimodal AI models comprising up to 10 billion parameters, including large language models (LLMs) such as Baichuan-7B, Llama 2, Gemini Nano, and Zhipu ChatGLM. Its Spectra 18-bit triple cognitive ISP offers AI-powered features like photo expansion, which intelligently fills in content beyond a capture’s original aspect ratio.

The Snapdragon 8s Gen 3 is slightly slower than the Snapdragon 8 Gen 3, and it has one less performance core. The 8s variant employs an Arm Cortex-X4 prime core running at 3 GHz, along with four performance cores operating at 2.8 GHz and three efficiency cores clocked at 2 GHz.

Snapdragon 8s Gen 3 will be adopted by key smartphone OEMs, including Honor, iQOO, Realme, Redmi, and Xiaomi. The first devices powered by the 8s Gen 3 are expected as soon as this month.

Snapdragon 8s Gen 3 product page

Qualcomm Technologies

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Snapdragon SoC brings AI to more smartphones appeared first on EDN.