Microelectronics world news

Understanding Magnetic Field Energy and Hysteresis Loss in Magnetic Cores

AAC - Wed, 06/26/2024 - 22:00
In this article, we use the concept of magnetic field energy to explore the relationship between a core's hysteresis loss and its B-H curve.

EC and Italian government awards IPCEI ME/CT funding to GlobalWafers/MEMC to establish 300mm wafer production

Semiconductor today - Wed, 06/26/2024 - 19:57
GlobalWafers Co Ltd of Hsinchu, Taiwan (GWC, the world’s third largest supplier of semiconductor wafers) says that the Italian Ministry of Enterprises and Made in Italy (MIMIT) — following project authorization by the EU Commission (Directorate General for Competition) — issued an Assignment Decree awarding MEMC Electronic Materials S.p.A. of Novara, Italy an R&D grant of up to €103m to establish Europe’s most advanced 300mm semiconductor wafer production facility...

SK keyfoundry intensifying efforts to develop GaN for power electronics

Semiconductor today - Wed, 06/26/2024 - 19:12
South Korea-based SK keyfoundry — which provides specialty analog and mixed-signal foundry services on 8-inch wafers for consumer, communications, computing, automotive and industrial applications — says that, after recently achieving key device characteristics, it is intensifying its efforts to develop 650V gallium nitride (GaN) high-electron-mobility transistors (HEMTs) as it aims to complete development by the end of this year...

The good, the bad, and the ugly of zero trims

EDN Network - Wed, 06/26/2024 - 17:51

Manual amplifier nulling circuits are simple topologies, typically consisting of just a trimmer pot and a couple of fixed resistors intended to allow offset adjustment by a (usually small) symmetrical fraction of bipolar supply voltages. So, it’s surprising how many variations exist, some very good, some very not. Figure 1 is an example of the latter case.

Figure 1 The bad: Attenuation of the supply voltages is done with subtraction instead of division, destroying the PSRR of the amplifier.

Wow the engineering world with your unique design: Design Ideas Submission Guide

This zero trim is a bad idea because attenuation of the supply voltages is done with (V+ – V–) subtraction instead of division. This virtually destroys the PSRR of the amplifier. That’s pretty bad.

Figure 2 corrects this serious defect, achieving attenuation with a proper (R3/R2) voltage divider instead of PSRR-robbing subtraction. But it still isn’t very pretty. Here’s why.

Figure 2 The ugly: An attempt to correct for the destroyed PSRR can be done by achieving attenuation with a voltage divider instead; however, the supply rails must be symmetrical, leading us back to our PSRR problem.

 Figure 2 can only give the (usually) desirable symmetrical trim range if the supply rails are likewise symmetrical (and vice versa). You could add a series resistor between R1 and the larger rail voltage to fix the problem, but that would (at least partly) revive the PSRR shortcoming of Figure 1. Ugly.

Figure 3 fixes both problems.

Figure 3 The good: Setting R2 = R3(-V+/ V–)/2 to get a symmetrical trim range.

All you have to do is set R2 = R3(-V+/ V–)/2 to get a symmetrical trim range regardless of the actual supply rail voltage ratio.

And I think that’s pretty good.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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IEEE’s 2nd Wide Bandgap Power Devices in Europe conference being held in South Wales

Semiconductor today - Wed, 06/26/2024 - 16:19
The Institute of Electrical and Electronics Engineers (IEEE) is hosting its second bi-annual Power Electronics and Wide Bandgap Power Devices and Applications (WiPDA-Europe 2024) conference at the Royal Welsh College of Music and Drama in Cardiff City Centre, Wales, UK (16-18 September)...

Tiny But Mighty: Ceva Reveals New NPUs for Tiny Machine Learning Devices

AAC - Wed, 06/26/2024 - 16:00
The new neural processing unit is designed for edge AI applications that require targeted machine learning in resource-constrained settings.

Explore the power of connectivity with STMicroelectronics at MWC Shanghai 2024

ELE Times - Wed, 06/26/2024 - 15:04

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, will exhibit at MWC Shanghai 2024 (Booth N1.D85) on 26-28 June.

ST is at the forefront of innovation, developing unique technologies and products that empower our customers to overcome challenges and capitalize on opportunities. At MWC Shanghai 2024, ST will collaborate with its ecosystem partners to present industry-leading solutions. Visitors will be immersed in the transformative power of connectivity with over 30 demonstrations designed to showcase our commitment to technological excellence and especially the future of connected experiences. These will be featured across 9 major application zones:

  • Smart Charging
  • Secure & Connectivity
  • IMU Attitude Detection
  • Smart Personal Electronics
  • Time-of-Flight & Smart Cameras
  • Air Quality Monitoring based on FlightSense
  • Bluetooth Connectivity & Low Power MCU
  • Edge AI & GUI
  • ST60 mmW Contactless Connector

Secure & Connectivity: According to the International Telecommunication Union (ITU), a staggering 2.6 billion people are still unconnected, 1.4 billion of whom are unbanked, mainly in emerging countries. This disconnect not only excludes them from the digital revolution, but also hinders economic development. To enable a seamless “tap and go” experience, KaiOS has collaborated with STMicroelectronics to develop game-changing solutions designed for underserved transportation drivers. At MWC Shanghai, STMicroelectronics and KaiOS will showcase a solution designed for informal transportation drivers. Utilizing the ST54L chip, this innovative solution combines an NFC controller with an integrated secure element (SE) IC to transform a simple “KaiOS-equipped smart feature phone” into a powerful tool for informal drivers, enabling the KaiOS “smart feature phone” to provide secure contactless ticketing, replacing cash transactions with contactless ones.

Air Quality Monitoring based on FlightSense: Measuring air quality has become crucial due to its direct impact on human health and the environment. A growing body of scientific evidence indicates that the air within homes and other buildings can be more seriously polluted than outdoor air. Most existing AQI stations are designed for outdoor and professional use; however, environmental analysis is now possible in consumer devices. At MWC Shanghai, visitors will have the exclusive opportunity to see the innovative personal mobile environmental monitor in action. ST and Mobile Physics will present a solution for air quality and smoke detection with ST’s VL53L8 direct Time-of-Flight sensor. The comprehensive system includes the VL53L8 hardware, along with tailored firmware and software, plus pioneering air quality algorithms developed by Mobile Physics. The VL53L8 is capable of measuring PM2.5 concentrations within 10% or 10µg/m³ of the reference sensor. Designed for seamless integration, this system is ideal for mobile phones, personal electronics, and a wide array of IoT products.

Bluetooth Connectivity & Low Power MCU:

ST will demonstrate two Bluetooth LE Audio solutions based on the recently announced STM32WBA55 microcontroller. Visitors are invited to put on headphones to personally experience the listening effects in unicast and broadcast scenarios. Harnessing the cutting-edge wireless STM32WBA5 series, ST has now integrated support for the newly finalized Bluetooth LE Audio specifications, achieving certification that unlocks the potential for groundbreaking products. These innovations promise to enrich audio experiences with superior listening, hearing, and sharing capabilities. Among these, the innovative Bluetooth LE Audio Auracast feature stands out, offering a transformative approach to audio broadcasting and sharing, and heralding a new era of auditory communication.

To display its expansive portfolio of solutions across different sectors at MWC Shanghai, ST will also showcase its advanced wireless charging and wireless power-transfer solutions. Highlights include the high-efficiency, compact 100W laptop wireless charger, boasting WPC Qi 1.3 compliance with a security profile, capable of supporting up to a 100W output using ST’s proprietary protocol (STSC). Additionally, ST offers an up to 300W wireless power transfer discrete solution designed for industrial applications with fast load transient response, wider spatial freedom, better thermal dissipation, and a user experience comparable to that of a wired power supply.

ST is proud to present the ST4SIM-300, its first eSIM compliant with the GSMA’s eSIM specification for IoT. The ST4SIM-300 unlocks new possibilities, including over-the-air profile swaps, and is supported by a streamlined ecosystem.  This design is well-suited for compact devices without a user interface. By integrating the ST4SIM-300 into their designs, IoT developers can now ensure the best connectivity anywhere, at any time.

At MWC Shanghai, ST will also showcase a solution that propels consumer products into the realm of high-end applications. With 6-axis architecture, the LSM6DSV32X Inertial Measurement Unit (IMU) is capable of superior edge processing, making it ideal for applications such as advanced 3D mapping on phones, contextual awareness in laptops and tablets, precise gesture recognition in AR and VR headsets, and always-on tracking in wearables.

Learn more about ST at MWC Shanghai 2024 and explore the power of connectivity together with us: https://www.st.com/content/st_com/en/events/mwc-shanghai-2024.html

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India Poised to Become Global Leader in Semiconductor and Electronics Manufacturing, says RBI

ELE Times - Wed, 06/26/2024 - 14:22

The Reserve Bank of India’s (RBI) annual report highlights India’s potential to become a global semiconductor and electronics manufacturing hub, driven by recent government initiatives. Key highlights include:

  1. Government Initiatives and Budget Allocation:
  • The interim Union Budget 2024-25 allocates ₹6,903 crore for semiconductor and display fabs.
  • Investments under the production-linked incentive (PLI) scheme are expected to gain momentum.
  1. Economic Growth and Employment:
  • These investments are anticipated to create new employment opportunities, improve labor incomes, and strengthen domestic demand.
  • Real GDP growth for 2024-25 is projected at 7.0%.
  1. Research and Innovation Boost:
  • The passage of ‘The Anusandhan National Research Foundation Bill, 2023’ will establish the Anusandhan National Research Foundation (NRF) to enhance research and innovation in basic science, healthcare, and humanities.
  1. National Quantum Mission (NQM):
  • Approved at a total cost of around ₹6,000 crore from 2023-24 to 2030-31, the NQM aims to scale up scientific and industrial R&D in quantum technology.
  • This mission aligns with national priorities like Digital India, Make in India, Skill India, Stand-up India, Start-up India, Self-reliant India, and the Sustainable Development Goals (SDGs).
  1. Infrastructure and Digital Technologies:
  • Government-led investments in infrastructure and the increasing adoption of digital technologies are expected to boost productivity and potential growth in the medium term.

These initiatives are poised to strengthen India’s position in the global semiconductor and electronics manufacturing sectors, fostering significant economic growth and technological advancement.

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Arduino shield simplifies use of fibre-optic datalink in MPU designs

ELE Times - Wed, 06/26/2024 - 14:09

OMC has introduced the H19 fibre optic shield, designed for the Arduino Uno, to facilitate the integration of optical fibre datalinks into microprocessor-based designs. This shield combines a transmitter, receiver, necessary drivers, and digital output, simplifying the receiver circuit by eliminating the need for a pin diode amplifier and Schmitt trigger circuits.

William Heath, OMC’s Commercial Director, highlighted the reliability and security of fibre optic datalinks, emphasizing their noise-free, interference-proof, and electrically isolated nature. The shield is stackable, featuring jumpers for both transmitter and receiver devices. It includes an example program to demonstrate data transmission over the optical fibre link using UART ports. Data can be monitored via the Arduino software’s serial monitor or interfaced with a standard 16×2 LCD shield stacked on top of the fibre shield.

The shield supports various microprocessor baud rates from 300 to 115200, with the optical fibre emitter and receiver capable of operating up to 5Mbd. It works with PMMA cables up to 25 meters in standard configuration, with high-power emitters and glass fibre options for extended range or specific applications. OMC offers customizable transmitter and receiver parts for integration into customers’ designs, including different cable lengths and fibre/jacket types.

This new product showcases the potential of incorporating fibre optic links into digital systems, providing a reliable and straightforward solution for secure data transmission.

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Early Access to MPLAB Extensions for VS Code Provides Designers with the Ability to Utilize Microchip’s Development Tools Inside of the Popular IDE

ELE Times - Wed, 06/26/2024 - 14:02

Extensions are the company’s first steps in a longer-term plan to expand its portfolio and better serve developers working within the VS Code ecosystem

Leveraging the versatility of Microsoft Visual Studio Code (VS Code), Microchip Technology has released an early access version of MPLAB Extensions for VS Code. This launch provides embedded designers with tools to import projects from MPLAB X Integrated Development Environment (IDE) to VS Code while still accessing Microchip’s debugging and programming support. This initiative is part of Microchip’s long-term strategy to expand its offerings and serve developers working within the VS Code ecosystem.

MPLAB X IDE is an expandable, highly configurable software program that incorporates powerful tools to help developers discover, configure, develop, debug and qualify embedded designs for most Microchip microcontrollers and digital signal controllers. The VS Code extensions merge the capabilities of MPLAB X IDE with the flexibility of VS Code to create a more seamless and efficient development environment for both new and existing customers. These products are being released under an early access program to provide the essential tools to customers quickly, while the Microchip development team continues to refine the extensions based on user feedback.

“At Microchip, we are dedicated to meeting developers in their environment of choice. VS Code is an extremely popular tool, and the recent MPLAB Extensions enable developers to continue working in the IDE they are most familiar with, while taking full advantage of Microchip’s complete device support and toolset,” said Rodger Richey, vice president of development systems and academic programs at Microchip. “This fusion offers an optimal blend of familiarity and functionality, providing an easy path for developers to integrate our resources and components.”

During this early access release, the MPLAB Extensions for VS Code include capabilities such as MPLAB X IDE project import and the ability to compile, program and perform basic debugging with any supported Microchip device. Additionally, MPLAB Data Visualizer can be utilized inside VS Code through an extension, offering users the opportunity to see what’s happening on the device at run time.

Future updates will bring MPLAB Code Configurator into VS Code to help set up preconfigured projects. Development has also started on a VS Code extension for the MPLAB Machine Learning Development Suite and an additional MPLAB Extension for AI code-generative assistance to review and improve code from inside the IDE.

The introduction of MPLAB Extensions for VS Code signifies a new phase of accessibility and flexibility for developers using Microchip tools. This launch represents the first instance of the MPLAB IDE software being available outside the MPLAB development ecosystem, but it is just the beginning of Microchip’s broader integration with the VS Code community. The current features are designed to meet the immediate needs of developers, with the intention to continue refining the toolset and introducing new extensions with added functionality in the future.

To learn more about Microchip’s ecosystem of development tools and software, visit https://www.microchip.com/en-us/tools-resources.

Pricing and Availability

MPLAB Extensions for VS Code are available for free; some advanced features may require a subscription license. For additional information and to purchase, contact a Microchip sales representative, authorized worldwide distributor or visit Microchip’s Purchasing and Client Services website, www.microchipdirect.com.

Resources

High-res images available through Flickr or editorial contact (feel free to publish):

  • Application image: https://www.flickr.com/photos/microchiptechnology/53785645044/sizes/l/
  • Videos available through YouTube or editorial contact (feel free to post):
    https://www.youtube.com/playlist?list=PLtQdQmNK_0DRncMlBVPL2JTDJnOpDdSWi

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Keysight Streamlines and Automates Samsung Semiconductor India Research’s 5G Field-to-Lab Workflow

ELE Times - Wed, 06/26/2024 - 13:25
  • Test automation solution quickly analyzes field logs and replicates complex 5G field issues in the lab as a test script
  • Solution enables Samsung Semiconductor India to significantly reduce the time it takes to replicate field scenarios in the lab and increase time spent on improving end user quality of experience

Keysight Technologies, Inc. (NYSE: KEYS) announces that Samsung Semiconductor India Research (SSIR) has selected the Keysight Signaling Field-To-Lab (S-FTL) solution to streamline and automate its 5G field-to-lab workflow in its Bengaluru lab. The comprehensive, end-to-end 5G wireless protocol signaling solution improves end-user quality of experience (QoE) by accelerating the replication, analysis, and resolution of 5G field issues in a test lab environment.

As 5G continues to be deployed, the focus has shifted to ensuring users receive the highest QoE by rapidly resolving issues reported from the field. A significant challenge is replicating complicated field scenarios in a lab environment to identify possible solutions. This involves the complex, time-consuming process of analyzing field logs, which are often missing data or contain errors, in order to replicate the issues. To solve this challenge, mobile operators, device makers, and chip manufacturers need an efficient and reliable solution that can quickly translate device field logs into precisely replicated protocol sequences in the lab.

To assist its global customer base, SSIR sought an intelligent test automation solution that could replicate field issues in its Bengaluru test lab. In addition, SSIR was looking for a solution allowing its engineers to focus on addressing field issues rather than analyzing logs or creating test cases. SSIR chose the Keysight S-FTL solution because it enables automated test case creation from device field logs. Based on the 5G Protocol R&D Toolset, this solution automates the process by analyzing field logs for 5G / 4G and IMS, making protocol-based adjustments to ensure protocol compliant behavior, and then replicating the field scenario as a test script. The S-FTL solution features an open input log template that accommodates various formats to enable faster adoption into the workflow.

By using the Keysight S-FTL solution, SSIR has significantly reduced the time it takes to replicate field scenarios in the lab and increased the time its engineers spend on improving end-user QoE. The solution has helped resolve a wide range of issues from real-world scenarios such as voice / data calls, handovers, 5G to 4G mobility, and carrier aggregation for deployments ranging from single SIM, dual SIM, and dual connectivity.

Balajee Sowrirajan, Corporate EVP & MD, SSIR, said: “Our partnership with Keysight has leveraged each of our strengths to recreate real-world field scenarios in a lab environment. This collaboration has accelerated resolution of communication and connectivity issues for our wireless modem customers. With a comprehensive set of tools and techniques for testing, the S-FTL solution enables our engineers to identify and resolve communication issues more accurately. This has also helped to significantly save validation costs and turnaround time. In a nutshell, it has ensured reliability and cost effectiveness, the two most critical components in today’s rapidly evolving telecommunications landscape.”

Cao Peng, Vice President and General Manager for Keysight’s Wireless Test Group, said: “We are pleased to support SSIR’s strategic goals in the current 5G technology phase of network rollout and field integration testing. Keysight’s automated software-based chipset and device test solutions for replicating field issues are designed to help improve efficiency of the process. Keysight is committed to delivering test solutions that help accelerate the commercial introduction of 5G devices and networks to 5G leaders such as SSIR.”

Resources
  • 5G Signaling Field to Lab Solution
  • Signaling Field to Lab Demo Video
  • S8701A Protocol R&D Toolset

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NY CREATES and CEA-Leti Announce Strategic Research Partnership

ELE Times - Wed, 06/26/2024 - 12:46

Trans-Atlantic Collaboration Starts with Focus on Enabling Next-Gen
Magnetic Memory Devices at the 300mm Wafer Scale

NY CREATES and CEA-Leti today announced their strategic partnership that will initially focus on the research and co-development of magnetic memory devices, which are used to store computer data. These devices would be produced at the 300mm wafer scale, the industry-standard platform upon which computer chips are produced. The announcement was made during the annual Leti Innovation Days in Grenoble.

Officials from the New York Center for Research, Economic Advancement, Technology, Engineering, and Science (NY CREATES), based in Albany, N.Y., USA, and CEA-Leti, based in Grenoble, France, established this joint development agreement to build upon each other’s strengths in the areas related to memory device R&D. CEA-Leti will contribute its expertise in magnetics, spintronics, and the testing of related devices, and NY CREATES will provide the facilities, process integration expertise, and materials process development to run the 300mm silicon hardware.

“By expanding our partnership with CEA-Leti and applying their recognized expertise in device physics and architectures, NY CREATES looks forward to jointly developing innovative technologies for computing. While we are known for our world-class Albany NanoTech Complex with experts in R&D focus areas ranging from advanced logic technologies to heterogeneous integration and more, this initiative’s focus on novel memory is an area in which we can break barriers together,” said NY CREATES President Dave Anderson. “A first objective of this collaboration will be to develop novel magnetic memory architectures and integration. This international partnership will help to address present-day memory needs as computing power continues to progress, and we anticipate a fruitful collaboration.”

“This collaboration will allow CEA-Leti to expand its capability to validate innovative concepts in synergy with the various facilities we have in Grenoble,” said CEA-Leti CEO Sébastien Dauvé. “We strongly believe that our collaboration will be a key enabler for both NY CREATES and CEA-Leti to be much more efficient in the lab-to-fab transition and to better impact our respective local ecosystems with more mature innovations.”

More specifically, the first joint research effort seeks to demonstrate two novel forms of memory devices: Spin Orbit Torque (SOT) Magnetoresistive Random Access Memory (MRAM), and Spin Transfer Torque (STT) MRAM. While both forms of MRAM manipulate different materials’ magnetization to store data, STT MRAM offers non-volatile memory with almost no power leakage; SOT MRAM is considered faster and more efficient.

Leaders of both R&D organizations expect the two-year collaboration to leverage NY CREATES’ 300mm wafer R&D ecosystem centered at its Albany NanoTech Complex, the most advanced non-profit semiconductor R&D facility in North America. CEA-Leti will provide its world-class engineering services and know-how to produce working memory elements on 300mm wafers.

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Donaldson’s new Dual-Stage Jet battery vent takes degassing rates to unmatched levels while reducing cost and complexity for OEMs

ELE Times - Wed, 06/26/2024 - 12:31

The unique medium-pressure design ejects the poppet and cap to provide a larger opening for gas to escape during an emergency situation, boosting safety and reducing the risk of damage to other battery packs. It’s so efficient, it can reduce the number of vents required on a battery pack by up to 90%.

Donaldson has extended its range of battery venting systems with the Dual-Stage Jet, a brand-new design that takes electric vehicle (EV) safety to a whole new level by offering the industry’s fastest degassing capabilities, while streamlining the installation process for OEMs. Launched this week at The Battery Show in Stuttgart, Germany, Dual-Stage Jet has been purposely designed to meet the increased demands of today’s more complex and powerful batteries – from providing enhanced pressure equalisation and ingress protection under normal operating conditions to allowing gases to escape at rates of approximately 100 lit/sec @ 100 mbar when necessary.

“Customers were telling us that they needed even higher degassing rates than what was available on the market, so the Donaldson Vehicle Electrification Development engineering team came up with a unique, creative design where the poppet and cap can be jettisoned to instantly produce a much larger opening for gas to escape and help mitigate thermal runaway,” explains Shane Campbell, Product Manager for Vehicle Electrification at Donaldson. “The pressure then rapidly decreases inside the pack, greatly reducing the risk of damage to additional cells and giving occupants extra time to escape from the vehicle.”

Tailored to OEM needs

Dual-Stage Jet is available in two distinct configurations – screw-in/bolt-on or quarter-turn bayonet fittings. Agricultural and other heavy-duty vehicle manufacturers are likely to favour the former, which can offer more flexibility for use in bulkier battery packs, while the lighter bayonet fittings will be of greater appeal to the automotive sector and provide clear haptic feedback of proper installation.

The new vent is now available for vehicle manufacturers, with the possibility for them to work on further customising the design to their precise needs in partnership with Donaldson’s own application engineers. “Our customers often have different thicknesses of aluminium for their battery pack housing, but it’s easy for us to make an almost identical part that has a small change in the leg length when required,” says Matt Goode, Engineering Manager – Vehicle Electrification Development, Donaldson.

“The option of multiple attachment methods is important to our customers, who want something that integrates really easily with their existing pack, and with application engineers all over the globe, we’re located near the OEM wherever they may be. I think our customers find it refreshing that we take the time to understand their true needs and then find the best solution for them, rather than an ‘off-the-shelf take it or leave it’ type of approach.

“Another major benefit is that these high-performance vents can reduce the number required on a battery pack by 50-90%,” continues Matt. “As well as reducing product cost, this also leads to significant time and money savings in the assembly, ordering and stock-keeping processes.”

Effective ventilation means efficient performance

At 58mm in diameter, and containing approximately 20% recycled plastic, the vent also delivers a simple solution to the occasionally tricky problem of performing a leak test on a product expressly designed to provide effective ventilation. Temporarily sealing the vent using the supplied leak-check cap is all that is required for manufacturers to carry out tests themselves.

Using Donaldson’s proprietary Tetratex expanded polytetrafluoroethylene (ePTFE) membranes for enhanced protection from contaminants, the Dual-Stage Jet enables consistent pressure equalisation with a minimum airflow of 97 lit/hr @ 10 mbar during normal operation. Manufactured in-house, the hydrophobic membrane is comprised of small, randomly connected fibrils that create a permeable water barrier, providing continuous pressure equalisation, while offering IP67, IP68 and IP69K ingress protection against water, dirt, and other contaminants. The membrane’s unique oleophobic treatment also helps the filter media repel oils, providing additional protection.

By ensuring that damp air, which could otherwise accumulate inside the battery housing, is expelled, the effective ventilation provided by the new vent thereby helps to prevent potential internal condensation issues reducing the lifespan of enclosures and batteries alike.

“Quality and reliability are top of our customers’ agenda, and our new vent really fits the bill,” concludes Shane. “Dual-Stage Jet is a fantastic addition to our portfolio; one that enables us to serve more of the global EV market by providing another best-in-class product while offering our customers even greater choice to match their specific applications. Our Dual-Stage Burst design is still available, with a high opening pressure [25 lit/sec @ 300 mbar] while Dual-Stage Jet occupies the medium-pressure section of our portfolio – facilitating industry-leading degassing airflow through a design that’s never been seen until now.”

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The 800V EV Transition: HIL Simulation’s Critical Role

ELE Times - Wed, 06/26/2024 - 12:10

In the rapidly evolving landscape of electric vehicles (EVs), the shift towards 800V power system architectures is gaining serious momentum. Our white paper “HIL Simulation’s Crucial Role in the 800V EV Transition” explores the reasons behind the move to 800V, the varied challenges this move presents to test professionals, and the pivotal role hardware-in-the-loop (HIL) simulation is playing in the transition from 400V to 800V architectures. In addition, we detail how to efficiently create a HIL test platform and outline a detailed migration path for testing 800V architectures.

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Cadence Expands System IP Portfolio with Network on Chip to Optimize Electronic System Connectivity

ELE Times - Wed, 06/26/2024 - 12:02

Cadence Janus NoC enables design teams to achieve better PPA faster and with lower risk, freeing up valuable engineering resources for SoC differentiation

Cadence Design Systems, Inc. today expanded its system IP portfolio with the addition of the Cadence Janus Network-on-Chip (NoC). As larger, more complex SoCs and disaggregated multi-chip systems proliferate to accommodate today’s escalating compute demands, data delivery within and between silicon components has become increasingly challenging—impacting power, performance and area (PPA). The Cadence Janus NoC manages these simultaneous high-speed communications efficiently with minimal latency, enabling customers to achieve their PPA targets faster and with lower risk.

“Cadence is an established leader in IP and design quality, and we continue to invest in our foundational interface and processor IP, system IP, software and design services capabilities to enable our customers to develop differentiated and disaggregated designs,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “The addition of the Cadence Janus NoC to our growing system IP portfolio is a key milestone in this strategy. Our evolution from an IP provider to an SoC design partner delivers greater value to our customers, empowering them to focus valuable engineering resources on differentiating their silicon.”

The Cadence Janus NoC leverages Cadence’s legacy of trusted and time-proven Tensilica RTL generation tools. Customers can utilize Cadence’s extensive portfolio of software and hardware for simulation and emulation of their NoC and gain deep insights into its performance using Cadence’s System Performance Analysis tool (SPA). By enabling architectural exploration, this flow results in the best NoC design to meet product needs. The NoC leverages Cadence’s well-established leadership in IP and quality, backed by industry-leading customer satisfaction for technical support.

The Cadence Janus NoC mitigates the routing congestion and timing issues associated with today’s complex SoC interconnects, which often don’t become apparent until physical implementation. Addressing the most pressing needs today, Cadence’s first-generation NoC provides a platform for future innovations, such as support for industry-standard memory and I/O coherence protocols. Current features and benefits include:

  • Easy to use: Cadence’s powerful, state-of-the-art GUI enables easy NoC configuration ranging from small subsystems to full SoCs and future multi-chip systems.
  • Accelerated time to market: PPA-optimized RTL enables SoC designers to achieve their bandwidth and latency goals. Packetized messages enable higher utilization of wires, reducing wire count and timing closure challenges.
  • Lower risk: The NoC’s built-in power management, clock domain crossing and width matching reduce design complexity.
  • Quick turnaround: Cadence’s extensive simulation and emulation capabilities enable early architectural exploration, allowing quick validation of PPA results to ensure the configuration meets design requirements.
  • Scalable architecture: Customers can design a subsystem and reuse it in a full SoC context of the NoC, allowing future reuse in a multi-chip system.
  • Flexible: The NoC is compatible with any IP with an industry-standard interface, including AXI4 and AHB.

“We are pleased that Cadence is expanding its IP portfolio by investing in system-level solutions,” said Suk Lee, VP and GM, Ecosystem Technology Office at Intel Foundry. “As a NoC is vital for almost any subsystem in today’s SoCs, we support Cadence’s initiatives in developing their NoC and look forward to them continuing to expand their IP offering going forward.”

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A Q&A With GlobalFoundries’ Vikas Gupta: With Silicon Photonics, Data Centers Can Shoulder AI

AAC - Wed, 06/26/2024 - 02:00
In this exclusive interview, GlobalFoundries representative Vikas Gupta discussed the advantages of silicon photonics for developing efficient AI chips.

NXP Adds to AI Automotive Portfolio With Audio Processing DSP Chips

AAC - Tue, 06/25/2024 - 20:00
The chip family promises to deliver a significant upgrade to automotive infotainment systems.

Marktech launches 235nm and 255nm dual-chip UVC LEDs

Semiconductor today - Tue, 06/25/2024 - 18:23
Marktech Optoelectronics Inc of Latham, NY, USA, a designer and manufacturer of optoelectronics components and assemblies — including UV, visible, near-infrared (NIR) and short-wave infrared (SWIR) emitters, detectors and indium phosphide (InP) epiwafers — has launched its dual-chip UVC LEDs in 235nm and 255nm wavelengths. Available now, the high-power UVC LEDs are engineered to double the power output of traditional single-chip LEDs, meeting the need for more effective deep-UVC light sources for purification and instrumentation applications across various industries...

Power Tips #130: Migrating from a barrel jack to USB Type-C PD

EDN Network - Tue, 06/25/2024 - 17:46

Over the last few years, the USB Type-C® with Power Delivery (PD) standard has been adopted in a wide variety of electronics. This adoption has been driven by benefits such as a unified port (reducing e-waste), the convenience of a reversible connector, and high-power capability.

As Table 1 shows, the latest release of USB PD 3.1 extends the power capability of USB up to 240 W, more than doubling the 100 W of available power from the previous USB PD 3.0 specification. This allows a wide range of new applications to now be powered from USB. In order to reduce e-waste, the European Union and India have started passing legislation mandating USB Type-C for personal electronics in 2025, and it is expected that this trend will likely extend to other applications such as power tools, smart speakers, vacuum cleaners, e-bike chargers and networking. These trends and regulations are forcing manufacturers to seek out simple and inexpensive ways to convert the power connectors on their products from a barrel jack to a USB-C connector.

Table 1 USB power standards where the latest USB PD 3.1 release extends the power capability of USB up to 240 W. Source: Texas Instruments

In this Power Tip, we will discuss system power considerations and demonstrate how you can quickly and easily implement a USB-C connector and power management circuitry that negotiates the appropriate USB PD contract for the power requirements your design.

USB PD power flows

It is also worth noting that there are three types of power flow in the USB PD ecosystem: devices that can only sink power, devices that can only source power, or devices that allow bi-directional power flow (dual-role power.) In this article, we’ll focus on sink-only applications.

Before a sink device utilizing USB PD can accept power from a USB PD power source, some hand-shaking and negotiation must take place between the device being powered and the power source. This is because the voltage on the USB PD power bus can be variable from 5 V to 48 V, depending on the power capability of the power source. Obviously, you would not want to apply 48 V to a sink device that is only designed to operate from a 15 V input source. In a USB PD sink application, a dedicated device called a port controller is needed to perform this power contract negotiation and provide protections like over-current and over-voltage. Previously, adding a USB PD port controller configured with the proper functionality required in-depth knowledge of the USB certification and a large amount of firmware development effort. To simplify the power architecture and reduce design complexity, a preprogrammed USB PD controller allows the designer to configure the maximum and minimum voltage and current sink capability through a simple resistor-divider setting, as shown in Table 2. This removes the need for external electrically erasable programmable read-only memory (EEPROM), an MCU, or any type of firmware development.

Table 2 The ADCIN pin of a preprogrammed USB PD controller that allows designers to configure the max and min voltage as well as the current sink capability through a simple resistor divider setting. Source: Texas Instruments

Negotiating power contracts and matching system power requirements

Before converting your product to USB PD, it is important to understand the limitations and requirements of the USB PD ecosystem. On the source side of the cable, a USB PD power source will be providing power to your system, but the person using your product could connect absolutely any USB PD adapter or other power source. You need to consider what power contract is needed to provide full power to your system. In addition, consider how your system will behave if insufficient power is available from that adapter.

The available current through the USB Type-C cable is limited to 3 A for voltages below 20 V, and 5 A for voltages 20 V and above. Additionally, USB PD power sources are only required to generate the minimum voltage necessary to provide rated power at the maximum allowed cable current. For example, a 45 W adapter will typically provide a maximum output voltage of 15 V, since 45 W divided by 3 A is 15 V.

What if your system is designed to run from a 15 V source, but needs 50 W of power? In this case, you need to configure your port controller to accept a higher voltage contract (e.g., 20 V) to ensure you have enough power to run your system, and you need to ensure your system is designed to handle this slightly higher input voltage. This may require you to make slight modifications to your product beyond just adding the USB Type-C connector and port controller. Additionally, typically you still want your product to be functional when connected to a USB PD source with insufficient power capacity, but perhaps operate at reduced performance level.

Design example

Consider, a product that needs to charge a 4S-7S battery at 27 W that was previously powered through a 15 V barrel jack. In this example, a buck-or-boost converter was used, since the battery voltage could be higher or lower than the 15 V input, depending on the state of charge. Converting this design to a USB PD input only requires a simple stand-alone USB PD controller like the TPS25730 and buck-boost battery charger. Figure 1 shows the system architecture. You can see that only a few components were required to convert the barrel jack to a USB PD port. The simple resistors connected to the ADCIN1 through ADCIN4 pins set the power profile without the need for any firmware development. In this case, the product must still charge from a 5 V power source even though available power is reduced, so the TPS25730 is configured for a 20 V maximum voltage and 5 V minimum voltage, with the operating current set to 3 A.

Figure 1 The 27W USB PD sink-only charger reference design block diagram. Source: Texas Instruments

Input voltage dynamic power management

Besides supporting a USB PD source input, the design should also support legacy USB input sources, such as 5 V and 2 A. To avoid collapse of the input voltage when the input power is limited, the BQ25756E provides an input voltage dynamic power-management feature in the BQ25756E which will reduce the charge current if the input voltage drops to a value set by the parameter Vin_dpm. The Vin_dpm should be set slightly lower than the input voltage minus the voltage drop through the cable and power path so that it can maximize the battery charge current while not overloading the input source, or creating an instability on the input bus.

Figure 2 shows experimental results charging from a 5 V, 2 A source with a 1 meter USB cable (0.25 Ω resistance). When you set Vin_dpm to 4.75 V, you can see that the input charge current is limited and unstable (left side of Figure 2). When properly configured, with the Vin_dpm set to 4.35 V to account for the resistive drop, the input voltage is stable and the charge current is increased by 50%, which will significantly shorten charging times.

Figure 2 Input dynamic power management when charging from a 5 V, 2 A source with a 1 m USB cable. Source: Texas Instruments

Implementing USB PD

With a simplified USB PD controller and battery charger architecture, you don’t need to have in-depth knowledge of USB PD. Not only can you eliminate the need for an extra MCU and EEPROM (and exert no firmware effort), but you can use just a simple resistor divider to configure your voltage and current sink capability and quickly convert your barrel jack to a USB Type-C input. For complete details of the example design highlighted here, check out the 27W USB Power Delivery Sink-Only Charger Reference Design for 4- to 7-Cell Batteries.

Author bios

Max Wang has been a systems engineer for the Power Design Services team at Texas Instruments, where he is responsible for power solution and reference designs for industrial and personal electronics applications. He recently created a series of high-efficiency compact AC/DC and DC/DC USB Type-C® PD charger solutions. Before joining TI, he worked at Delta, Power Integrations, and Infineon. He has a master’s degree in electrical engineering from Zhejiang University in Hangzhou, China.

 

 

Brian King is a systems manager and senior member technical staff at Texas Instruments. He has over 28 years of experience in power supply design, specializing in isolated AC-DC and DC-DC applications. Brian has worked directly with customers to support over 1300 business opportunities and has designed over 750 unique power supplies using a broad range of TI power supply controllers with a focus on maximizing efficiency and minimizing solution size and cost. He has published over 45 articles related to power supply design, and since 2016 is the lead organizer and content curator for the Texas Instruments Power Supply Design Seminar (PSDS) series, which provides training to thousands of power engineers worldwide on a regular basis. Brian received an MSEE and a BSEE from the University of Arkansas.

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