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This article demonstrates the operation of an LTspice shift register and discusses details of its schematic and timing relationships.

Photonic chips industry accelerator PhotonDelta of Eindhoven, The Netherlands (which connects and collaborates with an ecosystem of photonic chip technology organizations worldwide), has opened a new office in North America, with the aim of growing the photonic chip industry by promoting collaboration between European and North American organizations...

It has been an exciting year for mobile technology with the advent of AI Smartphones. Each year, like clockwork, I find myself eagerly lining up for the latest smartphone launch, driven by an insatiable curiosity and a bit of a tech addiction. My friends might jest that I switch phones more often than my single malt preferences, but through this annual ritual, I gain a front-row seat to the rapid evolution of technology. Each unboxing becomes a discovery of what’s newly possible at the intersection of hardware and software, particularly as smartphones grow not just smarter but seemingly wiser. The innovation of integrating generative AI in smartphones raises the customer experience bar exponentially.

This fascination isn’t merely about indulging in the latest bells and whistles; it’s about experiencing firsthand how intelligent operating systems are revolutionizing our interactions with mobile devices. As generative AI migrates from vast data centers to the palms of our hands, it transforms smartphones into central hubs of personalized technology and AI-driven companions, reshaping the foundations of mobile user interaction.

At the heart of this revolution is Micron Technology. Our advanced memory and storage products support the immense data demands of generative AI, turning what once seemed like a futuristic vision into today’s reality. These technological advancements are crucial as smartphones begin to transition from passive tools to active personal companions, deeply integrated into the fabric of our daily lives. They offer insightful recommendations and enhance our experiences in ways we are only beginning to imagine.

To truly appreciate the impact of these technologies, one must understand the intricate play between large language models (LLMs) like Llama 2, Google Gemini, and ChatGPT, as well as the advanced hardware that supports them. These AI models, which thrive on billions of parameters, demand unprecedented levels of memory capacity and speed—requirements that Micron’s innovative products are designed to meet. Integrating high-capacity, efficient memory systems is not just an improvement; it’s necessary to support the sophisticated AI functions that modern users will come to expect from their devices.

As we stand on the brink of this new era, our relationship with our devices is set to change profoundly. Smartphones will transition from passive tools to active personal companions, deeply integrated into the fabric of our daily lives, making insightful recommendations and enhancing our experiences in ways we are only beginning to imagine. This blog explores how generative AI is driving this monumental shift, redefining the possibilities of smartphone technology and ensuring that users can enjoy a seamless, intuitive, and highly personalized digital experience.

The generative AI advantage: Unlocking the ultimate smartphone companion experience

Generative AI is revolutionizing the capabilities of smartphones by introducing features that were once the domain of science fiction. At its core, generative AI involves using algorithms and models to generate text, images, and even predictions based on extensive data sets on which they have been trained. This transformative technology is making smartphones, not just tools for consumption but instruments of creation and personal assistance.

One of the key features enabled by generative AI is the ability to generate real-time content directly related to user inputs. For example, through AI-powered apps, users can request the generation of digital artwork or manipulate photos and videos in sophisticated ways that go far beyond the current filters and editing tools. Another significant capability is real-time language translation, which is advancing beyond simple text translation to include voice and even real-time video call translations. This allows for a seamless communication experience with almost no language barrier, effectively shrinking the global divide in personal and professional interactions.

Moreover, generative AI enhances personalized recommendations by analyzing user behaviour, preferences, and previous interactions. This data-driven approach allows smartphones to anticipate needs and offer suggestions for everything from daily tasks to complex decision-making processes. It can also guide users through interactive educational content, adapting to their learning pace and style, thus personalizing the educational experience more effectively than ever before.

These features, powered by generative AI, require advanced computational power and significant memory and storage capabilities. The processing occurs on the device itself to ensure responsiveness and data privacy. As these technologies continue to evolve, they promise to enhance how users interact with their devices further, making each smartphone a truly personalized digital companion that learns and grows with its user.

Smartphones that care: How AI is humanizing the mobile experience

The future of AI-enabled smartphones promises a landscape where the line between digital and physical realities blurs, ushering in a new era of interactive and immersive experiences that are currently difficult to imagine. As generative AI continues to evolve, the potential for creating features that transform everyday activities and expand our capabilities is immense.

One of the most exciting prospects is developing extended reality (XR) and spatial computing which is integrated seamlessly with AI. Future smartphones could leverage XR to overlay digital information onto the physical world in real time. Imagine pointing your smartphone at a restaurant and seeing menu recommendations tailored to your taste and dietary preferences pop up in your vision or looking at a piece of furniture and seeing how it would look in your home, configured to your space and color scheme instantly.

Health monitoring is another area ripe for transformation. Future AI smartphones could become proactive health advisors, tracking physical activity and health metrics and predicting potential health issues before they arise. These devices could use advanced sensors and AI-driven analytics to monitor changes in voice tone, breathing patterns, and even eye movements to provide early warnings about health risks such as heart disease or diabetic changes, potentially coordinating directly with medical professionals to provide timely interventions.

Moreover, integrating AI could redefine mobile security, transforming smartphones into highly secure devices that use biometric data like facial recognition, retinal scans, and even behavioural patterns to ensure that access to the device and its applications is intensely personal and completely secure. This could eliminate the need for passwords or traditional security measures, which are vulnerable to breaches.

The concept of an AI companion will likely mature into a fully interactive assistant capable of sophisticated conversation and decision-making assistance. This companion could manage schedules, suggest content, handle mundane tasks, and even offer psychological support, learning continuously from interactions to become more effective and personalized. Furthermore, as generative AI capabilities grow, so will the ability to create and simulate complex virtual environments directly from the device, allowing users to interact with virtual spaces for entertainment, education, or social interaction in unprecedented ways.

Now what does it mean to smartphones’ memory and storage capacities? And what does a phone need to take full advantage of AI applications? As generative AI grows, it becomes even more of a primary innovation driver in the mobile ecosystem. And to support flagships phone’s advanced sensors, cameras, and form factors, high capacity and bandwidth memory and storage is critical. Data is collected and stored on the handset memory and storage, calculated, and processed on the edge (not in the cloud) and translated to valuable and predictive insights.

The future of smartphones equipped with AI technologies offers enhancements of current features and a revolution in how we perceive and interact with our environment. This future is not only about technological advancements but about significantly enhancing human capabilities and experiences, making life more convenient, connected, and healthy. These developments, while complex, require the continued advancement of AI technology paired with significant improvements in hardware, like those provided by Micron, to make these unimagined features a reality.

Memory matters: How Micron’s solutions are unlocking the full potential of AI smartphones and super companions

Micron is at the forefront of defining the future capabilities of AI smartphones, leveraging its leading-edge UFS 4.0 and LPDDR5X DRAM technologies. These innovations are vital for meeting the increasingly complex demands of on-device AI applications, pushing the boundaries of what smartphones can achieve.

The UFS 4.0 technology introduced by Micron sets new standards for storage performance, essential for the fast processing speeds required by AI-driven applications. It achieves a remarkable 4300 megabytes per second (MBps) in sequential read and 4000 MBps in sequential write speeds, doubling the performance of the previous UFS 3.1 standards. This significant increase in data throughput ensures that AI applications can access and process large datasets much faster, reducing latency and enhancing overall device responsiveness​​.

Additionally, Micron’s UFS 4.0 features a compact design with a footprint of just 9×13 millimeters, supporting the development of slimmer and more aesthetically pleasing smartphone designs without compromising performance. The storage solution also includes innovative features like the One-button Refresh, which helps maintain long-term device performance by automating data defragmentation, ensuring that the storage performance remains like-new even after extended use​​.

On the memory side, Micron’s LPDDR5X DRAM is engineered to meet the requirements of advanced AI processing by delivering top speeds of up to 9600 megabits per second (Mbps), which is crucial for handling AI’s extensive computational demands. This speed enhancement, combined with the high-density packaging that allows for increased memory capacity within the same form factor, is critical for AI applications that require rapid access to large volumes of data. ​ It also features 13% Gain with faster Peak Bandwidth and up to 27% power reduction on day of use.

Micron’s advancements enhance smartphones’ raw computational and storage capabilities and enable new AI features by providing the necessary infrastructure to support real-time AI processing on the edge. This strategic focus on developing high-performance and efficient memory and storage solutions firmly positions Micron as a key enabler in the rapidly evolving landscape of AI mobile technology, facilitating the emergence of smartphones that can perform complex AI tasks directly on the device without relying on cloud processing.

The ethical compass: Navigating the moral landscape of AI smartphones

As AI smartphones continue to revolutionize our lives, it’s crucial to acknowledge the ethical considerations that come with these powerful devices. Like a moral compass, we must navigate the complexities of AI technology to ensure it aligns with our values and principles. Privacy and data security are paramount concerns. How will AI smartphones collect, store, and protect our personal information? Transparency and accountability are essential to prevent data breaches and cyber-attacks. Users must be informed about data usage and sharing practices, and measures must be taken to prevent biases and discrimination in AI decision-making. Transparency and explainability are vital in AI-driven processes. Users deserve to understand how AI arrives at its conclusions and make informed decisions. Autonomous decision-making raises questions about free will and moral agency, and AI smartphones must balance user autonomy and AI-driven actions.

The environmental impact of AI smartphones cannot be ignored. Sustainable manufacturing, reduced electronic waste, and energy efficiency are crucial to minimize their ecological footprint. Finally, human-AI collaboration must prioritize human well-being and dignity, enhancing our capabilities without replacing them. By acknowledging these ethical considerations, we can harness the potential of AI smartphones while upholding our values and principles. Like a compass guiding us through uncharted territory, ethical awareness will ensure AI technology serves humanity, not the other way around.

The future in focus: AI smartphones and the dawn of a new era

Imagine this: It’s a crisp Wednesday morning in the not-too-distant future. Your day begins not with a jarring alarm but with a gentle wake-up nudge from your AI-enhanced smartphone, which has analyzed your sleep patterns and knows the exact moment to wake you. As you stir, your phone has already started your coffee maker, selected a nutritious breakfast based on your health goals for the week, and displayed your optimized route to work, avoiding a traffic jam it predicted from historical data and real-time sensors.

While you eat, your smartphone reviews your calendar prioritizes tasks based on urgency and personal productivity patterns and seamlessly integrates your work commitments with personal ones. It reminds you of your daughter’s recital in the evening and schedules a reminder to leave work early. It even suggests a perfect gift for her performance tonight, which you can pick up on your route home—all curated from understanding your past purchases and her current interests.

This scenario isn’t just a futuristic dream; thanks to companies like Micron, it’s on the verge of becoming reality. By advancing AI capabilities through memory and storage solutions innovations like UFS 4.0 and LPDDR5X DRAM, Micron is turning smartphones into personal assistants that manage our digital tasks and enhance our human experiences.

Micron’s vision to “enrich life for all” is deeply embedded in these advancements. With AI on the edge, smartphones are evolving into devices that think, react, predict, and adapt to our needs in more personalized ways. This new generation of smartphones promises to enhance our productivity and leisure, making each interaction more meaningful by staying seamlessly connected to our loved ones and passions while navigating the complexities of our daily lives.

As we embrace these changes, let’s ponder the profound impact of having a device that does more than execute commands—it collaborates, advises, and supports our every decision. With Micron’s commitment to pushing the boundaries of what’s possible, the future is not just about technological advancement but about creating deeper, more meaningful connections with the world around us. How will you harness this power to reshape your day-to-day life? The possibilities are as boundless as your imagination.

The post AI Smartphones: The Era of the Super Companion in Your Pocket appeared first on ELE Times.

Researchers at Penn State have developed a new 3D-printed material designed to advance soft robotics, skin-integrated electronics, and biomedical devices. This material is soft, stretchable, and self-assembled, overcoming many limitations of previous fabrication methods, such as lower conductivity and device failure. According to Tao Zhou, an assistant professor at Penn State, the challenge of developing highly conductive, stretchable conductors has persisted for nearly a decade. While liquid metal-based conductors offered a solution, they required secondary activation methods—like stretching or laser activation—which complicated fabrication and risked device failure.

Zhou explained that their method removes the necessity for secondary activation to attain conductivity. The innovative approach combines liquid metal, a conductive polymer mixture called PEDOT: PSS, and hydrophilic polyurethane. When printed and heated, the liquid metal particles in the material’s bottom layer self-assemble into a conductive pathway, while the top layer oxidizes in an oxygen-rich environment, forming an insulated surface. This structure ensures efficient data transmission to sensors—such as those used for muscle activity recording and strain sensing—while preventing signal leakage that could compromise data accuracy.

“This materials innovation allows for self-assembly that results in high conductivity without secondary activation,” Zhou added. The ability to 3D print this material also simplifies the fabrication of wearable devices. The research team is exploring various potential applications, focusing on assistive technology for individuals with disabilities.

The research, supported by the National Taipei University of Technology-Penn State Collaborative Seed Grant Program, included contributions from doctoral students Salahuddin Ahmed, Marzia Momin, Jiashu Ren, and Hyunjin Lee.

The post Breakthrough 3D-Printed Material Revolutionizes Soft Robotics and Biomedical Devices appeared first on ELE Times.

Courtesy: Microchip

Silicon Carbide (SiC) Schottky Barrier Diodes (SBDs) increase efficiency and ruggedness to help create faster and more reliable applications.

Better Efficiency and Reliability Through Silicon Carbide

Silicon Carbide (SiC) Schottky Barrier Diodes (SBDs) increase efficiency and create reliable high-voltage applications. Our rich history and experience allow us to deliver highly reliable SBDs that are designed with high repetitive Unclamped Inductive Switching (UIS) capability at a rated current, which exhibits no degradation. Our mSiC diodes are designed with balanced surge current, forward voltage, thermal resistance and thermal capacitance ratings at low reverse current for lower switching loss to create more efficient power systems.

Because of differences in material properties between SiC and silicon, silicon Schottky diodes are limited to a lower voltage range with higher on-state resistance (RDS(on)) and leakage current. However, SiC Schottky diodes can obtain a much higher breakdown voltage while maintaining low on-resistance and low switching losses, improving ruggedness over traditional silicon Schottky diodes. Our portfolio of mSiC products covers 700V, 1200V, 1700V and 3300V (3.3 kV) SiC Schottky diodes.

In summary, SiC offers the following advantages over silicon:

• Better reverse current capability
• Higher temperature stability
• Higher radiation resistance

Breakdown Voltage

The breakdown voltage of a diode is the voltage at which the diode breaks down and starts conducting current. The breakdown voltage determines the maximum voltage that the diode can withstand before it fails. SiC SBDs exhibit higher breakdown voltages than silicon diodes because of the SiC material’s higher bandgap. This higher breakdown voltage rating allows SiC diodes to withstand higher voltages without damage.

The higher breakdown voltage of SiC diodes is important for several applications including power converters, inverters and motor drives. In these applications, the diodes are often exposed to high voltages. The higher breakdown voltage of SiC diodes allows them to withstand these high voltages without damage, which can lead to improved reliability and performance.

Forward Voltage Drop

The forward voltage drop of a diode is the voltage drop that occurs when the diode is conducting current. This parameter determines the efficiency of the diode. SiC diodes have a lower forward voltage drop than silicon diodes. The higher bandgap means it takes less energy for an electron to move through the material. This lower forward voltage drop allows SiC diodes to be more efficient than silicon.

The lower forward voltage drop is important for several applications including power converters, inverters and motor drives. In these applications, the diodes are often used to convert power from one form to another. The lower forward voltage drop of SiC diodes allows them to be more efficient in these applications, which can lead to reduced costs and improved performance.

Reverse Recovery

Reverse recovery is a phenomenon that occurs when a diode is switched from conducting current to non-conducting current. During reverse recovery, a small amount of current flows in the reverse direction. This current can cause a voltage drop across the diode, which can damage the diode if it is not properly managed.

SiC diodes have a much shorter reverse recovery time, allowing them to switch from conducting current to non-conducting current more quickly, which can reduce the risk of damage. Reverse recovery is an important consideration for any application that uses diodes.

Reverse Current

The reverse current of a diode is the current that flows in the reverse direction when the diode is biased in the reverse direction. This current is a major factor that limits the performance of SiC diodes in high-voltage applications. The reverse current of SiC diodes is typically much higher than that of silicon diodes because the SiC material has a higher bandgap, which causes it to take more energy to break an electron free from its atom. This higher bandgap also means that there are fewer free electrons available to carry current in the reverse direction.

High reverse current can cause several problems in high-voltage applications, causing the diode to overheat and fail. It can also cause the diode to emit noise and interference. There are a few ways to reduce the reverse current of SiC diodes. One way is to use a diode with a higher breakdown voltage. Another way is to use a diode with a lower doping level. However, these techniques can reduce the performance of the diode in other ways.

High Temperature and High Current Stability

High temperature and high current stability are crucial because SiC diodes are often used in a variety of applications that require high currents and temperatures of up to 150°C. The stability of SiC diodes is important for their use in applications with more demanding conditions.

Stability at high temperatures and currents is due to the higher bandgap, which makes SiC more resistant to damage from heat and high current conditions. SiC diodes have a lower concentration of impurities than silicon diodes, making SiC diodes less likely to experience recombination, the process by which an electron and a hole combine to form an atom. Recombination can cause the diode to lose its ability to conduct current, leading to failure.

These attributes make SiC diodes well suited for applications that require high temperatures and currents, such as power converters and inverters, leading to improved reliability and performance in the end equipment.

Start Designing with SiC

Getting started with designing with Silicon Carbide (SiC) involves understanding its benefits and applications. We offer a range of Silicon Carbide (SiC) power products which are the key to faster, more efficient energy solutions.

The post mSiC Diode Technology: Ruggedness and Reliability appeared first on ELE Times.

Courtesy: Lam Research

Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices, and can lead to poor device performance or even device failure [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this study, we demonstrate how virtual fabrication can provide guidance on how to perform deposition/etch cycling in order to reduce LER.

A typical line and via array pattern with a pitch of 40 nm was established as a test structure in the virtual fabrication software. Pattern critical dimensions (CD) and LER amplitude and correlation length (measures of line edge roughness) were then explored under different experimental conditions.

Figure 1:The virtual process flow of a deposition/etch cycle process used to improve LER. Figure 1 (a-c) 3D view,(d-f) top view of the incoming structure after deposition and etch cycling.

A deposition/etch cycling process was applied in a virtual model to improve the line edge roughness (LER) and critical dimension uniformity (CDU) of the pattern (Figure 1). Virtual metrology was used to measure LER standard deviation (LERSTD), LER correlation length (C) and Via CD range (VCDR) to evaluate the impact of the selected process changes on LER and CDU improvement.

We ran 1,500 virtual experiments using the incoming pattern CD, LER amplitude (A), LER correlation length (C), etch/deposition amount (THK), and number of deposition/etch cycles (NC) as experimental variables. Part of the results of our experiment are shown in Figure 2.

Figure 2 – improving line edge roughness

Figure 2 shows the trend in the Via CD ranges (VCDR), LER standard deviation (LERSTD), and LER correlation length (C) values with respect to the number of deposition / etch cycles (bottom axis) at different LER A and LER C conditions (top and right axis). Our goal is to minimize VCDR, LERSTD and CL values at the lowest number of deposition / etch cycles. We can draw 3 conclusions from Figure 2.

1) Most of the improvement to LER/VCDR occurs in the first deposition/etch cycle.

2) An increase in the deposition amount (THK, shown in color on Figure 2) has a greater impact on the LER/VCDR improvement than an increase in the number of deposition/etch cycles.

3) The LER correlation length (C) becomes larger after a deposition/etch cycle, but the LER/VCDR improvement is not obvious when the LER correlation length (C) increases.

Figure 3 – improving line edge roughness

As we mentioned earlier, most of the LER improvement happened in the first deposition/etch cycle, with the remaining deposition/etch cycles producing a much smaller improvement. Contour plots displaying the LER/VCDR improvement on the 1st cycle was fitted and illustrated in Figure 3. From Figure 3, we can draw 2 conclusions:

1). Although less improvement was noticed with a larger incoming LER correlation length (C), improvement still occurred at the via patterns if a thicker film was used during the deposition portion of the cycle when there was a larger LER correlation length (LER C) and lower LER amplitude (LER A).

2). LER/VCDR can be improved using a relatively thicker deposition film at larger incoming LER C conditions.

In this study, a deposition/etch cycling process was simulated to improve LER and CDU performance at advanced nodes by virtual fabrication. The results indicate that most of the LER/VCDR improvement seen during deposition/etch cycling processes occurred during the first deposition/etch cycle. The deposition/etch cycling process is very effective in reducing high frequency noise (when there is a smaller LER correlation length). LER improvements are larger at the via patterns than at the line patterns when a thicker film is deposited, exhibiting as larger LER correlation length values and lower LER amplitude. These results provide quantitative guidance on the optimal selection of deposition/etch amounts and the number of cycles needed, to both reduce LER and lower defects and variability in the production of advanced semiconductor devices.

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Change may be a constant in any industry, but the grid and energy industries are experiencing a revolutionary change they have never seen. The grid and energy industries are in the midst of a significant transformation, referred to as grid modernization, driven by the integration of cutting-edge technologies like telecommunications, distributed energy resources, battery storage, solar power, and the ever-present concern of cybersecurity. This fundamental shift presents both challenges and opportunities that will reshape how the world generates, distributes, and consumes electricity.

History of grid modernization

The traditional process that the grid and energy industries have utilized goes back to the late 19th century with the establishment of the first industrial power plants. In the early 20th century, the grid rapidly expanded, but with a focus on centralized power generation using fossil fuels and long-distance transmission lines. The power sources for energy expanded throughout the 20th century to include nuclear, hydroelectric, and some renewables, but the grid and energy industries continued to be separate, isolated entities until the 21st century.

The push for grid modernization came as concerns rose about aging infrastructure, increasing blackouts, and rising environmental impact. In 2003, the United States Department of Energy created dedicated offices to address grid reliability and security. The past two decades have seen a dramatic rise of renewable energy sources like wind and solar and pushes for grid upgrades to handle fluctuating power generation. Grid modernization strives to tackle these problems to ensure a better system moving forward.

Key aspects of grid modernization

Grid modernization is focused on transforming the current electricity delivery system to meet the demands of the 21st century and beyond. Key aspects of this transformation include:

• Integration of renewables: A core focus is on smoothly bringing renewable energy sources like solar and wind into the power generation mix. This often requires upgrades to handle the variable nature of these power sources.
• Smart grid technologies: The Smart Grid concept involves using digital technology to monitor, control, and optimize the flow of electricity. This includes smart meters for consumers and advanced grid management systems for utilities.
• Infrastructure improvements: Aging grid systems need upgrades to improve reliability and efficiency. This can involve replacing outdated equipment, strengthening transmission lines, and investing in new technologies for power distribution.
• Consumer management: Modernization aims to give consumers more control over their energy use. This might involve tools for monitoring consumption, participating in demand-response programs, and even generating their own power.
• Resilience and security: The grid needs to be more resistant to outages caused by weather events, cyberattacks, and other threats. This involves building redundancy and implementing advanced security measures.

Overall, grid modernization is a complex undertaking with far-reaching impacts. The goal of this process is to pave the way for a more reliable, efficient, secure, and environmentally sound electricity system for the future.

Challenges of grid modernization

Grid modernization is a necessary step towards a more sustainable and efficient energy future, but it is not without its hurdles to overcome. Some of the challenges that come with this transformation include:

• Cost: Upgrading the power grid requires significant investment in new technologies, infrastructure, and cybersecurity measures. Utilities need to find ways to finance these improvements while keeping electricity affordable for consumers.
• Variability of renewables: Renewable energy sources like solar and wind are variable in their output. The grid needs to be able to handle these fluctuations without compromising reliability.
• Interoperability: Modernization often involves integrating equipment from new technology sources. Ensuring seamless communication and utilization between new and legacy systems requires common standards and protocols, which are still being developed.
• Cybersecurity: A more digital grid with new data sources creates increasing vulnerabilities to cyberattacks. Robust security measures are essential to protect critical infrastructure.
• Regulation: The regulatory framework needs to adapt to support grid modernization efforts and incentivize investment and adoption of new technologies

Opportunities with grid modernization

While grid modernization presents a complex challenge, the potential benefits are significant. Overcoming the hurdles and capitalizing on these opportunities creates numerous advantages, including:

• Clean energy integration: A modernized grid can efficiently integrate renewable energy sources, reducing global reliance on fossil fuels and combating climate change.
• Consumer empowerment: Consumers can gain more control over their energy use through smart meters and demand-response programs, leading to increased participation in the energy market, potentially even selling excess power back to the grid.
• Improved grid reliability and efficiency: Modernization can lead to fewer power outages, reduced energy losses, and a more efficient overall system.
• Economic growth: Investment in a modern grid will drive economic growth and the creation of new jobs in areas like renewable energy technologies, grid construction, and cybersecurity solutions.
• Innovation: Modernization opens doors for innovation in areas like energy storage, distributed generation, data analytics, cybersecurity, and telecommunications.

The Road Ahead

The transformation of the grid and energy industry is complex and ongoing. Collaboration between utilities, technology companies, policymakers, and consumers are essential to overcome the challenges and seize the opportunities presented by grid modernization. By investing in infrastructure upgrades, developing innovative technologies, and prioritizing cybersecurity, the world can create a more resilient, efficient, and sustainable energy future.

Key to this transition will be the integration of five key technology areas: telecommunications, distributed energy resources, battery storage, solar power, and cybersecurity.

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PIC64GX MPU is the first of several product lines planned for Microchip’s PIC64 portfolio

Real-time, compute intensive applications such as smart embedded vision and Machine Learning (ML) are pushing the boundaries of embedded processing requirements, demanding more power-efficiency, hardware-level security and high reliability at the edge. With the launch of its PIC64 portfolio, Microchip Technology is expanding its computing range to meet the rising demands of today’s embedded designs. Making Microchip a single-vendor solution provider for MPUs, the PIC64 family will be designed to support a broad range of markets that require both real-time and application class processing. PIC64GX MPUs, the first of the new product line to be released, enable intelligent edge designs for the industrial, automotive, communications, IoT, aerospace and defense segments.

“Microchip is a leader in 8- 16- and 32-bit embedded solutions and, as the market evolves, so must our product lines. The addition of our 64-bit MPU portfolio allows us to offer low-, mid- and high-range compute processing solutions,” said Ganesh Moorthy, CEO and President of Microchip Technology. “The PIC64GX MPU is the first of several 64-bit MPUs designed to support the intelligent edge and address a broad range of performance requirements across all market segments.”

The intelligent edge often requires 64-bit heterogenous compute solutions with asymmetric processing to run Linux, real-time operating systems and bare metal in a single processor cluster with secure boot capabilities. Microchip’s PIC64GX family manages mid-range intelligent edge compute requirements using a 64-bit RISC-V quad-core processor with Asymmetric Multiprocessing (AMP) and deterministic latencies. The PIC64GX MPU is the first RISC-V multi-core solution that is AMP capable for mixed-criticality systems. It is designed with a quad-core, Linux-capable Central Processing Unit (CPU) cluster, fifth microcontroller class monitor and 2 MB flexible L2 Cache running at 625 MHz.

The PIC64GX family boasts pin-compatibility with Microchip’s PolarFire SoC FPGA devices, offering a large amount of flexibility in the development of embedded solutions. Additionally, the 64-bit portfolio will leverage Microchip’s easy-to-use ecosystem of tools and supporting software, including a host of powerful processes to help configure, develop, debug and qualify embedded designs.

The PIC64 High-Performance Spaceflight Computing (PIC64-HPSC) family is also being launched as part of Microchip’s first wave of 64-bit offerings. The space-grade, 64-bit multi-core RISC-V MPUs are designed to increase compute performance by more than 100 times while delivering unprecedented radiation and fault tolerance for aerospace and defense applications. NASA’s Jet Propulsion Laboratory (NASA-JPL) announced in August 2022 that it had selected Microchip to develop an HPSC processor as part of its ongoing commercial partnership efforts. The PIC64-HPSC family represents a new era of autonomous space computing for NASA-JPL and the broader defense and commercial aerospace industry.

With the introduction of its PIC64 portfolio, Microchip has become the only embedded solutions provider actively developing a full spectrum of 8-, 16-, 32- and 64-bit microcontrollers (MCUs) and microprocessors (MPUs). Future PIC64 families will include devices based on RISC-V or Arm architectures and embedded designers will be able to take advantage of Microchip’s end-to-end solutions—from silicon to embedded ecosystems—for faster design, debug and verification and a reduced time to market. To learn more, visit the Microchip 64-bit web page.

Development Tools

The PIC64GX family is supported by the PIC64GX Curiosity Evaluation Kit and will feature integration with Microchip’s MPLAB Extensions for VS Code. The PIC64 MPUs are also supported by Linux4Microchip resources and Linux distributors such as Canonical Ubuntu OS, the Yocto Project and Buildroot with support for Zephyr RTOS and associated software stacks.

Pricing and Availability

The PIC64GX Curiosity Kit is now available for designers to get started with evaluation— for additional information and to purchase, contact a Microchip sales representative, authorized worldwide distributor or visit Microchip’s Purchasing and Client Services website, www.microchipdirect.com.

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Courtesy: Infineon

Do you wonder how a traditional SIM works? Today, through this blog, I will talk about the working process of SIM as well as eSIM Remote SIM Provisioning (RSP). So, let’s jump into the techy details.

Working of physical SIM cards

Let’s first take a look at the figure 1 below:

Figure 1: Cases explaining the working of physical SIM cards

Did you understand anything from this given figure? Well, I’ll explain it now.

Traditional SIM cards were owned and issued by a particular network operator. The Figure 1.1 above showcases that an end user signs up a contract with their selected network operator, they pay the amount for the service and gets the physical SIM card (Case (a)).

Later, the same end user signs-up a contract with a different network operator, pays the service charges and gets the new physical SIM card (Case (b)).

Here, we see that if the end user has to use (a) network or (b) network, he needs to swap the SIM cards on their own.

eSIM remote SIM provisioning

After reading about how physical SIM works, you must be wondering how an eSIM differs from traditional SIMs?

Take a look at the image below:

Figure 2: Remote SIM Provisioning

For remote SIM provisioning, no physical SIM card is required, but an embedded SIM in your handset/device (also called eUICC) – a single eSIM can accommodate and securely store multiple profiles in a single device and each profile comprises operators as well as subscriber’s data.

Let’s see what this figure 2 explains. ­­

At first, in step (a) the end user signs-up a contract with their preferred network operator, pays the required charges, and instead of getting a physical SIM, he receives instructions to connect to operator’s Remote SIM Provisioning system (RSP) [e.g., QR code]. This QR code contains the address of RSP system (SM-DP+ (Subscription Manager Data Preparation) server within the GSMA specifications), which allows the end user to download and install a SIM profile (as shown in step (b)). Once the profile is active, the user can connect to the network successfully (as shown in step (c)).

Important note: In Figure 2, the end user can repeat the process to install more profiles on a single device as shown below in Figure 3. This allows users to switch between profiles 1 and 2 as per their needs.

Figure 3: Multiple Installed Profiles on eSIM

Some important terms:

Profile: A profile comprises of the operator data related to a subscription. It includes data like – operator’s credentials and provided third-party applications.

eUICC: Embedded Universal Integrated Circuit Card (eUICC) is a secure element in the eSIM solution which can accommodate multiple profiles.

Profiles are always remotely downloaded over-the-air into a eUICC. Although the eUICC is an integral part of the device, the profile remains the property of the operator as it contains items “owned” by the operator (International Mobile Subscriber Identity (ISMI), Integrated Circuit Card ID (ICCID), security algorithms, etc.) and is supplied under licence.

Hence, the eUICC acts as a secure element to store the eSIM Profiles in the device.

We now know how traditional SIM cards VS embedded SIMs (eSIMs) functions differently. In the next blog, I’ll discuss about GSMA M2M solution – The first RSP solution developed by GSM Association (GSMA) for Machine to Machine (M2M) connectivity. 

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Qromis Inc of Santa Clara, CA, USA (founded in 2015) has received the Frost & Sullivan 2024 Global Enabling Technology Leadership Award. Frost & Sullivan presents this award each year to a company that develops a pioneering technology that enhances current products and enables new product and application development...

A look at the simplest FM demodulation technique. It doesn’t give the lowest possible output distortion, it doesn’t reject amplitude distortion effects, but it is simple and can be used at virtually no cost.

Demodulation of frequency modulation (FM) signals can be done in many ways. There are FM discriminators, ratio detectors, quadrature detectors, phase lock loop designs, and even methods of getting down to first principles as shown on here.

However, one more method we can add to the toolkit is slope detection which is perhaps the simplest approach of them all.

Imagine a receiver of some sort which has some sort of bandpass characteristic. Typically, this would be a superheterodyne receiver whose bandpass properties are achieved in the intermediate frequency (IF) amplifier stage(s). We can tune our receiver so that the center frequency of the FM signal appears on one slope of the receiver’s bandpass characteristic meaning off to the side of the characteristic’s peak rather than at that peak itself (Figure 1).

Figure 1 Slope detection method where a bandpass slope below the resonant peak is used to create a slope-induced amplitude modulation where a simple envelope detector can be used to recover the modulation signal.

The figure above shows use of the bandpass slope below the resonant peak, but the slope above the resonant peak could be used just as well.

Whatever frequency deviation the input FM signal may have will result in an output signal in which an amplitude modulation property will have been imparted. A simple envelope detector can then be used to recover the modulation signal.

There will of course be some distortion because the bandpass scale factor versus frequency is not linear, but if that distortion is deemed tolerable, this very simple demodulation technique can work.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Build your own superheterodyne receiver
• A Quadrature Demodulator Tutorial
• Modulation basics, part 1: Amplitude and frequency modulation
• How to design a digital FM radio
• Understand Radio Architectures, Part 1
• Measuring pulsed RF signals with an oscilloscope

The post Slope detection for FM demodulation appeared first on EDN.

congatec – a leading provider of embedded and edge computing technology – presents new high-performance computer-on-modules (COMs) with i.MX 95 processors from NXP, thereby expanding its extensive module portfolio with low-power NXP i.MX Arm processors. In doing so, congatec underlines its strong partnership with NXP. Customers benefit from straightforward scalability and reliable upgrade paths for existing and new energy-efficient edge AI applications with high security requirements.

In these applications the new modules offer the advantages of up to three times the GFLOPS computing performance compared to the previous generation with i.MX8 M Plus processors. The new neural processing unit from NXP called ‘eIQ Neutron’ doubles the inference performance for AI accelerated machine vision. In addition, the hardware-integrated EdgeLock® secure enclave simplifies the implementation of in-house cyber security measures.

The new conga-SMX95 SMARC modules are designed for an industrial temperature range of -40°C to +85°C, are robust in mechanical terms and optimised for cost- and energy-efficient applications. The integrated high-performance eIQ Neutron NPU makes it possible for AI accelerated workloads to be performed even closer to the local device level. Specific applications for the new SMARC modules can be found in AI accelerated low-power applications in sectors such as industrial production, machine vision and visual inspection, rugged HMIs, 3D printers, robotics controllers in AMR and AGV, as well as medical imaging and patient monitoring systems. Other target applications include passenger seat back entertainment in buses and aircraft, along with fleet management in transportation, and construction and farming applications.

The feature set in detail

The new conga-SMX95 SMARC 2.1 modules are based on the next generation of the NXP i.MX 95 application processors with 4-6 Arm Cortex-A55 cores. NXP is now using the new Arm Mali 3D graphics unit for the first time, which delivers up to three times the GPU performance compared to predecessors based on i. MX8 M Plus. Also new is the image signal processor (ISP) for hardware accelerated image processing. Particularly noteworthy is the NXP eIQ Neutron NPU for hardware accelerated AI inference and machine learning (ML) on-the-edge in the new SMARC modules. The corresponding eIQ® software development environment from NXP offers OEMs a high-performance development environment which simplifies the implementation of in-house ML applications.

In addition, the new SMARC modules integrate a real-time domain for real-time controllers. The conga-SMX95 SMARC modules offer 2x Gbit Ethernet with TSN for synchronised and deterministic network data transmission, LPDDR5 (with inline ECC) for data security. For display connectivity the new modules offer DisplayPort as the standard interface and the still widely used LVDS display interface. For direct camera connectivity the modules have 2x MIPI-CSI.

congatec also offers an extensive hardware and software ecosystem as well as comprehensive design-in-services for simplified and accelerated application development. These include, among other things, evaluation- and production-ready application carrier boards and custom-tailored cooling solutions. In terms of services, congatec offers comprehensive documentation, training and signal integrity measurements for application development.

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Ever feel like the only constant in the data center industry is that things are always changing? You’re not alone. From rising densities to evolving environmental policies, there’s never a shortage of change in our field. Navigating this constant change is especially difficult for large enterprises with legacy infrastructures.

We believe that every data center should have its own digital twin to ensure data center teams are ready to adapt to these rapid changes. We put together an eBook that details several case studies from large enterprises in various industries with different pain points and needs that have found great success using Cadence data center digital twin solutions.

Aerospace Enterprise Dramatically Improves Data Center Performance

One of the world’s largest aerospace companies uses Cadence Reality DC Digital Twin for data center performance efficiency modeling and asset management. They initially needed a data center solution to help address cooling, compliance, and low operating efficiency issues. Before implementing Cadence Reality DC Digital Twin, the data center management team was using a manual, trial-and-error approach to IT installation planning, which was both time consuming and risky. At one point, they even experienced an outage.

This large aerospace enterprise began using Cadence Reality DC Digital Twin to perform engineering simulations. They built and calibrated models to form a digital twin model of their data halls, enabling them to see what would happen in different scenarios by testing them in the virtual model. Using Cadence’s built-in library items, which include cabinets, IT devices, and more, the aerospace enterprise could easily simulate how new deployments would perform in their data center environment. They also used Cadence Reality DC Digital Twin to examine cooling and power capacities and search for greater efficiency gains.

With help from Cadence tools and services, the company was able to simulate the changes in IT equipment in a virtual environment to understand the performance impact. Cadence Reality DC Digital Twin enabled the company to be more proactive in their approach to data center management. This simulation-based methodology for IT installation planning enabled the data center management team to adjust environments for maximum performance before installation. The company has quantified that it has been able to reduce power consumption and increase performance by 30-40% (depending on the data center).

This large enterprise now operates its data centers more reliably and sustainably, reducing power consumption without increasing environmental compliance risk, so much so that the management team was able to drop PUE at one of their data centers from PUE 4 to 1.6. They continue to use Cadence data center software to assess new deployments and efficiently perform monthly IT asset audits. Implementing Cadence Reality DC Digital Twin into their workflow for these purposes saves their engineering department a significant amount of time. Cadence Reality DC Digital Twin helps this aerospace enterprise overcome the challenge of fulfilling the competing objectives of compliance and efficiency at the same time.

Effectively Design and Operate Enterprise Data Centers

Large global companies in automotive, healthcare, finance, and aerospace are using Cadence data center solutions to effectively design and operate their data centers.

Danielle Gibson | Cadence Systems

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Ganga Sivaraman | Product Marketing Director, Optical Patterned Wafer Inspection | Applied Materials

Semiconductor production is an expensive and complex endeavor. The journey from R&D to high-volume manufacturing is a race, and whoever crosses the finish line first wins competitive advantage in terms of revenue, market share and profitability. Advanced chips are built up one layer at a time, and each of the billions of individual features must be perfectly patterned and aligned to create working transistors and interconnects with the best performance and power characteristics.

In both advanced logic and memory, the number of processing steps is increasing as we add more and more complexity to the latest and greatest chips. Defects introduced in between the process steps directly impact wafer yields and ultimately slow down an economy that runs on silicon. Patterned wafer inspection – the scientific study of defects across the entire wafer manufacturing lifecycle – has always been critical to controlling and perfecting the chipmaking process. However, as chip structures become ever smaller and the process grows in complexity, the way we inspect leading-edge chips needs to evolve.

More Complexity Calls for More Inspection

Management guru Peter Drucker is credited as saying, “what gets measured, gets managed.” Often, fab inspection strategies analyze data from a limited number of intermediate and end-of-module steps. But as process complexity increases, and techniques like multipatterning invite minor defects to become magnified, we need to gather data from all key process modules. Otherwise, defects and process drift may not become visible until engineers are faced with costly and inexplicable yield issues.

When determining where and how often to inspect, the right technical answer is, “more is better.” At the same time, fab managers need to control costs, which is why they must deploy an optimized approach that uses the most cost-efficient tools for the job. A mix and match of optical inspection approaches – both brightfield and darkfield – is the key for cost-effective yield monitoring and control.

Brightfield and darkfield wafer inspection technologies are complementary and typically used for addressing different application needs. Brightfield primarily collects reflected light, with the source of illumination oriented perpendicular to the wafer’s surface. Light bounces off the surface and returns a “bright” image showing a realistic view of the patterned features on the wafer, similar to the way a mirror shows a clear and precise reflection of a person’s face. With darkfield, the wafer can be imaged using either normal illumination or oblique illumination, where the light is at an angle to the wafer surface. Darkfield focuses primarily on collecting scattered light. When a beam of light encounters angled or rough surface features within a chip’s nanoscale patterns, its trajectory is altered. Collecting this scattered light produces images of the edges of 3D structures against a dark background.

Brightfield inspection primarily targets high-sensitivity applications and delivers lower inspection throughput. Darkfield is suited to lower-sensitivity applications — typically targeting defects of 20nm or greater in size — and delivers very high inspection throughput.

Wafer Inspection at a Crossroads

New challenges in advanced logic and memory are calling for a new playbook for optical wafer inspection. Chipmakers are telling us that they need new capabilities which maintain the high throughput and low cost-of-ownership characteristic of darkfield inspection while delivering optimal sensitivity for both 3D surface defects and surface pattern defects.

For example, defects in the sub-20nm range have traditionally been considered too small to have a significant impact on wafer yield and therefore have not been a priority for optical inspection. As the critical dimensions of devices continue to shrink, defects in this size range become more problematic. If left undetected, these small particles can block etching and cause pattern defects in subsequent steps. Traditional darkfield tools do not have the resolution to detect these critical defects of interest.

Likewise, when creating the vias that connect vertical layers of metal interconnects, tiny micro-scratches can be left behind in the oxide layer after chemical mechanical planarization (CMP) steps. These scratches must be detected early before they turn into bridge defects when the vias are filled with metal.

Applied Materials has a strong presence in the optical inspection market with its Enlight wafer inspection system which offers brightfield and darkfield modes. We believe chipmakers who are pushing the leading edge of logic and memory will eventually need a next-generation darkfield tool that can deliver a new combination of darkfield application sensitivity and throughput.

Based on extensive customer engagements, we are preparing to introduce a state-of-the-art wafer inspection system designed to deliver the industry’s highest darkfield application sensitivity at higher throughput. Our solution is designed to make it cost-effective for chipmakers to inspect more inter-module process steps, enabling them to effectively monitor and control wafer yield. With more than 10 customer engagements in 2023, we have successfully demonstrated our capabilities in high-throughput wafer inspection in a variety of processing modules such as deposition, CMP, lithography, etch, implant and a few custom modules.

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Courtesy: Anritsu

In our increasingly mobile-dependent world, the need for reliable wireless coverage and capacity inside buildings has become paramount.  This blog will delve into the concept of In-Building Wireless (IBW) systems, their significance, and the various architectures and technologies used to provide enhanced network coverage and capacity indoors. Understanding these systems is crucial as they are the backbone of our modern communication, enabling seamless connectivity in our homes, offices, and public spaces.

The demand for IBW systems becomes apparent when the existing macro network fails to meet the need for coverage and capacity within buildings adequately.  However, challenges such as building structure, low emissivity glass, and RF barriers created by adjacent buildings can lead to subpar coverage.  Overcoming these challenges is a testament to the importance and complexity of IBW systems, especially in densely populated urban areas and high-density venues like stadiums and convention centers.

The funding and ownership models for IBW systems are diverse, reflecting the various benefits derived from enhanced wireless services.  Operators sometimes negotiate leases with building owners, taking on the costs of designing, installing, and maintaining the IBW system in exchange for exclusive coverage rights.  In other cases, building owners are mandated by regulations to provide public safety coverage and cover the entire cost of the IBW system.  Cost-sharing is arranged in venues like shopping centers and stadiums, where both the building owner and mobile operators benefit, showcasing the adaptability and flexibility of IBW solutions.

IBW solutions are not one-size-fits-all. They can be categorized into three main architectures, each with its own unique features and benefits: Distributed Antenna Systems (DAS), Distributed Radio Systems (DRS), and Distributed Small Cells (DSC).  The choice of architecture is a critical decision, depending on various factors, including coverage objectives, budget, venue size, number of operators, and required technologies, emphasizing the importance of this selection process.

DAS is the most common method used to achieve IBW coverage and capacity.  It involves distributing signals from RF sources throughout the venue using passive components like coaxial cables, splitters, and directional couplers.  DAS can accept RF inputs from various signal sources, making it technology-neutral and suitable for multi-operator applications.  There are different types of DAS, each with its own unique characteristics: passive DAS, active DAS, hybrid DAS, and digital DAS, each with its strengths and weaknesses.

Passive DAS

Passive DAS uses only passive components to distribute signals throughout the venue.  It relies on coaxial cables, splitters, and directional couplers to divide the signal and achieve the desired signal level at each antenna.  Signal sources for passive DAS can include repeaters, bi-directional amplifiers (BDAs), and small cells.  Passive DAS is cost-effective, reliable, and suitable for multi-operator systems.  However, it can be challenging to modify after installation and may encounter passive intermodulation (PIM) issues.

Active DAS

Active DAS involves converting signals to light and distributing them over fiber optic cables to radio units distributed throughout the venue.  It offers greater flexibility in modifying sectorization and fine-tuning radiated power levels. Active DAS requires higher upfront costs but provides benefits such as easier cable routing, longer battery life for mobile users, and the ability to monitor system performance.  It is suitable for large venues and multi-operator applications.

Hybrid DAS

Hybrid DAS combines active and passive components to mitigate costs while maintaining performance.  It uses active components for long-distance signal transport and passive components for signal distribution within each zone.  Hybrid DAS provides a balance between cost, performance, and maintainability, making it suitable for multi-operator systems serving large and complex venues.

Digital DAS

Digital DAS utilizes radios manufactured by the DAS equipment provider and can accept RF inputs from various network equipment manufacturers.  It uses digital transport protocols to distribute signals and offers dynamic resource allocation within the venue.  Digital DAS supports centralized radio access network (C-RAN) and enables the backhaul of IP traffic.  It provides flexibility and scalability, making it suitable for venues with changing coverage requirements.

Conclusion

In-building wireless systems are crucial in providing reliable coverage and capacity inside buildings. The choice of IBW architecture depends on various factors, including coverage objectives, budget, and venue size.  Passive DAS, active DAS, hybrid DAS, and digital DAS each have their strengths and weaknesses, and the selection should be based on the specific requirements of the application.  As mobile devices evolve and data demands increase, IBW systems will continue to play a vital role in meeting the growing demand for indoor wireless connectivity.

The post Ensuring Seamless Connectivity: Guide to In-Building Wireless Systems and Distributed Antenna Systems appeared first on ELE Times.

Few methods for analog to digital conversion are more “mature” than the classic combination of a voltage-to-frequency converter (VFC) with a counter. VFC digitization is naturally integrating, so good noise rejection is inherent, as is programmable resolution (if you want more bits, just count longer). Unfortunately, and for the same reason, high conversion speed is not. Accurate, high resolution, microsecond VFC conversion times are defiantly difficult, but at least millisecond rates are definitely doable as shown in this design idea. 

Nearly four decades ago (in his Designs for High Performance Voltage-to-Frequency Converters), famed analog guru Jim Williams cataloged five fundamental techniques for voltage to frequency conversion. First on his list, described as “most obvious”, was the “Ramp-Comparator” type. Since I’ve always been a big fan of the obvious, the simple VFC shown in Figure 1 is a variation on that basic theme. It’s adapted for operation from a single supply rail, with convenient and flexible differential bipolar inputs, and acceptable linearity while running at frequencies up to 200 kHz. Here’s how it works.

Figure 1 A Ramp-Comparator style 200 kHz VFC that operates from a single supply rail, with differential bipolar inputs, and an acceptable linearity.

Wow the engineering world with your unique design: Design Ideas Submission Guide

A2, R1, and Q2 combine to make a precision (Q2 α~0.998) current sink with Q2 collector current:

Ic2 = (V1 –V2)/R1 = 100µA(V1 –V2)

Non-inverting input V1 can range from 0 to (2 – V2), has a nicely high input impedance (>1 TΩ) and a low bias current (10 pA). Inverting input V2 has a lower impedance (10 kΩ) but will accept a voltage span from as positive as V1 to as negative as (V1 – 2). If only one input is used, the other should simply be grounded. Zero offset is about 200 µV (0.01%).

As shown in Figure 2 (yellow trace), Ic2 ramps 1-nF timing capacitor C1 from its reset voltage of 3.5 V down to the 2.5-V trigger level provided by voltage reference U1. The ramp time required to do this is given by:

T = C1(3.5 – 2.5)/Ic2 = C1R1/(V1 – V2)
= 1nF 10k/(V1 – V2) = 10µs/(V1 – V2)
Fout = 1/T = 100kHz (V1 – V2) < 200kHz

Figure 2 VFC oscillation waveshapes where: Vc1 is the VFC timing ramp, Fout is the output to counter, and A1p5 is the comparator’s non-inverting input.

Comparator A1’s inverting input is connected to C1, while its non-inverting input watches the 2.5-V reference. When the Vc1 ramp descends to 2.5 V, a sequence of (quite quick) events are set in motion.

First, A1’s output transitions toward 5 V, completing the move at 30 V/µsec in about 160 ns, the speed being enhanced by positive feedback via C4. This provides an output pulse (Figure 2 green trace) on Fout and turns on Q3 to begin the ramp-reset recharge of C1. Meanwhile C3 couples Q3’s output to D1, reverse biasing the diode and temporarily diverting Ic2 away from C1, which creates the funny little flat spots seen on Figure 2’s yellow and red traces. More on this later.

C1’s recharge current is routed via Q3’s emitter to Q1’s base, driving Q1 into saturation, accurately pulling R3’s top end to +5 V and thereby A1’s non-inverting input (pin 5) to 2.5(R5/(R3 + R5)) + 2.5 = 3.5 V (Figure 2 red trace). C1 recharge continues until A1 pin 5 reaches pin 6’s 3.5 V, whereupon A1 switches back to 0, turning off Q3 (fast because Q3 never saturates) and completing the Fout pulse.

Meanwhile, Q3’s turnoff has removed base drive from Q1, allowing it to recover from saturation (which takes about 500 ns consisting mostly of storage time), turn off, and release R3. This allows A1’s pin 5 to return to U1’s 2.5-V reference, where it waits for the end of the next timeout and VFC cycle.

It also dumps integrated Ic2 charge accumulated on C3 during ramp reset through D1 onto C1. The D1 C3 circuit feature thus cancels out an integral nonlinearity error that typically bedevils Ramp-Comparator VFCs due to charge lost during the ramp reset interval. Williams advises about this defect in his analysis of the Ramp-Comparator topology “A serious drawback to this approach is the capacitor’s discharge-reset time. This time, ‘lost’ in the integration, results in significant linearity error…” The D1 C3 connection prevents this nonlinearity by allowing integration of Ic2 to continue uninterrupted during ramp reset, so no time is “lost”. Thanks for the warning, Jim!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• New VFC uses flip-flops as high speed, precision analog switches
• Inexpensive VFC features good linearity and dynamic range
• “Hippasian” nonlinear VFC stretches dynamic range
• Voltage-to-period converter improves speed, cost, and linearity of A-D conversion
• VFC makes simple capacitance meter

The post Single supply 200kHz VFC with bipolar differential inputs appeared first on EDN.

• Industry’s first use of ruthenium in high-volume production enables copper chip wiring to be scaled to the 2nm node and beyond and reduces resistance by as much as 25%
• New enhanced low-k dielectric material reduces chip capacitance and strengthens logic and DRAM chips for 3D stacking

Applied Materials, Inc. introduced materials engineering innovations designed to increase the performance-per-watt of computer systems by enabling copper wiring to scale to the 2nm logic node and beyond.

“The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption,” said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. “Applied’s newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights.”

Overcoming the Physics Challenges of Classic Moore’s Law Scaling

Today’s most advanced logic chips can contain tens of billions of transistors connected by more than 60 miles of microscopic copper wiring. Each layer of a chip’s wiring begins with a thin film of dielectric material, which is etched to create channels that are filled with copper. Low-k dielectrics and copper have been the industry’s workhorse wiring combination for decades, allowing chipmakers to deliver improvements in scaling, performance and power-efficiency with each generation.

However, as the industry scales to 2nm and below, thinner dielectric material renders chips mechanically weaker, and narrowing the copper wires creates steep increases in electrical resistance that can reduce chip performance and increase power consumption.

Enhanced Low-k Dielectric Reduces Interconnect Resistance and Strengthens Chips for 3D Stacking

Applied’s Black Diamond material has led the industry for decades, surrounding copper wires with a low-dielectric-constant – or “k-value” – film engineered to reduce the buildup of electrical charges that increase power consumption and cause interference between electrical signals.

Applied today introduced an enhanced version of Black Diamond, the latest in the company’s Producer Black Diamond PECVD* family. This new material reduces the minimum k-value to enable scaling to 2nm and below, while offering increased mechanical strength which is becoming critical as chipmakers and systems companies take 3D logic and memory stacking to new heights.

The latest Black Diamond technology is being adopted by all leading logic and DRAM chipmakers.

New Binary Metal Liner Enables Ultrathin Copper Wires

To scale chip wiring, chipmakers etch each layer of low-k film to create trenches, then deposit a barrier layer that prevents copper from migrating into the chip and creating yield issues. The barrier is then coated with a liner that ensures adhesion during the final copper reflow deposition sequence, which slowly fills the remaining volume with copper.

As chipmakers further scale the wiring, the barrier and liner take up a larger percentage of the volume intended for wiring, and it becomes physically impossible to create low-resistance, void-free copper wiring in the remaining space.

Today, Applied Materials publicly introduced its latest IMS (Integrated Materials Solution) which combines six different technologies in one high-vacuum system, including an industry-first combination of materials that enables chipmakers to scale copper wiring to the 2nm node and beyond. The solution is a binary metal combination of ruthenium and cobalt (RuCo), which simultaneously reduces the thickness of the liner by 33 percent to 2nm, produces better surface properties for void-free copper reflow, and reduces electrical line resistance by up to 25 percent to improve chip performance and power consumption.

The new Applied Endura Copper Barrier Seed IMS with Volta Ruthenium CVD is being adopted by all leading logic chipmakers and began shipping to customers at the 3nm node. An animation of the technology can be viewed here.

Customer Comments

“While advances in patterning are driving continued device scaling, critical challenges remain in other areas including interconnect wiring resistance, capacitance and reliability,” said Sunjung Kim, VP & Head of Foundry Development Team at Samsung Electronics. “To help overcome these challenges, Samsung is adopting multiple materials engineering innovations that extend the benefits of scaling to the most advanced nodes.”

“The semiconductor industry must deliver dramatic improvements in energy-efficient performance to enable sustainable growth in AI computing,” said Dr. Y.J. Mii, Executive Vice President and Co-Chief Operating Officer at TSMC. “New materials that reduce interconnect resistance will play an important role in the semiconductor industry, alongside other innovations to improve overall system performance and power.”

A Growing Wiring Opportunity

Applied is the industry leader in chip wiring process technologies. From the 7nm node to the 3nm node, interconnect wiring steps have approximately tripled, increasing Applied’s served available market opportunity in wiring by more than $1 billion per 100,000 wafer starts per month (100K WSPM) of greenfield capacity, to approximately $6 billion. Looking ahead, the introduction of backside power delivery is expected to increase Applied’s wiring opportunity by another $1 billion per 100K WSPM, to approximately $7 billion.

The new chip wiring products, along with other materials engineering innovations for making future AI chips, will be discussed at Applied’s SEMICON West 2024 Technology Breakfast. The presentation and other materials from the event will be available on the Applied Materials website at: https://ir.appliedmaterials.com on Tuesday, July 9, 2024 at approximately 9:00 a.m. ET / 6:00 a.m. PT.

*PECVD = Plasma-Enhanced Chemical Vapor Deposition

*CVD = Chemical Vapor Deposition

Forward-Looking Statements

This press release contains forward-looking statements, including those regarding anticipated benefits of our new products and technologies, expected growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, and other statements that are not historical facts. These statements and their underlying assumptions are subject to risks and uncertainties and are not guarantees of future performance. Factors that could cause actual results to differ materially from those expressed or implied by such statements include, without limitation: failure to realize anticipated benefits of our new products and technologies; the level of demand for semiconductors and for our products and technologies; customers’ technology and capacity requirements; the introduction of new and innovative technologies, and the timing of technology transitions; market acceptance of existing and newly developed products; the ability to obtain and protect intellectual property rights in technologies; our ability to ensure compliance with applicable law, rules and regulations; and other risks and uncertainties described in our SEC filings, including our recent Forms 10-Q and 8-K. All forward-looking statements are based on management’s current estimates, projections and assumptions, and we assume no obligation to update them.

The post Applied Materials Unveils Chip Wiring Innovations for More Energy-Efficient Computing appeared first on ELE Times.

Author: STMicroelectronics

What questions will ST answer at electronica China 2024? Too often, attendees don’t take the time to step back and ask what challenges they would need to solve or think of the answers they should seek. It’s easy to get caught up in the event’s excitement and the flood of information. That’s why we decided to highlight some of the questions our readers may have and provide answers. Hence, even if members of our community can’t physically attend this event, they will still get tools and ideas that can help them find innovations and efficiency.

What would it take to build an ST car? A powertrain domain controller!

Attendees at electronica China 2024 will probably be surprised when they see the ST car, a small mock-up electric vehicle. The demo aims to show a modern approach to domain controllers by grouping multiple systems under one host MCU. Thanks to its multiple cores and virtualization capabilities, the Stellar P3 can support mid-level integrated electrification applications, while the Stellar P6 could run even more highly integrated electrification systems. We also increased the battery management system from a previous demo to support 800 V and worked to create an ASIL-D-ready system. In a nutshell, we show how ST solution advantages can help design teams shorten the development cycle and gain market shares.

In our demo car, the host MCU runs the onboard charger and DC-DC converter, the vehicle control unit, which is responsible for the relays, pumps, charger-lock, and more, the battery management system, and the inverter. Additionally, we provide solutions for engine management systems (EMS), transmission control units (TCU), thermal management systems, and more. Integrators can focus on the application instead of worrying about how the electronics will work together. The platform we are showing is continuously evolving, and we’ll release a new version before the end of the year. In the meantime, we continue to show how car makers can take advantage of the computational throughput and safety features of a device like the Stellar P.

As readers of the blog will remember from our power liftgate demo, the industry is looking into consolidating resources. It is one of the simplest ways to bring new features to mainstream vehicles. It simplifies development and helps reduce costs by sourcing more components from the same company, which significantly helps with overall pricing. The ST mock-up vehicle is another example of how ST is helping makers jump on the bandwagon. We also try to make critical technologies more accessible, like over-the-air updates, thanks to our phase-change memory, which is capable of increasing its capacity to enable flashing a new firmware without requiring hardware partitioning like A/B memory banks.

How do you promote sustainability? With integrated hybrid photovoltaic, energy storage, and charging solutions!

Too often, cities know they need to implement new energy strategies that combine solar panels, energy storage, and charging solutions. Moreover, car makers must learn to utilize these new systems, which can lead to a lack of cohesion or slow adoption. Consequently, ST is featuring an energy storage and management solution demo at electronica China 2024 that shows how our devices can help deliver power across infrastructures. It uses our third-generation SiC MOSFETS, enhancement mode PowerGaN transistors, high-performance MCUs, galvanic isolation gate drivers, and more to control and protect the entire system. Put simply, it’s about achieving higher efficiency, better stability, and greater reliability than the industry traditionally offers today.

E-meter

It starts with a power line and hybrid platform for e-meters that uses the STM32WL3, which includes two radios and one ultra-low power wireless MCU. The board also comes with the ST8500 programmable powerline modem and the STLD1 driver.

Micro-inverter

Many charging solutions rely on solar energy to further improve their environmental impact. Hence, an efficient micro-inverter that transforms what solar panels capture is critical. That’s why we are featuring a micro-inverter powered by our MASTERGAN1L solution, which is key to such a small factor thanks to its wide bandgap. Additionally, the module runs on an STM32G4, thanks to its high-resolution timers and high-precision ADCs.

Main inverter

To ensure greater efficiency when converting solar energy and distributing it, ST developed an inverter powered by silicon carbide: the SCT070W120G3-4AG and SCT055W65G3-4AG. After 25 years of innovations, ST can offer a 15kW three-phase three-level Active Front End bidirectional PFC converter. We even provide design tools like STPOWER Studio to help engineers design their PCBs quickly.

Battery charging

To send power from the charger to the battery, we offer a couple of systems, both running on an STM32G4. We even provide the STGAP2SICS for SiC MOSFETs, which implements an under-voltage lockout (UVLO) to ensure the safe, stable, and efficient operation of the entire system.

Battery management

Finally, to manage the energy stored in the car’s batteries, we offer the AEK-POW-BMS63EN, a development platform for the L9963E that makes battery management solutions vastly more accessible. Indeed, thanks to its battery holder, its ability to daisy chain up to 31 nodes in minutes, its board dedicated to isolation, and software that helps take advantage of its features, engineers can significantly reduce their time to market.

How do you detect the orientation of a cup and its liquid level in a short time? Smart Cup Detection

 

It’s a complex problem because it requires fast computing, vision, and other sensors to determine where the cup is and how much liquid is in it. Or, one could just use the VL53L7CH or VL53L8CH time-of-flight sensors from ST. That’s what we will show at electronica China 2024 with a demo of a simulated coffee machine that can measure 64 different zones, represent the data in a compact normalized histogram, and enable the creation of a machine learning algorithm capable of detecting if the cup is upside down, off-center, absent, its height, and how much liquid it contains.

The only significant difference between the VL53L7CH and VL53L8CH is that the former has greater coverage and field of view for applications that monitor a larger area. The demo uses an X-NUCLEO-53L8A1 development board and a 3D-printed housing shaped like a coffee machine. Put simply, it showcases how integrators can create a complex detection system with few components and processing requirements, making this technology highly accessible.

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