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India is stepping up investments in key EV technologies. The South Asian country is speeding up its investments in key electric vehicle (EV) technologies while planning to boost a self-dependent and globally relevant EV manufacturing ecosystem. Driven by various central government initiatives, state government programs, and private sector investments, India attracted commitments for around US$25.6 billion worth of investments across battery manufacturing, advanced battery chemistries, powertrains, charging infrastructure, and technologies for battery and electric powertrains. These investments will help scale up domestic manufacturing and reduce dependence on imported components.

The Government of India launched multiple schemes to boost domestic manufacturing of the Electric Vehicles (EV) ecosystem through production-linked Incentive (PLI) Schemes for Advanced Chemistry Cell (ACC) and battery storage, as well as the PM E-Drive program to promote charging. The PM E-Drive program aims to promote charging for automobiles and auto components. Along with manufacturers both domestically and overseas, these schemes lead to localization of EVs’ key technologies.

The post India Accelerates Core EV Technology Investments to Strengthen Domestic Manufacturing Ecosystem appeared first on ELE Times.

High-voltage batteries for e-mobility have become highly complex systems consisting of numerous components. The market for these batteries is becoming increasingly dynamic, and technologies are constantly evolving: innovative battery cells with new chemical compositions are being introduced. Automotive suppliers and manufacturers therefore require a tailored and flexible testing strategy for battery cell quality assurance, both in development and in production. Only in this way can suppliers compete in the market with more powerful batteries, higher levels of automation, and optimized workflows.

To address these challenges, GÖPEL electronic has developed a high-performance and quickly configurable battery cell tester that features a modular design and high flexibility. This allows for the quick and transparent determination of quality, charging efficiency, and reliability in up to five battery cells simultaneously. The tester complements the product portfolio, which includes, among other things, GÖPEL electronic’s EOL battery test system, which performs comprehensive test routines for the entire battery pack.

The new battery cell tester covers standard safety tests that evaluate the condition of the cells: The OCV (Open Circuit Voltage) value indicates the voltage of a battery without a load (open circuit) and serves as an indicator of its state of charge. For the ACIR (Alternating Current Internal Resistance) measurement, the tester uses a test method to determine the internal resistance of the battery cells. This internal resistance under alternating current provides information about the performance, state of aging, and quality of the battery cell.

The main advantage of the new, smaller tester from GÖPEL electronic lies in its fast and reproducible test results: By interfacing with automated equipment, highly efficient batch testing can be performed in a matter of seconds. This is ideal, for example, for incoming inspection or cell grouping.

The post Fast and Flexible Test Device for Safety and Functional Testing of Battery Cells appeared first on ELE Times.

Ather Energy has started rolling out Pothole+ Alerts for customers with Gen 2 and above scooters, including the Ather 450 Apex, 450X and Rizta Z. The feature leverages data generated by Ather’s connected scooter fleet to warn riders about potholes, broken road sections, uneven surfaces and speed breakers ahead while navigating. It also goes a step further, suggesting the smoothest route before a ride begins, beyond just the fastest one.

Announcing the rollout on X, Ather Co-founder and CEO Tarun Mehta said the feature had been nearly nine years in the making. “The challenge was never the idea. It was the data,” Mehta wrote. He explained that building the feature required a large connected fleet travelling the same roads over time, allowing Ather to generate the scale of fleet intelligence needed to accurately identify road conditions.

Every Ather scooter comes equipped with onboard compute and connectivity, enabling the company to continuously gather real-world riding data and deliver new capabilities through over-the-air software updates. According to Mehta, Pothole+ Alerts represents one of the first large-scale applications of this connected ecosystem, transforming millions of kilometres of ride data into a feature that benefits riders every day.

Integrated into the scooter’s navigation experience, Pothole+ Alerts provides advance notifications for potholes, broken road sections, uneven surfaces and speed breakers. Alerts are displayed on the dashboard and can also be delivered through the scooter’s speakers, the Ather Halo smart helmet or any compatible Bluetooth headset.

The rollout reflects Ather’s continued focus on building connected features powered by real-world riding data. Mehta added that Pothole+ Alerts is just the beginning, with the company planning to build more rider experiences on top of its growing road intelligence dataset.

The post Ather Energy Rolls Out Pothole+ Alerts, Built on Connected Fleet Intelligence appeared first on ELE Times.

Aeluma Inc of Goleta, CA, USA has signed a letter of intent (LOI) for up to $30m of proposed funding under the CHIPS and Science Act, which is administered by the US Department of Commerce. The award will support R&D on the firm’s scalable, non-InP (indium phosphide) semiconductor manufacturing platform for photonics...

AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials at plants in China — has entered into a definitive agreement with Lumentum Operations LLC of San Jose, CA, USA (which designs and makes photonic products for optical networks and lasers for industrial and consumer markets) for the supply and capacity reservation of indium phosphide wafer substrates...

Стипендія КМУ за видатні заслуги у сфері вищої освіти Віталію Дідковському KPI4U-2 чт, 07/30/2026 - 10:00

Here’s a question your grandfather could have answered: Would you rather have a million dollars today or a penny that doubles every day for a month? Most people take the million. The penny reaches $5 million by day 30.

Human intuition is simply bad at exponential math. We think in straight lines, and compounding curves surprise us every time. Now run that intuition in reverse.

An AI coding agent that’s right 98% of the time sounds impressive. And 98% is a generous assumption, probably better than reality for most tasks. But apply that accuracy across 34 steps with no verification in the loop, and you’ve crossed the coin-flip line. More likely wrong than right. The math is 0.98^34 = 0.505.

The surprise is the same one your grandfather felt. And in a safety-critical development environment, the consequences are not a missed investment opportunity.

Sophisticated agentic systems don’t run open-loop. They compile, test, lint, and self-verify at each step, and the public record shows it works.

Andreas Kling ported Ladybird’s LibJS engine from C++ to Rust using AI agents across hundreds of human-directed prompts, producing 25,000 lines of Rust with zero regressions across 65,359 tests and byte-for-byte identical bytecode output. The human was in the loop at every decision point, which is precisely why it worked.

The Bun JavaScript runtime went further. AI Weekly highlighted that Claude agents rewrote roughly one million lines of Zig to Rust autonomously across 6,755 commits, passing 99.8% of its existing test suite. It also left 13,044 unsafe Rust blocks, where a comparable handwritten project would have 73. A passing test suite doesn’t surface this safety debt—it stops a safety-critical certification in its tracks.

Both of these projects succeeded because verification ran inside the loop at every step. They also illustrate exactly where the limits are. In most software development contexts, the floor is an efficiency problem. Verification catches it, the agent retries, and the process converges. Expensive in tokens and time, but recoverable.

In safety-critical development, the calculus is different. This is where functional correctness testing and safety-critical qualification part ways. Bun passed its own test suite. Ladybird produced byte-for-byte identical bytecode. Those are impressive results. But they are not safety cases. ISO 26262, DO-178C, and IEC 62304 don’t recognize self-generated test results as qualified verification evidence.

Your braking system software doesn’t get partial credit for passing tests it wrote for itself. Your insulin pump firmware isn’t certified on a curve. The standards assume deterministic tools producing verifiable evidence—qualified tools, documented configurations, and traceable outputs. An agentic workflow that self-verifies is better than one that doesn’t. But in safety-critical development, it still isn’t enough.

What safety-critical compliance actually requires isn’t vague.

ISO 26262 mandates a documented safety plan, requirements with bidirectional traceability from hazard analysis through to verified implementation, and evidence that coding guidelines—typically MISRA C or CERT C—were enforced by a qualified tool using a qualified configuration.

DO-178C adds structural coverage requirements. At the highest criticality levels, every statement, every branch, and every condition and its complement must be exercised by tests that are themselves traced to requirements.

IEC 62304 requires a software development lifecycle with documented verification activities at each phase. In every case, the evidence must be generated as the work happens rather than reconstructed afterward—and not self-certified by the tool that produced the artifact being evaluated.

The open-loop pipeline isn’t an edge case; it’s what every team promises to fix after the next release. A requirements review is handed to a code generator, a documentation tool, and a traceability updater with testing saved for the end. That’s not an agentic worst case. That’s a pipeline. At 98% per-step accuracy across 34 stages, you’ve crossed the coin-flip line before you’ve run a single test.

The answer isn’t a better model. It’s the same answer safety-critical engineers have always given to unreliable processes. You don’t improve your way to acceptable; you gate your way there.

Static analysis enforces expected coding patterns and flags dangerous anti-patterns like uninitialized memory, undefined behavior, and violations of MISRA or CERT rules that exist precisely because they’ve caused failures before.

Unit tests verify that individual components behave as specified under known conditions. And coverage in safety-critical development isn’t a spot-checking exercise. DO-178C requires 100% MC/DC coverage at DAL A, and ISO 26262 requires the same at ASIL D. Every line. Every branch. Every condition.

Each gate resets the accumulated uncertainty back toward zero before the next stage compounds it further. That’s not a new idea. It’s how you build software that people’s lives depend on.

The question AI raises isn’t whether to use gates. It’s whether the gates you already have are positioned to catch what an AI agent introduces and whether you’ve thought carefully about where in the workflow the uncertainty is actually accumulating.

The gates were designed for a world where code has an author who made deliberate choices. A human developer who writes an uninitialized variable made a mistake. A human developer who skips a boundary check made a tradeoff. Static analysis flags both—the developer understands the finding in context, and the correction is made by someone who knows what the code is supposed to do. The evidence trail is intact. The intent is recoverable.

An AI agent doesn’t make mistakes in that sense. It produces outputs that are statistically consistent with its training: plausible, often correct, and occasionally wrong in ways that look right.

The static analysis tool will still flag the MISRA violation. The unit test will still fail on the boundary condition. But the developer reviewing the finding is now one step removed from the original intent because there wasn’t original intent in the human sense. There was a probability distribution. And when you ask the agent why it made that choice, the answer is not recoverable in any form a certification auditor can use.

The gates catch the artifact. They don’t reconstruct the argument. In a safety case, you need both, and one of them must have been generated as the decisions were made, not reverse engineered from the output afterward.

The consumer technology press calls it “hallucination,” which means the AI confidently states something wrong. This term captures the symptom, but not the mechanism.

In safety-critical engineering the mechanism is what matters. ISO/PAS 8800, the emerging automotive standard for AI safety that the broader embedded industry is watching closely as a template, uses the term “functional insufficiency”: an unexpected error under specific conditions not adequately represented during development. As EDN noted, for engineers building software for medical devices, industrial automation, rail, aerospace, and defense, dismissing this document as “just for cars” would be a missed opportunity.

The distinction matters. Hallucination implies the system invented something from nothing. Functional insufficiency describes something more precise. The system performed exactly as its training data suggested it should, and the training data didn’t cover this case.

You can’t fix a hallucination by improving the model. You can’t fix a functional insufficiency that way either. What you can do is bound it, monitor it, and build an architecture that prevents it from propagating into a safety-critical decision unchecked.

None of this is an argument against AI in safety-critical development. These industries already have the architectural foundations to manage it responsibly. That argument is already lost, and it should be. AI tools are accelerating development, surfacing defects earlier, and handling the kind of repetitive verification work that exhausts engineers and introduces its own error rate.

The question was never whether AI would enter these industries. It’s here. The question is whether the engineering discipline surrounding it will keep pace.

Compound uncertainty doesn’t care about your intentions or your vendor’s benchmark scores. A 98% accurate agent in a 34-step open-loop workflow has already crossed the coin-flip line. Those numbers don’t improve because the use case is important or the schedule is tight.

Compound uncertainty in multi-step workflows. Even with 95% per-step accuracy, overall success rate declines sharply as the number of workflow steps (N) increases—not because model performance degrades, but because the workflow itself compounds error. Source: Parasoft

What does improve the outcome is treating AI in safety-critical development the way these industries have always treated unreliable components: with gates, evidence, and documented reasoning that survives an audit.

The standards that govern medical devices, aviation software, and automotive systems were written for a deterministic world. But the principles they encode—rigorous verification, traceable decisions, complete coverage, and structured safety arguments—turn out to be exactly the right response to a world where probabilistic behavior slipped into the development process before anyone checked its credentials.

ISO/PAS 8800 is the automotive industry’s first formal attempt to extend those principles into AI-specific territory. Other domains are watching. The framework outlined in the embedded world—manage uncertainty, bound it, argue it, and monitor it—applies whether you’re building firmware for a ventilator or a flight control system or an autonomous vehicle.

You will never eliminate functional insufficiency from an AI system. However, you can build an architecture that catches it before it becomes a safety event. That’s not a limitation of technology. It’s just engineering.

Arthur Hicken is a senior software evangelist at Parasoft.

Ricardo Camacho is director of product strategy for embedded and safety critical compliance at Parasoft.

Related Content

• AI Safety Moves to the Forefront
• Specifying Objectives is Key to AI Safety
• Can We Trust AI in Safety Critical Systems?
• Safe Automated Driving Starts with Architecture
• The impact of AI/ML on qualifying safety-critical software

The post Compound uncertainty: AI’s hidden risk in safety-critical development appeared first on EDN.

Multi-national industrial and energy company METLEN Energy & Metals S.A. of Athens, Greece — which operates the only vertically integrated bauxite, alumina and primary aluminium production unit in the European Union (EU) with privately owned port facilities — has announced a long-term commercial agreement for the supply of about 25% of the annual gallium production from its planned production facility in Greece...

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has appointed Andy W. Mattes to its board of directors...

Wide-bandgap (WBG) materials, particularly silicon carbide (SiC) and gallium nitride (GaN), are no longer considered exotic semiconductors. The automotive industry has chosen them for their ability to switch faster, tolerate higher blocking voltages and temperatures, and dissipate less energy than conventional silicon.

The physical and electrical characteristics of SiC and GaN enable improved efficiency in electric and hybrid drivetrains, higher power density, and better thermal management. This article examines the current state and next steps for both technologies across different key automotive areas, including traction inverters, on-board chargers (OBCs), DC/DC converters, and auxiliary power systems.

Traction inverters: the realm of SiC, but GaN makes headway

The transition from a 400-V to 800-V bus architecture, a common trend in electric-vehicle design, has halved the current required to deliver the same power. This reduction, in turn, enables ultra-fast charging, as EVs can absorb more power without incurring hazardous current levels or excessive heating. Moreover, the 800-V bus power delivery significantly lowers internal heat loss and allows for lighter and thinner vehicle wiring.

This architecture shift is a key factor for WBG adoption. At 800 V, the traction inverter operates with bus voltages that are very close, or even higher, than the rating limits of conventional silicon power devices, such as IGBTs.

SiC MOSFETs, rated at 1,200 V or higher with low on-resistance (RDS(on)) and fast-switching behavior, are suited for this application. In 2021, SiC inverters had a market share of less than 8% in global EV production, reaching 24% by 2026, according to market research firm Market Intelo. Analysts estimate that by 2030, SiC inverters will reach a 55% market share across EV production.

In January 2025, Wolfspeed Inc. introduced its Gen 4 SiC MOSFET platform, covering 750-V, 1,200-V, and 2,300-V voltage classes in discrete, module, and bare-die form. Compared with the previous version, Gen 4 technology reduces the specific on-resistance (Ron,sp) at high temperatures by up to 21% (with an even higher reduction at low temperatures) and provides improved turn-on performance with reduced ringing.

Built on this platform are the 1,200-V six-pack power modules (Figure 1), part of the automotive-qualified YM Six-Pack module line. These modules integrate a direct-cooled pin-fin baseplate and use sintered die-attach layers, copper-clip interconnects, and epoxy encapsulation to improve power-cycling capability. According to Wolfspeed, they deliver a 3× higher power-cycling capability at rated operating temperature than comparable competitor modules. The YM package size is compatible with existing IGBT inverter housings, simplifying platform migration.

Figure 1: Based on Wolfspeed’s Gen 4 SiC MOSFET technology, the six-pack YM power modules comply with the AQG-324 automotive standard. (Source: Wolfspeed Inc.)

Wolfspeed recently introduced its Gen 5 SiC MOSFET planar technology. Manufactured in Wolfspeed’s 200-mm fabs, the latest generation further reduces Ron,sp by up to 27% for 1,200-V devices, raising continuous junction temperature to 200°C for improved reliability.

STMicroelectronics provides 750-V and 1,200-V, automotive-qualified devices for 400-V and 800-V EV traction inverters, thanks to the introduction of the company’s Gen 4 SiC MOSFET technology. Gen 4 devices offer reduced RDS(on) (8.2 mΩ and 10.2–10.9 mΩ for the 750-V and 1,200-V classes, respectively) to cut conduction losses.

ST also announced the ongoing development of a higher-temperature-capable architecture to further reduce RDS(on) at high junction temperatures, meeting the requirements of air-cooled or passively cooled traction inverter designs.

Rohm Semiconductor introduced the TRCDRIVE pack, designed for xEV traction inverters. Built on Gen 4 SiC MOSFET technology, these 750-V and 1,200-V, two-in-one SiC molded modules feature higher power density, a compact layout that optimizes heat dissipation, and signal terminals supporting press-fit mounting (Figure 2).

Figure 2: Rohm’s TRCDRIVE pack modules offer high power density and simplify assembly through press-fit pins. (Source: Rohm Semiconductor)

Rohm also partnered with Schaeffler on a high-voltage inverter brick in mass production for a leading Chinese automaker. The brick integrates Rohm’s Gen 4 SiC MOSFET bare chips with a DC-link capacitor, a cooling solution, and a DC boost function. The design allows 800-V EVs to use a 400-V charging infrastructure. More recently, Rohm announced the availability of its Gen 5 SiC MOSFETs, targeting xEV traction inverters with a further reduction of RDS(on) at high temperatures.

Cambridge GaN Devices (CGD) has developed a 650-V ICeGaN device for automotive applications, including xEV traction inverters. While the device offers a lower blocking voltage than SiC counterparts, according to CGD, it can be paralleled without suffering imbalance or requiring a careful selection of components with similar characteristics.

The ICeGaN device integrates protection features, offering low RDS(on) (9 mΩ), reduced losses, and improved thermal management. CGD has also showcased a multilevel, 800-V inverter based on this device that can power electric motors to over 100-kW peak, 75-kW continuous power.

OBCs: SiC and GaN share the space

The OBC converts the AC grid power to the DC required by the main battery. It operates at lower power (typically 11 kW to 22 kW for passenger cars) than the traction inverter. SiC MOSFETs are currently the most common choice for OBCs, particularly for 800-V battery systems in which 1,200-V SiC devices offer wide operating margins and high reliability.

Rohm released a family of 750-V and 1,200-V SiC molded modules in the HSDIP20 package for xEV OBCs. The package integrates components for power-factor correction (PFC) and LLC conversion, including SiC MOSFETs, an insulating substrate, and decoupling elements. Available in four-in-one and six-in-one configurations, the modules reduce chip temperature by up to 38°C under a 25-W output load compared with discrete SiC MOSFETs.

Navitas Semiconductor announced the automotive qualification of its high-power GaNSafe Gen 4 ICs to both AEC-Q100 (integrated circuit) and AEC-Q101 (discrete transistor) standards (Figure 3). The GaNSafe family integrates control, gate drive, and sensing. It also offers short-circuit protection with a maximum latency of 350 ns, 2-kV ESD protection on all pins, programmable slew rate control, and elimination of the negative gate drive requirement. The devices are suited for OBCs and HV-LV DC/DC converters.

Navitas also introduced the first production-ready, 650-V bidirectional GaNFast ICs with IsoFast isolated gate drivers. This solution enables OBCs with a single-stage AC/DC topology that eliminates the conventional two-stage approach (with a separate PFC and DC/DC).

Figure 3: For the automotive-qualification process, Navitas prepared a reliability report with over seven years of production and field-data analysis. (Source: Navitas Semiconductor)

DC/DC converters and 48-V systems: GaN gains ground

GaN power devices are being adopted in DC/DC converters for EV applications. In EVs, DC/DC converters step down the main 400-V or 800-V battery bus to 12 V or 48 V for vehicle auxiliary loads. For example, Vitesco Technologies selected Infineon Technologies AG’s CoolGaN 650-V devices for its Generation 5+ DC/DC converter. The fast-switching capability of GaN at 650 V enables higher converter switching frequencies, which reduces the size of the magnetics and filtering capacitors.

Figure 4: Infineon’s 100-V CoolGaN transistors target applications such as zone control and main DC/DC converters, auxiliary systems, and Class D audio amplifiers. (Source: Infineon Technologies AG)

Also, auxiliary vehicle systems, such as electric power steering pumps, cooling fans, HVAC compressors, and 48-V mild hybrid motor generators, operate at voltage levels at which 100-V- to 200-V-rated GaN devices are fully suitable today.

One example is Infineon’s automotive-grade GaN transistor family that is suitable for low-voltage subsystems, such as 48-V and auxiliary power rails in hybrid and full-electric vehicles. These CoolGaN 100-V G1 devices (Figure 4) are qualified to AEC-Q101.

SiC is also used in DC/DC converters, particularly for bidirectional designs operating from 800-V battery systems. The Rohm HSDIP20 molded modules mentioned in the OBC section are specified for both PFC and LLC DC/DC stages, making them suitable for OBC and DC/DC converter applications.

Final considerations

After reaching mature status as a semiconductor technology, the primary challenge for SiC has shifted to scaling up production volume and reducing costs. The wide adoption of SiC in the automotive industry has forced the transition from older, 150-mm to 200-mm wafers, with the setup of dedicated fabs. This shift significantly reduces the cost of single chips and increases the yield per wafer. Wolfspeed has advanced production by developing the industry’s first 300-mm, single-crystal SiC wafer.

In the past, GaN faced issues with automotive adoption due to a lack of long-term field-reliability data. As mentioned, several GaN devices have successfully achieved AEC-Q101 and AEC-Q100 qualifications. Moreover, several manufacturers, including Texas Instruments Inc., are claiming a failure-in-time rate for GaN devices below 1 (fewer than one failure per billion device-hours) over a targeted 10- or 15-year lifecycle.

Interestingly, GaN is also experiencing a 300-mm trend. Because GaN is typically grown on top of standard silicon substrates (GaN-on-Si), companies such as Infineon have scaled 300-mm GaN power wafer technology by using existing silicon manufacturing lines, lowering the device costs.

Imec also announced plans to manufacture 300-mm GaN wafers with several partners, including Aixtron, GlobalFoundries, KLA Corporation, Synopsys, and Veeco. The GaN program will focus first on using 300-mm Si(111) as a substrate for low-power applications, followed by high-power applications (650 V and above) using 300-mm semi-spec and CMOS-compatible QST­ engineered substrates from Qromis Inc.

The post How SiC and GaN are reshaping automotive power electronics appeared first on EDN.

This is hackxpansion, it is powered by the RP2354B, has a 2" 240x320 LCD, and a ≈6h battery life while in use. It has two modules slots by default, and I'm currently working on a back attachment (last photo) which add two more slots, but I think the postal company lost one of my packages that had the parts for it😭 The modules connect with a 2x7 2.54mm header, this way you don't even need to make a pcb to create new modules, just use a pref board, and you can just plug in dupont cables directly into the device. Each module has two resistors, which when connected each become the top resistor of a voltage divider, a 12bit ADC measures the resulting voltages, and loads the correct driver for that module. The firmware is written in rust, in a way so that writing new drivers and apps is really easy, and can be done in external crates. Each app can depend on drivers, and only be loaded into the app list, if all their requirements are met. I tried porting a NES emulator, but there doesn't exist an emulator written in rust currently that actually performs well on this hardware, I got an average of 12FPS in Super Mario Bros. I've collabed with Hack Club, and I will be running a program where if you are a teen 13-18(inclusive) and design 4 modules, you get funding to make these modules and get one of these consoles for free. The program will start on Aug 3 and end on Aug 31. If you want to participate [RSVP] now! (https://meko.fillout.com/hackxpansion). Repo Website(docs WIP) submitted by /u/K0eg [link] [comments]

Based on BrainChip’s Akida neuromorphic engine, the AKD1500 edge AI coprocessor is now available in a compact M.2 2230 (22×30 mm) form factor. The card features a B+M key edge connector for use with Raspberry Pi 5 and compatible host systems, enabling fanless, plug-and-play AI acceleration without redesigning existing power or cooling systems.

Operating from a 3.3-V supply, the AKD1500 M.2 card connects through a two-lane PCIe Gen2 host interface. The coprocessor integrates 32 neural processing units (NPUs) and delivers up to 800 effective GOPS (INT4) for edge AI inference. It also includes 1 MB of dual-port on-chip memory and consumes a typical 250 mW at 400 MHz.

The event-based digital architecture delivers ultra-low-power acceleration for standard neural network models and supports on-device learning, enabling applications to adapt without a cloud connection or full model retraining. Models are developed and optimized using BrainChip’s MetaTF software flow with TensorFlow/Keras and PyTorch front ends before deployment to the card.

The AKD1500 M.2 card with a B+M key connector is priced at $129 and is available for purchase directly from BrainChip.

AKD1500 M.2 product page 

BrainChip Holdings 

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Advantech is launching a portfolio of servers based on AMD EPYC 9006 SP8 processors to support next-generation AI infrastructure. Servers, such as the SKY-924E5F, provide the scalability and reliability required for AI, high-performance computing (HPC), networking, and mission-critical industrial workloads.

EPYC 9006 series server CPUs feature up to 128 Zen 6 or Zen 6c cores, 256 threads, and 2-nm process technology, delivering up to a 20% average performance improvement over the previous generation and up to a 20% performance-per-watt improvement. These processors enable more virtual machines, higher throughput, and improved system efficiency. With up to 128 PCIe Gen6 lanes per CPU, CXL 3.1 memory expansion, and support for DDR5-8000MHz and MRDIMM-12800MHz, the EPYC-powered servers provide balanced compute, memory, and I/O performance.

The edge servers support GPU-accelerated AI workloads and AFA-ready high-density E1.S/E3.S NVMe SSD storage. The lineup includes the following models:

• SKY-642E5, 4U MGX GPU server for large-scale AI acceleration
• SKY-722E5, 2U DC-MHS server with DC-SCM capability for modular data center and edge AI deployments
• SKY-712E5, 1U DC-MHS server with HHHL and FH-3/4L expansion card compatibility for high-density enterprise edge and cloud workloads
• SKY-822E5, 2U short-depth DC-SCM modular server accommodating 2–3 dual-slot GPU cards for space-constrained edge data centers
• SKY-924E5F, 2U 4-node front-access server for distributed edge computing
• ASMB-982 and ASMB-832, server boards for flexible, expandable system designs

A timeline for server availability was not provided at the time of this announcement. Learn more about the Advantech + AMD EPYC 9006 platform here.

Advantech

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Optimized for physical AI, AMD’s Ryzen AI Embedded X100 series processors combine CPU, GPU, and NPU resources on a single embedded SoC. With up to 16 AMD Zen 5 CPU cores, an integrated GPU, power-efficient NPU, and unified memory, the processors handle perception, reasoning, and real-time control workloads in robotics, industrial automation, aerospace and defense, and other embedded systems.

AMD says the series delivers up to 2.1× higher multithreaded CPU performance, 1.7× higher graphics performance, and 3.5× higher AI token generation with 1.4× faster time-to-first-token than Intel Core Ultra Series 3 processors. The company also says the processors provide up to 3× higher peak FP32 performance than the NVIDIA Jetson T5000 and an average 1.7× faster beamforming for cardiac ultrasound than the NVIDIA RTX 4000 Ada.

The Ryzen AI Embedded X100 series supports an open software stack with Linux, the AMD ROCm GPU software stack, the Xen Hypervisor, and AI frameworks including PyTorch, ONNX, and TensorFlow. AMD also provides tools to migrate CUDA codebases to ROCm.

Production availability of the Ryzen AI Embedded X100 series is expected in Q4 2026. Learn more about the processors on the product page or in AMD’s technical blog.

Advanced Micro Devices 

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Advanced Energy’s AIH03ZPFC power factor correction (PFC) converter delivers 1100 W of output power in a half-brick form factor. The board-mount module achieves up to 97.3% peak efficiency and a power density of 380 W/in³. According to the company, this represents a 2.3% improvement in efficiency and a 44% increase in power density over its previous-generation PFC devices.

The AIH03ZPFC integrates features that enhance functionality in a small half-brick design, including internal inrush limiting, digital PMBus control and monitoring, and auxiliary power support for external housekeeping functions. These capabilities make the converter well suited for industrial, medical, defense, and telecommunications systems with demanding size and efficiency requirements.

The AIH03ZPFC provides a 390-VDC output with 1% load regulation, maintains a unity power factor across an 85-VAC to 264-VAC input range, and requires no power derating under low-line conditions.

Baseplate contact cooling supports operation from -20°C to +100°C, with startup at temperatures as low as -40°C. The encapsulated half-brick package measures 2.4 × 2.3 in. (61 × 58.4 mm) and has an installed height of 0.52 in. (13.3 mm).

AIH03ZPFC product page

Advanced Energy Industries

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Cadence says its AuraStack AI Super Agent is the industry’s first agentic AI platform for PCB and advanced packaging design. Running on the company’s Allegro AI Studio and accelerated by NVIDIA Blackwell GPUs and NVIDIA CUDA-X libraries, the platform coordinates domain-specific AI agents across planning, implementation, and tightly integrated multiphysics analysis. AuraStack joins Cadence’s ChipStack, InnoStack, and ViraStack AI Super Agents, extending the company’s agentic AI portfolio across IC design, advanced packaging, and PCB design.

Built on the same architecture as Cadence’s ChipStack AI Super Agent, AuraStack combines agentic AI with simulation and optimization tools to automate design exploration, implementation, and signoff. An AI-driven multiphysics foundation concurrently models electrical, thermal, and mechanical behavior to support earlier design optimization.

According to Cadence, AuraStack can accelerate time to market by up to 2× and increase productivity by up to 15× while identifying system issues earlier in the design process to help reduce costly respins. It also enables system-level co-optimization with advanced packaging technologies, including CoWoS, to improve product performance and manufacturability.

Cadence plans to make the AuraStack AI Super Agent available in 2026.

AuraStack product page 

Cadence

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As the automotive industry shifts toward software-defined vehicles (SDVs), with features and updates delivered via software, vehicle electrical/electronic (E/E) architectures are evolving. These architectures are moving away from traditional flat and domain-based designs, in which separate control units for each function were the norm, to zonal architectures that group vehicle functions based on various criteria, such as physical location, application group, and other functional criteria in zone electronic control units (ECUs).

In a zonal architecture, each zone of a vehicle, such as front, rear, or cabin, has a high-performance controller managing local devices and communicating with other controllers over high-speed networks. This approach is faster to update, easier to scale, less complex, and even cheaper, but it also presents new technical challenges for automakers to overcome. The good news is that innovative microcontroller (MCU) solutions can help tackle those challenges.

Key challenges in the shift to zonal architectures

Zonal architectures offer clear benefits of reducing wiring complexity and consolidating compute resources.

However, each zone controller in an SDV must handle a wide range of tasks, from low-level real-time control of sensors and actuators (such as sensing braking pressure, steering angle, or controlling window-lift motors) to high-level data processing tasks (including controlling advanced safety systems or vehicle dynamics or running local AI models to process sensor data). This means the ECUs in a zonal design require compute capabilities that can handle both time-sensitive and compute-intensive workloads concurrently.

Maintaining freedom from interference among functions is a key challenge. Zonal designs consolidate diverse functions, from safety-critical functions such as braking to non-critical functions such as body control on a single ECU with shared compute and communication resources. Without proper safeguards, a fault in one function could disrupt others.

To prevent this, robust isolation mechanisms such as hardware-enforced separation are needed. Ideally, these features should be embedded in the hardware design rather than software implementation to minimize the impact on performance, behavior, or safety.

In-vehicle networks also need rethinking. Modern SDVs generate massive amounts of data from sensors and devices, including cameras, LiDAR, and radar, to support advanced driver-assistance and autonomous-driving features. The vehicle network must ensure that this data is delivered in a predictable and time-sensitive manner.

Traditional in-vehicle networks such as CAN, LIN, and FlexRay struggle to meet these demands at the scale of the modern SDV. Moreover, Ethernet is increasingly used in vehicles for its advantages in performance, reliability, and connectivity options, and at the same time, many legacy devices in the vehicle still use CAN or LIN.

To ensure network performance and avoid communication bottlenecks, next-gen vehicle controllers should include native support for Ethernet and CAN networking on-chip. A well-architected MCU will also enable sufficient control and acceleration features to reduce latency and ensure predictable message delivery, ultimately resulting in deterministic communications at the vehicle level.

Next-generation automotive MCUs need to adopt improved, low-latency architectures and design philosophies to overcome key challenges in the shift to zonal architectures. (Source: NXP Semiconductors) Making updates secure, easy, and fast

A hallmark of SDVs is the ability and the need to receive secure over-the-air (OTA) updates throughout the vehicle’s life. This contrasts with traditional vehicle designs with dozens of ECUs for which updates are complex, time-consuming, and often performed only in service environments.

For an SDV built on a zonal E/E architecture, software updates can be pushed to a selected number of controllers that can be responsible for the software of an entire region of the vehicle, such as the front zone or the rear chassis zone. To support these frequent updates with minimal downtime, embedded nonvolatile memory (eNVM) needs to be upgraded as well to a more versatile option with much faster write speeds and higher endurance.

How modern MCUs lay the foundation for next-gen SDVs

Next-generation automotive MCUs need to adopt improved, low-latency architectures and design philosophies to overcome these challenges. Rather than relying on a homogeneous architecture, the implementation of heterogeneous cores optimized by functions is required.

The NXP S32K5 MCU, for example, integrates different kinds of CPU cores complemented by various accelerators for dedicated functions such as AI/ML, signal processing, and network acceleration, enabling designers to assign the right function to the right core. Furthermore, a dedicated low-power engine is available for simple tasks, such as periodic wakeups and sensor monitoring, which can help optimize battery life in electric vehicles.

The integration of multiple functions of mixed criticality warrants robust mechanisms to ensure freedom from interference. The S32K5 lives up to this challenge by implementing features such as XRDC, an in-house NXP IP for isolation and resource allocation in hardware from pin to core.

Moreover, dedicated network accelerators need to be implemented for CAN2CAN (communication between CAN networks) and CAN2ETH (communication between CAN and Ethernet networks) acceleration to ensure deterministic and low-latency architectures.

In addition, integrating an Ethernet switch with fast data-routing capabilities ensures that the latest-generation Ethernet vehicle architectures can achieve latency requirements with minimal CPU load.

With an embedded MRAM as the eNVM, the S32K5 offers write speeds that are 15× faster than conventional eFlash. Write without erase and endurance of 1M write cycles of MRAM helps optimize costs, simplify software development, and minimize downtime for the frequent OTA updates expected in an SDV architecture.

Building the foundation for next-gen SDVs

Zonal architectures are emerging as a necessity for next-gen vehicles because they align with the needs of SDVs. They concentrate compute, reduce complexity, and enable new, software-driven experiences. With the latest generation of MCUs as the building blocks, automakers now have more tools to develop zonal vehicle architectures to deliver the high performance, reliability, and flexibility required by next-gen vehicles.

The post Accelerating the shift to next-gen SDVs with zonal MCUs appeared first on EDN.

Self-heated Darlingtion transistor pair linearly senses airflow using just two wires for both power in and signal out.

Suppose we take a common TO-92 transistor and heat it to a constant temperature differential above ambient.  The power input required to keep it there will be determined by its thermal impedance ZT relative to the surrounding air. This suggests it might be handy for air flow measurement.  Maybe even moreso if it needed only a simple two-wire connection for both (phantom) power supply from, and signal delivery to, the supporting electronics.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Please see the Related content listings below for a more detailed treatment of the subject.  Figure 1 graphs the resulting power vs air speed relationship.  Unfortunately, it’s badly bent.

Figure 1 This graph logs power dissipated vs air speed of a TO92 held at a constant 31oC above ambient. Pw = 31/ZT.

Figure 2 shows a practical thermostat circuit to achieve and maintain the delta-T while outputting a signal predictably related to Pw.  It utilizes a Darlington sensor transistor pair (Q1 and Q2) to compensate for ambient temperature and convert the resulting nonlinear Pw curve into a linearized airflow readout.  Its current mode, phantom-power output is compatible and convenient for the long cable runs often seen in airflow measurement applications.

Figure 2 This circuit implements a phantom-powered Darlington anemometer with a 40-140 mA current mode output.  Adjust R10 to calibrate 40 mA (zero fpm), and R11 to calibrate 140 mA (250 fpm). The adjustments interact so some iteration may be necessary.  Sorry ‘bout that.

Q1 serves as the self-heated sensor with Q2 providing ambient temperature compensation.  Opamp A2 runs a feedback loop that forces a constant Vbe differential between Q1 and Q2.  This establishes a constant 31oC temperature differential between Q1 and ambient.  It does this (with the help of Darlington current gain) by forcing Q1’s current draw (I) through R3 to drive Q1’s power dissipation (Pw) to follow the Figure 1 curve of heat-vs-air flow.

Okay so far.  But how does compensation for Figure 1’s nonlinearity happen?   Well, happily the function of Q1’s Pw vs collector current I isn’t linear either.  In fact Pw = 5vI – I2R3.  That quadratic I2 term is the key.  It creates the lovely linearizing curve shown in Figure 3.

Figure 3 This graph logs Q1 power dissipation vs  collector current.  Pw = 5vI – I2R3.

The 2nd-order curvature of fig. 3 irons out (most of) the bend in Figure 1 and results in a linear 33 to 125 mA current draw over the 0 to 250 fpm flow rate range. Although the match isn’t perfect, when converted to the 40 to 140 mA by opamp A1 and output transistor Q4, the realized output is a calibrated readout of air speed that differs from ideal by less than +/- 5% from 0 to 250 fpm, as shown in Figure 4.

Figure 4 This graph logs anemometer output vs airspeed. FPM = 2.5(Iout – 40mA).

Note that most (~90%) of the output current is actually drawn by inverted regulator U1 as it maintains a constant 5v across the (thirsty) thermal transistors.  All that’s left for A2 and Q4 is to conduct several mA of shim current to establish and maintain calibration, which barely gets Q4 warm.  U1, however, can be called on to dissipate about three quarters of a watt and thus should be bundled in a TO220 or similar package.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Self-heated Darlington transistor pair comprises new air flow sensor
• Linearized portable anemometer with thermostated Darlington pair
• Nonlinearities of Darlington airflow sensor and VFC compensate each other
• Improve thermal airflow sensor PSRR with just two resistors
• A groovy apparatus for calibrating miniature high sensitivity anemometers

The post Phantom-powered solid-state linear airflow sensor appeared first on EDN.

Ather Energy has begun rolling out Pothole+ Alerts to customers with Gen 2 and above scooters, including the Ather 450 Apex, 450X and Rizta Z. The feature alerts riders to potholes, broken road patches, uneven roads and speed breakers ahead while navigating, using road intelligence built from data generated by Ather’s connected scooter fleet.

Announcing the rollout on X, Ather Co-founder and CEO Tarun Mehta said the feature has been nearly nine years in the making. “The challenge was never the idea. It was the data,” Mehta wrote, noting that Ather’s growing connected fleet has now generated the scale of road intelligence needed to make the feature a reality.

Every Ather scooter is equipped with onboard compute and connectivity, enabling the company to build large datasets over time and develop software-driven features for its customers. According to Mehta, Pothole+ Alerts is one of the strongest examples of how Ather is leveraging connected vehicle data to enhance the riding experience.

When using navigation, riders will receive alerts for potholes, broken road sections, uneven surfaces and speed breakers ahead. Notifications are displayed on the scooter dashboard and can also be heard through the scooter, the Ather Halo smart helmet or any compatible Bluetooth headset, allowing riders to stay informed without taking their attention off the road.

The rollout reflects Ather’s continued focus on building connected features powered by real-world riding data. Mehta added that Pothole+ Alerts is just the beginning, with the company planning to build more rider experiences on top of its growing road intelligence dataset.

The post Ather Energy Begins Rollout of Pothole+ Alerts to Gen 2 and Above Scooters appeared first on ELE Times.

Skyworks Solutions Inc of Irvine, CA, USA and Qorvo Inc of Greensboro, NC, USA have announced the expected executive leadership team for the combined company, effective upon completion of the pending transaction...