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Mouser Electronics has expanded its stock of Nordic Semiconductor products with development and evaluation kits for the nRF54L15 and nRF54LM20 Bluetooth Low Energy SoCs, the nRF9151 cellular IoT system-in-package, and the nPM2100 power management IC. Mouser has distributed Nordic products since 2011.

nRF54L15 development kit

The nRF54L15 DK is an evaluation and prototyping platform for the nRF54L Series of Bluetooth Low Energy (BLE) wireless SoCs. It supports the full BLE feature set as well as other common communication protocols, and is intended for applications such as Industrial IoT (IIoT), augmented and virtual reality (AR/VR), asset tracking, and smart home products.

nRF54LM20 development kit

The nRF54LM20 DK supports application development for the nRF54LM20A and nRF54LM20B wireless SoCs. It is a low-cost, single-board kit that gives access to all SoC features, backed by the software examples, modules, and libraries in the nRF Connect SDK.

Both SoCs support Bluetooth LE, Bluetooth Mesh, Matter, Aliro, Thread, Zigbee, and proprietary 2.4 GHz protocols (up to 4 Mbps), plus High-Speed USB. The nRF54LM20B also integrates an Axon neural processing unit (NPU) that accelerates edge AI workloads such as health, biometric and activity monitoring, voice control, audio classification, and low-fidelity vision.

nRF9151 SMA development kit

The nRF9151 SMA DK is designed for in-depth evaluation of the nRF9151 LTE-M/NB-IoT system-in-package (SiP), which also supports DECT NR+ and GNSS. Its SMA connectors allow direct connection to lab instruments for conducted measurements, or to external antennas for field testing. A beta modem firmware adds support for NB-IoT NTN (satellite communication).

The kit includes antennas from Taoglas (cellular/NTN) and Kyocera (GNSS), and IoT SIM cards from Deutsche Telekom, Onomondo, and Monogoto.

nPM2100 evaluation kit

The nPM2100 EK allows no-code configuration of the nPM2100 PMIC, which is designed for low-power devices running on non-rechargeable (primary) batteries. The PMIC includes a boost regulator with automatic pass-through mode, allowing batteries to be used down to their functional end point.

With the EK connected to a PC, all PMIC settings can be configured and exported as code for direct integration into the host microcontroller application. The kit comes with six interchangeable battery holders covering a wide range of primary cell configurations.

Availability

The kits are available from Mouser. The Nordic Semiconductor products stocked by Mouser are listed on the Nordic Semiconductor manufacturer page.

The post Mouser stocks Nordic nRF54L, nRF9151, and nPM2100 development kits appeared first on Open Electronics.

ROHM has developed a fourth generation of 650 V IGBTs for automotive electric compressors and HV heaters, and for inverters in industrial equipment. The devices reach a collector-emitter saturation voltage of VCE(sat) = 1.55 V, which ROHM reports as the lowest conduction loss among 650 V automotive devices*, while offering high short-circuit tolerance and qualification to the AEC-Q101 automotive reliability standard (Fig. 1).

Application context

As electric vehicles move to higher voltages, SiC devices are increasingly used in high-power applications such as traction inverters. 650 V IGBTs, meanwhile, remain widely used as switching devices in lower-power auxiliary systems, including automotive electric compressors and HV heaters. Silicon IGBTs are also common in industrial equipment, particularly in motors and compressors, and demand is expected to keep growing.

These applications call for energy savings and smaller equipment, and therefore for power devices with higher reliability, smaller size, and higher efficiency. Heater and inverter circuits in particular need enough short-circuit tolerance to withstand a fault for the time required to detect and interrupt the overcurrent.

Device design

ROHM revised the device structure, including the manufacturing process and the edge termination structure, to combine low loss with high short-circuit tolerance while meeting higher voltage requirements. The new structure increases current density and reduces both conduction and switching losses. Despite the trade-off between lower loss and short-circuit tolerance, the devices guarantee a short-circuit withstand time of 7 µs at Tj = 25 °C.

Lineup and availability

The lineup includes 12 products in the TO-247N package, the RGAxxTS65HR and RGAxxTS65EHR, and 10 bare-die products, the SG83xxWN series. ROHM is also developing 12 products in the TO-247-4L package, the RGAxxTR65HR/RGAxxTR65EHR series.

All packaged devices share a collector-emitter voltage of 650 V, a short-circuit withstand time of 7 µs at Tj = 25 °C, an operating junction temperature of -40 °C to +175 °C, and AEC-Q101 qualification. The -HR versions have no built-in diode; the -EHR versions integrate a fast recovery diode. The TO-247N package measures 16.0 × 21.0 × 5.0 mm, the TO-247-4L 16.0 × 23.45 × 5.0 mm.

TO-247N (available)TO-247-4L (under development)IC (TC = 100 °C)VCE(sat) typ.

RGA60TS65HR / RGA60TS65EHR	RGA60TR65HR / RGA60TR65EHR	35 A	1.55 V
RGA80TS65HR / RGA80TS65EHR	RGA80TR65HR / RGA80TR65EHR	44 A	1.55 V
RGA00TS65HR / RGA00TS65EHR	RGA00TR65HR / RGA00TR65EHR	52 A	1.55 V
RGAX2TS65HR / RGAX2TS65EHR	RGAX2TR65HR / RGAX2TR65EHR	62 A	1.55 V
RGAX5TS65HR / RGAX5TS65EHR	RGAX5TR65HR / RGAX5TR65EHR	74 A	1.60 V
RGAY0TS65HR / RGAY0TS65EHR	RGAY0TR65HR / RGAY0TR65EHR	88 A	1.65 V

Packaged 650 V IGBTs: -HR without diode, -EHR with built-in fast recovery diode.

The bare-die devices are rated at 650 V with a typical VCE(sat) of 1.55 V and a short-circuit withstand time of 7 µs; all chips are 75 µm thick.

Bare dieIC (TC = 100 °C)Chip size X × Y (mm)

SG8351WN	20 A	3.08 × 3.08
SG8352WN	25 A	3.10 × 3.48
SG8353WN	30 A	3.52 × 3.52
SG8359WN	40 A	3.74 × 4.10
SG8355WN	50 A	4.20 × 4.39
SG8356WN	60 A	3.90 × 5.48
SG8358WN	75 A	4.50 × 5.70
SG8357WN	100 A	5.70 × 5.70
SG8360WN*	150 A	6.82 × 6.82
SG8361WN*	200 A	7.75 × 7.75

* Under development.

The TO-247N products and some of the bare-die products are available now, and the TO-247N parts are sold through online distributors including DigiKey and Farnell. ROHM plans to add more products in the same packages and to develop compact surface-mount IGBTs in the TO-263L package and in top-side cooled (TSC) packages.

Applications

• Automotive electric compressors
• Automotive HV heaters (PTC heaters, coolant heaters)
• Inverters for industrial equipment

Design support

ROHM’s website provides SPICE models that reproduce the electrical characteristics of the devices in simulation, PLECS models for circuit simulation, and other circuit design material. More information is available on the field-stop trench IGBT product page.

EcoIGBT is ROHM’s IGBT brand for devices and modules aimed at high-voltage power applications. EcoIGBT is a trademark or registered trademark of ROHM Co., Ltd.

*ROHM research, August 2026.

The post ROHM fourth-generation 650 V IGBTs with 1.55 V VCE(sat) and AEC-Q101 appeared first on Open Electronics.

Cambium Networks has introduced cnMaestro MarketApps Hub, an open marketplace of web apps built to extend cnMaestro, the company’s centralized network management system. The hub turns a Cambium ONE network into an application platform: network operators, MSPs, site managers, and end users can run the workflows they need, and anyone able to call the cnMaestro APIs can develop and publish apps. According to Cambium, AI coding tools and an AI-ready development platform make it possible to build custom apps in hours or days.

An open marketplace with defined responsibilities

MarketApps Hub extends Cambium’s existing MarketApps framework into a governed app ecosystem, with a public catalog, a developer SDK, single sign-on (SSO), app hosting, and platform-level security. It is built on the public cnMaestro APIs and on a developer experience designed for AI coding agents. Apps are hosted and secured on the platform, and can be written by anyone from Cambium engineers to the customers who operate the network every day.

Bruce Miller, VP of Enterprise Marketing at Cambium Networks, said that AI has turned domain experts into developers, and that a purpose-built app that once took an engineering team a quarter to build can now be created in hours or days. In his view, the hub gives these developers a marketplace and gives customers functions tailored to their vertical market and workflow.

Five app classes

Every app in MarketApps Hub belongs to one of five classes, which tell customers where it comes from and how it is supported:

• Certified: production-grade apps developed, tested, hosted, and fully supported by Cambium.
• Labs: the fast track. Apps are released quickly and shaped by customer feedback, and those that prove themselves move to Certified.
• Partner: apps developed and supported by Cambium partners.
• Community: open contributions from the developer community.
• Private: apps exclusive to a single customer account, with that customer’s data and network.

Apps can move up to a higher class as adoption shows demand, so a community idea can become a Certified app or a native cnMaestro feature.

Development and distribution

Cambium’s position is that AI has made writing apps easier, and that the harder part is now hosting, securing, and distributing them to the right audience with adequate support. MarketApps Hub addresses this with platform hosting, SSO, a public catalog, and controlled distribution through the five app classes.

The MarketApps developer platform is designed for AI coding agents. A quick-start guide provides boilerplate code, an SDK, and a live cnMaestro development environment with a single command, and a single pull request publishes an app globally.

Because apps are delivered as plain web applications that run on mobile devices or in any browser, they can serve users outside the network team, such as a resident configuring personal Wi-Fi, a site manager overseeing a location, or a technician installing equipment, without requiring a cnMaestro account.

The post Cambium Networks launches MarketApps Hub, an app marketplace for cnMaestro appeared first on Open Electronics.

Mouser Electronics has launched a digital resource center dedicated to consumer technology. It collects material on emerging technologies, reference designs, and implementation guidelines for engineers developing connected consumer products.

Design topics

As consumer devices become more portable, intelligent, and interconnected, designers have to provide seamless connectivity and adaptive user experiences. The resource center covers several of these design priorities:

• USB Type-C® charging and power management systems, which enable faster charging and simpler connectivity
• AI-based ambient systems built on sensors and contextual processing, which make devices more adaptive and responsive
• Physical buttons, which are seeing renewed interest for tactile, distraction-free interaction, while touch and voice interfaces continue to spread

Content

The center was curated by Mouser’s technical team and its manufacturer partners, and includes articles, blogs, eBooks, and new products for consumer technology design. It also features the latest episode of Mouser’s Empowering Innovation Together (EIT) series, Engineering AI for Daily Life, which looks at emerging AI technologies and their practical uses in consumer products, including voice assistants, AI-based travel planning tools, and wearables that provide more detailed health information.

Featured products

The new consumer-oriented products stocked by Mouser include:

• STMicroelectronics LSM6DSV320X: a 6-axis inertial measurement unit (IMU) that combines an accelerometer and a gyroscope in a compact, low-power package. It integrates activity tracking, gesture recognition, and context detection, and targets wearables, AR/VR systems, and smart devices.
• Molex Premo-Flex SlimStack jumpers: flexible flat cable (FFC) and flexible printed circuit (FPC) jumpers that provide high-density, flexible interconnects for compact, lightweight consumer electronics. Their thin profile helps optimize the internal layout of smartphones, tablets, wearables, and portable devices, and simplifies wiring in tight spaces while preserving signal integrity.
• Littelfuse SC3402-02ETG: an ESD protection diode that protects sensitive consumer electronics from electrostatic discharge and transient voltage events. It is designed for high-speed interfaces and compact applications, and its small footprint suits mobile devices, wearables, and other space-constrained equipment.
• TE Connectivity 0.8 mm low-profile IDC connector system: compact, high-density board-to-board and wire-to-board connections for consumer electronics. The low profile helps reduce device thickness while carrying data and power, and the system is designed for automated assembly.

The post Mouser opens a consumer technology resource center appeared first on Open Electronics.

Taoglas, a supplier of antennas and RF solutions, has completed the acquisition of Wireless Instruments Sp. z o.o. (“QuWireless”), a company that designs antennas and antenna-enclosure systems for wireless communication devices. The deal extends Taoglas’s capabilities in outdoor and industrial connectivity, where demand for rugged solutions for harsh environments is growing.

Router inside the antenna enclosure

Based in Poland, QuWireless develops integrated “all-in-one” products in which the router is installed directly inside the antenna enclosure. Enclosures are available for all major brands of industrial routers: the installer inserts and secures the router in the enclosure, leaving a single unit to mount.

With significantly less RF cabling, this type of installation can also improve signal strength and reliability in settings such as:

• industrial sites
• telecom network infrastructure
• smart grids
• transport systems
• building rooftops
• remote locations and areas with limited network coverage

Combined portfolio

Taoglas says that adding QuWireless’s antenna and enclosure expertise to its own RF and antenna design, engineering, global testing, and certification capabilities will shorten development cycles and make field performance more predictable. The combined portfolio covers a wider range of supported devices, frequency bands, and form factors.

The acquisition comes as demand for wireless connectivity in outdoor, industrial, and remote environments grows with the expansion of 5G, private networks, and IoT deployments.

“Much of the challenge today isn’t just RF performance; it’s getting reliable, robust connectivity deployed quickly, with controlled installation costs, especially outdoors,” said Dermot O’Shea, CEO of Taoglas. “Their antenna enclosures remove much of that complexity and significantly reduce installation time.”

Deal terms

QuWireless will operate as “QuWireless, a Taoglas company”, and its product portfolio will initially continue under the QuWireless brand. The team will remain in Poland as a center of excellence for antenna-enclosure design, working with Taoglas’s global engineering teams.

According to Michal Gorzad, CEO of QuWireless, joining Taoglas will allow the company to bring its designs to a much wider market and integrate them with a broader range of RF technologies.

Financial terms of the transaction were not disclosed.

The post Taoglas acquires QuWireless, maker of outdoor antenna enclosures appeared first on Open Electronics.

Mouser Electronics now stocks the ESP32-P4X-EYE, a vision development kit from Espressif Systems designed for camera-based applications such as smart surveillance cameras, detection with vision models, and edge computing in IoT systems.

A development kit shaped like a small camera

The ESP32-P4X-EYE comes in a mini digital camera form factor: a compact camera-style enclosure houses the camera module, with a 1.54-inch SPI LCD on the back, a digital microphone, a rotary encoder, and a push button. The kit is intended for real-time image processing in AI, edge computing, human-machine interface (HMI), and camera applications.

With the camera, display, microphone, and microSD card on board, the kit can monitor its surroundings in real time and collect image and audio data.

Main features

• SoC: Espressif ESP32-P4 with a 400 MHz dual-core RISC-V processor
• Memory: support for up to 32 MB of PSRAM
• Interfaces: USB 2.0, MIPI-CSI/DSI, and several other peripherals
• Video: H.264 encoder
• Display: 1.54-inch SPI LCD on the back of the enclosure
• Audio: digital microphone
• Controls: rotary encoder and push button
• Storage: microSD card
• Wireless: ESP32-C6-MINI-1 module with Wi-Fi, IEEE 802.15.4, and Bluetooth LE

Wireless module

Wireless communication is handled by Espressif’s ESP32-C6-MINI-1 module, which supports Wi-Fi, IEEE 802.15.4, and Bluetooth LE and is designed for applications including smart home, industrial automation, healthcare, and consumer electronics. The module has an on-board PCB antenna.

Developers can also connect external peripherals to the ESP32-P4X-EYE using jumper wires.

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Inspired by PocketPD, I created a pocket-sized programmable power supply built on the USB Power Delivery (PD) standard and the USB Programmable Power Supply (PPS) feature. The main goal was to learn new skills while working on something that can be useful in the future. Key features: Single firmware supports AP33772 and AP33772S PD sink ICs Support for fixed PDO and PPS profiles Operating voltage range: 3.3V to 21V Output current up to 5A (charger and cable dependent) User-switchable output Programmable current limit: 250mA/Step with AP33772S 100mA/Step with AP33772 Programmable condtant voltage: 100mV/Step with AP33772S 20mV/Step with AP33772 Short-circuit protection Input/output TVS protection OVP, OCP and OTP 3D printed case More details: Project logs Github repo submitted by /u/denikty [link] [comments]

Vertiv, a critical digital infrastructure company, plans to expand its manufacturing and testing operations in Ireland and the North West. The company cites growing global demand for infrastructure supporting artificial intelligence (AI), colocation, and hyperscale data center deployments.

Planning application in Letterkenny

Vertiv will submit a planning application to Donegal County Council for an additional 7,000 m² at its Letterkenny site, supporting the planned creation of up to 300 new jobs in the region.

The company’s existing presence in Ireland and the North West includes manufacturing facilities in Letterkenny, Burnfoot, and Campsie (Derry), a Central Procurement Office in Limerick, and a sales and service office in Dublin. Vertiv is currently hiring at these locations to support ongoing organic growth.

Hiring and technical scope

Since the beginning of 2026, Vertiv has added more than 500 employees at its local sites and continues to recruit for engineering and operations roles. According to the company, the new staff will increase production capacity and expand its technical expertise in power, cooling, and industrialized infrastructure solutions, supporting faster deployment of AI, data center, and critical industrial infrastructure worldwide.

“As demand for critical digital infrastructure continues to rise, we are supporting customers as they deploy AI and data center capacity around the world,” said Paul Ryan, president of Vertiv in Europe, Middle East and Africa (EMEA).

Government support

The proposed project is supported by the Irish Government through IDA Ireland. Taoiseach Micheál Martin described the decision as good news for the region and for Ireland, while Peter Burke TD, Minister for Enterprise, Tourism and Employment, said the project underlines the role of the Irish facilities in Vertiv’s global manufacturing network.

Michael Lohan, CEO of IDA Ireland, pointed to the expansion as an example of global companies growing high-value operations from regional locations in Ireland.

The post Vertiv plans 7,000 m² expansion at Letterkenny with up to 300 new jobs appeared first on Open Electronics.

In a case study, Yokogawa describes how Integrated Optics, a Lithuanian manufacturer of lasers and photonics products, uses the AQ6373E optical spectrum analyzer to characterize its ultra-compact visible lasers during development and in production.

Visible lasers are used where spectral quality, stability, and repeatability matter: microscopy, spectroscopy, flow cytometry, quantum technologies, and LiDAR. In these applications even low-level unwanted spectral components can affect measurement accuracy and system performance, so accurate spectral characterization is needed throughout development and manufacturing.

MatchBox laser platform

Integrated Optics builds ultra-compact laser sources for scientific and industrial customers. Its MatchBox platform is a configurable family of continuous-wave, multi-wavelength, and pulsed lasers designed for integration, combining optics, control electronics, and thermal stabilization in a matchbox-sized housing.

The challenge: detecting weak spectral modes

A key problem for the company is detecting weak spectral modes and other low-level components close to the main laser line. Although much weaker than the dominant emission peak, these components can indicate unwanted laser behavior or reduced spectral purity. For both product development and production quality control, Integrated Optics needed an optical spectrum analyzer with wide wavelength coverage, high wavelength resolution, good sensitivity, and good close-in dynamic range, together with fast and repeatable measurements.

The AQ6373E optical spectrum analyzer

The company chose the Yokogawa AQ6373E optical spectrum analyzer, which covers wavelengths from 350 nm to 1200 nm. The instrument is used in single-mode laser production, spectral filtering, component characterization, quality checks, and new product development. Its close-in dynamic range of about 60 dB lets engineers separate weak spectral modes from the dominant laser peak and assess spectral purity, and so verify that each laser meets the requirements of its scientific or industrial application.

The analyzer’s sensitivity also allows measurements at relatively low optical input levels, which simplifies test setups in production. Because Integrated Optics’ lasers include control electronics and thermal stabilization, precise spectral calibration is needed to maintain performance and stability over a wide temperature range. The AQ6373E’s connectivity options support automated calibration and validation workflows, and its wavelength range lets the company use a single instrument platform across its portfolio of visible and near-infrared lasers.

The customer’s view

Evaldas Pebreza, CEO of Integrated Optics, describes the AQ6373E as a telecom-grade instrument whose performance suits laboratory laser measurements: the company gets the reliability typical of telecom equipment together with the resolution and sensitivity needed to characterize more demanding laser sources.

Results

With the AQ6373E, Integrated Optics performs fast, accurate, and repeatable measurements, identifies weak spectral components, verifies spectral purity, and evaluates new laser designs. The main benefit for the company is greater confidence that each laser meets customer requirements, both in production quality control and in the development of compact laser sources for medical, scientific, industrial, and quantum applications.

The full Integrated Optics case study is available from Yokogawa.

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SentinelOne has expanded its collaboration with Amazon Web Services (AWS) to provide unified AI governance for customers using Amazon Bedrock. The new integration combines SentinelOne’s AI runtime security with Amazon Bedrock AgentCore, so security teams can monitor, manage, and mitigate AI-related risks from a single platform. The stated aim is to narrow the gap between how fast companies deploy AI agents and how fast security teams can protect them.

The AI governance problem

As organizations deploy more AI agents, security teams need to see what those agents do, which data and applications they access, and whether that activity complies with governance requirements. In June 2026, SentinelOne and AWS addressed the first part of this problem with an integration between SentinelOne’s Prompt Security and Amazon Bedrock AgentCore, which added runtime protection to the Amazon Bedrock AgentCore gateway.

From guardrails to governance

The new integration goes beyond runtime guardrails and adds a governance layer for enterprise AI, with four functions:

• AI usage governance: visibility into how AI is used across the organization, both sanctioned and unsanctioned.
• Policy enforcement: real-time enforcement of AI usage policies on AWS and in multi-cloud environments.
• Threat detection: detection and root cause analysis of AI-related security risks.
• Automated remediation: automatic correction of misconfigurations and non-compliant AI code.

The governance layer connects Prompt Security, Singularity Cloud Security, and Singularity AI SIEM in a single platform on Amazon Bedrock, including AgentCore, with machine-speed policy enforcement, threat detection, and autonomous response across the customer’s AI environment.

SentinelOne’s view

According to Melissa K. Smith, SVP, Global Strategic Partnerships and Initiatives at SentinelOne, security teams want real-time visibility into what their AI agents are doing. The integration provides that visibility inside the workflows customers already run on AWS, so that security teams get answers immediately instead of reconstructing them afterwards.

Availability

The integration extends SentinelOne’s Prompt Security and Singularity AI Runtime offerings for companies building on AWS, and strengthens the partnership with AWS, including distribution through AWS Marketplace and joint commercial initiatives. Prompt Security, Singularity Hyperautomation, and SentinelOne AI SIEM are already available on AWS Marketplace. Full availability of the unified AI governance system is expected at AWS re:Invent 2026, at the end of November.

The post SentinelOne expands AWS integration for AI governance on Amazon Bedrock appeared first on Open Electronics.

TDK Corporation has introduced the TDK-Lambda DDSM series, programmable isolated DC-DC converters rated at 120 W and 240 W with wide input and output voltage ranges. The converters can be controlled and monitored remotely in real time via Modbus over USB, using the PowerCMC control and monitoring center. A digital display shows device settings, system alarms, and status information, and the unit can also be operated manually with three buttons on the front panel.

A wide conversion ratio

The DDSM series was designed for a wide conversion ratio. Typical uses include improving voltage stability over long cable runs, stepping up the voltage to support a system load, providing an independent isolated voltage for Power over Ethernet (PoE) requirements, and powering loads that need special operating voltages. Because the input and output ranges are wide, one model can replace several part numbers in stock.

Input, output, and efficiency

The converters accept a nominal input of 12 V to 48 V (10.8 V to 52.8 V maximum range) and deliver a nominal output of 5 V to 55 V (4.7 V to 57 V maximum range). Efficiency under standard conditions is up to 93.0%, which reduces internal heat losses and saves energy in standby. Rated output current is 5 A for the 120 W model and 10 A for the 240 W model. A 24 V/1 A DC-OK signal is accessible from the front panel. The DDSM measures 40.0 mm wide, 116.6 mm deep, and 115.0 mm high, and weighs 500 g.

Safety and EMC approvals

Safety certification covers IEC/EN/UL/CSA 61010-1, 61010-2-201, and IEC/EN/UL/CSA 62368-1 (Ed. 3). The series is CE and UKCA marked under the EU Low Voltage, EMC, and RoHS Directives and UK regulations. The models meet EN 55032 Class B for radiated and conducted emissions and EN 61000-6 for immunity.

Applications

• Factory automation
• General industrial automation
• Semiconductor manufacturing
• Renewable energy generation
• Telecommunications
• Test and measurement

Key features

• Wide input and output ranges
• High efficiency and low standby losses
• Digital control and monitoring
• Front-panel display and programming

Specifications ParameterValue

Series	DDSM
Input voltage range	10.8-52.8 Vdc
Output voltage	4.7-57 Vdc
Maximum output power	120 W or 240 W
Efficiency	Up to 93.0%
Isolation	Input to output: 2200 Vdc
Dimensions (W × D × H)	40.0 × 116.6 × 115.0 mm
Safety certifications	IEC/EN/UL/CSA 62368-1 (Ed. 3), IEC/EN/UL/CSA 61010-1, 61010-2-201

More information is available on the TDK-Lambda DDSM series page.

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As FPGA manufacturing migrates to smaller geometries, the process change has delivered extraordinary gains in density, speed, and power efficiency. However, these gains have come at a cost in terms of single event upset (SEU) sensitivity.

Starting in the mid-1990s, the FPGA industry began experiencing a more noticeable rate of SEU sensitivity in 2D planar transistor architectures. Smaller process geometries require less capacitance to store a given state, so a lower amount of energy can disrupt the stored state. Sensitivity increased proportionally to the geometry shrink.

Moving to tri-gate 3D FinFET geometries at 22 nm helped reduce SEU sensitivity compared to 2D planar, but as tri-gate geometry reduces, SEU sensitivity will continue to increase. A bit flip used to require a direct, high-energy particle strike; now even lower-energy neutrons, alpha particles from packaging materials, or even secondary particles generated within the device substrate itself can trigger bit flips.

The result is an unavoidable increase in SEU susceptibility in FPGAs as process nodes scale smaller and FPGAs are deployed in more applications. Part 1 of this mini-series examines SEU radiation particles and related SEU challenges for FPGA applications that require robustness and predictability in ground-based and terrestrial applications.

Radiation particle types and SEU

A variety of particle types can interact with an FPGA and negatively impact system functionality. These particles differ in mass, charge, and energy strength, and interact with the semiconductor material through distinct physical mechanisms. The following discussion focuses on four particle types that lead to SEUs in FPGAs: heavy ions, protons, neutrons, and alpha particles.

1. Heavy ions

Heavy ions, which are caused by galactic cosmic rays and solar flares, are the most potent SEU-inducing particles for space and high-altitude environments. To a lesser degree they can impact ground-based systems. These particles have a heavy nucleus, high linear energy transfer (LET) values, and a positive charge.

When heavy ions traverse through the silicon substrate, they deposit large amounts of charge in their path, generating free electrons and holes that can disrupt a memory cell’s stored charge. A memory cell is constructed with transistors, and if the accumulated charge added by the heavy ion exceeds the minimum charge required by a cell’s transistor, the memory cell state can switch, resulting in a bit flip. In other words, heavy ions cause bit flips through direct ionization.

Figure 1 Heavy ion striking a planar transistor result in ionization along its path, depositing charge and potentially impacting the transistor state. Source: Efinix

Figure 2 Junction current is induced from charge collection and diffusion over time. Source: Efinix

2. Protons

Protons are a secondary radiation particle caused by cosmic rays and solar flares but are weaker than heavy ions. When cosmic rays hit the earth’s atmosphere, they cause nuclear interactions that produce protons. Proton particles have a lighter nucleus, lower linear energy transfer (LET), and are positively charged.

Although the LET is lower, protons can cause indirect ionization via nuclear reactions with semiconductor material. When protons collide with semiconductor material, they can cause a higher LET secondary ion (known as a recoil ion), which can have enough energy to cause a bit flip.

Protons are abundant in the inner and outer Van Allen radiation belts. The stronger inner belt resides 370 – 620 miles above the earth’s surface. Protons are not considered a significant concern for SEU in ground-based systems.

Figure 3 Proton particle striking silicon substrate shows spallation and generates a recoil ion, which has ionization along its path depositing charge, potentially impacting the transistor state. Source: Efinix

3. Neutrons

Neutrons are another secondary radiation particle created by cosmic rays. Like protons, neutrons are created when cosmic rays hit the earth’s atmosphere and cause nuclear interaction. Compared to protons, neutrons are slightly heavier, have a higher LET, and are neutral in charge.

Neutrons also collide with semiconductor material causing secondary high LET recoil ions, which carry a strong enough charge to cause an SEU. Neutrons have also a higher penetration value and can pass through common building materials like concrete.

At commercial aviation altitudes, the number of neutrons in the atmosphere is approximately 300 times higher than at sea level. Although ground-based systems are not as exposed, neutron-induced soft error rates are still a growing concern for data centers and industrial systems operating high-density FPGA arrays.

Figure 4 Neutron particle striking silicon substrate shows spallation and generates a recoil ion, which has ionization along its path depositing charge, potentially impacting the transistor state. Source: Efinix

4. Alpha particles

Alpha particles are a terrestrial particle caused by trace radioactive element decay in silicon packaging materials. Packaging materials contain uranium and thorium in chip packaging and solder bumps. When the trace radioactive element decays, it produces helium nuclei alpha particles.

Alpha particles have a light nucleus, high LET compared to neutrons and protons, and are positively charged. They have a very low penetration value. However, because the packaging materials are very close to the silicon substrate and because of their higher LET, alpha particles can cause SEUs in FPGAs.

Alpha particles in packaging were the original source of DRAM soft errors found in 1978. Since then, manufacturing improvements for packaging materials have helped reduce the probability of high LET alpha particles due to radioactive decay.

Figure 5 Alpha particle emitted from radioactive decay in the package and depositing a charge along its path can impact the transistor state. Source: Efinix

SEU challenges in FPGA architectures

An SEU event can impact several resources within the FPGA architecture, including configuration RAM (CRAM), look-up tables (LUTs), routing, registers, and embedded memory (block RAM). However, a bit flip may or may not impact the design’s functionality.

• In unused resources, a bit flip will not affect the functionality.
• In resources used for non-critical functions (like test circuits, image/video signal processing, or audio data), a bit flip may not impact the design significantly.
• A bit flip in mission-critical systems, like flight control, defense systems, medical systems and energy grid systems, can have serious consequences.

The following subsections describe how SEUs impact the most vulnerable FPGA resources: CRAM, routing, LUTs, registers, embedded memories, and the broader design functionality that depends on their correct operation.

Configuration RAM (CRAM)

From an architecture perspective, SEUs in FPGA CRAM have the most negative consequences. Unlike a processor or ASIC, where logic behavior is fixed in silicon, an FPGA’s function, including routing connections, logic functions, and I/O standard settings, is defined by the CRAM contents. When the FPGA powers up, the CRAM is programmed with a specific bitstream for a specific application.

The function is expected to remain constant. The CRAM controls settings related to routing, LUTs, and configuration of hard IP like transceivers and DDR controllers that are now a part of most FPGA architectures. CRAM SEUs are persistent compared to data path storage elements and can go undetected without built-in detection circuits.

Routing

FPGA routing connects logic, embedded memory, set/resets, and I/O to and from the programmable fabric. A high percentage of the CRAM is dedicated to routing.

A flipped routing bit could lead to a disconnect on a signal path, set/reset path, or clocking path where clock trees are more flexible via configuration of the FPGA. In addition to disconnects, a routing upset could unintentionally merge two independent signal nets, resulting in driver contention, illegal voltage logic levels, and logic corruption.

LUTs

LUTs are an FPGA’s fundamental logic primitive, each implementing an arbitrary Boolean function of four to six inputs. The truth table values are stored in CRAM. Compared to routing, a lower percentage of the CRAM is dedicated to programming the LUTs.

An SEU in CRAM that impacts an LUT alters the truth table and can result in unanticipated results for a specific input state. For example, in a 4-input LUT, inputs of 1010 may be configured to output a 1. An LUT bit flip at address 1010 results in an output of 0, which could be a similar result for another combination of inputs, resulting in a missed condition or trigger, or incorrect control state calculation.

An unexpected bit flip can result in logic that enables an external I/O tri-state, or changes a voltage setting, drive strength, or termination, resulting in external I/O conflicts, poor signal integrity, and potential damage to other board components.

Registers

Registers are fundamental elements within FPGA architecture. They can be used as up/down counters, store control states, store status, and pipeline or buffer data. Registers do not have a persistent state if they are clocked and are not loaded from CRAM. Therefore, a register bit flip can be benign if it’s buffering non-critical data.

The corrupted data may make its way downstream and have no consequences. Incoming correct data to the register is then loaded on the next clock cycle. However, a bit flip in a state machine could put the state machine into an unknown state, freezing the design’s functionality or triggering an unintended action. A status register bit flip could trigger a similarly unwanted action.

Embedded memory (block RAM)

Block RAM is like a register in terms of SEU impact. A bit flip may not persist, depending on the functionality (look-up table, data buffering, or soft processor memory). Block RAM is not loaded from CRAM but can be initialized when you program the FPGA with a bitstream. If not initialized, the block RAM contents are 0 after the FPGA enters user mode.

Block RAM stores values that the design actively reads, writes, and depends upon during normal operation. The consequences of a bit flip depend on the block RAM use. For example, a bit flip can propagate downstream in video, image, or audio buffering applications without harm.

However, a bit flip within a stored soft processor program may have consequences like a control register where the executing software may branch to an unexpected area of code. A bit flip in block RAM that stores DSP coefficients can lead to a computational error that manifests itself as inaccurate results for an AI LLM or persistent unwanted noise in a filter.

SEU impact on FPGA functionality

The cumulative effect of uncorrected SEUs across CRAM, routing, LUTs, registers, and block RAM is a gradual and silent degradation of the design’s integrity. A single SEU could lead to a hard failure immediately but usually it will be unambiguous. Accumulated SEU failures follow a probabilistic profile.

The first upset may be functionally insignificant, the second may alter behavior in a rarely exercised path, and the third may corrupt a critical state register in a way that cascades into a system-level failure. This accumulation without detection or a means to correct it can result in increasing failure probability over time.

Mik Ichiba is principal field applications engineer at Efinix. He is a seasoned semiconductor and embedded systems professional with more than 30 years of experience spanning hardware architecture, PCB design, ASIC development, FPGA architecture, and system-level engineering. Throughout his career, Mik has worked across the hardware design lifecycle, helping organizations translate complex technical requirements into practical, high-performance solutions.

Editor’s Note

This is Part 1 of the mini-series about SEU challenges in FPGA architectures. Part 2 will cover SEU detection, recovery, and validation for FPGA applications that require robustness and predictability in ground-based and terrestrial applications.

Related Content

• Using FPGAs in mission-critical systems
• Rethinking the Logic-Routing Tradeoff in FPGAs
• Understanding Single Event Effects (SEEs) in FPGAs
• Enhancing robust SEU mitigation with 28-nm FPGAs
• Learn about SEU Immunity in Terrestrial FPGA Applications

The post FPGA architecture: Radiation particle types and single event upsets (SEUs) appeared first on EDN.

Lumentum Holdings Inc of San Jose, CA, USA (which designs and makes optical and photonic products for optical networks and lasers for industrial and consumer markets) has announced its speaker line-up for the European Conference on Optical Communications (ECOC 2026) at the Trade Fair and Congress Center in Málaga, Spain (20–24 September)...

This circuit exemplifies the thesis that the 555 is to analog timing what the op-amp is to analog “everything else”.

In any contest to see which is easier to manually program, digital potentiometers (dpots) suffer a big handicap when compared to traditional electromechanical pots.

No knob.

But henceforth, maybe that handicap won’t matter so much. This Design Idea implements a variable frequency oscillator circuit that produces dpot up/down steps. It generates step rates from zero to 20 Hz together with a separate up/down step direction signal. Both are controlled by simply (and quickly) twisting one knob on an inexpensive linear potentiometer (e.g. Bournes PTD90 series) a fraction of a turn.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Voila! There’s that long lost and longed for dpot knob at last! See the Figures that follow for how it works.

Figure 1 Current-to-frequency converter U1 generates dpot clock pulses at 20 Hz-0-20 Hz, controlled by the sum of Q1+Q2 collector currents set 0 to 5 µA by R1. A1 sets the up/down step direction.

0 µA = 0 Hz corresponds to R1’s wiper centered at (or near) the midpoint of travel, and 20 Hz to both its clockwise and counterclockwise limits (Figure 1). Comparator A1 sets the dpot step direction to UP if R1’s wiper is clockwise of midpoint, DOWN for counterclockwise (Figure 2).

Q1 sources the majority of current to U1 for UP steps, and Q2 takes over for DOWN. The Vpp amplitude of the sawtooth waveform on C1 is set by the R7/R8 and 555 internal dividers to ~250 mV.

Figure 2 This graph shows the dpot step rate and direction as a function of R1.

R1’s rest position is (anywhere near) midpoint where step rate = 0. Programming a new setpoint is done by the following steps.

1. Turning R1 in the desired direction until stepping begins at a rate appropriate to the size of the intended setpoint change.
2. Then gradually slowing the step rate to dead stop by returning R1 to midpoint as the new setpoint is approached.

Done. 

With a “bit” of practice, a U2 setpoint change of 127 steps (maximum for the 7-bit resolution AD5220) can be accurately completed in less than 10 seconds. And if you feel the need for speed beyond that, there’s nothing easier. Just back off on C1. Max step rate = 20Hz/C1 for C1 in µF.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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• DPOT push up/down
• Finger-friendly DPOT pushbuttons do ups, downs, and dittos
• Digital potentiometer simulates log taper to accurately set gain
• Push to increase, decrease a digital potentiometer
• Synthesize precision bipolar Dpot rheostats

 

The post Digital pot programming with a twist appeared first on EDN.

ClassOne Technology of Kalispell, MT, USA (which manufactures electroplating and wet-chemical process systems for ≤200mm wafers) says that two “industry-leading” photonics manufacturers have placed follow-on production orders for multiple Solstice S8 single-wafer wet processing systems. Configured with ClassOne’s GoldPro electroplating chambers, the Solstice systems will be used for high-volume gold electroplating of 4-inch and 6-inch indium phosphide (InP) wafers key to next-generation optical devices for artificial intelligence (AI) data centers and other high-bandwidth communications applications...

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Aeluma Inc of Goleta, CA, USA (which specializes in high-performance, scalable technologies for AI, mobile and consumer, defense & aerospace, and quantum) has executed an agreement with Sumitomo Chemical Advanced Technologies of Phoenix, AZ, USA (SCAT, a subsidiairy of Japan’s Sumitomo Chemical Co Ltd) to accelerate development and production of photonics wafers for the AI datacom market. The agreement will initially leverage existing metal-organic chemical vapor deposition (MOCVD) capabilities at SCAT’s manufacturing facility, and provides a path for increasing capacity in the future...

At European Microwave Week (EuMW 2026) at EXCEL, London, UK (4–9 October), Altum RF of Eindhoven, The Netherlands (which designs RF, microwave and millimeter-wave semiconductors) is showcasing its featured products and technical expertise in booth #L80 during the exhibition on 6–8 October...

Beyond low-power design and beyond multi-threshold-voltage libraries, clock and power gating, and voltage-frequency scaling lies the strange land of ultra-low-power systems. Here, power comes from tiny, semi-permanent batteries or energy scavenging, and it comes in microwatts or nanowatts, not milliwatts.

For system-on-chip (SoC) designers, this is the alien realm of ultra-low voltage (ULV): supply voltages near or below transistor threshold voltages. In this realm, many things are unfamiliar to conventional SoC designers. Foundational IP must be different. Familiar-looking tool flows may hide important differences in tools and skills. New challenges appear—threats that could sink a project.

ULV design explored

All differences in ULV design begin with the definition: ULV circuits use a VDD near or below the threshold voltage of the process’s MOSFETs. This leads to several important effects.

First, of course, is energy savings, the whole reason for ULV design. ULV works because instantaneous power is quadratic in supply voltage. So, the instantaneous power consumed when a circuit is active, and hence the energy required to complete a task, can be significantly lower at lower VDD.

Usually, designers will talk not about power consumption, but about the energy required to complete an operation, typically in nanoJoules. This is a preferred metric because, in ultra-low-power systems, ULV SoCs are usually quiescent for long periods, wake to perform specific tasks, and then reenter their trance. This activity pattern makes peak and average power figures poor indicators of energy consumption and, therefore, battery life or drain on energy scavengers.

But this energy benefit comes with challenges. Near threshold voltage, a MOSFET gate exerts only weak control over channel current. Leakage can be high, and the difference between ION and IOFF is small.

Maintaining the separation—the values of 1 and 0—throughout each net’s stages and across clock trees becomes a fundamental undertaking for the design team. The separation is already low, and other factors conspire against it. Interconnect parasitics, noise, and process variations can prevent circuits from working reliably. So, ULV design requires special measures.

Foundational IP

One of the first challenges designers will face is that conventional low-power libraries will not work for most ULV designs. Cells in standard libraries may be optimized for performance or packing density, but not for operation at ultra-low voltages. Some cells in the library are likely to fail or become unreliable simply because they cannot maintain the distinction between 1 and 0, even under ideal conditions. Add in parasitics, noise, and variations, and the library cells cannot cope. New, custom cell designs are needed.

In addition, some cells, such as high-fan-in gates, may work correctly but impose so much delay that they become useless. Such cells need to be eliminated from libraries. Other cells—ULV-level shifters, in particular—must be designed for the specific voltage range the design requires.

SRAM is another problem. The standard 6T SRAM cell usually cannot perform reliable reads and writes at ULV. Adding custom assist circuitry can help, as can simply enlarging the bit cell. The dual-rail design will work better (Figure 1). And some designers avoid the issue by making the SRAM a high-voltage island surrounded by level shifters, sacrificing energy efficiency for simplicity.

Figure 1 The dual-rail SRAM design highlights array on HV, periphery on ULV, and level shifter on the WL path. Source: Faraday Technology

Fine-grained characterization

Cells that work at ULV are necessary, but far from sufficient. Traditional delay modeling at a few process corners is hopelessly inadequate to achieve timing closure in a ULV design. In this voltage region, delay can vary exponentially with voltage, often in a non-Gaussian distribution. A traditional approach using a few corners would result in hopelessly large design margins.

We have found that fine-grained characterization of the foundational libraries, using voltage increments no larger than 50 mV and often finer, is a minimum requirement. This data must be captured in an advanced format such as Liberty Variation Format with Moments (LVFM). This allows statistical timing tools—using knowledge of the intended supply voltage range of the finished system—to produce design margins that are not overly pessimistic.

So, use knowledge of the intended supply voltage range of the finished system to produce design margins that are not overly pessimistic (Figure 2).

Figure 2 This data must be captured in an advanced format such as LVFM. This lets statistical timing tools produce design margins that are not overly pessimistic. Source: Faraday Technology

The bottom line for design teams is that ULV SoC design requires custom ULV foundational libraries, characterized over the expected operating range with very fine granularity.

Tool flow

Fortunately, ULV SoC design can use standard modern synthesis and place-and-route tools compatible with the LVFM format (Figure 3). But the standard flow still requires additional ULV expertise. For example, the synthesis tool must support the custom ULV libraries.

Figure 3 Standard Tools must possess critical ULV expertise. Source: Faraday Technology

All tools must recognize that, at ULV, timing will be extremely sensitive to routing paths due to both parasitic impedance and noise. Static timing tools must be variation-aware and able to consume LVFM data to exploit the libraries’ fine-grained characterization and minimize design margins.

Special attention must also be given to noise: crosstalk, supply transients, and even substrate noise. This may come down to the designers’ skill in floorplanning and in guiding placement and routing tools to anticipate and avoid noise sources.

The concluding steps

The ULV SoC design requires additional work to reach signoff. But then, both silicon bring-up and manufacturing test also have special requirements at ULV. Test equipment needs high accuracy at low voltages and, of course, a low-noise floor. So, load boards must be designed with extra care about leakage and parasitics.

During both silicon evaluation and manufacturing test, pay special attention to the power-on reset sequence across the entire operating voltage range, as it’s particularly vulnerable in ULV designs. Also, carefully test those ULV-level shifters.

Finally, the OSAT organization or internal manufacturing test facility must use the advanced binning strategy. Because process variations—even across a wafer—are so significant at ULV, it’s necessary to perform accurate voltage-speed binning (Figure 4). This separates chips that meet the requirements across the intended operating voltage range from those that work only at higher voltages.

Figure 4 Accurate voltage binning separates chips that meet requirements across the intended operating range from those that work only at higher voltages. Source: Faraday Technology

Why ULV expertise matters

ULV design facilitates SoCs that can operate almost indefinitely on tiny batteries or scavenged power. Custom libraries, fine-grained characterization, advanced design tools, and ULV-experienced designers make these projects achievable. Moreover, deep foundry and OSAT relationships make volume production realistic.

Some large design groups have these resources, expertise, and relationships in-house and can confidently undertake ULV SoC designs independently. But in many cases, an organization will want to deploy its assets across the overall low-energy system rather than to the specialized needs of the SoC design. In these cases, a traditional SoC design team can partner with an organization with extensive ULV experience.

The right ULV expert must be ideally positioned to partner with a traditional SoC design team entering ULV land. The land is indeed strange and strewn with risks. But with the right partner, it’s the land through which the path to technical and commercial success lies.

C.H. Chien has dedicated 33 years to IC design; his industry experience includes IP development and IC design flow. He also has 10 years of experience managing overseas R&D teams. Chien worked as a director at MediaTek and GlobalFoundries before joining Faraday Technology Corp.

Related Content

• Low power design is here to stay
• Scaling the Power Wall: Low-Power SOC Design
• Designing with ultra-low voltage MOSFET arrays
• The why, where and what of low-power SoC design
• Low Power Design Techniques, Design Methodology, and Tools

The post A design path to success exists for ultra-low-voltage SoCs appeared first on EDN.

Taking various considerations into account, the theoretical advantage of the spread bit PWM can be challenging to translate into practice.

A recent Design Idea (Reference 1) addressed the implementation of digital-to-analog converters using both common “clustered-bit” and less common “spread-bit” pulse-width modulation (PWM) techniques. Within a repetitive clustered PWM cycle, all of the ones appear in succession, as do all of the zeroes. In the spread PWM, the ones and zeroes are distributed more or less evenly within a cycle.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The clustered PWM tends to concentrate energy at lower frequencies, while the spread PWM moves energy towards the higher frequencies, allowing for faster-settling analog ripple-suppression filters. Given PWMs with individually-customized filters of the same complexities, clocks and cycle periods, the latter has clear advantages. Such is the case for hardware-based implementations such as FPGAs. However, while most microcontrollers can advance a clustered-bit PWM with the speed of their CPU clock, they cannot do so for a spread PWM. Effective clocks for these PWMs are slower because a microcontroller must implement them with multiple CPU instructions.

Clocks are further slowed by any code required to support features other than the PWM. Note that all code blocks must execute in invariant periods of time to prevent jitter from degrading the accuracy of the output. So including interrupts in the code is problematic. Another concern is the error which accrues to unequal rise and fall times, leading to mismatched logic one and zero durations. In a clustered cycle, there is only one rising and one falling transition, leading to an error considerably less than one bit. Unfortunately, the multiple transitions in a spread cycle make this type of PWM more subject to this type of error, which will be worst at a 50% duty cycle.

This all being said, the prior article investigated a claim that a microprocessor-implemented spread-bit PWM with a single resistor-capacitor pair filter outperformed a clustered-bit PWM with a three component-pair filter. This claim was shown to be true only for PWMs of 16 bits or more, and then only for a microcontroller which supported no features other than the PWM. But it’s unfair to tie one hand behind the back of the spread PWM, limiting it to first-order filters. This Design Idea compares spread and clustered alternatives driving individually customized filters of the same third order three-R/C-pair complexities.

The rules of the game

The b-bit PWMs discussed here can be thought of as having repetitive sequences of length N = 2b, where 1/N is the PWM resolution. N is an integer, but b needn’t be one for the clustered type. For the spread PWM, however, b typically is an integer for reasons of coding efficiency. See a discussion of why and of one way to code a spread-bit PWM in Reference 2.

Analog filters are employed to suppress PWM waveform-induced ripple. They exhibit a settling time in response to a duty cycle (DC) change. Some particular DC change will yield the maximum settling time TS to within VST of some fully settled voltage, and some duty cycle DC will produce the absolute maximum steady state error Vrip due to the ripple.

I’ve required that Vrip = ½ · 1/N and that VST = 1/N. Optimized-for-settling-time clustered-bit PWM filters are covered in Reference 3 and are easily designed. For the design of optimized spread-bit 3rd order filters (Figure 1), I’ll briefly describe the math involved at the end of his Design Idea.

Figure 1 These first (left) and third order (right) low-pass analog filter structures are buffered with op amps because their inputs employ resistors of high values. This is done to limit the errors imposed by the unequal resistances (Reference 4) of the logic high and low outputs of ICs such as the 74AC04 which drive the filter inputs.

Comparisons

The graph in Figure 2 is based on the data in Table 1. We see the expected superiority in settling time of the spread approach in comparison to the clustered alternative for PWMs with the same b (and therefore N) values and a clock frequency of 1 MHz. This relationship also holds for different frequencies as long as the clocks are identical.

Figure 2 In this comparison of b-bit PWMs clocked at 1 MHz, spread and clustered PWMs are investigated with individually optimized third order filters compliant with the information in the “Rules of the game” section. Additionally, the spread with a first order ( one R, one C ) filter (see Figure 1) is shown for reference. With third order filters, the improvement in settling time of the spread over that of the clustered PWM is apparent and grows with b and N.

Number of bits	Settling time (mS), spread, first order filter	Settling time (mS), spread, third order filter	Settling time (mS), clustered, third order filter	Spread/clustered improvement, third order filters
2	5.00E-03	3.09E-03	3.32E-03	1.08
3	1.80E-02	7.31E-03	1.01E-02	1.39
4	5.20E-02	1.65E-02	2.93E-02	1.77
5	1.34E-01	3.89E-02	8.32E-02	2.14
6	3.29E-01	9.29E-02	2.34E-01	2.52
7	7.78E-01	2.00E-01	6.53E-01	3.27
8	1.80E+00	4.23E-01	1.81E+00	4.28
9	3.74E+00	8.89E-01	4.98E+00	5.60
10	8.42E+00	1.87E+00	1.36E+01	7.28
11	1.87E+01	3.94E+00	3.71E+01	9.40
12	4.13E+01	8.32E+00	1.00E+02	12.07
13	9.03E+01	1.87E+01	2.71E+02	14.47
14	1.85E+02	4.02E+01	7.28E+02	18.11
15	4.00E+02	8.40E+01	1.95E+03	23.21
16	8.61E+02	1.74E+02	5.21E+03	29.88
17	1.84E+03	3.61E+02	1.39E+04	38.36
18	3.94E+03	7.50E+02	3.68E+04	49.09
19	8.01E+03	1.56E+03	9.75E+04	62.46
20	1.70E+04	3.43E+03	2.58E+05	75.14
21	3.59E+04	7.15E+03	6.80E+05	95.12
22	7.58E+04	1.52E+04	1.79E+06	117.43
23	1.59E+05	3.11E+04	4.71E+06	151.57
24	3.23E+05	6.33E+04	1.24E+07	195.18

Table 1 The data in this table forms the basis of the graphs shown in Figure 2.

A comparison based on identical clock rates would be appropriate if the two PWM alternatives were implemented in hardware, such as with an FPGA. But a microcontroller implementation of the spread, unlike that of the clustered, requires code execution. Comparatively, a microcontroller’s spread clock frequency is lower than that of the clustered (which requires no code to support an initialized, constant duty cycle PWM), especially if the microcontroller is performing tasks in addition to the spread PWM implementation.

Using the data

Defining a PWM whose full-scale output is “1” starts with specifying its 1 / N = 2-b resolution. With a 1 MHz clock, a PWM’s b bits correspond to points on each of the settling time curves in Figure 2. These are the maximum settling times TS, 1MHz to an error of 1/N. For a desired settling time of Tdes ≠ TS, 1MHz, the clock frequency must be changed. Defining a frequency scaling factor FSF equal to TS, 1MHz / Tdes, the PWM clock PWMclk becomes FSF · 1MHz.

If the clustered PWM has been selected, the spreadsheet in Reference 5 can be used to design the filter. Its parameter peak-peak Ripple, Fraction Frac of Full Scale should be set to 1/N, and the parameter PWM frequency, Hz to PWMclk/N. This spreadsheet executes the job with the press of a button, and it also runs an LTspice simulation of the filter’s worst-case transient response and ripple with the press of another button.

But if the spread PWM with a third order filter is selected instead, things are more complex (the first order spread PWM was discussed in Reference 6). Table 2 supplies three pairs of resistor and capacitor values to be used to implement a third order filter. These values will need to be modified to meet certain requirements. Recalling FSF, the actual component values are the table’s capacitor values divided by FSF · ZSF and the table’s resistor values multiplied by ZSF. ZSF is a positive, unit-less impedance scale factor which can be selected to meet requirements’ needs.

Number of bits	N ( 1/resolution)	r1, ohms (c1 = 10nF)	r2, ohms (c1 = 10nF)	r3, ohms (c1 = 1nF)
2	4	163.1000885	71.68292585	427.1087404
3	8	343.433862	271.9382005	828.4900535
4	16	716.8099067	681.854738	1497.328378
5	32	1444.093716	1398.000657	2966.654472
6	64	2816.731051	2186.864174	6876.068023
7	128	5619.092479	4103.426809	14167.24162
8	256	11229.51857	7684.085243	29082.22862
9	512	22464.62272	15027.67815	58621.97919
10	1024	45100.99781	27402.70118	120390.8368
11	2048	90360.13359	53513.94391	242063.9576
12	4096	182059.6186	99434.32312	490140.5768
13	8192	368094.4499	184124.8578	986470.2649
14	16384	736189.1063	368249.819	1972941.083
15	32768	1466466.446	755969.6418	3940496.058
16	65536	3005457.305	1320906.538	7870364.119
17	131072	5976310.761	2716759.439	15771899.07
18	262144	11952685.17	5433547.811	31543966.12
19	524288	24043631.67	10567240.53	62962842.83
20	1048576	47816245.75	21736693.78	126190392.7
21	2097152	95636270.97	43475105.66	252390759.7
22	4194304	191158658.6	86898441.34	504480973.5
23	8388608	384771591.2	169108145.2	1007597919
24	16777216	741230589.8	427594752.1	1990907707

Table 2 This table’s prototypical component values can be as-needed modified to implement a third order, spread-bit PWM filter (see text and Figure 1).

One of the requirements is that r1 should be large enough to swamp out the errors due to the difference rdiff between the logic high and logic low resistances of the digital ICs driving r1. A little math shows that this means that r1 > rdiff · (N -1) / 2 for an error of less than 1/ (2·N) = Vrip.

Don’t drive the circuit directly from a microcontroller, whose outputs generally won’t swing adequately close to the rails because of voltage drops across the IC’s bonding wires that accrue from the device’s supply currents. Consider buffering the output with a 74AC04. Five 74AC04 inverters connected in parallel and powered from 3V or more have a maximum rdiff of 9 ohms and a far lower typical value.

Another requirement is that the sum of r1, r2 and r3 should not be so large as to incur voltage drops in excess of Vrip due to op amp input current. All resistors should be metal film. As for the capacitors, ceramic NPO / C0G and polyester film types are sufficiently stable with temperature and voltage. Capacitor values should be more than 330pF so as to swamp out PCB and op amp input capacitances.

The freedom to choose a ZSF value might not be sufficient to meet the listed requirements. The addition of an op amp buffer stage (see Figure 3) between the 74AC04 and the filter transfers the filter’s r1 > rdiff · (N – 1) / 2 requirement to the buffer stage where it can be more easily met; the filter is now being driven from a low dynamic, constant- impedance op amp output.

Another way to ease requirement satisfaction is to sum the outputs of a “least significant” and a “most significant” PWM, also shown in Figure 3. This relaxes the r1 > rdiff · (N – 1) / 2 requirement to r1 > rdiff · (sqrt(N) – 1) / 2 and speeds settling time by a factor of sqrt(N).

Figure 3 In this circuit, ra, ca and U1 provide a means to eliminate the spread filter’s r1 > rdiff · (N – 1) / 2 requirement. Optionally, the entire circuit allows the addition of contributions from the outputs of separate PWMs weighted by factors of 1/257 and 256/257. It is recommended that the MS PWM be buffered by five 74AC04 inverters in parallel and the LS PWM by a single inverter.

A spread third order filter math overview

This section is supplied for completeness and can be skipped if desired.

The following is the transfer function of a third order low-pass filter, all of whose poles are constrained to have identical real parts so that they contribute more or less equally to the overall settling time.

H(s) = .5 · ω03 / Q / [ ( s + .5·ω0/Q ) ·  ( s2 + s·ω0/Q + ω02) ]

A worst-case settling time occurs when the filter input transitions at t = 0 from DC = 1 to DC = 0. The time domain transient response is calculated using the following equation.

ytr(t) = e-a·t · [ ( cos(a·β·t) – 4·Q2 ) / β2 –  sin(a·β·t) / β ]

where a = .5·ω0/Q  and  β = sqrt(4·Q2 – 1)

The biggest ripple occurs, perhaps surprisingly, with the input of a single one (or zero) in a cycle.

x(t) = 1

for (k · N) · T    ≤   t   ≤    (k · N + 1) · T, k = 0, 1, 2…, and T = 1/PWMcllk

x(t) = 0

otherwise.

This is well approximated by a truncated Fourier series.

x(t) = 1/N + (2/N) · Σ sinc ( π·k/N ) · cos ( 2·π·k·(t – T) / (N·T) )

where k = 0, 1, 2… 15.

The resulting steady state output ySS(t) is obtained by multiplying the amplitude and time-delaying each harmonic in x(t) by amounts determined by H( 2·π·k·j / (N·T) ). The total output y(t) is the sum of ytr(t) and ySS(t).

To design the filter, the maximum absolute values of ySS(t) – 1/N are constrained to be less than .5/N. They are examined for Q values between .5 and 2, and solved in each case for ω0. That Q, ω0 value pair is selected which corresponds to the smallest settling time of y(t) – 1/N to an absolute error less than 1/N.

The numerical values of H(s) now being determined, its analytic form expressed in terms of r1, r2, r3, c1, c2, and c3 is examined and solved through numerical techniques to obtain the resistor values (for the capacitor values shown) that appear in Table 1.

Conclusion

There’s no question that the spread PWM offers a substantially shorter settling time than the clustered alternative when same b-bit PWMs are driven by identical clocks and succeeded by topologically similar but individually optimized filters. The ratio of improvement increases with the number of PWM bits. If a PWM is to be implemented in hardware such as an FPGA, the spread PWM is probably the better choice.

The caveat comes when a microcontroller is doing the implementation. A clustered PWM can run at the CPU clock rate. The spread PWM effective clock is slower, with this type requiring the execution of X instruction cycles, including that needed to implement an infinite loop. So, the spread PWM clock is the CPU clock divided by X, and its filter’s settling time will be increased by that factor X.

Clock period and settling time are further increased if functions other than the PWM are to be implemented. And care must be taken to ensure that PWM code execution occurs at a consistent rate; a jittery clock will degrade accuracy. Accordingly, implementing interrupts is problematic.

Another concern is the error which accrues to unequal rise and fall times, leading to unequal durations of logic ones and zeroes. In a clustered cycle, there is one rising and one falling transition only, leading to an error considerably less than one bit. Unfortunately, the multiple transitions in a spread cycle make this type of PWM more subject to this type of error, which will be worst at a 50% duty cycle.

When considering PWMs with larger numbers of bits (16, for instance), minimized settling times favor the approach of using a pair of resistors to sum the contributions of two independent 8-bit PWMs. This PWM pair’s filter can settle 256 times faster than a single 16-bit PWM’s filter can do. Most microcontrollers support a pair of independent clustered PWMs running off the same counter, an approach which could be duplicated in an FPGA.

But spread PWMs, whether in hardware or on a microcontroller, demand entirely independent means of support. When these considerations are taken into account, it can be seen that the theoretical advantage of the spread bit PWM can be challenging to translate into practice.

References:

1. Implementing a DAC: The battle of the PWMs
2. Ibid
3. Custom design PWM filters easily
4. Ibid, see the SN74AC04-induced errors section.
5. Ibid
6. Implementing a DAC: The Battle of the PWMs

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content

• Implementing a DAC: The battle of the PWMs
• Custom design PWM filters easily
• A nice, simple, and reasonably accurate PWM-driven 16-bit DAC
• Parsing PWM (DAC) performance: Part 1—Mitigating errors, Part 2—Rail-to-rail outputs, Part 3—PWM analog filters, and Part 4 – Groups of inhomogeneous duty cycles

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