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In today’s world, motors are ubiquitous, powering everything from household appliances to industrial machinery. The importance of optimizing motor control for energy efficiency cannot be overstated, given that motors account for a significant portion of global energy consumption. This article delves into the structure of motors, the use of variable frequency drives (VFDs), and the solutions for motor control applications, including hardware support and advanced algorithms.

The prevalence of motors

Motors are integral to our daily lives, found in household appliances like washers, dryers, dishwashers, and pool pumps. They are also essential in automotive applications, with modern cars containing anywhere from 40 to 100 motors, depending on the model and trim level. Industrial environments are heavily reliant on motors, particularly in robotics and factory automation. Figure 1 shows the range of motor applications from household appliances to automotive and industrial.

Figure 1 The range of applications involving motors highlights the prevalence of this technology and thus the importance of considering their energy consumption and efficiency. Source: Microchip

According to the Energy Information Administration, approximately 50% of global energy consumption is attributed to motors. In industrial applications, this figure can exceed 80%. For instance, in the United States, the total energy consumption in 2022 was 4.07 trillion kilowatt-hours, equating to a daily consumption of 11.2 billion kilowatt-hours. Improving motor efficiency by just 1% could save 56 million kilowatt-hours of energy daily.

Key trends in motor efficiency

Figure 2 shows the four avenues to improve motor efficiency: energy efficiency motors, the use of drives and better electronics, advanced algorithms, and the integration of IoT. This section will touch upon these four topics and go into more detail.

Figure 2 The four avenues to improve motor efficiency: energy efficiency motors, the use of drives and better electronics, the integration of IoT, and advanced algorithms. Source: Microchip

Energy efficient motors

One of the primary trends in motor efficiency is the transition from traditional motors, such as AC induction motors, to more efficient types like brushless DC (BLDC) motors, permanent magnet synchronous motors (PMSM) and interior permanent magnet (IPM) motors. These motors offer higher efficiency and improved performance. Additionally, advancements in materials, such as the use of amorphous metals and rare earth magnets, have further enhanced motor efficiency.

Material advancements

In the realm of motor technology, advancements in materials and design have significantly enhanced the efficiency and performance of motors over the past century. As shown in Figure 3, a motor typically consists of end bells, a rotor, bearings, and a stator with windings.

Figure 3 The basic structure of a motor where rotor and stator coils materials have shifted from aluminum to copper. Source: Microchip

Over the years, the materials used in these components have evolved. For instance, the transition from aluminum to copper in the rotor and stator coils has improved conductivity and efficiency. Additionally, advancements in manufacturing tolerances have reduced noise and further increased efficiency.

One notable trend in motor technology is the use of amorphous materials in rotors and stators. Traditionally, silicon steels were used, but they had high eddy current and hysteresis losses. These are now being replaced by amorphous materials like metallic glasses, which have lower losses and thus higher efficiency.

For permanent magnet motors, stronger magnets, such as those made from rare earth materials like neodymium, iron and boron, provide more torque and efficiency. However, due to sustainability concerns, alternatives like aluminum, nickel, chromium, and ferrite-based magnets are being explored for their good properties over a range of temperatures and strong magnetic fields.

Motor structure

The transition from journal bearings to ball bearings has played a significant role in reducing friction and improving tolerances, thereby enhancing motor efficiency. Over the past century, motors have become considerably smaller while maintaining the same power output. As shown in Figure 4, a modern 5-horsepower, squirrel-cage rotor, three-phase induction electric motor (SCIM) is substantially smaller and weighs approximately 20% of what a motor with the same power rating did in 1910. This reduction in size can be attributed to the use of lighter and more efficient materials, as well as advancements in thermal and electrical insulation.

Figure 4 A timeline of the reduction in mass for a 3.7 kW SCIM motor from 1910 to 2020. Source: Hitachi

Lighter motors are particularly beneficial for automotive applications, where reducing weight can lead to increased efficiency and the ability to integrate motors into more compact spaces. As we continue to explore new materials and designs, the potential for even greater efficiency and performance in motor systems remains promising.

Variable frequency drives

Variable frequency drives (VFDs) have become increasingly popular for controlling motor speed and improving efficiency. VFDs adjust the motor’s speed to match the load requirements, reducing energy consumption. The transition from insulated gate bipolar transistors (IGBTs) to silicon carbide (SiC) and gallium nitride (GaN) technology in VFDs has also contributed to higher efficiency and faster switching.

VFD impact

Variable Frequency Drives (VFDs) have revolutionized motor control by allowing precise control over motor speed and torque. This technology optimizes motor performance and significantly improves system efficiency. A VFD adjusts the frequency and voltage supplied to the motor, enabling it to operate at the most efficient point for a given load.

For instance, traditional motor systems often operate at full power, with flow rates controlled by throttling valves, leading to substantial energy losses. In contrast, VFDs eliminate the need for throttling by adjusting the motor speed to match the required flow rate, thereby reducing energy consumption and increasing overall system efficiency. As shown in Figure 5, studies have shown that switching to a VFD can more than double the efficiency of a motor system, from around 31% to 72%.

Figure 5 Switching to a VFD can more than double the efficiency of a motor system, from around 31% to 72%. Source: [1]

Motor control hardware

As shown in Figure 6 a range of power management devices are necessary to effectively benefit from VFDs.

Figure 6 Basic block diagram of supporting power management devices for motor control. Source: Microchip

AC-DC converters utilizing SiC in tandem with gate drivers enable precision switching for efficient power conversion. MCUs with motor-specific peripherals and specialized algorithms, e.g. dsPIC33 digital signal controllers (DSCs), can be optimized to convert DC to variable AC. Finally, integrated sensors offer real-time feedback on current, voltage and temperature, enhancing system reliability.

Advanced control algorithms

Traditional methods, such as V/F control for AC induction motors, are cost-effective and straightforward but may not offer the highest efficiency. More advanced algorithms, such as six-step commutation for BLDC and PMSM motors, can offer sensor or sensor-less precision torque control. Field-oriented control (FOC), for example, uses a single-cycle MAC with data saturation as well a zero overhead looping and barrel shifting for high performance speed, position, and torque control. Figure 7 shows a sample block diagram for FOC of a motor using the least FPGA resources to execute a full motor control algorithm.

Figure 7 The block diagram for modular sensorless BLDC motor control algorithm using coordinate rotation digital computer (CORDIC) with sine-cosine required for FOC of motors. Source: Microchip

The Zero-Speed/Maximum-Torque (ZS/MT) control algorithm is a new variation of the sensorless FOC algorithm that enables the adoption of sensorless control techniques in high-torque or low-speed motor control applications. ZS/MT eliminates the need for Hall effect sensors by using a reliable initial position detection (IPD) method based on high-frequency injection (HFI) to determine the exact rotor position at zero and low speeds, making it ideal for applications like drilling machines, garage door openers, automotive starters and e-bikes.

Integration with IoT and AI/ML

The integration of IoT and AI technologies has revolutionized motor control. Sensors are used to detect current, torque, and rotor position, among other parameters, information that is then fed to MCUs for processing. With the integration of ML, these systems can perform predictive maintenance by analyzing sensor data to predict potential motor failures or maintenance needs.

Predictive maintenance ensures that motors operate at peak efficiency and performance, reducing the likelihood of unexpected breakdowns. By continuously analyzing parameters such as current, torque and vibration, predictive maintenance ensures efficient motor operation and minimizes downtime. Systems can, for instance, employ a classification model to determine the operational state of a motor, identifying whether it is functioning normally or experiencing anomalies such as an unbalanced load or a broken bearing, by monitoring the quiescent current of the motor.

Optimizing motor control

Optimizing motor control for energy efficiency is crucial for reducing global energy consumption and improving the performance of various applications. By transitioning to efficient motors, utilizing VFDs, implementing advanced control algorithms and integrating IoT and AI technologies, significant energy savings can be achieved. As the demand for energy-efficient solutions continues to grow, advancements in motor control technology will play a vital role in meeting these needs.

Pramit Nandy is a product marketing manager at Microchip Technology Inc., focused on motor control applications. Nandy has been with Microchip since 2021 and his previous experience includes a product marking manger position with Onsemi. He holds a master’s degree in electrical engineering from Arizona State University.

Reference

1. T. de Almeida, F. J. T. E. Ferreira and D. Both, “Technical and economical considerations in the application of variable-speed drives with electric motor systems,” in IEEE Transactions on Industry Applications, vol. 41, no. 1, pp. 188-199, Jan.-Feb. 2005, doi: 10.1109/TIA.2004.841022.

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The post Optimizing motor control for energy efficiency appeared first on EDN.

SemiQ Inc of Lake Forest, CA, USA — which designs, develops and manufactures silicon carbide (SiC) power semiconductors and 150mm SiC epitaxial wafers for high-voltage applications — has announced a family of three 1200V SiC full-bridge modules, each integrating two of the company’s rugged high-speed switching SiC MOSFETs with reliable body diode...

BluGlass Ltd of Silverwater, Australia — which develops and manufactures gallium nitride (GaN) blue laser diodes based on its proprietary low-temperature, low-hydrogen remote-plasma chemical vapor deposition (RPCVD) technology — has received an AUS$120,000 order for semi-custom GaN laser diode bar products from a repeat customer, the College of Optics and Photonics (CREOL) at the University of Central Florida...

📢 Курс «Інтенсив підготовки до НМТ-2025» від КПІ! kpi чт, 02/20/2025 - 12:09

День Героїв Небесної Сотні kpi чт, 02/20/2025 - 11:27

Dynamic random-access memory (DRAM) chips contain many other transistors besides the access transistor to enable full operation of the DRAM memory. These peripheral transistors must meet stringent requirements which preclude a ‘copy-paste’ of regular logic transistor process flows.

One critical requirement imposed by present DRAM chip architectures is the ability of the periphery to withstand thermal treatments at 550-600°C and above. While the first part of this article series focused on DRAM basics and peripheral circuits, this part will provide a detailed account of DRAM periphery, explaining different generations of thermally stable peripheral transistor technology ranging from planar high-k/metal-gate transistors to FinFETs.

DRAM periphery: From SiON-based gate stacks to high-k/metal gates

Until 2018, DRAM peripheral transistors were predominantly made in planar logic MOSFET technology with poly-Si/SiO2 or poly-Si/SiON gates. These technologies were less advanced than the transistors used for high-performance logic in order to maintain the DRAM cost-per-bit trendline.

However, an improved technology for the periphery became necessary to keep pace with the performance enhancement enabled by subsequent generations of DRAM memory. The most obvious candidate was moving to a planar transistor architecture with a high-k/metal-gate stack—a transition that occurred as early as 2007 in the high-volume manufacturing of logic technologies.

Since about 2007, imec, together with its partners, has actively explored a DRAM-compatible version of high-k/metal-gate transistors and proposed multiple material and integration options to the memory industry. Today, almost every device with a DRAM memory inside contains a planar peripheral transistor technology with high-k/metal gates, which imec has been pioneering for more than 15 years.

Below is a grasp of some of the proposed material, module, and integration options, all differing in fabrication complexity and performance levels.

High-k/metal-gate integration: Thermally stable gate-first and gate-last integration flows

One of the solutions demonstrated by imec for potential early introduction was based on a gate-first integration approach, in which the metal gate is deposited before the high-temperature source/drain junction activation anneal. Gate stacks for nMOS and pMOS can be optimized separately by using different work function metals and layer thicknesses for the high-k/metal-gate stack (for example, TiN/Mg/TiN for n; TiN for p).

One of the critical parameters is obtaining an effective work function that is low enough for nMOS and high enough for pMOS to ensure a good Ion/Ioff ratio. Researchers achieved this by doping the gate stacks (with different dopants for pMOS and nMOS), which enabled a shift in the threshold voltages.

The choice of the dopant materials and their integration also provided a knob for improving the thermal stability of the gate stack and enabling the different Vth required by the DRAM chip. The DRAM-specific requirement for low gate leakage was addressed, among others, by adopting thicker gate stacks compared to logic-oriented solutions.

Figure 1 Sketch of the critical fabrication steps is shown in a gate-first integration approach for planar high-k/metal-gate peripheral transistors. Source: PSS

Imec also successfully demonstrated a thermally improved version of a gate-last integration approach, also called replacement metal gate (RMG) flow. In a gate-last flow, a poly-Si capped dummy gate is deposited and remains in place until the junction activation anneal is applied. After that, the dummy poly is replaced by the target metal gate.

Optimized source/drain junctions

Source/drain junctions are critical to ensure the functionality of MOSFET transistors. They are formed by creating a dopant gradient in the source/drain areas. As conduction channel lengths continued to shrink, ultra-shallow junctions became indispensable to ensure good electrostatic control over the channel. However, for peripheral transistors, the thermal treatments during DRAM memory anneal trigger an unwanted diffusion of the dopants, requiring more complex process flows to maintain the dopant gradient.

This issue can be addressed by changing the junction implant scheme using, for example, pre-amorphization implants and junction co-implants. Imec demonstrated several sets of optimized junctions suited for various threshold voltage targets.

A thermally stable silicide process

A general challenge for all transistors is to keep the source/drain contact resistance as low as possible. Source/drain contacts are formed by bringing a metal in contact with the source/drain regions, creating a Schottky barrier at the interface.

To ensure low resistance, two techniques are typically applied: (1) heavy doping of the source/drain regions and (2) complete silicidation of the source/drain areas—the silicides being formed through the reaction of the contact metal with the doped Si.

However, Ni(Pt) silicide, traditionally used in logic devices, cannot withstand the DRAM-related anneal temperatures. Imec proposed a thermally stable NiPt-based silicide module with low contact resistance by implementing additional implants and annealing steps for silicide stabilization.

Thermally stable, FinFET-based peripheral platform

Applications like automotive, artificial intelligence (AI) and machine learning (ML) impose increasingly stringent requirements on DRAM memories, driving the need for faster, more reliable and power efficient peripheral transistors. One option is to retrace the path of ‘logic’ and move from planar high-k/metal-gate transistors to FinFETs.

The logic roadmap made this transition as early as 2011 after R&D clearly showed the superior performance of transistors with fin-shaped conduction channels: improved Ion/Ioff, better short channel control, higher drive current at reduced footprint (due to a higher effective width of the channel), and lower power consumption—while keeping cost under control. On top of that, the use of tall fins provides a way to reduce the threshold voltage mismatch, which can particularly benefit the DRAM sense amplifiers.

Just like for the planar versions, the DRAM-specific requirements preclude a copy-paste of FinFET process flows developed for regular logic. In response, imec developed a thermally stable FinFET-based peripheral technology platform with integrated modules optimized for DRAM. Multiple flavors with different performance-cost trade-offs have been proposed to the industry for their next-generation DRAM products.

Thermally stable gate-first and gate-last FinFET integration flows

In 2021, imec reported the first experimental demonstration of a thermally robust integration flow for FinFETs using an optimized gate-first approach for implementing the high-k/metal-gate stack. Compared to a traditional gate-first approach, the modified flow implements gate stacks with the same thickness and the same work function metal for both nMOS and pMOS. So-called Vth shifter materials are then diffused into the high-k dielectric to tune the effective work function of the nMOS and pMOS devices.

This modified gate-first approach reduces the gate asymmetry and enhances the thermal stability of the flow. By using this flow, the researchers demonstrated improved Ion/Ioff and short channel control over planar high-k/metal-gate counterparts. These metrics did not degrade after the DRAM-specific anneal. Flavors with taller fins (with up to 80-nm height) have also been developed, with improved threshold voltage mismatch and area gain.

Figure 2 Example of a fabricated high-k/metal-gate fin displays transmission electron microscope (TEM) cross sections for 40-nm, 65-nm, and ~80-nm tall fins. Source: imec

A drawback of the gate-first integration approach is the relatively high threshold voltage, which originates from the impact of the high-temperature anneal on the gate stack during junction activation. This issue can be solved using a gate-last (or RMG) integration approach, which, however, comes with additional process steps. At IEDM in 2022, imec showed a thermally stable version of a FinFET gate-last flow.

Figure 3 The above image shows a selection of relevant process step for the proposed gate-last process flow for thermally stable FinFETs. Source: 10.1109/IEDM45625.2022.10019422

An optimized and thermally stable gate-last FinFET flow with a Mo-based work function metal for pMOS

Typical for a gate-last flow is the use of different work function metals for nMOS and pMOS devices. At VLSI in 2024, imec demonstrated the performance benefits of using a novel Mo-based work function metal for pMOS instead of the conventional TiN-based approach. The new gate stack module was successfully integrated into a gate-last FinFET flow and proven to be thermally stable.

The DRAM-compatible flow with integrated Mo-based p-work function metal yielded sufficiently low Ioff current and low threshold voltage (0.12 V) for the pMOS devices. The FinFETs were also benchmarked against a thermally stable planar high-k/metal-gate reference, showing a three times higher Ion (at target Ioff) for the same Si footprint. These results make the thermally stable gate-last FinFET flow a valuable candidate for sub-10 nm DRAM peripheral logic.

Figure 4 On left and middle are TEM images across fins on a ring oscillator and on right is elemental mapping across gate (EDS) showing CMOS patterning and decent conformality of the Mo-based p-work function metal stacks. Source: VLSI 2024

Thermally stable Nb-based metal contacts with low contact resistance

In earlier work on planar high-k/metal-gate based peripheral transistors, imec researchers lowered the source/drain contact resistance by improving the dopant profile and adding pre-amorphization implants. At IEDM in 2024, imec introduced a different approach: replacing the conventional Ti contact metal with Nb for pMOS devices.

The thermal stability of the Nb-based contact module was demonstrated for the first time. In addition, superior performance was observed when integrated into the gate-last FinFET platform: record low contact resistance, reduced overall parasitic resistance, and improved Ion.

Figure 5 The above chart shows a comparison of the contact resistivities of Ti- and Nb-based contact modules (different thicknesses) for before and after DRAM anneal. Source: IEDM 2024

Ahead of DRAM mass production

Imec pioneered peripheral transistor technology 10 years ahead of the industry’s mass production introduction. In its most recent R&D work, imec demonstrated an industry-relevant, thermally stable FinFET-based platform to meet the requirements for sub-10 nm DRAM. Multiple flavors have been developed as possible solutions for next-generation DRAM products, providing different levels of fabrication complexity and transistor performance.

More disruptive concepts are envisioned in the longer term to continue the DRAM scaling path. One of these is building the periphery on a separate wafer and integrating it with the memory array using advanced wafer bonding techniques. Although this approach comes with additional process steps, a true benefit is the relaxed requirement for thermal stability, as the periphery is now manufactured separately from the memory array.

Imec recently initiated R&D work on peripheral transistors for this new DRAM architecture, guided by insights obtained from planar and FinFET-based technology.

Alessio Spessot, technical account director, has been involved in developing advanced CMOS, DRAM, NAND, emerging memory array, and periphery during his stints at Micron, Numonyx, and STMicro.

Naoto Horiguchi, director of CMOS device technology at imec, has worked in Fujitsu and the University of California Santa Barbara while being involved in advanced CMOS device R&D.

Related Content

• DRAM gets more exotic
• FCRAM 101: Understanding the Basics
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• Winbond’s innovative DRAM design and the legacy of Qimonda
• DRAM technology for SOC designers and—maybe—their customers

The post A new platform for thermally stable DRAM peripheral transistors appeared first on EDN.

India’s Focused Show for Robotics, Smart Manufacturing, India Manufacturing Week, Technologies, Materials, Composites and Engineering, Product Design

The India Manufacturing Week 2025 is set to be a landmark event for India’s manufacturing sector, bringing together industry leaders to explore the latest advancements in digitalization, automation, robotics, additive manufacturing (3D printing), innovative materials, and design technologies. This three-day event will showcase cutting-edge solutions for smart, lean, and high-volume production.

With participation from top IT solution providers, the expo will offer valuable insights on optimizing production processes, reducing costs, and integrating advanced systems like ERP, MES, IIoT, and CIM. It’s the perfect platform for C-level executives, industry experts, and government representatives to connect and drive digital transformation in manufacturing.

India’s manufacturing landscape is rapidly evolving with the rise of Industry 4.0, fueled by the integration of IoT, AI, robotics, and data analytics. These advanced technologies enable seamless communication between machines, devices, and people, driving automation and significantly improving operational efficiency.
The shift to smart manufacturing is not only enhancing productivity and reducing costs but also improving product quality and enabling faster responses to market demands.

The post “About India Manufacturing Week 2025” appeared first on ELE Times.

Kyocera has developed an innovative mmWave phased array antenna module (PAAM) that simultaneously creates multiple beams in different directions at different frequencies. These PAAMs will be used in 5G FR2 infrastructure installations, enabling for example site co-location of different operators running networks on different frequency bands. To ensure optimal beam steering and beam directivity of their groundbreaking product, Kyocera relies on CATR-based multi-reflector OTA testing technology from Rohde & Schwarz.

Kyocera and Rohde & Schwarz will showcase at MWC 2025 in Barcelona the characterization of a novel mmWave PAAM design for FR2 applications. Crucial to the demonstration at the Kyocera booth (5E12) is the R&S ATS1800M 5G NR multi-directional mmWave test chamber from Rohde & Schwarz, designed for over-the-air (OTA) testing with an exceptionally small footprint.

Mobile communications that operate in the FR2 frequency range experience a high path loss, something that can be solved by using beamforming antenna arrays. In contrast to traditional antennas, FR2 antennas typically use phased arrays with a high number of individual antenna elements. Kyocera has developed a novel phased array antenna module (PAAM) featuring 384 dual polarization elements which is able to create up to 8 simultaneous beams in different directions at different frequencies. With this design, the PAAM can be used in site installations allowing multiple operators to run networks on different frequency bands.

However, all these antenna elements need to work perfectly together to form an RF beam with the desired characteristics. Rohde & Schwarz offers a patented approach for testing such a complex antenna array over- the-air (OTA) in a fully shielded environment, which helps engineers verify the correct beam pattern and supports the process of minimizing sidelobes.

The R&S ATS1800M is a unique solution that features four feed antennas and CATR reflectors, each with a 30 cm quiet zone (QZ). In the demonstration at MWC 2025, the Kyocera PAAM device under test (DUT) is placed on a rugged 3D positioner in the center, where all four QZs overlap, coming from multiple directions. This allows Kyocera’s engineers to address a variety of different tests, including the simultaneous reception of RF beams from four different directions, as will be shown at MWC 2025. Thanks to the vertical CATR design patented by Rohde & Schwarz, this setup takes up a fairly small footprint in the lab compared to other OTA-solutions.

The full test setup contains multiple test instruments from Rohde & Schwarz in addition to the mmWave test chamber, which work seamlessly together: four 5G NR-capable R&S SMW200A vector signal generators, a 5G NR-capable R&S FSW signal and spectrum analyzer, and an R&S NGP800 power supply. Each generator simulates a 5G NR FR2 signal which will be fed through one of the R&S ATS1800M feed antennas. The DUT receives the signal via one of the CATR reflectors. With the combination of all signal

sources, feed antennas and reflectors, Kyocera’s engineers can simulate complex reception scenarios of four frequency independent signals from four different locations. The received signal quality can be observed using the signal analyzer connected to the Kyocera PAAM.

Visitors to MWC 2025 can experience this milestone demonstration live at the Kyocera booth 5E12 in hall 5 of the Fira Gran Via in Barcelona from March 3 to 6, 2025.

For further information on antenna testing solutions from Rohde & Schwarz, visit: https://www.rohde-schwarz.com/_231852.html

The post Kyocera and Rohde & Schwarz join forces to demonstrate OTA characterization of mmWave PAAM at MWC 2025 appeared first on ELE Times.

AI-powered tool streamlines software development for greater efficiency and accuracy

Microchip Technology is leveraging the power of Artificial Intelligence (AI) to assist software developers and embedded engineers in writing and debugging code with the launch of its MPLAB AI Coding Assistant. A Microsoft Visual Studio Code (VS Code) extension, the free tool is based on Continue—the market’s leading open-source AI code assistant—and comes preconfigured with Microchip’s AI chatbot for real-time support.

The Microchip chatbot enables a chat functionality which allows developers to evaluate and iterate on code directly from the sidebar. This interactive support enhances the coding experience by providing highly customized, relevant real-time assistance and insights on Microchip-specific products. Additional features include advanced autocomplete for easier coding, an edit feature and error detection for efficient code modifications within the current file and integrated access to searchable Microchip documentation within the IDE.

“The MPLAB AI Coding Assistant represents a significant leap forward in software development and will transform how engineers work with Microchip products,” said Rodger Richey, vice president of development systems and academic programs at Microchip. “We’re harnessing the power of AI to provide interactive, real-time support that helps developers create better software, more quickly and with less hassle.”

Unlike most other code assistants on the market, MPLAB AI Coding Assistant’s sidebar chat feature can deliver block diagrams directly within the VS Code interface rather than just text responses. This capability, combined with easy access to a library of documentation on Microchip microcontrollers and microprocessors, streamlines the coding process and helps enhance accuracy.

Visit the website to learn more about Microchip’s wide range of development tools.

Pricing and Availability

The MPLAB AI Coding Assistant is available for free; some advanced features may require a subscription license. For additional information contact a Microchip sales representative, authorized worldwide distributor or visit Microchip’s Purchasing and Client Services website, www.microchipdirect.com.

The post Artificial Intelligence Meets Embedded Development with Microchip’s MPLAB AI Coding Assistant appeared first on ELE Times.

Photos 1, 2: Ч1-40 (Ch1-40) DOCXO quartz frequency standard. Photos 3-6: В7-34А (V7-34A) Digital voltmeter. 5.5 digits. Features ovenized voltage reference, fully isolated and hermetically sealed analog part. Photo 7: С1-107 (S1-107) Hybrid portable oscilloscope/multimeter with multimeter part drawn directly on the scope tube. submitted by /u/AltCtrlGraphene [link] [comments]

Lumileds LLC of San Jose, CA, USA says that its new LUXEON HL2X-V is the latest result of its commitment to addressing lighting manufacturing issues. Many manufacturers with high-power LED solutions are considering re-engineering their designs with mid-power LEDs to take advantage of their lumen/$ position. Now, with LUXEON HL2X-V, manufacturers can achieve lm/$ ratios similar to mid-power products without spending valuable resources on redesigning or re-engineering, says the firm...

Multi-color LED fixtures based on a large LED cluster under a single optical system are preferred in many situations for their ability to deliver highly accurate illumination with superior beam quality. Until now, however, LED design has not allowed engineers to address the conflicting needs and challenges inherent to close-packed, high-power LEDs...

Infinera Corp of San Jose, CA, USA — a vertically integrated manufacturer of open optical networking systems and optical semiconductors — says that its pending acquisition by Nokia Corp should be completed on or about 28 February, subject to receipt of remaining outstanding regulatory approvals and the satisfaction of other remaining customary closing conditions...

Sivers Semiconductors AB of Kista, Sweden (which supplies RF beam-former ICs for SATCOMs and photonic lasers for AI data centers) has appointed Alexander McCann as a strategic senior advisor to the board and the CEO. His primary focus will be strengthening and scaling photonics operations...

Rheostats

Rheostats are simple and ubiquitous circuit elements, usually comprising a potentiometer connected as an adjustable two terminal resistor. The availability of manual pots with resistances spanning ohms to megohms makes the optimum choice of nominal resistance easy. But when an application calls for a digital potentiometer (Dpot), the problem can be challenging.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Dpots are only available in a resistance range that’s narrow compared to manual pots. They also typically suffer from problematically high wiper resistance and resistance tolerance. These limitations conspire to make Dpots a difficult medium for implementing precision rheostats. Recent EDN design idea (DI) articles have addressed these issues with a variety of strategies and topologies:

• Op-amp wipes out DPOT wiper resistance
• Synthesize precision Dpot resistances that aren’t in the catalog
• Synthesize precision bipolar Dpot rheostats
• A class of programmable rheostats

While each of these designs corrects one or more complaints on the lengthy list of digital rheostat shortcomings, none fixes them all and some introduce complications of their own. Examples include crossover distortion, unreduced sensitivity to resistance tolerances, resolution-reducing nonlinearity of the programmed resistance, and just plain old complexity.

The design

Figure 1’s circuit isn’t a perfect solution either. But it does synthesize an accurate programmed resistance equal to reference resistor R1 linearly multiplied by U1’s Rbw/Rab digital setting (the ratio between the terminal B to wiper resistance and total element resistance).

Figure 1 A precision digital rheostat that synthesizes an accurate programmed resistance equal to reference resistor R1 linearly multiplied by U1’s Rbw/Rab.

Here’s how it works.

 R = (Va – Vb)/Ia
R = R1/(Raw/Rbw + 1) = R1 Rbw/Rab
Rab = Raw + Rbw = typically 5k to 10k

Where R is the programmed synthetic resistance, R1 is the reference resistor, Raw is the resistance between terminal A and wiper terminal, Rbw is the resistance between B and wiper terminal, and Rab is the total element resistance.

U1 works in “voltage divider” (pot) mode to set the gain of inverting amplifier A2. Pot mode makes gain insensitive to both U1’s wiper resistance (Rw) and Rab. They really don’t matter much—see Figure 4-4 in the Microchip MCP41XXX/42XXX datasheet.

Turning the crank on Figure 1’s design equation math, we get:

Ga2 = Raw/Rbw

Where Ga2 is A2’s gain. Further,

Voltage across R1 = (Va – Vb) + Ga2(Va – Vb) = (Raw/Rbw + 1)(Va – Vb) =  Rab/Rbw(Va – Vb)
Current through R1 = Ia = Rab/Rbw(Va – Vb)/R1

Then, since R = (Va – Vb)/Ia:

R = R1*Rbw/Rab

Va is lightly loaded by A1’s ~10 picoamp (pA) input bias, so R1 can range from hundreds of ohms up to multiple megohms as the application may dictate. It should be precision, certainly 1% or better; then, programming and the math above takes over.

Figure 2 plots the linear relationship between R and Rbw.

Figure 2 Linear relationship between R and Rbw showing the circuit synthesizes an accurate programmed resistance equal to reference resistor R1 linearly multiplied by U1’s Rbw/Rab.

A compensation capacitor (C1) probably isn’t necessary for the parts selection shown in Figure 1 for A2 and U1. But if a faster amplifier or a higher resistance Dpot is chosen, then 10 pF to 20 pF would probably be prudent.

Meanwhile, I think it would be fair to say this design looks competitive with its peers. But earlier I described it as imperfect. Besides being a single-terminal topology (like two others on the list), where else does it fall short of being a complete solution to the ideal digital rheostat (Digistat) problem?

Shortcomings

Here’s where: As Figure 3 shows, when the programmed value for R goes down, A2’s gain (Ga2) must go up. Reading the graph from right to left, we see gain rising moderately as R declines by 75% from R1 to R1/4 where, Rbw/Rab = 64/256 and gain = 3, but then it takes off. This tends to exaggerate errors like input offset, finite GBW and other op-amp nonidealities while creating the possibility of early A2 saturation at relatively low signal levels.

Figure 3 Graphs for Ga2 (red) and R/R1 (black) versus Rbw/Rab on the x-axis. When the programmed value for R goes down, Ga2 must go up.

The severity of the impact of these effects on utility of the design, whether mild, serious, or fatal, will depend on how low you need go in R/R1 and other specifics of the application. So, it’s certainly not perfect, but maybe it’s still useful somewhere.

Two-terminal design

And about that single terminal problem. If you have an application that absolutely requires a two-terminal programmable resistance, you might consider Figure 4. Depending on the external circuitry, it might not oscillate.

Figure 4 Duplicate and cross-connect Figure 1’s circuitry to get a two-terminal programmable resistance.

In closing…

Thanks to frequent contributor Christopher R. Paul for his clever innovations and stimulating discussions on this topic, I would likely never have come up with this design without his help. More thanks go to editor Aalyia Shaukat for her clever creation of this DI section that makes fun teamwork like this possible in the first place. This article would definitely never have happened without her help.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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The post A precision digital rheostat appeared first on EDN.

Fabless firm Cambridge GaN Devices Ltd (CGD) — which was spun out of the University of Cambridge in 2016 to design, develop and commercialize power transistors and ICs that use GaN-on-silicon substrates — has closed a $32m Series C funding round led by a strategic investor with participation from British Patient Capital and supported by existing investors Parkwalk, BGF, Cambridge Innovation Capital (CIC), Foresight Group, and IQ Capital...

A new network-on-chip (NoC) IP aims to dramatically accelerate chip development by introducing artificial intelligence (AI)-driven automation and reducing wire length to lower power use in system-on-chip (SoC) interconnect design. Arteris, which calls its newly introduced FlexGen interconnect IP a smart NoC, claims to deliver a 10x productivity boost, shortening design iterations from weeks to days.

Modern chips—connected by billions of wires—are ever-expanding with growing complexity. Modern SoCs have 5 to 20+ unique NoC instances, and each instance can require 5-10 iterations. As a result, SoC design complexity has surpassed manual human capabilities, which calls for smarter NoC automation.

“In SoC interconnect, while technology has advanced to new levels, a lot of work is still done in manual mode,” said Michal Siwinski, CMO of Arteris. FlexGen accelerates chip design by shortening and reducing iterations from weeks to days for greater efficiency.

“While FlexGen is still using the tried-and-tested NoC IP technology as basic building blocks, it automates the existing infrastructure by employing AI technology,” said Andy Nightingale, VP of product management and marketing at Arteris. “With FlexGen, we automate the NoC IP generation to reduce the manual work while opening high-quality configurations that rival or surpass the manual designs.”

Figure 1 A FlexNoC manual interconnect (above) is shown for an ADAS chip, while an automated FlexGen interconnect (blow) accelerates this chip design by up to 10x. Source: Arteris

According to Nightingale, it enhances engineering efficiency by 3x while delivering expert-quality results with optimized routing and reduced congestion. Dream Chip Technologies, a supplier of advanced driver assistance systems (ADAS) silicon solutions, acknowledges reducing design iterations from weeks to days while using FlexGen in its Zukimo 1.1 automotive ADAS chip design.

“FlexGen’s automated NoC IP generation allows us to create floorplan adaptive topologies with complex automotive traffic requirements within minutes,” said Jens Benndorf, GM at Dream Chip Technologies. “That enabled rapid experimentation to find design sweet spots and to respond quickly to floorplan changes with almost push-button timing closure.”

Shorter wire length

With AI comes a compute performance explosion, and as a result, the complexity of interconnects is going to exponential levels in SoC designs, leading to a huge explosion in the number of wires. FlexGen claims to reduce wire length by up to 30% to improve chip or chiplet power efficiency.

“We are also tackling the big problem of wire length in modern SoC designs,” said Nightingale. “As the gate count size reduces, it inevitably leads to dynamic power issues due to massive data traffic across wires.” By reducing wire length, FlexGen interconnect IP can reduce overall system power and thus help heating problems caused by the energy density of moving massive amounts of data across SoC interconnects.

Figure 2 FlexNoC manual interconnect (above) is shown with the best performance, while automated FlexGen (below) significantly reduces the interconnect wire length. Source: Arteris

Siwinski added that the number of gates doesn’t matter at smaller nodes. “Power from wire length kills you, so we reduce wire length to reduce overall power, performance, and area (PPA) in SoC designs.” That’s crucial as SoCs scale and become more powerful to meet the demands of applications like AI, autonomous driving, and cloud computing.

FlexGen is processor agnostic and supports Arm, RISC-V, and x86 processors. Moreover, its IP generation is highly repeatable to facilitate incremental design.

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The post SoC interconnect automates processes, reduces wire length appeared first on EDN.