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President Donald Trump’s administration has dramatically escalated trade tensions by imposing heavy new tariffs on Chinese goods, some of which are as high as 245%. The rising economic and geopolitical competition between the United States and China is the driving force behind this audacious move, which marks a new chapter in Trump’s “America First Trade Policy.”

Late Tuesday, the White House released a fact sheet outlining how these penalties are a direct response to China’s recent actions. By imposing export restrictions on crucial raw minerals like gallium, germanium, and antimony as well as rare earth magnets and six heavy rare earth elements—items essential to the semiconductor, aerospace, and defense industries—Beijing has been showing off its power.

This strong reaction is a result of the U.S.’s perception that China is using its supply chain dominance as a weapon. “China now faces up to a 245% tariff on imports to the United States because of its retaliatory actions,” the White House stated.

Karoline Leavitt, the press secretary for the White House, added that although President Trump is amenable to a trade agreement with China, he is waiting for Beijing to initiate this increasingly heated tariff spat.

What’s Hard Hit: A More Detailed Look at Tariffs

Needles and syringes: 245%

Lithium-ion batteries: 173%

Seafood: 170%

Wool sweaters: 169%

Plastic dishes: 159%

Toasters: 150%.

Electric vehicles: 148%

Toys, dolls, and puzzles: 145%

Vitamin C: 145%

Car wheels: 73%

Semiconductors: 70%

Metal furniture: 70%

Car door hinges: 67%

Laptops: 20%

Children’s books: 0%

These tariffs have enormous knock-on effects that affect everything from clothing to electronics and medical equipment.

Examining the Specifics:

Devices and Cell Phones

According to the U.S. Commerce Department, electronics, including TVs and mechanical appliances, account for 46.4% of all imports from China in 2022, including smartphones and accessories. More over 80% of the $52 billion worth of cellphones imported into the United States in 2024 came from China. These were initially subject to 145% taxes, but new customs regulations exempted phones and laptops from a reciprocal 125% levy. They are nevertheless forced to pay a 20% total tariff, which builds up over time (0% base + 20% fentanyl-related penalty).

Furniture, Clothes, and Toys

China is a major supplier of consumer products, furniture, and textiles, accounting for more than 50% of toys, furniture, and almost 30% of U.S. textile imports. Up until now, items like tricycles and plush animals were duty-free, which kept costs down. Toys are no longer a deal, though, because to a new 145% tax (0% base + 20% fentanyl penalty + 125% reciprocal). Wool sweaters and other clothing are now subject to a staggering 168.5% total tax (16% base + 7.5% pre-2025 + 20% penalty + 125% reciprocal), which significantly raises the cost of wardrobes.

Conclusion: Companies will have to assess their supply chains to ascertain the damage as these tariffs are not universal; they vary by product, material, and exclusions. EV makers, electronic companies, and energy storage companies that rely on Chinese suppliers will suffer from the 173% tariff on lithium-ion batteries. What about the 70% semiconductor duty? For American computer companies already dealing with chip shortages, that presents even another challenge.

It’s a complicated problem, and if businesses pass it on, the true cost may end up on customers. The United States and China are currently engaged in a high-stake game of chess.

The post Trump’s Trade Bombshell: Tariffs on China Hit 245% appeared first on ELE Times.

Цифрова освіта як спільний вектор kpi пт, 04/18/2025 - 11:51

🌸 Святкові дні під час воєнного стану kpi пт, 04/18/2025 - 10:10

📹 Візит віцепрем'єр-міністра Чеської Республіки до КПІ ім. Ігоря Сікорського Інформація КП пт, 04/18/2025 - 10:07

IPEC eyes market expansion of its EV Charging Products and Solutions business with new funding and aims to diversify into wider power electronics domain

Bengaluru-based IPEC, a first-mover and innovator in the EV charging space, has secured an investment of $3 million from Nikhil Kamath and Abhijeet Pai’s Gruhas. This investment from Gruhas in IPEC’s journey strengthens IPEC’s mission to consolidate its leadership status in the EV Charging sector and accelerate its growth in the broader power electronics domain. Having successfully delivered over 1 million EV charging products to the top EV OEMs in India, IPEC is now gearing up to expand its manufacturing capacities to 50,000 units per month. IPEC offers a range of EV charging products that include private, portable, and public chargers as well as EV Connectors and Vehicle Charging Inlets. These products are fully compliant with various national and international standards and the latest localisation regulations, including the PM E-Drive and PLI Scheme. Beyond hardware, IPEC also offers Cloud-based Charging Management Systems (CMS) and a user-friendly mobile app for real-time control and insights. IPEC is an approved supplier to leading EV OEMs like Ather Energy, Bajaj Auto, Greaves (Ampere), and more. Recognising the emerging need for power electronics in the EV Sector and in the energy transition, IPEC was created in 2017 by the MEHER Group, together with DEKI Electronics & Sungho Electronics, with Zohra Khan as its CEO. At the core of energy transition is Power Electronics – the technology that facilitates efficient power conversion in EVs, charging infrastructure, renewable energy, energy storage systems and green hydrogen. IPEC is driving this energy transition in e-mobility with intelligent, reliable and cost-effective charging solutions at scale that address India’s specific needs and the rising demand for locally manufactured alternatives. Among its strengths is IPEC’s highly evolved design and manufacturing expertise combined with the ability to seamlessly integrate sophisticated hardware, advanced software and AI.

Zohra Khan, CEO of IPEC, remarked, “Traditionally, India’s reliance on imports for power electronics has been high. At IPEC, we are changing that by designing and manufacturing power electronic products in India – for India and the world. This investment by Gruhas shall further propel our contributions to the ‘Make In India’ mission and enhance India’s EV ecosystem. IPEC has witnessed a 40% growth in revenue in FY25 and anticipates doubling its revenue in FY26.

This investment also enables IPEC to expand our avenues and capabilities to launch IPEC into global markets. We are excited to have Gruhas as part of the team and look forward to a great journey ahead.” Abhijeet Pai, Co-Founder of Gruhas, adds, “IPEC is fast emerging as a changemaker in India’s EV charging ecosystem. As the country accelerates toward an electric future, reliable and scalable charging infrastructure built on quality components, sub-assemblies, and smart chargers becomes mission-critical. Together, Zohra and IPEC have led the way in this space. By already serving four of India’s top OEMs, they’ve set benchmarks in manufacturing chargers, especially for the two-wheeler segment. Their deep ecosystem understanding and technical capabilities position them to expand beyond two-wheelers, into broader applications. At Gruhas, we are committed to backing companies that scale in tandem with OEMs — building the long-term future of the industry together.”

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As India accelerates its journey toward a digitally empowered, sustainable energy future, Advanced Metering Infrastructure (AMI) has emerged as a linchpin for modernizing the nation’s power grid. With rising energy demands, expanding renewable integration, and bold policy initiatives like the Revamped Distribution Sector Scheme (RDSS), the role of smart metering has never been more critical.

Ashish Sahay, Country Manager and Sales Director at Wirepas

In this exclusive interview with ELE Times, Ashish Sahay, Country Manager and Sales Director at Wirepas, shares insights into the transformative role of AMI and RF mesh technology in India’s smart grid evolution. With Wirepas leading the charge in next-gen, infrastructure-free connectivity, Sahay outlines how the company is enabling scalable, cost-effective solutions tailored to India’s unique power distribution landscape.

Excerpt:

ELE Times: India is undergoing a massive transformation in its power sector. How do you see Advanced Metering Infrastructure (AMI) playing a critical role in this journey toward a smarter, more resilient grid?

India’s energy landscape is evolving rapidly, and Advanced Metering Infrastructure (AMI) is emerging as a foundational pillar in building a smarter, more resilient power grid. With rising energy demand and a growing share of renewables, utilities need real-time visibility and control to ensure grid stability. Smart meters provide exactly that – enabling accurate consumption data, reducing non-commercial losses, and helping utilities become financially viable. The loss-making governmental electricity distribution companies, which already have implemented smart meters, have become profitable. This, in turn, allows them to reinvest in modernizing the grid. For consumers, AMI brings transparency, accurate billing, and better control over energy usage. It’s a critical enabler in India’s journey toward sustainable and equitable energy access.

ELE Times: Wirepas has introduced a unique 5G RF Mesh technology to the Indian market. Can you explain how this solution differs from traditional communication networks and how it improves scalability, cost-efficiency, and performance for smart metering?

Ashish Sahay: Wirepas’ RF mesh technology is fundamentally different from traditional communication networks used in smart metering. Instead of relying on costly and complex infrastructure like cellular base stations, Wirepas turns each smart meter into part of a decentralized, self-healing mesh network. This means meters connect directly with their neighbors, forming a resilient and scalable system with no single point of failure.

The real game-changer is cost and scalability. We have removed the need for network infrastructure. RF Mesh requires a point collecting data to be sent to the cloud. Wirepas has enabled in-meter gateway where,  one smart meter having a cellular connection can support up to 300 Wirepas RF mesh meters, dramatically reducing communication costs. With built-in wireless modules running Wirepas software, utilities can deploy at scale without compromising on performance – achieving proven 99.9% reliability even in challenging environments. It’s a flexible, high-performance solution designed from the ground up to meet the unique demands of India’s smart metering rollout.

Current regulatory setup in India, has not yet adapted to the European harmonized standard for 5G mesh. India has 1880-1900 MHz spectrum available, but not yet allocated for NR+ 5G standard, like in Europe. For this reason Wirepas has adapted 5G technology to be used on 865-868 MHz spectrum with less performance. Going further, the Indian government should enable NR+ 5G technology to be used on the 1880-1900 MHz band which is currently allocated to legacy DECT devices.

ELE Times: Despite government mandates, large-scale smart grid adoption still faces hurdles. From your experience, what are the key challenges utilities face when implementing AMI solutions, and how can they be addressed?

Ashish Sahay: Despite strong government support, large-scale smart grid adoption in India still faces several key hurdles. One major challenge is the industry’s limited experience with smart metering – especially early on, when the local ecosystem was still developing under the Make in India initiative. Many utilities and contractors are still climbing the learning curve, which has led to delays and uneven rollouts.

Reliable communication is another critical issue. AMI depends on consistent, high-quality connectivity, yet cellular coverage in India can be patchy – especially in rural or densely built-up areas. In some cases, only 70% of cellular smart meters maintain a connection, and even when coverage exists, the quality may fall short of AMI service requirements. Workarounds like BLE-based smartphone reconnections are not scalable solutions. While lower cost RF Mesh can deliver better coverage and SLA. Typically each smart meter using Wirepas Mesh communication technology is able to communicate via 50 or more meters, providing seamless network coverage and strong network signal.

Additionally, utilities must navigate the massive scale of deployment and the hidden costs tied to cellular technologies, such as SEP (Standard Essential Patent) fees and long-term subscription costs, which can significantly impact margins.

To overcome these challenges, solutions like Wirepas Mesh offer a compelling alternative. By turning each smart meter into a node in a self-healing, decentralized mesh network, Wirepas eliminates dependency on cellular coverage. It also reduces cost and risk by avoiding SEP-related liabilities. This approach not only ensures reliable connectivity across urban and rural environments but also supports fast, large-scale rollouts, making it a strong fit for India’s ambitious AMI goals.

ELE Times: India’s power sector is guided by ambitious digitalization goals under initiatives like RDSS. How aligned is Wirepas with these national programs, and what role does policy play in accelerating smart metering deployment?

Ashish Sahay: Wirepas is fully aligned with India’s digitalization goals under initiatives like the Revamped Distribution Sector Scheme (RDSS). These policy-driven programs have been instrumental in accelerating smart metering adoption by providing clear targets, financial support, and standardized requirements that create a level playing field for all stakeholders. Without such initiatives, large-scale rollouts would be fragmented and far slower. For Wirepas, this policy alignment means we can offer scalable, infrastructure-free connectivity that meets national standards, helping utilities deploy faster, more efficiently, and at lower cost. Policy has truly been the catalyst turning smart metering from a tech upgrade into a national imperative.

India government RDSS is becoming a worldwide role model of well executed national smart metering programs. Defining the standard at the right level enables the free competition and helps utilities to reach their roll-out targets in time.

ELE Times: You’ve worked across global markets—what lessons from international smart grid rollouts are particularly relevant to India’s unique power distribution landscape

Ashish Sahay: The lifetime of AMI systems is increasingly reaching 15 years or more. This places significant demands on the selected technologies to ensure they do not become obsolete during their operational lifespan.

India tends to focus on short-term goals, such as the upfront cost of hardware, while in reality, maintenance costs (OPEX) play a major role in the overall business case. For instance, parts of Southern Europe widely adopted PLC technology, which, despite the low cost of smart meters, led to high system maintenance costs.

In Europe, in-meter RF mesh gateways have proven to be by far the most economical solution for deploying RF connectivity, effectively covering both rural and densely populated urban areas. India has the opportunity to replicate this success.

ELE Times: With rapid innovation in IoT and connectivity, where do you see the future of connected utilities heading in India over the next five years—and how is Wirepas positioning itself to lead that future?

Ashish Sahay: Over the next five years, India’s connected utilities will evolve into highly data-driven, responsive systems, powered by real-time insights and seamless IoT connectivity. At Wirepas, we see this transformation as a huge opportunity, and we’re positioning ourselves to lead it. Today, our RF mesh technology is already used in around 25% of new smart meter deployments in India, and we’re committed to expanding that footprint by partnering with local players and licensing our technology to Indian manufacturers.

Our solution is built for scale, performance, and future demands, supporting granular data collection intervals and ultra-resilient communication, all with the lowest total cost of ownership. We’re not just keeping pace with innovation; we’re setting the standard for what AMI connectivity should look like in India’s next phase of digital utility transformation.

Wirepas based systems enable utilities to also benefit from load balancing use cases to utilize the same RF communication with the electricity loads connected to the grid.

The post Rewiring the Future of India’s Power Grid with Wirepas appeared first on ELE Times.

Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA has released its latest SiCPAK power modules with epoxy-resin potting technology, powered by proprietary trench-assisted planar SiC MOSFET technology, that have been rigorously designed and validated for the most demanding high-power environments, prioritizing reliability and high-temperature performance. Target markets include electric vehicle (EV) DC fast chargers (DCFC), industrial motor drives, interruptible power supplies (UPS), solar inverters and power optimizers, energy storage systems (ESS), industrial welding, and induction heating...

At booth 304 (hall 9) at the Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM 2025) Expo & Conference in Nuremberg, Germany (6–8 May), ROHM is showcasing reference projects with partners and presenting the evolution of its package designs and evaluation boards. Highlights include the following...

Віктору Миколайовичу Марчевському – 90! kpi чт, 04/17/2025 - 17:30

TI has expanded its automotive portfolio with a high-speed lidar laser driver, BAW-based clocks, and a mmWave radar sensor. These devices support the development of adaptable ADAS for safer, more automated driving.

The LMH13000 is claimed to be the first laser driver with an ultra-fast 800-ps rise time, enabling up to 30% longer distance measurements than discrete implementations and enhancing real-time decision making. It integrates LVDS, CMOS, and TTL control signals, eliminating the need for large capacitors or additional external circuitry. The device delivers up to 5 A of adjustable output current with just 2% variation across an ambient temperature range of -40°C to +125°C.

By leveraging bulk acoustic wave (BAW) technology, the CDC6C-Q1 oscillator and the LMK3H0102-Q1 and LMK3C0105-Q1 clock generators provide 100× greater reliability than quartz-based clocks, with a failure-in-time (FIT) rate as low as 0.3. These devices improve clocking precision in next-generation vehicle subsystems.

TI’s AWR2944P front and corner radar sensor builds on the AWR2944 platform, offering a higher signal-to-noise ratio, enhanced compute performance, expanded memory, and an integrated radar hardware accelerator. The accelerator enables the system’s MCU and DSP to perform machine learning tasks for edge AI applications.

Preproduction quantities of the LMH13000, CDC6C-Q1, LMK3H0102-Q1, LMK3C0105-Q1, and AWR2944P are available now on TI.com. Additional output current options and an automotive-qualified version of the LMH13000 are expected in 2026.

Texas Instruments 

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Designed for high-end MPU and FPGA systems, the Microchip MCP16701 PMIC integrates eight 1.5-A buck converters that can be paralleled and are duty cycle-capable. It also includes four 300-mA LDO regulators and a controller to drive external MOSFETs.

The MCP16701 enables dynamic VOUT adjustment across all converters, from 0.6 V to 1.6 V in 12.5-mV steps and from 1.6 V to 3.8 V in 25-mV steps. This flexibility allows precise power tuning for specific requirements in industrial computing, data servers, and edge AI, enhancing overall system efficiency.

Housed in a compact 8×8-mm VQFN package, the PMIC reduces board area by 48% and lowers component count to less than 60% compared to discrete designs. It supports Microchip’s PIC64-GX MPU and PolarFire FPGAs with a configurable feature set and operates from -40°C to +105°C. An I2C interface facilitates communication with other system components.

The MCP16701 costs $3 each in lots of 10,000 units.

MCP16701 product page

Microchip Technology 

The post PMIC fine-tunes power for MPUs and FPGAs appeared first on EDN.

The DS1050A Embedded Security Testbench from Keysight is a scalable PXI-based platform for advanced side-channel analysis (SCA) and fault injection (FI) testing. Designed for modern chips and embedded devices, it builds on the Device Vulnerability Analysis product line, offering up to 10× higher test effectiveness to help identify and mitigate hardware-level security threats.

This modular platform combines three core components—the M9046A PXIe chassis, M9038A PXIe embedded controller, and Inspector software. It integrates key tools, including oscilloscopes, interface equipment, amplifiers, and trigger generators, into a single chassis, reducing cabling and improving inter-module communication speed.

The 18-slot M9046A PXIe chassis delivers up to 1675 W of power and supports 85 W of cooling per slot, accommodating both Keysight and third-party test modules. Powered by an Intel Core i7-9850HE processor, the M9038A embedded controller provides the computing performance required for complex tests. Inspector software simulates diverse fault conditions, supports data acquisition, and enables advanced cryptanalysis across embedded devices, chips, and smart cards.

For more information on the DS1050A Embedded Security Testbench, or to request a price quote, click the product page link below.

DS1050A product page

Keysight Technologies 

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Omnivision’s OV50X CMOS image sensor delivers movie-grade video capture with ultra-high dynamic range (HDR) for premium smartphones. Based on the company’s TheiaCel and dual conversion gain (DCG) technologies, the color sensor achieves single-exposure HDR approaching 110 dB—reportedly the highest available in smartphones.

The OV50X is a 50-Mpixel sensor with a 1.6-µm pixel pitch and an 8192×6144 active array in a 1-in. optical format. It supports 4-cell binning, providing 12.5-Mpixel output at up to 180 frames/s, or 60 frames/s with three-exposure HDR. The sensor also enables 8K video with dual analog gain HDR and on-sensor crop-zoom capability.

TheiaCel employs lateral overflow integration capacitor (LOFIC) technology in combination with Omnivision’s proprietary DCG HDR to capture high-quality images and video in difficult lighting conditions. Quad phase detection (QPD) with 100% sensor coverage enables fast, precise autofocus across the entire frame—even in low light.

The OV50X image sensor is currently sampling, with mass production slated for Q3 2025.

OV50X product page

Omnivision 

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Medium-voltage CoolGaN G5 transistors from Infineon include a built-in Schottky diode to minimize dead-time losses and enhance system efficiency. The integrated diode also streamlines power stage design and helps reduce BOM cost.

In hard-switching designs, GaN devices can suffer from higher power losses due to body diode behavior, especially with long controller dead times. CoolGaN G5 transistors address this by integrating a Schottky diode, improving efficiency across applications such as telecom IBCs, DC/DC converters, USB-C chargers, power supplies, and motor drives.

GaN transistor reverse conduction voltage (VRC) depends on the threshold voltage (VTH) and OFF-state gate bias (VGS), as there is no body diode. Since VTH is typically higher than the turn-on voltage of silicon diodes, reverse conduction losses increase in third-quadrant operation. The CoolGaN transistor reduces these losses, improves compatibility with high-side gate drivers, and allows broader controller compatibility due to relaxed dead-time.

The first device in the CoolGaN G5 series with an integrated Schottky diode is a 100-V, 1.5-mΩ transistor in a 3×5-mm PQFN package. Engineering samples and a target datasheet are available upon request.

CoolGaN G5 product page

Infineon Technologies 

The post GaN transistors integrate Schottky diode appeared first on EDN.

This phenomenon has nothing to do with “Gunsmoke” or with “Have Gun, Will Travel”. (Do you remember those old TV shows?) The phrase “shoot- through” describes unwanted and possibly destructive pulses of current flowing through power semiconductors in certain power supply designs.

In half-bridge and full-bridge power inverters, we have one pair (half-bridge) or two pairs (full-bridge) of power switching devices connected in series from a rail voltage to a rail voltage return. Those devices could be power MOSFETs, IGBTs, or whatever but the requirement in each case is the same. That requirement is that the two devices in each pair turn on and off in alternate fashion. If the upper one is on, the lower one is off. If the upper one is off, the lower one is on.

The circuit board seen in Figure 1 was one such design based on a full-bridge power inverter, and it had a shoot- through issue.

Figure 1 A full-bridge circuit board with a shoot-through issue and the test arrangement used to assess it.

A super simplified SPICE simulation shows conceptually what was going amiss with that circuit board, Figure 2.

Figure 2 A SPICE simulation that conceptually walks through the shoot-through problem occurring on the circuit in Figure 1.

S1 represents the board’s Q1 and Q2 upper switches and S2 represents the board’s Q4 and Q3 lower switches. At each switching transition, there was a brief moment when one switch had not quite turned off by the time its corresponding switch had turned on. With both switching devices on at the same time, however brief that “same” time was, there would be a pulse of current flowing from the board’s rail through the two switches an into the board’s rail return. That current pulse would be of essentially unlimited magnitude and the two switching devices could and would suffer damage.

Electromagnetic interference issues arose as well, but that’s a separate discussion.

Old hands will undoubtedly recognize the following, but let’s take a look at the remedy shown in Figure 3.

Figure 3 Shoot-through problem solved by introducing two diodes to speed up the switchs’ turn-off times.

The capacitors C1 and C2 represent the input gate capacitances of the power MOSFETs that served as the switches. The shoot-through issue would arise when one of those capacitances was not fully discharged before the other capacitance got raised to its own full charge. Adding two diodes sped up the capacitance discharge times so that essentially full discharge was achieved for each FET before the other one could turn on.

Having thus prevented simultaneous turn-ons, the troublesome current pulses on that circuit board were eliminated.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Shoot-thru suppression
• Tip of the Week: How to best implement a synchronous buck converter
• MOSFET Qrr: Ignore at your peril in the pursuit of power efficiency
• EMI and circuit components: Where the rubber meets the road

The post Shoot-through appeared first on EDN.

Professor Can Bayram and his colleagues at University of Illinois at Urbana-Champaign (UIUC) in the USA have reported diamond photoconductive semiconductor switches (PCSS) with record-breaking voltage/current handling and slew rates, efficiency and reliability simultaneously (Z. Han et al, ‘Record Performance in Intrinsic, Impurity-Free Lateral Diamond Photoconductive Semiconductor Switches’ Appl. Phys. Lett. 126, 152105 (2025)...

Проректорка з навчальної роботи Тетяна Желяскова про розбудову в КПІ якісної високотехнологічної освіти та підготовку фахівців, яких потребує сучасний ринок праці Інформація КП чт, 04/17/2025 - 13:27

Compound Semiconductor Applications (CSA) Catapult says that Dr Jayakrishnan (Jay) Chandrappan, its head of technology – advanced packaging, has been appointed visiting industrial professor at the University of Bristol and visiting professor at the University of Strathclyde...

Meta trained one of its AI models, called Llama 3, in 2024 and published the results in a widely covered paper. During a 54-day period of pre-training, Llama 3 experienced 466 job interruptions, 419 of which were unexpected. Upon further investigation, Meta learned 78% of those hiccups were caused by hardware issues such as GPU and host component failures.

Hardware issues like these don’t just cause job interruptions. They can also lead to silent data corruption (SDC), causing unwanted data loss or inaccuracies that often go undetected for extended periods.

While Meta’s pre-training interruptions were unexpected, they shouldn’t be entirely surprising. AI models like Llama 3 have massive processing demands that require colossal computing clusters. For training alone, AI workloads can require hundreds of thousands of nodes and associated GPUs working in unison for weeks or months at a time.

The intensity and scale of AI processing and switching create a tremendous amount of heat, voltage fluctuations and noise, all of which place unprecedented stress on computational hardware. The GPUs and underlying silicon can degrade more rapidly than they would under normal (or what used to be normal) conditions. Performance and reliability wane accordingly.

This is especially true for sub-5 nm process technologies, where silicon degradation and faulty behavior are observed upon manufacturing and in the field.

But what can be done about it? How can unanticipated interruptions and SDC be mitigated? And how can chip design teams ensure optimal performance and reliability as the industry pushes forward with newer, bigger AI workloads that demand even more processing capacity and scale?

Ensuring silicon reliability, availability and serviceability (RAS)

Certain AI players like Meta have established monitoring and diagnostics capabilities to improve the availability and reliability of their computing environments. But with processing demands, hardware failures and SDC issues on the rise, there is a distinct need for test and telemetry capabilities at deeper levels—all the way down to the silicon and multi-die packages within each XPU/GPU as well as the interconnects that bring them together.

The key is silicon lifecycle management (SLM) solutions that help ensure end-to-end RAS, from design and manufacturing to bring-up and in-field operation.

With better visibility, monitoring, and diagnostics at the silicon level, design teams can:

• Gain telemetry-based insights into why chips are failing or why SDC is occurring.
• Identify voltage or timing degradation, overheating, and mechanical failures in silicon components, multi-die packages, and high-speed interconnects.
• Conduct more precise thermal and power characterization for AI workloads.
• Detect, characterize, and resolve radiation, voltage noise, and mechanism failures that can lead to undetected bit flips and SDC.
• Improve silicon yield, quality, and in-field RAS.
• Implement reliability-focused techniques—like triple modular redundancy and dual core lock step—during the register-transfer level (RTL) design phase to mitigate SDC.
• Establish an accurate pre-silicon aging simulation methodology to detect sensitive or vulnerable circuits and replace them with aging-resilient circuits.
• Improve outlier detection on reliability models, which helps minimize in-field SDC.

Silicon lifecycle management (SLM) solutions help ensure end-to-end reliability, availability, and serviceability. Source: Synopsys

An SML design example

SLM IP and analytics solutions help improve silicon health and provide operational metrics at each phase of the system lifecycle. This includes environmental monitoring for understanding and optimizing silicon performance based on the operating environment of the device; structural monitoring to identify performance variations from design to in-field operation; and functional monitoring to track the health and anomalies of critical device functions.

Below are the key features and capabilities that SLM IP provides:

1. Process, voltage and temperature monitors

• Help ensure optimal operation while maximizing performance, power, and reliability.
• Highly accurate and distributed monitoring throughout the die, enabling thermal management via frequency throttling.

2. Path margin monitors

• Measure timing margin of 1000+ synthetic and functional paths (in-test and in-field).
• Enable silicon performance optimization based on actual margins.
• Automated path selection, IP insertion, and scan generation.

3. Clock and delay monitors

• Measure the delay between the edges of one or more signals.
• Check the quality of the clock duty cycle.
• Measure memory read access time tracking with built-in self-test (BIST).
• Characterize digital delay lines.

4. UCIe monitor, test and repair

• Monitor signal integrity of die-to-die UCIe lane(s).
• Generate algorithmic BIST patterns to detect interconnect fault types, including lane-to-lane crosstalk.
• Perform cumulative lane repair with redundancy allocation (upon manufacturing and in-field).

5. High-speed access and test

• Enable testing over functional interfaces (PCIe, USB and SPI).
• For in-field operation as well as wafer sort, final test, and system-level test.
• Can be used in conjunction with automated test equipment.
• Help conduct in-field remote diagnoses and lower-cost test via reduced pin count.

6. HBM external test and repair

• Comprehensive, silicon-proven DRAM stack test, repair and diagnostics engine.
• Support third-party HBM DRAM stack providers.
• Provide high-performance die to die interconnect test and repair support.
• Operate in conjunction with HBM PHY and support a range of HBM protocols and configurations.

7. SLM hierarchical subsystem

• Automated hierarchical SLM and test manageability solution for system-on-chips (SoCs).
• Automated integration and access of all IP/cores with in-system scheduling.
• Pre-validated, ready ATE patterns with pattern porting.

Silicon test and telemetry in the age of AI

With the scale and processing demands of AI devices and workloads on the rise, system reliability, silicon health and SDC issues are becoming more widespread. While there is no single solution or antidote for avoiding these issues, deeper and more comprehensive test, repair, and telemetry—at the silicon level—can help mitigate them. The ability to detect or predict in-field chip degradation is particularly valuable, enabling corrective action before sudden or catastrophic system failures occur.

Delivering end-to-end visibility through RAS, silicon test, repair, and telemetry will be increasingly important as we move toward the age of AI.

Shankar Krishnamoorthy is chief product development officer at Synopsys.

Krishna Adusumalli is R&D engineer at Synopsys.

Jyotika Athavale is architecture engineering director at Synopsys.

Yervant Zorian is chief architect at Synopsys.

Related Content

• Uncovering Silent Data Errors with AI
• 11 steps to successful hardware troubleshooting
• Self-testing in embedded systems: Hardware failure
• Understanding and combating silent data corruption
• Test solutions to confront silent data corruption in ICs

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